Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 23
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 24
1 14:46:38.461870 lava-dispatcher, installed at version: 2024.03
2 14:46:38.462069 start: 0 validate
3 14:46:38.462204 Start time: 2024-06-04 14:46:38.462197+00:00 (UTC)
4 14:46:38.462319 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:46:38.462450 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 14:46:38.725304 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:46:38.725477 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:46:38.984039 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:46:38.984676 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:46:39.246253 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:46:39.246877 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 14:46:39.499688 validate duration: 1.04
14 14:46:39.499969 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:46:39.500080 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:46:39.500180 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:46:39.500315 Not decompressing ramdisk as can be used compressed.
18 14:46:39.500398 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 14:46:39.500461 saving as /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/ramdisk/rootfs.cpio.gz
20 14:46:39.500523 total size: 28105535 (26 MB)
21 14:46:39.501597 progress 0 % (0 MB)
22 14:46:39.508868 progress 5 % (1 MB)
23 14:46:39.516034 progress 10 % (2 MB)
24 14:46:39.523167 progress 15 % (4 MB)
25 14:46:39.530389 progress 20 % (5 MB)
26 14:46:39.537627 progress 25 % (6 MB)
27 14:46:39.544783 progress 30 % (8 MB)
28 14:46:39.552008 progress 35 % (9 MB)
29 14:46:39.559312 progress 40 % (10 MB)
30 14:46:39.566310 progress 45 % (12 MB)
31 14:46:39.573481 progress 50 % (13 MB)
32 14:46:39.580608 progress 55 % (14 MB)
33 14:46:39.587722 progress 60 % (16 MB)
34 14:46:39.594836 progress 65 % (17 MB)
35 14:46:39.601959 progress 70 % (18 MB)
36 14:46:39.609143 progress 75 % (20 MB)
37 14:46:39.616353 progress 80 % (21 MB)
38 14:46:39.623558 progress 85 % (22 MB)
39 14:46:39.630457 progress 90 % (24 MB)
40 14:46:39.637634 progress 95 % (25 MB)
41 14:46:39.644606 progress 100 % (26 MB)
42 14:46:39.644819 26 MB downloaded in 0.14 s (185.76 MB/s)
43 14:46:39.644984 end: 1.1.1 http-download (duration 00:00:00) [common]
45 14:46:39.645249 end: 1.1 download-retry (duration 00:00:00) [common]
46 14:46:39.645334 start: 1.2 download-retry (timeout 00:10:00) [common]
47 14:46:39.645417 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 14:46:39.645550 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 14:46:39.645622 saving as /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/kernel/Image
50 14:46:39.645682 total size: 54682112 (52 MB)
51 14:46:39.645741 No compression specified
52 14:46:39.646843 progress 0 % (0 MB)
53 14:46:39.660560 progress 5 % (2 MB)
54 14:46:39.674474 progress 10 % (5 MB)
55 14:46:39.688284 progress 15 % (7 MB)
56 14:46:39.701908 progress 20 % (10 MB)
57 14:46:39.715722 progress 25 % (13 MB)
58 14:46:39.729544 progress 30 % (15 MB)
59 14:46:39.743438 progress 35 % (18 MB)
60 14:46:39.757212 progress 40 % (20 MB)
61 14:46:39.770973 progress 45 % (23 MB)
62 14:46:39.784944 progress 50 % (26 MB)
63 14:46:39.798597 progress 55 % (28 MB)
64 14:46:39.812451 progress 60 % (31 MB)
65 14:46:39.826128 progress 65 % (33 MB)
66 14:46:39.840083 progress 70 % (36 MB)
67 14:46:39.853884 progress 75 % (39 MB)
68 14:46:39.867696 progress 80 % (41 MB)
69 14:46:39.881373 progress 85 % (44 MB)
70 14:46:39.894967 progress 90 % (46 MB)
71 14:46:39.908728 progress 95 % (49 MB)
72 14:46:39.922194 progress 100 % (52 MB)
73 14:46:39.922427 52 MB downloaded in 0.28 s (188.44 MB/s)
74 14:46:39.922576 end: 1.2.1 http-download (duration 00:00:00) [common]
76 14:46:39.922806 end: 1.2 download-retry (duration 00:00:00) [common]
77 14:46:39.922890 start: 1.3 download-retry (timeout 00:10:00) [common]
78 14:46:39.922973 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 14:46:39.923107 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 14:46:39.923179 saving as /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/dtb/mt8192-asurada-spherion-r0.dtb
81 14:46:39.923239 total size: 47258 (0 MB)
82 14:46:39.923299 No compression specified
83 14:46:39.924411 progress 69 % (0 MB)
84 14:46:39.924681 progress 100 % (0 MB)
85 14:46:39.924856 0 MB downloaded in 0.00 s (27.93 MB/s)
86 14:46:39.924984 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:46:39.925215 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:46:39.925298 start: 1.4 download-retry (timeout 00:10:00) [common]
90 14:46:39.925378 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 14:46:39.925487 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 14:46:39.925553 saving as /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/modules/modules.tar
93 14:46:39.925612 total size: 8608920 (8 MB)
94 14:46:39.925672 Using unxz to decompress xz
95 14:46:39.929798 progress 0 % (0 MB)
96 14:46:39.949563 progress 5 % (0 MB)
97 14:46:39.977742 progress 10 % (0 MB)
98 14:46:40.008288 progress 15 % (1 MB)
99 14:46:40.033151 progress 20 % (1 MB)
100 14:46:40.057949 progress 25 % (2 MB)
101 14:46:40.082770 progress 30 % (2 MB)
102 14:46:40.108124 progress 35 % (2 MB)
103 14:46:40.135906 progress 40 % (3 MB)
104 14:46:40.159851 progress 45 % (3 MB)
105 14:46:40.185349 progress 50 % (4 MB)
106 14:46:40.211451 progress 55 % (4 MB)
107 14:46:40.236872 progress 60 % (4 MB)
108 14:46:40.262580 progress 65 % (5 MB)
109 14:46:40.288108 progress 70 % (5 MB)
110 14:46:40.314426 progress 75 % (6 MB)
111 14:46:40.341344 progress 80 % (6 MB)
112 14:46:40.366878 progress 85 % (7 MB)
113 14:46:40.392962 progress 90 % (7 MB)
114 14:46:40.418729 progress 95 % (7 MB)
115 14:46:40.444562 progress 100 % (8 MB)
116 14:46:40.450252 8 MB downloaded in 0.52 s (15.65 MB/s)
117 14:46:40.450493 end: 1.4.1 http-download (duration 00:00:01) [common]
119 14:46:40.450754 end: 1.4 download-retry (duration 00:00:01) [common]
120 14:46:40.450846 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 14:46:40.450939 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 14:46:40.451019 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:46:40.451105 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 14:46:40.451331 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v
125 14:46:40.451461 makedir: /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin
126 14:46:40.451566 makedir: /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/tests
127 14:46:40.451663 makedir: /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/results
128 14:46:40.451779 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-add-keys
129 14:46:40.451926 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-add-sources
130 14:46:40.452054 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-background-process-start
131 14:46:40.452182 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-background-process-stop
132 14:46:40.452306 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-common-functions
133 14:46:40.452428 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-echo-ipv4
134 14:46:40.452553 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-install-packages
135 14:46:40.452675 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-installed-packages
136 14:46:40.452795 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-os-build
137 14:46:40.452919 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-probe-channel
138 14:46:40.453076 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-probe-ip
139 14:46:40.453197 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-target-ip
140 14:46:40.453316 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-target-mac
141 14:46:40.453436 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-target-storage
142 14:46:40.453562 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-test-case
143 14:46:40.453684 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-test-event
144 14:46:40.453804 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-test-feedback
145 14:46:40.453923 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-test-raise
146 14:46:40.454041 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-test-reference
147 14:46:40.454165 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-test-runner
148 14:46:40.454284 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-test-set
149 14:46:40.454407 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-test-shell
150 14:46:40.454532 Updating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-install-packages (oe)
151 14:46:40.454681 Updating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/bin/lava-installed-packages (oe)
152 14:46:40.454799 Creating /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/environment
153 14:46:40.454897 LAVA metadata
154 14:46:40.454968 - LAVA_JOB_ID=14167053
155 14:46:40.455032 - LAVA_DISPATCHER_IP=192.168.201.1
156 14:46:40.455130 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 14:46:40.455199 skipped lava-vland-overlay
158 14:46:40.455272 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 14:46:40.455354 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 14:46:40.455427 skipped lava-multinode-overlay
161 14:46:40.455500 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 14:46:40.455582 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 14:46:40.455655 Loading test definitions
164 14:46:40.455744 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 14:46:40.455816 Using /lava-14167053 at stage 0
166 14:46:40.456125 uuid=14167053_1.5.2.3.1 testdef=None
167 14:46:40.456213 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 14:46:40.456298 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 14:46:40.456802 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 14:46:40.457060 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 14:46:40.457660 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 14:46:40.457887 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 14:46:40.458467 runner path: /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14167053_1.5.2.3.1
176 14:46:40.458620 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 14:46:40.458823 Creating lava-test-runner.conf files
179 14:46:40.458886 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14167053/lava-overlay-k5hzgx0v/lava-14167053/0 for stage 0
180 14:46:40.458973 - 0_v4l2-compliance-mtk-vcodec-enc
181 14:46:40.459067 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 14:46:40.459151 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 14:46:40.466338 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 14:46:40.466445 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 14:46:40.466529 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 14:46:40.466612 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 14:46:40.466695 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 14:46:41.357542 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 14:46:41.357917 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 14:46:41.358030 extracting modules file /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167053/extract-overlay-ramdisk-dhdzqj6c/ramdisk
191 14:46:41.575347 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 14:46:41.575520 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 14:46:41.575614 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167053/compress-overlay-b3m7sh7w/overlay-1.5.2.4.tar.gz to ramdisk
194 14:46:41.575684 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167053/compress-overlay-b3m7sh7w/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14167053/extract-overlay-ramdisk-dhdzqj6c/ramdisk
195 14:46:41.582214 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 14:46:41.582331 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 14:46:41.582420 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 14:46:41.582512 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 14:46:41.582592 Building ramdisk /var/lib/lava/dispatcher/tmp/14167053/extract-overlay-ramdisk-dhdzqj6c/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14167053/extract-overlay-ramdisk-dhdzqj6c/ramdisk
200 14:46:42.305742 >> 275882 blocks
201 14:46:46.439913 rename /var/lib/lava/dispatcher/tmp/14167053/extract-overlay-ramdisk-dhdzqj6c/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/ramdisk/ramdisk.cpio.gz
202 14:46:46.440360 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 14:46:46.440489 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 14:46:46.440584 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 14:46:46.440695 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/kernel/Image']
206 14:46:59.499380 Returned 0 in 13 seconds
207 14:46:59.599994 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/kernel/image.itb
208 14:47:00.232862 output: FIT description: Kernel Image image with one or more FDT blobs
209 14:47:00.233261 output: Created: Tue Jun 4 15:47:00 2024
210 14:47:00.233329 output: Image 0 (kernel-1)
211 14:47:00.233393 output: Description:
212 14:47:00.233453 output: Created: Tue Jun 4 15:47:00 2024
213 14:47:00.233511 output: Type: Kernel Image
214 14:47:00.233572 output: Compression: lzma compressed
215 14:47:00.233631 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
216 14:47:00.233693 output: Architecture: AArch64
217 14:47:00.233751 output: OS: Linux
218 14:47:00.233811 output: Load Address: 0x00000000
219 14:47:00.233868 output: Entry Point: 0x00000000
220 14:47:00.233923 output: Hash algo: crc32
221 14:47:00.233981 output: Hash value: 88dcd836
222 14:47:00.234035 output: Image 1 (fdt-1)
223 14:47:00.234089 output: Description: mt8192-asurada-spherion-r0
224 14:47:00.234141 output: Created: Tue Jun 4 15:47:00 2024
225 14:47:00.234196 output: Type: Flat Device Tree
226 14:47:00.234249 output: Compression: uncompressed
227 14:47:00.234301 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 14:47:00.234353 output: Architecture: AArch64
229 14:47:00.234404 output: Hash algo: crc32
230 14:47:00.234455 output: Hash value: 0f8e4d2e
231 14:47:00.234507 output: Image 2 (ramdisk-1)
232 14:47:00.234558 output: Description: unavailable
233 14:47:00.234609 output: Created: Tue Jun 4 15:47:00 2024
234 14:47:00.234661 output: Type: RAMDisk Image
235 14:47:00.234713 output: Compression: Unknown Compression
236 14:47:00.234765 output: Data Size: 41210554 Bytes = 40244.68 KiB = 39.30 MiB
237 14:47:00.234817 output: Architecture: AArch64
238 14:47:00.234869 output: OS: Linux
239 14:47:00.234921 output: Load Address: unavailable
240 14:47:00.234973 output: Entry Point: unavailable
241 14:47:00.235024 output: Hash algo: crc32
242 14:47:00.235076 output: Hash value: cc4bd698
243 14:47:00.235127 output: Default Configuration: 'conf-1'
244 14:47:00.235178 output: Configuration 0 (conf-1)
245 14:47:00.235230 output: Description: mt8192-asurada-spherion-r0
246 14:47:00.235282 output: Kernel: kernel-1
247 14:47:00.235334 output: Init Ramdisk: ramdisk-1
248 14:47:00.235385 output: FDT: fdt-1
249 14:47:00.235436 output: Loadables: kernel-1
250 14:47:00.235488 output:
251 14:47:00.235692 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 14:47:00.235787 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 14:47:00.235894 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 14:47:00.235984 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 14:47:00.236060 No LXC device requested
256 14:47:00.236138 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 14:47:00.236220 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 14:47:00.236296 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 14:47:00.236365 Checking files for TFTP limit of 4294967296 bytes.
260 14:47:00.236854 end: 1 tftp-deploy (duration 00:00:21) [common]
261 14:47:00.236959 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 14:47:00.237090 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 14:47:00.237215 substitutions:
264 14:47:00.237281 - {DTB}: 14167053/tftp-deploy-4rwsbx_p/dtb/mt8192-asurada-spherion-r0.dtb
265 14:47:00.237345 - {INITRD}: 14167053/tftp-deploy-4rwsbx_p/ramdisk/ramdisk.cpio.gz
266 14:47:00.237402 - {KERNEL}: 14167053/tftp-deploy-4rwsbx_p/kernel/Image
267 14:47:00.237458 - {LAVA_MAC}: None
268 14:47:00.237514 - {PRESEED_CONFIG}: None
269 14:47:00.237568 - {PRESEED_LOCAL}: None
270 14:47:00.237622 - {RAMDISK}: 14167053/tftp-deploy-4rwsbx_p/ramdisk/ramdisk.cpio.gz
271 14:47:00.237675 - {ROOT_PART}: None
272 14:47:00.237728 - {ROOT}: None
273 14:47:00.237781 - {SERVER_IP}: 192.168.201.1
274 14:47:00.237834 - {TEE}: None
275 14:47:00.237887 Parsed boot commands:
276 14:47:00.237939 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 14:47:00.238113 Parsed boot commands: tftpboot 192.168.201.1 14167053/tftp-deploy-4rwsbx_p/kernel/image.itb 14167053/tftp-deploy-4rwsbx_p/kernel/cmdline
278 14:47:00.238200 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 14:47:00.238284 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 14:47:00.238370 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 14:47:00.238453 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 14:47:00.238526 Not connected, no need to disconnect.
283 14:47:00.238598 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 14:47:00.238677 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 14:47:00.238746 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 14:47:00.242476 Setting prompt string to ['lava-test: # ']
287 14:47:00.242832 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 14:47:00.242934 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 14:47:00.243031 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 14:47:00.243121 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 14:47:00.243333 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 14:47:05.379792 >> Command sent successfully.
293 14:47:05.382090 Returned 0 in 5 seconds
294 14:47:05.482422 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 14:47:05.482726 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 14:47:05.482820 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 14:47:05.482905 Setting prompt string to 'Starting depthcharge on Spherion...'
299 14:47:05.482970 Changing prompt to 'Starting depthcharge on Spherion...'
300 14:47:05.483036 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 14:47:05.483411 [Enter `^Ec?' for help]
302 14:47:05.658139
303 14:47:05.658272
304 14:47:05.658344 F0: 102B 0000
305 14:47:05.658409
306 14:47:05.658471 F3: 1001 0000 [0200]
307 14:47:05.661494
308 14:47:05.661579 F3: 1001 0000
309 14:47:05.661646
310 14:47:05.661706 F7: 102D 0000
311 14:47:05.661763
312 14:47:05.665827 F1: 0000 0000
313 14:47:05.665923
314 14:47:05.665990 V0: 0000 0000 [0001]
315 14:47:05.666050
316 14:47:05.668302 00: 0007 8000
317 14:47:05.668387
318 14:47:05.668451 01: 0000 0000
319 14:47:05.668512
320 14:47:05.671380 BP: 0C00 0209 [0000]
321 14:47:05.671460
322 14:47:05.671524 G0: 1182 0000
323 14:47:05.671583
324 14:47:05.675414 EC: 0000 0021 [4000]
325 14:47:05.675494
326 14:47:05.675558 S7: 0000 0000 [0000]
327 14:47:05.675617
328 14:47:05.679317 CC: 0000 0000 [0001]
329 14:47:05.679398
330 14:47:05.679462 T0: 0000 0040 [010F]
331 14:47:05.679522
332 14:47:05.679579 Jump to BL
333 14:47:05.679635
334 14:47:05.705807
335 14:47:05.705891
336 14:47:05.713484 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 14:47:05.717358 ARM64: Exception handlers installed.
338 14:47:05.721403 ARM64: Testing exception
339 14:47:05.721486 ARM64: Done test exception
340 14:47:05.730488 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 14:47:05.741411 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 14:47:05.748090 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 14:47:05.757727 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 14:47:05.764836 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 14:47:05.771496 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 14:47:05.782102 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 14:47:05.788798 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 14:47:05.808389 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 14:47:05.812208 WDT: Last reset was cold boot
350 14:47:05.814897 SPI1(PAD0) initialized at 2873684 Hz
351 14:47:05.818747 SPI5(PAD0) initialized at 992727 Hz
352 14:47:05.821688 VBOOT: Loading verstage.
353 14:47:05.828253 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 14:47:05.831398 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 14:47:05.835060 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 14:47:05.838186 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 14:47:05.845752 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 14:47:05.852592 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 14:47:05.862916 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 14:47:05.862997
361 14:47:05.863061
362 14:47:05.873137 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 14:47:05.876423 ARM64: Exception handlers installed.
364 14:47:05.879602 ARM64: Testing exception
365 14:47:05.879684 ARM64: Done test exception
366 14:47:05.886405 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 14:47:05.889645 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 14:47:05.904421 Probing TPM: . done!
369 14:47:05.904503 TPM ready after 0 ms
370 14:47:05.910933 Connected to device vid:did:rid of 1ae0:0028:00
371 14:47:05.918505 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 14:47:05.921797 Initialized TPM device CR50 revision 0
373 14:47:05.987173 tlcl_send_startup: Startup return code is 0
374 14:47:05.987268 TPM: setup succeeded
375 14:47:05.999124 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 14:47:06.007378 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 14:47:06.019021 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 14:47:06.029047 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 14:47:06.032074 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 14:47:06.040972 in-header: 03 07 00 00 08 00 00 00
381 14:47:06.044138 in-data: aa e4 47 04 13 02 00 00
382 14:47:06.048034 Chrome EC: UHEPI supported
383 14:47:06.055380 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 14:47:06.058744 in-header: 03 ad 00 00 08 00 00 00
385 14:47:06.063289 in-data: 00 20 20 08 00 00 00 00
386 14:47:06.063363 Phase 1
387 14:47:06.066513 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 14:47:06.070361 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 14:47:06.078211 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 14:47:06.081367 Recovery requested (1009000e)
391 14:47:06.089436 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 14:47:06.094543 tlcl_extend: response is 0
393 14:47:06.103712 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 14:47:06.109702 tlcl_extend: response is 0
395 14:47:06.117066 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 14:47:06.136569 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 14:47:06.143184 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 14:47:06.143265
399 14:47:06.143329
400 14:47:06.154017 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 14:47:06.157455 ARM64: Exception handlers installed.
402 14:47:06.157536 ARM64: Testing exception
403 14:47:06.161249 ARM64: Done test exception
404 14:47:06.182477 pmic_efuse_setting: Set efuses in 11 msecs
405 14:47:06.185269 pmwrap_interface_init: Select PMIF_VLD_RDY
406 14:47:06.192026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 14:47:06.195505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 14:47:06.202095 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 14:47:06.205732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 14:47:06.209265 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 14:47:06.213892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 14:47:06.221253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 14:47:06.224831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 14:47:06.228536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 14:47:06.236684 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 14:47:06.239575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 14:47:06.243796 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 14:47:06.247114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 14:47:06.255548 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 14:47:06.257995 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 14:47:06.265734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 14:47:06.272945 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 14:47:06.277069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 14:47:06.284403 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 14:47:06.288025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 14:47:06.295168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 14:47:06.298839 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 14:47:06.306244 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 14:47:06.310535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 14:47:06.313580 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 14:47:06.321217 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 14:47:06.324873 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 14:47:06.332288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 14:47:06.336288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 14:47:06.339699 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 14:47:06.347640 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 14:47:06.351082 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 14:47:06.355648 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 14:47:06.361821 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 14:47:06.365472 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 14:47:06.369558 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 14:47:06.377230 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 14:47:06.380548 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 14:47:06.384313 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 14:47:06.388994 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 14:47:06.395186 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 14:47:06.398870 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 14:47:06.402557 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 14:47:06.406109 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 14:47:06.410249 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 14:47:06.418217 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 14:47:06.421670 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 14:47:06.425631 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 14:47:06.428939 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 14:47:06.432427 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 14:47:06.435984 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 14:47:06.443664 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 14:47:06.455197 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 14:47:06.458731 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 14:47:06.465757 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 14:47:06.473315 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 14:47:06.480524 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 14:47:06.484472 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 14:47:06.487592 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 14:47:06.495724 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
466 14:47:06.499096 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 14:47:06.507507 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 14:47:06.510392 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 14:47:06.519204 [RTC]rtc_get_frequency_meter,154: input=15, output=790
470 14:47:06.528863 [RTC]rtc_get_frequency_meter,154: input=23, output=978
471 14:47:06.538375 [RTC]rtc_get_frequency_meter,154: input=19, output=884
472 14:47:06.547686 [RTC]rtc_get_frequency_meter,154: input=17, output=835
473 14:47:06.557153 [RTC]rtc_get_frequency_meter,154: input=16, output=813
474 14:47:06.566970 [RTC]rtc_get_frequency_meter,154: input=15, output=790
475 14:47:06.576858 [RTC]rtc_get_frequency_meter,154: input=16, output=813
476 14:47:06.581428 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 14:47:06.584261 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 14:47:06.587901 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 14:47:06.595229 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 14:47:06.599940 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 14:47:06.602960 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 14:47:06.606916 ADC[4]: Raw value=901697 ID=7
483 14:47:06.606999 ADC[3]: Raw value=213336 ID=1
484 14:47:06.611009 RAM Code: 0x71
485 14:47:06.614444 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 14:47:06.618829 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 14:47:06.625451 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 14:47:06.633463 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 14:47:06.637669 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 14:47:06.641278 in-header: 03 07 00 00 08 00 00 00
491 14:47:06.646289 in-data: aa e4 47 04 13 02 00 00
492 14:47:06.646371 Chrome EC: UHEPI supported
493 14:47:06.652853 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 14:47:06.655692 in-header: 03 ed 00 00 08 00 00 00
495 14:47:06.659612 in-data: 80 20 60 08 00 00 00 00
496 14:47:06.663423 MRC: failed to locate region type 0.
497 14:47:06.671241 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 14:47:06.671323 DRAM-K: Running full calibration
499 14:47:06.678013 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 14:47:06.682009 header.status = 0x0
501 14:47:06.685420 header.version = 0x6 (expected: 0x6)
502 14:47:06.685502 header.size = 0xd00 (expected: 0xd00)
503 14:47:06.689624 header.flags = 0x0
504 14:47:06.696119 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 14:47:06.713664 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
506 14:47:06.720766 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 14:47:06.720874 dram_init: ddr_geometry: 2
508 14:47:06.724277 [EMI] MDL number = 2
509 14:47:06.728028 [EMI] Get MDL freq = 0
510 14:47:06.728109 dram_init: ddr_type: 0
511 14:47:06.732649 is_discrete_lpddr4: 1
512 14:47:06.736047 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 14:47:06.736128
514 14:47:06.736192
515 14:47:06.736251 [Bian_co] ETT version 0.0.0.1
516 14:47:06.742971 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 14:47:06.743052
518 14:47:06.747252 dramc_set_vcore_voltage set vcore to 650000
519 14:47:06.747333 Read voltage for 800, 4
520 14:47:06.750404 Vio18 = 0
521 14:47:06.750484 Vcore = 650000
522 14:47:06.750548 Vdram = 0
523 14:47:06.750607 Vddq = 0
524 14:47:06.753836 Vmddr = 0
525 14:47:06.753917 dram_init: config_dvfs: 1
526 14:47:06.761973 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 14:47:06.764995 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 14:47:06.768522 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 14:47:06.771822 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 14:47:06.778432 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 14:47:06.782465 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 14:47:06.782546 MEM_TYPE=3, freq_sel=18
533 14:47:06.785493 sv_algorithm_assistance_LP4_1600
534 14:47:06.788572 ============ PULL DRAM RESETB DOWN ============
535 14:47:06.795217 ========== PULL DRAM RESETB DOWN end =========
536 14:47:06.798982 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 14:47:06.802287 ===================================
538 14:47:06.805137 LPDDR4 DRAM CONFIGURATION
539 14:47:06.808739 ===================================
540 14:47:06.808821 EX_ROW_EN[0] = 0x0
541 14:47:06.812574 EX_ROW_EN[1] = 0x0
542 14:47:06.812654 LP4Y_EN = 0x0
543 14:47:06.815179 WORK_FSP = 0x0
544 14:47:06.815260 WL = 0x2
545 14:47:06.819131 RL = 0x2
546 14:47:06.822196 BL = 0x2
547 14:47:06.822277 RPST = 0x0
548 14:47:06.826077 RD_PRE = 0x0
549 14:47:06.826158 WR_PRE = 0x1
550 14:47:06.828530 WR_PST = 0x0
551 14:47:06.828610 DBI_WR = 0x0
552 14:47:06.832346 DBI_RD = 0x0
553 14:47:06.832426 OTF = 0x1
554 14:47:06.835406 ===================================
555 14:47:06.838630 ===================================
556 14:47:06.838711 ANA top config
557 14:47:06.842288 ===================================
558 14:47:06.845442 DLL_ASYNC_EN = 0
559 14:47:06.849165 ALL_SLAVE_EN = 1
560 14:47:06.852856 NEW_RANK_MODE = 1
561 14:47:06.855736 DLL_IDLE_MODE = 1
562 14:47:06.855816 LP45_APHY_COMB_EN = 1
563 14:47:06.859475 TX_ODT_DIS = 1
564 14:47:06.862561 NEW_8X_MODE = 1
565 14:47:06.865556 ===================================
566 14:47:06.869185 ===================================
567 14:47:06.872365 data_rate = 1600
568 14:47:06.872451 CKR = 1
569 14:47:06.876012 DQ_P2S_RATIO = 8
570 14:47:06.879902 ===================================
571 14:47:06.882251 CA_P2S_RATIO = 8
572 14:47:06.885587 DQ_CA_OPEN = 0
573 14:47:06.889231 DQ_SEMI_OPEN = 0
574 14:47:06.892757 CA_SEMI_OPEN = 0
575 14:47:06.892864 CA_FULL_RATE = 0
576 14:47:06.896908 DQ_CKDIV4_EN = 1
577 14:47:06.899116 CA_CKDIV4_EN = 1
578 14:47:06.902592 CA_PREDIV_EN = 0
579 14:47:06.905909 PH8_DLY = 0
580 14:47:06.909514 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 14:47:06.909595 DQ_AAMCK_DIV = 4
582 14:47:06.912435 CA_AAMCK_DIV = 4
583 14:47:06.915886 CA_ADMCK_DIV = 4
584 14:47:06.919534 DQ_TRACK_CA_EN = 0
585 14:47:06.922641 CA_PICK = 800
586 14:47:06.925833 CA_MCKIO = 800
587 14:47:06.925913 MCKIO_SEMI = 0
588 14:47:06.929261 PLL_FREQ = 3068
589 14:47:06.933483 DQ_UI_PI_RATIO = 32
590 14:47:06.936560 CA_UI_PI_RATIO = 0
591 14:47:06.940038 ===================================
592 14:47:06.943724 ===================================
593 14:47:06.943805 memory_type:LPDDR4
594 14:47:06.947313 GP_NUM : 10
595 14:47:06.947395 SRAM_EN : 1
596 14:47:06.951440 MD32_EN : 0
597 14:47:06.954783 ===================================
598 14:47:06.958446 [ANA_INIT] >>>>>>>>>>>>>>
599 14:47:06.958527 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 14:47:06.962462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 14:47:06.965829 ===================================
602 14:47:06.969374 data_rate = 1600,PCW = 0X7600
603 14:47:06.972965 ===================================
604 14:47:06.976204 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 14:47:06.979527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 14:47:06.986684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 14:47:06.989995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 14:47:06.996887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 14:47:06.999410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 14:47:06.999506 [ANA_INIT] flow start
611 14:47:07.003639 [ANA_INIT] PLL >>>>>>>>
612 14:47:07.006329 [ANA_INIT] PLL <<<<<<<<
613 14:47:07.006409 [ANA_INIT] MIDPI >>>>>>>>
614 14:47:07.009355 [ANA_INIT] MIDPI <<<<<<<<
615 14:47:07.013232 [ANA_INIT] DLL >>>>>>>>
616 14:47:07.013312 [ANA_INIT] flow end
617 14:47:07.019358 ============ LP4 DIFF to SE enter ============
618 14:47:07.023239 ============ LP4 DIFF to SE exit ============
619 14:47:07.023320 [ANA_INIT] <<<<<<<<<<<<<
620 14:47:07.026581 [Flow] Enable top DCM control >>>>>
621 14:47:07.030227 [Flow] Enable top DCM control <<<<<
622 14:47:07.032770 Enable DLL master slave shuffle
623 14:47:07.040375 ==============================================================
624 14:47:07.040456 Gating Mode config
625 14:47:07.046323 ==============================================================
626 14:47:07.050078 Config description:
627 14:47:07.059901 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 14:47:07.066489 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 14:47:07.069601 SELPH_MODE 0: By rank 1: By Phase
630 14:47:07.076898 ==============================================================
631 14:47:07.080151 GAT_TRACK_EN = 1
632 14:47:07.080231 RX_GATING_MODE = 2
633 14:47:07.083766 RX_GATING_TRACK_MODE = 2
634 14:47:07.086573 SELPH_MODE = 1
635 14:47:07.089864 PICG_EARLY_EN = 1
636 14:47:07.093433 VALID_LAT_VALUE = 1
637 14:47:07.099862 ==============================================================
638 14:47:07.103407 Enter into Gating configuration >>>>
639 14:47:07.106802 Exit from Gating configuration <<<<
640 14:47:07.110278 Enter into DVFS_PRE_config >>>>>
641 14:47:07.120512 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 14:47:07.123663 Exit from DVFS_PRE_config <<<<<
643 14:47:07.127150 Enter into PICG configuration >>>>
644 14:47:07.131407 Exit from PICG configuration <<<<
645 14:47:07.131488 [RX_INPUT] configuration >>>>>
646 14:47:07.133585 [RX_INPUT] configuration <<<<<
647 14:47:07.140000 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 14:47:07.143954 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 14:47:07.150844 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 14:47:07.157904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 14:47:07.164300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 14:47:07.171180 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 14:47:07.174572 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 14:47:07.178051 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 14:47:07.181609 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 14:47:07.188123 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 14:47:07.191126 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 14:47:07.194963 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 14:47:07.198126 ===================================
660 14:47:07.201603 LPDDR4 DRAM CONFIGURATION
661 14:47:07.204704 ===================================
662 14:47:07.204784 EX_ROW_EN[0] = 0x0
663 14:47:07.207759 EX_ROW_EN[1] = 0x0
664 14:47:07.207841 LP4Y_EN = 0x0
665 14:47:07.211317 WORK_FSP = 0x0
666 14:47:07.211398 WL = 0x2
667 14:47:07.214842 RL = 0x2
668 14:47:07.214923 BL = 0x2
669 14:47:07.217915 RPST = 0x0
670 14:47:07.217996 RD_PRE = 0x0
671 14:47:07.221960 WR_PRE = 0x1
672 14:47:07.224985 WR_PST = 0x0
673 14:47:07.225066 DBI_WR = 0x0
674 14:47:07.228296 DBI_RD = 0x0
675 14:47:07.228376 OTF = 0x1
676 14:47:07.231592 ===================================
677 14:47:07.234908 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 14:47:07.238107 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 14:47:07.245149 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 14:47:07.248711 ===================================
681 14:47:07.248818 LPDDR4 DRAM CONFIGURATION
682 14:47:07.251736 ===================================
683 14:47:07.254878 EX_ROW_EN[0] = 0x10
684 14:47:07.258913 EX_ROW_EN[1] = 0x0
685 14:47:07.258994 LP4Y_EN = 0x0
686 14:47:07.261991 WORK_FSP = 0x0
687 14:47:07.262072 WL = 0x2
688 14:47:07.265741 RL = 0x2
689 14:47:07.265822 BL = 0x2
690 14:47:07.268783 RPST = 0x0
691 14:47:07.268863 RD_PRE = 0x0
692 14:47:07.271832 WR_PRE = 0x1
693 14:47:07.271913 WR_PST = 0x0
694 14:47:07.275613 DBI_WR = 0x0
695 14:47:07.275720 DBI_RD = 0x0
696 14:47:07.278628 OTF = 0x1
697 14:47:07.281925 ===================================
698 14:47:07.288634 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 14:47:07.292146 nWR fixed to 40
700 14:47:07.292228 [ModeRegInit_LP4] CH0 RK0
701 14:47:07.296033 [ModeRegInit_LP4] CH0 RK1
702 14:47:07.299161 [ModeRegInit_LP4] CH1 RK0
703 14:47:07.299242 [ModeRegInit_LP4] CH1 RK1
704 14:47:07.302251 match AC timing 13
705 14:47:07.305682 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 14:47:07.308959 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 14:47:07.315528 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 14:47:07.318789 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 14:47:07.326096 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 14:47:07.326177 [EMI DOE] emi_dcm 0
711 14:47:07.329406 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 14:47:07.329487 ==
713 14:47:07.332262 Dram Type= 6, Freq= 0, CH_0, rank 0
714 14:47:07.339386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 14:47:07.339467 ==
716 14:47:07.342282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 14:47:07.349224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 14:47:07.358578 [CA 0] Center 37 (7~68) winsize 62
719 14:47:07.362710 [CA 1] Center 37 (6~68) winsize 63
720 14:47:07.366225 [CA 2] Center 35 (5~66) winsize 62
721 14:47:07.368690 [CA 3] Center 34 (4~65) winsize 62
722 14:47:07.371955 [CA 4] Center 34 (3~65) winsize 63
723 14:47:07.375151 [CA 5] Center 33 (3~64) winsize 62
724 14:47:07.375232
725 14:47:07.378959 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 14:47:07.379040
727 14:47:07.381942 [CATrainingPosCal] consider 1 rank data
728 14:47:07.385449 u2DelayCellTimex100 = 270/100 ps
729 14:47:07.389103 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 14:47:07.392076 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 14:47:07.398859 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 14:47:07.402113 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 14:47:07.405295 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 14:47:07.408734 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 14:47:07.408832
736 14:47:07.412175 CA PerBit enable=1, Macro0, CA PI delay=33
737 14:47:07.412246
738 14:47:07.416024 [CBTSetCACLKResult] CA Dly = 33
739 14:47:07.416104 CS Dly: 5 (0~36)
740 14:47:07.416167 ==
741 14:47:07.418808 Dram Type= 6, Freq= 0, CH_0, rank 1
742 14:47:07.425660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 14:47:07.425735 ==
744 14:47:07.429542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 14:47:07.435802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 14:47:07.444728 [CA 0] Center 37 (6~68) winsize 63
747 14:47:07.448050 [CA 1] Center 37 (7~68) winsize 62
748 14:47:07.451765 [CA 2] Center 35 (5~66) winsize 62
749 14:47:07.455345 [CA 3] Center 35 (4~66) winsize 63
750 14:47:07.458669 [CA 4] Center 34 (4~65) winsize 62
751 14:47:07.461869 [CA 5] Center 33 (3~64) winsize 62
752 14:47:07.461965
753 14:47:07.465895 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 14:47:07.465991
755 14:47:07.469278 [CATrainingPosCal] consider 2 rank data
756 14:47:07.472199 u2DelayCellTimex100 = 270/100 ps
757 14:47:07.474926 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 14:47:07.478254 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 14:47:07.485394 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 14:47:07.488196 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 14:47:07.492062 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
762 14:47:07.495179 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 14:47:07.495280
764 14:47:07.498428 CA PerBit enable=1, Macro0, CA PI delay=33
765 14:47:07.498502
766 14:47:07.501705 [CBTSetCACLKResult] CA Dly = 33
767 14:47:07.501787 CS Dly: 6 (0~38)
768 14:47:07.501865
769 14:47:07.505262 ----->DramcWriteLeveling(PI) begin...
770 14:47:07.508276 ==
771 14:47:07.508374 Dram Type= 6, Freq= 0, CH_0, rank 0
772 14:47:07.515346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 14:47:07.515446 ==
774 14:47:07.518930 Write leveling (Byte 0): 29 => 29
775 14:47:07.519028 Write leveling (Byte 1): 29 => 29
776 14:47:07.523060 DramcWriteLeveling(PI) end<-----
777 14:47:07.523155
778 14:47:07.523242 ==
779 14:47:07.526729 Dram Type= 6, Freq= 0, CH_0, rank 0
780 14:47:07.530159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 14:47:07.530256 ==
782 14:47:07.533835 [Gating] SW mode calibration
783 14:47:07.540794 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 14:47:07.548101 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 14:47:07.551168 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 14:47:07.554565 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 14:47:07.558012 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 14:47:07.564637 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 14:47:07.568556 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 14:47:07.572029 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 14:47:07.578369 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 14:47:07.581980 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 14:47:07.585561 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 14:47:07.591733 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 14:47:07.595017 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 14:47:07.598645 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 14:47:07.602210 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 14:47:07.608563 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 14:47:07.611908 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 14:47:07.615401 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 14:47:07.621872 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 14:47:07.625502 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
803 14:47:07.628515 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 14:47:07.635812 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 14:47:07.638726 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 14:47:07.642719 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 14:47:07.648752 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 14:47:07.652056 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 14:47:07.655700 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 14:47:07.661937 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 14:47:07.665393 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 14:47:07.669355 0 9 12 | B1->B0 | 2626 3333 | 1 0 | (1 1) (0 0)
813 14:47:07.672186 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 14:47:07.678887 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 14:47:07.682837 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 14:47:07.685380 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 14:47:07.692495 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 14:47:07.696124 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 14:47:07.699151 0 10 8 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
820 14:47:07.706310 0 10 12 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (1 0)
821 14:47:07.709179 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 14:47:07.713232 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 14:47:07.719643 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 14:47:07.722473 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 14:47:07.725965 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 14:47:07.729501 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 14:47:07.736139 0 11 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
828 14:47:07.739600 0 11 12 | B1->B0 | 3535 3f3f | 1 0 | (1 1) (0 0)
829 14:47:07.743077 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 14:47:07.750053 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 14:47:07.752755 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 14:47:07.756272 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 14:47:07.762801 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 14:47:07.767898 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 14:47:07.770062 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 14:47:07.776586 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 14:47:07.779938 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 14:47:07.783304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 14:47:07.786505 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 14:47:07.794053 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 14:47:07.796679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 14:47:07.800457 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 14:47:07.806746 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 14:47:07.810126 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 14:47:07.813183 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 14:47:07.820260 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 14:47:07.823451 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 14:47:07.826750 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 14:47:07.833614 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 14:47:07.837136 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 14:47:07.840198 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 14:47:07.844129 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 14:47:07.850910 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 14:47:07.853773 Total UI for P1: 0, mck2ui 16
855 14:47:07.857138 best dqsien dly found for B0: ( 0, 14, 10)
856 14:47:07.860865 Total UI for P1: 0, mck2ui 16
857 14:47:07.863648 best dqsien dly found for B1: ( 0, 14, 10)
858 14:47:07.866849 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
859 14:47:07.871376 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 14:47:07.871457
861 14:47:07.874018 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 14:47:07.877154 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 14:47:07.880327 [Gating] SW calibration Done
864 14:47:07.880468 ==
865 14:47:07.883690 Dram Type= 6, Freq= 0, CH_0, rank 0
866 14:47:07.887234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 14:47:07.887315 ==
868 14:47:07.890352 RX Vref Scan: 0
869 14:47:07.890432
870 14:47:07.890496 RX Vref 0 -> 0, step: 1
871 14:47:07.890555
872 14:47:07.893745 RX Delay -130 -> 252, step: 16
873 14:47:07.897295 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 14:47:07.903875 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 14:47:07.907056 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 14:47:07.912477 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 14:47:07.914429 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 14:47:07.917349 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 14:47:07.924076 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 14:47:07.927638 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 14:47:07.930876 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 14:47:07.934151 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 14:47:07.937370 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 14:47:07.944591 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 14:47:07.948032 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 14:47:07.951776 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
887 14:47:07.955454 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 14:47:07.957652 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 14:47:07.957732 ==
890 14:47:07.961295 Dram Type= 6, Freq= 0, CH_0, rank 0
891 14:47:07.968028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 14:47:07.968109 ==
893 14:47:07.968172 DQS Delay:
894 14:47:07.971294 DQS0 = 0, DQS1 = 0
895 14:47:07.971375 DQM Delay:
896 14:47:07.971439 DQM0 = 86, DQM1 = 79
897 14:47:07.974646 DQ Delay:
898 14:47:07.977672 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 14:47:07.981370 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
900 14:47:07.984780 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 14:47:07.987960 DQ12 =85, DQ13 =77, DQ14 =93, DQ15 =93
902 14:47:07.988041
903 14:47:07.988105
904 14:47:07.988197 ==
905 14:47:07.991137 Dram Type= 6, Freq= 0, CH_0, rank 0
906 14:47:07.995081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 14:47:07.995162 ==
908 14:47:07.995225
909 14:47:07.995283
910 14:47:07.997962 TX Vref Scan disable
911 14:47:07.998042 == TX Byte 0 ==
912 14:47:08.004419 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 14:47:08.008154 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 14:47:08.008236 == TX Byte 1 ==
915 14:47:08.015133 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 14:47:08.018247 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 14:47:08.018327 ==
918 14:47:08.021578 Dram Type= 6, Freq= 0, CH_0, rank 0
919 14:47:08.024770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 14:47:08.024852 ==
921 14:47:08.038614 TX Vref=22, minBit 0, minWin=27, winSum=442
922 14:47:08.042453 TX Vref=24, minBit 3, minWin=27, winSum=444
923 14:47:08.045724 TX Vref=26, minBit 12, minWin=27, winSum=448
924 14:47:08.048395 TX Vref=28, minBit 1, minWin=28, winSum=452
925 14:47:08.051963 TX Vref=30, minBit 2, minWin=28, winSum=452
926 14:47:08.055456 TX Vref=32, minBit 3, minWin=27, winSum=451
927 14:47:08.062105 [TxChooseVref] Worse bit 1, Min win 28, Win sum 452, Final Vref 28
928 14:47:08.062187
929 14:47:08.065461 Final TX Range 1 Vref 28
930 14:47:08.065542
931 14:47:08.065605 ==
932 14:47:08.068828 Dram Type= 6, Freq= 0, CH_0, rank 0
933 14:47:08.072435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 14:47:08.072516 ==
935 14:47:08.072580
936 14:47:08.072640
937 14:47:08.075680 TX Vref Scan disable
938 14:47:08.080243 == TX Byte 0 ==
939 14:47:08.082297 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 14:47:08.085778 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 14:47:08.089120 == TX Byte 1 ==
942 14:47:08.092021 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 14:47:08.095918 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 14:47:08.095999
945 14:47:08.099250 [DATLAT]
946 14:47:08.099331 Freq=800, CH0 RK0
947 14:47:08.099395
948 14:47:08.102084 DATLAT Default: 0xa
949 14:47:08.102182 0, 0xFFFF, sum = 0
950 14:47:08.105585 1, 0xFFFF, sum = 0
951 14:47:08.105667 2, 0xFFFF, sum = 0
952 14:47:08.108704 3, 0xFFFF, sum = 0
953 14:47:08.108812 4, 0xFFFF, sum = 0
954 14:47:08.112197 5, 0xFFFF, sum = 0
955 14:47:08.112279 6, 0xFFFF, sum = 0
956 14:47:08.115669 7, 0xFFFF, sum = 0
957 14:47:08.115750 8, 0xFFFF, sum = 0
958 14:47:08.118918 9, 0x0, sum = 1
959 14:47:08.119000 10, 0x0, sum = 2
960 14:47:08.122522 11, 0x0, sum = 3
961 14:47:08.122604 12, 0x0, sum = 4
962 14:47:08.125892 best_step = 10
963 14:47:08.125972
964 14:47:08.126035 ==
965 14:47:08.128929 Dram Type= 6, Freq= 0, CH_0, rank 0
966 14:47:08.132509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 14:47:08.132590 ==
968 14:47:08.132653 RX Vref Scan: 1
969 14:47:08.136615
970 14:47:08.136696 Set Vref Range= 32 -> 127
971 14:47:08.136759
972 14:47:08.139768 RX Vref 32 -> 127, step: 1
973 14:47:08.139848
974 14:47:08.142721 RX Delay -95 -> 252, step: 8
975 14:47:08.142801
976 14:47:08.146147 Set Vref, RX VrefLevel [Byte0]: 32
977 14:47:08.149038 [Byte1]: 32
978 14:47:08.149144
979 14:47:08.153183 Set Vref, RX VrefLevel [Byte0]: 33
980 14:47:08.156509 [Byte1]: 33
981 14:47:08.156589
982 14:47:08.159714 Set Vref, RX VrefLevel [Byte0]: 34
983 14:47:08.162786 [Byte1]: 34
984 14:47:08.166264
985 14:47:08.166344 Set Vref, RX VrefLevel [Byte0]: 35
986 14:47:08.170149 [Byte1]: 35
987 14:47:08.174119
988 14:47:08.174198 Set Vref, RX VrefLevel [Byte0]: 36
989 14:47:08.177720 [Byte1]: 36
990 14:47:08.181725
991 14:47:08.181805 Set Vref, RX VrefLevel [Byte0]: 37
992 14:47:08.185410 [Byte1]: 37
993 14:47:08.189474
994 14:47:08.189554 Set Vref, RX VrefLevel [Byte0]: 38
995 14:47:08.193235 [Byte1]: 38
996 14:47:08.197325
997 14:47:08.197407 Set Vref, RX VrefLevel [Byte0]: 39
998 14:47:08.200778 [Byte1]: 39
999 14:47:08.205090
1000 14:47:08.205160 Set Vref, RX VrefLevel [Byte0]: 40
1001 14:47:08.208148 [Byte1]: 40
1002 14:47:08.213187
1003 14:47:08.213254 Set Vref, RX VrefLevel [Byte0]: 41
1004 14:47:08.216159 [Byte1]: 41
1005 14:47:08.219411
1006 14:47:08.219480 Set Vref, RX VrefLevel [Byte0]: 42
1007 14:47:08.222862 [Byte1]: 42
1008 14:47:08.226963
1009 14:47:08.227032 Set Vref, RX VrefLevel [Byte0]: 43
1010 14:47:08.231009 [Byte1]: 43
1011 14:47:08.234523
1012 14:47:08.234590 Set Vref, RX VrefLevel [Byte0]: 44
1013 14:47:08.237827 [Byte1]: 44
1014 14:47:08.242382
1015 14:47:08.242454 Set Vref, RX VrefLevel [Byte0]: 45
1016 14:47:08.245460 [Byte1]: 45
1017 14:47:08.249803
1018 14:47:08.249876 Set Vref, RX VrefLevel [Byte0]: 46
1019 14:47:08.253394 [Byte1]: 46
1020 14:47:08.257916
1021 14:47:08.257986 Set Vref, RX VrefLevel [Byte0]: 47
1022 14:47:08.261123 [Byte1]: 47
1023 14:47:08.265113
1024 14:47:08.265181 Set Vref, RX VrefLevel [Byte0]: 48
1025 14:47:08.268556 [Byte1]: 48
1026 14:47:08.272932
1027 14:47:08.273026 Set Vref, RX VrefLevel [Byte0]: 49
1028 14:47:08.276456 [Byte1]: 49
1029 14:47:08.280371
1030 14:47:08.280444 Set Vref, RX VrefLevel [Byte0]: 50
1031 14:47:08.283613 [Byte1]: 50
1032 14:47:08.287826
1033 14:47:08.287894 Set Vref, RX VrefLevel [Byte0]: 51
1034 14:47:08.292076 [Byte1]: 51
1035 14:47:08.295483
1036 14:47:08.295557 Set Vref, RX VrefLevel [Byte0]: 52
1037 14:47:08.298795 [Byte1]: 52
1038 14:47:08.303476
1039 14:47:08.303546 Set Vref, RX VrefLevel [Byte0]: 53
1040 14:47:08.306490 [Byte1]: 53
1041 14:47:08.310615
1042 14:47:08.310693 Set Vref, RX VrefLevel [Byte0]: 54
1043 14:47:08.314159 [Byte1]: 54
1044 14:47:08.318102
1045 14:47:08.318181 Set Vref, RX VrefLevel [Byte0]: 55
1046 14:47:08.321563 [Byte1]: 55
1047 14:47:08.325898
1048 14:47:08.325977 Set Vref, RX VrefLevel [Byte0]: 56
1049 14:47:08.329555 [Byte1]: 56
1050 14:47:08.333524
1051 14:47:08.333628 Set Vref, RX VrefLevel [Byte0]: 57
1052 14:47:08.336513 [Byte1]: 57
1053 14:47:08.341094
1054 14:47:08.341173 Set Vref, RX VrefLevel [Byte0]: 58
1055 14:47:08.344413 [Byte1]: 58
1056 14:47:08.348426
1057 14:47:08.348504 Set Vref, RX VrefLevel [Byte0]: 59
1058 14:47:08.352433 [Byte1]: 59
1059 14:47:08.356083
1060 14:47:08.356161 Set Vref, RX VrefLevel [Byte0]: 60
1061 14:47:08.359595 [Byte1]: 60
1062 14:47:08.363868
1063 14:47:08.363939 Set Vref, RX VrefLevel [Byte0]: 61
1064 14:47:08.367904 [Byte1]: 61
1065 14:47:08.371763
1066 14:47:08.371829 Set Vref, RX VrefLevel [Byte0]: 62
1067 14:47:08.374782 [Byte1]: 62
1068 14:47:08.379271
1069 14:47:08.379341 Set Vref, RX VrefLevel [Byte0]: 63
1070 14:47:08.383524 [Byte1]: 63
1071 14:47:08.387356
1072 14:47:08.387430 Set Vref, RX VrefLevel [Byte0]: 64
1073 14:47:08.390226 [Byte1]: 64
1074 14:47:08.394133
1075 14:47:08.394201 Set Vref, RX VrefLevel [Byte0]: 65
1076 14:47:08.397978 [Byte1]: 65
1077 14:47:08.402198
1078 14:47:08.402264 Set Vref, RX VrefLevel [Byte0]: 66
1079 14:47:08.405618 [Byte1]: 66
1080 14:47:08.409998
1081 14:47:08.410068 Set Vref, RX VrefLevel [Byte0]: 67
1082 14:47:08.412608 [Byte1]: 67
1083 14:47:08.417272
1084 14:47:08.417336 Set Vref, RX VrefLevel [Byte0]: 68
1085 14:47:08.420521 [Byte1]: 68
1086 14:47:08.424634
1087 14:47:08.424698 Set Vref, RX VrefLevel [Byte0]: 69
1088 14:47:08.428127 [Byte1]: 69
1089 14:47:08.432519
1090 14:47:08.432586 Set Vref, RX VrefLevel [Byte0]: 70
1091 14:47:08.435743 [Byte1]: 70
1092 14:47:08.439924
1093 14:47:08.439987 Set Vref, RX VrefLevel [Byte0]: 71
1094 14:47:08.443151 [Byte1]: 71
1095 14:47:08.447385
1096 14:47:08.447453 Set Vref, RX VrefLevel [Byte0]: 72
1097 14:47:08.450718 [Byte1]: 72
1098 14:47:08.455416
1099 14:47:08.455483 Set Vref, RX VrefLevel [Byte0]: 73
1100 14:47:08.458240 [Byte1]: 73
1101 14:47:08.462314
1102 14:47:08.462378 Set Vref, RX VrefLevel [Byte0]: 74
1103 14:47:08.466082 [Byte1]: 74
1104 14:47:08.470511
1105 14:47:08.470577 Set Vref, RX VrefLevel [Byte0]: 75
1106 14:47:08.474058 [Byte1]: 75
1107 14:47:08.478165
1108 14:47:08.478277 Set Vref, RX VrefLevel [Byte0]: 76
1109 14:47:08.481459 [Byte1]: 76
1110 14:47:08.485132
1111 14:47:08.485196 Final RX Vref Byte 0 = 60 to rank0
1112 14:47:08.488690 Final RX Vref Byte 1 = 58 to rank0
1113 14:47:08.492922 Final RX Vref Byte 0 = 60 to rank1
1114 14:47:08.495498 Final RX Vref Byte 1 = 58 to rank1==
1115 14:47:08.498838 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 14:47:08.502123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 14:47:08.505682 ==
1118 14:47:08.505749 DQS Delay:
1119 14:47:08.505807 DQS0 = 0, DQS1 = 0
1120 14:47:08.509290 DQM Delay:
1121 14:47:08.509357 DQM0 = 87, DQM1 = 78
1122 14:47:08.512390 DQ Delay:
1123 14:47:08.512451 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1124 14:47:08.515673 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1125 14:47:08.519051 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1126 14:47:08.522089 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1127 14:47:08.522159
1128 14:47:08.526673
1129 14:47:08.533171 [DQSOSCAuto] RK0, (LSB)MR18= 0x240b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 400 ps
1130 14:47:08.536127 CH0 RK0: MR19=606, MR18=240B
1131 14:47:08.539395 CH0_RK0: MR19=0x606, MR18=0x240B, DQSOSC=400, MR23=63, INC=92, DEC=61
1132 14:47:08.542407
1133 14:47:08.545915 ----->DramcWriteLeveling(PI) begin...
1134 14:47:08.545980 ==
1135 14:47:08.549278 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 14:47:08.552644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 14:47:08.552710 ==
1138 14:47:08.555617 Write leveling (Byte 0): 29 => 29
1139 14:47:08.559860 Write leveling (Byte 1): 27 => 27
1140 14:47:08.563178 DramcWriteLeveling(PI) end<-----
1141 14:47:08.563244
1142 14:47:08.563301 ==
1143 14:47:08.566566 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 14:47:08.569552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 14:47:08.569617 ==
1146 14:47:08.573102 [Gating] SW mode calibration
1147 14:47:08.579171 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 14:47:08.582599 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 14:47:08.589965 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 14:47:08.633430 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 14:47:08.633691 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 14:47:08.633759 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 14:47:08.634440 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 14:47:08.635131 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 14:47:08.635529 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 14:47:08.635775 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 14:47:08.635838 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 14:47:08.636080 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 14:47:08.636324 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 14:47:08.656889 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 14:47:08.657225 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 14:47:08.657300 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 14:47:08.657546 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 14:47:08.658157 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 14:47:08.660688 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 14:47:08.664810 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1167 14:47:08.667715 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1168 14:47:08.670703 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 14:47:08.677461 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 14:47:08.681000 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 14:47:08.683943 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 14:47:08.690627 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 14:47:08.694129 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 14:47:08.697568 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 14:47:08.705130 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1176 14:47:08.707616 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1177 14:47:08.710951 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 14:47:08.717782 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 14:47:08.721911 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 14:47:08.725280 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 14:47:08.728784 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 14:47:08.735120 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1183 14:47:08.738693 0 10 8 | B1->B0 | 3232 2828 | 0 0 | (0 0) (1 1)
1184 14:47:08.741598 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1185 14:47:08.748478 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 14:47:08.751788 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 14:47:08.755241 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 14:47:08.761955 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 14:47:08.765222 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 14:47:08.768806 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1191 14:47:08.772841 0 11 8 | B1->B0 | 2727 3a3a | 1 0 | (0 0) (0 0)
1192 14:47:08.776639 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1193 14:47:08.783365 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 14:47:08.786968 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 14:47:08.790560 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 14:47:08.797475 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 14:47:08.800648 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 14:47:08.804364 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 14:47:08.807299 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 14:47:08.813949 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 14:47:08.817932 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 14:47:08.821298 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 14:47:08.827561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 14:47:08.830763 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 14:47:08.834419 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 14:47:08.841691 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 14:47:08.844064 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 14:47:08.847761 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 14:47:08.851297 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 14:47:08.858816 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 14:47:08.861114 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 14:47:08.864582 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 14:47:08.871299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 14:47:08.874653 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 14:47:08.877671 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 14:47:08.882026 Total UI for P1: 0, mck2ui 16
1217 14:47:08.884552 best dqsien dly found for B0: ( 0, 14, 4)
1218 14:47:08.891501 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 14:47:08.891906 Total UI for P1: 0, mck2ui 16
1220 14:47:08.897907 best dqsien dly found for B1: ( 0, 14, 6)
1221 14:47:08.902022 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1222 14:47:08.904812 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1223 14:47:08.905313
1224 14:47:08.907949 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 14:47:08.911185 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1226 14:47:08.914756 [Gating] SW calibration Done
1227 14:47:08.915163 ==
1228 14:47:08.918135 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 14:47:08.921304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 14:47:08.921712 ==
1231 14:47:08.922048 RX Vref Scan: 0
1232 14:47:08.924666
1233 14:47:08.925120 RX Vref 0 -> 0, step: 1
1234 14:47:08.925451
1235 14:47:08.928447 RX Delay -130 -> 252, step: 16
1236 14:47:08.931770 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 14:47:08.934970 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1238 14:47:08.941496 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1239 14:47:08.945013 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1240 14:47:08.948696 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1241 14:47:08.951785 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 14:47:08.955336 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 14:47:08.961947 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1244 14:47:08.965473 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 14:47:08.968448 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 14:47:08.971890 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1247 14:47:08.975192 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 14:47:08.982432 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1249 14:47:08.985345 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1250 14:47:08.988477 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1251 14:47:08.992670 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1252 14:47:08.993131 ==
1253 14:47:08.995401 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 14:47:08.998648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 14:47:09.002176 ==
1256 14:47:09.002590 DQS Delay:
1257 14:47:09.003175 DQS0 = 0, DQS1 = 0
1258 14:47:09.005268 DQM Delay:
1259 14:47:09.005680 DQM0 = 85, DQM1 = 75
1260 14:47:09.008671 DQ Delay:
1261 14:47:09.009124 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1262 14:47:09.012634 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1263 14:47:09.015706 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1264 14:47:09.018542 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1265 14:47:09.018955
1266 14:47:09.022218
1267 14:47:09.022630 ==
1268 14:47:09.025755 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 14:47:09.028756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 14:47:09.029217 ==
1271 14:47:09.029547
1272 14:47:09.029848
1273 14:47:09.032493 TX Vref Scan disable
1274 14:47:09.032905 == TX Byte 0 ==
1275 14:47:09.038608 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1276 14:47:09.042327 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1277 14:47:09.042746 == TX Byte 1 ==
1278 14:47:09.045348 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1279 14:47:09.052643 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1280 14:47:09.053234 ==
1281 14:47:09.056418 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 14:47:09.058834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 14:47:09.059245 ==
1284 14:47:09.072913 TX Vref=22, minBit 12, minWin=26, winSum=436
1285 14:47:09.075456 TX Vref=24, minBit 3, minWin=27, winSum=444
1286 14:47:09.079210 TX Vref=26, minBit 3, minWin=27, winSum=448
1287 14:47:09.082437 TX Vref=28, minBit 12, minWin=27, winSum=450
1288 14:47:09.086205 TX Vref=30, minBit 9, minWin=27, winSum=449
1289 14:47:09.089310 TX Vref=32, minBit 8, minWin=27, winSum=450
1290 14:47:09.095869 [TxChooseVref] Worse bit 12, Min win 27, Win sum 450, Final Vref 28
1291 14:47:09.096277
1292 14:47:09.099665 Final TX Range 1 Vref 28
1293 14:47:09.100072
1294 14:47:09.100402 ==
1295 14:47:09.102959 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 14:47:09.105864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 14:47:09.106272 ==
1298 14:47:09.106617
1299 14:47:09.109676
1300 14:47:09.110077 TX Vref Scan disable
1301 14:47:09.112932 == TX Byte 0 ==
1302 14:47:09.115927 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1303 14:47:09.119834 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1304 14:47:09.123013 == TX Byte 1 ==
1305 14:47:09.126202 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1306 14:47:09.129693 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1307 14:47:09.130129
1308 14:47:09.132850 [DATLAT]
1309 14:47:09.133456 Freq=800, CH0 RK1
1310 14:47:09.133935
1311 14:47:09.136777 DATLAT Default: 0xa
1312 14:47:09.137307 0, 0xFFFF, sum = 0
1313 14:47:09.139807 1, 0xFFFF, sum = 0
1314 14:47:09.140369 2, 0xFFFF, sum = 0
1315 14:47:09.143208 3, 0xFFFF, sum = 0
1316 14:47:09.143786 4, 0xFFFF, sum = 0
1317 14:47:09.146321 5, 0xFFFF, sum = 0
1318 14:47:09.146779 6, 0xFFFF, sum = 0
1319 14:47:09.149906 7, 0xFFFF, sum = 0
1320 14:47:09.150508 8, 0xFFFF, sum = 0
1321 14:47:09.152758 9, 0x0, sum = 1
1322 14:47:09.153308 10, 0x0, sum = 2
1323 14:47:09.156836 11, 0x0, sum = 3
1324 14:47:09.157469 12, 0x0, sum = 4
1325 14:47:09.159419 best_step = 10
1326 14:47:09.159763
1327 14:47:09.160058 ==
1328 14:47:09.163183 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 14:47:09.166234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 14:47:09.166673 ==
1331 14:47:09.169677 RX Vref Scan: 0
1332 14:47:09.170153
1333 14:47:09.170479 RX Vref 0 -> 0, step: 1
1334 14:47:09.170784
1335 14:47:09.172829 RX Delay -95 -> 252, step: 8
1336 14:47:09.179958 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 14:47:09.182890 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 14:47:09.186448 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 14:47:09.190030 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 14:47:09.193344 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 14:47:09.196453 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 14:47:09.203362 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 14:47:09.206808 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 14:47:09.211188 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 14:47:09.213944 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 14:47:09.216470 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 14:47:09.223420 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 14:47:09.227037 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1349 14:47:09.230385 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 14:47:09.233353 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 14:47:09.236523 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 14:47:09.240009 ==
1353 14:47:09.243269 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 14:47:09.246854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 14:47:09.247296 ==
1356 14:47:09.247641 DQS Delay:
1357 14:47:09.250076 DQS0 = 0, DQS1 = 0
1358 14:47:09.250629 DQM Delay:
1359 14:47:09.253689 DQM0 = 87, DQM1 = 78
1360 14:47:09.254102 DQ Delay:
1361 14:47:09.256703 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1362 14:47:09.259926 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 14:47:09.263471 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 14:47:09.266632 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1365 14:47:09.267183
1366 14:47:09.267658
1367 14:47:09.273725 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1368 14:47:09.276793 CH0 RK1: MR19=606, MR18=2C15
1369 14:47:09.284028 CH0_RK1: MR19=0x606, MR18=0x2C15, DQSOSC=398, MR23=63, INC=93, DEC=62
1370 14:47:09.287162 [RxdqsGatingPostProcess] freq 800
1371 14:47:09.290115 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 14:47:09.293886 Pre-setting of DQS Precalculation
1373 14:47:09.300150 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 14:47:09.300228 ==
1375 14:47:09.303559 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 14:47:09.306712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 14:47:09.306791 ==
1378 14:47:09.313666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 14:47:09.316947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 14:47:09.327443 [CA 0] Center 36 (6~66) winsize 61
1381 14:47:09.330599 [CA 1] Center 36 (6~66) winsize 61
1382 14:47:09.333922 [CA 2] Center 34 (4~64) winsize 61
1383 14:47:09.337268 [CA 3] Center 33 (3~64) winsize 62
1384 14:47:09.340883 [CA 4] Center 34 (4~65) winsize 62
1385 14:47:09.343836 [CA 5] Center 33 (3~64) winsize 62
1386 14:47:09.343914
1387 14:47:09.347648 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 14:47:09.347751
1389 14:47:09.350684 [CATrainingPosCal] consider 1 rank data
1390 14:47:09.353738 u2DelayCellTimex100 = 270/100 ps
1391 14:47:09.358258 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 14:47:09.360588 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 14:47:09.363928 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1394 14:47:09.370493 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 14:47:09.373646 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 14:47:09.377440 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 14:47:09.377519
1398 14:47:09.380522 CA PerBit enable=1, Macro0, CA PI delay=33
1399 14:47:09.380601
1400 14:47:09.383929 [CBTSetCACLKResult] CA Dly = 33
1401 14:47:09.384008 CS Dly: 3 (0~34)
1402 14:47:09.384069 ==
1403 14:47:09.387327 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 14:47:09.394894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 14:47:09.394973 ==
1406 14:47:09.397520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 14:47:09.404404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 14:47:09.412988 [CA 0] Center 36 (6~67) winsize 62
1409 14:47:09.416558 [CA 1] Center 36 (6~67) winsize 62
1410 14:47:09.419621 [CA 2] Center 34 (4~65) winsize 62
1411 14:47:09.423566 [CA 3] Center 33 (3~64) winsize 62
1412 14:47:09.426389 [CA 4] Center 34 (4~65) winsize 62
1413 14:47:09.430156 [CA 5] Center 33 (3~64) winsize 62
1414 14:47:09.430235
1415 14:47:09.433881 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 14:47:09.433961
1417 14:47:09.437576 [CATrainingPosCal] consider 2 rank data
1418 14:47:09.441396 u2DelayCellTimex100 = 270/100 ps
1419 14:47:09.444829 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 14:47:09.448892 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 14:47:09.453173 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1422 14:47:09.456443 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 14:47:09.460436 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 14:47:09.464134 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 14:47:09.464213
1426 14:47:09.467860 CA PerBit enable=1, Macro0, CA PI delay=33
1427 14:47:09.467939
1428 14:47:09.471360 [CBTSetCACLKResult] CA Dly = 33
1429 14:47:09.471438 CS Dly: 4 (0~37)
1430 14:47:09.471500
1431 14:47:09.474628 ----->DramcWriteLeveling(PI) begin...
1432 14:47:09.474708 ==
1433 14:47:09.477638 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 14:47:09.480895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 14:47:09.481035 ==
1436 14:47:09.484297 Write leveling (Byte 0): 26 => 26
1437 14:47:09.487532 Write leveling (Byte 1): 28 => 28
1438 14:47:09.490967 DramcWriteLeveling(PI) end<-----
1439 14:47:09.491046
1440 14:47:09.491108 ==
1441 14:47:09.495290 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 14:47:09.497565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 14:47:09.501365 ==
1444 14:47:09.501444 [Gating] SW mode calibration
1445 14:47:09.507879 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 14:47:09.514522 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 14:47:09.517940 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 14:47:09.524446 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1449 14:47:09.527657 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1450 14:47:09.531381 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 14:47:09.538113 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 14:47:09.541191 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 14:47:09.544871 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 14:47:09.547907 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 14:47:09.554515 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 14:47:09.558016 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 14:47:09.561359 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 14:47:09.568297 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 14:47:09.571354 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1460 14:47:09.575469 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 14:47:09.582041 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 14:47:09.584987 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 14:47:09.588798 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1464 14:47:09.595124 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 14:47:09.598762 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1466 14:47:09.601566 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1467 14:47:09.605047 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 14:47:09.611668 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 14:47:09.616625 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 14:47:09.619189 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 14:47:09.625025 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 14:47:09.628470 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 14:47:09.631718 0 9 8 | B1->B0 | 2525 2828 | 1 0 | (1 1) (0 0)
1474 14:47:09.638645 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1475 14:47:09.642121 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1476 14:47:09.645119 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 14:47:09.652116 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 14:47:09.655320 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 14:47:09.658429 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 14:47:09.665428 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1481 14:47:09.668611 0 10 8 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
1482 14:47:09.672813 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 14:47:09.675470 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 14:47:09.682818 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 14:47:09.685415 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1486 14:47:09.689294 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 14:47:09.695896 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 14:47:09.698951 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 14:47:09.702771 0 11 8 | B1->B0 | 3434 3636 | 0 0 | (0 0) (1 1)
1490 14:47:09.709347 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 14:47:09.712664 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 14:47:09.716672 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 14:47:09.722621 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 14:47:09.725732 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 14:47:09.729394 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 14:47:09.732558 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1497 14:47:09.739602 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 14:47:09.742546 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 14:47:09.746121 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 14:47:09.752851 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 14:47:09.756157 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 14:47:09.759794 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 14:47:09.766608 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 14:47:09.769441 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 14:47:09.772931 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 14:47:09.780104 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 14:47:09.783567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 14:47:09.785982 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 14:47:09.792925 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 14:47:09.796287 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 14:47:09.799370 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 14:47:09.803004 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 14:47:09.809626 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 14:47:09.812750 Total UI for P1: 0, mck2ui 16
1515 14:47:09.816078 best dqsien dly found for B0: ( 0, 14, 6)
1516 14:47:09.819940 Total UI for P1: 0, mck2ui 16
1517 14:47:09.822859 best dqsien dly found for B1: ( 0, 14, 6)
1518 14:47:09.826736 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1519 14:47:09.829887 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1520 14:47:09.829966
1521 14:47:09.832987 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 14:47:09.836675 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1523 14:47:09.839835 [Gating] SW calibration Done
1524 14:47:09.839914 ==
1525 14:47:09.843199 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 14:47:09.846482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 14:47:09.846562 ==
1528 14:47:09.850225 RX Vref Scan: 0
1529 14:47:09.850320
1530 14:47:09.850382 RX Vref 0 -> 0, step: 1
1531 14:47:09.850440
1532 14:47:09.853126 RX Delay -130 -> 252, step: 16
1533 14:47:09.856895 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1534 14:47:09.860223 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1535 14:47:09.867015 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1536 14:47:09.870426 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1537 14:47:09.873792 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1538 14:47:09.876659 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1539 14:47:09.880365 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1540 14:47:09.887333 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1541 14:47:09.890903 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1542 14:47:09.893618 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1543 14:47:09.897782 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1544 14:47:09.900333 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1545 14:47:09.907213 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1546 14:47:09.910564 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1547 14:47:09.914072 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1548 14:47:09.917340 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1549 14:47:09.917411 ==
1550 14:47:09.920515 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 14:47:09.924226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 14:47:09.927249 ==
1553 14:47:09.927344 DQS Delay:
1554 14:47:09.927430 DQS0 = 0, DQS1 = 0
1555 14:47:09.930972 DQM Delay:
1556 14:47:09.931041 DQM0 = 82, DQM1 = 75
1557 14:47:09.934264 DQ Delay:
1558 14:47:09.934380 DQ0 =93, DQ1 =69, DQ2 =69, DQ3 =85
1559 14:47:09.937623 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1560 14:47:09.940910 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1561 14:47:09.944777 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1562 14:47:09.944880
1563 14:47:09.944967
1564 14:47:09.947690 ==
1565 14:47:09.950714 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 14:47:09.953942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 14:47:09.954027 ==
1568 14:47:09.954090
1569 14:47:09.954148
1570 14:47:09.957365 TX Vref Scan disable
1571 14:47:09.957444 == TX Byte 0 ==
1572 14:47:09.960786 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1573 14:47:09.967544 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1574 14:47:09.967629 == TX Byte 1 ==
1575 14:47:09.971011 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 14:47:09.977713 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 14:47:09.977793 ==
1578 14:47:09.981129 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 14:47:09.984526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 14:47:09.984605 ==
1581 14:47:09.997188 TX Vref=22, minBit 0, minWin=27, winSum=435
1582 14:47:10.000544 TX Vref=24, minBit 0, minWin=27, winSum=438
1583 14:47:10.004174 TX Vref=26, minBit 0, minWin=27, winSum=444
1584 14:47:10.007599 TX Vref=28, minBit 4, minWin=27, winSum=449
1585 14:47:10.010668 TX Vref=30, minBit 5, minWin=27, winSum=448
1586 14:47:10.014164 TX Vref=32, minBit 9, minWin=27, winSum=450
1587 14:47:10.021418 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 32
1588 14:47:10.021499
1589 14:47:10.025173 Final TX Range 1 Vref 32
1590 14:47:10.025253
1591 14:47:10.025315 ==
1592 14:47:10.028710 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 14:47:10.031654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 14:47:10.031734 ==
1595 14:47:10.031796
1596 14:47:10.031854
1597 14:47:10.034717 TX Vref Scan disable
1598 14:47:10.038208 == TX Byte 0 ==
1599 14:47:10.041878 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1600 14:47:10.044695 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1601 14:47:10.048461 == TX Byte 1 ==
1602 14:47:10.051669 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 14:47:10.054992 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 14:47:10.055082
1605 14:47:10.055145 [DATLAT]
1606 14:47:10.058766 Freq=800, CH1 RK0
1607 14:47:10.058845
1608 14:47:10.061918 DATLAT Default: 0xa
1609 14:47:10.061998 0, 0xFFFF, sum = 0
1610 14:47:10.064829 1, 0xFFFF, sum = 0
1611 14:47:10.064935 2, 0xFFFF, sum = 0
1612 14:47:10.068368 3, 0xFFFF, sum = 0
1613 14:47:10.068439 4, 0xFFFF, sum = 0
1614 14:47:10.071630 5, 0xFFFF, sum = 0
1615 14:47:10.071715 6, 0xFFFF, sum = 0
1616 14:47:10.075075 7, 0xFFFF, sum = 0
1617 14:47:10.075152 8, 0xFFFF, sum = 0
1618 14:47:10.078619 9, 0x0, sum = 1
1619 14:47:10.078693 10, 0x0, sum = 2
1620 14:47:10.081989 11, 0x0, sum = 3
1621 14:47:10.082059 12, 0x0, sum = 4
1622 14:47:10.082118 best_step = 10
1623 14:47:10.082174
1624 14:47:10.085198 ==
1625 14:47:10.085291 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 14:47:10.091875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 14:47:10.091981 ==
1628 14:47:10.092070 RX Vref Scan: 1
1629 14:47:10.092165
1630 14:47:10.095070 Set Vref Range= 32 -> 127
1631 14:47:10.095163
1632 14:47:10.098387 RX Vref 32 -> 127, step: 1
1633 14:47:10.098500
1634 14:47:10.102058 RX Delay -111 -> 252, step: 8
1635 14:47:10.102130
1636 14:47:10.105463 Set Vref, RX VrefLevel [Byte0]: 32
1637 14:47:10.108507 [Byte1]: 32
1638 14:47:10.108603
1639 14:47:10.112039 Set Vref, RX VrefLevel [Byte0]: 33
1640 14:47:10.115335 [Byte1]: 33
1641 14:47:10.115404
1642 14:47:10.118796 Set Vref, RX VrefLevel [Byte0]: 34
1643 14:47:10.122101 [Byte1]: 34
1644 14:47:10.125636
1645 14:47:10.125730 Set Vref, RX VrefLevel [Byte0]: 35
1646 14:47:10.128829 [Byte1]: 35
1647 14:47:10.132928
1648 14:47:10.133040 Set Vref, RX VrefLevel [Byte0]: 36
1649 14:47:10.136123 [Byte1]: 36
1650 14:47:10.140330
1651 14:47:10.140398 Set Vref, RX VrefLevel [Byte0]: 37
1652 14:47:10.143966 [Byte1]: 37
1653 14:47:10.148787
1654 14:47:10.148881 Set Vref, RX VrefLevel [Byte0]: 38
1655 14:47:10.151638 [Byte1]: 38
1656 14:47:10.156043
1657 14:47:10.156115 Set Vref, RX VrefLevel [Byte0]: 39
1658 14:47:10.159224 [Byte1]: 39
1659 14:47:10.163487
1660 14:47:10.163582 Set Vref, RX VrefLevel [Byte0]: 40
1661 14:47:10.166850 [Byte1]: 40
1662 14:47:10.171568
1663 14:47:10.171638 Set Vref, RX VrefLevel [Byte0]: 41
1664 14:47:10.174833 [Byte1]: 41
1665 14:47:10.178889
1666 14:47:10.178963 Set Vref, RX VrefLevel [Byte0]: 42
1667 14:47:10.182515 [Byte1]: 42
1668 14:47:10.186450
1669 14:47:10.186546 Set Vref, RX VrefLevel [Byte0]: 43
1670 14:47:10.189598 [Byte1]: 43
1671 14:47:10.195110
1672 14:47:10.195181 Set Vref, RX VrefLevel [Byte0]: 44
1673 14:47:10.197591 [Byte1]: 44
1674 14:47:10.202323
1675 14:47:10.202398 Set Vref, RX VrefLevel [Byte0]: 45
1676 14:47:10.205086 [Byte1]: 45
1677 14:47:10.209239
1678 14:47:10.209312 Set Vref, RX VrefLevel [Byte0]: 46
1679 14:47:10.215643 [Byte1]: 46
1680 14:47:10.215739
1681 14:47:10.219618 Set Vref, RX VrefLevel [Byte0]: 47
1682 14:47:10.222298 [Byte1]: 47
1683 14:47:10.222369
1684 14:47:10.225685 Set Vref, RX VrefLevel [Byte0]: 48
1685 14:47:10.229471 [Byte1]: 48
1686 14:47:10.229541
1687 14:47:10.232678 Set Vref, RX VrefLevel [Byte0]: 49
1688 14:47:10.236172 [Byte1]: 49
1689 14:47:10.239997
1690 14:47:10.240076 Set Vref, RX VrefLevel [Byte0]: 50
1691 14:47:10.243059 [Byte1]: 50
1692 14:47:10.247723
1693 14:47:10.247803 Set Vref, RX VrefLevel [Byte0]: 51
1694 14:47:10.251063 [Byte1]: 51
1695 14:47:10.255054
1696 14:47:10.255133 Set Vref, RX VrefLevel [Byte0]: 52
1697 14:47:10.258659 [Byte1]: 52
1698 14:47:10.262958
1699 14:47:10.263037 Set Vref, RX VrefLevel [Byte0]: 53
1700 14:47:10.266064 [Byte1]: 53
1701 14:47:10.270792
1702 14:47:10.270871 Set Vref, RX VrefLevel [Byte0]: 54
1703 14:47:10.274407 [Byte1]: 54
1704 14:47:10.278036
1705 14:47:10.278115 Set Vref, RX VrefLevel [Byte0]: 55
1706 14:47:10.281668 [Byte1]: 55
1707 14:47:10.286254
1708 14:47:10.286333 Set Vref, RX VrefLevel [Byte0]: 56
1709 14:47:10.289349 [Byte1]: 56
1710 14:47:10.293509
1711 14:47:10.293588 Set Vref, RX VrefLevel [Byte0]: 57
1712 14:47:10.296851 [Byte1]: 57
1713 14:47:10.300988
1714 14:47:10.301103 Set Vref, RX VrefLevel [Byte0]: 58
1715 14:47:10.304336 [Byte1]: 58
1716 14:47:10.308840
1717 14:47:10.308918 Set Vref, RX VrefLevel [Byte0]: 59
1718 14:47:10.312203 [Byte1]: 59
1719 14:47:10.316440
1720 14:47:10.316511 Set Vref, RX VrefLevel [Byte0]: 60
1721 14:47:10.320788 [Byte1]: 60
1722 14:47:10.325240
1723 14:47:10.325336 Set Vref, RX VrefLevel [Byte0]: 61
1724 14:47:10.327320 [Byte1]: 61
1725 14:47:10.331524
1726 14:47:10.331593 Set Vref, RX VrefLevel [Byte0]: 62
1727 14:47:10.334757 [Byte1]: 62
1728 14:47:10.339314
1729 14:47:10.339383 Set Vref, RX VrefLevel [Byte0]: 63
1730 14:47:10.343379 [Byte1]: 63
1731 14:47:10.347426
1732 14:47:10.347520 Set Vref, RX VrefLevel [Byte0]: 64
1733 14:47:10.351004 [Byte1]: 64
1734 14:47:10.355417
1735 14:47:10.355497 Set Vref, RX VrefLevel [Byte0]: 65
1736 14:47:10.357759 [Byte1]: 65
1737 14:47:10.362325
1738 14:47:10.362407 Set Vref, RX VrefLevel [Byte0]: 66
1739 14:47:10.365816 [Byte1]: 66
1740 14:47:10.369920
1741 14:47:10.369990 Set Vref, RX VrefLevel [Byte0]: 67
1742 14:47:10.373899 [Byte1]: 67
1743 14:47:10.378132
1744 14:47:10.378226 Set Vref, RX VrefLevel [Byte0]: 68
1745 14:47:10.381190 [Byte1]: 68
1746 14:47:10.385355
1747 14:47:10.385428 Set Vref, RX VrefLevel [Byte0]: 69
1748 14:47:10.388286 [Byte1]: 69
1749 14:47:10.392677
1750 14:47:10.392748 Set Vref, RX VrefLevel [Byte0]: 70
1751 14:47:10.395943 [Byte1]: 70
1752 14:47:10.400332
1753 14:47:10.400426 Set Vref, RX VrefLevel [Byte0]: 71
1754 14:47:10.404847 [Byte1]: 71
1755 14:47:10.408581
1756 14:47:10.408654 Set Vref, RX VrefLevel [Byte0]: 72
1757 14:47:10.411466 [Byte1]: 72
1758 14:47:10.415938
1759 14:47:10.416010 Set Vref, RX VrefLevel [Byte0]: 73
1760 14:47:10.419107 [Byte1]: 73
1761 14:47:10.423481
1762 14:47:10.423583 Set Vref, RX VrefLevel [Byte0]: 74
1763 14:47:10.427562 [Byte1]: 74
1764 14:47:10.430975
1765 14:47:10.431068 Set Vref, RX VrefLevel [Byte0]: 75
1766 14:47:10.435737 [Byte1]: 75
1767 14:47:10.439281
1768 14:47:10.439353 Set Vref, RX VrefLevel [Byte0]: 76
1769 14:47:10.441913 [Byte1]: 76
1770 14:47:10.446506
1771 14:47:10.446601 Set Vref, RX VrefLevel [Byte0]: 77
1772 14:47:10.449438 [Byte1]: 77
1773 14:47:10.454377
1774 14:47:10.454471 Set Vref, RX VrefLevel [Byte0]: 78
1775 14:47:10.458200 [Byte1]: 78
1776 14:47:10.461470
1777 14:47:10.461549 Set Vref, RX VrefLevel [Byte0]: 79
1778 14:47:10.464753 [Byte1]: 79
1779 14:47:10.469178
1780 14:47:10.469285 Set Vref, RX VrefLevel [Byte0]: 80
1781 14:47:10.473191 [Byte1]: 80
1782 14:47:10.477496
1783 14:47:10.477597 Final RX Vref Byte 0 = 63 to rank0
1784 14:47:10.480191 Final RX Vref Byte 1 = 60 to rank0
1785 14:47:10.484085 Final RX Vref Byte 0 = 63 to rank1
1786 14:47:10.487193 Final RX Vref Byte 1 = 60 to rank1==
1787 14:47:10.490644 Dram Type= 6, Freq= 0, CH_1, rank 0
1788 14:47:10.496803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 14:47:10.496908 ==
1790 14:47:10.497024 DQS Delay:
1791 14:47:10.497106 DQS0 = 0, DQS1 = 0
1792 14:47:10.500493 DQM Delay:
1793 14:47:10.500572 DQM0 = 83, DQM1 = 74
1794 14:47:10.504541 DQ Delay:
1795 14:47:10.507971 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1796 14:47:10.508050 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1797 14:47:10.510359 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1798 14:47:10.517542 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =80
1799 14:47:10.517621
1800 14:47:10.517683
1801 14:47:10.523684 [DQSOSCAuto] RK0, (LSB)MR18= 0x24fa, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1802 14:47:10.527132 CH1 RK0: MR19=605, MR18=24FA
1803 14:47:10.533561 CH1_RK0: MR19=0x605, MR18=0x24FA, DQSOSC=400, MR23=63, INC=92, DEC=61
1804 14:47:10.533642
1805 14:47:10.537173 ----->DramcWriteLeveling(PI) begin...
1806 14:47:10.537254 ==
1807 14:47:10.540729 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 14:47:10.543690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 14:47:10.543790 ==
1810 14:47:10.548165 Write leveling (Byte 0): 28 => 28
1811 14:47:10.550377 Write leveling (Byte 1): 30 => 30
1812 14:47:10.553681 DramcWriteLeveling(PI) end<-----
1813 14:47:10.553753
1814 14:47:10.553813 ==
1815 14:47:10.557476 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 14:47:10.560765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 14:47:10.560862 ==
1818 14:47:10.564161 [Gating] SW mode calibration
1819 14:47:10.570459 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1820 14:47:10.577972 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1821 14:47:10.580528 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1822 14:47:10.583909 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1823 14:47:10.590616 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1824 14:47:10.594320 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 14:47:10.597527 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 14:47:10.601577 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 14:47:10.607701 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 14:47:10.611384 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1829 14:47:10.614561 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 14:47:10.621105 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 14:47:10.624284 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 14:47:10.627621 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 14:47:10.634556 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 14:47:10.638465 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 14:47:10.640945 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1836 14:47:10.644813 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 14:47:10.651702 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1838 14:47:10.655389 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1839 14:47:10.657919 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1840 14:47:10.664606 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 14:47:10.667823 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 14:47:10.671094 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 14:47:10.678779 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 14:47:10.681230 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 14:47:10.685566 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 14:47:10.691496 0 9 4 | B1->B0 | 2424 2424 | 0 1 | (0 0) (0 0)
1847 14:47:10.694687 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1848 14:47:10.697991 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 14:47:10.704721 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 14:47:10.708450 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1851 14:47:10.711746 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 14:47:10.718139 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 14:47:10.721915 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 14:47:10.725701 0 10 4 | B1->B0 | 3131 2d2d | 0 1 | (0 1) (0 1)
1855 14:47:10.728359 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1856 14:47:10.734899 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 14:47:10.738624 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 14:47:10.741872 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 14:47:10.748755 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 14:47:10.751775 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 14:47:10.755005 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 14:47:10.761905 0 11 4 | B1->B0 | 2424 3333 | 0 0 | (0 0) (1 1)
1863 14:47:10.765429 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1864 14:47:10.768398 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 14:47:10.777230 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 14:47:10.778366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 14:47:10.782245 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 14:47:10.785166 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 14:47:10.792101 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1870 14:47:10.795327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1871 14:47:10.799598 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 14:47:10.805043 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 14:47:10.808405 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 14:47:10.812079 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 14:47:10.818639 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 14:47:10.822282 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 14:47:10.825449 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 14:47:10.832089 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 14:47:10.835904 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 14:47:10.838858 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 14:47:10.845262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 14:47:10.848670 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 14:47:10.852623 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 14:47:10.855827 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 14:47:10.861945 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 14:47:10.865554 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1887 14:47:10.868847 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 14:47:10.872469 Total UI for P1: 0, mck2ui 16
1889 14:47:10.875357 best dqsien dly found for B0: ( 0, 14, 4)
1890 14:47:10.879088 Total UI for P1: 0, mck2ui 16
1891 14:47:10.882564 best dqsien dly found for B1: ( 0, 14, 4)
1892 14:47:10.885532 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1893 14:47:10.889467 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1894 14:47:10.889540
1895 14:47:10.895582 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1896 14:47:10.898899 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1897 14:47:10.898979 [Gating] SW calibration Done
1898 14:47:10.902291 ==
1899 14:47:10.902387 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 14:47:10.909445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 14:47:10.909548 ==
1902 14:47:10.909638 RX Vref Scan: 0
1903 14:47:10.909725
1904 14:47:10.912504 RX Vref 0 -> 0, step: 1
1905 14:47:10.912597
1906 14:47:10.915946 RX Delay -130 -> 252, step: 16
1907 14:47:10.919487 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1908 14:47:10.922944 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1909 14:47:10.926008 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1910 14:47:10.932735 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1911 14:47:10.936401 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1912 14:47:10.939558 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1913 14:47:10.942641 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1914 14:47:10.945866 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1915 14:47:10.952616 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1916 14:47:10.955823 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1917 14:47:10.959190 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1918 14:47:10.962664 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1919 14:47:10.965834 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1920 14:47:10.972842 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1921 14:47:10.975801 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1922 14:47:10.979137 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1923 14:47:10.979217 ==
1924 14:47:10.983080 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 14:47:10.986042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 14:47:10.986142 ==
1927 14:47:10.989753 DQS Delay:
1928 14:47:10.989877 DQS0 = 0, DQS1 = 0
1929 14:47:10.989941 DQM Delay:
1930 14:47:10.992847 DQM0 = 83, DQM1 = 80
1931 14:47:10.992942 DQ Delay:
1932 14:47:10.995892 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1933 14:47:10.999453 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1934 14:47:11.003753 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1935 14:47:11.005949 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1936 14:47:11.006018
1937 14:47:11.006076
1938 14:47:11.006134 ==
1939 14:47:11.009672 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 14:47:11.016034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 14:47:11.016111 ==
1942 14:47:11.016171
1943 14:47:11.016228
1944 14:47:11.016283 TX Vref Scan disable
1945 14:47:11.019621 == TX Byte 0 ==
1946 14:47:11.022968 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1947 14:47:11.026823 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1948 14:47:11.029568 == TX Byte 1 ==
1949 14:47:11.033215 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1950 14:47:11.036488 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1951 14:47:11.040622 ==
1952 14:47:11.043720 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 14:47:11.046250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 14:47:11.046319 ==
1955 14:47:11.059027 TX Vref=22, minBit 15, minWin=26, winSum=444
1956 14:47:11.062344 TX Vref=24, minBit 1, minWin=27, winSum=443
1957 14:47:11.065918 TX Vref=26, minBit 15, minWin=27, winSum=449
1958 14:47:11.069232 TX Vref=28, minBit 11, minWin=27, winSum=453
1959 14:47:11.072219 TX Vref=30, minBit 0, minWin=28, winSum=455
1960 14:47:11.078644 TX Vref=32, minBit 0, minWin=28, winSum=454
1961 14:47:11.082696 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1962 14:47:11.082777
1963 14:47:11.085505 Final TX Range 1 Vref 30
1964 14:47:11.085586
1965 14:47:11.085649 ==
1966 14:47:11.089134 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 14:47:11.092338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 14:47:11.092418 ==
1969 14:47:11.092481
1970 14:47:11.095622
1971 14:47:11.095703 TX Vref Scan disable
1972 14:47:11.099040 == TX Byte 0 ==
1973 14:47:11.102164 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1974 14:47:11.105866 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1975 14:47:11.109367 == TX Byte 1 ==
1976 14:47:11.112641 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1977 14:47:11.115563 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1978 14:47:11.118776
1979 14:47:11.118856 [DATLAT]
1980 14:47:11.118920 Freq=800, CH1 RK1
1981 14:47:11.118979
1982 14:47:11.122553 DATLAT Default: 0xa
1983 14:47:11.122633 0, 0xFFFF, sum = 0
1984 14:47:11.126057 1, 0xFFFF, sum = 0
1985 14:47:11.126139 2, 0xFFFF, sum = 0
1986 14:47:11.129527 3, 0xFFFF, sum = 0
1987 14:47:11.129609 4, 0xFFFF, sum = 0
1988 14:47:11.132656 5, 0xFFFF, sum = 0
1989 14:47:11.132737 6, 0xFFFF, sum = 0
1990 14:47:11.135971 7, 0xFFFF, sum = 0
1991 14:47:11.136052 8, 0xFFFF, sum = 0
1992 14:47:11.138977 9, 0x0, sum = 1
1993 14:47:11.139058 10, 0x0, sum = 2
1994 14:47:11.142457 11, 0x0, sum = 3
1995 14:47:11.142538 12, 0x0, sum = 4
1996 14:47:11.145863 best_step = 10
1997 14:47:11.145953
1998 14:47:11.146017 ==
1999 14:47:11.149314 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 14:47:11.152761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 14:47:11.152841 ==
2002 14:47:11.155988 RX Vref Scan: 0
2003 14:47:11.156068
2004 14:47:11.156132 RX Vref 0 -> 0, step: 1
2005 14:47:11.156191
2006 14:47:11.159709 RX Delay -95 -> 252, step: 8
2007 14:47:11.166155 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2008 14:47:11.169257 iDelay=201, Bit 1, Center 72 (-47 ~ 192) 240
2009 14:47:11.172861 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2010 14:47:11.176388 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2011 14:47:11.180000 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2012 14:47:11.183354 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2013 14:47:11.189979 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2014 14:47:11.193444 iDelay=201, Bit 7, Center 76 (-39 ~ 192) 232
2015 14:47:11.196502 iDelay=201, Bit 8, Center 68 (-47 ~ 184) 232
2016 14:47:11.200161 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2017 14:47:11.203689 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2018 14:47:11.210060 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2019 14:47:11.213306 iDelay=201, Bit 12, Center 84 (-31 ~ 200) 232
2020 14:47:11.216408 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2021 14:47:11.219697 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2022 14:47:11.223229 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2023 14:47:11.223310 ==
2024 14:47:11.226688 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 14:47:11.233160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 14:47:11.233241 ==
2027 14:47:11.233304 DQS Delay:
2028 14:47:11.236662 DQS0 = 0, DQS1 = 0
2029 14:47:11.236741 DQM Delay:
2030 14:47:11.236805 DQM0 = 79, DQM1 = 76
2031 14:47:11.240065 DQ Delay:
2032 14:47:11.243554 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2033 14:47:11.246877 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
2034 14:47:11.249990 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2035 14:47:11.253378 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2036 14:47:11.253458
2037 14:47:11.253521
2038 14:47:11.260487 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2039 14:47:11.264377 CH1 RK1: MR19=606, MR18=1F2A
2040 14:47:11.270411 CH1_RK1: MR19=0x606, MR18=0x1F2A, DQSOSC=399, MR23=63, INC=92, DEC=61
2041 14:47:11.273661 [RxdqsGatingPostProcess] freq 800
2042 14:47:11.276712 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 14:47:11.280255 Pre-setting of DQS Precalculation
2044 14:47:11.286954 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 14:47:11.294380 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 14:47:11.300670 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 14:47:11.300753
2048 14:47:11.300816
2049 14:47:11.304145 [Calibration Summary] 1600 Mbps
2050 14:47:11.304213 CH 0, Rank 0
2051 14:47:11.307397 SW Impedance : PASS
2052 14:47:11.307466 DUTY Scan : NO K
2053 14:47:11.310969 ZQ Calibration : PASS
2054 14:47:11.314105 Jitter Meter : NO K
2055 14:47:11.314179 CBT Training : PASS
2056 14:47:11.317178 Write leveling : PASS
2057 14:47:11.320296 RX DQS gating : PASS
2058 14:47:11.320365 RX DQ/DQS(RDDQC) : PASS
2059 14:47:11.325281 TX DQ/DQS : PASS
2060 14:47:11.326971 RX DATLAT : PASS
2061 14:47:11.327036 RX DQ/DQS(Engine): PASS
2062 14:47:11.330855 TX OE : NO K
2063 14:47:11.330924 All Pass.
2064 14:47:11.330980
2065 14:47:11.334089 CH 0, Rank 1
2066 14:47:11.334153 SW Impedance : PASS
2067 14:47:11.337278 DUTY Scan : NO K
2068 14:47:11.340416 ZQ Calibration : PASS
2069 14:47:11.340486 Jitter Meter : NO K
2070 14:47:11.343688 CBT Training : PASS
2071 14:47:11.343753 Write leveling : PASS
2072 14:47:11.347201 RX DQS gating : PASS
2073 14:47:11.351027 RX DQ/DQS(RDDQC) : PASS
2074 14:47:11.351102 TX DQ/DQS : PASS
2075 14:47:11.353861 RX DATLAT : PASS
2076 14:47:11.357402 RX DQ/DQS(Engine): PASS
2077 14:47:11.357472 TX OE : NO K
2078 14:47:11.360650 All Pass.
2079 14:47:11.360717
2080 14:47:11.360777 CH 1, Rank 0
2081 14:47:11.364067 SW Impedance : PASS
2082 14:47:11.364131 DUTY Scan : NO K
2083 14:47:11.367593 ZQ Calibration : PASS
2084 14:47:11.370766 Jitter Meter : NO K
2085 14:47:11.370838 CBT Training : PASS
2086 14:47:11.374009 Write leveling : PASS
2087 14:47:11.374074 RX DQS gating : PASS
2088 14:47:11.377724 RX DQ/DQS(RDDQC) : PASS
2089 14:47:11.380960 TX DQ/DQS : PASS
2090 14:47:11.381073 RX DATLAT : PASS
2091 14:47:11.384589 RX DQ/DQS(Engine): PASS
2092 14:47:11.387631 TX OE : NO K
2093 14:47:11.387702 All Pass.
2094 14:47:11.387761
2095 14:47:11.387820 CH 1, Rank 1
2096 14:47:11.391152 SW Impedance : PASS
2097 14:47:11.394317 DUTY Scan : NO K
2098 14:47:11.394382 ZQ Calibration : PASS
2099 14:47:11.397766 Jitter Meter : NO K
2100 14:47:11.401465 CBT Training : PASS
2101 14:47:11.401538 Write leveling : PASS
2102 14:47:11.404587 RX DQS gating : PASS
2103 14:47:11.408150 RX DQ/DQS(RDDQC) : PASS
2104 14:47:11.408215 TX DQ/DQS : PASS
2105 14:47:11.410947 RX DATLAT : PASS
2106 14:47:11.411010 RX DQ/DQS(Engine): PASS
2107 14:47:11.414750 TX OE : NO K
2108 14:47:11.414817 All Pass.
2109 14:47:11.414876
2110 14:47:11.417956 DramC Write-DBI off
2111 14:47:11.422003 PER_BANK_REFRESH: Hybrid Mode
2112 14:47:11.422068 TX_TRACKING: ON
2113 14:47:11.424927 [GetDramInforAfterCalByMRR] Vendor 6.
2114 14:47:11.429265 [GetDramInforAfterCalByMRR] Revision 606.
2115 14:47:11.431283 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 14:47:11.435127 MR0 0x3b3b
2117 14:47:11.435191 MR8 0x5151
2118 14:47:11.438777 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 14:47:11.438840
2120 14:47:11.438898 MR0 0x3b3b
2121 14:47:11.441620 MR8 0x5151
2122 14:47:11.444934 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 14:47:11.445011
2124 14:47:11.455186 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 14:47:11.458259 [FAST_K] Save calibration result to emmc
2126 14:47:11.461565 [FAST_K] Save calibration result to emmc
2127 14:47:11.461636 dram_init: config_dvfs: 1
2128 14:47:11.468144 dramc_set_vcore_voltage set vcore to 662500
2129 14:47:11.468214 Read voltage for 1200, 2
2130 14:47:11.471632 Vio18 = 0
2131 14:47:11.471699 Vcore = 662500
2132 14:47:11.471756 Vdram = 0
2133 14:47:11.471811 Vddq = 0
2134 14:47:11.474864 Vmddr = 0
2135 14:47:11.478332 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 14:47:11.485459 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 14:47:11.485539 MEM_TYPE=3, freq_sel=15
2138 14:47:11.488320 sv_algorithm_assistance_LP4_1600
2139 14:47:11.494918 ============ PULL DRAM RESETB DOWN ============
2140 14:47:11.499064 ========== PULL DRAM RESETB DOWN end =========
2141 14:47:11.502007 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 14:47:11.505864 ===================================
2143 14:47:11.508386 LPDDR4 DRAM CONFIGURATION
2144 14:47:11.512273 ===================================
2145 14:47:11.515342 EX_ROW_EN[0] = 0x0
2146 14:47:11.515409 EX_ROW_EN[1] = 0x0
2147 14:47:11.518809 LP4Y_EN = 0x0
2148 14:47:11.518874 WORK_FSP = 0x0
2149 14:47:11.521886 WL = 0x4
2150 14:47:11.521954 RL = 0x4
2151 14:47:11.525162 BL = 0x2
2152 14:47:11.525226 RPST = 0x0
2153 14:47:11.528375 RD_PRE = 0x0
2154 14:47:11.528439 WR_PRE = 0x1
2155 14:47:11.532044 WR_PST = 0x0
2156 14:47:11.532108 DBI_WR = 0x0
2157 14:47:11.535643 DBI_RD = 0x0
2158 14:47:11.535710 OTF = 0x1
2159 14:47:11.538887 ===================================
2160 14:47:11.541943 ===================================
2161 14:47:11.545224 ANA top config
2162 14:47:11.549269 ===================================
2163 14:47:11.549370 DLL_ASYNC_EN = 0
2164 14:47:11.552273 ALL_SLAVE_EN = 0
2165 14:47:11.555308 NEW_RANK_MODE = 1
2166 14:47:11.558558 DLL_IDLE_MODE = 1
2167 14:47:11.558627 LP45_APHY_COMB_EN = 1
2168 14:47:11.562776 TX_ODT_DIS = 1
2169 14:47:11.565570 NEW_8X_MODE = 1
2170 14:47:11.568874 ===================================
2171 14:47:11.572492 ===================================
2172 14:47:11.575894 data_rate = 2400
2173 14:47:11.579071 CKR = 1
2174 14:47:11.582150 DQ_P2S_RATIO = 8
2175 14:47:11.582224 ===================================
2176 14:47:11.585792 CA_P2S_RATIO = 8
2177 14:47:11.589366 DQ_CA_OPEN = 0
2178 14:47:11.592502 DQ_SEMI_OPEN = 0
2179 14:47:11.595795 CA_SEMI_OPEN = 0
2180 14:47:11.599560 CA_FULL_RATE = 0
2181 14:47:11.599627 DQ_CKDIV4_EN = 0
2182 14:47:11.602176 CA_CKDIV4_EN = 0
2183 14:47:11.605597 CA_PREDIV_EN = 0
2184 14:47:11.608830 PH8_DLY = 17
2185 14:47:11.612309 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 14:47:11.615701 DQ_AAMCK_DIV = 4
2187 14:47:11.615769 CA_AAMCK_DIV = 4
2188 14:47:11.618767 CA_ADMCK_DIV = 4
2189 14:47:11.622408 DQ_TRACK_CA_EN = 0
2190 14:47:11.626212 CA_PICK = 1200
2191 14:47:11.629689 CA_MCKIO = 1200
2192 14:47:11.632775 MCKIO_SEMI = 0
2193 14:47:11.635484 PLL_FREQ = 2366
2194 14:47:11.639652 DQ_UI_PI_RATIO = 32
2195 14:47:11.639717 CA_UI_PI_RATIO = 0
2196 14:47:11.642200 ===================================
2197 14:47:11.645454 ===================================
2198 14:47:11.648942 memory_type:LPDDR4
2199 14:47:11.652272 GP_NUM : 10
2200 14:47:11.652341 SRAM_EN : 1
2201 14:47:11.655762 MD32_EN : 0
2202 14:47:11.659272 ===================================
2203 14:47:11.662307 [ANA_INIT] >>>>>>>>>>>>>>
2204 14:47:11.662373 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 14:47:11.666351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 14:47:11.669218 ===================================
2207 14:47:11.672563 data_rate = 2400,PCW = 0X5b00
2208 14:47:11.675707 ===================================
2209 14:47:11.679751 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 14:47:11.686231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 14:47:11.689079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 14:47:11.695941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 14:47:11.699429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 14:47:11.702876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 14:47:11.706574 [ANA_INIT] flow start
2216 14:47:11.706646 [ANA_INIT] PLL >>>>>>>>
2217 14:47:11.709110 [ANA_INIT] PLL <<<<<<<<
2218 14:47:11.712837 [ANA_INIT] MIDPI >>>>>>>>
2219 14:47:11.712930 [ANA_INIT] MIDPI <<<<<<<<
2220 14:47:11.716056 [ANA_INIT] DLL >>>>>>>>
2221 14:47:11.719132 [ANA_INIT] DLL <<<<<<<<
2222 14:47:11.719203 [ANA_INIT] flow end
2223 14:47:11.722551 ============ LP4 DIFF to SE enter ============
2224 14:47:11.729123 ============ LP4 DIFF to SE exit ============
2225 14:47:11.729197 [ANA_INIT] <<<<<<<<<<<<<
2226 14:47:11.732854 [Flow] Enable top DCM control >>>>>
2227 14:47:11.736764 [Flow] Enable top DCM control <<<<<
2228 14:47:11.739272 Enable DLL master slave shuffle
2229 14:47:11.746375 ==============================================================
2230 14:47:11.746445 Gating Mode config
2231 14:47:11.753404 ==============================================================
2232 14:47:11.756177 Config description:
2233 14:47:11.762608 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 14:47:11.769439 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 14:47:11.776186 SELPH_MODE 0: By rank 1: By Phase
2236 14:47:11.783298 ==============================================================
2237 14:47:11.783401 GAT_TRACK_EN = 1
2238 14:47:11.785949 RX_GATING_MODE = 2
2239 14:47:11.789388 RX_GATING_TRACK_MODE = 2
2240 14:47:11.793586 SELPH_MODE = 1
2241 14:47:11.796569 PICG_EARLY_EN = 1
2242 14:47:11.799967 VALID_LAT_VALUE = 1
2243 14:47:11.806667 ==============================================================
2244 14:47:11.809880 Enter into Gating configuration >>>>
2245 14:47:11.812983 Exit from Gating configuration <<<<
2246 14:47:11.816843 Enter into DVFS_PRE_config >>>>>
2247 14:47:11.826487 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 14:47:11.829661 Exit from DVFS_PRE_config <<<<<
2249 14:47:11.833114 Enter into PICG configuration >>>>
2250 14:47:11.836690 Exit from PICG configuration <<<<
2251 14:47:11.836759 [RX_INPUT] configuration >>>>>
2252 14:47:11.839899 [RX_INPUT] configuration <<<<<
2253 14:47:11.846498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 14:47:11.849957 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 14:47:11.856875 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 14:47:11.863817 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 14:47:11.869783 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 14:47:11.876754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 14:47:11.880212 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 14:47:11.883361 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 14:47:11.886592 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 14:47:11.893564 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 14:47:11.896882 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 14:47:11.900197 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 14:47:11.903652 ===================================
2266 14:47:11.907340 LPDDR4 DRAM CONFIGURATION
2267 14:47:11.910575 ===================================
2268 14:47:11.910654 EX_ROW_EN[0] = 0x0
2269 14:47:11.913495 EX_ROW_EN[1] = 0x0
2270 14:47:11.917679 LP4Y_EN = 0x0
2271 14:47:11.917759 WORK_FSP = 0x0
2272 14:47:11.920240 WL = 0x4
2273 14:47:11.920319 RL = 0x4
2274 14:47:11.923772 BL = 0x2
2275 14:47:11.923852 RPST = 0x0
2276 14:47:11.927361 RD_PRE = 0x0
2277 14:47:11.927441 WR_PRE = 0x1
2278 14:47:11.930732 WR_PST = 0x0
2279 14:47:11.930812 DBI_WR = 0x0
2280 14:47:11.934182 DBI_RD = 0x0
2281 14:47:11.934263 OTF = 0x1
2282 14:47:11.937622 ===================================
2283 14:47:11.941161 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 14:47:11.947425 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 14:47:11.951126 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 14:47:11.953970 ===================================
2287 14:47:11.957728 LPDDR4 DRAM CONFIGURATION
2288 14:47:11.961264 ===================================
2289 14:47:11.961344 EX_ROW_EN[0] = 0x10
2290 14:47:11.964001 EX_ROW_EN[1] = 0x0
2291 14:47:11.964081 LP4Y_EN = 0x0
2292 14:47:11.967664 WORK_FSP = 0x0
2293 14:47:11.967743 WL = 0x4
2294 14:47:11.970502 RL = 0x4
2295 14:47:11.970580 BL = 0x2
2296 14:47:11.974138 RPST = 0x0
2297 14:47:11.974218 RD_PRE = 0x0
2298 14:47:11.977467 WR_PRE = 0x1
2299 14:47:11.977546 WR_PST = 0x0
2300 14:47:11.981243 DBI_WR = 0x0
2301 14:47:11.981322 DBI_RD = 0x0
2302 14:47:11.984030 OTF = 0x1
2303 14:47:11.987706 ===================================
2304 14:47:11.994767 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 14:47:11.994847 ==
2306 14:47:11.998219 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 14:47:12.000971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 14:47:12.001072 ==
2309 14:47:12.004098 [Duty_Offset_Calibration]
2310 14:47:12.004177 B0:2 B1:-1 CA:1
2311 14:47:12.004239
2312 14:47:12.008092 [DutyScan_Calibration_Flow] k_type=0
2313 14:47:12.017943
2314 14:47:12.018024 ==CLK 0==
2315 14:47:12.020914 Final CLK duty delay cell = -4
2316 14:47:12.024282 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2317 14:47:12.027588 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2318 14:47:12.031565 [-4] AVG Duty = 4953%(X100)
2319 14:47:12.031645
2320 14:47:12.034545 CH0 CLK Duty spec in!! Max-Min= 156%
2321 14:47:12.037500 [DutyScan_Calibration_Flow] ====Done====
2322 14:47:12.037580
2323 14:47:12.040877 [DutyScan_Calibration_Flow] k_type=1
2324 14:47:12.055886
2325 14:47:12.055995 ==DQS 0 ==
2326 14:47:12.059389 Final DQS duty delay cell = -4
2327 14:47:12.062771 [-4] MAX Duty = 5000%(X100), DQS PI = 44
2328 14:47:12.066021 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2329 14:47:12.068904 [-4] AVG Duty = 4938%(X100)
2330 14:47:12.069045
2331 14:47:12.069111 ==DQS 1 ==
2332 14:47:12.072648 Final DQS duty delay cell = -4
2333 14:47:12.076511 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2334 14:47:12.079380 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2335 14:47:12.082486 [-4] AVG Duty = 5062%(X100)
2336 14:47:12.082567
2337 14:47:12.086048 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2338 14:47:12.086128
2339 14:47:12.088830 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2340 14:47:12.092477 [DutyScan_Calibration_Flow] ====Done====
2341 14:47:12.092556
2342 14:47:12.095977 [DutyScan_Calibration_Flow] k_type=3
2343 14:47:12.112586
2344 14:47:12.112666 ==DQM 0 ==
2345 14:47:12.116563 Final DQM duty delay cell = 0
2346 14:47:12.119882 [0] MAX Duty = 4969%(X100), DQS PI = 0
2347 14:47:12.123115 [0] MIN Duty = 4907%(X100), DQS PI = 2
2348 14:47:12.123195 [0] AVG Duty = 4938%(X100)
2349 14:47:12.123257
2350 14:47:12.126238 ==DQM 1 ==
2351 14:47:12.129539 Final DQM duty delay cell = 0
2352 14:47:12.133285 [0] MAX Duty = 5156%(X100), DQS PI = 62
2353 14:47:12.136578 [0] MIN Duty = 4969%(X100), DQS PI = 58
2354 14:47:12.136658 [0] AVG Duty = 5062%(X100)
2355 14:47:12.136720
2356 14:47:12.139737 CH0 DQM 0 Duty spec in!! Max-Min= 62%
2357 14:47:12.139817
2358 14:47:12.146145 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2359 14:47:12.149826 [DutyScan_Calibration_Flow] ====Done====
2360 14:47:12.149906
2361 14:47:12.152799 [DutyScan_Calibration_Flow] k_type=2
2362 14:47:12.168089
2363 14:47:12.168172 ==DQ 0 ==
2364 14:47:12.171919 Final DQ duty delay cell = -4
2365 14:47:12.175700 [-4] MAX Duty = 5031%(X100), DQS PI = 46
2366 14:47:12.178357 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2367 14:47:12.182220 [-4] AVG Duty = 4937%(X100)
2368 14:47:12.182301
2369 14:47:12.182364 ==DQ 1 ==
2370 14:47:12.184938 Final DQ duty delay cell = 0
2371 14:47:12.188703 [0] MAX Duty = 5031%(X100), DQS PI = 26
2372 14:47:12.191590 [0] MIN Duty = 4907%(X100), DQS PI = 46
2373 14:47:12.191671 [0] AVG Duty = 4969%(X100)
2374 14:47:12.195100
2375 14:47:12.198511 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2376 14:47:12.198591
2377 14:47:12.201948 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2378 14:47:12.205306 [DutyScan_Calibration_Flow] ====Done====
2379 14:47:12.205387 ==
2380 14:47:12.208385 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 14:47:12.211689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 14:47:12.211770 ==
2383 14:47:12.215422 [Duty_Offset_Calibration]
2384 14:47:12.215502 B0:1 B1:1 CA:2
2385 14:47:12.215565
2386 14:47:12.219284 [DutyScan_Calibration_Flow] k_type=0
2387 14:47:12.228561
2388 14:47:12.228641 ==CLK 0==
2389 14:47:12.231695 Final CLK duty delay cell = 0
2390 14:47:12.234910 [0] MAX Duty = 5156%(X100), DQS PI = 24
2391 14:47:12.238190 [0] MIN Duty = 4969%(X100), DQS PI = 38
2392 14:47:12.241597 [0] AVG Duty = 5062%(X100)
2393 14:47:12.241677
2394 14:47:12.245121 CH1 CLK Duty spec in!! Max-Min= 187%
2395 14:47:12.248793 [DutyScan_Calibration_Flow] ====Done====
2396 14:47:12.248873
2397 14:47:12.251751 [DutyScan_Calibration_Flow] k_type=1
2398 14:47:12.267696
2399 14:47:12.267777 ==DQS 0 ==
2400 14:47:12.271584 Final DQS duty delay cell = 0
2401 14:47:12.274670 [0] MAX Duty = 5031%(X100), DQS PI = 18
2402 14:47:12.278242 [0] MIN Duty = 4813%(X100), DQS PI = 50
2403 14:47:12.278322 [0] AVG Duty = 4922%(X100)
2404 14:47:12.281664
2405 14:47:12.281743 ==DQS 1 ==
2406 14:47:12.284919 Final DQS duty delay cell = 0
2407 14:47:12.287747 [0] MAX Duty = 5031%(X100), DQS PI = 36
2408 14:47:12.291449 [0] MIN Duty = 4906%(X100), DQS PI = 14
2409 14:47:12.291529 [0] AVG Duty = 4968%(X100)
2410 14:47:12.295046
2411 14:47:12.298639 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2412 14:47:12.298720
2413 14:47:12.301407 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2414 14:47:12.304759 [DutyScan_Calibration_Flow] ====Done====
2415 14:47:12.304839
2416 14:47:12.308014 [DutyScan_Calibration_Flow] k_type=3
2417 14:47:12.324638
2418 14:47:12.324718 ==DQM 0 ==
2419 14:47:12.327928 Final DQM duty delay cell = 0
2420 14:47:12.331353 [0] MAX Duty = 5093%(X100), DQS PI = 18
2421 14:47:12.334475 [0] MIN Duty = 4875%(X100), DQS PI = 50
2422 14:47:12.337690 [0] AVG Duty = 4984%(X100)
2423 14:47:12.337770
2424 14:47:12.337834 ==DQM 1 ==
2425 14:47:12.341341 Final DQM duty delay cell = 0
2426 14:47:12.344260 [0] MAX Duty = 5156%(X100), DQS PI = 62
2427 14:47:12.347677 [0] MIN Duty = 4938%(X100), DQS PI = 22
2428 14:47:12.347758 [0] AVG Duty = 5047%(X100)
2429 14:47:12.351047
2430 14:47:12.354614 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2431 14:47:12.354694
2432 14:47:12.358044 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2433 14:47:12.361214 [DutyScan_Calibration_Flow] ====Done====
2434 14:47:12.361319
2435 14:47:12.364736 [DutyScan_Calibration_Flow] k_type=2
2436 14:47:12.380952
2437 14:47:12.381097 ==DQ 0 ==
2438 14:47:12.384665 Final DQ duty delay cell = 0
2439 14:47:12.388547 [0] MAX Duty = 5093%(X100), DQS PI = 18
2440 14:47:12.392534 [0] MIN Duty = 4938%(X100), DQS PI = 60
2441 14:47:12.392606 [0] AVG Duty = 5015%(X100)
2442 14:47:12.392667
2443 14:47:12.394642 ==DQ 1 ==
2444 14:47:12.398014 Final DQ duty delay cell = 0
2445 14:47:12.401295 [0] MAX Duty = 5093%(X100), DQS PI = 26
2446 14:47:12.404444 [0] MIN Duty = 5031%(X100), DQS PI = 2
2447 14:47:12.404516 [0] AVG Duty = 5062%(X100)
2448 14:47:12.404576
2449 14:47:12.408263 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2450 14:47:12.408329
2451 14:47:12.411394 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2452 14:47:12.414935 [DutyScan_Calibration_Flow] ====Done====
2453 14:47:12.420323 nWR fixed to 30
2454 14:47:12.423395 [ModeRegInit_LP4] CH0 RK0
2455 14:47:12.423464 [ModeRegInit_LP4] CH0 RK1
2456 14:47:12.426765 [ModeRegInit_LP4] CH1 RK0
2457 14:47:12.430539 [ModeRegInit_LP4] CH1 RK1
2458 14:47:12.430606 match AC timing 7
2459 14:47:12.436888 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 14:47:12.439929 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 14:47:12.443075 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 14:47:12.450136 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 14:47:12.453323 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 14:47:12.453393 ==
2465 14:47:12.456684 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 14:47:12.460437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 14:47:12.460508 ==
2468 14:47:12.467047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 14:47:12.473829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 14:47:12.481260 [CA 0] Center 40 (10~71) winsize 62
2471 14:47:12.484155 [CA 1] Center 39 (9~70) winsize 62
2472 14:47:12.487682 [CA 2] Center 36 (6~67) winsize 62
2473 14:47:12.491098 [CA 3] Center 36 (6~66) winsize 61
2474 14:47:12.495422 [CA 4] Center 34 (4~65) winsize 62
2475 14:47:12.497960 [CA 5] Center 34 (4~64) winsize 61
2476 14:47:12.498034
2477 14:47:12.500841 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 14:47:12.500911
2479 14:47:12.505603 [CATrainingPosCal] consider 1 rank data
2480 14:47:12.507430 u2DelayCellTimex100 = 270/100 ps
2481 14:47:12.511077 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2482 14:47:12.514200 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2483 14:47:12.521102 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2484 14:47:12.524816 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2485 14:47:12.527952 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2486 14:47:12.531398 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2487 14:47:12.531474
2488 14:47:12.534578 CA PerBit enable=1, Macro0, CA PI delay=34
2489 14:47:12.534646
2490 14:47:12.537781 [CBTSetCACLKResult] CA Dly = 34
2491 14:47:12.537852 CS Dly: 7 (0~38)
2492 14:47:12.537912 ==
2493 14:47:12.541236 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 14:47:12.548249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 14:47:12.548321 ==
2496 14:47:12.551136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 14:47:12.557733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2498 14:47:12.566627 [CA 0] Center 39 (9~70) winsize 62
2499 14:47:12.570217 [CA 1] Center 40 (10~70) winsize 61
2500 14:47:12.573352 [CA 2] Center 36 (6~67) winsize 62
2501 14:47:12.576913 [CA 3] Center 35 (5~66) winsize 62
2502 14:47:12.580525 [CA 4] Center 34 (4~65) winsize 62
2503 14:47:12.583899 [CA 5] Center 34 (4~64) winsize 61
2504 14:47:12.583972
2505 14:47:12.587083 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2506 14:47:12.587153
2507 14:47:12.590160 [CATrainingPosCal] consider 2 rank data
2508 14:47:12.593457 u2DelayCellTimex100 = 270/100 ps
2509 14:47:12.597110 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2510 14:47:12.600684 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2511 14:47:12.607387 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2512 14:47:12.610225 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2513 14:47:12.613928 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2514 14:47:12.616947 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2515 14:47:12.617067
2516 14:47:12.620604 CA PerBit enable=1, Macro0, CA PI delay=34
2517 14:47:12.620678
2518 14:47:12.623893 [CBTSetCACLKResult] CA Dly = 34
2519 14:47:12.623961 CS Dly: 8 (0~41)
2520 14:47:12.624019
2521 14:47:12.627447 ----->DramcWriteLeveling(PI) begin...
2522 14:47:12.627519 ==
2523 14:47:12.630584 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 14:47:12.637083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 14:47:12.637167 ==
2526 14:47:12.640424 Write leveling (Byte 0): 30 => 30
2527 14:47:12.644470 Write leveling (Byte 1): 30 => 30
2528 14:47:12.644536 DramcWriteLeveling(PI) end<-----
2529 14:47:12.647668
2530 14:47:12.647739 ==
2531 14:47:12.650790 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 14:47:12.654174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 14:47:12.654241 ==
2534 14:47:12.657389 [Gating] SW mode calibration
2535 14:47:12.664372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 14:47:12.667270 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 14:47:12.674360 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 14:47:12.677811 0 15 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2539 14:47:12.681459 0 15 8 | B1->B0 | 3332 3434 | 1 1 | (1 1) (1 1)
2540 14:47:12.687771 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 14:47:12.691030 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 14:47:12.694176 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 14:47:12.697685 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 14:47:12.704088 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 14:47:12.707384 1 0 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2546 14:47:12.711786 1 0 4 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
2547 14:47:12.717758 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 14:47:12.721197 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 14:47:12.724908 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 14:47:12.731614 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 14:47:12.734832 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 14:47:12.737539 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 14:47:12.744555 1 1 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2554 14:47:12.747637 1 1 4 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2555 14:47:12.751217 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 14:47:12.758127 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 14:47:12.761385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 14:47:12.764951 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 14:47:12.767874 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 14:47:12.774729 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 14:47:12.778676 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2562 14:47:12.781800 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2563 14:47:12.788178 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 14:47:12.791759 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 14:47:12.795100 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 14:47:12.801572 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 14:47:12.805099 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 14:47:12.808431 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 14:47:12.814650 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 14:47:12.818585 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 14:47:12.822072 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 14:47:12.828181 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 14:47:12.831412 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 14:47:12.834989 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 14:47:12.838464 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 14:47:12.845170 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 14:47:12.848969 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2578 14:47:12.851726 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2579 14:47:12.855721 Total UI for P1: 0, mck2ui 16
2580 14:47:12.858347 best dqsien dly found for B0: ( 1, 4, 0)
2581 14:47:12.865212 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 14:47:12.865321 Total UI for P1: 0, mck2ui 16
2583 14:47:12.871801 best dqsien dly found for B1: ( 1, 4, 2)
2584 14:47:12.875130 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2585 14:47:12.878501 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2586 14:47:12.878581
2587 14:47:12.881857 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2588 14:47:12.885924 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2589 14:47:12.888476 [Gating] SW calibration Done
2590 14:47:12.888556 ==
2591 14:47:12.891795 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 14:47:12.895372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 14:47:12.895453 ==
2594 14:47:12.898468 RX Vref Scan: 0
2595 14:47:12.898548
2596 14:47:12.898612 RX Vref 0 -> 0, step: 1
2597 14:47:12.898671
2598 14:47:12.902423 RX Delay -40 -> 252, step: 8
2599 14:47:12.905079 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2600 14:47:12.908396 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2601 14:47:12.915325 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2602 14:47:12.918476 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2603 14:47:12.921838 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2604 14:47:12.925403 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2605 14:47:12.929059 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2606 14:47:12.935507 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2607 14:47:12.938836 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2608 14:47:12.942417 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2609 14:47:12.945583 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2610 14:47:12.948753 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2611 14:47:12.955433 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2612 14:47:12.958589 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2613 14:47:12.962163 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2614 14:47:12.965496 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2615 14:47:12.965577 ==
2616 14:47:12.969174 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 14:47:12.972296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 14:47:12.976078 ==
2619 14:47:12.976158 DQS Delay:
2620 14:47:12.976221 DQS0 = 0, DQS1 = 0
2621 14:47:12.978966 DQM Delay:
2622 14:47:12.979046 DQM0 = 115, DQM1 = 107
2623 14:47:12.982237 DQ Delay:
2624 14:47:12.985606 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2625 14:47:12.989102 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2626 14:47:12.992207 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2627 14:47:12.995446 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2628 14:47:12.995526
2629 14:47:12.995589
2630 14:47:12.995648 ==
2631 14:47:12.998896 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 14:47:13.002244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 14:47:13.002325 ==
2634 14:47:13.002389
2635 14:47:13.002448
2636 14:47:13.005945 TX Vref Scan disable
2637 14:47:13.008825 == TX Byte 0 ==
2638 14:47:13.012574 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2639 14:47:13.016109 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2640 14:47:13.019635 == TX Byte 1 ==
2641 14:47:13.022800 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2642 14:47:13.026095 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2643 14:47:13.026175 ==
2644 14:47:13.029086 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 14:47:13.032936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 14:47:13.033066 ==
2647 14:47:13.045743 TX Vref=22, minBit 7, minWin=24, winSum=417
2648 14:47:13.048744 TX Vref=24, minBit 1, minWin=25, winSum=419
2649 14:47:13.052500 TX Vref=26, minBit 12, minWin=25, winSum=425
2650 14:47:13.056005 TX Vref=28, minBit 0, minWin=26, winSum=429
2651 14:47:13.058797 TX Vref=30, minBit 1, minWin=26, winSum=433
2652 14:47:13.062088 TX Vref=32, minBit 3, minWin=26, winSum=428
2653 14:47:13.068805 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
2654 14:47:13.068886
2655 14:47:13.072528 Final TX Range 1 Vref 30
2656 14:47:13.072609
2657 14:47:13.072673 ==
2658 14:47:13.076470 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 14:47:13.078815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 14:47:13.078896 ==
2661 14:47:13.078961
2662 14:47:13.082328
2663 14:47:13.082407 TX Vref Scan disable
2664 14:47:13.085706 == TX Byte 0 ==
2665 14:47:13.088723 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2666 14:47:13.092367 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2667 14:47:13.095233 == TX Byte 1 ==
2668 14:47:13.098964 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2669 14:47:13.101979 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2670 14:47:13.102059
2671 14:47:13.105471 [DATLAT]
2672 14:47:13.105551 Freq=1200, CH0 RK0
2673 14:47:13.105615
2674 14:47:13.108699 DATLAT Default: 0xd
2675 14:47:13.108804 0, 0xFFFF, sum = 0
2676 14:47:13.112592 1, 0xFFFF, sum = 0
2677 14:47:13.112673 2, 0xFFFF, sum = 0
2678 14:47:13.115879 3, 0xFFFF, sum = 0
2679 14:47:13.115961 4, 0xFFFF, sum = 0
2680 14:47:13.119183 5, 0xFFFF, sum = 0
2681 14:47:13.119265 6, 0xFFFF, sum = 0
2682 14:47:13.122634 7, 0xFFFF, sum = 0
2683 14:47:13.122716 8, 0xFFFF, sum = 0
2684 14:47:13.125770 9, 0xFFFF, sum = 0
2685 14:47:13.129248 10, 0xFFFF, sum = 0
2686 14:47:13.129329 11, 0xFFFF, sum = 0
2687 14:47:13.132404 12, 0x0, sum = 1
2688 14:47:13.132485 13, 0x0, sum = 2
2689 14:47:13.132549 14, 0x0, sum = 3
2690 14:47:13.136361 15, 0x0, sum = 4
2691 14:47:13.136442 best_step = 13
2692 14:47:13.136506
2693 14:47:13.136564 ==
2694 14:47:13.139050 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 14:47:13.146149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 14:47:13.146230 ==
2697 14:47:13.146297 RX Vref Scan: 1
2698 14:47:13.146361
2699 14:47:13.150359 Set Vref Range= 32 -> 127
2700 14:47:13.150440
2701 14:47:13.152354 RX Vref 32 -> 127, step: 1
2702 14:47:13.152435
2703 14:47:13.156139 RX Delay -21 -> 252, step: 4
2704 14:47:13.156220
2705 14:47:13.159195 Set Vref, RX VrefLevel [Byte0]: 32
2706 14:47:13.159275 [Byte1]: 32
2707 14:47:13.163788
2708 14:47:13.163867 Set Vref, RX VrefLevel [Byte0]: 33
2709 14:47:13.167555 [Byte1]: 33
2710 14:47:13.172045
2711 14:47:13.172124 Set Vref, RX VrefLevel [Byte0]: 34
2712 14:47:13.175103 [Byte1]: 34
2713 14:47:13.179998
2714 14:47:13.180093 Set Vref, RX VrefLevel [Byte0]: 35
2715 14:47:13.183020 [Byte1]: 35
2716 14:47:13.187880
2717 14:47:13.187969 Set Vref, RX VrefLevel [Byte0]: 36
2718 14:47:13.190938 [Byte1]: 36
2719 14:47:13.195945
2720 14:47:13.196025 Set Vref, RX VrefLevel [Byte0]: 37
2721 14:47:13.198807 [Byte1]: 37
2722 14:47:13.203906
2723 14:47:13.203986 Set Vref, RX VrefLevel [Byte0]: 38
2724 14:47:13.206883 [Byte1]: 38
2725 14:47:13.211171
2726 14:47:13.211251 Set Vref, RX VrefLevel [Byte0]: 39
2727 14:47:13.214407 [Byte1]: 39
2728 14:47:13.219736
2729 14:47:13.219816 Set Vref, RX VrefLevel [Byte0]: 40
2730 14:47:13.222514 [Byte1]: 40
2731 14:47:13.227645
2732 14:47:13.227725 Set Vref, RX VrefLevel [Byte0]: 41
2733 14:47:13.230741 [Byte1]: 41
2734 14:47:13.235358
2735 14:47:13.235438 Set Vref, RX VrefLevel [Byte0]: 42
2736 14:47:13.238244 [Byte1]: 42
2737 14:47:13.243808
2738 14:47:13.243888 Set Vref, RX VrefLevel [Byte0]: 43
2739 14:47:13.246620 [Byte1]: 43
2740 14:47:13.251074
2741 14:47:13.251153 Set Vref, RX VrefLevel [Byte0]: 44
2742 14:47:13.254782 [Byte1]: 44
2743 14:47:13.259395
2744 14:47:13.259475 Set Vref, RX VrefLevel [Byte0]: 45
2745 14:47:13.262529 [Byte1]: 45
2746 14:47:13.267425
2747 14:47:13.267505 Set Vref, RX VrefLevel [Byte0]: 46
2748 14:47:13.270372 [Byte1]: 46
2749 14:47:13.274659
2750 14:47:13.274738 Set Vref, RX VrefLevel [Byte0]: 47
2751 14:47:13.277878 [Byte1]: 47
2752 14:47:13.282985
2753 14:47:13.283065 Set Vref, RX VrefLevel [Byte0]: 48
2754 14:47:13.285968 [Byte1]: 48
2755 14:47:13.290701
2756 14:47:13.290780 Set Vref, RX VrefLevel [Byte0]: 49
2757 14:47:13.294111 [Byte1]: 49
2758 14:47:13.301010
2759 14:47:13.301090 Set Vref, RX VrefLevel [Byte0]: 50
2760 14:47:13.301824 [Byte1]: 50
2761 14:47:13.306653
2762 14:47:13.306732 Set Vref, RX VrefLevel [Byte0]: 51
2763 14:47:13.309819 [Byte1]: 51
2764 14:47:13.314568
2765 14:47:13.314648 Set Vref, RX VrefLevel [Byte0]: 52
2766 14:47:13.317399 [Byte1]: 52
2767 14:47:13.322058
2768 14:47:13.322141 Set Vref, RX VrefLevel [Byte0]: 53
2769 14:47:13.325592 [Byte1]: 53
2770 14:47:13.329991
2771 14:47:13.330071 Set Vref, RX VrefLevel [Byte0]: 54
2772 14:47:13.334095 [Byte1]: 54
2773 14:47:13.338063
2774 14:47:13.338143 Set Vref, RX VrefLevel [Byte0]: 55
2775 14:47:13.341474 [Byte1]: 55
2776 14:47:13.346110
2777 14:47:13.346190 Set Vref, RX VrefLevel [Byte0]: 56
2778 14:47:13.349888 [Byte1]: 56
2779 14:47:13.353973
2780 14:47:13.354062 Set Vref, RX VrefLevel [Byte0]: 57
2781 14:47:13.357168 [Byte1]: 57
2782 14:47:13.361864
2783 14:47:13.361944 Set Vref, RX VrefLevel [Byte0]: 58
2784 14:47:13.365535 [Byte1]: 58
2785 14:47:13.370500
2786 14:47:13.370580 Set Vref, RX VrefLevel [Byte0]: 59
2787 14:47:13.372970 [Byte1]: 59
2788 14:47:13.379089
2789 14:47:13.379168 Set Vref, RX VrefLevel [Byte0]: 60
2790 14:47:13.381147 [Byte1]: 60
2791 14:47:13.385502
2792 14:47:13.385573 Set Vref, RX VrefLevel [Byte0]: 61
2793 14:47:13.389476 [Byte1]: 61
2794 14:47:13.393423
2795 14:47:13.393492 Set Vref, RX VrefLevel [Byte0]: 62
2796 14:47:13.398384 [Byte1]: 62
2797 14:47:13.401356
2798 14:47:13.401420 Set Vref, RX VrefLevel [Byte0]: 63
2799 14:47:13.405354 [Byte1]: 63
2800 14:47:13.409634
2801 14:47:13.409704 Set Vref, RX VrefLevel [Byte0]: 64
2802 14:47:13.412928 [Byte1]: 64
2803 14:47:13.417389
2804 14:47:13.417455 Set Vref, RX VrefLevel [Byte0]: 65
2805 14:47:13.420857 [Byte1]: 65
2806 14:47:13.426111
2807 14:47:13.426197 Set Vref, RX VrefLevel [Byte0]: 66
2808 14:47:13.428732 [Byte1]: 66
2809 14:47:13.433335
2810 14:47:13.433405 Set Vref, RX VrefLevel [Byte0]: 67
2811 14:47:13.436400 [Byte1]: 67
2812 14:47:13.441582
2813 14:47:13.441649 Set Vref, RX VrefLevel [Byte0]: 68
2814 14:47:13.444337 [Byte1]: 68
2815 14:47:13.448853
2816 14:47:13.448965 Set Vref, RX VrefLevel [Byte0]: 69
2817 14:47:13.452624 [Byte1]: 69
2818 14:47:13.456857
2819 14:47:13.456963 Final RX Vref Byte 0 = 52 to rank0
2820 14:47:13.460428 Final RX Vref Byte 1 = 51 to rank0
2821 14:47:13.463834 Final RX Vref Byte 0 = 52 to rank1
2822 14:47:13.467067 Final RX Vref Byte 1 = 51 to rank1==
2823 14:47:13.470751 Dram Type= 6, Freq= 0, CH_0, rank 0
2824 14:47:13.473786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 14:47:13.477970 ==
2826 14:47:13.478050 DQS Delay:
2827 14:47:13.478114 DQS0 = 0, DQS1 = 0
2828 14:47:13.481475 DQM Delay:
2829 14:47:13.481555 DQM0 = 115, DQM1 = 104
2830 14:47:13.483947 DQ Delay:
2831 14:47:13.487190 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2832 14:47:13.491687 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2833 14:47:13.493746 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2834 14:47:13.497207 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =114
2835 14:47:13.497287
2836 14:47:13.497351
2837 14:47:13.504286 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2838 14:47:13.507191 CH0 RK0: MR19=303, MR18=FCEC
2839 14:47:13.514111 CH0_RK0: MR19=0x303, MR18=0xFCEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2840 14:47:13.514193
2841 14:47:13.517436 ----->DramcWriteLeveling(PI) begin...
2842 14:47:13.517517 ==
2843 14:47:13.520796 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 14:47:13.524210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 14:47:13.524294 ==
2846 14:47:13.527594 Write leveling (Byte 0): 32 => 32
2847 14:47:13.531426 Write leveling (Byte 1): 27 => 27
2848 14:47:13.534320 DramcWriteLeveling(PI) end<-----
2849 14:47:13.534449
2850 14:47:13.534527 ==
2851 14:47:13.538352 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 14:47:13.540884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 14:47:13.541026 ==
2854 14:47:13.544014 [Gating] SW mode calibration
2855 14:47:13.550984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2856 14:47:13.557409 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2857 14:47:13.560857 0 15 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
2858 14:47:13.567487 0 15 4 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 0)
2859 14:47:13.571369 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 14:47:13.574464 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 14:47:13.577860 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 14:47:13.584639 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 14:47:13.588067 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 14:47:13.591537 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
2865 14:47:13.597681 1 0 0 | B1->B0 | 3030 2a2a | 1 0 | (1 0) (0 0)
2866 14:47:13.601546 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 14:47:13.604855 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 14:47:13.611137 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 14:47:13.614919 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 14:47:13.618464 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 14:47:13.625212 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2872 14:47:13.628517 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2873 14:47:13.631995 1 1 0 | B1->B0 | 3636 4141 | 1 0 | (0 0) (0 0)
2874 14:47:13.634928 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 14:47:13.641654 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 14:47:13.645437 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 14:47:13.648155 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 14:47:13.656572 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 14:47:13.658656 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 14:47:13.661778 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2881 14:47:13.668685 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2882 14:47:13.671852 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2883 14:47:13.676126 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 14:47:13.681877 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 14:47:13.685154 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 14:47:13.689175 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 14:47:13.692078 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 14:47:13.699978 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 14:47:13.702038 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 14:47:13.705357 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 14:47:13.712904 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 14:47:13.715887 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 14:47:13.719676 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 14:47:13.725583 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 14:47:13.728893 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 14:47:13.732293 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2897 14:47:13.739246 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2898 14:47:13.739327 Total UI for P1: 0, mck2ui 16
2899 14:47:13.742761 best dqsien dly found for B0: ( 1, 3, 28)
2900 14:47:13.749091 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 14:47:13.753390 Total UI for P1: 0, mck2ui 16
2902 14:47:13.756426 best dqsien dly found for B1: ( 1, 4, 0)
2903 14:47:13.759548 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2904 14:47:13.762266 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2905 14:47:13.762346
2906 14:47:13.765733 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2907 14:47:13.769625 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2908 14:47:13.772407 [Gating] SW calibration Done
2909 14:47:13.772487 ==
2910 14:47:13.775947 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 14:47:13.779252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 14:47:13.779333 ==
2913 14:47:13.782732 RX Vref Scan: 0
2914 14:47:13.782812
2915 14:47:13.782874 RX Vref 0 -> 0, step: 1
2916 14:47:13.782933
2917 14:47:13.785792 RX Delay -40 -> 252, step: 8
2918 14:47:13.789725 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2919 14:47:13.796114 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2920 14:47:13.799721 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2921 14:47:13.802841 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2922 14:47:13.805976 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2923 14:47:13.809274 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2924 14:47:13.816498 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2925 14:47:13.821456 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2926 14:47:13.822749 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2927 14:47:13.826045 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2928 14:47:13.829252 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2929 14:47:13.832805 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2930 14:47:13.839707 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2931 14:47:13.843798 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2932 14:47:13.846776 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2933 14:47:13.850071 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2934 14:47:13.850151 ==
2935 14:47:13.853266 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 14:47:13.860317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 14:47:13.860399 ==
2938 14:47:13.860463 DQS Delay:
2939 14:47:13.860522 DQS0 = 0, DQS1 = 0
2940 14:47:13.862991 DQM Delay:
2941 14:47:13.863071 DQM0 = 115, DQM1 = 106
2942 14:47:13.866685 DQ Delay:
2943 14:47:13.870010 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2944 14:47:13.872957 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2945 14:47:13.876812 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2946 14:47:13.879773 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2947 14:47:13.879853
2948 14:47:13.879916
2949 14:47:13.879975 ==
2950 14:47:13.883662 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 14:47:13.886492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 14:47:13.886572 ==
2953 14:47:13.886635
2954 14:47:13.886694
2955 14:47:13.889700 TX Vref Scan disable
2956 14:47:13.894221 == TX Byte 0 ==
2957 14:47:13.896425 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2958 14:47:13.900394 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2959 14:47:13.903563 == TX Byte 1 ==
2960 14:47:13.906792 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2961 14:47:13.910133 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2962 14:47:13.910213 ==
2963 14:47:13.913459 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 14:47:13.916823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 14:47:13.920069 ==
2966 14:47:13.930877 TX Vref=22, minBit 1, minWin=26, winSum=425
2967 14:47:13.934194 TX Vref=24, minBit 1, minWin=25, winSum=430
2968 14:47:13.937439 TX Vref=26, minBit 3, minWin=26, winSum=433
2969 14:47:13.941708 TX Vref=28, minBit 3, minWin=26, winSum=436
2970 14:47:13.943864 TX Vref=30, minBit 14, minWin=26, winSum=436
2971 14:47:13.947634 TX Vref=32, minBit 0, minWin=27, winSum=436
2972 14:47:13.954346 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 32
2973 14:47:13.954427
2974 14:47:13.957926 Final TX Range 1 Vref 32
2975 14:47:13.958006
2976 14:47:13.958070 ==
2977 14:47:13.960696 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 14:47:13.963961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 14:47:13.964042 ==
2980 14:47:13.964106
2981 14:47:13.964165
2982 14:47:13.967672 TX Vref Scan disable
2983 14:47:13.971146 == TX Byte 0 ==
2984 14:47:13.974361 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2985 14:47:13.977444 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2986 14:47:13.980912 == TX Byte 1 ==
2987 14:47:13.983979 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2988 14:47:13.988126 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2989 14:47:13.988207
2990 14:47:13.990981 [DATLAT]
2991 14:47:13.991060 Freq=1200, CH0 RK1
2992 14:47:13.991123
2993 14:47:13.994325 DATLAT Default: 0xd
2994 14:47:13.994405 0, 0xFFFF, sum = 0
2995 14:47:13.997632 1, 0xFFFF, sum = 0
2996 14:47:13.997713 2, 0xFFFF, sum = 0
2997 14:47:14.001113 3, 0xFFFF, sum = 0
2998 14:47:14.001195 4, 0xFFFF, sum = 0
2999 14:47:14.004517 5, 0xFFFF, sum = 0
3000 14:47:14.004599 6, 0xFFFF, sum = 0
3001 14:47:14.007471 7, 0xFFFF, sum = 0
3002 14:47:14.007553 8, 0xFFFF, sum = 0
3003 14:47:14.010921 9, 0xFFFF, sum = 0
3004 14:47:14.011003 10, 0xFFFF, sum = 0
3005 14:47:14.014640 11, 0xFFFF, sum = 0
3006 14:47:14.014721 12, 0x0, sum = 1
3007 14:47:14.017570 13, 0x0, sum = 2
3008 14:47:14.017651 14, 0x0, sum = 3
3009 14:47:14.021110 15, 0x0, sum = 4
3010 14:47:14.021191 best_step = 13
3011 14:47:14.021255
3012 14:47:14.021314 ==
3013 14:47:14.024963 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 14:47:14.031008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 14:47:14.031089 ==
3016 14:47:14.031152 RX Vref Scan: 0
3017 14:47:14.031211
3018 14:47:14.034676 RX Vref 0 -> 0, step: 1
3019 14:47:14.034757
3020 14:47:14.038099 RX Delay -21 -> 252, step: 4
3021 14:47:14.041190 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3022 14:47:14.044408 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3023 14:47:14.051015 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3024 14:47:14.055947 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3025 14:47:14.058297 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3026 14:47:14.061990 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3027 14:47:14.064895 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3028 14:47:14.068036 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3029 14:47:14.074887 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3030 14:47:14.077979 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3031 14:47:14.081834 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3032 14:47:14.085522 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3033 14:47:14.088275 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3034 14:47:14.092008 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3035 14:47:14.098179 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3036 14:47:14.101894 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3037 14:47:14.101961 ==
3038 14:47:14.105724 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 14:47:14.108379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 14:47:14.108444 ==
3041 14:47:14.111547 DQS Delay:
3042 14:47:14.111614 DQS0 = 0, DQS1 = 0
3043 14:47:14.111671 DQM Delay:
3044 14:47:14.115229 DQM0 = 114, DQM1 = 104
3045 14:47:14.115299 DQ Delay:
3046 14:47:14.119036 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3047 14:47:14.122154 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =120
3048 14:47:14.125299 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3049 14:47:14.131928 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114
3050 14:47:14.132001
3051 14:47:14.132059
3052 14:47:14.138791 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3053 14:47:14.141611 CH0 RK1: MR19=403, MR18=4F6
3054 14:47:14.145548 CH0_RK1: MR19=0x403, MR18=0x4F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3055 14:47:14.148872 [RxdqsGatingPostProcess] freq 1200
3056 14:47:14.155524 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 14:47:14.159654 best DQS0 dly(2T, 0.5T) = (0, 12)
3058 14:47:14.162935 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 14:47:14.165644 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3060 14:47:14.168834 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 14:47:14.172188 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 14:47:14.175958 best DQS1 dly(2T, 0.5T) = (0, 12)
3063 14:47:14.179255 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 14:47:14.182524 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3065 14:47:14.182622 Pre-setting of DQS Precalculation
3066 14:47:14.189223 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 14:47:14.189297 ==
3068 14:47:14.193066 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 14:47:14.195903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 14:47:14.195970 ==
3071 14:47:14.202680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 14:47:14.209399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3073 14:47:14.216562 [CA 0] Center 38 (9~68) winsize 60
3074 14:47:14.220061 [CA 1] Center 38 (8~68) winsize 61
3075 14:47:14.223481 [CA 2] Center 35 (5~65) winsize 61
3076 14:47:14.226238 [CA 3] Center 34 (4~65) winsize 62
3077 14:47:14.229573 [CA 4] Center 34 (4~65) winsize 62
3078 14:47:14.232842 [CA 5] Center 34 (4~64) winsize 61
3079 14:47:14.232923
3080 14:47:14.236199 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3081 14:47:14.236268
3082 14:47:14.239489 [CATrainingPosCal] consider 1 rank data
3083 14:47:14.242892 u2DelayCellTimex100 = 270/100 ps
3084 14:47:14.246457 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3085 14:47:14.250118 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3086 14:47:14.253228 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3087 14:47:14.260611 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3088 14:47:14.263368 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3089 14:47:14.266262 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3090 14:47:14.266328
3091 14:47:14.269758 CA PerBit enable=1, Macro0, CA PI delay=34
3092 14:47:14.269827
3093 14:47:14.272890 [CBTSetCACLKResult] CA Dly = 34
3094 14:47:14.272957 CS Dly: 6 (0~37)
3095 14:47:14.273051 ==
3096 14:47:14.276666 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 14:47:14.283389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 14:47:14.283465 ==
3099 14:47:14.286985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 14:47:14.294109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3101 14:47:14.301679 [CA 0] Center 38 (8~68) winsize 61
3102 14:47:14.304868 [CA 1] Center 38 (9~68) winsize 60
3103 14:47:14.308470 [CA 2] Center 34 (4~65) winsize 62
3104 14:47:14.311780 [CA 3] Center 34 (4~65) winsize 62
3105 14:47:14.315314 [CA 4] Center 34 (4~65) winsize 62
3106 14:47:14.318533 [CA 5] Center 33 (3~64) winsize 62
3107 14:47:14.318602
3108 14:47:14.322590 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3109 14:47:14.322665
3110 14:47:14.325421 [CATrainingPosCal] consider 2 rank data
3111 14:47:14.328698 u2DelayCellTimex100 = 270/100 ps
3112 14:47:14.332104 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3113 14:47:14.334903 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3114 14:47:14.341741 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 14:47:14.345049 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3116 14:47:14.348552 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3117 14:47:14.353039 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3118 14:47:14.353115
3119 14:47:14.355234 CA PerBit enable=1, Macro0, CA PI delay=34
3120 14:47:14.355305
3121 14:47:14.358442 [CBTSetCACLKResult] CA Dly = 34
3122 14:47:14.358507 CS Dly: 7 (0~40)
3123 14:47:14.358565
3124 14:47:14.361782 ----->DramcWriteLeveling(PI) begin...
3125 14:47:14.361853 ==
3126 14:47:14.365236 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 14:47:14.372693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 14:47:14.372766 ==
3129 14:47:14.376836 Write leveling (Byte 0): 27 => 27
3130 14:47:14.378761 Write leveling (Byte 1): 29 => 29
3131 14:47:14.378826 DramcWriteLeveling(PI) end<-----
3132 14:47:14.378887
3133 14:47:14.382814 ==
3134 14:47:14.386510 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 14:47:14.389545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 14:47:14.389611 ==
3137 14:47:14.392150 [Gating] SW mode calibration
3138 14:47:14.398754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 14:47:14.402890 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 14:47:14.409123 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3141 14:47:14.412226 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 14:47:14.415616 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 14:47:14.422374 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3144 14:47:14.425558 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3145 14:47:14.428911 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 14:47:14.436031 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3147 14:47:14.438874 0 15 28 | B1->B0 | 3232 3434 | 1 1 | (1 1) (0 1)
3148 14:47:14.442412 1 0 0 | B1->B0 | 2424 2d2d | 0 0 | (1 0) (1 0)
3149 14:47:14.446091 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3150 14:47:14.453326 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 14:47:14.455893 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 14:47:14.459367 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 14:47:14.465951 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 14:47:14.469209 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 14:47:14.473000 1 0 28 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
3156 14:47:14.479787 1 1 0 | B1->B0 | 3f3f 3131 | 0 0 | (0 0) (0 0)
3157 14:47:14.483126 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 14:47:14.485743 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 14:47:14.492362 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 14:47:14.495734 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 14:47:14.499390 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 14:47:14.505785 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 14:47:14.509137 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3164 14:47:14.513078 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3165 14:47:14.519074 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 14:47:14.522653 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 14:47:14.525747 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 14:47:14.529908 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 14:47:14.536647 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 14:47:14.539007 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 14:47:14.543428 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 14:47:14.548928 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 14:47:14.552607 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 14:47:14.555906 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 14:47:14.562634 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 14:47:14.566350 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 14:47:14.568972 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 14:47:14.576442 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 14:47:14.579419 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3180 14:47:14.582745 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3181 14:47:14.585881 Total UI for P1: 0, mck2ui 16
3182 14:47:14.589123 best dqsien dly found for B1: ( 1, 3, 28)
3183 14:47:14.592884 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 14:47:14.595898 Total UI for P1: 0, mck2ui 16
3185 14:47:14.599528 best dqsien dly found for B0: ( 1, 3, 30)
3186 14:47:14.602711 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3187 14:47:14.609692 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3188 14:47:14.609768
3189 14:47:14.612909 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3190 14:47:14.616022 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3191 14:47:14.619533 [Gating] SW calibration Done
3192 14:47:14.619598 ==
3193 14:47:14.622632 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 14:47:14.625902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 14:47:14.625971 ==
3196 14:47:14.626028 RX Vref Scan: 0
3197 14:47:14.626082
3198 14:47:14.630064 RX Vref 0 -> 0, step: 1
3199 14:47:14.630131
3200 14:47:14.633307 RX Delay -40 -> 252, step: 8
3201 14:47:14.636118 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3202 14:47:14.639316 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3203 14:47:14.646547 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3204 14:47:14.649583 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3205 14:47:14.653209 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3206 14:47:14.656300 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3207 14:47:14.659764 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3208 14:47:14.664000 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3209 14:47:14.669990 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3210 14:47:14.672925 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3211 14:47:14.676368 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3212 14:47:14.680216 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3213 14:47:14.682977 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3214 14:47:14.690140 iDelay=200, Bit 13, Center 119 (56 ~ 183) 128
3215 14:47:14.693809 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3216 14:47:14.696473 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3217 14:47:14.696580 ==
3218 14:47:14.700350 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 14:47:14.703888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 14:47:14.703963 ==
3221 14:47:14.706579 DQS Delay:
3222 14:47:14.706655 DQS0 = 0, DQS1 = 0
3223 14:47:14.709647 DQM Delay:
3224 14:47:14.709752 DQM0 = 115, DQM1 = 109
3225 14:47:14.709840 DQ Delay:
3226 14:47:14.713450 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3227 14:47:14.720575 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111
3228 14:47:14.723321 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3229 14:47:14.726402 DQ12 =123, DQ13 =119, DQ14 =111, DQ15 =111
3230 14:47:14.726502
3231 14:47:14.726595
3232 14:47:14.726676 ==
3233 14:47:14.729879 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 14:47:14.733642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 14:47:14.733712 ==
3236 14:47:14.733772
3237 14:47:14.733828
3238 14:47:14.736665 TX Vref Scan disable
3239 14:47:14.736757 == TX Byte 0 ==
3240 14:47:14.743639 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3241 14:47:14.747107 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3242 14:47:14.747179 == TX Byte 1 ==
3243 14:47:14.753829 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3244 14:47:14.757080 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3245 14:47:14.757184 ==
3246 14:47:14.760666 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 14:47:14.763411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 14:47:14.763485 ==
3249 14:47:14.776329 TX Vref=22, minBit 1, minWin=25, winSum=414
3250 14:47:14.780010 TX Vref=24, minBit 1, minWin=25, winSum=416
3251 14:47:14.782904 TX Vref=26, minBit 0, minWin=26, winSum=424
3252 14:47:14.786487 TX Vref=28, minBit 1, minWin=26, winSum=430
3253 14:47:14.790115 TX Vref=30, minBit 1, minWin=26, winSum=433
3254 14:47:14.793072 TX Vref=32, minBit 3, minWin=26, winSum=431
3255 14:47:14.799976 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
3256 14:47:14.800076
3257 14:47:14.803069 Final TX Range 1 Vref 30
3258 14:47:14.803164
3259 14:47:14.803254 ==
3260 14:47:14.806438 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 14:47:14.809593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 14:47:14.809696 ==
3263 14:47:14.809797
3264 14:47:14.809884
3265 14:47:14.813178 TX Vref Scan disable
3266 14:47:14.816498 == TX Byte 0 ==
3267 14:47:14.819922 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3268 14:47:14.823471 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3269 14:47:14.826484 == TX Byte 1 ==
3270 14:47:14.829803 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3271 14:47:14.834538 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3272 14:47:14.834637
3273 14:47:14.836723 [DATLAT]
3274 14:47:14.836793 Freq=1200, CH1 RK0
3275 14:47:14.836854
3276 14:47:14.839988 DATLAT Default: 0xd
3277 14:47:14.840082 0, 0xFFFF, sum = 0
3278 14:47:14.843584 1, 0xFFFF, sum = 0
3279 14:47:14.843678 2, 0xFFFF, sum = 0
3280 14:47:14.847110 3, 0xFFFF, sum = 0
3281 14:47:14.847178 4, 0xFFFF, sum = 0
3282 14:47:14.850209 5, 0xFFFF, sum = 0
3283 14:47:14.850280 6, 0xFFFF, sum = 0
3284 14:47:14.853981 7, 0xFFFF, sum = 0
3285 14:47:14.854053 8, 0xFFFF, sum = 0
3286 14:47:14.856984 9, 0xFFFF, sum = 0
3287 14:47:14.857052 10, 0xFFFF, sum = 0
3288 14:47:14.860405 11, 0xFFFF, sum = 0
3289 14:47:14.860469 12, 0x0, sum = 1
3290 14:47:14.863939 13, 0x0, sum = 2
3291 14:47:14.864011 14, 0x0, sum = 3
3292 14:47:14.868213 15, 0x0, sum = 4
3293 14:47:14.868280 best_step = 13
3294 14:47:14.868338
3295 14:47:14.868399 ==
3296 14:47:14.870263 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 14:47:14.873933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 14:47:14.876623 ==
3299 14:47:14.876686 RX Vref Scan: 1
3300 14:47:14.876745
3301 14:47:14.880694 Set Vref Range= 32 -> 127
3302 14:47:14.880756
3303 14:47:14.883768 RX Vref 32 -> 127, step: 1
3304 14:47:14.883835
3305 14:47:14.883892 RX Delay -21 -> 252, step: 4
3306 14:47:14.883947
3307 14:47:14.887385 Set Vref, RX VrefLevel [Byte0]: 32
3308 14:47:14.890130 [Byte1]: 32
3309 14:47:14.894106
3310 14:47:14.894177 Set Vref, RX VrefLevel [Byte0]: 33
3311 14:47:14.897394 [Byte1]: 33
3312 14:47:14.902627
3313 14:47:14.902696 Set Vref, RX VrefLevel [Byte0]: 34
3314 14:47:14.905352 [Byte1]: 34
3315 14:47:14.910077
3316 14:47:14.910153 Set Vref, RX VrefLevel [Byte0]: 35
3317 14:47:14.913221 [Byte1]: 35
3318 14:47:14.918054
3319 14:47:14.918128 Set Vref, RX VrefLevel [Byte0]: 36
3320 14:47:14.921606 [Byte1]: 36
3321 14:47:14.926244
3322 14:47:14.926311 Set Vref, RX VrefLevel [Byte0]: 37
3323 14:47:14.929150 [Byte1]: 37
3324 14:47:14.934469
3325 14:47:14.934545 Set Vref, RX VrefLevel [Byte0]: 38
3326 14:47:14.937516 [Byte1]: 38
3327 14:47:14.943907
3328 14:47:14.943979 Set Vref, RX VrefLevel [Byte0]: 39
3329 14:47:14.946395 [Byte1]: 39
3330 14:47:14.950510
3331 14:47:14.950581 Set Vref, RX VrefLevel [Byte0]: 40
3332 14:47:14.953275 [Byte1]: 40
3333 14:47:14.958527
3334 14:47:14.958599 Set Vref, RX VrefLevel [Byte0]: 41
3335 14:47:14.960930 [Byte1]: 41
3336 14:47:14.965348
3337 14:47:14.965420 Set Vref, RX VrefLevel [Byte0]: 42
3338 14:47:14.969556 [Byte1]: 42
3339 14:47:14.973734
3340 14:47:14.973801 Set Vref, RX VrefLevel [Byte0]: 43
3341 14:47:14.977086 [Byte1]: 43
3342 14:47:14.981604
3343 14:47:14.981697 Set Vref, RX VrefLevel [Byte0]: 44
3344 14:47:14.984786 [Byte1]: 44
3345 14:47:14.989335
3346 14:47:14.989400 Set Vref, RX VrefLevel [Byte0]: 45
3347 14:47:14.992697 [Byte1]: 45
3348 14:47:14.997320
3349 14:47:14.997394 Set Vref, RX VrefLevel [Byte0]: 46
3350 14:47:15.001151 [Byte1]: 46
3351 14:47:15.005582
3352 14:47:15.005649 Set Vref, RX VrefLevel [Byte0]: 47
3353 14:47:15.008312 [Byte1]: 47
3354 14:47:15.013156
3355 14:47:15.013225 Set Vref, RX VrefLevel [Byte0]: 48
3356 14:47:15.016626 [Byte1]: 48
3357 14:47:15.021158
3358 14:47:15.021231 Set Vref, RX VrefLevel [Byte0]: 49
3359 14:47:15.024096 [Byte1]: 49
3360 14:47:15.029315
3361 14:47:15.029384 Set Vref, RX VrefLevel [Byte0]: 50
3362 14:47:15.032334 [Byte1]: 50
3363 14:47:15.037066
3364 14:47:15.037133 Set Vref, RX VrefLevel [Byte0]: 51
3365 14:47:15.039958 [Byte1]: 51
3366 14:47:15.046168
3367 14:47:15.046234 Set Vref, RX VrefLevel [Byte0]: 52
3368 14:47:15.048388 [Byte1]: 52
3369 14:47:15.052825
3370 14:47:15.052893 Set Vref, RX VrefLevel [Byte0]: 53
3371 14:47:15.056298 [Byte1]: 53
3372 14:47:15.060753
3373 14:47:15.060847 Set Vref, RX VrefLevel [Byte0]: 54
3374 14:47:15.064044 [Byte1]: 54
3375 14:47:15.068957
3376 14:47:15.069093 Set Vref, RX VrefLevel [Byte0]: 55
3377 14:47:15.072611 [Byte1]: 55
3378 14:47:15.076579
3379 14:47:15.076654 Set Vref, RX VrefLevel [Byte0]: 56
3380 14:47:15.079877 [Byte1]: 56
3381 14:47:15.084917
3382 14:47:15.085047 Set Vref, RX VrefLevel [Byte0]: 57
3383 14:47:15.088218 [Byte1]: 57
3384 14:47:15.092721
3385 14:47:15.092796 Set Vref, RX VrefLevel [Byte0]: 58
3386 14:47:15.096381 [Byte1]: 58
3387 14:47:15.100560
3388 14:47:15.100632 Set Vref, RX VrefLevel [Byte0]: 59
3389 14:47:15.103857 [Byte1]: 59
3390 14:47:15.108050
3391 14:47:15.108151 Set Vref, RX VrefLevel [Byte0]: 60
3392 14:47:15.111702 [Byte1]: 60
3393 14:47:15.116108
3394 14:47:15.116178 Set Vref, RX VrefLevel [Byte0]: 61
3395 14:47:15.119446 [Byte1]: 61
3396 14:47:15.123954
3397 14:47:15.124023 Set Vref, RX VrefLevel [Byte0]: 62
3398 14:47:15.127049 [Byte1]: 62
3399 14:47:15.131834
3400 14:47:15.131928 Set Vref, RX VrefLevel [Byte0]: 63
3401 14:47:15.135236 [Byte1]: 63
3402 14:47:15.139924
3403 14:47:15.140006 Set Vref, RX VrefLevel [Byte0]: 64
3404 14:47:15.143289 [Byte1]: 64
3405 14:47:15.147499
3406 14:47:15.147567 Set Vref, RX VrefLevel [Byte0]: 65
3407 14:47:15.151202 [Byte1]: 65
3408 14:47:15.156406
3409 14:47:15.156474 Set Vref, RX VrefLevel [Byte0]: 66
3410 14:47:15.159185 [Byte1]: 66
3411 14:47:15.163509
3412 14:47:15.163576 Set Vref, RX VrefLevel [Byte0]: 67
3413 14:47:15.166719 [Byte1]: 67
3414 14:47:15.171695
3415 14:47:15.171760 Set Vref, RX VrefLevel [Byte0]: 68
3416 14:47:15.174814 [Byte1]: 68
3417 14:47:15.179215
3418 14:47:15.179314 Set Vref, RX VrefLevel [Byte0]: 69
3419 14:47:15.182760 [Byte1]: 69
3420 14:47:15.188213
3421 14:47:15.188317 Set Vref, RX VrefLevel [Byte0]: 70
3422 14:47:15.191637 [Byte1]: 70
3423 14:47:15.195303
3424 14:47:15.195398 Final RX Vref Byte 0 = 56 to rank0
3425 14:47:15.198734 Final RX Vref Byte 1 = 45 to rank0
3426 14:47:15.202087 Final RX Vref Byte 0 = 56 to rank1
3427 14:47:15.205412 Final RX Vref Byte 1 = 45 to rank1==
3428 14:47:15.208852 Dram Type= 6, Freq= 0, CH_1, rank 0
3429 14:47:15.212045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 14:47:15.215288 ==
3431 14:47:15.215365 DQS Delay:
3432 14:47:15.215435 DQS0 = 0, DQS1 = 0
3433 14:47:15.218975 DQM Delay:
3434 14:47:15.219049 DQM0 = 115, DQM1 = 107
3435 14:47:15.222235 DQ Delay:
3436 14:47:15.225911 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3437 14:47:15.228830 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3438 14:47:15.232081 DQ8 =94, DQ9 =94, DQ10 =110, DQ11 =102
3439 14:47:15.235679 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3440 14:47:15.235753
3441 14:47:15.235813
3442 14:47:15.242674 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3443 14:47:15.245421 CH1 RK0: MR19=303, MR18=FEE3
3444 14:47:15.252310 CH1_RK0: MR19=0x303, MR18=0xFEE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3445 14:47:15.252389
3446 14:47:15.255940 ----->DramcWriteLeveling(PI) begin...
3447 14:47:15.256040 ==
3448 14:47:15.259174 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 14:47:15.262320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 14:47:15.262393 ==
3451 14:47:15.265635 Write leveling (Byte 0): 27 => 27
3452 14:47:15.269190 Write leveling (Byte 1): 28 => 28
3453 14:47:15.272469 DramcWriteLeveling(PI) end<-----
3454 14:47:15.272540
3455 14:47:15.272600 ==
3456 14:47:15.276068 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 14:47:15.279403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 14:47:15.279498 ==
3459 14:47:15.282831 [Gating] SW mode calibration
3460 14:47:15.289558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3461 14:47:15.296100 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3462 14:47:15.299232 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 14:47:15.307342 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 14:47:15.309312 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 14:47:15.313354 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 14:47:15.317140 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3467 14:47:15.322932 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
3468 14:47:15.326525 0 15 24 | B1->B0 | 3333 2929 | 1 1 | (1 1) (1 0)
3469 14:47:15.329395 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3470 14:47:15.336849 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 14:47:15.339692 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 14:47:15.343854 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 14:47:15.349306 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 14:47:15.352993 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 14:47:15.356412 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
3476 14:47:15.362778 1 0 24 | B1->B0 | 2828 4040 | 0 0 | (0 0) (0 0)
3477 14:47:15.366082 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3478 14:47:15.369432 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 14:47:15.375844 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 14:47:15.379514 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 14:47:15.383001 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 14:47:15.389872 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 14:47:15.392667 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 14:47:15.395988 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3485 14:47:15.402507 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3486 14:47:15.406259 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 14:47:15.410089 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 14:47:15.416835 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 14:47:15.419250 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 14:47:15.422814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 14:47:15.425873 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 14:47:15.432657 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 14:47:15.436153 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 14:47:15.439396 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 14:47:15.445758 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 14:47:15.449790 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 14:47:15.452751 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 14:47:15.459194 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 14:47:15.462620 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3500 14:47:15.466173 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3501 14:47:15.472672 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3502 14:47:15.472776 Total UI for P1: 0, mck2ui 16
3503 14:47:15.479256 best dqsien dly found for B0: ( 1, 3, 22)
3504 14:47:15.483071 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 14:47:15.485739 Total UI for P1: 0, mck2ui 16
3506 14:47:15.489179 best dqsien dly found for B1: ( 1, 3, 26)
3507 14:47:15.492804 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3508 14:47:15.495885 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3509 14:47:15.495985
3510 14:47:15.499019 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3511 14:47:15.502244 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3512 14:47:15.506157 [Gating] SW calibration Done
3513 14:47:15.506234 ==
3514 14:47:15.508926 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 14:47:15.512454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 14:47:15.516041 ==
3517 14:47:15.516145 RX Vref Scan: 0
3518 14:47:15.516235
3519 14:47:15.519198 RX Vref 0 -> 0, step: 1
3520 14:47:15.519293
3521 14:47:15.519390 RX Delay -40 -> 252, step: 8
3522 14:47:15.526100 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3523 14:47:15.529480 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3524 14:47:15.532773 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3525 14:47:15.535897 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3526 14:47:15.540506 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3527 14:47:15.546285 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3528 14:47:15.549293 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3529 14:47:15.552479 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3530 14:47:15.556418 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3531 14:47:15.559483 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3532 14:47:15.562963 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3533 14:47:15.569939 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3534 14:47:15.572675 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3535 14:47:15.576346 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3536 14:47:15.579507 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3537 14:47:15.585940 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3538 14:47:15.586022 ==
3539 14:47:15.589900 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 14:47:15.592851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 14:47:15.592956 ==
3542 14:47:15.593033 DQS Delay:
3543 14:47:15.596274 DQS0 = 0, DQS1 = 0
3544 14:47:15.596368 DQM Delay:
3545 14:47:15.599675 DQM0 = 113, DQM1 = 107
3546 14:47:15.599770 DQ Delay:
3547 14:47:15.603050 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3548 14:47:15.606636 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3549 14:47:15.609364 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3550 14:47:15.612738 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
3551 14:47:15.612836
3552 14:47:15.612934
3553 14:47:15.613063 ==
3554 14:47:15.616742 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 14:47:15.624324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 14:47:15.624423 ==
3557 14:47:15.624512
3558 14:47:15.624616
3559 14:47:15.624702 TX Vref Scan disable
3560 14:47:15.626599 == TX Byte 0 ==
3561 14:47:15.630161 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3562 14:47:15.636638 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3563 14:47:15.636712 == TX Byte 1 ==
3564 14:47:15.639959 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3565 14:47:15.645985 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3566 14:47:15.646093 ==
3567 14:47:15.649542 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 14:47:15.652695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 14:47:15.652792 ==
3570 14:47:15.664067 TX Vref=22, minBit 1, minWin=25, winSum=417
3571 14:47:15.668254 TX Vref=24, minBit 1, minWin=25, winSum=424
3572 14:47:15.671026 TX Vref=26, minBit 2, minWin=26, winSum=433
3573 14:47:15.674053 TX Vref=28, minBit 3, minWin=26, winSum=430
3574 14:47:15.677636 TX Vref=30, minBit 2, minWin=26, winSum=429
3575 14:47:15.680927 TX Vref=32, minBit 2, minWin=26, winSum=433
3576 14:47:15.687108 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 26
3577 14:47:15.687185
3578 14:47:15.691268 Final TX Range 1 Vref 26
3579 14:47:15.691345
3580 14:47:15.691408 ==
3581 14:47:15.694372 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 14:47:15.697324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 14:47:15.697409 ==
3584 14:47:15.697508
3585 14:47:15.700448
3586 14:47:15.700541 TX Vref Scan disable
3587 14:47:15.704101 == TX Byte 0 ==
3588 14:47:15.707176 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3589 14:47:15.710518 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3590 14:47:15.714106 == TX Byte 1 ==
3591 14:47:15.717319 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3592 14:47:15.720609 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3593 14:47:15.720711
3594 14:47:15.724150 [DATLAT]
3595 14:47:15.724251 Freq=1200, CH1 RK1
3596 14:47:15.724345
3597 14:47:15.727291 DATLAT Default: 0xd
3598 14:47:15.727385 0, 0xFFFF, sum = 0
3599 14:47:15.731267 1, 0xFFFF, sum = 0
3600 14:47:15.731339 2, 0xFFFF, sum = 0
3601 14:47:15.733887 3, 0xFFFF, sum = 0
3602 14:47:15.733990 4, 0xFFFF, sum = 0
3603 14:47:15.737580 5, 0xFFFF, sum = 0
3604 14:47:15.737652 6, 0xFFFF, sum = 0
3605 14:47:15.740909 7, 0xFFFF, sum = 0
3606 14:47:15.741036 8, 0xFFFF, sum = 0
3607 14:47:15.744012 9, 0xFFFF, sum = 0
3608 14:47:15.747314 10, 0xFFFF, sum = 0
3609 14:47:15.747398 11, 0xFFFF, sum = 0
3610 14:47:15.750442 12, 0x0, sum = 1
3611 14:47:15.750523 13, 0x0, sum = 2
3612 14:47:15.753637 14, 0x0, sum = 3
3613 14:47:15.753719 15, 0x0, sum = 4
3614 14:47:15.753784 best_step = 13
3615 14:47:15.753844
3616 14:47:15.757228 ==
3617 14:47:15.761567 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 14:47:15.763741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 14:47:15.763821 ==
3620 14:47:15.763885 RX Vref Scan: 0
3621 14:47:15.763944
3622 14:47:15.767394 RX Vref 0 -> 0, step: 1
3623 14:47:15.767474
3624 14:47:15.770472 RX Delay -21 -> 252, step: 4
3625 14:47:15.774100 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3626 14:47:15.780665 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3627 14:47:15.784740 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3628 14:47:15.787370 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3629 14:47:15.790680 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3630 14:47:15.793875 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3631 14:47:15.797619 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3632 14:47:15.804267 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3633 14:47:15.807429 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3634 14:47:15.810307 iDelay=191, Bit 9, Center 96 (31 ~ 162) 132
3635 14:47:15.814185 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3636 14:47:15.816897 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3637 14:47:15.824088 iDelay=191, Bit 12, Center 116 (55 ~ 178) 124
3638 14:47:15.827391 iDelay=191, Bit 13, Center 116 (51 ~ 182) 132
3639 14:47:15.830867 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3640 14:47:15.833672 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3641 14:47:15.833752 ==
3642 14:47:15.837182 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 14:47:15.843750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 14:47:15.843832 ==
3645 14:47:15.843914 DQS Delay:
3646 14:47:15.843987 DQS0 = 0, DQS1 = 0
3647 14:47:15.848622 DQM Delay:
3648 14:47:15.848728 DQM0 = 113, DQM1 = 108
3649 14:47:15.851156 DQ Delay:
3650 14:47:15.854224 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3651 14:47:15.857592 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3652 14:47:15.860934 DQ8 =96, DQ9 =96, DQ10 =110, DQ11 =100
3653 14:47:15.864008 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3654 14:47:15.864114
3655 14:47:15.864204
3656 14:47:15.870682 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5fc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3657 14:47:15.873972 CH1 RK1: MR19=303, MR18=F5FC
3658 14:47:15.880955 CH1_RK1: MR19=0x303, MR18=0xF5FC, DQSOSC=411, MR23=63, INC=38, DEC=25
3659 14:47:15.884516 [RxdqsGatingPostProcess] freq 1200
3660 14:47:15.890585 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3661 14:47:15.894749 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 14:47:15.894830 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 14:47:15.897752 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 14:47:15.900571 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 14:47:15.904655 best DQS0 dly(2T, 0.5T) = (0, 11)
3666 14:47:15.908070 best DQS1 dly(2T, 0.5T) = (0, 11)
3667 14:47:15.911262 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3668 14:47:15.914042 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3669 14:47:15.918008 Pre-setting of DQS Precalculation
3670 14:47:15.924366 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3671 14:47:15.931208 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3672 14:47:15.937484 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3673 14:47:15.937565
3674 14:47:15.937628
3675 14:47:15.940943 [Calibration Summary] 2400 Mbps
3676 14:47:15.941046 CH 0, Rank 0
3677 14:47:15.944240 SW Impedance : PASS
3678 14:47:15.947751 DUTY Scan : NO K
3679 14:47:15.947831 ZQ Calibration : PASS
3680 14:47:15.951045 Jitter Meter : NO K
3681 14:47:15.951125 CBT Training : PASS
3682 14:47:15.953919 Write leveling : PASS
3683 14:47:15.957707 RX DQS gating : PASS
3684 14:47:15.957788 RX DQ/DQS(RDDQC) : PASS
3685 14:47:15.961189 TX DQ/DQS : PASS
3686 14:47:15.964049 RX DATLAT : PASS
3687 14:47:15.964128 RX DQ/DQS(Engine): PASS
3688 14:47:15.968092 TX OE : NO K
3689 14:47:15.968172 All Pass.
3690 14:47:15.968235
3691 14:47:15.970686 CH 0, Rank 1
3692 14:47:15.970766 SW Impedance : PASS
3693 14:47:15.974035 DUTY Scan : NO K
3694 14:47:15.977439 ZQ Calibration : PASS
3695 14:47:15.977519 Jitter Meter : NO K
3696 14:47:15.980754 CBT Training : PASS
3697 14:47:15.984423 Write leveling : PASS
3698 14:47:15.984503 RX DQS gating : PASS
3699 14:47:15.987263 RX DQ/DQS(RDDQC) : PASS
3700 14:47:15.990788 TX DQ/DQS : PASS
3701 14:47:15.990869 RX DATLAT : PASS
3702 14:47:15.993915 RX DQ/DQS(Engine): PASS
3703 14:47:15.993995 TX OE : NO K
3704 14:47:15.997456 All Pass.
3705 14:47:15.997536
3706 14:47:15.997599 CH 1, Rank 0
3707 14:47:16.001089 SW Impedance : PASS
3708 14:47:16.001168 DUTY Scan : NO K
3709 14:47:16.003848 ZQ Calibration : PASS
3710 14:47:16.007586 Jitter Meter : NO K
3711 14:47:16.007666 CBT Training : PASS
3712 14:47:16.011411 Write leveling : PASS
3713 14:47:16.014505 RX DQS gating : PASS
3714 14:47:16.014585 RX DQ/DQS(RDDQC) : PASS
3715 14:47:16.017364 TX DQ/DQS : PASS
3716 14:47:16.020500 RX DATLAT : PASS
3717 14:47:16.020580 RX DQ/DQS(Engine): PASS
3718 14:47:16.024751 TX OE : NO K
3719 14:47:16.024831 All Pass.
3720 14:47:16.024894
3721 14:47:16.027331 CH 1, Rank 1
3722 14:47:16.027411 SW Impedance : PASS
3723 14:47:16.031071 DUTY Scan : NO K
3724 14:47:16.031152 ZQ Calibration : PASS
3725 14:47:16.033911 Jitter Meter : NO K
3726 14:47:16.038334 CBT Training : PASS
3727 14:47:16.038414 Write leveling : PASS
3728 14:47:16.040730 RX DQS gating : PASS
3729 14:47:16.044110 RX DQ/DQS(RDDQC) : PASS
3730 14:47:16.044190 TX DQ/DQS : PASS
3731 14:47:16.048126 RX DATLAT : PASS
3732 14:47:16.051006 RX DQ/DQS(Engine): PASS
3733 14:47:16.051086 TX OE : NO K
3734 14:47:16.054734 All Pass.
3735 14:47:16.054814
3736 14:47:16.054878 DramC Write-DBI off
3737 14:47:16.057816 PER_BANK_REFRESH: Hybrid Mode
3738 14:47:16.057896 TX_TRACKING: ON
3739 14:47:16.067464 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3740 14:47:16.071356 [FAST_K] Save calibration result to emmc
3741 14:47:16.074585 dramc_set_vcore_voltage set vcore to 650000
3742 14:47:16.077593 Read voltage for 600, 5
3743 14:47:16.077673 Vio18 = 0
3744 14:47:16.080788 Vcore = 650000
3745 14:47:16.080868 Vdram = 0
3746 14:47:16.080931 Vddq = 0
3747 14:47:16.081027 Vmddr = 0
3748 14:47:16.087353 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3749 14:47:16.094124 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3750 14:47:16.094205 MEM_TYPE=3, freq_sel=19
3751 14:47:16.097501 sv_algorithm_assistance_LP4_1600
3752 14:47:16.101190 ============ PULL DRAM RESETB DOWN ============
3753 14:47:16.107824 ========== PULL DRAM RESETB DOWN end =========
3754 14:47:16.110790 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3755 14:47:16.114028 ===================================
3756 14:47:16.117376 LPDDR4 DRAM CONFIGURATION
3757 14:47:16.120537 ===================================
3758 14:47:16.120618 EX_ROW_EN[0] = 0x0
3759 14:47:16.124136 EX_ROW_EN[1] = 0x0
3760 14:47:16.127742 LP4Y_EN = 0x0
3761 14:47:16.127822 WORK_FSP = 0x0
3762 14:47:16.130497 WL = 0x2
3763 14:47:16.130576 RL = 0x2
3764 14:47:16.134120 BL = 0x2
3765 14:47:16.134200 RPST = 0x0
3766 14:47:16.137648 RD_PRE = 0x0
3767 14:47:16.137728 WR_PRE = 0x1
3768 14:47:16.140824 WR_PST = 0x0
3769 14:47:16.140905 DBI_WR = 0x0
3770 14:47:16.143988 DBI_RD = 0x0
3771 14:47:16.144068 OTF = 0x1
3772 14:47:16.147219 ===================================
3773 14:47:16.150553 ===================================
3774 14:47:16.154342 ANA top config
3775 14:47:16.157437 ===================================
3776 14:47:16.157518 DLL_ASYNC_EN = 0
3777 14:47:16.161020 ALL_SLAVE_EN = 1
3778 14:47:16.164291 NEW_RANK_MODE = 1
3779 14:47:16.167334 DLL_IDLE_MODE = 1
3780 14:47:16.167414 LP45_APHY_COMB_EN = 1
3781 14:47:16.170706 TX_ODT_DIS = 1
3782 14:47:16.174240 NEW_8X_MODE = 1
3783 14:47:16.177217 ===================================
3784 14:47:16.181781 ===================================
3785 14:47:16.184330 data_rate = 1200
3786 14:47:16.187500 CKR = 1
3787 14:47:16.187600 DQ_P2S_RATIO = 8
3788 14:47:16.190645 ===================================
3789 14:47:16.194052 CA_P2S_RATIO = 8
3790 14:47:16.198205 DQ_CA_OPEN = 0
3791 14:47:16.201335 DQ_SEMI_OPEN = 0
3792 14:47:16.204526 CA_SEMI_OPEN = 0
3793 14:47:16.207916 CA_FULL_RATE = 0
3794 14:47:16.208015 DQ_CKDIV4_EN = 1
3795 14:47:16.210634 CA_CKDIV4_EN = 1
3796 14:47:16.214455 CA_PREDIV_EN = 0
3797 14:47:16.217649 PH8_DLY = 0
3798 14:47:16.220773 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3799 14:47:16.224031 DQ_AAMCK_DIV = 4
3800 14:47:16.224111 CA_AAMCK_DIV = 4
3801 14:47:16.228056 CA_ADMCK_DIV = 4
3802 14:47:16.231014 DQ_TRACK_CA_EN = 0
3803 14:47:16.234454 CA_PICK = 600
3804 14:47:16.237496 CA_MCKIO = 600
3805 14:47:16.241012 MCKIO_SEMI = 0
3806 14:47:16.245100 PLL_FREQ = 2288
3807 14:47:16.245180 DQ_UI_PI_RATIO = 32
3808 14:47:16.247796 CA_UI_PI_RATIO = 0
3809 14:47:16.250741 ===================================
3810 14:47:16.254140 ===================================
3811 14:47:16.257783 memory_type:LPDDR4
3812 14:47:16.260654 GP_NUM : 10
3813 14:47:16.260735 SRAM_EN : 1
3814 14:47:16.264254 MD32_EN : 0
3815 14:47:16.267300 ===================================
3816 14:47:16.267381 [ANA_INIT] >>>>>>>>>>>>>>
3817 14:47:16.271055 <<<<<< [CONFIGURE PHASE]: ANA_TX
3818 14:47:16.274000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3819 14:47:16.278202 ===================================
3820 14:47:16.280507 data_rate = 1200,PCW = 0X5800
3821 14:47:16.284509 ===================================
3822 14:47:16.287802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3823 14:47:16.294402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3824 14:47:16.297615 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 14:47:16.304114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3826 14:47:16.307395 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3827 14:47:16.310770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3828 14:47:16.313982 [ANA_INIT] flow start
3829 14:47:16.314062 [ANA_INIT] PLL >>>>>>>>
3830 14:47:16.317366 [ANA_INIT] PLL <<<<<<<<
3831 14:47:16.320862 [ANA_INIT] MIDPI >>>>>>>>
3832 14:47:16.320942 [ANA_INIT] MIDPI <<<<<<<<
3833 14:47:16.324130 [ANA_INIT] DLL >>>>>>>>
3834 14:47:16.327565 [ANA_INIT] flow end
3835 14:47:16.330348 ============ LP4 DIFF to SE enter ============
3836 14:47:16.334050 ============ LP4 DIFF to SE exit ============
3837 14:47:16.337178 [ANA_INIT] <<<<<<<<<<<<<
3838 14:47:16.340528 [Flow] Enable top DCM control >>>>>
3839 14:47:16.344185 [Flow] Enable top DCM control <<<<<
3840 14:47:16.347354 Enable DLL master slave shuffle
3841 14:47:16.350610 ==============================================================
3842 14:47:16.354193 Gating Mode config
3843 14:47:16.357464 ==============================================================
3844 14:47:16.361101 Config description:
3845 14:47:16.370566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3846 14:47:16.377487 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3847 14:47:16.381025 SELPH_MODE 0: By rank 1: By Phase
3848 14:47:16.387461 ==============================================================
3849 14:47:16.391067 GAT_TRACK_EN = 1
3850 14:47:16.395023 RX_GATING_MODE = 2
3851 14:47:16.397608 RX_GATING_TRACK_MODE = 2
3852 14:47:16.400565 SELPH_MODE = 1
3853 14:47:16.403953 PICG_EARLY_EN = 1
3854 14:47:16.404054 VALID_LAT_VALUE = 1
3855 14:47:16.410951 ==============================================================
3856 14:47:16.414451 Enter into Gating configuration >>>>
3857 14:47:16.418183 Exit from Gating configuration <<<<
3858 14:47:16.421352 Enter into DVFS_PRE_config >>>>>
3859 14:47:16.431345 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3860 14:47:16.434075 Exit from DVFS_PRE_config <<<<<
3861 14:47:16.438753 Enter into PICG configuration >>>>
3862 14:47:16.440696 Exit from PICG configuration <<<<
3863 14:47:16.444192 [RX_INPUT] configuration >>>>>
3864 14:47:16.448099 [RX_INPUT] configuration <<<<<
3865 14:47:16.450923 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3866 14:47:16.457324 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3867 14:47:16.464052 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 14:47:16.470603 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 14:47:16.478036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 14:47:16.480866 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 14:47:16.487568 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3872 14:47:16.491441 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3873 14:47:16.494803 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3874 14:47:16.498095 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3875 14:47:16.504909 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3876 14:47:16.508328 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 14:47:16.511200 ===================================
3878 14:47:16.515011 LPDDR4 DRAM CONFIGURATION
3879 14:47:16.517597 ===================================
3880 14:47:16.518048 EX_ROW_EN[0] = 0x0
3881 14:47:16.521125 EX_ROW_EN[1] = 0x0
3882 14:47:16.521692 LP4Y_EN = 0x0
3883 14:47:16.524227 WORK_FSP = 0x0
3884 14:47:16.524660 WL = 0x2
3885 14:47:16.527856 RL = 0x2
3886 14:47:16.528315 BL = 0x2
3887 14:47:16.531197 RPST = 0x0
3888 14:47:16.531629 RD_PRE = 0x0
3889 14:47:16.535120 WR_PRE = 0x1
3890 14:47:16.535550 WR_PST = 0x0
3891 14:47:16.537843 DBI_WR = 0x0
3892 14:47:16.538274 DBI_RD = 0x0
3893 14:47:16.541587 OTF = 0x1
3894 14:47:16.544451 ===================================
3895 14:47:16.547872 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3896 14:47:16.551271 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3897 14:47:16.558013 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 14:47:16.561443 ===================================
3899 14:47:16.561892 LPDDR4 DRAM CONFIGURATION
3900 14:47:16.564753 ===================================
3901 14:47:16.567660 EX_ROW_EN[0] = 0x10
3902 14:47:16.570606 EX_ROW_EN[1] = 0x0
3903 14:47:16.571050 LP4Y_EN = 0x0
3904 14:47:16.574341 WORK_FSP = 0x0
3905 14:47:16.574784 WL = 0x2
3906 14:47:16.577562 RL = 0x2
3907 14:47:16.578010 BL = 0x2
3908 14:47:16.580622 RPST = 0x0
3909 14:47:16.581134 RD_PRE = 0x0
3910 14:47:16.584141 WR_PRE = 0x1
3911 14:47:16.584581 WR_PST = 0x0
3912 14:47:16.587569 DBI_WR = 0x0
3913 14:47:16.588002 DBI_RD = 0x0
3914 14:47:16.590921 OTF = 0x1
3915 14:47:16.595401 ===================================
3916 14:47:16.601004 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3917 14:47:16.604474 nWR fixed to 30
3918 14:47:16.607398 [ModeRegInit_LP4] CH0 RK0
3919 14:47:16.607991 [ModeRegInit_LP4] CH0 RK1
3920 14:47:16.610632 [ModeRegInit_LP4] CH1 RK0
3921 14:47:16.614864 [ModeRegInit_LP4] CH1 RK1
3922 14:47:16.615387 match AC timing 17
3923 14:47:16.621114 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3924 14:47:16.624202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3925 14:47:16.627908 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3926 14:47:16.634037 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3927 14:47:16.637205 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3928 14:47:16.637654 ==
3929 14:47:16.640549 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 14:47:16.644029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 14:47:16.644465 ==
3932 14:47:16.650560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 14:47:16.657554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 14:47:16.660699 [CA 0] Center 36 (6~67) winsize 62
3935 14:47:16.663935 [CA 1] Center 36 (6~66) winsize 61
3936 14:47:16.667645 [CA 2] Center 34 (4~65) winsize 62
3937 14:47:16.670868 [CA 3] Center 34 (4~65) winsize 62
3938 14:47:16.673957 [CA 4] Center 33 (3~64) winsize 62
3939 14:47:16.677307 [CA 5] Center 33 (3~64) winsize 62
3940 14:47:16.677900
3941 14:47:16.680414 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 14:47:16.680885
3943 14:47:16.683997 [CATrainingPosCal] consider 1 rank data
3944 14:47:16.687326 u2DelayCellTimex100 = 270/100 ps
3945 14:47:16.690190 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3946 14:47:16.693798 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3947 14:47:16.697094 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 14:47:16.700855 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3949 14:47:16.704139 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 14:47:16.707047 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 14:47:16.707645
3952 14:47:16.714776 CA PerBit enable=1, Macro0, CA PI delay=33
3953 14:47:16.715202
3954 14:47:16.715530 [CBTSetCACLKResult] CA Dly = 33
3955 14:47:16.717710 CS Dly: 5 (0~36)
3956 14:47:16.718222 ==
3957 14:47:16.720392 Dram Type= 6, Freq= 0, CH_0, rank 1
3958 14:47:16.724471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 14:47:16.725065 ==
3960 14:47:16.730879 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 14:47:16.737750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3962 14:47:16.741254 [CA 0] Center 36 (6~66) winsize 61
3963 14:47:16.743979 [CA 1] Center 36 (6~66) winsize 61
3964 14:47:16.747136 [CA 2] Center 34 (4~65) winsize 62
3965 14:47:16.750497 [CA 3] Center 34 (4~65) winsize 62
3966 14:47:16.754318 [CA 4] Center 33 (3~64) winsize 62
3967 14:47:16.757367 [CA 5] Center 33 (3~64) winsize 62
3968 14:47:16.757815
3969 14:47:16.761070 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3970 14:47:16.761504
3971 14:47:16.763978 [CATrainingPosCal] consider 2 rank data
3972 14:47:16.767318 u2DelayCellTimex100 = 270/100 ps
3973 14:47:16.771553 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 14:47:16.774812 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 14:47:16.777121 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 14:47:16.780893 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3977 14:47:16.784108 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 14:47:16.787618 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 14:47:16.788050
3980 14:47:16.791396 CA PerBit enable=1, Macro0, CA PI delay=33
3981 14:47:16.794368
3982 14:47:16.794800 [CBTSetCACLKResult] CA Dly = 33
3983 14:47:16.797571 CS Dly: 5 (0~36)
3984 14:47:16.798017
3985 14:47:16.800403 ----->DramcWriteLeveling(PI) begin...
3986 14:47:16.800916 ==
3987 14:47:16.804161 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 14:47:16.807675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 14:47:16.808108 ==
3990 14:47:16.810821 Write leveling (Byte 0): 34 => 34
3991 14:47:16.814103 Write leveling (Byte 1): 28 => 28
3992 14:47:16.818014 DramcWriteLeveling(PI) end<-----
3993 14:47:16.818547
3994 14:47:16.818964 ==
3995 14:47:16.821433 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 14:47:16.824018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 14:47:16.824485 ==
3998 14:47:16.827515 [Gating] SW mode calibration
3999 14:47:16.834221 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4000 14:47:16.840893 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4001 14:47:16.844223 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 14:47:16.850810 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 14:47:16.854120 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 14:47:16.857509 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4005 14:47:16.860882 0 9 16 | B1->B0 | 3030 2626 | 0 0 | (0 1) (1 1)
4006 14:47:16.867682 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 14:47:16.871152 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 14:47:16.874947 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 14:47:16.881208 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 14:47:16.884293 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 14:47:16.887427 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 14:47:16.894278 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4013 14:47:16.897418 0 10 16 | B1->B0 | 2929 3838 | 0 0 | (0 0) (0 0)
4014 14:47:16.900693 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4015 14:47:16.907418 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 14:47:16.911061 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 14:47:16.914031 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 14:47:16.920614 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 14:47:16.923997 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 14:47:16.927528 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 14:47:16.933911 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4022 14:47:16.938633 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 14:47:16.941068 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 14:47:16.947399 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 14:47:16.951223 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 14:47:16.954108 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 14:47:16.958017 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 14:47:16.964554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 14:47:16.967927 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 14:47:16.970843 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 14:47:16.977760 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 14:47:16.980965 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 14:47:16.984528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 14:47:16.991303 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 14:47:16.993982 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 14:47:16.997515 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 14:47:17.004304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4038 14:47:17.007277 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 14:47:17.011293 Total UI for P1: 0, mck2ui 16
4040 14:47:17.014057 best dqsien dly found for B0: ( 0, 13, 16)
4041 14:47:17.018417 Total UI for P1: 0, mck2ui 16
4042 14:47:17.021412 best dqsien dly found for B1: ( 0, 13, 16)
4043 14:47:17.025219 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4044 14:47:17.027418 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4045 14:47:17.027826
4046 14:47:17.030205 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4047 14:47:17.033740 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4048 14:47:17.036888 [Gating] SW calibration Done
4049 14:47:17.037039 ==
4050 14:47:17.041082 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 14:47:17.043507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 14:47:17.047081 ==
4053 14:47:17.047160 RX Vref Scan: 0
4054 14:47:17.047224
4055 14:47:17.050887 RX Vref 0 -> 0, step: 1
4056 14:47:17.050967
4057 14:47:17.053544 RX Delay -230 -> 252, step: 16
4058 14:47:17.056747 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4059 14:47:17.060496 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4060 14:47:17.063237 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4061 14:47:17.070686 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4062 14:47:17.073305 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4063 14:47:17.076568 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4064 14:47:17.080067 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4065 14:47:17.083561 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4066 14:47:17.090181 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4067 14:47:17.093668 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4068 14:47:17.096570 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4069 14:47:17.099885 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4070 14:47:17.106929 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4071 14:47:17.109611 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4072 14:47:17.113200 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4073 14:47:17.116339 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4074 14:47:17.116445 ==
4075 14:47:17.119760 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 14:47:17.126735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 14:47:17.126816 ==
4078 14:47:17.126879 DQS Delay:
4079 14:47:17.129796 DQS0 = 0, DQS1 = 0
4080 14:47:17.129892 DQM Delay:
4081 14:47:17.129985 DQM0 = 44, DQM1 = 34
4082 14:47:17.133420 DQ Delay:
4083 14:47:17.136532 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4084 14:47:17.139630 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4085 14:47:17.143256 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4086 14:47:17.147166 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4087 14:47:17.147245
4088 14:47:17.147307
4089 14:47:17.147364 ==
4090 14:47:17.149817 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 14:47:17.154066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 14:47:17.154163 ==
4093 14:47:17.154240
4094 14:47:17.154299
4095 14:47:17.156946 TX Vref Scan disable
4096 14:47:17.159693 == TX Byte 0 ==
4097 14:47:17.163884 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4098 14:47:17.166662 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4099 14:47:17.169763 == TX Byte 1 ==
4100 14:47:17.173178 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4101 14:47:17.176922 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4102 14:47:17.177058 ==
4103 14:47:17.179788 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 14:47:17.183245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 14:47:17.183325 ==
4106 14:47:17.186406
4107 14:47:17.186485
4108 14:47:17.186548 TX Vref Scan disable
4109 14:47:17.191405 == TX Byte 0 ==
4110 14:47:17.193965 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4111 14:47:17.200125 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4112 14:47:17.200205 == TX Byte 1 ==
4113 14:47:17.203441 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4114 14:47:17.210911 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4115 14:47:17.210992
4116 14:47:17.211055 [DATLAT]
4117 14:47:17.211113 Freq=600, CH0 RK0
4118 14:47:17.211171
4119 14:47:17.213797 DATLAT Default: 0x9
4120 14:47:17.213880 0, 0xFFFF, sum = 0
4121 14:47:17.217004 1, 0xFFFF, sum = 0
4122 14:47:17.217100 2, 0xFFFF, sum = 0
4123 14:47:17.220577 3, 0xFFFF, sum = 0
4124 14:47:17.220684 4, 0xFFFF, sum = 0
4125 14:47:17.223523 5, 0xFFFF, sum = 0
4126 14:47:17.227167 6, 0xFFFF, sum = 0
4127 14:47:17.227264 7, 0xFFFF, sum = 0
4128 14:47:17.227342 8, 0x0, sum = 1
4129 14:47:17.229953 9, 0x0, sum = 2
4130 14:47:17.230034 10, 0x0, sum = 3
4131 14:47:17.233338 11, 0x0, sum = 4
4132 14:47:17.233419 best_step = 9
4133 14:47:17.233481
4134 14:47:17.233540 ==
4135 14:47:17.237124 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 14:47:17.243468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 14:47:17.243548 ==
4138 14:47:17.243610 RX Vref Scan: 1
4139 14:47:17.243669
4140 14:47:17.247199 RX Vref 0 -> 0, step: 1
4141 14:47:17.247279
4142 14:47:17.250858 RX Delay -195 -> 252, step: 8
4143 14:47:17.250937
4144 14:47:17.254375 Set Vref, RX VrefLevel [Byte0]: 52
4145 14:47:17.256816 [Byte1]: 51
4146 14:47:17.256896
4147 14:47:17.260498 Final RX Vref Byte 0 = 52 to rank0
4148 14:47:17.263840 Final RX Vref Byte 1 = 51 to rank0
4149 14:47:17.267233 Final RX Vref Byte 0 = 52 to rank1
4150 14:47:17.270641 Final RX Vref Byte 1 = 51 to rank1==
4151 14:47:17.273333 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 14:47:17.276839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 14:47:17.276945 ==
4154 14:47:17.280911 DQS Delay:
4155 14:47:17.281046 DQS0 = 0, DQS1 = 0
4156 14:47:17.281111 DQM Delay:
4157 14:47:17.283844 DQM0 = 42, DQM1 = 33
4158 14:47:17.283923 DQ Delay:
4159 14:47:17.287189 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4160 14:47:17.290121 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4161 14:47:17.293546 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4162 14:47:17.296875 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4163 14:47:17.297000
4164 14:47:17.297081
4165 14:47:17.306936 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4166 14:47:17.307017 CH0 RK0: MR19=808, MR18=3E1D
4167 14:47:17.313777 CH0_RK0: MR19=0x808, MR18=0x3E1D, DQSOSC=398, MR23=63, INC=165, DEC=110
4168 14:47:17.313857
4169 14:47:17.316857 ----->DramcWriteLeveling(PI) begin...
4170 14:47:17.316964 ==
4171 14:47:17.320938 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 14:47:17.327575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 14:47:17.327655 ==
4174 14:47:17.330406 Write leveling (Byte 0): 33 => 33
4175 14:47:17.333527 Write leveling (Byte 1): 30 => 30
4176 14:47:17.333606 DramcWriteLeveling(PI) end<-----
4177 14:47:17.337237
4178 14:47:17.337316 ==
4179 14:47:17.340339 Dram Type= 6, Freq= 0, CH_0, rank 1
4180 14:47:17.343689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 14:47:17.343770 ==
4182 14:47:17.346853 [Gating] SW mode calibration
4183 14:47:17.354223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4184 14:47:17.357275 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4185 14:47:17.363977 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 14:47:17.366831 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 14:47:17.370818 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 14:47:17.377136 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
4189 14:47:17.380185 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
4190 14:47:17.383723 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 14:47:17.391421 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 14:47:17.393626 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 14:47:17.396916 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 14:47:17.403751 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 14:47:17.406954 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 14:47:17.410714 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4197 14:47:17.414177 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4198 14:47:17.420523 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 14:47:17.423589 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 14:47:17.427420 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 14:47:17.433938 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 14:47:17.437594 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 14:47:17.440755 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 14:47:17.447093 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4205 14:47:17.450707 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4206 14:47:17.454556 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 14:47:17.460371 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 14:47:17.463985 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 14:47:17.467450 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 14:47:17.473808 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 14:47:17.476910 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 14:47:17.480870 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 14:47:17.487759 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 14:47:17.490551 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 14:47:17.493557 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 14:47:17.500209 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 14:47:17.503780 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 14:47:17.508244 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 14:47:17.514145 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 14:47:17.517359 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 14:47:17.520232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4222 14:47:17.523764 Total UI for P1: 0, mck2ui 16
4223 14:47:17.527125 best dqsien dly found for B0: ( 0, 13, 14)
4224 14:47:17.530844 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 14:47:17.533564 Total UI for P1: 0, mck2ui 16
4226 14:47:17.536891 best dqsien dly found for B1: ( 0, 13, 16)
4227 14:47:17.540230 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4228 14:47:17.547373 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4229 14:47:17.547445
4230 14:47:17.550497 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4231 14:47:17.553903 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4232 14:47:17.557334 [Gating] SW calibration Done
4233 14:47:17.557430 ==
4234 14:47:17.560205 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 14:47:17.563414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 14:47:17.563488 ==
4237 14:47:17.566782 RX Vref Scan: 0
4238 14:47:17.566850
4239 14:47:17.566908 RX Vref 0 -> 0, step: 1
4240 14:47:17.566964
4241 14:47:17.570044 RX Delay -230 -> 252, step: 16
4242 14:47:17.573622 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4243 14:47:17.580833 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4244 14:47:17.583319 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4245 14:47:17.587301 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4246 14:47:17.590225 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4247 14:47:17.593434 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4248 14:47:17.599951 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4249 14:47:17.603331 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4250 14:47:17.607063 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4251 14:47:17.610146 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4252 14:47:17.616919 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4253 14:47:17.620374 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4254 14:47:17.623748 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4255 14:47:17.627255 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4256 14:47:17.630073 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4257 14:47:17.637405 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4258 14:47:17.637485 ==
4259 14:47:17.640660 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 14:47:17.643248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 14:47:17.643329 ==
4262 14:47:17.643392 DQS Delay:
4263 14:47:17.647067 DQS0 = 0, DQS1 = 0
4264 14:47:17.647147 DQM Delay:
4265 14:47:17.649861 DQM0 = 41, DQM1 = 32
4266 14:47:17.649941 DQ Delay:
4267 14:47:17.653544 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4268 14:47:17.656579 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4269 14:47:17.660127 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4270 14:47:17.663931 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4271 14:47:17.664011
4272 14:47:17.664073
4273 14:47:17.664131 ==
4274 14:47:17.666743 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 14:47:17.670442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 14:47:17.673423 ==
4277 14:47:17.673503
4278 14:47:17.673568
4279 14:47:17.673684 TX Vref Scan disable
4280 14:47:17.677515 == TX Byte 0 ==
4281 14:47:17.679929 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4282 14:47:17.683427 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4283 14:47:17.687080 == TX Byte 1 ==
4284 14:47:17.689931 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4285 14:47:17.693358 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4286 14:47:17.696935 ==
4287 14:47:17.700187 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 14:47:17.703494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 14:47:17.703574 ==
4290 14:47:17.703637
4291 14:47:17.703696
4292 14:47:17.706412 TX Vref Scan disable
4293 14:47:17.706491 == TX Byte 0 ==
4294 14:47:17.713023 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4295 14:47:17.717481 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4296 14:47:17.717561 == TX Byte 1 ==
4297 14:47:17.723223 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4298 14:47:17.727148 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4299 14:47:17.727243
4300 14:47:17.727307 [DATLAT]
4301 14:47:17.730193 Freq=600, CH0 RK1
4302 14:47:17.730273
4303 14:47:17.730354 DATLAT Default: 0x9
4304 14:47:17.733530 0, 0xFFFF, sum = 0
4305 14:47:17.733612 1, 0xFFFF, sum = 0
4306 14:47:17.736946 2, 0xFFFF, sum = 0
4307 14:47:17.737070 3, 0xFFFF, sum = 0
4308 14:47:17.740309 4, 0xFFFF, sum = 0
4309 14:47:17.740383 5, 0xFFFF, sum = 0
4310 14:47:17.743618 6, 0xFFFF, sum = 0
4311 14:47:17.746734 7, 0xFFFF, sum = 0
4312 14:47:17.746814 8, 0x0, sum = 1
4313 14:47:17.746878 9, 0x0, sum = 2
4314 14:47:17.750389 10, 0x0, sum = 3
4315 14:47:17.750469 11, 0x0, sum = 4
4316 14:47:17.753863 best_step = 9
4317 14:47:17.753941
4318 14:47:17.754003 ==
4319 14:47:17.756705 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 14:47:17.760458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 14:47:17.760537 ==
4322 14:47:17.764315 RX Vref Scan: 0
4323 14:47:17.764394
4324 14:47:17.764457 RX Vref 0 -> 0, step: 1
4325 14:47:17.764515
4326 14:47:17.766670 RX Delay -179 -> 252, step: 8
4327 14:47:17.773934 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4328 14:47:17.777364 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4329 14:47:17.780268 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4330 14:47:17.784112 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4331 14:47:17.790429 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4332 14:47:17.794117 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4333 14:47:17.796869 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4334 14:47:17.800913 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4335 14:47:17.804257 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4336 14:47:17.810466 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4337 14:47:17.813804 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4338 14:47:17.817108 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4339 14:47:17.820631 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4340 14:47:17.827040 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4341 14:47:17.830367 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4342 14:47:17.833606 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4343 14:47:17.833686 ==
4344 14:47:17.837270 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 14:47:17.840671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 14:47:17.840751 ==
4347 14:47:17.844025 DQS Delay:
4348 14:47:17.844104 DQS0 = 0, DQS1 = 0
4349 14:47:17.847366 DQM Delay:
4350 14:47:17.847445 DQM0 = 39, DQM1 = 33
4351 14:47:17.847507 DQ Delay:
4352 14:47:17.850663 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4353 14:47:17.855129 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4354 14:47:17.857393 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4355 14:47:17.860789 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4356 14:47:17.860868
4357 14:47:17.860929
4358 14:47:17.870848 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4359 14:47:17.873894 CH0 RK1: MR19=808, MR18=4E31
4360 14:47:17.877631 CH0_RK1: MR19=0x808, MR18=0x4E31, DQSOSC=395, MR23=63, INC=168, DEC=112
4361 14:47:17.880926 [RxdqsGatingPostProcess] freq 600
4362 14:47:17.887347 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4363 14:47:17.890551 Pre-setting of DQS Precalculation
4364 14:47:17.893754 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4365 14:47:17.893833 ==
4366 14:47:17.896970 Dram Type= 6, Freq= 0, CH_1, rank 0
4367 14:47:17.903592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 14:47:17.903688 ==
4369 14:47:17.907150 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4370 14:47:17.913808 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4371 14:47:17.917131 [CA 0] Center 35 (5~66) winsize 62
4372 14:47:17.920653 [CA 1] Center 35 (5~66) winsize 62
4373 14:47:17.923921 [CA 2] Center 34 (3~65) winsize 63
4374 14:47:17.927219 [CA 3] Center 33 (3~64) winsize 62
4375 14:47:17.931229 [CA 4] Center 34 (3~65) winsize 63
4376 14:47:17.934131 [CA 5] Center 33 (2~64) winsize 63
4377 14:47:17.934211
4378 14:47:17.936915 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4379 14:47:17.937049
4380 14:47:17.940815 [CATrainingPosCal] consider 1 rank data
4381 14:47:17.944255 u2DelayCellTimex100 = 270/100 ps
4382 14:47:17.947262 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4383 14:47:17.950465 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4384 14:47:17.957150 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4385 14:47:17.960391 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4386 14:47:17.964279 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4387 14:47:17.968255 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4388 14:47:17.968353
4389 14:47:17.970814 CA PerBit enable=1, Macro0, CA PI delay=33
4390 14:47:17.970888
4391 14:47:17.974583 [CBTSetCACLKResult] CA Dly = 33
4392 14:47:17.974653 CS Dly: 3 (0~34)
4393 14:47:17.974712 ==
4394 14:47:17.977389 Dram Type= 6, Freq= 0, CH_1, rank 1
4395 14:47:17.984086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 14:47:17.984190 ==
4397 14:47:17.987834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 14:47:17.993938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4399 14:47:17.997147 [CA 0] Center 35 (5~66) winsize 62
4400 14:47:18.000750 [CA 1] Center 35 (5~66) winsize 62
4401 14:47:18.004108 [CA 2] Center 34 (4~65) winsize 62
4402 14:47:18.007769 [CA 3] Center 34 (3~65) winsize 63
4403 14:47:18.010992 [CA 4] Center 34 (3~65) winsize 63
4404 14:47:18.013979 [CA 5] Center 33 (3~64) winsize 62
4405 14:47:18.014059
4406 14:47:18.018140 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4407 14:47:18.018220
4408 14:47:18.020557 [CATrainingPosCal] consider 2 rank data
4409 14:47:18.024124 u2DelayCellTimex100 = 270/100 ps
4410 14:47:18.027079 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4411 14:47:18.030867 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4412 14:47:18.037411 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 14:47:18.040628 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 14:47:18.043756 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4415 14:47:18.047538 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 14:47:18.047633
4417 14:47:18.050795 CA PerBit enable=1, Macro0, CA PI delay=33
4418 14:47:18.050889
4419 14:47:18.053818 [CBTSetCACLKResult] CA Dly = 33
4420 14:47:18.053888 CS Dly: 4 (0~37)
4421 14:47:18.053946
4422 14:47:18.057848 ----->DramcWriteLeveling(PI) begin...
4423 14:47:18.060325 ==
4424 14:47:18.064632 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 14:47:18.067454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 14:47:18.067550 ==
4427 14:47:18.071691 Write leveling (Byte 0): 28 => 28
4428 14:47:18.073966 Write leveling (Byte 1): 31 => 31
4429 14:47:18.077387 DramcWriteLeveling(PI) end<-----
4430 14:47:18.077457
4431 14:47:18.077516 ==
4432 14:47:18.080645 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 14:47:18.084326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 14:47:18.084401 ==
4435 14:47:18.087347 [Gating] SW mode calibration
4436 14:47:18.094957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4437 14:47:18.097782 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4438 14:47:18.103985 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 14:47:18.107326 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 14:47:18.110937 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 14:47:18.117371 0 9 12 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 0)
4442 14:47:18.121510 0 9 16 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
4443 14:47:18.124048 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 14:47:18.131088 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 14:47:18.134152 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 14:47:18.137255 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 14:47:18.144077 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 14:47:18.147247 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 14:47:18.150609 0 10 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
4450 14:47:18.154616 0 10 16 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)
4451 14:47:18.160705 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 14:47:18.164238 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 14:47:18.167204 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 14:47:18.174388 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 14:47:18.177233 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 14:47:18.181213 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 14:47:18.187770 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 14:47:18.190996 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4459 14:47:18.194389 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 14:47:18.200742 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 14:47:18.204056 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 14:47:18.207306 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 14:47:18.213798 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 14:47:18.218338 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 14:47:18.220890 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 14:47:18.227304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 14:47:18.230667 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 14:47:18.234142 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 14:47:18.240463 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 14:47:18.244458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 14:47:18.247280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 14:47:18.254454 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 14:47:18.257404 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4474 14:47:18.260623 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 14:47:18.264122 Total UI for P1: 0, mck2ui 16
4476 14:47:18.267539 best dqsien dly found for B0: ( 0, 13, 12)
4477 14:47:18.270992 Total UI for P1: 0, mck2ui 16
4478 14:47:18.273848 best dqsien dly found for B1: ( 0, 13, 12)
4479 14:47:18.277644 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4480 14:47:18.280740 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4481 14:47:18.280820
4482 14:47:18.283822 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4483 14:47:18.291530 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4484 14:47:18.291618 [Gating] SW calibration Done
4485 14:47:18.291683 ==
4486 14:47:18.294084 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 14:47:18.301098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 14:47:18.301179 ==
4489 14:47:18.301243 RX Vref Scan: 0
4490 14:47:18.301327
4491 14:47:18.303972 RX Vref 0 -> 0, step: 1
4492 14:47:18.304052
4493 14:47:18.307756 RX Delay -230 -> 252, step: 16
4494 14:47:18.311212 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4495 14:47:18.314295 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4496 14:47:18.317289 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4497 14:47:18.323661 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4498 14:47:18.328070 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4499 14:47:18.330626 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4500 14:47:18.334199 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4501 14:47:18.340664 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4502 14:47:18.343942 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4503 14:47:18.347369 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4504 14:47:18.350718 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4505 14:47:18.353983 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4506 14:47:18.360324 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4507 14:47:18.363545 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4508 14:47:18.367131 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4509 14:47:18.370172 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4510 14:47:18.373733 ==
4511 14:47:18.377240 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 14:47:18.380445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 14:47:18.380551 ==
4514 14:47:18.380642 DQS Delay:
4515 14:47:18.383626 DQS0 = 0, DQS1 = 0
4516 14:47:18.383746 DQM Delay:
4517 14:47:18.386951 DQM0 = 43, DQM1 = 33
4518 14:47:18.387031 DQ Delay:
4519 14:47:18.391165 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4520 14:47:18.393872 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4521 14:47:18.396656 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4522 14:47:18.400045 DQ12 =49, DQ13 =41, DQ14 =33, DQ15 =33
4523 14:47:18.400151
4524 14:47:18.400240
4525 14:47:18.400325 ==
4526 14:47:18.403317 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 14:47:18.407429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 14:47:18.407534 ==
4529 14:47:18.407627
4530 14:47:18.407713
4531 14:47:18.410091 TX Vref Scan disable
4532 14:47:18.413420 == TX Byte 0 ==
4533 14:47:18.417191 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 14:47:18.419859 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 14:47:18.423487 == TX Byte 1 ==
4536 14:47:18.426684 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4537 14:47:18.430057 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4538 14:47:18.430151 ==
4539 14:47:18.433939 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 14:47:18.439926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 14:47:18.440021 ==
4542 14:47:18.440083
4543 14:47:18.440139
4544 14:47:18.440198 TX Vref Scan disable
4545 14:47:18.444154 == TX Byte 0 ==
4546 14:47:18.447871 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4547 14:47:18.451134 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4548 14:47:18.454294 == TX Byte 1 ==
4549 14:47:18.457906 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4550 14:47:18.460954 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4551 14:47:18.464429
4552 14:47:18.464522 [DATLAT]
4553 14:47:18.464610 Freq=600, CH1 RK0
4554 14:47:18.464696
4555 14:47:18.467565 DATLAT Default: 0x9
4556 14:47:18.467663 0, 0xFFFF, sum = 0
4557 14:47:18.471280 1, 0xFFFF, sum = 0
4558 14:47:18.471352 2, 0xFFFF, sum = 0
4559 14:47:18.474418 3, 0xFFFF, sum = 0
4560 14:47:18.474483 4, 0xFFFF, sum = 0
4561 14:47:18.477915 5, 0xFFFF, sum = 0
4562 14:47:18.478007 6, 0xFFFF, sum = 0
4563 14:47:18.481745 7, 0xFFFF, sum = 0
4564 14:47:18.481814 8, 0x0, sum = 1
4565 14:47:18.484414 9, 0x0, sum = 2
4566 14:47:18.484505 10, 0x0, sum = 3
4567 14:47:18.487681 11, 0x0, sum = 4
4568 14:47:18.487775 best_step = 9
4569 14:47:18.487893
4570 14:47:18.487975 ==
4571 14:47:18.490870 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 14:47:18.498374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 14:47:18.498470 ==
4574 14:47:18.498557 RX Vref Scan: 1
4575 14:47:18.498644
4576 14:47:18.502549 RX Vref 0 -> 0, step: 1
4577 14:47:18.502615
4578 14:47:18.504764 RX Delay -195 -> 252, step: 8
4579 14:47:18.504899
4580 14:47:18.507852 Set Vref, RX VrefLevel [Byte0]: 56
4581 14:47:18.511240 [Byte1]: 45
4582 14:47:18.511330
4583 14:47:18.514655 Final RX Vref Byte 0 = 56 to rank0
4584 14:47:18.518539 Final RX Vref Byte 1 = 45 to rank0
4585 14:47:18.521260 Final RX Vref Byte 0 = 56 to rank1
4586 14:47:18.524176 Final RX Vref Byte 1 = 45 to rank1==
4587 14:47:18.527965 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 14:47:18.530806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 14:47:18.530873 ==
4590 14:47:18.534434 DQS Delay:
4591 14:47:18.534527 DQS0 = 0, DQS1 = 0
4592 14:47:18.534612 DQM Delay:
4593 14:47:18.537616 DQM0 = 40, DQM1 = 33
4594 14:47:18.537686 DQ Delay:
4595 14:47:18.541530 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4596 14:47:18.544887 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4597 14:47:18.547800 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4598 14:47:18.551092 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =36
4599 14:47:18.551182
4600 14:47:18.551269
4601 14:47:18.561575 [DQSOSCAuto] RK0, (LSB)MR18= 0x4309, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4602 14:47:18.561673 CH1 RK0: MR19=808, MR18=4309
4603 14:47:18.568098 CH1_RK0: MR19=0x808, MR18=0x4309, DQSOSC=397, MR23=63, INC=166, DEC=110
4604 14:47:18.568210
4605 14:47:18.571473 ----->DramcWriteLeveling(PI) begin...
4606 14:47:18.571555 ==
4607 14:47:18.574573 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 14:47:18.580934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 14:47:18.581038 ==
4610 14:47:18.584501 Write leveling (Byte 0): 31 => 31
4611 14:47:18.588379 Write leveling (Byte 1): 28 => 28
4612 14:47:18.588459 DramcWriteLeveling(PI) end<-----
4613 14:47:18.588522
4614 14:47:18.591438 ==
4615 14:47:18.594965 Dram Type= 6, Freq= 0, CH_1, rank 1
4616 14:47:18.598393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 14:47:18.598473 ==
4618 14:47:18.601689 [Gating] SW mode calibration
4619 14:47:18.607503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4620 14:47:18.610886 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4621 14:47:18.617546 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 14:47:18.620932 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 14:47:18.624671 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
4624 14:47:18.631799 0 9 12 | B1->B0 | 3030 2e2e | 1 1 | (0 1) (0 0)
4625 14:47:18.635210 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4626 14:47:18.637724 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 14:47:18.645205 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 14:47:18.648039 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 14:47:18.651020 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 14:47:18.654591 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4631 14:47:18.661269 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4632 14:47:18.664420 0 10 12 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
4633 14:47:18.667658 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4634 14:47:18.674713 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 14:47:18.678098 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 14:47:18.681131 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 14:47:18.688329 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 14:47:18.691837 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 14:47:18.694820 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4640 14:47:18.701714 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4641 14:47:18.704678 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 14:47:18.708051 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 14:47:18.714826 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 14:47:18.717831 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 14:47:18.721414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 14:47:18.727820 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 14:47:18.731163 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 14:47:18.734587 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 14:47:18.742273 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 14:47:18.744624 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 14:47:18.748169 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 14:47:18.751613 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 14:47:18.757689 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 14:47:18.761461 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 14:47:18.764804 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 14:47:18.771266 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4657 14:47:18.774632 Total UI for P1: 0, mck2ui 16
4658 14:47:18.777901 best dqsien dly found for B0: ( 0, 13, 10)
4659 14:47:18.781704 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 14:47:18.784985 Total UI for P1: 0, mck2ui 16
4661 14:47:18.787865 best dqsien dly found for B1: ( 0, 13, 12)
4662 14:47:18.791718 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4663 14:47:18.794709 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4664 14:47:18.794789
4665 14:47:18.798098 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4666 14:47:18.801401 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4667 14:47:18.804672 [Gating] SW calibration Done
4668 14:47:18.804751 ==
4669 14:47:18.808028 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 14:47:18.811208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 14:47:18.814672 ==
4672 14:47:18.814785 RX Vref Scan: 0
4673 14:47:18.814851
4674 14:47:18.818035 RX Vref 0 -> 0, step: 1
4675 14:47:18.818115
4676 14:47:18.821533 RX Delay -230 -> 252, step: 16
4677 14:47:18.824622 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4678 14:47:18.827985 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4679 14:47:18.831117 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4680 14:47:18.838406 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4681 14:47:18.841331 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4682 14:47:18.844644 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4683 14:47:18.848110 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4684 14:47:18.851461 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4685 14:47:18.857937 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4686 14:47:18.861697 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4687 14:47:18.864455 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4688 14:47:18.867841 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4689 14:47:18.875012 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4690 14:47:18.877940 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4691 14:47:18.881232 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4692 14:47:18.885202 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4693 14:47:18.885283 ==
4694 14:47:18.887935 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 14:47:18.894448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 14:47:18.894529 ==
4697 14:47:18.894593 DQS Delay:
4698 14:47:18.897781 DQS0 = 0, DQS1 = 0
4699 14:47:18.897862 DQM Delay:
4700 14:47:18.897926 DQM0 = 40, DQM1 = 36
4701 14:47:18.901349 DQ Delay:
4702 14:47:18.905225 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4703 14:47:18.908002 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4704 14:47:18.911147 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4705 14:47:18.914493 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4706 14:47:18.914572
4707 14:47:18.914635
4708 14:47:18.914693 ==
4709 14:47:18.917832 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 14:47:18.921394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 14:47:18.921492 ==
4712 14:47:18.921588
4713 14:47:18.921663
4714 14:47:18.924776 TX Vref Scan disable
4715 14:47:18.924856 == TX Byte 0 ==
4716 14:47:18.931796 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4717 14:47:18.935150 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4718 14:47:18.935255 == TX Byte 1 ==
4719 14:47:18.941277 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4720 14:47:18.944628 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4721 14:47:18.944725 ==
4722 14:47:18.948303 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 14:47:18.951896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 14:47:18.951991 ==
4725 14:47:18.952077
4726 14:47:18.952163
4727 14:47:18.955285 TX Vref Scan disable
4728 14:47:18.958195 == TX Byte 0 ==
4729 14:47:18.961562 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4730 14:47:18.964899 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4731 14:47:18.968013 == TX Byte 1 ==
4732 14:47:18.971807 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4733 14:47:18.975154 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4734 14:47:18.975235
4735 14:47:18.978617 [DATLAT]
4736 14:47:18.978697 Freq=600, CH1 RK1
4737 14:47:18.978761
4738 14:47:18.981359 DATLAT Default: 0x9
4739 14:47:18.981470 0, 0xFFFF, sum = 0
4740 14:47:18.984846 1, 0xFFFF, sum = 0
4741 14:47:18.984927 2, 0xFFFF, sum = 0
4742 14:47:18.988447 3, 0xFFFF, sum = 0
4743 14:47:18.988529 4, 0xFFFF, sum = 0
4744 14:47:18.991516 5, 0xFFFF, sum = 0
4745 14:47:18.991597 6, 0xFFFF, sum = 0
4746 14:47:18.994980 7, 0xFFFF, sum = 0
4747 14:47:18.995061 8, 0x0, sum = 1
4748 14:47:18.998183 9, 0x0, sum = 2
4749 14:47:18.998282 10, 0x0, sum = 3
4750 14:47:19.001175 11, 0x0, sum = 4
4751 14:47:19.001285 best_step = 9
4752 14:47:19.001381
4753 14:47:19.001468 ==
4754 14:47:19.004988 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 14:47:19.008236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 14:47:19.011500 ==
4757 14:47:19.011580 RX Vref Scan: 0
4758 14:47:19.011643
4759 14:47:19.014767 RX Vref 0 -> 0, step: 1
4760 14:47:19.014847
4761 14:47:19.018092 RX Delay -179 -> 252, step: 8
4762 14:47:19.022272 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4763 14:47:19.024552 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4764 14:47:19.031530 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4765 14:47:19.035452 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4766 14:47:19.038053 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4767 14:47:19.041288 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4768 14:47:19.047699 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4769 14:47:19.051266 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4770 14:47:19.054692 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4771 14:47:19.057923 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4772 14:47:19.061349 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4773 14:47:19.067863 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4774 14:47:19.071343 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4775 14:47:19.074616 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4776 14:47:19.078168 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4777 14:47:19.085729 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4778 14:47:19.085810 ==
4779 14:47:19.088314 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 14:47:19.092563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 14:47:19.092644 ==
4782 14:47:19.092708 DQS Delay:
4783 14:47:19.094872 DQS0 = 0, DQS1 = 0
4784 14:47:19.094952 DQM Delay:
4785 14:47:19.098076 DQM0 = 38, DQM1 = 33
4786 14:47:19.098156 DQ Delay:
4787 14:47:19.101871 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4788 14:47:19.105617 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4789 14:47:19.108052 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4790 14:47:19.111686 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4791 14:47:19.111766
4792 14:47:19.111830
4793 14:47:19.118449 [DQSOSCAuto] RK1, (LSB)MR18= 0x3747, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4794 14:47:19.122606 CH1 RK1: MR19=808, MR18=3747
4795 14:47:19.128784 CH1_RK1: MR19=0x808, MR18=0x3747, DQSOSC=396, MR23=63, INC=167, DEC=111
4796 14:47:19.131342 [RxdqsGatingPostProcess] freq 600
4797 14:47:19.138153 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4798 14:47:19.138234 Pre-setting of DQS Precalculation
4799 14:47:19.145734 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4800 14:47:19.151941 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4801 14:47:19.158114 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4802 14:47:19.158220
4803 14:47:19.158316
4804 14:47:19.162261 [Calibration Summary] 1200 Mbps
4805 14:47:19.164874 CH 0, Rank 0
4806 14:47:19.164954 SW Impedance : PASS
4807 14:47:19.169363 DUTY Scan : NO K
4808 14:47:19.169474 ZQ Calibration : PASS
4809 14:47:19.171690 Jitter Meter : NO K
4810 14:47:19.175317 CBT Training : PASS
4811 14:47:19.175423 Write leveling : PASS
4812 14:47:19.178772 RX DQS gating : PASS
4813 14:47:19.181545 RX DQ/DQS(RDDQC) : PASS
4814 14:47:19.181626 TX DQ/DQS : PASS
4815 14:47:19.185215 RX DATLAT : PASS
4816 14:47:19.188341 RX DQ/DQS(Engine): PASS
4817 14:47:19.188420 TX OE : NO K
4818 14:47:19.191685 All Pass.
4819 14:47:19.191765
4820 14:47:19.191828 CH 0, Rank 1
4821 14:47:19.195403 SW Impedance : PASS
4822 14:47:19.195483 DUTY Scan : NO K
4823 14:47:19.198505 ZQ Calibration : PASS
4824 14:47:19.201613 Jitter Meter : NO K
4825 14:47:19.201693 CBT Training : PASS
4826 14:47:19.205209 Write leveling : PASS
4827 14:47:19.205289 RX DQS gating : PASS
4828 14:47:19.208553 RX DQ/DQS(RDDQC) : PASS
4829 14:47:19.211790 TX DQ/DQS : PASS
4830 14:47:19.211871 RX DATLAT : PASS
4831 14:47:19.215327 RX DQ/DQS(Engine): PASS
4832 14:47:19.218367 TX OE : NO K
4833 14:47:19.218448 All Pass.
4834 14:47:19.218512
4835 14:47:19.218570 CH 1, Rank 0
4836 14:47:19.221918 SW Impedance : PASS
4837 14:47:19.225301 DUTY Scan : NO K
4838 14:47:19.225386 ZQ Calibration : PASS
4839 14:47:19.227944 Jitter Meter : NO K
4840 14:47:19.231472 CBT Training : PASS
4841 14:47:19.231551 Write leveling : PASS
4842 14:47:19.235236 RX DQS gating : PASS
4843 14:47:19.238692 RX DQ/DQS(RDDQC) : PASS
4844 14:47:19.238772 TX DQ/DQS : PASS
4845 14:47:19.241974 RX DATLAT : PASS
4846 14:47:19.244731 RX DQ/DQS(Engine): PASS
4847 14:47:19.244811 TX OE : NO K
4848 14:47:19.244875 All Pass.
4849 14:47:19.248144
4850 14:47:19.248257 CH 1, Rank 1
4851 14:47:19.251523 SW Impedance : PASS
4852 14:47:19.251604 DUTY Scan : NO K
4853 14:47:19.254780 ZQ Calibration : PASS
4854 14:47:19.254860 Jitter Meter : NO K
4855 14:47:19.258101 CBT Training : PASS
4856 14:47:19.261427 Write leveling : PASS
4857 14:47:19.261508 RX DQS gating : PASS
4858 14:47:19.265032 RX DQ/DQS(RDDQC) : PASS
4859 14:47:19.268061 TX DQ/DQS : PASS
4860 14:47:19.268142 RX DATLAT : PASS
4861 14:47:19.271269 RX DQ/DQS(Engine): PASS
4862 14:47:19.275855 TX OE : NO K
4863 14:47:19.275935 All Pass.
4864 14:47:19.275999
4865 14:47:19.278024 DramC Write-DBI off
4866 14:47:19.278104 PER_BANK_REFRESH: Hybrid Mode
4867 14:47:19.281683 TX_TRACKING: ON
4868 14:47:19.287927 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4869 14:47:19.295274 [FAST_K] Save calibration result to emmc
4870 14:47:19.298010 dramc_set_vcore_voltage set vcore to 662500
4871 14:47:19.298091 Read voltage for 933, 3
4872 14:47:19.301754 Vio18 = 0
4873 14:47:19.301833 Vcore = 662500
4874 14:47:19.301896 Vdram = 0
4875 14:47:19.304766 Vddq = 0
4876 14:47:19.304846 Vmddr = 0
4877 14:47:19.308328 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4878 14:47:19.314864 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4879 14:47:19.318355 MEM_TYPE=3, freq_sel=17
4880 14:47:19.321337 sv_algorithm_assistance_LP4_1600
4881 14:47:19.324605 ============ PULL DRAM RESETB DOWN ============
4882 14:47:19.327933 ========== PULL DRAM RESETB DOWN end =========
4883 14:47:19.332080 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4884 14:47:19.335137 ===================================
4885 14:47:19.338419 LPDDR4 DRAM CONFIGURATION
4886 14:47:19.341498 ===================================
4887 14:47:19.344926 EX_ROW_EN[0] = 0x0
4888 14:47:19.345041 EX_ROW_EN[1] = 0x0
4889 14:47:19.347833 LP4Y_EN = 0x0
4890 14:47:19.347913 WORK_FSP = 0x0
4891 14:47:19.351332 WL = 0x3
4892 14:47:19.351413 RL = 0x3
4893 14:47:19.354561 BL = 0x2
4894 14:47:19.354648 RPST = 0x0
4895 14:47:19.357992 RD_PRE = 0x0
4896 14:47:19.358071 WR_PRE = 0x1
4897 14:47:19.361792 WR_PST = 0x0
4898 14:47:19.361861 DBI_WR = 0x0
4899 14:47:19.364605 DBI_RD = 0x0
4900 14:47:19.368280 OTF = 0x1
4901 14:47:19.371304 ===================================
4902 14:47:19.371375 ===================================
4903 14:47:19.374662 ANA top config
4904 14:47:19.377845 ===================================
4905 14:47:19.381280 DLL_ASYNC_EN = 0
4906 14:47:19.381349 ALL_SLAVE_EN = 1
4907 14:47:19.384774 NEW_RANK_MODE = 1
4908 14:47:19.388581 DLL_IDLE_MODE = 1
4909 14:47:19.390987 LP45_APHY_COMB_EN = 1
4910 14:47:19.394444 TX_ODT_DIS = 1
4911 14:47:19.394520 NEW_8X_MODE = 1
4912 14:47:19.398116 ===================================
4913 14:47:19.401849 ===================================
4914 14:47:19.404411 data_rate = 1866
4915 14:47:19.408268 CKR = 1
4916 14:47:19.411691 DQ_P2S_RATIO = 8
4917 14:47:19.415413 ===================================
4918 14:47:19.418168 CA_P2S_RATIO = 8
4919 14:47:19.418353 DQ_CA_OPEN = 0
4920 14:47:19.421425 DQ_SEMI_OPEN = 0
4921 14:47:19.424288 CA_SEMI_OPEN = 0
4922 14:47:19.427714 CA_FULL_RATE = 0
4923 14:47:19.431449 DQ_CKDIV4_EN = 1
4924 14:47:19.434930 CA_CKDIV4_EN = 1
4925 14:47:19.435013 CA_PREDIV_EN = 0
4926 14:47:19.438023 PH8_DLY = 0
4927 14:47:19.441561 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4928 14:47:19.445309 DQ_AAMCK_DIV = 4
4929 14:47:19.447758 CA_AAMCK_DIV = 4
4930 14:47:19.451288 CA_ADMCK_DIV = 4
4931 14:47:19.451360 DQ_TRACK_CA_EN = 0
4932 14:47:19.454513 CA_PICK = 933
4933 14:47:19.458151 CA_MCKIO = 933
4934 14:47:19.462101 MCKIO_SEMI = 0
4935 14:47:19.464707 PLL_FREQ = 3732
4936 14:47:19.468434 DQ_UI_PI_RATIO = 32
4937 14:47:19.471526 CA_UI_PI_RATIO = 0
4938 14:47:19.475166 ===================================
4939 14:47:19.477997 ===================================
4940 14:47:19.478078 memory_type:LPDDR4
4941 14:47:19.481291 GP_NUM : 10
4942 14:47:19.481371 SRAM_EN : 1
4943 14:47:19.484972 MD32_EN : 0
4944 14:47:19.488088 ===================================
4945 14:47:19.491349 [ANA_INIT] >>>>>>>>>>>>>>
4946 14:47:19.494752 <<<<<< [CONFIGURE PHASE]: ANA_TX
4947 14:47:19.498146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4948 14:47:19.501558 ===================================
4949 14:47:19.501638 data_rate = 1866,PCW = 0X8f00
4950 14:47:19.504572 ===================================
4951 14:47:19.511113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4952 14:47:19.514953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 14:47:19.521711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 14:47:19.524871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4955 14:47:19.527980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4956 14:47:19.531809 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4957 14:47:19.534840 [ANA_INIT] flow start
4958 14:47:19.538119 [ANA_INIT] PLL >>>>>>>>
4959 14:47:19.538199 [ANA_INIT] PLL <<<<<<<<
4960 14:47:19.542349 [ANA_INIT] MIDPI >>>>>>>>
4961 14:47:19.545342 [ANA_INIT] MIDPI <<<<<<<<
4962 14:47:19.545423 [ANA_INIT] DLL >>>>>>>>
4963 14:47:19.548828 [ANA_INIT] flow end
4964 14:47:19.551257 ============ LP4 DIFF to SE enter ============
4965 14:47:19.554608 ============ LP4 DIFF to SE exit ============
4966 14:47:19.558088 [ANA_INIT] <<<<<<<<<<<<<
4967 14:47:19.562176 [Flow] Enable top DCM control >>>>>
4968 14:47:19.565194 [Flow] Enable top DCM control <<<<<
4969 14:47:19.568136 Enable DLL master slave shuffle
4970 14:47:19.574834 ==============================================================
4971 14:47:19.574915 Gating Mode config
4972 14:47:19.581394 ==============================================================
4973 14:47:19.581474 Config description:
4974 14:47:19.591862 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4975 14:47:19.598191 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4976 14:47:19.604820 SELPH_MODE 0: By rank 1: By Phase
4977 14:47:19.608017 ==============================================================
4978 14:47:19.611899 GAT_TRACK_EN = 1
4979 14:47:19.614595 RX_GATING_MODE = 2
4980 14:47:19.617991 RX_GATING_TRACK_MODE = 2
4981 14:47:19.621656 SELPH_MODE = 1
4982 14:47:19.624564 PICG_EARLY_EN = 1
4983 14:47:19.628407 VALID_LAT_VALUE = 1
4984 14:47:19.631222 ==============================================================
4985 14:47:19.634906 Enter into Gating configuration >>>>
4986 14:47:19.638400 Exit from Gating configuration <<<<
4987 14:47:19.641825 Enter into DVFS_PRE_config >>>>>
4988 14:47:19.655562 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4989 14:47:19.657954 Exit from DVFS_PRE_config <<<<<
4990 14:47:19.661441 Enter into PICG configuration >>>>
4991 14:47:19.661522 Exit from PICG configuration <<<<
4992 14:47:19.664893 [RX_INPUT] configuration >>>>>
4993 14:47:19.668633 [RX_INPUT] configuration <<<<<
4994 14:47:19.674691 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4995 14:47:19.677760 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4996 14:47:19.684454 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4997 14:47:19.690934 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4998 14:47:19.698391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 14:47:19.705207 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 14:47:19.708183 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5001 14:47:19.711390 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5002 14:47:19.714516 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5003 14:47:19.721544 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5004 14:47:19.725368 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5005 14:47:19.727884 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 14:47:19.731222 ===================================
5007 14:47:19.735279 LPDDR4 DRAM CONFIGURATION
5008 14:47:19.738019 ===================================
5009 14:47:19.741082 EX_ROW_EN[0] = 0x0
5010 14:47:19.741162 EX_ROW_EN[1] = 0x0
5011 14:47:19.744375 LP4Y_EN = 0x0
5012 14:47:19.744454 WORK_FSP = 0x0
5013 14:47:19.747622 WL = 0x3
5014 14:47:19.747702 RL = 0x3
5015 14:47:19.750934 BL = 0x2
5016 14:47:19.751014 RPST = 0x0
5017 14:47:19.754514 RD_PRE = 0x0
5018 14:47:19.754593 WR_PRE = 0x1
5019 14:47:19.758435 WR_PST = 0x0
5020 14:47:19.758514 DBI_WR = 0x0
5021 14:47:19.761901 DBI_RD = 0x0
5022 14:47:19.761980 OTF = 0x1
5023 14:47:19.764464 ===================================
5024 14:47:19.768074 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5025 14:47:19.774322 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5026 14:47:19.778311 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 14:47:19.781387 ===================================
5028 14:47:19.785084 LPDDR4 DRAM CONFIGURATION
5029 14:47:19.788195 ===================================
5030 14:47:19.788275 EX_ROW_EN[0] = 0x10
5031 14:47:19.791165 EX_ROW_EN[1] = 0x0
5032 14:47:19.791244 LP4Y_EN = 0x0
5033 14:47:19.794839 WORK_FSP = 0x0
5034 14:47:19.794933 WL = 0x3
5035 14:47:19.798032 RL = 0x3
5036 14:47:19.801961 BL = 0x2
5037 14:47:19.802033 RPST = 0x0
5038 14:47:19.805078 RD_PRE = 0x0
5039 14:47:19.805153 WR_PRE = 0x1
5040 14:47:19.808091 WR_PST = 0x0
5041 14:47:19.808160 DBI_WR = 0x0
5042 14:47:19.811223 DBI_RD = 0x0
5043 14:47:19.811289 OTF = 0x1
5044 14:47:19.814613 ===================================
5045 14:47:19.821297 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5046 14:47:19.825136 nWR fixed to 30
5047 14:47:19.829055 [ModeRegInit_LP4] CH0 RK0
5048 14:47:19.829124 [ModeRegInit_LP4] CH0 RK1
5049 14:47:19.831964 [ModeRegInit_LP4] CH1 RK0
5050 14:47:19.834992 [ModeRegInit_LP4] CH1 RK1
5051 14:47:19.835062 match AC timing 9
5052 14:47:19.842559 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5053 14:47:19.845112 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5054 14:47:19.848880 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5055 14:47:19.855265 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5056 14:47:19.858697 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5057 14:47:19.858767 ==
5058 14:47:19.861971 Dram Type= 6, Freq= 0, CH_0, rank 0
5059 14:47:19.865790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 14:47:19.865884 ==
5061 14:47:19.872367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 14:47:19.878691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5063 14:47:19.881989 [CA 0] Center 38 (8~69) winsize 62
5064 14:47:19.885575 [CA 1] Center 38 (7~69) winsize 63
5065 14:47:19.888441 [CA 2] Center 35 (5~66) winsize 62
5066 14:47:19.892319 [CA 3] Center 35 (5~66) winsize 62
5067 14:47:19.895960 [CA 4] Center 34 (4~64) winsize 61
5068 14:47:19.898932 [CA 5] Center 34 (4~64) winsize 61
5069 14:47:19.899034
5070 14:47:19.902627 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5071 14:47:19.902696
5072 14:47:19.905518 [CATrainingPosCal] consider 1 rank data
5073 14:47:19.908892 u2DelayCellTimex100 = 270/100 ps
5074 14:47:19.912473 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5075 14:47:19.915764 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5076 14:47:19.919228 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5077 14:47:19.922194 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5078 14:47:19.925537 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5079 14:47:19.929084 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5080 14:47:19.929153
5081 14:47:19.932481 CA PerBit enable=1, Macro0, CA PI delay=34
5082 14:47:19.932551
5083 14:47:19.935710 [CBTSetCACLKResult] CA Dly = 34
5084 14:47:19.938885 CS Dly: 6 (0~37)
5085 14:47:19.938955 ==
5086 14:47:19.942067 Dram Type= 6, Freq= 0, CH_0, rank 1
5087 14:47:19.945535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 14:47:19.945602 ==
5089 14:47:19.952666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 14:47:19.958980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5091 14:47:19.962244 [CA 0] Center 38 (7~69) winsize 63
5092 14:47:19.966145 [CA 1] Center 38 (7~69) winsize 63
5093 14:47:19.969468 [CA 2] Center 35 (5~66) winsize 62
5094 14:47:19.972326 [CA 3] Center 35 (5~65) winsize 61
5095 14:47:19.975322 [CA 4] Center 34 (3~65) winsize 63
5096 14:47:19.975392 [CA 5] Center 33 (3~64) winsize 62
5097 14:47:19.979181
5098 14:47:19.982472 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5099 14:47:19.982541
5100 14:47:19.986684 [CATrainingPosCal] consider 2 rank data
5101 14:47:19.988811 u2DelayCellTimex100 = 270/100 ps
5102 14:47:19.992369 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5103 14:47:19.995531 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5104 14:47:19.998893 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5105 14:47:20.002020 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5106 14:47:20.006018 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5107 14:47:20.009282 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5108 14:47:20.009349
5109 14:47:20.012287 CA PerBit enable=1, Macro0, CA PI delay=34
5110 14:47:20.012354
5111 14:47:20.015395 [CBTSetCACLKResult] CA Dly = 34
5112 14:47:20.019045 CS Dly: 7 (0~39)
5113 14:47:20.019124
5114 14:47:20.021930 ----->DramcWriteLeveling(PI) begin...
5115 14:47:20.022011 ==
5116 14:47:20.025385 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 14:47:20.028392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 14:47:20.028471 ==
5119 14:47:20.032294 Write leveling (Byte 0): 28 => 28
5120 14:47:20.035496 Write leveling (Byte 1): 27 => 27
5121 14:47:20.038819 DramcWriteLeveling(PI) end<-----
5122 14:47:20.038891
5123 14:47:20.038952 ==
5124 14:47:20.042517 Dram Type= 6, Freq= 0, CH_0, rank 0
5125 14:47:20.045309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 14:47:20.045396 ==
5127 14:47:20.048589 [Gating] SW mode calibration
5128 14:47:20.055642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5129 14:47:20.062060 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5130 14:47:20.065265 0 14 0 | B1->B0 | 2323 2e2d | 1 1 | (1 1) (1 1)
5131 14:47:20.069079 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5132 14:47:20.076223 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 14:47:20.078693 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 14:47:20.082593 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 14:47:20.089078 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 14:47:20.092273 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 14:47:20.095814 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5138 14:47:20.102031 0 15 0 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 0)
5139 14:47:20.105729 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5140 14:47:20.109216 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 14:47:20.115342 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 14:47:20.118992 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 14:47:20.121979 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 14:47:20.128746 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 14:47:20.132314 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 14:47:20.135733 1 0 0 | B1->B0 | 2f2f 4141 | 0 0 | (1 1) (0 0)
5147 14:47:20.142470 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 14:47:20.146050 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 14:47:20.149033 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 14:47:20.153015 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 14:47:20.159106 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 14:47:20.162577 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 14:47:20.165523 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 14:47:20.172891 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5155 14:47:20.175555 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 14:47:20.178974 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 14:47:20.185484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 14:47:20.189552 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 14:47:20.192439 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 14:47:20.199161 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 14:47:20.202208 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 14:47:20.205514 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 14:47:20.212542 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 14:47:20.215750 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 14:47:20.219199 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 14:47:20.225536 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 14:47:20.228839 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 14:47:20.232157 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 14:47:20.238878 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 14:47:20.242085 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5171 14:47:20.245794 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 14:47:20.249381 Total UI for P1: 0, mck2ui 16
5173 14:47:20.252570 best dqsien dly found for B0: ( 1, 3, 0)
5174 14:47:20.255899 Total UI for P1: 0, mck2ui 16
5175 14:47:20.259060 best dqsien dly found for B1: ( 1, 3, 0)
5176 14:47:20.262290 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5177 14:47:20.265625 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5178 14:47:20.265692
5179 14:47:20.268938 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5180 14:47:20.272246 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5181 14:47:20.275450 [Gating] SW calibration Done
5182 14:47:20.275520 ==
5183 14:47:20.278834 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 14:47:20.282357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 14:47:20.285541 ==
5186 14:47:20.285605 RX Vref Scan: 0
5187 14:47:20.285663
5188 14:47:20.288843 RX Vref 0 -> 0, step: 1
5189 14:47:20.288907
5190 14:47:20.292184 RX Delay -80 -> 252, step: 8
5191 14:47:20.296735 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5192 14:47:20.298601 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5193 14:47:20.301951 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5194 14:47:20.305326 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5195 14:47:20.308930 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5196 14:47:20.315846 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5197 14:47:20.318813 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5198 14:47:20.322071 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5199 14:47:20.325493 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5200 14:47:20.328695 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5201 14:47:20.332400 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5202 14:47:20.339196 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5203 14:47:20.342388 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5204 14:47:20.345260 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5205 14:47:20.348956 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5206 14:47:20.352675 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5207 14:47:20.352742 ==
5208 14:47:20.355537 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 14:47:20.362074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 14:47:20.362149 ==
5211 14:47:20.362210 DQS Delay:
5212 14:47:20.365986 DQS0 = 0, DQS1 = 0
5213 14:47:20.366052 DQM Delay:
5214 14:47:20.366111 DQM0 = 98, DQM1 = 87
5215 14:47:20.369978 DQ Delay:
5216 14:47:20.372495 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5217 14:47:20.375605 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5218 14:47:20.379176 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5219 14:47:20.382434 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5220 14:47:20.382514
5221 14:47:20.382577
5222 14:47:20.382634 ==
5223 14:47:20.385888 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 14:47:20.388812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 14:47:20.388914 ==
5226 14:47:20.389034
5227 14:47:20.389094
5228 14:47:20.392477 TX Vref Scan disable
5229 14:47:20.392547 == TX Byte 0 ==
5230 14:47:20.399270 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5231 14:47:20.402434 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5232 14:47:20.402503 == TX Byte 1 ==
5233 14:47:20.409619 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5234 14:47:20.412202 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5235 14:47:20.412268 ==
5236 14:47:20.416388 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 14:47:20.419217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 14:47:20.419291 ==
5239 14:47:20.419351
5240 14:47:20.419406
5241 14:47:20.422441 TX Vref Scan disable
5242 14:47:20.426856 == TX Byte 0 ==
5243 14:47:20.429079 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5244 14:47:20.432774 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5245 14:47:20.435543 == TX Byte 1 ==
5246 14:47:20.438707 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5247 14:47:20.442156 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5248 14:47:20.442231
5249 14:47:20.446034 [DATLAT]
5250 14:47:20.446103 Freq=933, CH0 RK0
5251 14:47:20.446165
5252 14:47:20.448899 DATLAT Default: 0xd
5253 14:47:20.449012 0, 0xFFFF, sum = 0
5254 14:47:20.452348 1, 0xFFFF, sum = 0
5255 14:47:20.452413 2, 0xFFFF, sum = 0
5256 14:47:20.455779 3, 0xFFFF, sum = 0
5257 14:47:20.455881 4, 0xFFFF, sum = 0
5258 14:47:20.460402 5, 0xFFFF, sum = 0
5259 14:47:20.460473 6, 0xFFFF, sum = 0
5260 14:47:20.462279 7, 0xFFFF, sum = 0
5261 14:47:20.462348 8, 0xFFFF, sum = 0
5262 14:47:20.465531 9, 0xFFFF, sum = 0
5263 14:47:20.465596 10, 0x0, sum = 1
5264 14:47:20.469173 11, 0x0, sum = 2
5265 14:47:20.469246 12, 0x0, sum = 3
5266 14:47:20.472498 13, 0x0, sum = 4
5267 14:47:20.472565 best_step = 11
5268 14:47:20.472626
5269 14:47:20.472685 ==
5270 14:47:20.476097 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 14:47:20.482246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 14:47:20.482318 ==
5273 14:47:20.482376 RX Vref Scan: 1
5274 14:47:20.482433
5275 14:47:20.486140 RX Vref 0 -> 0, step: 1
5276 14:47:20.486209
5277 14:47:20.489272 RX Delay -61 -> 252, step: 4
5278 14:47:20.489338
5279 14:47:20.492122 Set Vref, RX VrefLevel [Byte0]: 52
5280 14:47:20.495835 [Byte1]: 51
5281 14:47:20.495901
5282 14:47:20.499211 Final RX Vref Byte 0 = 52 to rank0
5283 14:47:20.502309 Final RX Vref Byte 1 = 51 to rank0
5284 14:47:20.505240 Final RX Vref Byte 0 = 52 to rank1
5285 14:47:20.509050 Final RX Vref Byte 1 = 51 to rank1==
5286 14:47:20.512204 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 14:47:20.515557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 14:47:20.515627 ==
5289 14:47:20.518642 DQS Delay:
5290 14:47:20.518709 DQS0 = 0, DQS1 = 0
5291 14:47:20.518768 DQM Delay:
5292 14:47:20.522913 DQM0 = 96, DQM1 = 88
5293 14:47:20.522983 DQ Delay:
5294 14:47:20.525415 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5295 14:47:20.529047 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5296 14:47:20.532146 DQ8 =78, DQ9 =74, DQ10 =90, DQ11 =80
5297 14:47:20.535512 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =96
5298 14:47:20.535611
5299 14:47:20.535697
5300 14:47:20.546189 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5301 14:47:20.549160 CH0 RK0: MR19=504, MR18=13FF
5302 14:47:20.552222 CH0_RK0: MR19=0x504, MR18=0x13FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5303 14:47:20.552297
5304 14:47:20.555438 ----->DramcWriteLeveling(PI) begin...
5305 14:47:20.558823 ==
5306 14:47:20.558897 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 14:47:20.565708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 14:47:20.565790 ==
5309 14:47:20.569098 Write leveling (Byte 0): 33 => 33
5310 14:47:20.572202 Write leveling (Byte 1): 33 => 33
5311 14:47:20.575681 DramcWriteLeveling(PI) end<-----
5312 14:47:20.575761
5313 14:47:20.575822 ==
5314 14:47:20.578764 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 14:47:20.582261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 14:47:20.582341 ==
5317 14:47:20.585930 [Gating] SW mode calibration
5318 14:47:20.592185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5319 14:47:20.596242 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5320 14:47:20.602485 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5321 14:47:20.605832 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5322 14:47:20.608922 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 14:47:20.615845 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 14:47:20.619326 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 14:47:20.622496 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 14:47:20.629716 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5327 14:47:20.632376 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5328 14:47:20.635420 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5329 14:47:20.642644 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 14:47:20.645752 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 14:47:20.648680 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 14:47:20.655426 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 14:47:20.660183 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 14:47:20.662226 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 14:47:20.669022 0 15 28 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
5336 14:47:20.672808 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5337 14:47:20.675442 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5338 14:47:20.682792 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 14:47:20.685601 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 14:47:20.689464 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 14:47:20.692821 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 14:47:20.699457 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5343 14:47:20.702523 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5344 14:47:20.705308 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5345 14:47:20.712291 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 14:47:20.715551 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 14:47:20.718772 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 14:47:20.725655 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 14:47:20.728700 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 14:47:20.732164 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 14:47:20.739043 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 14:47:20.742284 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 14:47:20.745200 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 14:47:20.752464 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 14:47:20.755883 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 14:47:20.759331 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 14:47:20.765571 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 14:47:20.768623 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5359 14:47:20.771942 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 14:47:20.775212 Total UI for P1: 0, mck2ui 16
5361 14:47:20.779451 best dqsien dly found for B0: ( 1, 2, 24)
5362 14:47:20.785457 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5363 14:47:20.788767 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 14:47:20.792376 Total UI for P1: 0, mck2ui 16
5365 14:47:20.795777 best dqsien dly found for B1: ( 1, 2, 30)
5366 14:47:20.798994 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5367 14:47:20.802281 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5368 14:47:20.802361
5369 14:47:20.805988 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5370 14:47:20.808633 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5371 14:47:20.812490 [Gating] SW calibration Done
5372 14:47:20.812569 ==
5373 14:47:20.815576 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 14:47:20.819130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 14:47:20.819210 ==
5376 14:47:20.822328 RX Vref Scan: 0
5377 14:47:20.822408
5378 14:47:20.822471 RX Vref 0 -> 0, step: 1
5379 14:47:20.825490
5380 14:47:20.825569 RX Delay -80 -> 252, step: 8
5381 14:47:20.832531 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5382 14:47:20.835535 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5383 14:47:20.839215 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5384 14:47:20.842158 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5385 14:47:20.845691 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5386 14:47:20.849550 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5387 14:47:20.852299 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5388 14:47:20.858739 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5389 14:47:20.862052 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5390 14:47:20.865461 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5391 14:47:20.868950 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5392 14:47:20.872531 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5393 14:47:20.878781 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5394 14:47:20.882023 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5395 14:47:20.885670 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5396 14:47:20.888785 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5397 14:47:20.888865 ==
5398 14:47:20.891942 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 14:47:20.895603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 14:47:20.895684 ==
5401 14:47:20.899346 DQS Delay:
5402 14:47:20.899426 DQS0 = 0, DQS1 = 0
5403 14:47:20.902189 DQM Delay:
5404 14:47:20.902269 DQM0 = 97, DQM1 = 87
5405 14:47:20.902331 DQ Delay:
5406 14:47:20.905840 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5407 14:47:20.909115 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5408 14:47:20.912076 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5409 14:47:20.915440 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5410 14:47:20.915521
5411 14:47:20.915583
5412 14:47:20.918660 ==
5413 14:47:20.918740 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 14:47:20.925556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 14:47:20.925636 ==
5416 14:47:20.925699
5417 14:47:20.925757
5418 14:47:20.929256 TX Vref Scan disable
5419 14:47:20.929335 == TX Byte 0 ==
5420 14:47:20.932031 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5421 14:47:20.938648 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5422 14:47:20.938728 == TX Byte 1 ==
5423 14:47:20.942258 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5424 14:47:20.948802 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5425 14:47:20.948908 ==
5426 14:47:20.952283 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 14:47:20.955300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 14:47:20.955380 ==
5429 14:47:20.955443
5430 14:47:20.955501
5431 14:47:20.958807 TX Vref Scan disable
5432 14:47:20.962120 == TX Byte 0 ==
5433 14:47:20.965576 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5434 14:47:20.968681 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5435 14:47:20.972278 == TX Byte 1 ==
5436 14:47:20.975960 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5437 14:47:20.979298 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5438 14:47:20.979378
5439 14:47:20.979440 [DATLAT]
5440 14:47:20.982291 Freq=933, CH0 RK1
5441 14:47:20.982371
5442 14:47:20.982434 DATLAT Default: 0xb
5443 14:47:20.985550 0, 0xFFFF, sum = 0
5444 14:47:20.988597 1, 0xFFFF, sum = 0
5445 14:47:20.988678 2, 0xFFFF, sum = 0
5446 14:47:20.992199 3, 0xFFFF, sum = 0
5447 14:47:20.992283 4, 0xFFFF, sum = 0
5448 14:47:20.995644 5, 0xFFFF, sum = 0
5449 14:47:20.995725 6, 0xFFFF, sum = 0
5450 14:47:20.998852 7, 0xFFFF, sum = 0
5451 14:47:20.998933 8, 0xFFFF, sum = 0
5452 14:47:21.002322 9, 0xFFFF, sum = 0
5453 14:47:21.002404 10, 0x0, sum = 1
5454 14:47:21.005940 11, 0x0, sum = 2
5455 14:47:21.006021 12, 0x0, sum = 3
5456 14:47:21.009438 13, 0x0, sum = 4
5457 14:47:21.009518 best_step = 11
5458 14:47:21.009581
5459 14:47:21.009638 ==
5460 14:47:21.012286 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 14:47:21.015778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 14:47:21.015858 ==
5463 14:47:21.018914 RX Vref Scan: 0
5464 14:47:21.018994
5465 14:47:21.022411 RX Vref 0 -> 0, step: 1
5466 14:47:21.022495
5467 14:47:21.022577 RX Delay -61 -> 252, step: 4
5468 14:47:21.030204 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5469 14:47:21.033233 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5470 14:47:21.036609 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5471 14:47:21.040201 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5472 14:47:21.042948 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5473 14:47:21.046704 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5474 14:47:21.052917 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5475 14:47:21.056320 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5476 14:47:21.060202 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5477 14:47:21.063282 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5478 14:47:21.066346 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5479 14:47:21.070793 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5480 14:47:21.076174 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5481 14:47:21.079993 iDelay=199, Bit 13, Center 92 (7 ~ 178) 172
5482 14:47:21.083413 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5483 14:47:21.086689 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5484 14:47:21.086771 ==
5485 14:47:21.089817 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 14:47:21.093764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 14:47:21.096532 ==
5488 14:47:21.096637 DQS Delay:
5489 14:47:21.096729 DQS0 = 0, DQS1 = 0
5490 14:47:21.101388 DQM Delay:
5491 14:47:21.101460 DQM0 = 96, DQM1 = 88
5492 14:47:21.103997 DQ Delay:
5493 14:47:21.104068 DQ0 =98, DQ1 =96, DQ2 =92, DQ3 =94
5494 14:47:21.106371 DQ4 =96, DQ5 =84, DQ6 =106, DQ7 =104
5495 14:47:21.110121 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =80
5496 14:47:21.113424 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5497 14:47:21.116261
5498 14:47:21.116332
5499 14:47:21.123437 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5500 14:47:21.126652 CH0 RK1: MR19=505, MR18=1D0B
5501 14:47:21.133168 CH0_RK1: MR19=0x505, MR18=0x1D0B, DQSOSC=412, MR23=63, INC=63, DEC=42
5502 14:47:21.133238 [RxdqsGatingPostProcess] freq 933
5503 14:47:21.140080 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5504 14:47:21.143769 best DQS0 dly(2T, 0.5T) = (0, 11)
5505 14:47:21.146923 best DQS1 dly(2T, 0.5T) = (0, 11)
5506 14:47:21.150012 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5507 14:47:21.153511 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5508 14:47:21.156658 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 14:47:21.160926 best DQS1 dly(2T, 0.5T) = (0, 10)
5510 14:47:21.163714 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 14:47:21.166416 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5512 14:47:21.170399 Pre-setting of DQS Precalculation
5513 14:47:21.173523 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5514 14:47:21.173592 ==
5515 14:47:21.176321 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 14:47:21.180511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 14:47:21.183289 ==
5518 14:47:21.186897 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 14:47:21.193353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5520 14:47:21.196792 [CA 0] Center 36 (6~67) winsize 62
5521 14:47:21.199427 [CA 1] Center 36 (6~67) winsize 62
5522 14:47:21.202961 [CA 2] Center 34 (4~65) winsize 62
5523 14:47:21.206367 [CA 3] Center 33 (3~64) winsize 62
5524 14:47:21.209764 [CA 4] Center 34 (3~65) winsize 63
5525 14:47:21.212968 [CA 5] Center 33 (3~64) winsize 62
5526 14:47:21.213075
5527 14:47:21.216908 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5528 14:47:21.216983
5529 14:47:21.219734 [CATrainingPosCal] consider 1 rank data
5530 14:47:21.222789 u2DelayCellTimex100 = 270/100 ps
5531 14:47:21.226535 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 14:47:21.229723 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5533 14:47:21.232750 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5534 14:47:21.236237 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 14:47:21.242911 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5536 14:47:21.246671 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 14:47:21.246768
5538 14:47:21.249931 CA PerBit enable=1, Macro0, CA PI delay=33
5539 14:47:21.249998
5540 14:47:21.253345 [CBTSetCACLKResult] CA Dly = 33
5541 14:47:21.253411 CS Dly: 4 (0~35)
5542 14:47:21.253468 ==
5543 14:47:21.256388 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 14:47:21.259574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 14:47:21.263005 ==
5546 14:47:21.266378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 14:47:21.272798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5548 14:47:21.276070 [CA 0] Center 36 (6~67) winsize 62
5549 14:47:21.279545 [CA 1] Center 37 (7~67) winsize 61
5550 14:47:21.283189 [CA 2] Center 34 (4~64) winsize 61
5551 14:47:21.285756 [CA 3] Center 33 (3~64) winsize 62
5552 14:47:21.290012 [CA 4] Center 34 (4~64) winsize 61
5553 14:47:21.293244 [CA 5] Center 33 (3~63) winsize 61
5554 14:47:21.293317
5555 14:47:21.296051 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5556 14:47:21.296122
5557 14:47:21.299113 [CATrainingPosCal] consider 2 rank data
5558 14:47:21.302826 u2DelayCellTimex100 = 270/100 ps
5559 14:47:21.305832 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 14:47:21.309478 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5561 14:47:21.312348 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5562 14:47:21.320007 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5563 14:47:21.322547 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5564 14:47:21.326179 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5565 14:47:21.326248
5566 14:47:21.329100 CA PerBit enable=1, Macro0, CA PI delay=33
5567 14:47:21.329164
5568 14:47:21.333078 [CBTSetCACLKResult] CA Dly = 33
5569 14:47:21.333145 CS Dly: 5 (0~37)
5570 14:47:21.333202
5571 14:47:21.335774 ----->DramcWriteLeveling(PI) begin...
5572 14:47:21.335842 ==
5573 14:47:21.339357 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 14:47:21.347165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 14:47:21.347242 ==
5576 14:47:21.349489 Write leveling (Byte 0): 25 => 25
5577 14:47:21.349559 Write leveling (Byte 1): 31 => 31
5578 14:47:21.352732 DramcWriteLeveling(PI) end<-----
5579 14:47:21.352797
5580 14:47:21.356493 ==
5581 14:47:21.356587 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 14:47:21.362827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 14:47:21.362899 ==
5584 14:47:21.365855 [Gating] SW mode calibration
5585 14:47:21.372779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5586 14:47:21.375916 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5587 14:47:21.382432 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5588 14:47:21.386511 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 14:47:21.389815 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 14:47:21.395708 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 14:47:21.399424 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 14:47:21.402629 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5593 14:47:21.409203 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 14:47:21.412380 0 14 28 | B1->B0 | 2f2f 3232 | 1 0 | (1 1) (0 1)
5595 14:47:21.415883 0 15 0 | B1->B0 | 2b2b 2929 | 0 0 | (0 0) (0 0)
5596 14:47:21.422958 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 14:47:21.426208 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 14:47:21.429201 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 14:47:21.432946 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 14:47:21.439118 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 14:47:21.442586 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 14:47:21.445667 0 15 28 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
5603 14:47:21.452316 1 0 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
5604 14:47:21.455869 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 14:47:21.459506 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 14:47:21.465943 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 14:47:21.469356 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 14:47:21.472942 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 14:47:21.479205 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 14:47:21.482842 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5611 14:47:21.485999 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5612 14:47:21.492893 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 14:47:21.496429 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 14:47:21.499480 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 14:47:21.506057 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 14:47:21.510107 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 14:47:21.513171 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 14:47:21.516042 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 14:47:21.522666 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 14:47:21.526468 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 14:47:21.529514 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 14:47:21.537012 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 14:47:21.539611 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 14:47:21.542846 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 14:47:21.549441 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 14:47:21.552940 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5627 14:47:21.556191 Total UI for P1: 0, mck2ui 16
5628 14:47:21.559425 best dqsien dly found for B0: ( 1, 2, 26)
5629 14:47:21.563052 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5630 14:47:21.569409 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 14:47:21.569483 Total UI for P1: 0, mck2ui 16
5632 14:47:21.572903 best dqsien dly found for B1: ( 1, 2, 30)
5633 14:47:21.579508 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5634 14:47:21.583000 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5635 14:47:21.583069
5636 14:47:21.586179 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5637 14:47:21.589632 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5638 14:47:21.592562 [Gating] SW calibration Done
5639 14:47:21.592630 ==
5640 14:47:21.596139 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 14:47:21.599775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 14:47:21.599847 ==
5643 14:47:21.602815 RX Vref Scan: 0
5644 14:47:21.602885
5645 14:47:21.602947 RX Vref 0 -> 0, step: 1
5646 14:47:21.603005
5647 14:47:21.606697 RX Delay -80 -> 252, step: 8
5648 14:47:21.609832 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5649 14:47:21.612570 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5650 14:47:21.619726 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5651 14:47:21.622665 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5652 14:47:21.626575 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5653 14:47:21.629530 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5654 14:47:21.632845 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5655 14:47:21.636271 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5656 14:47:21.643639 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5657 14:47:21.645943 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5658 14:47:21.649559 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5659 14:47:21.652537 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5660 14:47:21.656292 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5661 14:47:21.662654 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5662 14:47:21.666100 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5663 14:47:21.669350 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5664 14:47:21.669419 ==
5665 14:47:21.672736 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 14:47:21.676302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 14:47:21.676372 ==
5668 14:47:21.679577 DQS Delay:
5669 14:47:21.679646 DQS0 = 0, DQS1 = 0
5670 14:47:21.679703 DQM Delay:
5671 14:47:21.683068 DQM0 = 96, DQM1 = 88
5672 14:47:21.683156 DQ Delay:
5673 14:47:21.685947 DQ0 =99, DQ1 =95, DQ2 =87, DQ3 =95
5674 14:47:21.690132 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5675 14:47:21.692825 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5676 14:47:21.696434 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5677 14:47:21.696516
5678 14:47:21.696599
5679 14:47:21.696678 ==
5680 14:47:21.699258 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 14:47:21.706078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 14:47:21.706161 ==
5683 14:47:21.706244
5684 14:47:21.706323
5685 14:47:21.706399 TX Vref Scan disable
5686 14:47:21.709293 == TX Byte 0 ==
5687 14:47:21.712959 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5688 14:47:21.716641 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5689 14:47:21.719611 == TX Byte 1 ==
5690 14:47:21.723775 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5691 14:47:21.729674 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5692 14:47:21.729752 ==
5693 14:47:21.732848 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 14:47:21.736353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 14:47:21.736423 ==
5696 14:47:21.736486
5697 14:47:21.736542
5698 14:47:21.739279 TX Vref Scan disable
5699 14:47:21.739344 == TX Byte 0 ==
5700 14:47:21.746261 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5701 14:47:21.749759 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5702 14:47:21.749834 == TX Byte 1 ==
5703 14:47:21.756358 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5704 14:47:21.759148 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5705 14:47:21.759216
5706 14:47:21.759278 [DATLAT]
5707 14:47:21.762503 Freq=933, CH1 RK0
5708 14:47:21.762570
5709 14:47:21.762626 DATLAT Default: 0xd
5710 14:47:21.766299 0, 0xFFFF, sum = 0
5711 14:47:21.766371 1, 0xFFFF, sum = 0
5712 14:47:21.769499 2, 0xFFFF, sum = 0
5713 14:47:21.769571 3, 0xFFFF, sum = 0
5714 14:47:21.772654 4, 0xFFFF, sum = 0
5715 14:47:21.772720 5, 0xFFFF, sum = 0
5716 14:47:21.775968 6, 0xFFFF, sum = 0
5717 14:47:21.779557 7, 0xFFFF, sum = 0
5718 14:47:21.779630 8, 0xFFFF, sum = 0
5719 14:47:21.782809 9, 0xFFFF, sum = 0
5720 14:47:21.782887 10, 0x0, sum = 1
5721 14:47:21.782949 11, 0x0, sum = 2
5722 14:47:21.786025 12, 0x0, sum = 3
5723 14:47:21.786114 13, 0x0, sum = 4
5724 14:47:21.789364 best_step = 11
5725 14:47:21.789446
5726 14:47:21.789530 ==
5727 14:47:21.793295 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 14:47:21.796211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 14:47:21.796294 ==
5730 14:47:21.799379 RX Vref Scan: 1
5731 14:47:21.799461
5732 14:47:21.799545 RX Vref 0 -> 0, step: 1
5733 14:47:21.799624
5734 14:47:21.803133 RX Delay -61 -> 252, step: 4
5735 14:47:21.803216
5736 14:47:21.805934 Set Vref, RX VrefLevel [Byte0]: 56
5737 14:47:21.809369 [Byte1]: 45
5738 14:47:21.813858
5739 14:47:21.813940 Final RX Vref Byte 0 = 56 to rank0
5740 14:47:21.818704 Final RX Vref Byte 1 = 45 to rank0
5741 14:47:21.822842 Final RX Vref Byte 0 = 56 to rank1
5742 14:47:21.823303 Final RX Vref Byte 1 = 45 to rank1==
5743 14:47:21.827280 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 14:47:21.833426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 14:47:21.833510 ==
5746 14:47:21.833593 DQS Delay:
5747 14:47:21.833670 DQS0 = 0, DQS1 = 0
5748 14:47:21.836560 DQM Delay:
5749 14:47:21.836646 DQM0 = 97, DQM1 = 90
5750 14:47:21.840172 DQ Delay:
5751 14:47:21.843711 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5752 14:47:21.846859 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5753 14:47:21.849960 DQ8 =78, DQ9 =78, DQ10 =92, DQ11 =88
5754 14:47:21.853792 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =94
5755 14:47:21.853874
5756 14:47:21.853957
5757 14:47:21.860131 [DQSOSCAuto] RK0, (LSB)MR18= 0x15f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 415 ps
5758 14:47:21.863428 CH1 RK0: MR19=504, MR18=15F2
5759 14:47:21.870714 CH1_RK0: MR19=0x504, MR18=0x15F2, DQSOSC=415, MR23=63, INC=62, DEC=41
5760 14:47:21.870797
5761 14:47:21.873669 ----->DramcWriteLeveling(PI) begin...
5762 14:47:21.873753 ==
5763 14:47:21.877297 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 14:47:21.880262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 14:47:21.880344 ==
5766 14:47:21.883403 Write leveling (Byte 0): 26 => 26
5767 14:47:21.886763 Write leveling (Byte 1): 29 => 29
5768 14:47:21.889955 DramcWriteLeveling(PI) end<-----
5769 14:47:21.890038
5770 14:47:21.890120 ==
5771 14:47:21.893929 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 14:47:21.896556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 14:47:21.896664 ==
5774 14:47:21.900187 [Gating] SW mode calibration
5775 14:47:21.906950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5776 14:47:21.913869 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5777 14:47:21.917145 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 14:47:21.920375 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 14:47:21.926847 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 14:47:21.930196 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 14:47:21.933493 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 14:47:21.940066 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 14:47:21.943104 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5784 14:47:21.946908 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
5785 14:47:21.953360 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5786 14:47:21.956729 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 14:47:21.959924 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 14:47:21.966474 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 14:47:21.969970 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 14:47:21.973431 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 14:47:21.980107 0 15 24 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
5792 14:47:21.983820 0 15 28 | B1->B0 | 3838 4141 | 0 1 | (0 0) (0 0)
5793 14:47:21.986768 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 14:47:21.993923 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 14:47:21.996920 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 14:47:22.000106 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 14:47:22.004219 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 14:47:22.010194 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 14:47:22.013670 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5800 14:47:22.016998 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5801 14:47:22.023733 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 14:47:22.027193 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 14:47:22.030466 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 14:47:22.037256 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 14:47:22.040177 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 14:47:22.043931 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 14:47:22.051075 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 14:47:22.053611 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 14:47:22.057147 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 14:47:22.063857 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 14:47:22.067715 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 14:47:22.070598 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 14:47:22.076859 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 14:47:22.080249 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5815 14:47:22.083611 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5816 14:47:22.087263 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5817 14:47:22.091336 Total UI for P1: 0, mck2ui 16
5818 14:47:22.093850 best dqsien dly found for B0: ( 1, 2, 22)
5819 14:47:22.100730 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 14:47:22.103875 Total UI for P1: 0, mck2ui 16
5821 14:47:22.107809 best dqsien dly found for B1: ( 1, 2, 28)
5822 14:47:22.110245 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5823 14:47:22.113518 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5824 14:47:22.113599
5825 14:47:22.117264 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5826 14:47:22.120329 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5827 14:47:22.123323 [Gating] SW calibration Done
5828 14:47:22.123402 ==
5829 14:47:22.126918 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 14:47:22.130324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 14:47:22.130403 ==
5832 14:47:22.133795 RX Vref Scan: 0
5833 14:47:22.133874
5834 14:47:22.133937 RX Vref 0 -> 0, step: 1
5835 14:47:22.137303
5836 14:47:22.137382 RX Delay -80 -> 252, step: 8
5837 14:47:22.143632 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5838 14:47:22.146592 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5839 14:47:22.150279 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5840 14:47:22.153780 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5841 14:47:22.157152 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5842 14:47:22.160612 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5843 14:47:22.163535 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5844 14:47:22.170628 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5845 14:47:22.173242 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5846 14:47:22.176652 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5847 14:47:22.180369 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5848 14:47:22.183717 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5849 14:47:22.189971 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5850 14:47:22.193469 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5851 14:47:22.197010 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5852 14:47:22.200234 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5853 14:47:22.200305 ==
5854 14:47:22.203576 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 14:47:22.207185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 14:47:22.207255 ==
5857 14:47:22.209934 DQS Delay:
5858 14:47:22.210005 DQS0 = 0, DQS1 = 0
5859 14:47:22.213871 DQM Delay:
5860 14:47:22.213963 DQM0 = 94, DQM1 = 88
5861 14:47:22.214047 DQ Delay:
5862 14:47:22.217132 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5863 14:47:22.220470 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5864 14:47:22.223942 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5865 14:47:22.226876 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5866 14:47:22.226943
5867 14:47:22.227002
5868 14:47:22.230389 ==
5869 14:47:22.230456 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 14:47:22.237124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 14:47:22.237228 ==
5872 14:47:22.237292
5873 14:47:22.237352
5874 14:47:22.240463 TX Vref Scan disable
5875 14:47:22.240527 == TX Byte 0 ==
5876 14:47:22.243336 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5877 14:47:22.250066 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5878 14:47:22.250137 == TX Byte 1 ==
5879 14:47:22.253340 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5880 14:47:22.260104 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5881 14:47:22.260180 ==
5882 14:47:22.263398 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 14:47:22.267345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 14:47:22.267412 ==
5885 14:47:22.267474
5886 14:47:22.267530
5887 14:47:22.270388 TX Vref Scan disable
5888 14:47:22.274067 == TX Byte 0 ==
5889 14:47:22.276994 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5890 14:47:22.280291 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5891 14:47:22.283526 == TX Byte 1 ==
5892 14:47:22.287264 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5893 14:47:22.290205 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5894 14:47:22.290272
5895 14:47:22.290334 [DATLAT]
5896 14:47:22.293391 Freq=933, CH1 RK1
5897 14:47:22.293484
5898 14:47:22.293570 DATLAT Default: 0xb
5899 14:47:22.297478 0, 0xFFFF, sum = 0
5900 14:47:22.297550 1, 0xFFFF, sum = 0
5901 14:47:22.300138 2, 0xFFFF, sum = 0
5902 14:47:22.300206 3, 0xFFFF, sum = 0
5903 14:47:22.303598 4, 0xFFFF, sum = 0
5904 14:47:22.307359 5, 0xFFFF, sum = 0
5905 14:47:22.307437 6, 0xFFFF, sum = 0
5906 14:47:22.310383 7, 0xFFFF, sum = 0
5907 14:47:22.310450 8, 0xFFFF, sum = 0
5908 14:47:22.313408 9, 0xFFFF, sum = 0
5909 14:47:22.313473 10, 0x0, sum = 1
5910 14:47:22.317671 11, 0x0, sum = 2
5911 14:47:22.317746 12, 0x0, sum = 3
5912 14:47:22.317806 13, 0x0, sum = 4
5913 14:47:22.320434 best_step = 11
5914 14:47:22.320503
5915 14:47:22.320560 ==
5916 14:47:22.323697 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 14:47:22.326653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 14:47:22.326728 ==
5919 14:47:22.331346 RX Vref Scan: 0
5920 14:47:22.331419
5921 14:47:22.331484 RX Vref 0 -> 0, step: 1
5922 14:47:22.333524
5923 14:47:22.333588 RX Delay -61 -> 252, step: 4
5924 14:47:22.340882 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5925 14:47:22.344220 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5926 14:47:22.347763 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5927 14:47:22.351380 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5928 14:47:22.354326 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5929 14:47:22.358174 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5930 14:47:22.364544 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5931 14:47:22.367925 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5932 14:47:22.371703 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5933 14:47:22.375177 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5934 14:47:22.377969 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5935 14:47:22.384870 iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176
5936 14:47:22.388320 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5937 14:47:22.391593 iDelay=199, Bit 13, Center 96 (3 ~ 190) 188
5938 14:47:22.394747 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5939 14:47:22.397769 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5940 14:47:22.397840 ==
5941 14:47:22.400933 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 14:47:22.408181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 14:47:22.408257 ==
5944 14:47:22.408320 DQS Delay:
5945 14:47:22.408377 DQS0 = 0, DQS1 = 0
5946 14:47:22.411355 DQM Delay:
5947 14:47:22.411419 DQM0 = 94, DQM1 = 89
5948 14:47:22.414459 DQ Delay:
5949 14:47:22.418309 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5950 14:47:22.421334 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =90
5951 14:47:22.424646 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =82
5952 14:47:22.428064 DQ12 =94, DQ13 =96, DQ14 =100, DQ15 =96
5953 14:47:22.428132
5954 14:47:22.428191
5955 14:47:22.434624 [DQSOSCAuto] RK1, (LSB)MR18= 0x912, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 419 ps
5956 14:47:22.438000 CH1 RK1: MR19=505, MR18=912
5957 14:47:22.444416 CH1_RK1: MR19=0x505, MR18=0x912, DQSOSC=416, MR23=63, INC=62, DEC=41
5958 14:47:22.447818 [RxdqsGatingPostProcess] freq 933
5959 14:47:22.450966 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5960 14:47:22.455009 best DQS0 dly(2T, 0.5T) = (0, 10)
5961 14:47:22.457791 best DQS1 dly(2T, 0.5T) = (0, 10)
5962 14:47:22.461185 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5963 14:47:22.464187 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5964 14:47:22.467717 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 14:47:22.471337 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 14:47:22.474268 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 14:47:22.477529 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 14:47:22.480853 Pre-setting of DQS Precalculation
5969 14:47:22.484870 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5970 14:47:22.490959 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5971 14:47:22.501379 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5972 14:47:22.501478
5973 14:47:22.501563
5974 14:47:22.505387 [Calibration Summary] 1866 Mbps
5975 14:47:22.505456 CH 0, Rank 0
5976 14:47:22.508121 SW Impedance : PASS
5977 14:47:22.508186 DUTY Scan : NO K
5978 14:47:22.511156 ZQ Calibration : PASS
5979 14:47:22.511225 Jitter Meter : NO K
5980 14:47:22.514378 CBT Training : PASS
5981 14:47:22.517815 Write leveling : PASS
5982 14:47:22.517886 RX DQS gating : PASS
5983 14:47:22.521122 RX DQ/DQS(RDDQC) : PASS
5984 14:47:22.524467 TX DQ/DQS : PASS
5985 14:47:22.524536 RX DATLAT : PASS
5986 14:47:22.528221 RX DQ/DQS(Engine): PASS
5987 14:47:22.531220 TX OE : NO K
5988 14:47:22.531286 All Pass.
5989 14:47:22.531345
5990 14:47:22.531404 CH 0, Rank 1
5991 14:47:22.534788 SW Impedance : PASS
5992 14:47:22.538559 DUTY Scan : NO K
5993 14:47:22.538632 ZQ Calibration : PASS
5994 14:47:22.541483 Jitter Meter : NO K
5995 14:47:22.544680 CBT Training : PASS
5996 14:47:22.544744 Write leveling : PASS
5997 14:47:22.548320 RX DQS gating : PASS
5998 14:47:22.548388 RX DQ/DQS(RDDQC) : PASS
5999 14:47:22.551460 TX DQ/DQS : PASS
6000 14:47:22.555130 RX DATLAT : PASS
6001 14:47:22.555197 RX DQ/DQS(Engine): PASS
6002 14:47:22.558239 TX OE : NO K
6003 14:47:22.558308 All Pass.
6004 14:47:22.558370
6005 14:47:22.562861 CH 1, Rank 0
6006 14:47:22.562929 SW Impedance : PASS
6007 14:47:22.564254 DUTY Scan : NO K
6008 14:47:22.567509 ZQ Calibration : PASS
6009 14:47:22.567580 Jitter Meter : NO K
6010 14:47:22.571397 CBT Training : PASS
6011 14:47:22.574521 Write leveling : PASS
6012 14:47:22.574595 RX DQS gating : PASS
6013 14:47:22.577659 RX DQ/DQS(RDDQC) : PASS
6014 14:47:22.580927 TX DQ/DQS : PASS
6015 14:47:22.581001 RX DATLAT : PASS
6016 14:47:22.584211 RX DQ/DQS(Engine): PASS
6017 14:47:22.588221 TX OE : NO K
6018 14:47:22.588310 All Pass.
6019 14:47:22.588370
6020 14:47:22.588426 CH 1, Rank 1
6021 14:47:22.591013 SW Impedance : PASS
6022 14:47:22.594452 DUTY Scan : NO K
6023 14:47:22.594560 ZQ Calibration : PASS
6024 14:47:22.597866 Jitter Meter : NO K
6025 14:47:22.597934 CBT Training : PASS
6026 14:47:22.600941 Write leveling : PASS
6027 14:47:22.604646 RX DQS gating : PASS
6028 14:47:22.604738 RX DQ/DQS(RDDQC) : PASS
6029 14:47:22.608164 TX DQ/DQS : PASS
6030 14:47:22.611231 RX DATLAT : PASS
6031 14:47:22.611297 RX DQ/DQS(Engine): PASS
6032 14:47:22.614898 TX OE : NO K
6033 14:47:22.614967 All Pass.
6034 14:47:22.615024
6035 14:47:22.617729 DramC Write-DBI off
6036 14:47:22.621380 PER_BANK_REFRESH: Hybrid Mode
6037 14:47:22.621453 TX_TRACKING: ON
6038 14:47:22.631007 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6039 14:47:22.634838 [FAST_K] Save calibration result to emmc
6040 14:47:22.637519 dramc_set_vcore_voltage set vcore to 650000
6041 14:47:22.640819 Read voltage for 400, 6
6042 14:47:22.640912 Vio18 = 0
6043 14:47:22.641003 Vcore = 650000
6044 14:47:22.644494 Vdram = 0
6045 14:47:22.644560 Vddq = 0
6046 14:47:22.644621 Vmddr = 0
6047 14:47:22.651020 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6048 14:47:22.654981 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6049 14:47:22.658072 MEM_TYPE=3, freq_sel=20
6050 14:47:22.661323 sv_algorithm_assistance_LP4_800
6051 14:47:22.664785 ============ PULL DRAM RESETB DOWN ============
6052 14:47:22.668227 ========== PULL DRAM RESETB DOWN end =========
6053 14:47:22.674849 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6054 14:47:22.677340 ===================================
6055 14:47:22.677413 LPDDR4 DRAM CONFIGURATION
6056 14:47:22.681250 ===================================
6057 14:47:22.684205 EX_ROW_EN[0] = 0x0
6058 14:47:22.687776 EX_ROW_EN[1] = 0x0
6059 14:47:22.687848 LP4Y_EN = 0x0
6060 14:47:22.691767 WORK_FSP = 0x0
6061 14:47:22.691833 WL = 0x2
6062 14:47:22.694376 RL = 0x2
6063 14:47:22.694442 BL = 0x2
6064 14:47:22.697676 RPST = 0x0
6065 14:47:22.697746 RD_PRE = 0x0
6066 14:47:22.700955 WR_PRE = 0x1
6067 14:47:22.701031 WR_PST = 0x0
6068 14:47:22.704856 DBI_WR = 0x0
6069 14:47:22.704924 DBI_RD = 0x0
6070 14:47:22.707644 OTF = 0x1
6071 14:47:22.711060 ===================================
6072 14:47:22.714871 ===================================
6073 14:47:22.714945 ANA top config
6074 14:47:22.717771 ===================================
6075 14:47:22.721611 DLL_ASYNC_EN = 0
6076 14:47:22.724491 ALL_SLAVE_EN = 1
6077 14:47:22.724557 NEW_RANK_MODE = 1
6078 14:47:22.727754 DLL_IDLE_MODE = 1
6079 14:47:22.730867 LP45_APHY_COMB_EN = 1
6080 14:47:22.735056 TX_ODT_DIS = 1
6081 14:47:22.738035 NEW_8X_MODE = 1
6082 14:47:22.741364 ===================================
6083 14:47:22.744462 ===================================
6084 14:47:22.744526 data_rate = 800
6085 14:47:22.747977 CKR = 1
6086 14:47:22.751199 DQ_P2S_RATIO = 4
6087 14:47:22.754671 ===================================
6088 14:47:22.758487 CA_P2S_RATIO = 4
6089 14:47:22.761491 DQ_CA_OPEN = 0
6090 14:47:22.764313 DQ_SEMI_OPEN = 1
6091 14:47:22.764383 CA_SEMI_OPEN = 1
6092 14:47:22.767784 CA_FULL_RATE = 0
6093 14:47:22.771239 DQ_CKDIV4_EN = 0
6094 14:47:22.774334 CA_CKDIV4_EN = 1
6095 14:47:22.778301 CA_PREDIV_EN = 0
6096 14:47:22.778371 PH8_DLY = 0
6097 14:47:22.782497 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6098 14:47:22.785205 DQ_AAMCK_DIV = 0
6099 14:47:22.787969 CA_AAMCK_DIV = 0
6100 14:47:22.791282 CA_ADMCK_DIV = 4
6101 14:47:22.794605 DQ_TRACK_CA_EN = 0
6102 14:47:22.794702 CA_PICK = 800
6103 14:47:22.798561 CA_MCKIO = 400
6104 14:47:22.801678 MCKIO_SEMI = 400
6105 14:47:22.804999 PLL_FREQ = 3016
6106 14:47:22.808552 DQ_UI_PI_RATIO = 32
6107 14:47:22.811795 CA_UI_PI_RATIO = 32
6108 14:47:22.814860 ===================================
6109 14:47:22.818576 ===================================
6110 14:47:22.821136 memory_type:LPDDR4
6111 14:47:22.821207 GP_NUM : 10
6112 14:47:22.825623 SRAM_EN : 1
6113 14:47:22.825693 MD32_EN : 0
6114 14:47:22.828057 ===================================
6115 14:47:22.831690 [ANA_INIT] >>>>>>>>>>>>>>
6116 14:47:22.834846 <<<<<< [CONFIGURE PHASE]: ANA_TX
6117 14:47:22.838020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6118 14:47:22.842008 ===================================
6119 14:47:22.845071 data_rate = 800,PCW = 0X7400
6120 14:47:22.848505 ===================================
6121 14:47:22.851490 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6122 14:47:22.854831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6123 14:47:22.868053 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6124 14:47:22.871472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6125 14:47:22.875124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6126 14:47:22.879547 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6127 14:47:22.881489 [ANA_INIT] flow start
6128 14:47:22.884641 [ANA_INIT] PLL >>>>>>>>
6129 14:47:22.884712 [ANA_INIT] PLL <<<<<<<<
6130 14:47:22.887847 [ANA_INIT] MIDPI >>>>>>>>
6131 14:47:22.891528 [ANA_INIT] MIDPI <<<<<<<<
6132 14:47:22.891601 [ANA_INIT] DLL >>>>>>>>
6133 14:47:22.894780 [ANA_INIT] flow end
6134 14:47:22.898050 ============ LP4 DIFF to SE enter ============
6135 14:47:22.901604 ============ LP4 DIFF to SE exit ============
6136 14:47:22.904986 [ANA_INIT] <<<<<<<<<<<<<
6137 14:47:22.908166 [Flow] Enable top DCM control >>>>>
6138 14:47:22.911294 [Flow] Enable top DCM control <<<<<
6139 14:47:22.914587 Enable DLL master slave shuffle
6140 14:47:22.921499 ==============================================================
6141 14:47:22.921601 Gating Mode config
6142 14:47:22.928002 ==============================================================
6143 14:47:22.928079 Config description:
6144 14:47:22.938788 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6145 14:47:22.944691 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6146 14:47:22.951259 SELPH_MODE 0: By rank 1: By Phase
6147 14:47:22.954598 ==============================================================
6148 14:47:22.958011 GAT_TRACK_EN = 0
6149 14:47:22.961377 RX_GATING_MODE = 2
6150 14:47:22.964780 RX_GATING_TRACK_MODE = 2
6151 14:47:22.968222 SELPH_MODE = 1
6152 14:47:22.971592 PICG_EARLY_EN = 1
6153 14:47:22.974537 VALID_LAT_VALUE = 1
6154 14:47:22.978470 ==============================================================
6155 14:47:22.981254 Enter into Gating configuration >>>>
6156 14:47:22.984579 Exit from Gating configuration <<<<
6157 14:47:22.988267 Enter into DVFS_PRE_config >>>>>
6158 14:47:23.001262 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6159 14:47:23.005091 Exit from DVFS_PRE_config <<<<<
6160 14:47:23.008156 Enter into PICG configuration >>>>
6161 14:47:23.008230 Exit from PICG configuration <<<<
6162 14:47:23.011571 [RX_INPUT] configuration >>>>>
6163 14:47:23.015125 [RX_INPUT] configuration <<<<<
6164 14:47:23.021648 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6165 14:47:23.025040 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6166 14:47:23.031897 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6167 14:47:23.038495 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6168 14:47:23.044934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6169 14:47:23.051980 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6170 14:47:23.055272 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6171 14:47:23.058251 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6172 14:47:23.061471 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6173 14:47:23.068293 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6174 14:47:23.072145 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6175 14:47:23.074901 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6176 14:47:23.078586 ===================================
6177 14:47:23.081939 LPDDR4 DRAM CONFIGURATION
6178 14:47:23.084952 ===================================
6179 14:47:23.085059 EX_ROW_EN[0] = 0x0
6180 14:47:23.088080 EX_ROW_EN[1] = 0x0
6181 14:47:23.092144 LP4Y_EN = 0x0
6182 14:47:23.092240 WORK_FSP = 0x0
6183 14:47:23.095218 WL = 0x2
6184 14:47:23.095297 RL = 0x2
6185 14:47:23.098647 BL = 0x2
6186 14:47:23.098727 RPST = 0x0
6187 14:47:23.101644 RD_PRE = 0x0
6188 14:47:23.101723 WR_PRE = 0x1
6189 14:47:23.105667 WR_PST = 0x0
6190 14:47:23.105747 DBI_WR = 0x0
6191 14:47:23.108440 DBI_RD = 0x0
6192 14:47:23.108520 OTF = 0x1
6193 14:47:23.111912 ===================================
6194 14:47:23.114965 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6195 14:47:23.122145 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6196 14:47:23.124961 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 14:47:23.128826 ===================================
6198 14:47:23.131450 LPDDR4 DRAM CONFIGURATION
6199 14:47:23.135200 ===================================
6200 14:47:23.135280 EX_ROW_EN[0] = 0x10
6201 14:47:23.138940 EX_ROW_EN[1] = 0x0
6202 14:47:23.139019 LP4Y_EN = 0x0
6203 14:47:23.141743 WORK_FSP = 0x0
6204 14:47:23.141823 WL = 0x2
6205 14:47:23.145286 RL = 0x2
6206 14:47:23.145365 BL = 0x2
6207 14:47:23.148695 RPST = 0x0
6208 14:47:23.148799 RD_PRE = 0x0
6209 14:47:23.152834 WR_PRE = 0x1
6210 14:47:23.152914 WR_PST = 0x0
6211 14:47:23.155221 DBI_WR = 0x0
6212 14:47:23.158440 DBI_RD = 0x0
6213 14:47:23.158519 OTF = 0x1
6214 14:47:23.162099 ===================================
6215 14:47:23.168765 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6216 14:47:23.172231 nWR fixed to 30
6217 14:47:23.175576 [ModeRegInit_LP4] CH0 RK0
6218 14:47:23.175656 [ModeRegInit_LP4] CH0 RK1
6219 14:47:23.179028 [ModeRegInit_LP4] CH1 RK0
6220 14:47:23.182491 [ModeRegInit_LP4] CH1 RK1
6221 14:47:23.182571 match AC timing 19
6222 14:47:23.188480 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6223 14:47:23.192036 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6224 14:47:23.195267 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6225 14:47:23.201960 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6226 14:47:23.206182 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6227 14:47:23.206262 ==
6228 14:47:23.208647 Dram Type= 6, Freq= 0, CH_0, rank 0
6229 14:47:23.212860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 14:47:23.212966 ==
6231 14:47:23.218854 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 14:47:23.225430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6233 14:47:23.228552 [CA 0] Center 36 (8~64) winsize 57
6234 14:47:23.232230 [CA 1] Center 36 (8~64) winsize 57
6235 14:47:23.232310 [CA 2] Center 36 (8~64) winsize 57
6236 14:47:23.235078 [CA 3] Center 36 (8~64) winsize 57
6237 14:47:23.239052 [CA 4] Center 36 (8~64) winsize 57
6238 14:47:23.241859 [CA 5] Center 36 (8~64) winsize 57
6239 14:47:23.241939
6240 14:47:23.245123 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6241 14:47:23.245203
6242 14:47:23.251845 [CATrainingPosCal] consider 1 rank data
6243 14:47:23.251926 u2DelayCellTimex100 = 270/100 ps
6244 14:47:23.258461 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 14:47:23.261909 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 14:47:23.265234 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 14:47:23.268841 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 14:47:23.272161 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 14:47:23.275442 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 14:47:23.275522
6251 14:47:23.278457 CA PerBit enable=1, Macro0, CA PI delay=36
6252 14:47:23.278537
6253 14:47:23.283160 [CBTSetCACLKResult] CA Dly = 36
6254 14:47:23.283239 CS Dly: 1 (0~32)
6255 14:47:23.285804 ==
6256 14:47:23.288557 Dram Type= 6, Freq= 0, CH_0, rank 1
6257 14:47:23.291835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 14:47:23.291908 ==
6259 14:47:23.295258 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6260 14:47:23.301816 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6261 14:47:23.305883 [CA 0] Center 36 (8~64) winsize 57
6262 14:47:23.308683 [CA 1] Center 36 (8~64) winsize 57
6263 14:47:23.312296 [CA 2] Center 36 (8~64) winsize 57
6264 14:47:23.315615 [CA 3] Center 36 (8~64) winsize 57
6265 14:47:23.318847 [CA 4] Center 36 (8~64) winsize 57
6266 14:47:23.322581 [CA 5] Center 36 (8~64) winsize 57
6267 14:47:23.322660
6268 14:47:23.325491 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6269 14:47:23.325570
6270 14:47:23.329208 [CATrainingPosCal] consider 2 rank data
6271 14:47:23.332050 u2DelayCellTimex100 = 270/100 ps
6272 14:47:23.335761 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 14:47:23.338601 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 14:47:23.342757 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 14:47:23.345250 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 14:47:23.349338 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 14:47:23.355491 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 14:47:23.355572
6279 14:47:23.358620 CA PerBit enable=1, Macro0, CA PI delay=36
6280 14:47:23.358700
6281 14:47:23.362274 [CBTSetCACLKResult] CA Dly = 36
6282 14:47:23.362353 CS Dly: 1 (0~32)
6283 14:47:23.362416
6284 14:47:23.365461 ----->DramcWriteLeveling(PI) begin...
6285 14:47:23.365542 ==
6286 14:47:23.368440 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 14:47:23.372193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 14:47:23.375574 ==
6289 14:47:23.375654 Write leveling (Byte 0): 40 => 8
6290 14:47:23.378503 Write leveling (Byte 1): 32 => 0
6291 14:47:23.381922 DramcWriteLeveling(PI) end<-----
6292 14:47:23.382001
6293 14:47:23.382063 ==
6294 14:47:23.385013 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 14:47:23.392021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 14:47:23.392101 ==
6297 14:47:23.392163 [Gating] SW mode calibration
6298 14:47:23.402166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6299 14:47:23.405983 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6300 14:47:23.409157 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6301 14:47:23.415926 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6302 14:47:23.419615 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 14:47:23.421895 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 14:47:23.428497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 14:47:23.433379 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 14:47:23.435982 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 14:47:23.442197 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 14:47:23.445393 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 14:47:23.449317 Total UI for P1: 0, mck2ui 16
6310 14:47:23.451977 best dqsien dly found for B0: ( 0, 14, 24)
6311 14:47:23.455702 Total UI for P1: 0, mck2ui 16
6312 14:47:23.458624 best dqsien dly found for B1: ( 0, 14, 24)
6313 14:47:23.462059 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6314 14:47:23.465299 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6315 14:47:23.465378
6316 14:47:23.469364 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6317 14:47:23.472759 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6318 14:47:23.475631 [Gating] SW calibration Done
6319 14:47:23.475710 ==
6320 14:47:23.478584 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 14:47:23.482026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 14:47:23.485780 ==
6323 14:47:23.485858 RX Vref Scan: 0
6324 14:47:23.485920
6325 14:47:23.489136 RX Vref 0 -> 0, step: 1
6326 14:47:23.489215
6327 14:47:23.491950 RX Delay -410 -> 252, step: 16
6328 14:47:23.495222 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6329 14:47:23.498310 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6330 14:47:23.502563 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6331 14:47:23.508831 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6332 14:47:23.512462 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6333 14:47:23.515089 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6334 14:47:23.518652 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6335 14:47:23.525422 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6336 14:47:23.528471 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6337 14:47:23.532084 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6338 14:47:23.535340 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6339 14:47:23.542187 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6340 14:47:23.545303 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6341 14:47:23.549008 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6342 14:47:23.552571 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6343 14:47:23.559696 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6344 14:47:23.559775 ==
6345 14:47:23.562511 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 14:47:23.565812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 14:47:23.565891 ==
6348 14:47:23.565975 DQS Delay:
6349 14:47:23.568737 DQS0 = 35, DQS1 = 51
6350 14:47:23.568816 DQM Delay:
6351 14:47:23.572023 DQM0 = 8, DQM1 = 11
6352 14:47:23.572102 DQ Delay:
6353 14:47:23.575454 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6354 14:47:23.580432 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6355 14:47:23.582246 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6356 14:47:23.585526 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6357 14:47:23.585606
6358 14:47:23.585668
6359 14:47:23.585726 ==
6360 14:47:23.588847 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 14:47:23.592242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 14:47:23.592319 ==
6363 14:47:23.592382
6364 14:47:23.592439
6365 14:47:23.595966 TX Vref Scan disable
6366 14:47:23.596037 == TX Byte 0 ==
6367 14:47:23.602616 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 14:47:23.605746 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 14:47:23.605813 == TX Byte 1 ==
6370 14:47:23.612063 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6371 14:47:23.615532 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6372 14:47:23.615602 ==
6373 14:47:23.618571 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 14:47:23.622120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 14:47:23.622189 ==
6376 14:47:23.622248
6377 14:47:23.622306
6378 14:47:23.625724 TX Vref Scan disable
6379 14:47:23.625788 == TX Byte 0 ==
6380 14:47:23.632202 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6381 14:47:23.635871 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6382 14:47:23.635939 == TX Byte 1 ==
6383 14:47:23.642387 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6384 14:47:23.645607 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6385 14:47:23.645683
6386 14:47:23.645744 [DATLAT]
6387 14:47:23.648703 Freq=400, CH0 RK0
6388 14:47:23.648767
6389 14:47:23.648823 DATLAT Default: 0xf
6390 14:47:23.651996 0, 0xFFFF, sum = 0
6391 14:47:23.652063 1, 0xFFFF, sum = 0
6392 14:47:23.655074 2, 0xFFFF, sum = 0
6393 14:47:23.655143 3, 0xFFFF, sum = 0
6394 14:47:23.658966 4, 0xFFFF, sum = 0
6395 14:47:23.662099 5, 0xFFFF, sum = 0
6396 14:47:23.662165 6, 0xFFFF, sum = 0
6397 14:47:23.665333 7, 0xFFFF, sum = 0
6398 14:47:23.665403 8, 0xFFFF, sum = 0
6399 14:47:23.668518 9, 0xFFFF, sum = 0
6400 14:47:23.668583 10, 0xFFFF, sum = 0
6401 14:47:23.671864 11, 0xFFFF, sum = 0
6402 14:47:23.671932 12, 0xFFFF, sum = 0
6403 14:47:23.675268 13, 0x0, sum = 1
6404 14:47:23.675350 14, 0x0, sum = 2
6405 14:47:23.678637 15, 0x0, sum = 3
6406 14:47:23.678718 16, 0x0, sum = 4
6407 14:47:23.678782 best_step = 14
6408 14:47:23.681800
6409 14:47:23.681879 ==
6410 14:47:23.685736 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 14:47:23.688727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 14:47:23.688806 ==
6413 14:47:23.688869 RX Vref Scan: 1
6414 14:47:23.688928
6415 14:47:23.691691 RX Vref 0 -> 0, step: 1
6416 14:47:23.691770
6417 14:47:23.695176 RX Delay -343 -> 252, step: 8
6418 14:47:23.695256
6419 14:47:23.698774 Set Vref, RX VrefLevel [Byte0]: 52
6420 14:47:23.701821 [Byte1]: 51
6421 14:47:23.705710
6422 14:47:23.705790 Final RX Vref Byte 0 = 52 to rank0
6423 14:47:23.709729 Final RX Vref Byte 1 = 51 to rank0
6424 14:47:23.712588 Final RX Vref Byte 0 = 52 to rank1
6425 14:47:23.715776 Final RX Vref Byte 1 = 51 to rank1==
6426 14:47:23.718900 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 14:47:23.725546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 14:47:23.725627 ==
6429 14:47:23.725690 DQS Delay:
6430 14:47:23.725748 DQS0 = 44, DQS1 = 60
6431 14:47:23.728921 DQM Delay:
6432 14:47:23.729052 DQM0 = 11, DQM1 = 14
6433 14:47:23.732476 DQ Delay:
6434 14:47:23.735947 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6435 14:47:23.736026 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6436 14:47:23.739575 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6437 14:47:23.742731 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6438 14:47:23.742849
6439 14:47:23.742917
6440 14:47:23.752372 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e4d, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
6441 14:47:23.756312 CH0 RK0: MR19=C0C, MR18=7E4D
6442 14:47:23.762560 CH0_RK0: MR19=0xC0C, MR18=0x7E4D, DQSOSC=393, MR23=63, INC=382, DEC=254
6443 14:47:23.762642 ==
6444 14:47:23.766925 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 14:47:23.769531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 14:47:23.769614 ==
6447 14:47:23.772578 [Gating] SW mode calibration
6448 14:47:23.779491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6449 14:47:23.782818 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6450 14:47:23.789447 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6451 14:47:23.792893 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6452 14:47:23.796851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 14:47:23.802962 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 14:47:23.806404 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 14:47:23.809451 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 14:47:23.816001 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 14:47:23.819901 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 14:47:23.822849 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 14:47:23.826524 Total UI for P1: 0, mck2ui 16
6460 14:47:23.830181 best dqsien dly found for B0: ( 0, 14, 24)
6461 14:47:23.833099 Total UI for P1: 0, mck2ui 16
6462 14:47:23.836085 best dqsien dly found for B1: ( 0, 14, 24)
6463 14:47:23.839819 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6464 14:47:23.843730 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6465 14:47:23.843813
6466 14:47:23.846570 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6467 14:47:23.852967 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6468 14:47:23.853109 [Gating] SW calibration Done
6469 14:47:23.853192 ==
6470 14:47:23.856742 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 14:47:23.863316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 14:47:23.863399 ==
6473 14:47:23.863482 RX Vref Scan: 0
6474 14:47:23.863560
6475 14:47:23.866422 RX Vref 0 -> 0, step: 1
6476 14:47:23.866504
6477 14:47:23.869637 RX Delay -410 -> 252, step: 16
6478 14:47:23.872921 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6479 14:47:23.876400 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6480 14:47:23.879871 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6481 14:47:23.886911 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6482 14:47:23.889870 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6483 14:47:23.892931 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6484 14:47:23.896438 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6485 14:47:23.902995 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6486 14:47:23.906169 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6487 14:47:23.909737 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6488 14:47:23.913674 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6489 14:47:23.919736 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6490 14:47:23.923176 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6491 14:47:23.926517 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6492 14:47:23.930024 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6493 14:47:23.936342 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6494 14:47:23.936427 ==
6495 14:47:23.939919 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 14:47:23.943494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 14:47:23.943577 ==
6498 14:47:23.943660 DQS Delay:
6499 14:47:23.946787 DQS0 = 43, DQS1 = 51
6500 14:47:23.946870 DQM Delay:
6501 14:47:23.949991 DQM0 = 12, DQM1 = 9
6502 14:47:23.950073 DQ Delay:
6503 14:47:23.953983 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6504 14:47:23.956888 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6505 14:47:23.960203 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6506 14:47:23.963309 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6507 14:47:23.963391
6508 14:47:23.963474
6509 14:47:23.963551 ==
6510 14:47:23.966928 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 14:47:23.970487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 14:47:23.970570 ==
6513 14:47:23.970653
6514 14:47:23.970731
6515 14:47:23.973296 TX Vref Scan disable
6516 14:47:23.973378 == TX Byte 0 ==
6517 14:47:23.980425 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6518 14:47:23.983454 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6519 14:47:23.983536 == TX Byte 1 ==
6520 14:47:23.990619 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6521 14:47:23.993529 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6522 14:47:23.993612 ==
6523 14:47:23.996582 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 14:47:23.999999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 14:47:24.000082 ==
6526 14:47:24.000165
6527 14:47:24.000242
6528 14:47:24.004403 TX Vref Scan disable
6529 14:47:24.004485 == TX Byte 0 ==
6530 14:47:24.010372 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6531 14:47:24.013538 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6532 14:47:24.013627 == TX Byte 1 ==
6533 14:47:24.020466 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6534 14:47:24.023474 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6535 14:47:24.023576
6536 14:47:24.023679 [DATLAT]
6537 14:47:24.027053 Freq=400, CH0 RK1
6538 14:47:24.027155
6539 14:47:24.027277 DATLAT Default: 0xe
6540 14:47:24.030507 0, 0xFFFF, sum = 0
6541 14:47:24.030621 1, 0xFFFF, sum = 0
6542 14:47:24.033472 2, 0xFFFF, sum = 0
6543 14:47:24.033597 3, 0xFFFF, sum = 0
6544 14:47:24.036956 4, 0xFFFF, sum = 0
6545 14:47:24.037095 5, 0xFFFF, sum = 0
6546 14:47:24.040101 6, 0xFFFF, sum = 0
6547 14:47:24.040239 7, 0xFFFF, sum = 0
6548 14:47:24.043877 8, 0xFFFF, sum = 0
6549 14:47:24.044033 9, 0xFFFF, sum = 0
6550 14:47:24.046971 10, 0xFFFF, sum = 0
6551 14:47:24.047170 11, 0xFFFF, sum = 0
6552 14:47:24.050173 12, 0xFFFF, sum = 0
6553 14:47:24.050350 13, 0x0, sum = 1
6554 14:47:24.053883 14, 0x0, sum = 2
6555 14:47:24.054088 15, 0x0, sum = 3
6556 14:47:24.056992 16, 0x0, sum = 4
6557 14:47:24.057199 best_step = 14
6558 14:47:24.057407
6559 14:47:24.057602 ==
6560 14:47:24.060693 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 14:47:24.067108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 14:47:24.067409 ==
6563 14:47:24.067715 RX Vref Scan: 0
6564 14:47:24.068048
6565 14:47:24.070564 RX Vref 0 -> 0, step: 1
6566 14:47:24.070952
6567 14:47:24.074264 RX Delay -343 -> 252, step: 8
6568 14:47:24.081310 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6569 14:47:24.084797 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6570 14:47:24.088386 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6571 14:47:24.090396 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6572 14:47:24.097543 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6573 14:47:24.100735 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6574 14:47:24.104238 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6575 14:47:24.107528 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6576 14:47:24.114446 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6577 14:47:24.117238 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6578 14:47:24.120950 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6579 14:47:24.124091 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6580 14:47:24.130992 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6581 14:47:24.134963 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6582 14:47:24.137632 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6583 14:47:24.140640 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6584 14:47:24.141069 ==
6585 14:47:24.144041 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 14:47:24.150904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 14:47:24.151304 ==
6588 14:47:24.151630 DQS Delay:
6589 14:47:24.154164 DQS0 = 44, DQS1 = 60
6590 14:47:24.154591 DQM Delay:
6591 14:47:24.154952 DQM0 = 9, DQM1 = 13
6592 14:47:24.157853 DQ Delay:
6593 14:47:24.161253 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6594 14:47:24.161738 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6595 14:47:24.164231 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6596 14:47:24.167469 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6597 14:47:24.167877
6598 14:47:24.170977
6599 14:47:24.177764 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c60, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6600 14:47:24.180828 CH0 RK1: MR19=C0C, MR18=8C60
6601 14:47:24.187283 CH0_RK1: MR19=0xC0C, MR18=0x8C60, DQSOSC=392, MR23=63, INC=384, DEC=256
6602 14:47:24.191520 [RxdqsGatingPostProcess] freq 400
6603 14:47:24.194860 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6604 14:47:24.198030 best DQS0 dly(2T, 0.5T) = (0, 10)
6605 14:47:24.201841 best DQS1 dly(2T, 0.5T) = (0, 10)
6606 14:47:24.204601 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6607 14:47:24.207984 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6608 14:47:24.210987 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 14:47:24.214546 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 14:47:24.217865 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 14:47:24.221423 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 14:47:24.224747 Pre-setting of DQS Precalculation
6613 14:47:24.228176 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6614 14:47:24.228588 ==
6615 14:47:24.231014 Dram Type= 6, Freq= 0, CH_1, rank 0
6616 14:47:24.234415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 14:47:24.234828 ==
6618 14:47:24.241055 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 14:47:24.247732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6620 14:47:24.251056 [CA 0] Center 36 (8~64) winsize 57
6621 14:47:24.254646 [CA 1] Center 36 (8~64) winsize 57
6622 14:47:24.257844 [CA 2] Center 36 (8~64) winsize 57
6623 14:47:24.260889 [CA 3] Center 36 (8~64) winsize 57
6624 14:47:24.264479 [CA 4] Center 36 (8~64) winsize 57
6625 14:47:24.267688 [CA 5] Center 36 (8~64) winsize 57
6626 14:47:24.268098
6627 14:47:24.271205 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6628 14:47:24.271614
6629 14:47:24.274807 [CATrainingPosCal] consider 1 rank data
6630 14:47:24.277994 u2DelayCellTimex100 = 270/100 ps
6631 14:47:24.281217 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 14:47:24.284810 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 14:47:24.287703 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 14:47:24.290857 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 14:47:24.293949 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 14:47:24.297576 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 14:47:24.297986
6638 14:47:24.300820 CA PerBit enable=1, Macro0, CA PI delay=36
6639 14:47:24.301275
6640 14:47:24.304194 [CBTSetCACLKResult] CA Dly = 36
6641 14:47:24.307639 CS Dly: 1 (0~32)
6642 14:47:24.308045 ==
6643 14:47:24.311103 Dram Type= 6, Freq= 0, CH_1, rank 1
6644 14:47:24.314807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 14:47:24.315350 ==
6646 14:47:24.320672 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6647 14:47:24.327864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6648 14:47:24.328281 [CA 0] Center 36 (8~64) winsize 57
6649 14:47:24.331257 [CA 1] Center 36 (8~64) winsize 57
6650 14:47:24.334550 [CA 2] Center 36 (8~64) winsize 57
6651 14:47:24.337541 [CA 3] Center 36 (8~64) winsize 57
6652 14:47:24.340743 [CA 4] Center 36 (8~64) winsize 57
6653 14:47:24.344248 [CA 5] Center 36 (8~64) winsize 57
6654 14:47:24.344648
6655 14:47:24.347486 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6656 14:47:24.347873
6657 14:47:24.350853 [CATrainingPosCal] consider 2 rank data
6658 14:47:24.354235 u2DelayCellTimex100 = 270/100 ps
6659 14:47:24.358173 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 14:47:24.360968 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 14:47:24.367977 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 14:47:24.371007 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 14:47:24.374452 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 14:47:24.378211 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 14:47:24.378584
6666 14:47:24.381266 CA PerBit enable=1, Macro0, CA PI delay=36
6667 14:47:24.381686
6668 14:47:24.385767 [CBTSetCACLKResult] CA Dly = 36
6669 14:47:24.386184 CS Dly: 1 (0~32)
6670 14:47:24.386504
6671 14:47:24.387826 ----->DramcWriteLeveling(PI) begin...
6672 14:47:24.388195 ==
6673 14:47:24.390886 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 14:47:24.398070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 14:47:24.398509 ==
6676 14:47:24.401085 Write leveling (Byte 0): 40 => 8
6677 14:47:24.404316 Write leveling (Byte 1): 40 => 8
6678 14:47:24.404738 DramcWriteLeveling(PI) end<-----
6679 14:47:24.405149
6680 14:47:24.407578 ==
6681 14:47:24.411067 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 14:47:24.414297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 14:47:24.414740 ==
6684 14:47:24.417875 [Gating] SW mode calibration
6685 14:47:24.424903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6686 14:47:24.427498 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6687 14:47:24.434456 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6688 14:47:24.437973 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6689 14:47:24.442542 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 14:47:24.448066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 14:47:24.450776 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 14:47:24.454391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 14:47:24.460904 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 14:47:24.464454 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 14:47:24.468442 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 14:47:24.470963 Total UI for P1: 0, mck2ui 16
6697 14:47:24.474463 best dqsien dly found for B0: ( 0, 14, 24)
6698 14:47:24.477511 Total UI for P1: 0, mck2ui 16
6699 14:47:24.481508 best dqsien dly found for B1: ( 0, 14, 24)
6700 14:47:24.484432 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6701 14:47:24.487691 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6702 14:47:24.488239
6703 14:47:24.490704 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6704 14:47:24.499043 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6705 14:47:24.499460 [Gating] SW calibration Done
6706 14:47:24.501033 ==
6707 14:47:24.501450 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 14:47:24.507990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 14:47:24.508409 ==
6710 14:47:24.508736 RX Vref Scan: 0
6711 14:47:24.509087
6712 14:47:24.510756 RX Vref 0 -> 0, step: 1
6713 14:47:24.511170
6714 14:47:24.514615 RX Delay -410 -> 252, step: 16
6715 14:47:24.517808 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6716 14:47:24.520953 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6717 14:47:24.527971 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6718 14:47:24.531686 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6719 14:47:24.534480 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6720 14:47:24.537824 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6721 14:47:24.544439 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6722 14:47:24.547954 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6723 14:47:24.550685 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6724 14:47:24.554239 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6725 14:47:24.561217 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6726 14:47:24.564293 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6727 14:47:24.567925 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6728 14:47:24.570875 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6729 14:47:24.577506 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6730 14:47:24.580778 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6731 14:47:24.581226 ==
6732 14:47:24.584194 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 14:47:24.588376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 14:47:24.588808 ==
6735 14:47:24.591195 DQS Delay:
6736 14:47:24.591594 DQS0 = 51, DQS1 = 59
6737 14:47:24.591939 DQM Delay:
6738 14:47:24.594136 DQM0 = 19, DQM1 = 17
6739 14:47:24.594570 DQ Delay:
6740 14:47:24.597821 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6741 14:47:24.602213 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6742 14:47:24.604572 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6743 14:47:24.607820 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6744 14:47:24.608255
6745 14:47:24.608684
6746 14:47:24.609201 ==
6747 14:47:24.611356 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 14:47:24.617897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 14:47:24.618341 ==
6750 14:47:24.618703
6751 14:47:24.619032
6752 14:47:24.619357 TX Vref Scan disable
6753 14:47:24.621177 == TX Byte 0 ==
6754 14:47:24.624051 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 14:47:24.627565 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 14:47:24.631047 == TX Byte 1 ==
6757 14:47:24.635348 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 14:47:24.637527 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 14:47:24.638094 ==
6760 14:47:24.641356 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 14:47:24.647921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 14:47:24.648503 ==
6763 14:47:24.648874
6764 14:47:24.649266
6765 14:47:24.649592 TX Vref Scan disable
6766 14:47:24.651106 == TX Byte 0 ==
6767 14:47:24.654195 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 14:47:24.657678 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 14:47:24.661519 == TX Byte 1 ==
6770 14:47:24.664745 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 14:47:24.667323 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 14:47:24.667767
6773 14:47:24.671049 [DATLAT]
6774 14:47:24.671581 Freq=400, CH1 RK0
6775 14:47:24.671931
6776 14:47:24.674559 DATLAT Default: 0xf
6777 14:47:24.675001 0, 0xFFFF, sum = 0
6778 14:47:24.677784 1, 0xFFFF, sum = 0
6779 14:47:24.678237 2, 0xFFFF, sum = 0
6780 14:47:24.681082 3, 0xFFFF, sum = 0
6781 14:47:24.681535 4, 0xFFFF, sum = 0
6782 14:47:24.684350 5, 0xFFFF, sum = 0
6783 14:47:24.684808 6, 0xFFFF, sum = 0
6784 14:47:24.688034 7, 0xFFFF, sum = 0
6785 14:47:24.688471 8, 0xFFFF, sum = 0
6786 14:47:24.691205 9, 0xFFFF, sum = 0
6787 14:47:24.691656 10, 0xFFFF, sum = 0
6788 14:47:24.694271 11, 0xFFFF, sum = 0
6789 14:47:24.694721 12, 0xFFFF, sum = 0
6790 14:47:24.697498 13, 0x0, sum = 1
6791 14:47:24.697930 14, 0x0, sum = 2
6792 14:47:24.700917 15, 0x0, sum = 3
6793 14:47:24.701409 16, 0x0, sum = 4
6794 14:47:24.704576 best_step = 14
6795 14:47:24.705045
6796 14:47:24.705392 ==
6797 14:47:24.708187 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 14:47:24.710907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 14:47:24.711337 ==
6800 14:47:24.714368 RX Vref Scan: 1
6801 14:47:24.714795
6802 14:47:24.715151 RX Vref 0 -> 0, step: 1
6803 14:47:24.715606
6804 14:47:24.717676 RX Delay -359 -> 252, step: 8
6805 14:47:24.718108
6806 14:47:24.721224 Set Vref, RX VrefLevel [Byte0]: 56
6807 14:47:24.724131 [Byte1]: 45
6808 14:47:24.728921
6809 14:47:24.729396 Final RX Vref Byte 0 = 56 to rank0
6810 14:47:24.732325 Final RX Vref Byte 1 = 45 to rank0
6811 14:47:24.736003 Final RX Vref Byte 0 = 56 to rank1
6812 14:47:24.739297 Final RX Vref Byte 1 = 45 to rank1==
6813 14:47:24.742717 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 14:47:24.749505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 14:47:24.749929 ==
6816 14:47:24.750267 DQS Delay:
6817 14:47:24.750579 DQS0 = 48, DQS1 = 60
6818 14:47:24.753150 DQM Delay:
6819 14:47:24.753576 DQM0 = 12, DQM1 = 13
6820 14:47:24.756261 DQ Delay:
6821 14:47:24.758971 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6822 14:47:24.759440 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6823 14:47:24.762929 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6824 14:47:24.765907 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =16
6825 14:47:24.766340
6826 14:47:24.766701
6827 14:47:24.775837 [DQSOSCAuto] RK0, (LSB)MR18= 0x862e, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6828 14:47:24.778892 CH1 RK0: MR19=C0C, MR18=862E
6829 14:47:24.785710 CH1_RK0: MR19=0xC0C, MR18=0x862E, DQSOSC=393, MR23=63, INC=382, DEC=254
6830 14:47:24.786156 ==
6831 14:47:24.789220 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 14:47:24.792217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 14:47:24.792654 ==
6834 14:47:24.795830 [Gating] SW mode calibration
6835 14:47:24.802165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6836 14:47:24.805256 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6837 14:47:24.812290 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6838 14:47:24.815440 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6839 14:47:24.818762 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 14:47:24.825692 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 14:47:24.829508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 14:47:24.832703 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 14:47:24.838964 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 14:47:24.842130 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 14:47:24.846163 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 14:47:24.849187 Total UI for P1: 0, mck2ui 16
6847 14:47:24.851992 best dqsien dly found for B0: ( 0, 14, 24)
6848 14:47:24.855464 Total UI for P1: 0, mck2ui 16
6849 14:47:24.858606 best dqsien dly found for B1: ( 0, 14, 24)
6850 14:47:24.862626 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6851 14:47:24.865682 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6852 14:47:24.865749
6853 14:47:24.869124 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6854 14:47:24.875550 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6855 14:47:24.875620 [Gating] SW calibration Done
6856 14:47:24.875683 ==
6857 14:47:24.878923 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 14:47:24.885823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 14:47:24.885898 ==
6860 14:47:24.885961 RX Vref Scan: 0
6861 14:47:24.886018
6862 14:47:24.889177 RX Vref 0 -> 0, step: 1
6863 14:47:24.889243
6864 14:47:24.892964 RX Delay -410 -> 252, step: 16
6865 14:47:24.895761 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6866 14:47:24.899081 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6867 14:47:24.905805 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6868 14:47:24.908958 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6869 14:47:24.912306 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6870 14:47:24.915803 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6871 14:47:24.922523 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6872 14:47:24.925974 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6873 14:47:24.928799 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6874 14:47:24.932321 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6875 14:47:24.938800 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6876 14:47:24.942146 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6877 14:47:24.946542 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6878 14:47:24.948833 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6879 14:47:24.955707 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6880 14:47:24.959052 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6881 14:47:24.959120 ==
6882 14:47:24.962193 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 14:47:24.965587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 14:47:24.965659 ==
6885 14:47:24.969167 DQS Delay:
6886 14:47:24.969233 DQS0 = 43, DQS1 = 51
6887 14:47:24.969289 DQM Delay:
6888 14:47:24.972838 DQM0 = 9, DQM1 = 9
6889 14:47:24.972923 DQ Delay:
6890 14:47:24.975442 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6891 14:47:24.978829 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6892 14:47:24.982378 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6893 14:47:24.986274 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6894 14:47:24.986346
6895 14:47:24.986409
6896 14:47:24.986465 ==
6897 14:47:24.989143 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 14:47:24.992038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 14:47:24.992109 ==
6900 14:47:24.992168
6901 14:47:24.992223
6902 14:47:24.996055 TX Vref Scan disable
6903 14:47:24.998840 == TX Byte 0 ==
6904 14:47:25.002374 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6905 14:47:25.006676 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6906 14:47:25.006748 == TX Byte 1 ==
6907 14:47:25.012790 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6908 14:47:25.015647 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6909 14:47:25.015722 ==
6910 14:47:25.019532 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 14:47:25.022300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 14:47:25.022367 ==
6913 14:47:25.022426
6914 14:47:25.022482
6915 14:47:25.025563 TX Vref Scan disable
6916 14:47:25.030212 == TX Byte 0 ==
6917 14:47:25.032658 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6918 14:47:25.036215 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6919 14:47:25.036318 == TX Byte 1 ==
6920 14:47:25.042468 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6921 14:47:25.046049 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6922 14:47:25.046118
6923 14:47:25.046179 [DATLAT]
6924 14:47:25.049289 Freq=400, CH1 RK1
6925 14:47:25.049357
6926 14:47:25.049416 DATLAT Default: 0xe
6927 14:47:25.052491 0, 0xFFFF, sum = 0
6928 14:47:25.052561 1, 0xFFFF, sum = 0
6929 14:47:25.056524 2, 0xFFFF, sum = 0
6930 14:47:25.056597 3, 0xFFFF, sum = 0
6931 14:47:25.058959 4, 0xFFFF, sum = 0
6932 14:47:25.059032 5, 0xFFFF, sum = 0
6933 14:47:25.062997 6, 0xFFFF, sum = 0
6934 14:47:25.063092 7, 0xFFFF, sum = 0
6935 14:47:25.066745 8, 0xFFFF, sum = 0
6936 14:47:25.069641 9, 0xFFFF, sum = 0
6937 14:47:25.069737 10, 0xFFFF, sum = 0
6938 14:47:25.072147 11, 0xFFFF, sum = 0
6939 14:47:25.072241 12, 0xFFFF, sum = 0
6940 14:47:25.075449 13, 0x0, sum = 1
6941 14:47:25.075519 14, 0x0, sum = 2
6942 14:47:25.078986 15, 0x0, sum = 3
6943 14:47:25.079057 16, 0x0, sum = 4
6944 14:47:25.079118 best_step = 14
6945 14:47:25.079176
6946 14:47:25.082443 ==
6947 14:47:25.085497 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 14:47:25.089119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 14:47:25.089188 ==
6950 14:47:25.089249 RX Vref Scan: 0
6951 14:47:25.089306
6952 14:47:25.092129 RX Vref 0 -> 0, step: 1
6953 14:47:25.092219
6954 14:47:25.095446 RX Delay -343 -> 252, step: 8
6955 14:47:25.102916 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6956 14:47:25.106920 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6957 14:47:25.109312 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6958 14:47:25.113268 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6959 14:47:25.119722 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6960 14:47:25.122660 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6961 14:47:25.126943 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6962 14:47:25.129362 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6963 14:47:25.135909 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6964 14:47:25.139195 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6965 14:47:25.142649 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6966 14:47:25.145871 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6967 14:47:25.152592 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6968 14:47:25.156019 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6969 14:47:25.159241 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6970 14:47:25.166334 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6971 14:47:25.166411 ==
6972 14:47:25.169128 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 14:47:25.173325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 14:47:25.173397 ==
6975 14:47:25.173458 DQS Delay:
6976 14:47:25.176381 DQS0 = 52, DQS1 = 60
6977 14:47:25.176473 DQM Delay:
6978 14:47:25.179573 DQM0 = 13, DQM1 = 13
6979 14:47:25.179667 DQ Delay:
6980 14:47:25.182827 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6981 14:47:25.186672 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6982 14:47:25.189325 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6983 14:47:25.192764 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6984 14:47:25.192832
6985 14:47:25.192920
6986 14:47:25.199346 [DQSOSCAuto] RK1, (LSB)MR18= 0x7086, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
6987 14:47:25.202407 CH1 RK1: MR19=C0C, MR18=7086
6988 14:47:25.208984 CH1_RK1: MR19=0xC0C, MR18=0x7086, DQSOSC=393, MR23=63, INC=382, DEC=254
6989 14:47:25.212747 [RxdqsGatingPostProcess] freq 400
6990 14:47:25.216330 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6991 14:47:25.220611 best DQS0 dly(2T, 0.5T) = (0, 10)
6992 14:47:25.222863 best DQS1 dly(2T, 0.5T) = (0, 10)
6993 14:47:25.226151 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6994 14:47:25.229397 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6995 14:47:25.232544 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 14:47:25.235942 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 14:47:25.239312 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 14:47:25.242442 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 14:47:25.245913 Pre-setting of DQS Precalculation
7000 14:47:25.249166 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7001 14:47:25.259585 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7002 14:47:25.266400 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7003 14:47:25.266475
7004 14:47:25.266537
7005 14:47:25.270366 [Calibration Summary] 800 Mbps
7006 14:47:25.270461 CH 0, Rank 0
7007 14:47:25.272908 SW Impedance : PASS
7008 14:47:25.273037 DUTY Scan : NO K
7009 14:47:25.276329 ZQ Calibration : PASS
7010 14:47:25.279507 Jitter Meter : NO K
7011 14:47:25.279581 CBT Training : PASS
7012 14:47:25.283040 Write leveling : PASS
7013 14:47:25.283115 RX DQS gating : PASS
7014 14:47:25.286506 RX DQ/DQS(RDDQC) : PASS
7015 14:47:25.290105 TX DQ/DQS : PASS
7016 14:47:25.290174 RX DATLAT : PASS
7017 14:47:25.293239 RX DQ/DQS(Engine): PASS
7018 14:47:25.296340 TX OE : NO K
7019 14:47:25.296435 All Pass.
7020 14:47:25.296522
7021 14:47:25.296606 CH 0, Rank 1
7022 14:47:25.299580 SW Impedance : PASS
7023 14:47:25.302427 DUTY Scan : NO K
7024 14:47:25.302497 ZQ Calibration : PASS
7025 14:47:25.306360 Jitter Meter : NO K
7026 14:47:25.309875 CBT Training : PASS
7027 14:47:25.309942 Write leveling : NO K
7028 14:47:25.312535 RX DQS gating : PASS
7029 14:47:25.316097 RX DQ/DQS(RDDQC) : PASS
7030 14:47:25.316166 TX DQ/DQS : PASS
7031 14:47:25.319316 RX DATLAT : PASS
7032 14:47:25.322833 RX DQ/DQS(Engine): PASS
7033 14:47:25.322903 TX OE : NO K
7034 14:47:25.322963 All Pass.
7035 14:47:25.325805
7036 14:47:25.325872 CH 1, Rank 0
7037 14:47:25.329567 SW Impedance : PASS
7038 14:47:25.329632 DUTY Scan : NO K
7039 14:47:25.332978 ZQ Calibration : PASS
7040 14:47:25.333045 Jitter Meter : NO K
7041 14:47:25.336031 CBT Training : PASS
7042 14:47:25.339460 Write leveling : PASS
7043 14:47:25.339536 RX DQS gating : PASS
7044 14:47:25.342544 RX DQ/DQS(RDDQC) : PASS
7045 14:47:25.345813 TX DQ/DQS : PASS
7046 14:47:25.345881 RX DATLAT : PASS
7047 14:47:25.349804 RX DQ/DQS(Engine): PASS
7048 14:47:25.352809 TX OE : NO K
7049 14:47:25.352902 All Pass.
7050 14:47:25.353013
7051 14:47:25.353086 CH 1, Rank 1
7052 14:47:25.355767 SW Impedance : PASS
7053 14:47:25.359824 DUTY Scan : NO K
7054 14:47:25.359890 ZQ Calibration : PASS
7055 14:47:25.362240 Jitter Meter : NO K
7056 14:47:25.365980 CBT Training : PASS
7057 14:47:25.366050 Write leveling : NO K
7058 14:47:25.368977 RX DQS gating : PASS
7059 14:47:25.372240 RX DQ/DQS(RDDQC) : PASS
7060 14:47:25.372307 TX DQ/DQS : PASS
7061 14:47:25.375749 RX DATLAT : PASS
7062 14:47:25.379280 RX DQ/DQS(Engine): PASS
7063 14:47:25.379350 TX OE : NO K
7064 14:47:25.379415 All Pass.
7065 14:47:25.383034
7066 14:47:25.383106 DramC Write-DBI off
7067 14:47:25.386375 PER_BANK_REFRESH: Hybrid Mode
7068 14:47:25.386449 TX_TRACKING: ON
7069 14:47:25.396009 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7070 14:47:25.399033 [FAST_K] Save calibration result to emmc
7071 14:47:25.403048 dramc_set_vcore_voltage set vcore to 725000
7072 14:47:25.405614 Read voltage for 1600, 0
7073 14:47:25.405712 Vio18 = 0
7074 14:47:25.408900 Vcore = 725000
7075 14:47:25.409033 Vdram = 0
7076 14:47:25.409097 Vddq = 0
7077 14:47:25.409159 Vmddr = 0
7078 14:47:25.416256 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7079 14:47:25.419339 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7080 14:47:25.422642 MEM_TYPE=3, freq_sel=13
7081 14:47:25.426317 sv_algorithm_assistance_LP4_3733
7082 14:47:25.429339 ============ PULL DRAM RESETB DOWN ============
7083 14:47:25.436145 ========== PULL DRAM RESETB DOWN end =========
7084 14:47:25.439424 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7085 14:47:25.442534 ===================================
7086 14:47:25.445832 LPDDR4 DRAM CONFIGURATION
7087 14:47:25.450003 ===================================
7088 14:47:25.450099 EX_ROW_EN[0] = 0x0
7089 14:47:25.452862 EX_ROW_EN[1] = 0x0
7090 14:47:25.452955 LP4Y_EN = 0x0
7091 14:47:25.456100 WORK_FSP = 0x1
7092 14:47:25.456165 WL = 0x5
7093 14:47:25.459287 RL = 0x5
7094 14:47:25.459355 BL = 0x2
7095 14:47:25.462820 RPST = 0x0
7096 14:47:25.462886 RD_PRE = 0x0
7097 14:47:25.466041 WR_PRE = 0x1
7098 14:47:25.466111 WR_PST = 0x1
7099 14:47:25.469459 DBI_WR = 0x0
7100 14:47:25.469555 DBI_RD = 0x0
7101 14:47:25.472783 OTF = 0x1
7102 14:47:25.475965 ===================================
7103 14:47:25.479169 ===================================
7104 14:47:25.479242 ANA top config
7105 14:47:25.482719 ===================================
7106 14:47:25.485849 DLL_ASYNC_EN = 0
7107 14:47:25.489701 ALL_SLAVE_EN = 0
7108 14:47:25.492688 NEW_RANK_MODE = 1
7109 14:47:25.492785 DLL_IDLE_MODE = 1
7110 14:47:25.496870 LP45_APHY_COMB_EN = 1
7111 14:47:25.500143 TX_ODT_DIS = 0
7112 14:47:25.502774 NEW_8X_MODE = 1
7113 14:47:25.506176 ===================================
7114 14:47:25.509401 ===================================
7115 14:47:25.512605 data_rate = 3200
7116 14:47:25.512710 CKR = 1
7117 14:47:25.515846 DQ_P2S_RATIO = 8
7118 14:47:25.519529 ===================================
7119 14:47:25.522822 CA_P2S_RATIO = 8
7120 14:47:25.526608 DQ_CA_OPEN = 0
7121 14:47:25.529932 DQ_SEMI_OPEN = 0
7122 14:47:25.532626 CA_SEMI_OPEN = 0
7123 14:47:25.532727 CA_FULL_RATE = 0
7124 14:47:25.536295 DQ_CKDIV4_EN = 0
7125 14:47:25.539541 CA_CKDIV4_EN = 0
7126 14:47:25.543355 CA_PREDIV_EN = 0
7127 14:47:25.546426 PH8_DLY = 12
7128 14:47:25.546502 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7129 14:47:25.549785 DQ_AAMCK_DIV = 4
7130 14:47:25.553061 CA_AAMCK_DIV = 4
7131 14:47:25.556569 CA_ADMCK_DIV = 4
7132 14:47:25.559863 DQ_TRACK_CA_EN = 0
7133 14:47:25.562797 CA_PICK = 1600
7134 14:47:25.566161 CA_MCKIO = 1600
7135 14:47:25.566234 MCKIO_SEMI = 0
7136 14:47:25.569772 PLL_FREQ = 3068
7137 14:47:25.572822 DQ_UI_PI_RATIO = 32
7138 14:47:25.575908 CA_UI_PI_RATIO = 0
7139 14:47:25.579372 ===================================
7140 14:47:25.583549 ===================================
7141 14:47:25.586004 memory_type:LPDDR4
7142 14:47:25.586072 GP_NUM : 10
7143 14:47:25.589490 SRAM_EN : 1
7144 14:47:25.592797 MD32_EN : 0
7145 14:47:25.596107 ===================================
7146 14:47:25.596178 [ANA_INIT] >>>>>>>>>>>>>>
7147 14:47:25.599707 <<<<<< [CONFIGURE PHASE]: ANA_TX
7148 14:47:25.603649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7149 14:47:25.606517 ===================================
7150 14:47:25.609298 data_rate = 3200,PCW = 0X7600
7151 14:47:25.613294 ===================================
7152 14:47:25.616557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7153 14:47:25.623081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7154 14:47:25.626310 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7155 14:47:25.632987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7156 14:47:25.636313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7157 14:47:25.639569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7158 14:47:25.639641 [ANA_INIT] flow start
7159 14:47:25.643097 [ANA_INIT] PLL >>>>>>>>
7160 14:47:25.645900 [ANA_INIT] PLL <<<<<<<<
7161 14:47:25.645966 [ANA_INIT] MIDPI >>>>>>>>
7162 14:47:25.650049 [ANA_INIT] MIDPI <<<<<<<<
7163 14:47:25.652904 [ANA_INIT] DLL >>>>>>>>
7164 14:47:25.653020 [ANA_INIT] DLL <<<<<<<<
7165 14:47:25.655917 [ANA_INIT] flow end
7166 14:47:25.659692 ============ LP4 DIFF to SE enter ============
7167 14:47:25.666226 ============ LP4 DIFF to SE exit ============
7168 14:47:25.666307 [ANA_INIT] <<<<<<<<<<<<<
7169 14:47:25.669436 [Flow] Enable top DCM control >>>>>
7170 14:47:25.672634 [Flow] Enable top DCM control <<<<<
7171 14:47:25.676843 Enable DLL master slave shuffle
7172 14:47:25.683195 ==============================================================
7173 14:47:25.683295 Gating Mode config
7174 14:47:25.689444 ==============================================================
7175 14:47:25.689546 Config description:
7176 14:47:25.699833 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7177 14:47:25.706399 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7178 14:47:25.713484 SELPH_MODE 0: By rank 1: By Phase
7179 14:47:25.716165 ==============================================================
7180 14:47:25.719770 GAT_TRACK_EN = 1
7181 14:47:25.724288 RX_GATING_MODE = 2
7182 14:47:25.726272 RX_GATING_TRACK_MODE = 2
7183 14:47:25.730198 SELPH_MODE = 1
7184 14:47:25.732826 PICG_EARLY_EN = 1
7185 14:47:25.736383 VALID_LAT_VALUE = 1
7186 14:47:25.743004 ==============================================================
7187 14:47:25.746151 Enter into Gating configuration >>>>
7188 14:47:25.749738 Exit from Gating configuration <<<<
7189 14:47:25.749836 Enter into DVFS_PRE_config >>>>>
7190 14:47:25.763207 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7191 14:47:25.766369 Exit from DVFS_PRE_config <<<<<
7192 14:47:25.770284 Enter into PICG configuration >>>>
7193 14:47:25.773750 Exit from PICG configuration <<<<
7194 14:47:25.773822 [RX_INPUT] configuration >>>>>
7195 14:47:25.776571 [RX_INPUT] configuration <<<<<
7196 14:47:25.783609 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7197 14:47:25.786645 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7198 14:47:25.792963 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7199 14:47:25.799799 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7200 14:47:25.806770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7201 14:47:25.813552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7202 14:47:25.816715 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7203 14:47:25.820392 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7204 14:47:25.823810 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7205 14:47:25.830579 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7206 14:47:25.833327 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7207 14:47:25.836657 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7208 14:47:25.839746 ===================================
7209 14:47:25.843214 LPDDR4 DRAM CONFIGURATION
7210 14:47:25.846821 ===================================
7211 14:47:25.850127 EX_ROW_EN[0] = 0x0
7212 14:47:25.850194 EX_ROW_EN[1] = 0x0
7213 14:47:25.853264 LP4Y_EN = 0x0
7214 14:47:25.853336 WORK_FSP = 0x1
7215 14:47:25.856431 WL = 0x5
7216 14:47:25.856496 RL = 0x5
7217 14:47:25.860274 BL = 0x2
7218 14:47:25.860340 RPST = 0x0
7219 14:47:25.863280 RD_PRE = 0x0
7220 14:47:25.863343 WR_PRE = 0x1
7221 14:47:25.866523 WR_PST = 0x1
7222 14:47:25.866589 DBI_WR = 0x0
7223 14:47:25.870079 DBI_RD = 0x0
7224 14:47:25.870188 OTF = 0x1
7225 14:47:25.873836 ===================================
7226 14:47:25.876576 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7227 14:47:25.883258 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7228 14:47:25.887432 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 14:47:25.889643 ===================================
7230 14:47:25.893090 LPDDR4 DRAM CONFIGURATION
7231 14:47:25.896950 ===================================
7232 14:47:25.897055 EX_ROW_EN[0] = 0x10
7233 14:47:25.900526 EX_ROW_EN[1] = 0x0
7234 14:47:25.903152 LP4Y_EN = 0x0
7235 14:47:25.903230 WORK_FSP = 0x1
7236 14:47:25.906362 WL = 0x5
7237 14:47:25.906433 RL = 0x5
7238 14:47:25.909684 BL = 0x2
7239 14:47:25.909752 RPST = 0x0
7240 14:47:25.913370 RD_PRE = 0x0
7241 14:47:25.913437 WR_PRE = 0x1
7242 14:47:25.917186 WR_PST = 0x1
7243 14:47:25.917258 DBI_WR = 0x0
7244 14:47:25.920317 DBI_RD = 0x0
7245 14:47:25.920382 OTF = 0x1
7246 14:47:25.923117 ===================================
7247 14:47:25.929903 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7248 14:47:25.929973 ==
7249 14:47:25.933028 Dram Type= 6, Freq= 0, CH_0, rank 0
7250 14:47:25.937431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7251 14:47:25.937506 ==
7252 14:47:25.939665 [Duty_Offset_Calibration]
7253 14:47:25.943518 B0:2 B1:-1 CA:1
7254 14:47:25.943590
7255 14:47:25.946435 [DutyScan_Calibration_Flow] k_type=0
7256 14:47:25.954842
7257 14:47:25.954917 ==CLK 0==
7258 14:47:25.957480 Final CLK duty delay cell = -4
7259 14:47:25.960774 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7260 14:47:25.964760 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7261 14:47:25.967282 [-4] AVG Duty = 4937%(X100)
7262 14:47:25.967351
7263 14:47:25.970764 CH0 CLK Duty spec in!! Max-Min= 187%
7264 14:47:25.973922 [DutyScan_Calibration_Flow] ====Done====
7265 14:47:25.973992
7266 14:47:25.977441 [DutyScan_Calibration_Flow] k_type=1
7267 14:47:25.993995
7268 14:47:25.994081 ==DQS 0 ==
7269 14:47:25.996744 Final DQS duty delay cell = 0
7270 14:47:26.000218 [0] MAX Duty = 5125%(X100), DQS PI = 20
7271 14:47:26.003777 [0] MIN Duty = 5000%(X100), DQS PI = 14
7272 14:47:26.007194 [0] AVG Duty = 5062%(X100)
7273 14:47:26.007263
7274 14:47:26.007325 ==DQS 1 ==
7275 14:47:26.010401 Final DQS duty delay cell = -4
7276 14:47:26.013954 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7277 14:47:26.017134 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7278 14:47:26.020466 [-4] AVG Duty = 5046%(X100)
7279 14:47:26.020532
7280 14:47:26.023575 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7281 14:47:26.023646
7282 14:47:26.027132 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7283 14:47:26.030163 [DutyScan_Calibration_Flow] ====Done====
7284 14:47:26.030231
7285 14:47:26.033643 [DutyScan_Calibration_Flow] k_type=3
7286 14:47:26.050888
7287 14:47:26.050963 ==DQM 0 ==
7288 14:47:26.054551 Final DQM duty delay cell = 0
7289 14:47:26.057842 [0] MAX Duty = 5000%(X100), DQS PI = 18
7290 14:47:26.061147 [0] MIN Duty = 4875%(X100), DQS PI = 4
7291 14:47:26.061218 [0] AVG Duty = 4937%(X100)
7292 14:47:26.064570
7293 14:47:26.064634 ==DQM 1 ==
7294 14:47:26.068119 Final DQM duty delay cell = 0
7295 14:47:26.071616 [0] MAX Duty = 5218%(X100), DQS PI = 58
7296 14:47:26.074283 [0] MIN Duty = 4969%(X100), DQS PI = 18
7297 14:47:26.074349 [0] AVG Duty = 5093%(X100)
7298 14:47:26.077635
7299 14:47:26.081490 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7300 14:47:26.081559
7301 14:47:26.084315 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7302 14:47:26.087519 [DutyScan_Calibration_Flow] ====Done====
7303 14:47:26.087590
7304 14:47:26.090945 [DutyScan_Calibration_Flow] k_type=2
7305 14:47:26.108222
7306 14:47:26.108297 ==DQ 0 ==
7307 14:47:26.111383 Final DQ duty delay cell = 0
7308 14:47:26.115074 [0] MAX Duty = 5156%(X100), DQS PI = 0
7309 14:47:26.118730 [0] MIN Duty = 5031%(X100), DQS PI = 4
7310 14:47:26.118799 [0] AVG Duty = 5093%(X100)
7311 14:47:26.118858
7312 14:47:26.121412 ==DQ 1 ==
7313 14:47:26.121477 Final DQ duty delay cell = 0
7314 14:47:26.128375 [0] MAX Duty = 5031%(X100), DQS PI = 38
7315 14:47:26.132619 [0] MIN Duty = 4907%(X100), DQS PI = 18
7316 14:47:26.132688 [0] AVG Duty = 4969%(X100)
7317 14:47:26.132747
7318 14:47:26.134822 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7319 14:47:26.134887
7320 14:47:26.138321 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7321 14:47:26.144762 [DutyScan_Calibration_Flow] ====Done====
7322 14:47:26.144832 ==
7323 14:47:26.148394 Dram Type= 6, Freq= 0, CH_1, rank 0
7324 14:47:26.152198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7325 14:47:26.152270 ==
7326 14:47:26.155142 [Duty_Offset_Calibration]
7327 14:47:26.155243 B0:1 B1:1 CA:2
7328 14:47:26.155330
7329 14:47:26.158457 [DutyScan_Calibration_Flow] k_type=0
7330 14:47:26.168226
7331 14:47:26.168300 ==CLK 0==
7332 14:47:26.171701 Final CLK duty delay cell = 0
7333 14:47:26.175258 [0] MAX Duty = 5187%(X100), DQS PI = 24
7334 14:47:26.178693 [0] MIN Duty = 4938%(X100), DQS PI = 48
7335 14:47:26.178760 [0] AVG Duty = 5062%(X100)
7336 14:47:26.181852
7337 14:47:26.181921 CH1 CLK Duty spec in!! Max-Min= 249%
7338 14:47:26.188073 [DutyScan_Calibration_Flow] ====Done====
7339 14:47:26.188149
7340 14:47:26.191245 [DutyScan_Calibration_Flow] k_type=1
7341 14:47:26.207795
7342 14:47:26.207868 ==DQS 0 ==
7343 14:47:26.211383 Final DQS duty delay cell = 0
7344 14:47:26.215088 [0] MAX Duty = 5062%(X100), DQS PI = 20
7345 14:47:26.218192 [0] MIN Duty = 4813%(X100), DQS PI = 52
7346 14:47:26.221036 [0] AVG Duty = 4937%(X100)
7347 14:47:26.221102
7348 14:47:26.221159 ==DQS 1 ==
7349 14:47:26.224746 Final DQS duty delay cell = 0
7350 14:47:26.227819 [0] MAX Duty = 5031%(X100), DQS PI = 34
7351 14:47:26.231288 [0] MIN Duty = 4938%(X100), DQS PI = 14
7352 14:47:26.236665 [0] AVG Duty = 4984%(X100)
7353 14:47:26.236728
7354 14:47:26.237940 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7355 14:47:26.238003
7356 14:47:26.241387 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7357 14:47:26.244561 [DutyScan_Calibration_Flow] ====Done====
7358 14:47:26.244624
7359 14:47:26.248099 [DutyScan_Calibration_Flow] k_type=3
7360 14:47:26.265017
7361 14:47:26.265085 ==DQM 0 ==
7362 14:47:26.268051 Final DQM duty delay cell = 0
7363 14:47:26.271716 [0] MAX Duty = 5156%(X100), DQS PI = 20
7364 14:47:26.274880 [0] MIN Duty = 4813%(X100), DQS PI = 52
7365 14:47:26.278320 [0] AVG Duty = 4984%(X100)
7366 14:47:26.278387
7367 14:47:26.278444 ==DQM 1 ==
7368 14:47:26.281593 Final DQM duty delay cell = 0
7369 14:47:26.285020 [0] MAX Duty = 5125%(X100), DQS PI = 10
7370 14:47:26.288018 [0] MIN Duty = 4907%(X100), DQS PI = 20
7371 14:47:26.291530 [0] AVG Duty = 5016%(X100)
7372 14:47:26.291595
7373 14:47:26.294900 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7374 14:47:26.294975
7375 14:47:26.298545 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7376 14:47:26.301783 [DutyScan_Calibration_Flow] ====Done====
7377 14:47:26.301849
7378 14:47:26.305573 [DutyScan_Calibration_Flow] k_type=2
7379 14:47:26.321862
7380 14:47:26.321938 ==DQ 0 ==
7381 14:47:26.325576 Final DQ duty delay cell = 0
7382 14:47:26.328334 [0] MAX Duty = 5156%(X100), DQS PI = 20
7383 14:47:26.332063 [0] MIN Duty = 4907%(X100), DQS PI = 50
7384 14:47:26.332128 [0] AVG Duty = 5031%(X100)
7385 14:47:26.332184
7386 14:47:26.335633 ==DQ 1 ==
7387 14:47:26.338421 Final DQ duty delay cell = 0
7388 14:47:26.342463 [0] MAX Duty = 5093%(X100), DQS PI = 8
7389 14:47:26.345343 [0] MIN Duty = 5031%(X100), DQS PI = 0
7390 14:47:26.345439 [0] AVG Duty = 5062%(X100)
7391 14:47:26.345530
7392 14:47:26.349018 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7393 14:47:26.349112
7394 14:47:26.352178 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7395 14:47:26.358360 [DutyScan_Calibration_Flow] ====Done====
7396 14:47:26.362090 nWR fixed to 30
7397 14:47:26.362161 [ModeRegInit_LP4] CH0 RK0
7398 14:47:26.365046 [ModeRegInit_LP4] CH0 RK1
7399 14:47:26.368528 [ModeRegInit_LP4] CH1 RK0
7400 14:47:26.368601 [ModeRegInit_LP4] CH1 RK1
7401 14:47:26.371986 match AC timing 5
7402 14:47:26.375655 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7403 14:47:26.378944 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7404 14:47:26.385541 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7405 14:47:26.388438 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7406 14:47:26.394995 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7407 14:47:26.395066 [MiockJmeterHQA]
7408 14:47:26.395126
7409 14:47:26.398895 [DramcMiockJmeter] u1RxGatingPI = 0
7410 14:47:26.398976 0 : 4363, 4138
7411 14:47:26.402059 4 : 4253, 4026
7412 14:47:26.402132 8 : 4363, 4137
7413 14:47:26.405415 12 : 4363, 4137
7414 14:47:26.405506 16 : 4253, 4027
7415 14:47:26.408639 20 : 4363, 4137
7416 14:47:26.408746 24 : 4252, 4027
7417 14:47:26.408835 28 : 4252, 4027
7418 14:47:26.411902 32 : 4253, 4026
7419 14:47:26.412007 36 : 4255, 4029
7420 14:47:26.415598 40 : 4252, 4027
7421 14:47:26.415673 44 : 4252, 4027
7422 14:47:26.418927 48 : 4366, 4139
7423 14:47:26.419026 52 : 4250, 4026
7424 14:47:26.422004 56 : 4252, 4029
7425 14:47:26.422101 60 : 4250, 4027
7426 14:47:26.422200 64 : 4361, 4137
7427 14:47:26.425826 68 : 4250, 4027
7428 14:47:26.425897 72 : 4360, 4137
7429 14:47:26.429174 76 : 4250, 4027
7430 14:47:26.429247 80 : 4250, 4026
7431 14:47:26.432172 84 : 4250, 4026
7432 14:47:26.432246 88 : 4253, 4030
7433 14:47:26.435526 92 : 4361, 4137
7434 14:47:26.435604 96 : 4252, 3215
7435 14:47:26.435666 100 : 4360, 0
7436 14:47:26.438997 104 : 4250, 0
7437 14:47:26.439071 108 : 4363, 0
7438 14:47:26.442300 112 : 4250, 0
7439 14:47:26.442370 116 : 4250, 0
7440 14:47:26.442429 120 : 4253, 0
7441 14:47:26.446192 124 : 4250, 0
7442 14:47:26.446258 128 : 4252, 0
7443 14:47:26.446322 132 : 4250, 0
7444 14:47:26.449863 136 : 4250, 0
7445 14:47:26.449957 140 : 4252, 0
7446 14:47:26.452338 144 : 4250, 0
7447 14:47:26.452406 148 : 4360, 0
7448 14:47:26.452492 152 : 4361, 0
7449 14:47:26.455605 156 : 4250, 0
7450 14:47:26.455671 160 : 4250, 0
7451 14:47:26.458793 164 : 4361, 0
7452 14:47:26.458887 168 : 4250, 0
7453 14:47:26.458974 172 : 4250, 0
7454 14:47:26.462862 176 : 4250, 0
7455 14:47:26.462931 180 : 4252, 0
7456 14:47:26.462989 184 : 4250, 0
7457 14:47:26.465418 188 : 4250, 0
7458 14:47:26.465514 192 : 4252, 0
7459 14:47:26.468881 196 : 4250, 0
7460 14:47:26.468982 200 : 4249, 0
7461 14:47:26.469074 204 : 4250, 0
7462 14:47:26.472266 208 : 4250, 0
7463 14:47:26.472336 212 : 4250, 64
7464 14:47:26.475470 216 : 4253, 3307
7465 14:47:26.475567 220 : 4250, 4027
7466 14:47:26.478897 224 : 4250, 4026
7467 14:47:26.478968 228 : 4361, 4137
7468 14:47:26.479027 232 : 4250, 4027
7469 14:47:26.482125 236 : 4250, 4027
7470 14:47:26.482193 240 : 4360, 4138
7471 14:47:26.485833 244 : 4361, 4137
7472 14:47:26.485901 248 : 4250, 4027
7473 14:47:26.489229 252 : 4363, 4140
7474 14:47:26.489323 256 : 4250, 4027
7475 14:47:26.492710 260 : 4250, 4026
7476 14:47:26.492777 264 : 4250, 4027
7477 14:47:26.496088 268 : 4252, 4030
7478 14:47:26.496183 272 : 4250, 4027
7479 14:47:26.498840 276 : 4250, 4026
7480 14:47:26.498935 280 : 4250, 4027
7481 14:47:26.502459 284 : 4253, 4030
7482 14:47:26.502528 288 : 4250, 4027
7483 14:47:26.502586 292 : 4360, 4137
7484 14:47:26.505661 296 : 4361, 4137
7485 14:47:26.505759 300 : 4250, 4027
7486 14:47:26.508908 304 : 4363, 4140
7487 14:47:26.509039 308 : 4250, 4027
7488 14:47:26.512782 312 : 4253, 4027
7489 14:47:26.512879 316 : 4253, 4029
7490 14:47:26.515589 320 : 4252, 4030
7491 14:47:26.515685 324 : 4250, 4027
7492 14:47:26.519375 328 : 4250, 4026
7493 14:47:26.519472 332 : 4250, 3150
7494 14:47:26.522181 336 : 4252, 130
7495 14:47:26.522248
7496 14:47:26.522309 MIOCK jitter meter ch=0
7497 14:47:26.522403
7498 14:47:26.525983 1T = (336-100) = 236 dly cells
7499 14:47:26.532530 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7500 14:47:26.532629 ==
7501 14:47:26.535724 Dram Type= 6, Freq= 0, CH_0, rank 0
7502 14:47:26.539354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 14:47:26.539426 ==
7504 14:47:26.545487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 14:47:26.548897 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 14:47:26.552409 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 14:47:26.558909 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 14:47:26.568631 [CA 0] Center 44 (14~75) winsize 62
7509 14:47:26.571747 [CA 1] Center 43 (13~74) winsize 62
7510 14:47:26.575154 [CA 2] Center 39 (10~68) winsize 59
7511 14:47:26.578321 [CA 3] Center 39 (10~68) winsize 59
7512 14:47:26.582523 [CA 4] Center 37 (8~67) winsize 60
7513 14:47:26.584937 [CA 5] Center 37 (7~67) winsize 61
7514 14:47:26.585024
7515 14:47:26.588244 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7516 14:47:26.588310
7517 14:47:26.593226 [CATrainingPosCal] consider 1 rank data
7518 14:47:26.595069 u2DelayCellTimex100 = 275/100 ps
7519 14:47:26.602115 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7520 14:47:26.605571 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7521 14:47:26.608656 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7522 14:47:26.611565 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7523 14:47:26.615138 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7524 14:47:26.618444 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7525 14:47:26.618548
7526 14:47:26.621605 CA PerBit enable=1, Macro0, CA PI delay=37
7527 14:47:26.621676
7528 14:47:26.625011 [CBTSetCACLKResult] CA Dly = 37
7529 14:47:26.628789 CS Dly: 10 (0~41)
7530 14:47:26.631761 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 14:47:26.635040 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 14:47:26.635140 ==
7533 14:47:26.638638 Dram Type= 6, Freq= 0, CH_0, rank 1
7534 14:47:26.641548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 14:47:26.644870 ==
7536 14:47:26.648967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7537 14:47:26.651301 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7538 14:47:26.658542 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7539 14:47:26.661534 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7540 14:47:26.673182 [CA 0] Center 44 (14~75) winsize 62
7541 14:47:26.675820 [CA 1] Center 44 (14~75) winsize 62
7542 14:47:26.679049 [CA 2] Center 40 (11~69) winsize 59
7543 14:47:26.682882 [CA 3] Center 39 (10~69) winsize 60
7544 14:47:26.685937 [CA 4] Center 37 (8~67) winsize 60
7545 14:47:26.688968 [CA 5] Center 37 (7~67) winsize 61
7546 14:47:26.689073
7547 14:47:26.692263 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7548 14:47:26.692331
7549 14:47:26.695858 [CATrainingPosCal] consider 2 rank data
7550 14:47:26.698912 u2DelayCellTimex100 = 275/100 ps
7551 14:47:26.702677 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7552 14:47:26.709275 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7553 14:47:26.712769 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7554 14:47:26.715453 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7555 14:47:26.718797 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7556 14:47:26.722211 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7557 14:47:26.722302
7558 14:47:26.725458 CA PerBit enable=1, Macro0, CA PI delay=37
7559 14:47:26.725531
7560 14:47:26.728731 [CBTSetCACLKResult] CA Dly = 37
7561 14:47:26.731989 CS Dly: 11 (0~44)
7562 14:47:26.735351 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7563 14:47:26.738703 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7564 14:47:26.738797
7565 14:47:26.742403 ----->DramcWriteLeveling(PI) begin...
7566 14:47:26.742474 ==
7567 14:47:26.745672 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 14:47:26.749275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 14:47:26.752047 ==
7570 14:47:26.752144 Write leveling (Byte 0): 33 => 33
7571 14:47:26.755682 Write leveling (Byte 1): 26 => 26
7572 14:47:26.758942 DramcWriteLeveling(PI) end<-----
7573 14:47:26.759042
7574 14:47:26.759132 ==
7575 14:47:26.762000 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 14:47:26.768649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 14:47:26.768752 ==
7578 14:47:26.771941 [Gating] SW mode calibration
7579 14:47:26.779018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7580 14:47:26.783219 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7581 14:47:26.788603 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 14:47:26.792061 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 14:47:26.795791 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 14:47:26.798874 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 14:47:26.805858 1 4 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7586 14:47:26.809105 1 4 20 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7587 14:47:26.812197 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7588 14:47:26.818681 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 14:47:26.822478 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 14:47:26.825271 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 14:47:26.832247 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 14:47:26.835742 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 14:47:26.838880 1 5 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7594 14:47:26.845574 1 5 20 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
7595 14:47:26.849250 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7596 14:47:26.852303 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 14:47:26.859948 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 14:47:26.862120 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 14:47:26.865737 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 14:47:26.872646 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 14:47:26.875374 1 6 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7602 14:47:26.879126 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7603 14:47:26.882405 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7604 14:47:26.888851 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 14:47:26.893570 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 14:47:26.897534 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 14:47:26.902487 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 14:47:26.905734 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 14:47:26.909213 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 14:47:26.915939 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 14:47:26.918868 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7612 14:47:26.922376 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 14:47:26.929102 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 14:47:26.932087 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 14:47:26.935495 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 14:47:26.942232 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 14:47:26.945759 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 14:47:26.948810 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 14:47:26.956076 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 14:47:26.959336 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 14:47:26.962269 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 14:47:26.965514 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 14:47:26.972254 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 14:47:26.975913 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 14:47:26.979354 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 14:47:26.985345 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 14:47:26.989271 Total UI for P1: 0, mck2ui 16
7628 14:47:26.992292 best dqsien dly found for B0: ( 1, 9, 16)
7629 14:47:26.996733 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7630 14:47:26.999214 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 14:47:27.002264 Total UI for P1: 0, mck2ui 16
7632 14:47:27.005577 best dqsien dly found for B1: ( 1, 9, 22)
7633 14:47:27.008758 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7634 14:47:27.013352 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7635 14:47:27.013424
7636 14:47:27.019289 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7637 14:47:27.022224 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7638 14:47:27.025616 [Gating] SW calibration Done
7639 14:47:27.025687 ==
7640 14:47:27.028773 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 14:47:27.032458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 14:47:27.032533 ==
7643 14:47:27.032594 RX Vref Scan: 0
7644 14:47:27.032655
7645 14:47:27.035546 RX Vref 0 -> 0, step: 1
7646 14:47:27.035613
7647 14:47:27.039050 RX Delay 0 -> 252, step: 8
7648 14:47:27.042362 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7649 14:47:27.046059 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7650 14:47:27.048877 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7651 14:47:27.056062 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7652 14:47:27.059590 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7653 14:47:27.062317 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7654 14:47:27.065616 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7655 14:47:27.068903 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7656 14:47:27.075739 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7657 14:47:27.078982 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7658 14:47:27.082778 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7659 14:47:27.085630 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7660 14:47:27.089364 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7661 14:47:27.096633 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7662 14:47:27.099419 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7663 14:47:27.102696 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7664 14:47:27.102765 ==
7665 14:47:27.106656 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 14:47:27.109597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 14:47:27.109698 ==
7668 14:47:27.112585 DQS Delay:
7669 14:47:27.112652 DQS0 = 0, DQS1 = 0
7670 14:47:27.115857 DQM Delay:
7671 14:47:27.115930 DQM0 = 132, DQM1 = 125
7672 14:47:27.115989 DQ Delay:
7673 14:47:27.119982 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7674 14:47:27.122652 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7675 14:47:27.129434 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7676 14:47:27.132786 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7677 14:47:27.132853
7678 14:47:27.132914
7679 14:47:27.132970 ==
7680 14:47:27.135934 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 14:47:27.139633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 14:47:27.139708 ==
7683 14:47:27.139767
7684 14:47:27.139824
7685 14:47:27.143038 TX Vref Scan disable
7686 14:47:27.146773 == TX Byte 0 ==
7687 14:47:27.149494 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7688 14:47:27.152833 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7689 14:47:27.155783 == TX Byte 1 ==
7690 14:47:27.159435 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7691 14:47:27.162506 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7692 14:47:27.162576 ==
7693 14:47:27.166204 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 14:47:27.169260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 14:47:27.169331 ==
7696 14:47:27.185833
7697 14:47:27.188633 TX Vref early break, caculate TX vref
7698 14:47:27.192167 TX Vref=16, minBit 8, minWin=21, winSum=361
7699 14:47:27.195747 TX Vref=18, minBit 4, minWin=22, winSum=375
7700 14:47:27.199145 TX Vref=20, minBit 4, minWin=23, winSum=384
7701 14:47:27.202079 TX Vref=22, minBit 0, minWin=24, winSum=391
7702 14:47:27.205773 TX Vref=24, minBit 2, minWin=24, winSum=405
7703 14:47:27.212385 TX Vref=26, minBit 4, minWin=24, winSum=410
7704 14:47:27.215418 TX Vref=28, minBit 4, minWin=25, winSum=419
7705 14:47:27.218917 TX Vref=30, minBit 0, minWin=25, winSum=416
7706 14:47:27.222476 TX Vref=32, minBit 4, minWin=24, winSum=403
7707 14:47:27.225665 TX Vref=34, minBit 0, minWin=24, winSum=400
7708 14:47:27.228670 TX Vref=36, minBit 4, minWin=23, winSum=387
7709 14:47:27.235325 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 28
7710 14:47:27.235396
7711 14:47:27.238660 Final TX Range 0 Vref 28
7712 14:47:27.238728
7713 14:47:27.238785 ==
7714 14:47:27.242363 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 14:47:27.245203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 14:47:27.245272 ==
7717 14:47:27.245330
7718 14:47:27.245388
7719 14:47:27.248585 TX Vref Scan disable
7720 14:47:27.255629 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7721 14:47:27.255703 == TX Byte 0 ==
7722 14:47:27.259131 u2DelayCellOfst[0]=14 cells (4 PI)
7723 14:47:27.262933 u2DelayCellOfst[1]=21 cells (6 PI)
7724 14:47:27.266363 u2DelayCellOfst[2]=10 cells (3 PI)
7725 14:47:27.268940 u2DelayCellOfst[3]=17 cells (5 PI)
7726 14:47:27.272252 u2DelayCellOfst[4]=10 cells (3 PI)
7727 14:47:27.275597 u2DelayCellOfst[5]=0 cells (0 PI)
7728 14:47:27.278670 u2DelayCellOfst[6]=21 cells (6 PI)
7729 14:47:27.282489 u2DelayCellOfst[7]=21 cells (6 PI)
7730 14:47:27.285795 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7731 14:47:27.288956 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7732 14:47:27.292150 == TX Byte 1 ==
7733 14:47:27.295660 u2DelayCellOfst[8]=0 cells (0 PI)
7734 14:47:27.295760 u2DelayCellOfst[9]=0 cells (0 PI)
7735 14:47:27.299400 u2DelayCellOfst[10]=7 cells (2 PI)
7736 14:47:27.301899 u2DelayCellOfst[11]=0 cells (0 PI)
7737 14:47:27.305233 u2DelayCellOfst[12]=10 cells (3 PI)
7738 14:47:27.309416 u2DelayCellOfst[13]=10 cells (3 PI)
7739 14:47:27.311938 u2DelayCellOfst[14]=17 cells (5 PI)
7740 14:47:27.315211 u2DelayCellOfst[15]=10 cells (3 PI)
7741 14:47:27.319368 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7742 14:47:27.325347 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7743 14:47:27.325445 DramC Write-DBI on
7744 14:47:27.325542 ==
7745 14:47:27.329149 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 14:47:27.332353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 14:47:27.335502 ==
7748 14:47:27.335597
7749 14:47:27.335683
7750 14:47:27.335777 TX Vref Scan disable
7751 14:47:27.339483 == TX Byte 0 ==
7752 14:47:27.342277 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7753 14:47:27.346545 == TX Byte 1 ==
7754 14:47:27.349181 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7755 14:47:27.352915 DramC Write-DBI off
7756 14:47:27.353045
7757 14:47:27.353106 [DATLAT]
7758 14:47:27.353163 Freq=1600, CH0 RK0
7759 14:47:27.353222
7760 14:47:27.355926 DATLAT Default: 0xf
7761 14:47:27.355991 0, 0xFFFF, sum = 0
7762 14:47:27.359243 1, 0xFFFF, sum = 0
7763 14:47:27.359340 2, 0xFFFF, sum = 0
7764 14:47:27.362343 3, 0xFFFF, sum = 0
7765 14:47:27.365777 4, 0xFFFF, sum = 0
7766 14:47:27.365874 5, 0xFFFF, sum = 0
7767 14:47:27.369211 6, 0xFFFF, sum = 0
7768 14:47:27.369284 7, 0xFFFF, sum = 0
7769 14:47:27.372369 8, 0xFFFF, sum = 0
7770 14:47:27.372464 9, 0xFFFF, sum = 0
7771 14:47:27.376488 10, 0xFFFF, sum = 0
7772 14:47:27.376560 11, 0xFFFF, sum = 0
7773 14:47:27.379115 12, 0xFFFF, sum = 0
7774 14:47:27.379188 13, 0xFFFF, sum = 0
7775 14:47:27.382838 14, 0x0, sum = 1
7776 14:47:27.382908 15, 0x0, sum = 2
7777 14:47:27.385733 16, 0x0, sum = 3
7778 14:47:27.385802 17, 0x0, sum = 4
7779 14:47:27.388981 best_step = 15
7780 14:47:27.389103
7781 14:47:27.389187 ==
7782 14:47:27.393400 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 14:47:27.395519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 14:47:27.395614 ==
7785 14:47:27.395703 RX Vref Scan: 1
7786 14:47:27.395792
7787 14:47:27.399078 Set Vref Range= 24 -> 127
7788 14:47:27.399172
7789 14:47:27.402523 RX Vref 24 -> 127, step: 1
7790 14:47:27.402616
7791 14:47:27.405732 RX Delay 11 -> 252, step: 4
7792 14:47:27.405810
7793 14:47:27.409620 Set Vref, RX VrefLevel [Byte0]: 24
7794 14:47:27.412478 [Byte1]: 24
7795 14:47:27.412548
7796 14:47:27.415875 Set Vref, RX VrefLevel [Byte0]: 25
7797 14:47:27.419363 [Byte1]: 25
7798 14:47:27.419509
7799 14:47:27.423397 Set Vref, RX VrefLevel [Byte0]: 26
7800 14:47:27.426027 [Byte1]: 26
7801 14:47:27.430051
7802 14:47:27.430136 Set Vref, RX VrefLevel [Byte0]: 27
7803 14:47:27.432683 [Byte1]: 27
7804 14:47:27.437580
7805 14:47:27.437676 Set Vref, RX VrefLevel [Byte0]: 28
7806 14:47:27.440579 [Byte1]: 28
7807 14:47:27.444686
7808 14:47:27.444756 Set Vref, RX VrefLevel [Byte0]: 29
7809 14:47:27.448421 [Byte1]: 29
7810 14:47:27.452342
7811 14:47:27.452410 Set Vref, RX VrefLevel [Byte0]: 30
7812 14:47:27.455569 [Byte1]: 30
7813 14:47:27.459603
7814 14:47:27.459675 Set Vref, RX VrefLevel [Byte0]: 31
7815 14:47:27.463130 [Byte1]: 31
7816 14:47:27.467568
7817 14:47:27.467662 Set Vref, RX VrefLevel [Byte0]: 32
7818 14:47:27.470869 [Byte1]: 32
7819 14:47:27.475101
7820 14:47:27.475169 Set Vref, RX VrefLevel [Byte0]: 33
7821 14:47:27.478209 [Byte1]: 33
7822 14:47:27.482702
7823 14:47:27.482770 Set Vref, RX VrefLevel [Byte0]: 34
7824 14:47:27.486174 [Byte1]: 34
7825 14:47:27.490602
7826 14:47:27.490669 Set Vref, RX VrefLevel [Byte0]: 35
7827 14:47:27.493813 [Byte1]: 35
7828 14:47:27.498203
7829 14:47:27.498297 Set Vref, RX VrefLevel [Byte0]: 36
7830 14:47:27.501093 [Byte1]: 36
7831 14:47:27.505686
7832 14:47:27.505753 Set Vref, RX VrefLevel [Byte0]: 37
7833 14:47:27.509176 [Byte1]: 37
7834 14:47:27.513704
7835 14:47:27.513772 Set Vref, RX VrefLevel [Byte0]: 38
7836 14:47:27.516515 [Byte1]: 38
7837 14:47:27.521381
7838 14:47:27.521454 Set Vref, RX VrefLevel [Byte0]: 39
7839 14:47:27.524176 [Byte1]: 39
7840 14:47:27.528152
7841 14:47:27.528219 Set Vref, RX VrefLevel [Byte0]: 40
7842 14:47:27.531745 [Byte1]: 40
7843 14:47:27.535863
7844 14:47:27.535930 Set Vref, RX VrefLevel [Byte0]: 41
7845 14:47:27.539076 [Byte1]: 41
7846 14:47:27.543658
7847 14:47:27.543756 Set Vref, RX VrefLevel [Byte0]: 42
7848 14:47:27.547199 [Byte1]: 42
7849 14:47:27.551627
7850 14:47:27.551700 Set Vref, RX VrefLevel [Byte0]: 43
7851 14:47:27.554647 [Byte1]: 43
7852 14:47:27.558616
7853 14:47:27.558710 Set Vref, RX VrefLevel [Byte0]: 44
7854 14:47:27.562258 [Byte1]: 44
7855 14:47:27.566886
7856 14:47:27.566983 Set Vref, RX VrefLevel [Byte0]: 45
7857 14:47:27.569570 [Byte1]: 45
7858 14:47:27.573937
7859 14:47:27.574031 Set Vref, RX VrefLevel [Byte0]: 46
7860 14:47:27.578422 [Byte1]: 46
7861 14:47:27.581841
7862 14:47:27.581912 Set Vref, RX VrefLevel [Byte0]: 47
7863 14:47:27.585398 [Byte1]: 47
7864 14:47:27.589082
7865 14:47:27.589150 Set Vref, RX VrefLevel [Byte0]: 48
7866 14:47:27.592459 [Byte1]: 48
7867 14:47:27.596771
7868 14:47:27.596865 Set Vref, RX VrefLevel [Byte0]: 49
7869 14:47:27.600069 [Byte1]: 49
7870 14:47:27.604801
7871 14:47:27.604901 Set Vref, RX VrefLevel [Byte0]: 50
7872 14:47:27.607904 [Byte1]: 50
7873 14:47:27.611885
7874 14:47:27.611990 Set Vref, RX VrefLevel [Byte0]: 51
7875 14:47:27.615756 [Byte1]: 51
7876 14:47:27.620403
7877 14:47:27.620500 Set Vref, RX VrefLevel [Byte0]: 52
7878 14:47:27.623089 [Byte1]: 52
7879 14:47:27.627678
7880 14:47:27.627777 Set Vref, RX VrefLevel [Byte0]: 53
7881 14:47:27.631170 [Byte1]: 53
7882 14:47:27.635361
7883 14:47:27.635457 Set Vref, RX VrefLevel [Byte0]: 54
7884 14:47:27.638672 [Byte1]: 54
7885 14:47:27.642366
7886 14:47:27.642435 Set Vref, RX VrefLevel [Byte0]: 55
7887 14:47:27.646033 [Byte1]: 55
7888 14:47:27.650356
7889 14:47:27.650425 Set Vref, RX VrefLevel [Byte0]: 56
7890 14:47:27.653388 [Byte1]: 56
7891 14:47:27.657775
7892 14:47:27.657846 Set Vref, RX VrefLevel [Byte0]: 57
7893 14:47:27.661334 [Byte1]: 57
7894 14:47:27.665456
7895 14:47:27.665553 Set Vref, RX VrefLevel [Byte0]: 58
7896 14:47:27.668585 [Byte1]: 58
7897 14:47:27.672798
7898 14:47:27.672900 Set Vref, RX VrefLevel [Byte0]: 59
7899 14:47:27.676181 [Byte1]: 59
7900 14:47:27.680590
7901 14:47:27.680659 Set Vref, RX VrefLevel [Byte0]: 60
7902 14:47:27.684042 [Byte1]: 60
7903 14:47:27.688978
7904 14:47:27.689076 Set Vref, RX VrefLevel [Byte0]: 61
7905 14:47:27.691575 [Byte1]: 61
7906 14:47:27.695689
7907 14:47:27.695793 Set Vref, RX VrefLevel [Byte0]: 62
7908 14:47:27.699347 [Byte1]: 62
7909 14:47:27.703253
7910 14:47:27.703325 Set Vref, RX VrefLevel [Byte0]: 63
7911 14:47:27.707044 [Byte1]: 63
7912 14:47:27.711860
7913 14:47:27.711965 Set Vref, RX VrefLevel [Byte0]: 64
7914 14:47:27.715034 [Byte1]: 64
7915 14:47:27.718858
7916 14:47:27.718929 Set Vref, RX VrefLevel [Byte0]: 65
7917 14:47:27.722380 [Byte1]: 65
7918 14:47:27.726374
7919 14:47:27.726444 Set Vref, RX VrefLevel [Byte0]: 66
7920 14:47:27.730379 [Byte1]: 66
7921 14:47:27.733699
7922 14:47:27.733798 Set Vref, RX VrefLevel [Byte0]: 67
7923 14:47:27.737328 [Byte1]: 67
7924 14:47:27.742506
7925 14:47:27.742602 Set Vref, RX VrefLevel [Byte0]: 68
7926 14:47:27.744936 [Byte1]: 68
7927 14:47:27.749784
7928 14:47:27.749854 Set Vref, RX VrefLevel [Byte0]: 69
7929 14:47:27.752441 [Byte1]: 69
7930 14:47:27.756652
7931 14:47:27.756747 Set Vref, RX VrefLevel [Byte0]: 70
7932 14:47:27.760110 [Byte1]: 70
7933 14:47:27.764706
7934 14:47:27.764781 Set Vref, RX VrefLevel [Byte0]: 71
7935 14:47:27.767710 [Byte1]: 71
7936 14:47:27.772004
7937 14:47:27.772102 Set Vref, RX VrefLevel [Byte0]: 72
7938 14:47:27.775653 [Byte1]: 72
7939 14:47:27.780221
7940 14:47:27.780302 Set Vref, RX VrefLevel [Byte0]: 73
7941 14:47:27.783277 [Byte1]: 73
7942 14:47:27.786949
7943 14:47:27.787022 Set Vref, RX VrefLevel [Byte0]: 74
7944 14:47:27.790875 [Byte1]: 74
7945 14:47:27.795034
7946 14:47:27.795141 Set Vref, RX VrefLevel [Byte0]: 75
7947 14:47:27.798911 [Byte1]: 75
7948 14:47:27.802472
7949 14:47:27.802561 Final RX Vref Byte 0 = 60 to rank0
7950 14:47:27.805906 Final RX Vref Byte 1 = 62 to rank0
7951 14:47:27.809269 Final RX Vref Byte 0 = 60 to rank1
7952 14:47:27.812504 Final RX Vref Byte 1 = 62 to rank1==
7953 14:47:27.816203 Dram Type= 6, Freq= 0, CH_0, rank 0
7954 14:47:27.822494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 14:47:27.822569 ==
7956 14:47:27.822630 DQS Delay:
7957 14:47:27.822688 DQS0 = 0, DQS1 = 0
7958 14:47:27.825943 DQM Delay:
7959 14:47:27.826037 DQM0 = 129, DQM1 = 122
7960 14:47:27.829270 DQ Delay:
7961 14:47:27.833269 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7962 14:47:27.835773 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =136
7963 14:47:27.838812 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7964 14:47:27.842651 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =130
7965 14:47:27.842746
7966 14:47:27.842832
7967 14:47:27.842926
7968 14:47:27.845935 [DramC_TX_OE_Calibration] TA2
7969 14:47:27.848908 Original DQ_B0 (3 6) =30, OEN = 27
7970 14:47:27.852497 Original DQ_B1 (3 6) =30, OEN = 27
7971 14:47:27.855864 24, 0x0, End_B0=24 End_B1=24
7972 14:47:27.855971 25, 0x0, End_B0=25 End_B1=25
7973 14:47:27.859252 26, 0x0, End_B0=26 End_B1=26
7974 14:47:27.862564 27, 0x0, End_B0=27 End_B1=27
7975 14:47:27.865684 28, 0x0, End_B0=28 End_B1=28
7976 14:47:27.865799 29, 0x0, End_B0=29 End_B1=29
7977 14:47:27.869300 30, 0x0, End_B0=30 End_B1=30
7978 14:47:27.872212 31, 0x4141, End_B0=30 End_B1=30
7979 14:47:27.876147 Byte0 end_step=30 best_step=27
7980 14:47:27.879127 Byte1 end_step=30 best_step=27
7981 14:47:27.882529 Byte0 TX OE(2T, 0.5T) = (3, 3)
7982 14:47:27.882601 Byte1 TX OE(2T, 0.5T) = (3, 3)
7983 14:47:27.882661
7984 14:47:27.885628
7985 14:47:27.892743 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7986 14:47:27.896860 CH0 RK0: MR19=303, MR18=1307
7987 14:47:27.902240 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
7988 14:47:27.902316
7989 14:47:27.905854 ----->DramcWriteLeveling(PI) begin...
7990 14:47:27.905928 ==
7991 14:47:27.908866 Dram Type= 6, Freq= 0, CH_0, rank 1
7992 14:47:27.912577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7993 14:47:27.912648 ==
7994 14:47:27.915624 Write leveling (Byte 0): 32 => 32
7995 14:47:27.919449 Write leveling (Byte 1): 25 => 25
7996 14:47:27.922781 DramcWriteLeveling(PI) end<-----
7997 14:47:27.922855
7998 14:47:27.922915 ==
7999 14:47:27.925694 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 14:47:27.929473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 14:47:27.929556 ==
8002 14:47:27.932453 [Gating] SW mode calibration
8003 14:47:27.939209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8004 14:47:27.945929 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8005 14:47:27.949086 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 14:47:27.952494 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 14:47:27.959335 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8008 14:47:27.962531 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8009 14:47:27.965877 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8010 14:47:27.972982 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (1 1) (1 1)
8011 14:47:27.976414 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 14:47:27.979184 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 14:47:27.985848 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 14:47:27.988786 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 14:47:27.992051 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8016 14:47:27.999215 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
8017 14:47:28.002617 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8018 14:47:28.005917 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
8019 14:47:28.009386 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 14:47:28.016373 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 14:47:28.019185 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 14:47:28.022421 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 14:47:28.028830 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
8024 14:47:28.031842 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8025 14:47:28.035400 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8026 14:47:28.042300 1 6 20 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8027 14:47:28.045081 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 14:47:28.048635 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 14:47:28.055214 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 14:47:28.058261 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 14:47:28.061996 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 14:47:28.068239 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8033 14:47:28.072072 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8034 14:47:28.074887 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8035 14:47:28.081539 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 14:47:28.084920 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 14:47:28.088219 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 14:47:28.095054 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 14:47:28.098309 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 14:47:28.102169 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 14:47:28.108550 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 14:47:28.111534 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 14:47:28.114576 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 14:47:28.121906 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 14:47:28.124565 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 14:47:28.128716 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 14:47:28.135137 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8048 14:47:28.138033 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8049 14:47:28.141983 Total UI for P1: 0, mck2ui 16
8050 14:47:28.144900 best dqsien dly found for B0: ( 1, 9, 6)
8051 14:47:28.148483 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 14:47:28.154836 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8053 14:47:28.158105 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 14:47:28.161515 Total UI for P1: 0, mck2ui 16
8055 14:47:28.164716 best dqsien dly found for B1: ( 1, 9, 18)
8056 14:47:28.167858 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8057 14:47:28.171286 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8058 14:47:28.171355
8059 14:47:28.174725 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8060 14:47:28.177836 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8061 14:47:28.181235 [Gating] SW calibration Done
8062 14:47:28.181308 ==
8063 14:47:28.185210 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 14:47:28.188025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 14:47:28.188090 ==
8066 14:47:28.191966 RX Vref Scan: 0
8067 14:47:28.192045
8068 14:47:28.194867 RX Vref 0 -> 0, step: 1
8069 14:47:28.194938
8070 14:47:28.194999 RX Delay 0 -> 252, step: 8
8071 14:47:28.202082 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8072 14:47:28.205240 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8073 14:47:28.208002 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8074 14:47:28.211445 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8075 14:47:28.215853 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8076 14:47:28.217929 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8077 14:47:28.224950 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8078 14:47:28.228168 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8079 14:47:28.231951 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8080 14:47:28.234733 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8081 14:47:28.238696 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8082 14:47:28.245101 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8083 14:47:28.247964 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8084 14:47:28.251368 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8085 14:47:28.254605 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8086 14:47:28.261260 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8087 14:47:28.261360 ==
8088 14:47:28.264601 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 14:47:28.268400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 14:47:28.268473 ==
8091 14:47:28.268535 DQS Delay:
8092 14:47:28.271679 DQS0 = 0, DQS1 = 0
8093 14:47:28.271773 DQM Delay:
8094 14:47:28.275015 DQM0 = 130, DQM1 = 124
8095 14:47:28.275112 DQ Delay:
8096 14:47:28.277984 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8097 14:47:28.281739 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8098 14:47:28.285178 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8099 14:47:28.288199 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8100 14:47:28.288280
8101 14:47:28.288438
8102 14:47:28.288526 ==
8103 14:47:28.291512 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 14:47:28.298530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 14:47:28.298607 ==
8106 14:47:28.298673
8107 14:47:28.298731
8108 14:47:28.298786 TX Vref Scan disable
8109 14:47:28.302167 == TX Byte 0 ==
8110 14:47:28.305321 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8111 14:47:28.311629 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8112 14:47:28.311732 == TX Byte 1 ==
8113 14:47:28.315652 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8114 14:47:28.321733 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8115 14:47:28.321804 ==
8116 14:47:28.325052 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 14:47:28.328144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 14:47:28.328234 ==
8119 14:47:28.343377
8120 14:47:28.345998 TX Vref early break, caculate TX vref
8121 14:47:28.349610 TX Vref=16, minBit 8, minWin=22, winSum=372
8122 14:47:28.353365 TX Vref=18, minBit 8, minWin=22, winSum=378
8123 14:47:28.356033 TX Vref=20, minBit 3, minWin=23, winSum=386
8124 14:47:28.359482 TX Vref=22, minBit 0, minWin=24, winSum=397
8125 14:47:28.362746 TX Vref=24, minBit 9, minWin=24, winSum=406
8126 14:47:28.369233 TX Vref=26, minBit 1, minWin=25, winSum=417
8127 14:47:28.372870 TX Vref=28, minBit 7, minWin=25, winSum=421
8128 14:47:28.376359 TX Vref=30, minBit 8, minWin=24, winSum=415
8129 14:47:28.379483 TX Vref=32, minBit 1, minWin=25, winSum=410
8130 14:47:28.383204 TX Vref=34, minBit 4, minWin=24, winSum=402
8131 14:47:28.386686 TX Vref=36, minBit 8, minWin=23, winSum=392
8132 14:47:28.392663 [TxChooseVref] Worse bit 7, Min win 25, Win sum 421, Final Vref 28
8133 14:47:28.392764
8134 14:47:28.396597 Final TX Range 0 Vref 28
8135 14:47:28.396693
8136 14:47:28.396779 ==
8137 14:47:28.399800 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 14:47:28.402941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 14:47:28.403036 ==
8140 14:47:28.403123
8141 14:47:28.403211
8142 14:47:28.406180 TX Vref Scan disable
8143 14:47:28.412685 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8144 14:47:28.412788 == TX Byte 0 ==
8145 14:47:28.415897 u2DelayCellOfst[0]=14 cells (4 PI)
8146 14:47:28.419892 u2DelayCellOfst[1]=21 cells (6 PI)
8147 14:47:28.423005 u2DelayCellOfst[2]=14 cells (4 PI)
8148 14:47:28.426615 u2DelayCellOfst[3]=14 cells (4 PI)
8149 14:47:28.429299 u2DelayCellOfst[4]=10 cells (3 PI)
8150 14:47:28.433418 u2DelayCellOfst[5]=0 cells (0 PI)
8151 14:47:28.436514 u2DelayCellOfst[6]=21 cells (6 PI)
8152 14:47:28.439971 u2DelayCellOfst[7]=21 cells (6 PI)
8153 14:47:28.442843 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8154 14:47:28.446156 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8155 14:47:28.449321 == TX Byte 1 ==
8156 14:47:28.452740 u2DelayCellOfst[8]=0 cells (0 PI)
8157 14:47:28.452812 u2DelayCellOfst[9]=0 cells (0 PI)
8158 14:47:28.456259 u2DelayCellOfst[10]=3 cells (1 PI)
8159 14:47:28.459880 u2DelayCellOfst[11]=0 cells (0 PI)
8160 14:47:28.463120 u2DelayCellOfst[12]=10 cells (3 PI)
8161 14:47:28.466893 u2DelayCellOfst[13]=7 cells (2 PI)
8162 14:47:28.469461 u2DelayCellOfst[14]=14 cells (4 PI)
8163 14:47:28.472970 u2DelayCellOfst[15]=10 cells (3 PI)
8164 14:47:28.476322 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8165 14:47:28.482817 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8166 14:47:28.482915 DramC Write-DBI on
8167 14:47:28.483002 ==
8168 14:47:28.486798 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 14:47:28.489737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 14:47:28.489808 ==
8171 14:47:28.489868
8172 14:47:28.493878
8173 14:47:28.493971 TX Vref Scan disable
8174 14:47:28.496736 == TX Byte 0 ==
8175 14:47:28.500311 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8176 14:47:28.503258 == TX Byte 1 ==
8177 14:47:28.506572 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8178 14:47:28.506646 DramC Write-DBI off
8179 14:47:28.506705
8180 14:47:28.509761 [DATLAT]
8181 14:47:28.509829 Freq=1600, CH0 RK1
8182 14:47:28.509887
8183 14:47:28.513040 DATLAT Default: 0xf
8184 14:47:28.513106 0, 0xFFFF, sum = 0
8185 14:47:28.516501 1, 0xFFFF, sum = 0
8186 14:47:28.516567 2, 0xFFFF, sum = 0
8187 14:47:28.520243 3, 0xFFFF, sum = 0
8188 14:47:28.520311 4, 0xFFFF, sum = 0
8189 14:47:28.522985 5, 0xFFFF, sum = 0
8190 14:47:28.523053 6, 0xFFFF, sum = 0
8191 14:47:28.526404 7, 0xFFFF, sum = 0
8192 14:47:28.529962 8, 0xFFFF, sum = 0
8193 14:47:28.530036 9, 0xFFFF, sum = 0
8194 14:47:28.533296 10, 0xFFFF, sum = 0
8195 14:47:28.533365 11, 0xFFFF, sum = 0
8196 14:47:28.536508 12, 0xFFFF, sum = 0
8197 14:47:28.536602 13, 0xFFFF, sum = 0
8198 14:47:28.540772 14, 0x0, sum = 1
8199 14:47:28.540871 15, 0x0, sum = 2
8200 14:47:28.543583 16, 0x0, sum = 3
8201 14:47:28.543677 17, 0x0, sum = 4
8202 14:47:28.543764 best_step = 15
8203 14:47:28.546472
8204 14:47:28.546542 ==
8205 14:47:28.549713 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 14:47:28.553024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 14:47:28.553091 ==
8208 14:47:28.553148 RX Vref Scan: 0
8209 14:47:28.553208
8210 14:47:28.556334 RX Vref 0 -> 0, step: 1
8211 14:47:28.556425
8212 14:47:28.560206 RX Delay 11 -> 252, step: 4
8213 14:47:28.563172 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8214 14:47:28.566598 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8215 14:47:28.573100 iDelay=195, Bit 2, Center 122 (67 ~ 178) 112
8216 14:47:28.576241 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8217 14:47:28.580101 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8218 14:47:28.583302 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8219 14:47:28.586968 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8220 14:47:28.593348 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8221 14:47:28.597526 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8222 14:47:28.599705 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8223 14:47:28.603244 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8224 14:47:28.606967 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8225 14:47:28.613457 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8226 14:47:28.616638 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8227 14:47:28.619837 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8228 14:47:28.623419 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8229 14:47:28.623513 ==
8230 14:47:28.626460 Dram Type= 6, Freq= 0, CH_0, rank 1
8231 14:47:28.633071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 14:47:28.633143 ==
8233 14:47:28.633208 DQS Delay:
8234 14:47:28.633265 DQS0 = 0, DQS1 = 0
8235 14:47:28.636818 DQM Delay:
8236 14:47:28.636908 DQM0 = 127, DQM1 = 122
8237 14:47:28.640315 DQ Delay:
8238 14:47:28.643178 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8239 14:47:28.647212 DQ4 =126, DQ5 =116, DQ6 =138, DQ7 =134
8240 14:47:28.650949 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8241 14:47:28.653077 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8242 14:47:28.653146
8243 14:47:28.653204
8244 14:47:28.653260
8245 14:47:28.657786 [DramC_TX_OE_Calibration] TA2
8246 14:47:28.659965 Original DQ_B0 (3 6) =30, OEN = 27
8247 14:47:28.663464 Original DQ_B1 (3 6) =30, OEN = 27
8248 14:47:28.666363 24, 0x0, End_B0=24 End_B1=24
8249 14:47:28.666463 25, 0x0, End_B0=25 End_B1=25
8250 14:47:28.670174 26, 0x0, End_B0=26 End_B1=26
8251 14:47:28.673320 27, 0x0, End_B0=27 End_B1=27
8252 14:47:28.676614 28, 0x0, End_B0=28 End_B1=28
8253 14:47:28.676683 29, 0x0, End_B0=29 End_B1=29
8254 14:47:28.679853 30, 0x0, End_B0=30 End_B1=30
8255 14:47:28.683192 31, 0x4141, End_B0=30 End_B1=30
8256 14:47:28.686876 Byte0 end_step=30 best_step=27
8257 14:47:28.690612 Byte1 end_step=30 best_step=27
8258 14:47:28.693826 Byte0 TX OE(2T, 0.5T) = (3, 3)
8259 14:47:28.693918 Byte1 TX OE(2T, 0.5T) = (3, 3)
8260 14:47:28.694006
8261 14:47:28.694089
8262 14:47:28.703892 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8263 14:47:28.707032 CH0 RK1: MR19=303, MR18=180D
8264 14:47:28.713367 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8265 14:47:28.713438 [RxdqsGatingPostProcess] freq 1600
8266 14:47:28.720440 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8267 14:47:28.723230 best DQS0 dly(2T, 0.5T) = (1, 1)
8268 14:47:28.726461 best DQS1 dly(2T, 0.5T) = (1, 1)
8269 14:47:28.729928 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8270 14:47:28.733651 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8271 14:47:28.737102 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 14:47:28.739671 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 14:47:28.743714 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 14:47:28.743786 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 14:47:28.746844 Pre-setting of DQS Precalculation
8276 14:47:28.753476 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8277 14:47:28.753546 ==
8278 14:47:28.756897 Dram Type= 6, Freq= 0, CH_1, rank 0
8279 14:47:28.760128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 14:47:28.760194 ==
8281 14:47:28.766806 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8282 14:47:28.770300 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8283 14:47:28.774646 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8284 14:47:28.779973 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8285 14:47:28.789067 [CA 0] Center 44 (15~73) winsize 59
8286 14:47:28.792418 [CA 1] Center 43 (14~72) winsize 59
8287 14:47:28.796756 [CA 2] Center 38 (10~67) winsize 58
8288 14:47:28.799106 [CA 3] Center 37 (8~66) winsize 59
8289 14:47:28.802630 [CA 4] Center 38 (8~68) winsize 61
8290 14:47:28.806446 [CA 5] Center 37 (9~66) winsize 58
8291 14:47:28.806514
8292 14:47:28.809600 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8293 14:47:28.809667
8294 14:47:28.812618 [CATrainingPosCal] consider 1 rank data
8295 14:47:28.816094 u2DelayCellTimex100 = 275/100 ps
8296 14:47:28.819736 CA0 delay=44 (15~73),Diff = 7 PI (24 cell)
8297 14:47:28.825943 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8298 14:47:28.829250 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8299 14:47:28.833215 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8300 14:47:28.836202 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8301 14:47:28.839725 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8302 14:47:28.839816
8303 14:47:28.842841 CA PerBit enable=1, Macro0, CA PI delay=37
8304 14:47:28.842930
8305 14:47:28.846151 [CBTSetCACLKResult] CA Dly = 37
8306 14:47:28.846218 CS Dly: 9 (0~40)
8307 14:47:28.852631 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8308 14:47:28.856236 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8309 14:47:28.856328 ==
8310 14:47:28.859399 Dram Type= 6, Freq= 0, CH_1, rank 1
8311 14:47:28.862929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 14:47:28.863020 ==
8313 14:47:28.869264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8314 14:47:28.872814 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8315 14:47:28.879584 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8316 14:47:28.882791 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8317 14:47:28.892943 [CA 0] Center 43 (14~72) winsize 59
8318 14:47:28.895924 [CA 1] Center 43 (14~72) winsize 59
8319 14:47:28.899148 [CA 2] Center 38 (9~67) winsize 59
8320 14:47:28.902421 [CA 3] Center 37 (8~67) winsize 60
8321 14:47:28.906556 [CA 4] Center 38 (8~68) winsize 61
8322 14:47:28.909473 [CA 5] Center 36 (7~66) winsize 60
8323 14:47:28.909545
8324 14:47:28.912956 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8325 14:47:28.913084
8326 14:47:28.915744 [CATrainingPosCal] consider 2 rank data
8327 14:47:28.919394 u2DelayCellTimex100 = 275/100 ps
8328 14:47:28.922666 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8329 14:47:28.930921 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8330 14:47:28.932425 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8331 14:47:28.935977 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8332 14:47:28.939259 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8333 14:47:28.942688 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8334 14:47:28.942780
8335 14:47:28.945973 CA PerBit enable=1, Macro0, CA PI delay=37
8336 14:47:28.946040
8337 14:47:28.949877 [CBTSetCACLKResult] CA Dly = 37
8338 14:47:28.952865 CS Dly: 10 (0~43)
8339 14:47:28.956081 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8340 14:47:28.958798 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8341 14:47:28.958865
8342 14:47:28.963279 ----->DramcWriteLeveling(PI) begin...
8343 14:47:28.963352 ==
8344 14:47:28.965451 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 14:47:28.969112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 14:47:28.972452 ==
8347 14:47:28.972546 Write leveling (Byte 0): 23 => 23
8348 14:47:28.975957 Write leveling (Byte 1): 30 => 30
8349 14:47:28.979321 DramcWriteLeveling(PI) end<-----
8350 14:47:28.979414
8351 14:47:28.979500 ==
8352 14:47:28.982857 Dram Type= 6, Freq= 0, CH_1, rank 0
8353 14:47:28.989170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 14:47:28.989259 ==
8355 14:47:28.989325 [Gating] SW mode calibration
8356 14:47:28.999014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8357 14:47:29.002638 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8358 14:47:29.006222 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 14:47:29.012861 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 14:47:29.015793 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 14:47:29.019322 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 14:47:29.026260 1 4 16 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
8363 14:47:29.029479 1 4 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8364 14:47:29.032664 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 14:47:29.039208 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 14:47:29.043166 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 14:47:29.046497 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 14:47:29.052883 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 14:47:29.056215 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (0 1) (1 0)
8370 14:47:29.059916 1 5 16 | B1->B0 | 2727 2d2d | 0 0 | (1 0) (0 1)
8371 14:47:29.063148 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8372 14:47:29.069708 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 14:47:29.072891 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 14:47:29.076335 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 14:47:29.082927 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 14:47:29.086266 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 14:47:29.090155 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 14:47:29.096530 1 6 16 | B1->B0 | 4343 3b3b | 0 0 | (0 0) (0 0)
8379 14:47:29.099724 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 14:47:29.102875 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 14:47:29.109512 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 14:47:29.112971 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 14:47:29.116153 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 14:47:29.122902 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 14:47:29.126484 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 14:47:29.131229 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8387 14:47:29.136210 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 14:47:29.139493 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 14:47:29.143345 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 14:47:29.149872 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 14:47:29.153058 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 14:47:29.156041 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 14:47:29.159949 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 14:47:29.166801 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 14:47:29.169975 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 14:47:29.173233 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 14:47:29.179817 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 14:47:29.182939 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 14:47:29.186732 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 14:47:29.192802 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 14:47:29.197743 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 14:47:29.199987 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8403 14:47:29.206720 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 14:47:29.206821 Total UI for P1: 0, mck2ui 16
8405 14:47:29.213329 best dqsien dly found for B0: ( 1, 9, 16)
8406 14:47:29.213403 Total UI for P1: 0, mck2ui 16
8407 14:47:29.216547 best dqsien dly found for B1: ( 1, 9, 16)
8408 14:47:29.222983 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8409 14:47:29.226454 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8410 14:47:29.226524
8411 14:47:29.229898 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8412 14:47:29.233328 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8413 14:47:29.236518 [Gating] SW calibration Done
8414 14:47:29.236619 ==
8415 14:47:29.240645 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 14:47:29.243104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 14:47:29.243197 ==
8418 14:47:29.246949 RX Vref Scan: 0
8419 14:47:29.247025
8420 14:47:29.247117 RX Vref 0 -> 0, step: 1
8421 14:47:29.247202
8422 14:47:29.250102 RX Delay 0 -> 252, step: 8
8423 14:47:29.252957 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8424 14:47:29.260005 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8425 14:47:29.263002 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8426 14:47:29.266222 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8427 14:47:29.270223 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8428 14:47:29.273228 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8429 14:47:29.276578 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8430 14:47:29.282897 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8431 14:47:29.286473 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8432 14:47:29.289896 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8433 14:47:29.292911 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8434 14:47:29.296380 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8435 14:47:29.302988 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8436 14:47:29.307155 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8437 14:47:29.309959 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8438 14:47:29.313160 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8439 14:47:29.313242 ==
8440 14:47:29.316354 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 14:47:29.323555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 14:47:29.323638 ==
8443 14:47:29.323720 DQS Delay:
8444 14:47:29.323798 DQS0 = 0, DQS1 = 0
8445 14:47:29.326755 DQM Delay:
8446 14:47:29.326837 DQM0 = 134, DQM1 = 127
8447 14:47:29.329777 DQ Delay:
8448 14:47:29.333068 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8449 14:47:29.336653 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8450 14:47:29.340094 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8451 14:47:29.343253 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8452 14:47:29.343377
8453 14:47:29.343526
8454 14:47:29.343618 ==
8455 14:47:29.346599 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 14:47:29.349985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 14:47:29.350065 ==
8458 14:47:29.354872
8459 14:47:29.354952
8460 14:47:29.355013 TX Vref Scan disable
8461 14:47:29.356379 == TX Byte 0 ==
8462 14:47:29.360180 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8463 14:47:29.363034 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8464 14:47:29.366633 == TX Byte 1 ==
8465 14:47:29.369884 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8466 14:47:29.373177 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8467 14:47:29.373257 ==
8468 14:47:29.376780 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 14:47:29.383146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 14:47:29.383228 ==
8471 14:47:29.396658
8472 14:47:29.400331 TX Vref early break, caculate TX vref
8473 14:47:29.403475 TX Vref=16, minBit 8, minWin=21, winSum=359
8474 14:47:29.406875 TX Vref=18, minBit 5, minWin=22, winSum=370
8475 14:47:29.409522 TX Vref=20, minBit 8, minWin=22, winSum=382
8476 14:47:29.413097 TX Vref=22, minBit 8, minWin=23, winSum=389
8477 14:47:29.416635 TX Vref=24, minBit 5, minWin=24, winSum=405
8478 14:47:29.422979 TX Vref=26, minBit 0, minWin=25, winSum=415
8479 14:47:29.426393 TX Vref=28, minBit 8, minWin=25, winSum=420
8480 14:47:29.430695 TX Vref=30, minBit 5, minWin=25, winSum=418
8481 14:47:29.433532 TX Vref=32, minBit 8, minWin=24, winSum=411
8482 14:47:29.436687 TX Vref=34, minBit 8, minWin=24, winSum=401
8483 14:47:29.439857 TX Vref=36, minBit 9, minWin=23, winSum=390
8484 14:47:29.446300 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8485 14:47:29.446375
8486 14:47:29.449888 Final TX Range 0 Vref 28
8487 14:47:29.449991
8488 14:47:29.450079 ==
8489 14:47:29.453455 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 14:47:29.456556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 14:47:29.456649 ==
8492 14:47:29.456734
8493 14:47:29.456829
8494 14:47:29.459997 TX Vref Scan disable
8495 14:47:29.467024 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8496 14:47:29.467125 == TX Byte 0 ==
8497 14:47:29.469928 u2DelayCellOfst[0]=17 cells (5 PI)
8498 14:47:29.474203 u2DelayCellOfst[1]=14 cells (4 PI)
8499 14:47:29.476930 u2DelayCellOfst[2]=0 cells (0 PI)
8500 14:47:29.480125 u2DelayCellOfst[3]=7 cells (2 PI)
8501 14:47:29.483484 u2DelayCellOfst[4]=7 cells (2 PI)
8502 14:47:29.487161 u2DelayCellOfst[5]=17 cells (5 PI)
8503 14:47:29.490321 u2DelayCellOfst[6]=17 cells (5 PI)
8504 14:47:29.490419 u2DelayCellOfst[7]=7 cells (2 PI)
8505 14:47:29.497077 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8506 14:47:29.500023 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8507 14:47:29.500119 == TX Byte 1 ==
8508 14:47:29.503254 u2DelayCellOfst[8]=0 cells (0 PI)
8509 14:47:29.506730 u2DelayCellOfst[9]=7 cells (2 PI)
8510 14:47:29.510707 u2DelayCellOfst[10]=10 cells (3 PI)
8511 14:47:29.513617 u2DelayCellOfst[11]=7 cells (2 PI)
8512 14:47:29.517153 u2DelayCellOfst[12]=14 cells (4 PI)
8513 14:47:29.520220 u2DelayCellOfst[13]=21 cells (6 PI)
8514 14:47:29.523306 u2DelayCellOfst[14]=17 cells (5 PI)
8515 14:47:29.526875 u2DelayCellOfst[15]=17 cells (5 PI)
8516 14:47:29.529899 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8517 14:47:29.536703 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8518 14:47:29.536806 DramC Write-DBI on
8519 14:47:29.536894 ==
8520 14:47:29.540759 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 14:47:29.543307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 14:47:29.543403 ==
8523 14:47:29.543500
8524 14:47:29.547182
8525 14:47:29.547252 TX Vref Scan disable
8526 14:47:29.549925 == TX Byte 0 ==
8527 14:47:29.553900 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8528 14:47:29.557175 == TX Byte 1 ==
8529 14:47:29.560217 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8530 14:47:29.560310 DramC Write-DBI off
8531 14:47:29.560406
8532 14:47:29.563575 [DATLAT]
8533 14:47:29.563668 Freq=1600, CH1 RK0
8534 14:47:29.563754
8535 14:47:29.566858 DATLAT Default: 0xf
8536 14:47:29.566926 0, 0xFFFF, sum = 0
8537 14:47:29.570869 1, 0xFFFF, sum = 0
8538 14:47:29.570941 2, 0xFFFF, sum = 0
8539 14:47:29.573428 3, 0xFFFF, sum = 0
8540 14:47:29.573526 4, 0xFFFF, sum = 0
8541 14:47:29.576895 5, 0xFFFF, sum = 0
8542 14:47:29.576965 6, 0xFFFF, sum = 0
8543 14:47:29.580179 7, 0xFFFF, sum = 0
8544 14:47:29.580284 8, 0xFFFF, sum = 0
8545 14:47:29.584161 9, 0xFFFF, sum = 0
8546 14:47:29.584260 10, 0xFFFF, sum = 0
8547 14:47:29.586771 11, 0xFFFF, sum = 0
8548 14:47:29.590743 12, 0xFFFF, sum = 0
8549 14:47:29.590850 13, 0xFFFF, sum = 0
8550 14:47:29.593713 14, 0x0, sum = 1
8551 14:47:29.593784 15, 0x0, sum = 2
8552 14:47:29.596917 16, 0x0, sum = 3
8553 14:47:29.597045 17, 0x0, sum = 4
8554 14:47:29.597120 best_step = 15
8555 14:47:29.597177
8556 14:47:29.600270 ==
8557 14:47:29.600365 Dram Type= 6, Freq= 0, CH_1, rank 0
8558 14:47:29.607567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8559 14:47:29.607665 ==
8560 14:47:29.607753 RX Vref Scan: 1
8561 14:47:29.607837
8562 14:47:29.610671 Set Vref Range= 24 -> 127
8563 14:47:29.610741
8564 14:47:29.613468 RX Vref 24 -> 127, step: 1
8565 14:47:29.613552
8566 14:47:29.616840 RX Delay 11 -> 252, step: 4
8567 14:47:29.616932
8568 14:47:29.620530 Set Vref, RX VrefLevel [Byte0]: 24
8569 14:47:29.623481 [Byte1]: 24
8570 14:47:29.623576
8571 14:47:29.626844 Set Vref, RX VrefLevel [Byte0]: 25
8572 14:47:29.630784 [Byte1]: 25
8573 14:47:29.630855
8574 14:47:29.633483 Set Vref, RX VrefLevel [Byte0]: 26
8575 14:47:29.636891 [Byte1]: 26
8576 14:47:29.640747
8577 14:47:29.640849 Set Vref, RX VrefLevel [Byte0]: 27
8578 14:47:29.643580 [Byte1]: 27
8579 14:47:29.647787
8580 14:47:29.647883 Set Vref, RX VrefLevel [Byte0]: 28
8581 14:47:29.651391 [Byte1]: 28
8582 14:47:29.655703
8583 14:47:29.655797 Set Vref, RX VrefLevel [Byte0]: 29
8584 14:47:29.658480 [Byte1]: 29
8585 14:47:29.662851
8586 14:47:29.662919 Set Vref, RX VrefLevel [Byte0]: 30
8587 14:47:29.666779 [Byte1]: 30
8588 14:47:29.670623
8589 14:47:29.670718 Set Vref, RX VrefLevel [Byte0]: 31
8590 14:47:29.673780 [Byte1]: 31
8591 14:47:29.678365
8592 14:47:29.678435 Set Vref, RX VrefLevel [Byte0]: 32
8593 14:47:29.681477 [Byte1]: 32
8594 14:47:29.686336
8595 14:47:29.686410 Set Vref, RX VrefLevel [Byte0]: 33
8596 14:47:29.689189 [Byte1]: 33
8597 14:47:29.693297
8598 14:47:29.693399 Set Vref, RX VrefLevel [Byte0]: 34
8599 14:47:29.697842 [Byte1]: 34
8600 14:47:29.701049
8601 14:47:29.701153 Set Vref, RX VrefLevel [Byte0]: 35
8602 14:47:29.704242 [Byte1]: 35
8603 14:47:29.708573
8604 14:47:29.708669 Set Vref, RX VrefLevel [Byte0]: 36
8605 14:47:29.712206 [Byte1]: 36
8606 14:47:29.716337
8607 14:47:29.716431 Set Vref, RX VrefLevel [Byte0]: 37
8608 14:47:29.719504 [Byte1]: 37
8609 14:47:29.724265
8610 14:47:29.724366 Set Vref, RX VrefLevel [Byte0]: 38
8611 14:47:29.727300 [Byte1]: 38
8612 14:47:29.731675
8613 14:47:29.731771 Set Vref, RX VrefLevel [Byte0]: 39
8614 14:47:29.735529 [Byte1]: 39
8615 14:47:29.739705
8616 14:47:29.739799 Set Vref, RX VrefLevel [Byte0]: 40
8617 14:47:29.742728 [Byte1]: 40
8618 14:47:29.746738
8619 14:47:29.746813 Set Vref, RX VrefLevel [Byte0]: 41
8620 14:47:29.749902 [Byte1]: 41
8621 14:47:29.754846
8622 14:47:29.754926 Set Vref, RX VrefLevel [Byte0]: 42
8623 14:47:29.757582 [Byte1]: 42
8624 14:47:29.761744
8625 14:47:29.761823 Set Vref, RX VrefLevel [Byte0]: 43
8626 14:47:29.765921 [Byte1]: 43
8627 14:47:29.769699
8628 14:47:29.769778 Set Vref, RX VrefLevel [Byte0]: 44
8629 14:47:29.772608 [Byte1]: 44
8630 14:47:29.777458
8631 14:47:29.777538 Set Vref, RX VrefLevel [Byte0]: 45
8632 14:47:29.781449 [Byte1]: 45
8633 14:47:29.784843
8634 14:47:29.784948 Set Vref, RX VrefLevel [Byte0]: 46
8635 14:47:29.788413 [Byte1]: 46
8636 14:47:29.792371
8637 14:47:29.792449 Set Vref, RX VrefLevel [Byte0]: 47
8638 14:47:29.795511 [Byte1]: 47
8639 14:47:29.799722
8640 14:47:29.799801 Set Vref, RX VrefLevel [Byte0]: 48
8641 14:47:29.803249 [Byte1]: 48
8642 14:47:29.808794
8643 14:47:29.808898 Set Vref, RX VrefLevel [Byte0]: 49
8644 14:47:29.811051 [Byte1]: 49
8645 14:47:29.815102
8646 14:47:29.815181 Set Vref, RX VrefLevel [Byte0]: 50
8647 14:47:29.818803 [Byte1]: 50
8648 14:47:29.822770
8649 14:47:29.822849 Set Vref, RX VrefLevel [Byte0]: 51
8650 14:47:29.826803 [Byte1]: 51
8651 14:47:29.830233
8652 14:47:29.830312 Set Vref, RX VrefLevel [Byte0]: 52
8653 14:47:29.833997 [Byte1]: 52
8654 14:47:29.838572
8655 14:47:29.838650 Set Vref, RX VrefLevel [Byte0]: 53
8656 14:47:29.842118 [Byte1]: 53
8657 14:47:29.845969
8658 14:47:29.848956 Set Vref, RX VrefLevel [Byte0]: 54
8659 14:47:29.849078 [Byte1]: 54
8660 14:47:29.853794
8661 14:47:29.853873 Set Vref, RX VrefLevel [Byte0]: 55
8662 14:47:29.857049 [Byte1]: 55
8663 14:47:29.861229
8664 14:47:29.861308 Set Vref, RX VrefLevel [Byte0]: 56
8665 14:47:29.864354 [Byte1]: 56
8666 14:47:29.868619
8667 14:47:29.868699 Set Vref, RX VrefLevel [Byte0]: 57
8668 14:47:29.872207 [Byte1]: 57
8669 14:47:29.876162
8670 14:47:29.876241 Set Vref, RX VrefLevel [Byte0]: 58
8671 14:47:29.879456 [Byte1]: 58
8672 14:47:29.883524
8673 14:47:29.883603 Set Vref, RX VrefLevel [Byte0]: 59
8674 14:47:29.887317 [Byte1]: 59
8675 14:47:29.891735
8676 14:47:29.891814 Set Vref, RX VrefLevel [Byte0]: 60
8677 14:47:29.894647 [Byte1]: 60
8678 14:47:29.899595
8679 14:47:29.899674 Set Vref, RX VrefLevel [Byte0]: 61
8680 14:47:29.902292 [Byte1]: 61
8681 14:47:29.906832
8682 14:47:29.906912 Set Vref, RX VrefLevel [Byte0]: 62
8683 14:47:29.910078 [Byte1]: 62
8684 14:47:29.913921
8685 14:47:29.914001 Set Vref, RX VrefLevel [Byte0]: 63
8686 14:47:29.917641 [Byte1]: 63
8687 14:47:29.921571
8688 14:47:29.921676 Set Vref, RX VrefLevel [Byte0]: 64
8689 14:47:29.925927 [Byte1]: 64
8690 14:47:29.929301
8691 14:47:29.929379 Set Vref, RX VrefLevel [Byte0]: 65
8692 14:47:29.932516 [Byte1]: 65
8693 14:47:29.936860
8694 14:47:29.936939 Set Vref, RX VrefLevel [Byte0]: 66
8695 14:47:29.940821 [Byte1]: 66
8696 14:47:29.944600
8697 14:47:29.944680 Set Vref, RX VrefLevel [Byte0]: 67
8698 14:47:29.948467 [Byte1]: 67
8699 14:47:29.952096
8700 14:47:29.952174 Set Vref, RX VrefLevel [Byte0]: 68
8701 14:47:29.955401 [Byte1]: 68
8702 14:47:29.960853
8703 14:47:29.960958 Set Vref, RX VrefLevel [Byte0]: 69
8704 14:47:29.963679 [Byte1]: 69
8705 14:47:29.967244
8706 14:47:29.967324 Set Vref, RX VrefLevel [Byte0]: 70
8707 14:47:29.971220 [Byte1]: 70
8708 14:47:29.975349
8709 14:47:29.975428 Set Vref, RX VrefLevel [Byte0]: 71
8710 14:47:29.978698 [Byte1]: 71
8711 14:47:29.982480
8712 14:47:29.982559 Set Vref, RX VrefLevel [Byte0]: 72
8713 14:47:29.985917 [Byte1]: 72
8714 14:47:29.990480
8715 14:47:29.990559 Set Vref, RX VrefLevel [Byte0]: 73
8716 14:47:29.993817 [Byte1]: 73
8717 14:47:29.997958
8718 14:47:29.998037 Set Vref, RX VrefLevel [Byte0]: 74
8719 14:47:30.001145 [Byte1]: 74
8720 14:47:30.006161
8721 14:47:30.006276 Set Vref, RX VrefLevel [Byte0]: 75
8722 14:47:30.009109 [Byte1]: 75
8723 14:47:30.013583
8724 14:47:30.013663 Final RX Vref Byte 0 = 55 to rank0
8725 14:47:30.016528 Final RX Vref Byte 1 = 58 to rank0
8726 14:47:30.019554 Final RX Vref Byte 0 = 55 to rank1
8727 14:47:30.022963 Final RX Vref Byte 1 = 58 to rank1==
8728 14:47:30.027061 Dram Type= 6, Freq= 0, CH_1, rank 0
8729 14:47:30.033359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 14:47:30.033440 ==
8731 14:47:30.033503 DQS Delay:
8732 14:47:30.033561 DQS0 = 0, DQS1 = 0
8733 14:47:30.036295 DQM Delay:
8734 14:47:30.036374 DQM0 = 130, DQM1 = 124
8735 14:47:30.040104 DQ Delay:
8736 14:47:30.043375 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8737 14:47:30.046555 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =126
8738 14:47:30.049574 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =120
8739 14:47:30.053724 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8740 14:47:30.053819
8741 14:47:30.053884
8742 14:47:30.053943
8743 14:47:30.056604 [DramC_TX_OE_Calibration] TA2
8744 14:47:30.059901 Original DQ_B0 (3 6) =30, OEN = 27
8745 14:47:30.063067 Original DQ_B1 (3 6) =30, OEN = 27
8746 14:47:30.066900 24, 0x0, End_B0=24 End_B1=24
8747 14:47:30.066970 25, 0x0, End_B0=25 End_B1=25
8748 14:47:30.070062 26, 0x0, End_B0=26 End_B1=26
8749 14:47:30.073136 27, 0x0, End_B0=27 End_B1=27
8750 14:47:30.076563 28, 0x0, End_B0=28 End_B1=28
8751 14:47:30.076669 29, 0x0, End_B0=29 End_B1=29
8752 14:47:30.079895 30, 0x0, End_B0=30 End_B1=30
8753 14:47:30.083383 31, 0x4141, End_B0=30 End_B1=30
8754 14:47:30.086273 Byte0 end_step=30 best_step=27
8755 14:47:30.090027 Byte1 end_step=30 best_step=27
8756 14:47:30.093512 Byte0 TX OE(2T, 0.5T) = (3, 3)
8757 14:47:30.093606 Byte1 TX OE(2T, 0.5T) = (3, 3)
8758 14:47:30.093703
8759 14:47:30.096250
8760 14:47:30.103428 [DQSOSCAuto] RK0, (LSB)MR18= 0x15ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8761 14:47:30.106204 CH1 RK0: MR19=302, MR18=15FF
8762 14:47:30.113149 CH1_RK0: MR19=0x302, MR18=0x15FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8763 14:47:30.113226
8764 14:47:30.116119 ----->DramcWriteLeveling(PI) begin...
8765 14:47:30.116193 ==
8766 14:47:30.119768 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 14:47:30.122717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 14:47:30.122792 ==
8769 14:47:30.126624 Write leveling (Byte 0): 26 => 26
8770 14:47:30.129432 Write leveling (Byte 1): 28 => 28
8771 14:47:30.132840 DramcWriteLeveling(PI) end<-----
8772 14:47:30.132908
8773 14:47:30.132967 ==
8774 14:47:30.136222 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 14:47:30.140067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 14:47:30.140168 ==
8777 14:47:30.143321 [Gating] SW mode calibration
8778 14:47:30.149729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8779 14:47:30.156609 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8780 14:47:30.159684 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 14:47:30.163874 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 14:47:30.169863 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
8783 14:47:30.173467 1 4 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8784 14:47:30.177063 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 14:47:30.183219 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 14:47:30.186780 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 14:47:30.190528 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 14:47:30.196739 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 14:47:30.199550 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8790 14:47:30.203505 1 5 8 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
8791 14:47:30.206565 1 5 12 | B1->B0 | 3232 2626 | 0 0 | (0 1) (0 0)
8792 14:47:30.214046 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 14:47:30.216280 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 14:47:30.220058 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 14:47:30.226662 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 14:47:30.229511 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 14:47:30.232845 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 14:47:30.239968 1 6 8 | B1->B0 | 2424 3535 | 0 1 | (0 0) (0 0)
8799 14:47:30.242972 1 6 12 | B1->B0 | 3030 4545 | 1 0 | (0 0) (0 0)
8800 14:47:30.246817 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 14:47:30.252860 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 14:47:30.256332 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 14:47:30.259893 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 14:47:30.266465 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 14:47:30.269675 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 14:47:30.273347 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8807 14:47:30.279511 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8808 14:47:30.282765 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 14:47:30.286500 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8810 14:47:30.293031 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 14:47:30.296130 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 14:47:30.299878 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 14:47:30.306605 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 14:47:30.310048 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 14:47:30.313635 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 14:47:30.316256 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 14:47:30.323360 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 14:47:30.326400 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 14:47:30.329390 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 14:47:30.337019 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 14:47:30.339862 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8822 14:47:30.342555 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8823 14:47:30.349647 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8824 14:47:30.353163 Total UI for P1: 0, mck2ui 16
8825 14:47:30.356504 best dqsien dly found for B0: ( 1, 9, 6)
8826 14:47:30.359511 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 14:47:30.363051 Total UI for P1: 0, mck2ui 16
8828 14:47:30.366199 best dqsien dly found for B1: ( 1, 9, 12)
8829 14:47:30.369669 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8830 14:47:30.372493 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8831 14:47:30.372565
8832 14:47:30.376166 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8833 14:47:30.379346 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8834 14:47:30.382761 [Gating] SW calibration Done
8835 14:47:30.382827 ==
8836 14:47:30.385777 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 14:47:30.389384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 14:47:30.392967 ==
8839 14:47:30.393071 RX Vref Scan: 0
8840 14:47:30.393153
8841 14:47:30.396453 RX Vref 0 -> 0, step: 1
8842 14:47:30.396535
8843 14:47:30.396616 RX Delay 0 -> 252, step: 8
8844 14:47:30.402703 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8845 14:47:30.406384 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8846 14:47:30.409481 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8847 14:47:30.413011 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8848 14:47:30.416538 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8849 14:47:30.422602 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8850 14:47:30.426198 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8851 14:47:30.429920 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8852 14:47:30.432826 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8853 14:47:30.436570 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8854 14:47:30.442705 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8855 14:47:30.445860 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8856 14:47:30.449767 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8857 14:47:30.453047 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8858 14:47:30.456405 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8859 14:47:30.462959 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8860 14:47:30.463041 ==
8861 14:47:30.466022 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 14:47:30.469844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 14:47:30.469927 ==
8864 14:47:30.470009 DQS Delay:
8865 14:47:30.472795 DQS0 = 0, DQS1 = 0
8866 14:47:30.472900 DQM Delay:
8867 14:47:30.476212 DQM0 = 132, DQM1 = 127
8868 14:47:30.476286 DQ Delay:
8869 14:47:30.479787 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8870 14:47:30.483350 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8871 14:47:30.486047 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8872 14:47:30.490109 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8873 14:47:30.490191
8874 14:47:30.490273
8875 14:47:30.492946 ==
8876 14:47:30.496263 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 14:47:30.500510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 14:47:30.500607 ==
8879 14:47:30.500699
8880 14:47:30.500787
8881 14:47:30.502827 TX Vref Scan disable
8882 14:47:30.502920 == TX Byte 0 ==
8883 14:47:30.506323 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8884 14:47:30.513128 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8885 14:47:30.513210 == TX Byte 1 ==
8886 14:47:30.516544 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8887 14:47:30.523100 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8888 14:47:30.523183 ==
8889 14:47:30.526438 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 14:47:30.530193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 14:47:30.530276 ==
8892 14:47:30.543367
8893 14:47:30.546770 TX Vref early break, caculate TX vref
8894 14:47:30.550527 TX Vref=16, minBit 6, minWin=22, winSum=371
8895 14:47:30.553535 TX Vref=18, minBit 0, minWin=23, winSum=384
8896 14:47:30.556898 TX Vref=20, minBit 8, minWin=23, winSum=392
8897 14:47:30.560564 TX Vref=22, minBit 9, minWin=24, winSum=403
8898 14:47:30.563430 TX Vref=24, minBit 15, minWin=24, winSum=409
8899 14:47:30.570379 TX Vref=26, minBit 8, minWin=24, winSum=418
8900 14:47:30.573626 TX Vref=28, minBit 9, minWin=25, winSum=424
8901 14:47:30.576988 TX Vref=30, minBit 0, minWin=24, winSum=417
8902 14:47:30.580955 TX Vref=32, minBit 13, minWin=24, winSum=410
8903 14:47:30.583852 TX Vref=34, minBit 0, minWin=24, winSum=403
8904 14:47:30.587179 TX Vref=36, minBit 8, minWin=23, winSum=393
8905 14:47:30.593425 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 28
8906 14:47:30.593509
8907 14:47:30.597120 Final TX Range 0 Vref 28
8908 14:47:30.597202
8909 14:47:30.597284 ==
8910 14:47:30.600570 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 14:47:30.603327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 14:47:30.603410 ==
8913 14:47:30.603492
8914 14:47:30.603569
8915 14:47:30.606816 TX Vref Scan disable
8916 14:47:30.613982 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8917 14:47:30.614066 == TX Byte 0 ==
8918 14:47:30.616778 u2DelayCellOfst[0]=17 cells (5 PI)
8919 14:47:30.620517 u2DelayCellOfst[1]=10 cells (3 PI)
8920 14:47:30.623438 u2DelayCellOfst[2]=0 cells (0 PI)
8921 14:47:30.627042 u2DelayCellOfst[3]=7 cells (2 PI)
8922 14:47:30.630243 u2DelayCellOfst[4]=10 cells (3 PI)
8923 14:47:30.633718 u2DelayCellOfst[5]=17 cells (5 PI)
8924 14:47:30.637197 u2DelayCellOfst[6]=17 cells (5 PI)
8925 14:47:30.640412 u2DelayCellOfst[7]=7 cells (2 PI)
8926 14:47:30.643377 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8927 14:47:30.646791 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8928 14:47:30.650290 == TX Byte 1 ==
8929 14:47:30.650372 u2DelayCellOfst[8]=0 cells (0 PI)
8930 14:47:30.653814 u2DelayCellOfst[9]=0 cells (0 PI)
8931 14:47:30.656658 u2DelayCellOfst[10]=7 cells (2 PI)
8932 14:47:30.660138 u2DelayCellOfst[11]=0 cells (0 PI)
8933 14:47:30.663402 u2DelayCellOfst[12]=10 cells (3 PI)
8934 14:47:30.666827 u2DelayCellOfst[13]=14 cells (4 PI)
8935 14:47:30.670231 u2DelayCellOfst[14]=14 cells (4 PI)
8936 14:47:30.673528 u2DelayCellOfst[15]=10 cells (3 PI)
8937 14:47:30.677085 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8938 14:47:30.683628 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8939 14:47:30.683727 DramC Write-DBI on
8940 14:47:30.683815 ==
8941 14:47:30.687273 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 14:47:30.690502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 14:47:30.693499 ==
8944 14:47:30.693573
8945 14:47:30.693635
8946 14:47:30.693692 TX Vref Scan disable
8947 14:47:30.696780 == TX Byte 0 ==
8948 14:47:30.700183 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8949 14:47:30.704492 == TX Byte 1 ==
8950 14:47:30.707599 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8951 14:47:30.707694 DramC Write-DBI off
8952 14:47:30.710377
8953 14:47:30.710476 [DATLAT]
8954 14:47:30.710554 Freq=1600, CH1 RK1
8955 14:47:30.710628
8956 14:47:30.713462 DATLAT Default: 0xf
8957 14:47:30.713570 0, 0xFFFF, sum = 0
8958 14:47:30.718382 1, 0xFFFF, sum = 0
8959 14:47:30.718504 2, 0xFFFF, sum = 0
8960 14:47:30.722130 3, 0xFFFF, sum = 0
8961 14:47:30.723749 4, 0xFFFF, sum = 0
8962 14:47:30.723962 5, 0xFFFF, sum = 0
8963 14:47:30.727044 6, 0xFFFF, sum = 0
8964 14:47:30.727181 7, 0xFFFF, sum = 0
8965 14:47:30.730521 8, 0xFFFF, sum = 0
8966 14:47:30.730673 9, 0xFFFF, sum = 0
8967 14:47:30.733982 10, 0xFFFF, sum = 0
8968 14:47:30.734156 11, 0xFFFF, sum = 0
8969 14:47:30.736990 12, 0xFFFF, sum = 0
8970 14:47:30.737164 13, 0xFFFF, sum = 0
8971 14:47:30.740694 14, 0x0, sum = 1
8972 14:47:30.740954 15, 0x0, sum = 2
8973 14:47:30.744229 16, 0x0, sum = 3
8974 14:47:30.744539 17, 0x0, sum = 4
8975 14:47:30.747170 best_step = 15
8976 14:47:30.747444
8977 14:47:30.747633 ==
8978 14:47:30.750407 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 14:47:30.753928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 14:47:30.754311 ==
8981 14:47:30.754614 RX Vref Scan: 0
8982 14:47:30.754895
8983 14:47:30.758014 RX Vref 0 -> 0, step: 1
8984 14:47:30.758429
8985 14:47:30.760776 RX Delay 11 -> 252, step: 4
8986 14:47:30.764249 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8987 14:47:30.770507 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8988 14:47:30.773988 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8989 14:47:30.777501 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8990 14:47:30.780798 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8991 14:47:30.783833 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8992 14:47:30.787913 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8993 14:47:30.794175 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8994 14:47:30.797131 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8995 14:47:30.801641 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8996 14:47:30.803983 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8997 14:47:30.807844 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8998 14:47:30.814563 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8999 14:47:30.817564 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9000 14:47:30.820931 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9001 14:47:30.824368 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9002 14:47:30.824893 ==
9003 14:47:30.828132 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 14:47:30.835378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 14:47:30.835922 ==
9006 14:47:30.836286 DQS Delay:
9007 14:47:30.837287 DQS0 = 0, DQS1 = 0
9008 14:47:30.837794 DQM Delay:
9009 14:47:30.838288 DQM0 = 129, DQM1 = 126
9010 14:47:30.840583 DQ Delay:
9011 14:47:30.844948 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
9012 14:47:30.847203 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9013 14:47:30.850685 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120
9014 14:47:30.854260 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9015 14:47:30.854763
9016 14:47:30.855144
9017 14:47:30.855476
9018 14:47:30.857326 [DramC_TX_OE_Calibration] TA2
9019 14:47:30.861292 Original DQ_B0 (3 6) =30, OEN = 27
9020 14:47:30.863794 Original DQ_B1 (3 6) =30, OEN = 27
9021 14:47:30.867841 24, 0x0, End_B0=24 End_B1=24
9022 14:47:30.868399 25, 0x0, End_B0=25 End_B1=25
9023 14:47:30.871113 26, 0x0, End_B0=26 End_B1=26
9024 14:47:30.874138 27, 0x0, End_B0=27 End_B1=27
9025 14:47:30.877543 28, 0x0, End_B0=28 End_B1=28
9026 14:47:30.880868 29, 0x0, End_B0=29 End_B1=29
9027 14:47:30.881310 30, 0x0, End_B0=30 End_B1=30
9028 14:47:30.884811 31, 0x4141, End_B0=30 End_B1=30
9029 14:47:30.888236 Byte0 end_step=30 best_step=27
9030 14:47:30.892510 Byte1 end_step=30 best_step=27
9031 14:47:30.893830 Byte0 TX OE(2T, 0.5T) = (3, 3)
9032 14:47:30.897649 Byte1 TX OE(2T, 0.5T) = (3, 3)
9033 14:47:30.898193
9034 14:47:30.898553
9035 14:47:30.904459 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9036 14:47:30.907671 CH1 RK1: MR19=303, MR18=1117
9037 14:47:30.914367 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9038 14:47:30.917403 [RxdqsGatingPostProcess] freq 1600
9039 14:47:30.921114 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9040 14:47:30.925040 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 14:47:30.927519 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 14:47:30.931062 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 14:47:30.934080 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 14:47:30.938834 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 14:47:30.940657 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 14:47:30.944670 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 14:47:30.947319 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 14:47:30.950805 Pre-setting of DQS Precalculation
9049 14:47:30.954095 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9050 14:47:30.960652 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9051 14:47:30.967558 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 14:47:30.968107
9053 14:47:30.968464
9054 14:47:30.971136 [Calibration Summary] 3200 Mbps
9055 14:47:30.973822 CH 0, Rank 0
9056 14:47:30.974275 SW Impedance : PASS
9057 14:47:30.977207 DUTY Scan : NO K
9058 14:47:30.980473 ZQ Calibration : PASS
9059 14:47:30.980925 Jitter Meter : NO K
9060 14:47:30.983911 CBT Training : PASS
9061 14:47:30.987479 Write leveling : PASS
9062 14:47:30.988031 RX DQS gating : PASS
9063 14:47:30.990738 RX DQ/DQS(RDDQC) : PASS
9064 14:47:30.994138 TX DQ/DQS : PASS
9065 14:47:30.994685 RX DATLAT : PASS
9066 14:47:30.997677 RX DQ/DQS(Engine): PASS
9067 14:47:30.998218 TX OE : PASS
9068 14:47:31.000693 All Pass.
9069 14:47:31.001277
9070 14:47:31.001634 CH 0, Rank 1
9071 14:47:31.003870 SW Impedance : PASS
9072 14:47:31.007637 DUTY Scan : NO K
9073 14:47:31.008187 ZQ Calibration : PASS
9074 14:47:31.010824 Jitter Meter : NO K
9075 14:47:31.011272 CBT Training : PASS
9076 14:47:31.013731 Write leveling : PASS
9077 14:47:31.017576 RX DQS gating : PASS
9078 14:47:31.018020 RX DQ/DQS(RDDQC) : PASS
9079 14:47:31.020353 TX DQ/DQS : PASS
9080 14:47:31.023939 RX DATLAT : PASS
9081 14:47:31.024482 RX DQ/DQS(Engine): PASS
9082 14:47:31.027429 TX OE : PASS
9083 14:47:31.027908 All Pass.
9084 14:47:31.028260
9085 14:47:31.030075 CH 1, Rank 0
9086 14:47:31.030527 SW Impedance : PASS
9087 14:47:31.034445 DUTY Scan : NO K
9088 14:47:31.037811 ZQ Calibration : PASS
9089 14:47:31.038266 Jitter Meter : NO K
9090 14:47:31.040732 CBT Training : PASS
9091 14:47:31.043680 Write leveling : PASS
9092 14:47:31.044136 RX DQS gating : PASS
9093 14:47:31.047298 RX DQ/DQS(RDDQC) : PASS
9094 14:47:31.051754 TX DQ/DQS : PASS
9095 14:47:31.052321 RX DATLAT : PASS
9096 14:47:31.054107 RX DQ/DQS(Engine): PASS
9097 14:47:31.054648 TX OE : PASS
9098 14:47:31.057460 All Pass.
9099 14:47:31.057942
9100 14:47:31.058298 CH 1, Rank 1
9101 14:47:31.060488 SW Impedance : PASS
9102 14:47:31.060936 DUTY Scan : NO K
9103 14:47:31.063719 ZQ Calibration : PASS
9104 14:47:31.067647 Jitter Meter : NO K
9105 14:47:31.068212 CBT Training : PASS
9106 14:47:31.071020 Write leveling : PASS
9107 14:47:31.074587 RX DQS gating : PASS
9108 14:47:31.075134 RX DQ/DQS(RDDQC) : PASS
9109 14:47:31.077731 TX DQ/DQS : PASS
9110 14:47:31.080666 RX DATLAT : PASS
9111 14:47:31.081243 RX DQ/DQS(Engine): PASS
9112 14:47:31.083739 TX OE : PASS
9113 14:47:31.084189 All Pass.
9114 14:47:31.084562
9115 14:47:31.087752 DramC Write-DBI on
9116 14:47:31.090338 PER_BANK_REFRESH: Hybrid Mode
9117 14:47:31.090791 TX_TRACKING: ON
9118 14:47:31.100543 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9119 14:47:31.107344 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9120 14:47:31.115306 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 14:47:31.116737 [FAST_K] Save calibration result to emmc
9122 14:47:31.120418 sync common calibartion params.
9123 14:47:31.123397 sync cbt_mode0:1, 1:1
9124 14:47:31.127187 dram_init: ddr_geometry: 2
9125 14:47:31.127733 dram_init: ddr_geometry: 2
9126 14:47:31.130746 dram_init: ddr_geometry: 2
9127 14:47:31.134097 0:dram_rank_size:100000000
9128 14:47:31.134563 1:dram_rank_size:100000000
9129 14:47:31.140472 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9130 14:47:31.143856 DFS_SHUFFLE_HW_MODE: ON
9131 14:47:31.147200 dramc_set_vcore_voltage set vcore to 725000
9132 14:47:31.150523 Read voltage for 1600, 0
9133 14:47:31.150977 Vio18 = 0
9134 14:47:31.151335 Vcore = 725000
9135 14:47:31.154547 Vdram = 0
9136 14:47:31.155087 Vddq = 0
9137 14:47:31.155445 Vmddr = 0
9138 14:47:31.156919 switch to 3200 Mbps bootup
9139 14:47:31.157410 [DramcRunTimeConfig]
9140 14:47:31.160480 PHYPLL
9141 14:47:31.161080 DPM_CONTROL_AFTERK: ON
9142 14:47:31.164228 PER_BANK_REFRESH: ON
9143 14:47:31.167345 REFRESH_OVERHEAD_REDUCTION: ON
9144 14:47:31.167801 CMD_PICG_NEW_MODE: OFF
9145 14:47:31.171122 XRTWTW_NEW_MODE: ON
9146 14:47:31.171576 XRTRTR_NEW_MODE: ON
9147 14:47:31.173714 TX_TRACKING: ON
9148 14:47:31.174168 RDSEL_TRACKING: OFF
9149 14:47:31.177319 DQS Precalculation for DVFS: ON
9150 14:47:31.181019 RX_TRACKING: OFF
9151 14:47:31.181567 HW_GATING DBG: ON
9152 14:47:31.183733 ZQCS_ENABLE_LP4: ON
9153 14:47:31.184188 RX_PICG_NEW_MODE: ON
9154 14:47:31.187356 TX_PICG_NEW_MODE: ON
9155 14:47:31.187904 ENABLE_RX_DCM_DPHY: ON
9156 14:47:31.190459 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9157 14:47:31.193857 DUMMY_READ_FOR_TRACKING: OFF
9158 14:47:31.197719 !!! SPM_CONTROL_AFTERK: OFF
9159 14:47:31.200736 !!! SPM could not control APHY
9160 14:47:31.201336 IMPEDANCE_TRACKING: ON
9161 14:47:31.203913 TEMP_SENSOR: ON
9162 14:47:31.204365 HW_SAVE_FOR_SR: OFF
9163 14:47:31.207385 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9164 14:47:31.210673 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9165 14:47:31.213699 Read ODT Tracking: ON
9166 14:47:31.217617 Refresh Rate DeBounce: ON
9167 14:47:31.218162 DFS_NO_QUEUE_FLUSH: ON
9168 14:47:31.221538 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9169 14:47:31.224149 ENABLE_DFS_RUNTIME_MRW: OFF
9170 14:47:31.227500 DDR_RESERVE_NEW_MODE: ON
9171 14:47:31.228045 MR_CBT_SWITCH_FREQ: ON
9172 14:47:31.230707 =========================
9173 14:47:31.249050 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9174 14:47:31.253198 dram_init: ddr_geometry: 2
9175 14:47:31.271224 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9176 14:47:31.274549 dram_init: dram init end (result: 0)
9177 14:47:31.280448 DRAM-K: Full calibration passed in 24595 msecs
9178 14:47:31.283826 MRC: failed to locate region type 0.
9179 14:47:31.284284 DRAM rank0 size:0x100000000,
9180 14:47:31.287509 DRAM rank1 size=0x100000000
9181 14:47:31.297445 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9182 14:47:31.303933 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9183 14:47:31.311102 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9184 14:47:31.317414 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9185 14:47:31.320535 DRAM rank0 size:0x100000000,
9186 14:47:31.323995 DRAM rank1 size=0x100000000
9187 14:47:31.324449 CBMEM:
9188 14:47:31.327752 IMD: root @ 0xfffff000 254 entries.
9189 14:47:31.330568 IMD: root @ 0xffffec00 62 entries.
9190 14:47:31.333820 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9191 14:47:31.337035 WARNING: RO_VPD is uninitialized or empty.
9192 14:47:31.344254 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9193 14:47:31.350696 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9194 14:47:31.364417 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9195 14:47:31.375289 BS: romstage times (exec / console): total (unknown) / 24093 ms
9196 14:47:31.375834
9197 14:47:31.376193
9198 14:47:31.386154 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9199 14:47:31.388385 ARM64: Exception handlers installed.
9200 14:47:31.391555 ARM64: Testing exception
9201 14:47:31.395455 ARM64: Done test exception
9202 14:47:31.395913 Enumerating buses...
9203 14:47:31.398431 Show all devs... Before device enumeration.
9204 14:47:31.401225 Root Device: enabled 1
9205 14:47:31.404927 CPU_CLUSTER: 0: enabled 1
9206 14:47:31.405602 CPU: 00: enabled 1
9207 14:47:31.407961 Compare with tree...
9208 14:47:31.408414 Root Device: enabled 1
9209 14:47:31.411464 CPU_CLUSTER: 0: enabled 1
9210 14:47:31.414528 CPU: 00: enabled 1
9211 14:47:31.414989 Root Device scanning...
9212 14:47:31.419325 scan_static_bus for Root Device
9213 14:47:31.421344 CPU_CLUSTER: 0 enabled
9214 14:47:31.425037 scan_static_bus for Root Device done
9215 14:47:31.428102 scan_bus: bus Root Device finished in 8 msecs
9216 14:47:31.428665 done
9217 14:47:31.434794 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9218 14:47:31.438228 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9219 14:47:31.444840 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9220 14:47:31.447984 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9221 14:47:31.451889 Allocating resources...
9222 14:47:31.452440 Reading resources...
9223 14:47:31.458445 Root Device read_resources bus 0 link: 0
9224 14:47:31.458995 DRAM rank0 size:0x100000000,
9225 14:47:31.462306 DRAM rank1 size=0x100000000
9226 14:47:31.464394 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9227 14:47:31.468669 CPU: 00 missing read_resources
9228 14:47:31.471851 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9229 14:47:31.478765 Root Device read_resources bus 0 link: 0 done
9230 14:47:31.479315 Done reading resources.
9231 14:47:31.485135 Show resources in subtree (Root Device)...After reading.
9232 14:47:31.488015 Root Device child on link 0 CPU_CLUSTER: 0
9233 14:47:31.491757 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 14:47:31.501535 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 14:47:31.502069 CPU: 00
9236 14:47:31.504739 Root Device assign_resources, bus 0 link: 0
9237 14:47:31.508136 CPU_CLUSTER: 0 missing set_resources
9238 14:47:31.512396 Root Device assign_resources, bus 0 link: 0 done
9239 14:47:31.514539 Done setting resources.
9240 14:47:31.521607 Show resources in subtree (Root Device)...After assigning values.
9241 14:47:31.525092 Root Device child on link 0 CPU_CLUSTER: 0
9242 14:47:31.528518 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 14:47:31.538087 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 14:47:31.538663 CPU: 00
9245 14:47:31.541337 Done allocating resources.
9246 14:47:31.545139 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9247 14:47:31.547911 Enabling resources...
9248 14:47:31.548446 done.
9249 14:47:31.551398 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9250 14:47:31.555044 Initializing devices...
9251 14:47:31.558507 Root Device init
9252 14:47:31.559047 init hardware done!
9253 14:47:31.561215 0x00000018: ctrlr->caps
9254 14:47:31.561674 52.000 MHz: ctrlr->f_max
9255 14:47:31.565026 0.400 MHz: ctrlr->f_min
9256 14:47:31.568290 0x40ff8080: ctrlr->voltages
9257 14:47:31.568850 sclk: 390625
9258 14:47:31.572440 Bus Width = 1
9259 14:47:31.573033 sclk: 390625
9260 14:47:31.573427 Bus Width = 1
9261 14:47:31.574701 Early init status = 3
9262 14:47:31.577954 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9263 14:47:31.582966 in-header: 03 fc 00 00 01 00 00 00
9264 14:47:31.585804 in-data: 00
9265 14:47:31.588730 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9266 14:47:31.594199 in-header: 03 fd 00 00 00 00 00 00
9267 14:47:31.597681 in-data:
9268 14:47:31.601143 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9269 14:47:31.605101 in-header: 03 fc 00 00 01 00 00 00
9270 14:47:31.608338 in-data: 00
9271 14:47:31.611606 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9272 14:47:31.617361 in-header: 03 fd 00 00 00 00 00 00
9273 14:47:31.620938 in-data:
9274 14:47:31.624028 [SSUSB] Setting up USB HOST controller...
9275 14:47:31.627664 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9276 14:47:31.631333 [SSUSB] phy power-on done.
9277 14:47:31.634293 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9278 14:47:31.641153 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9279 14:47:31.644346 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9280 14:47:31.650565 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9281 14:47:31.657172 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9282 14:47:31.663760 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9283 14:47:31.670309 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9284 14:47:31.677574 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9285 14:47:31.680709 SPM: binary array size = 0x9dc
9286 14:47:31.683684 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9287 14:47:31.690397 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9288 14:47:31.697205 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9289 14:47:31.701085 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9290 14:47:31.706890 configure_display: Starting display init
9291 14:47:31.740727 anx7625_power_on_init: Init interface.
9292 14:47:31.743717 anx7625_disable_pd_protocol: Disabled PD feature.
9293 14:47:31.747510 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9294 14:47:31.776237 anx7625_start_dp_work: Secure OCM version=00
9295 14:47:31.778622 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9296 14:47:31.794050 sp_tx_get_edid_block: EDID Block = 1
9297 14:47:31.895365 Extracted contents:
9298 14:47:31.899137 header: 00 ff ff ff ff ff ff 00
9299 14:47:31.902552 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9300 14:47:31.905734 version: 01 04
9301 14:47:31.909511 basic params: 95 1f 11 78 0a
9302 14:47:31.912371 chroma info: 76 90 94 55 54 90 27 21 50 54
9303 14:47:31.916042 established: 00 00 00
9304 14:47:31.922567 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9305 14:47:31.925338 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9306 14:47:31.932476 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9307 14:47:31.938956 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9308 14:47:31.945431 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9309 14:47:31.948878 extensions: 00
9310 14:47:31.949360 checksum: fb
9311 14:47:31.949800
9312 14:47:31.952473 Manufacturer: IVO Model 57d Serial Number 0
9313 14:47:31.955367 Made week 0 of 2020
9314 14:47:31.955818 EDID version: 1.4
9315 14:47:31.958386 Digital display
9316 14:47:31.962250 6 bits per primary color channel
9317 14:47:31.962711 DisplayPort interface
9318 14:47:31.965830 Maximum image size: 31 cm x 17 cm
9319 14:47:31.968555 Gamma: 220%
9320 14:47:31.969129 Check DPMS levels
9321 14:47:31.972226 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9322 14:47:31.976080 First detailed timing is preferred timing
9323 14:47:31.979097 Established timings supported:
9324 14:47:31.982322 Standard timings supported:
9325 14:47:31.982773 Detailed timings
9326 14:47:31.988748 Hex of detail: 383680a07038204018303c0035ae10000019
9327 14:47:31.992649 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9328 14:47:31.999308 0780 0798 07c8 0820 hborder 0
9329 14:47:32.003079 0438 043b 0447 0458 vborder 0
9330 14:47:32.003567 -hsync -vsync
9331 14:47:32.005369 Did detailed timing
9332 14:47:32.009030 Hex of detail: 000000000000000000000000000000000000
9333 14:47:32.012646 Manufacturer-specified data, tag 0
9334 14:47:32.018327 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9335 14:47:32.018788 ASCII string: InfoVision
9336 14:47:32.025501 Hex of detail: 000000fe00523134304e574635205248200a
9337 14:47:32.029027 ASCII string: R140NWF5 RH
9338 14:47:32.029572 Checksum
9339 14:47:32.029935 Checksum: 0xfb (valid)
9340 14:47:32.035687 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9341 14:47:32.038810 DSI data_rate: 832800000 bps
9342 14:47:32.041864 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9343 14:47:32.045242 anx7625_parse_edid: pixelclock(138800).
9344 14:47:32.052292 hactive(1920), hsync(48), hfp(24), hbp(88)
9345 14:47:32.055690 vactive(1080), vsync(12), vfp(3), vbp(17)
9346 14:47:32.059126 anx7625_dsi_config: config dsi.
9347 14:47:32.065134 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9348 14:47:32.077682 anx7625_dsi_config: success to config DSI
9349 14:47:32.081277 anx7625_dp_start: MIPI phy setup OK.
9350 14:47:32.084653 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9351 14:47:32.087703 mtk_ddp_mode_set invalid vrefresh 60
9352 14:47:32.091204 main_disp_path_setup
9353 14:47:32.091656 ovl_layer_smi_id_en
9354 14:47:32.094400 ovl_layer_smi_id_en
9355 14:47:32.094959 ccorr_config
9356 14:47:32.095320 aal_config
9357 14:47:32.097834 gamma_config
9358 14:47:32.098394 postmask_config
9359 14:47:32.100748 dither_config
9360 14:47:32.104799 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9361 14:47:32.111026 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9362 14:47:32.114329 Root Device init finished in 554 msecs
9363 14:47:32.114968 CPU_CLUSTER: 0 init
9364 14:47:32.124923 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9365 14:47:32.128234 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9366 14:47:32.131307 APU_MBOX 0x190000b0 = 0x10001
9367 14:47:32.134558 APU_MBOX 0x190001b0 = 0x10001
9368 14:47:32.138402 APU_MBOX 0x190005b0 = 0x10001
9369 14:47:32.138971 APU_MBOX 0x190006b0 = 0x10001
9370 14:47:32.145004 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9371 14:47:32.156673 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9372 14:47:32.170507 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9373 14:47:32.175416 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9374 14:47:32.187525 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9375 14:47:32.197599 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9376 14:47:32.200121 CPU_CLUSTER: 0 init finished in 81 msecs
9377 14:47:32.203575 Devices initialized
9378 14:47:32.206817 Show all devs... After init.
9379 14:47:32.207403 Root Device: enabled 1
9380 14:47:32.210495 CPU_CLUSTER: 0: enabled 1
9381 14:47:32.213179 CPU: 00: enabled 1
9382 14:47:32.217537 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9383 14:47:32.219550 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9384 14:47:32.222932 ELOG: NV offset 0x57f000 size 0x1000
9385 14:47:32.229487 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9386 14:47:32.236278 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9387 14:47:32.239729 ELOG: Event(17) added with size 13 at 2024-06-04 14:47:32 UTC
9388 14:47:32.242707 out: cmd=0x121: 03 db 21 01 00 00 00 00
9389 14:47:32.247475 in-header: 03 c1 00 00 2c 00 00 00
9390 14:47:32.261399 in-data: 9e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 14:47:32.266956 ELOG: Event(A1) added with size 10 at 2024-06-04 14:47:32 UTC
9392 14:47:32.273911 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9393 14:47:32.280900 ELOG: Event(A0) added with size 9 at 2024-06-04 14:47:32 UTC
9394 14:47:32.283309 elog_add_boot_reason: Logged dev mode boot
9395 14:47:32.286421 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9396 14:47:32.290797 Finalize devices...
9397 14:47:32.291341 Devices finalized
9398 14:47:32.296919 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9399 14:47:32.300427 Writing coreboot table at 0xffe64000
9400 14:47:32.303685 0. 000000000010a000-0000000000113fff: RAMSTAGE
9401 14:47:32.306955 1. 0000000040000000-00000000400fffff: RAM
9402 14:47:32.313912 2. 0000000040100000-000000004032afff: RAMSTAGE
9403 14:47:32.316804 3. 000000004032b000-00000000545fffff: RAM
9404 14:47:32.320640 4. 0000000054600000-000000005465ffff: BL31
9405 14:47:32.323310 5. 0000000054660000-00000000ffe63fff: RAM
9406 14:47:32.330407 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9407 14:47:32.333223 7. 0000000100000000-000000023fffffff: RAM
9408 14:47:32.333679 Passing 5 GPIOs to payload:
9409 14:47:32.341093 NAME | PORT | POLARITY | VALUE
9410 14:47:32.343404 EC in RW | 0x000000aa | low | undefined
9411 14:47:32.350208 EC interrupt | 0x00000005 | low | undefined
9412 14:47:32.353577 TPM interrupt | 0x000000ab | high | undefined
9413 14:47:32.356467 SD card detect | 0x00000011 | high | undefined
9414 14:47:32.363418 speaker enable | 0x00000093 | high | undefined
9415 14:47:32.366863 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9416 14:47:32.370100 in-header: 03 f9 00 00 02 00 00 00
9417 14:47:32.370556 in-data: 02 00
9418 14:47:32.373308 ADC[4]: Raw value=900959 ID=7
9419 14:47:32.376693 ADC[3]: Raw value=213336 ID=1
9420 14:47:32.377206 RAM Code: 0x71
9421 14:47:32.380252 ADC[6]: Raw value=74926 ID=0
9422 14:47:32.383542 ADC[5]: Raw value=212598 ID=1
9423 14:47:32.383990 SKU Code: 0x1
9424 14:47:32.390045 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cb8c
9425 14:47:32.393755 coreboot table: 964 bytes.
9426 14:47:32.397130 IMD ROOT 0. 0xfffff000 0x00001000
9427 14:47:32.400145 IMD SMALL 1. 0xffffe000 0x00001000
9428 14:47:32.403286 RO MCACHE 2. 0xffffc000 0x00001104
9429 14:47:32.406917 CONSOLE 3. 0xfff7c000 0x00080000
9430 14:47:32.410876 FMAP 4. 0xfff7b000 0x00000452
9431 14:47:32.413388 TIME STAMP 5. 0xfff7a000 0x00000910
9432 14:47:32.416349 VBOOT WORK 6. 0xfff66000 0x00014000
9433 14:47:32.419952 RAMOOPS 7. 0xffe66000 0x00100000
9434 14:47:32.423541 COREBOOT 8. 0xffe64000 0x00002000
9435 14:47:32.424024 IMD small region:
9436 14:47:32.427989 IMD ROOT 0. 0xffffec00 0x00000400
9437 14:47:32.430761 VPD 1. 0xffffeb80 0x0000006c
9438 14:47:32.433485 MMC STATUS 2. 0xffffeb60 0x00000004
9439 14:47:32.440305 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9440 14:47:32.440713 Probing TPM: done!
9441 14:47:32.446688 Connected to device vid:did:rid of 1ae0:0028:00
9442 14:47:32.453443 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9443 14:47:32.457275 Initialized TPM device CR50 revision 0
9444 14:47:32.460671 Checking cr50 for pending updates
9445 14:47:32.466775 Reading cr50 TPM mode
9446 14:47:32.475455 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9447 14:47:32.481759 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9448 14:47:32.521945 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9449 14:47:32.525714 Checking segment from ROM address 0x40100000
9450 14:47:32.528492 Checking segment from ROM address 0x4010001c
9451 14:47:32.535056 Loading segment from ROM address 0x40100000
9452 14:47:32.535591 code (compression=0)
9453 14:47:32.541899 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9454 14:47:32.551909 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9455 14:47:32.552364 it's not compressed!
9456 14:47:32.558458 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9457 14:47:32.562131 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9458 14:47:32.582887 Loading segment from ROM address 0x4010001c
9459 14:47:32.583422 Entry Point 0x80000000
9460 14:47:32.585404 Loaded segments
9461 14:47:32.589856 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9462 14:47:32.595585 Jumping to boot code at 0x80000000(0xffe64000)
9463 14:47:32.602578 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9464 14:47:32.609576 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9465 14:47:32.616655 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9466 14:47:32.620289 Checking segment from ROM address 0x40100000
9467 14:47:32.623211 Checking segment from ROM address 0x4010001c
9468 14:47:32.630074 Loading segment from ROM address 0x40100000
9469 14:47:32.630489 code (compression=1)
9470 14:47:32.637287 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9471 14:47:32.646738 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9472 14:47:32.647153 using LZMA
9473 14:47:32.655184 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9474 14:47:32.662470 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9475 14:47:32.665750 Loading segment from ROM address 0x4010001c
9476 14:47:32.666245 Entry Point 0x54601000
9477 14:47:32.668441 Loaded segments
9478 14:47:32.671690 NOTICE: MT8192 bl31_setup
9479 14:47:32.678441 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9480 14:47:32.681978 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9481 14:47:32.685335 WARNING: region 0:
9482 14:47:32.689058 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 14:47:32.689466 WARNING: region 1:
9484 14:47:32.695588 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9485 14:47:32.698734 WARNING: region 2:
9486 14:47:32.702138 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9487 14:47:32.705181 WARNING: region 3:
9488 14:47:32.709199 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 14:47:32.712389 WARNING: region 4:
9490 14:47:32.715826 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 14:47:32.719021 WARNING: region 5:
9492 14:47:32.722657 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 14:47:32.725488 WARNING: region 6:
9494 14:47:32.729404 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 14:47:32.729952 WARNING: region 7:
9496 14:47:32.735470 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 14:47:32.742627 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9498 14:47:32.745527 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9499 14:47:32.749112 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9500 14:47:32.752252 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9501 14:47:32.758984 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9502 14:47:32.762911 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9503 14:47:32.769683 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9504 14:47:32.773192 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9505 14:47:32.776423 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9506 14:47:32.783149 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9507 14:47:32.786113 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9508 14:47:32.789445 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9509 14:47:32.796087 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9510 14:47:32.799447 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9511 14:47:32.802835 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9512 14:47:32.809941 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9513 14:47:32.812595 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9514 14:47:32.819957 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9515 14:47:32.822760 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9516 14:47:32.826938 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9517 14:47:32.833192 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9518 14:47:32.836474 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9519 14:47:32.839994 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9520 14:47:32.846607 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9521 14:47:32.850524 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9522 14:47:32.856764 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9523 14:47:32.860471 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9524 14:47:32.863101 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9525 14:47:32.869690 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9526 14:47:32.873489 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9527 14:47:32.880007 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9528 14:47:32.883097 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9529 14:47:32.886899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9530 14:47:32.889784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9531 14:47:32.896586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9532 14:47:32.900322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9533 14:47:32.903997 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9534 14:47:32.906833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9535 14:47:32.913406 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9536 14:47:32.917378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9537 14:47:32.920430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9538 14:47:32.923349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9539 14:47:32.927178 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9540 14:47:32.933728 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9541 14:47:32.937480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9542 14:47:32.940766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9543 14:47:32.946911 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9544 14:47:32.950869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9545 14:47:32.953788 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9546 14:47:32.960808 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9547 14:47:32.964040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9548 14:47:32.967749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9549 14:47:32.973683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9550 14:47:32.977893 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9551 14:47:32.983978 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9552 14:47:32.987345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9553 14:47:32.990470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9554 14:47:32.997992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9555 14:47:33.001380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9556 14:47:33.007516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9557 14:47:33.011231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9558 14:47:33.017227 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9559 14:47:33.020956 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9560 14:47:33.027635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9561 14:47:33.031149 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9562 14:47:33.034255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9563 14:47:33.041165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9564 14:47:33.044413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9565 14:47:33.051519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9566 14:47:33.054659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9567 14:47:33.057996 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9568 14:47:33.064913 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9569 14:47:33.068189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9570 14:47:33.074622 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9571 14:47:33.078273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9572 14:47:33.081477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9573 14:47:33.088264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9574 14:47:33.091707 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9575 14:47:33.098560 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9576 14:47:33.101339 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9577 14:47:33.108031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9578 14:47:33.111718 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9579 14:47:33.115110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9580 14:47:33.121621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9581 14:47:33.125341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9582 14:47:33.132168 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9583 14:47:33.135177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9584 14:47:33.141525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9585 14:47:33.145250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9586 14:47:33.148466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9587 14:47:33.155471 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9588 14:47:33.159212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9589 14:47:33.165135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9590 14:47:33.168296 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9591 14:47:33.175104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9592 14:47:33.178546 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9593 14:47:33.181715 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9594 14:47:33.185101 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9595 14:47:33.191621 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9596 14:47:33.195654 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9597 14:47:33.199735 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9598 14:47:33.205345 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9599 14:47:33.208629 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9600 14:47:33.211948 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9601 14:47:33.219072 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9602 14:47:33.222406 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9603 14:47:33.229212 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9604 14:47:33.232642 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9605 14:47:33.235698 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9606 14:47:33.242293 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9607 14:47:33.245693 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9608 14:47:33.249789 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9609 14:47:33.255529 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9610 14:47:33.259678 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9611 14:47:33.265878 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9612 14:47:33.269723 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9613 14:47:33.272035 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9614 14:47:33.279086 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9615 14:47:33.282395 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9616 14:47:33.286047 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9617 14:47:33.289096 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9618 14:47:33.295922 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9619 14:47:33.300768 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9620 14:47:33.302529 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9621 14:47:33.306016 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9622 14:47:33.312950 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9623 14:47:33.316091 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9624 14:47:33.322756 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9625 14:47:33.326425 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9626 14:47:33.330294 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9627 14:47:33.336429 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9628 14:47:33.339572 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9629 14:47:33.343765 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9630 14:47:33.349716 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9631 14:47:33.352774 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9632 14:47:33.359766 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9633 14:47:33.363239 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9634 14:47:33.366482 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9635 14:47:33.373094 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9636 14:47:33.376019 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9637 14:47:33.379586 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9638 14:47:33.386394 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9639 14:47:33.389820 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9640 14:47:33.396443 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9641 14:47:33.399705 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9642 14:47:33.403240 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9643 14:47:33.409556 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9644 14:47:33.413384 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9645 14:47:33.416305 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9646 14:47:33.423131 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9647 14:47:33.426902 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9648 14:47:33.433855 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9649 14:47:33.436772 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9650 14:47:33.441533 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9651 14:47:33.447348 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9652 14:47:33.450440 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9653 14:47:33.456731 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9654 14:47:33.460860 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9655 14:47:33.463756 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9656 14:47:33.470463 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9657 14:47:33.473679 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9658 14:47:33.477064 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9659 14:47:33.483669 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9660 14:47:33.487641 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9661 14:47:33.494136 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9662 14:47:33.496817 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9663 14:47:33.500393 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9664 14:47:33.507769 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9665 14:47:33.510436 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9666 14:47:33.517008 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9667 14:47:33.520366 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9668 14:47:33.523994 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9669 14:47:33.530744 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9670 14:47:33.533994 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9671 14:47:33.537348 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9672 14:47:33.543788 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9673 14:47:33.547801 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9674 14:47:33.553857 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9675 14:47:33.556893 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9676 14:47:33.560333 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9677 14:47:33.567415 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9678 14:47:33.570124 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9679 14:47:33.573737 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9680 14:47:33.580233 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9681 14:47:33.583924 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9682 14:47:33.590343 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9683 14:47:33.593491 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9684 14:47:33.596880 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9685 14:47:33.603785 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9686 14:47:33.606970 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9687 14:47:33.613358 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9688 14:47:33.617162 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9689 14:47:33.623859 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9690 14:47:33.627170 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9691 14:47:33.630033 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9692 14:47:33.637395 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9693 14:47:33.640605 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9694 14:47:33.644045 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9695 14:47:33.650809 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9696 14:47:33.654193 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9697 14:47:33.660809 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9698 14:47:33.663879 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9699 14:47:33.667608 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9700 14:47:33.674295 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9701 14:47:33.677608 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9702 14:47:33.684534 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9703 14:47:33.687576 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9704 14:47:33.694141 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9705 14:47:33.697754 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9706 14:47:33.701349 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9707 14:47:33.707335 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9708 14:47:33.710771 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9709 14:47:33.717404 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9710 14:47:33.720477 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9711 14:47:33.723779 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9712 14:47:33.730759 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9713 14:47:33.734402 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9714 14:47:33.740459 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9715 14:47:33.744480 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9716 14:47:33.750353 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9717 14:47:33.753823 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9718 14:47:33.758765 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9719 14:47:33.763636 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9720 14:47:33.767233 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9721 14:47:33.773839 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9722 14:47:33.777304 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9723 14:47:33.780353 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9724 14:47:33.787110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9725 14:47:33.790493 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9726 14:47:33.793624 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9727 14:47:33.800487 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9728 14:47:33.803723 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9729 14:47:33.808246 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9730 14:47:33.810596 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9731 14:47:33.817146 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9732 14:47:33.820427 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9733 14:47:33.824492 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9734 14:47:33.830722 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9735 14:47:33.834247 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9736 14:47:33.837506 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9737 14:47:33.844267 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9738 14:47:33.847798 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9739 14:47:33.853685 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9740 14:47:33.858095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9741 14:47:33.860669 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9742 14:47:33.867516 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9743 14:47:33.870802 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9744 14:47:33.874429 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9745 14:47:33.880337 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9746 14:47:33.884174 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9747 14:47:33.887235 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9748 14:47:33.894071 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9749 14:47:33.897451 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9750 14:47:33.900581 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9751 14:47:33.907369 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9752 14:47:33.910578 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9753 14:47:33.917250 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9754 14:47:33.920732 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9755 14:47:33.924240 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9756 14:47:33.930568 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9757 14:47:33.934125 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9758 14:47:33.937174 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9759 14:47:33.943981 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9760 14:47:33.947774 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9761 14:47:33.950743 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9762 14:47:33.957793 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9763 14:47:33.960469 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9764 14:47:33.967500 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9765 14:47:33.970382 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9766 14:47:33.974130 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9767 14:47:33.977808 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9768 14:47:33.980834 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9769 14:47:33.986838 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9770 14:47:33.990733 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9771 14:47:33.994190 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9772 14:47:33.997984 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9773 14:47:34.004516 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9774 14:47:34.007363 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9775 14:47:34.010466 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9776 14:47:34.013924 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9777 14:47:34.020482 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9778 14:47:34.023554 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9779 14:47:34.027330 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9780 14:47:34.033810 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9781 14:47:34.037137 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9782 14:47:34.044500 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9783 14:47:34.048488 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9784 14:47:34.053563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9785 14:47:34.057908 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9786 14:47:34.060682 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9787 14:47:34.067430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9788 14:47:34.070247 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9789 14:47:34.073583 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9790 14:47:34.080560 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9791 14:47:34.084014 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9792 14:47:34.090596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9793 14:47:34.094222 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9794 14:47:34.097506 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9795 14:47:34.103563 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9796 14:47:34.106897 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9797 14:47:34.113595 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9798 14:47:34.117019 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9799 14:47:34.123873 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9800 14:47:34.127275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9801 14:47:34.130252 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9802 14:47:34.136845 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9803 14:47:34.141037 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9804 14:47:34.144039 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9805 14:47:34.150736 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9806 14:47:34.153709 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9807 14:47:34.161230 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9808 14:47:34.164310 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9809 14:47:34.170288 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9810 14:47:34.173532 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9811 14:47:34.176888 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9812 14:47:34.183907 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9813 14:47:34.187338 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9814 14:47:34.193896 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9815 14:47:34.196841 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9816 14:47:34.200892 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9817 14:47:34.208897 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9818 14:47:34.211471 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9819 14:47:34.217143 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9820 14:47:34.220462 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9821 14:47:34.223890 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9822 14:47:34.230238 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9823 14:47:34.234092 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9824 14:47:34.240084 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9825 14:47:34.244035 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9826 14:47:34.247156 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9827 14:47:34.253796 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9828 14:47:34.257528 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9829 14:47:34.263757 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9830 14:47:34.267278 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9831 14:47:34.270083 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9832 14:47:34.277019 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9833 14:47:34.280430 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9834 14:47:34.287360 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9835 14:47:34.290425 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9836 14:47:34.293910 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9837 14:47:34.300377 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9838 14:47:34.304023 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9839 14:47:34.310923 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9840 14:47:34.313714 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9841 14:47:34.320327 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9842 14:47:34.323757 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9843 14:47:34.326911 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9844 14:47:34.333672 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9845 14:47:34.337197 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9846 14:47:34.340494 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9847 14:47:34.347122 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9848 14:47:34.350612 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9849 14:47:34.357291 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9850 14:47:34.360538 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9851 14:47:34.363674 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9852 14:47:34.370807 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9853 14:47:34.373920 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9854 14:47:34.380258 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9855 14:47:34.384095 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9856 14:47:34.390559 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9857 14:47:34.394236 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9858 14:47:34.397107 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9859 14:47:34.404120 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9860 14:47:34.407296 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9861 14:47:34.413838 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9862 14:47:34.416852 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9863 14:47:34.423457 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9864 14:47:34.426898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9865 14:47:34.430340 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9866 14:47:34.437252 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9867 14:47:34.440800 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9868 14:47:34.447431 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9869 14:47:34.450628 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9870 14:47:34.457322 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9871 14:47:34.460777 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9872 14:47:34.463917 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9873 14:47:34.471726 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9874 14:47:34.473787 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9875 14:47:34.480655 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9876 14:47:34.484010 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9877 14:47:34.490477 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9878 14:47:34.494548 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9879 14:47:34.497570 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9880 14:47:34.504302 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9881 14:47:34.508015 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9882 14:47:34.513970 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9883 14:47:34.517466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9884 14:47:34.523903 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9885 14:47:34.527576 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9886 14:47:34.530869 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9887 14:47:34.537741 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9888 14:47:34.541188 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9889 14:47:34.547470 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9890 14:47:34.551290 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9891 14:47:34.554187 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9892 14:47:34.561357 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9893 14:47:34.564191 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9894 14:47:34.570732 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9895 14:47:34.574755 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9896 14:47:34.581077 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9897 14:47:34.584428 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9898 14:47:34.587815 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9899 14:47:34.594218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9900 14:47:34.597804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9901 14:47:34.604019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9902 14:47:34.607692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9903 14:47:34.614290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9904 14:47:34.617726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9905 14:47:34.620913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9906 14:47:34.627749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9907 14:47:34.631257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9908 14:47:34.637670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9909 14:47:34.641079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9910 14:47:34.647821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9911 14:47:34.651388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9912 14:47:34.658129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9913 14:47:34.660789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9914 14:47:34.667473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9915 14:47:34.670880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9916 14:47:34.677700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9917 14:47:34.680938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9918 14:47:34.687893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9919 14:47:34.691230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9920 14:47:34.697778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9921 14:47:34.701123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9922 14:47:34.708656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9923 14:47:34.711266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9924 14:47:34.719161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9925 14:47:34.721330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9926 14:47:34.728167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9927 14:47:34.730920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9928 14:47:34.737897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9929 14:47:34.741364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9930 14:47:34.748084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9931 14:47:34.751329 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9932 14:47:34.751875 INFO: [APUAPC] vio 0
9933 14:47:34.758532 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9934 14:47:34.762555 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9935 14:47:34.766064 INFO: [APUAPC] D0_APC_0: 0x400510
9936 14:47:34.768794 INFO: [APUAPC] D0_APC_1: 0x0
9937 14:47:34.772506 INFO: [APUAPC] D0_APC_2: 0x1540
9938 14:47:34.775396 INFO: [APUAPC] D0_APC_3: 0x0
9939 14:47:34.778437 INFO: [APUAPC] D1_APC_0: 0xffffffff
9940 14:47:34.781591 INFO: [APUAPC] D1_APC_1: 0xffffffff
9941 14:47:34.786621 INFO: [APUAPC] D1_APC_2: 0x3fffff
9942 14:47:34.788600 INFO: [APUAPC] D1_APC_3: 0x0
9943 14:47:34.792918 INFO: [APUAPC] D2_APC_0: 0xffffffff
9944 14:47:34.795929 INFO: [APUAPC] D2_APC_1: 0xffffffff
9945 14:47:34.799033 INFO: [APUAPC] D2_APC_2: 0x3fffff
9946 14:47:34.802350 INFO: [APUAPC] D2_APC_3: 0x0
9947 14:47:34.805351 INFO: [APUAPC] D3_APC_0: 0xffffffff
9948 14:47:34.808916 INFO: [APUAPC] D3_APC_1: 0xffffffff
9949 14:47:34.811818 INFO: [APUAPC] D3_APC_2: 0x3fffff
9950 14:47:34.812423 INFO: [APUAPC] D3_APC_3: 0x0
9951 14:47:34.815255 INFO: [APUAPC] D4_APC_0: 0xffffffff
9952 14:47:34.822035 INFO: [APUAPC] D4_APC_1: 0xffffffff
9953 14:47:34.822464 INFO: [APUAPC] D4_APC_2: 0x3fffff
9954 14:47:34.825400 INFO: [APUAPC] D4_APC_3: 0x0
9955 14:47:34.829202 INFO: [APUAPC] D5_APC_0: 0xffffffff
9956 14:47:34.833026 INFO: [APUAPC] D5_APC_1: 0xffffffff
9957 14:47:34.835633 INFO: [APUAPC] D5_APC_2: 0x3fffff
9958 14:47:34.838651 INFO: [APUAPC] D5_APC_3: 0x0
9959 14:47:34.841638 INFO: [APUAPC] D6_APC_0: 0xffffffff
9960 14:47:34.845662 INFO: [APUAPC] D6_APC_1: 0xffffffff
9961 14:47:34.849304 INFO: [APUAPC] D6_APC_2: 0x3fffff
9962 14:47:34.851679 INFO: [APUAPC] D6_APC_3: 0x0
9963 14:47:34.855814 INFO: [APUAPC] D7_APC_0: 0xffffffff
9964 14:47:34.859470 INFO: [APUAPC] D7_APC_1: 0xffffffff
9965 14:47:34.862271 INFO: [APUAPC] D7_APC_2: 0x3fffff
9966 14:47:34.865207 INFO: [APUAPC] D7_APC_3: 0x0
9967 14:47:34.868853 INFO: [APUAPC] D8_APC_0: 0xffffffff
9968 14:47:34.872269 INFO: [APUAPC] D8_APC_1: 0xffffffff
9969 14:47:34.875228 INFO: [APUAPC] D8_APC_2: 0x3fffff
9970 14:47:34.878199 INFO: [APUAPC] D8_APC_3: 0x0
9971 14:47:34.881702 INFO: [APUAPC] D9_APC_0: 0xffffffff
9972 14:47:34.885908 INFO: [APUAPC] D9_APC_1: 0xffffffff
9973 14:47:34.888797 INFO: [APUAPC] D9_APC_2: 0x3fffff
9974 14:47:34.892020 INFO: [APUAPC] D9_APC_3: 0x0
9975 14:47:34.895568 INFO: [APUAPC] D10_APC_0: 0xffffffff
9976 14:47:34.898794 INFO: [APUAPC] D10_APC_1: 0xffffffff
9977 14:47:34.903070 INFO: [APUAPC] D10_APC_2: 0x3fffff
9978 14:47:34.905473 INFO: [APUAPC] D10_APC_3: 0x0
9979 14:47:34.908582 INFO: [APUAPC] D11_APC_0: 0xffffffff
9980 14:47:34.911887 INFO: [APUAPC] D11_APC_1: 0xffffffff
9981 14:47:34.914714 INFO: [APUAPC] D11_APC_2: 0x3fffff
9982 14:47:34.919094 INFO: [APUAPC] D11_APC_3: 0x0
9983 14:47:34.921607 INFO: [APUAPC] D12_APC_0: 0xffffffff
9984 14:47:34.925252 INFO: [APUAPC] D12_APC_1: 0xffffffff
9985 14:47:34.928780 INFO: [APUAPC] D12_APC_2: 0x3fffff
9986 14:47:34.931439 INFO: [APUAPC] D12_APC_3: 0x0
9987 14:47:34.934972 INFO: [APUAPC] D13_APC_0: 0xffffffff
9988 14:47:34.938019 INFO: [APUAPC] D13_APC_1: 0xffffffff
9989 14:47:34.941749 INFO: [APUAPC] D13_APC_2: 0x3fffff
9990 14:47:34.945191 INFO: [APUAPC] D13_APC_3: 0x0
9991 14:47:34.948357 INFO: [APUAPC] D14_APC_0: 0xffffffff
9992 14:47:34.951767 INFO: [APUAPC] D14_APC_1: 0xffffffff
9993 14:47:34.954908 INFO: [APUAPC] D14_APC_2: 0x3fffff
9994 14:47:34.958528 INFO: [APUAPC] D14_APC_3: 0x0
9995 14:47:34.961732 INFO: [APUAPC] D15_APC_0: 0xffffffff
9996 14:47:34.964829 INFO: [APUAPC] D15_APC_1: 0xffffffff
9997 14:47:34.968483 INFO: [APUAPC] D15_APC_2: 0x3fffff
9998 14:47:34.971875 INFO: [APUAPC] D15_APC_3: 0x0
9999 14:47:34.975519 INFO: [APUAPC] APC_CON: 0x4
10000 14:47:34.978272 INFO: [NOCDAPC] D0_APC_0: 0x0
10001 14:47:34.982092 INFO: [NOCDAPC] D0_APC_1: 0x0
10002 14:47:34.982505 INFO: [NOCDAPC] D1_APC_0: 0x0
10003 14:47:34.985422 INFO: [NOCDAPC] D1_APC_1: 0xfff
10004 14:47:34.988141 INFO: [NOCDAPC] D2_APC_0: 0x0
10005 14:47:34.991819 INFO: [NOCDAPC] D2_APC_1: 0xfff
10006 14:47:34.995079 INFO: [NOCDAPC] D3_APC_0: 0x0
10007 14:47:34.998559 INFO: [NOCDAPC] D3_APC_1: 0xfff
10008 14:47:35.001848 INFO: [NOCDAPC] D4_APC_0: 0x0
10009 14:47:35.005119 INFO: [NOCDAPC] D4_APC_1: 0xfff
10010 14:47:35.009019 INFO: [NOCDAPC] D5_APC_0: 0x0
10011 14:47:35.011859 INFO: [NOCDAPC] D5_APC_1: 0xfff
10012 14:47:35.012456 INFO: [NOCDAPC] D6_APC_0: 0x0
10013 14:47:35.014980 INFO: [NOCDAPC] D6_APC_1: 0xfff
10014 14:47:35.018597 INFO: [NOCDAPC] D7_APC_0: 0x0
10015 14:47:35.021651 INFO: [NOCDAPC] D7_APC_1: 0xfff
10016 14:47:35.025009 INFO: [NOCDAPC] D8_APC_0: 0x0
10017 14:47:35.028507 INFO: [NOCDAPC] D8_APC_1: 0xfff
10018 14:47:35.031514 INFO: [NOCDAPC] D9_APC_0: 0x0
10019 14:47:35.035126 INFO: [NOCDAPC] D9_APC_1: 0xfff
10020 14:47:35.038662 INFO: [NOCDAPC] D10_APC_0: 0x0
10021 14:47:35.041818 INFO: [NOCDAPC] D10_APC_1: 0xfff
10022 14:47:35.044932 INFO: [NOCDAPC] D11_APC_0: 0x0
10023 14:47:35.048008 INFO: [NOCDAPC] D11_APC_1: 0xfff
10024 14:47:35.048558 INFO: [NOCDAPC] D12_APC_0: 0x0
10025 14:47:35.052270 INFO: [NOCDAPC] D12_APC_1: 0xfff
10026 14:47:35.055873 INFO: [NOCDAPC] D13_APC_0: 0x0
10027 14:47:35.058819 INFO: [NOCDAPC] D13_APC_1: 0xfff
10028 14:47:35.061258 INFO: [NOCDAPC] D14_APC_0: 0x0
10029 14:47:35.064954 INFO: [NOCDAPC] D14_APC_1: 0xfff
10030 14:47:35.068669 INFO: [NOCDAPC] D15_APC_0: 0x0
10031 14:47:35.071687 INFO: [NOCDAPC] D15_APC_1: 0xfff
10032 14:47:35.074833 INFO: [NOCDAPC] APC_CON: 0x4
10033 14:47:35.078476 INFO: [APUAPC] set_apusys_apc done
10034 14:47:35.081600 INFO: [DEVAPC] devapc_init done
10035 14:47:35.085314 INFO: GICv3 without legacy support detected.
10036 14:47:35.088124 INFO: ARM GICv3 driver initialized in EL3
10037 14:47:35.091835 INFO: Maximum SPI INTID supported: 639
10038 14:47:35.097983 INFO: BL31: Initializing runtime services
10039 14:47:35.101610 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10040 14:47:35.105339 INFO: SPM: enable CPC mode
10041 14:47:35.111686 INFO: mcdi ready for mcusys-off-idle and system suspend
10042 14:47:35.115518 INFO: BL31: Preparing for EL3 exit to normal world
10043 14:47:35.118140 INFO: Entry point address = 0x80000000
10044 14:47:35.121698 INFO: SPSR = 0x8
10045 14:47:35.126426
10046 14:47:35.126926
10047 14:47:35.127250
10048 14:47:35.130023 Starting depthcharge on Spherion...
10049 14:47:35.130484
10050 14:47:35.130822 Wipe memory regions:
10051 14:47:35.131126
10052 14:47:35.133845 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10053 14:47:35.134346 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10054 14:47:35.134749 Setting prompt string to ['asurada:']
10055 14:47:35.135141 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10056 14:47:35.135798 [0x00000040000000, 0x00000054600000)
10057 14:47:35.256022
10058 14:47:35.256572 [0x00000054660000, 0x00000080000000)
10059 14:47:35.515821
10060 14:47:35.516319 [0x000000821a7280, 0x000000ffe64000)
10061 14:47:36.260725
10062 14:47:36.261328 [0x00000100000000, 0x00000240000000)
10063 14:47:38.150758
10064 14:47:38.153803 Initializing XHCI USB controller at 0x11200000.
10065 14:47:39.191951
10066 14:47:39.194741 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10067 14:47:39.195203
10068 14:47:39.195565
10069 14:47:39.196344 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 14:47:39.297807 asurada: tftpboot 192.168.201.1 14167053/tftp-deploy-4rwsbx_p/kernel/image.itb 14167053/tftp-deploy-4rwsbx_p/kernel/cmdline
10072 14:47:39.298432 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 14:47:39.298867 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10074 14:47:39.304078 tftpboot 192.168.201.1 14167053/tftp-deploy-4rwsbx_p/kernel/image.ittp-deploy-4rwsbx_p/kernel/cmdline
10075 14:47:39.304715
10076 14:47:39.305140 Waiting for link
10077 14:47:39.464334
10078 14:47:39.464833 R8152: Initializing
10079 14:47:39.465246
10080 14:47:39.467469 Version 6 (ocp_data = 5c30)
10081 14:47:39.468002
10082 14:47:39.470804 R8152: Done initializing
10083 14:47:39.471350
10084 14:47:39.471716 Adding net device
10085 14:47:41.433328
10086 14:47:41.433933 done.
10087 14:47:41.434509
10088 14:47:41.434876 MAC: 00:24:32:30:78:52
10089 14:47:41.435214
10090 14:47:41.436446 Sending DHCP discover... done.
10091 14:47:41.436901
10092 14:47:41.439873 Waiting for reply... done.
10093 14:47:41.440562
10094 14:47:41.443595 Sending DHCP request... done.
10095 14:47:41.444053
10096 14:47:41.449042 Waiting for reply... done.
10097 14:47:41.449588
10098 14:47:41.449948 My ip is 192.168.201.14
10099 14:47:41.450283
10100 14:47:41.452088 The DHCP server ip is 192.168.201.1
10101 14:47:41.452547
10102 14:47:41.459470 TFTP server IP predefined by user: 192.168.201.1
10103 14:47:41.460014
10104 14:47:41.465327 Bootfile predefined by user: 14167053/tftp-deploy-4rwsbx_p/kernel/image.itb
10105 14:47:41.465879
10106 14:47:41.466324 Sending tftp read request... done.
10107 14:47:41.468373
10108 14:47:41.475563 Waiting for the transfer...
10109 14:47:41.476118
10110 14:47:42.178909 00000000 ################################################################
10111 14:47:42.179492
10112 14:47:42.892820 00080000 ################################################################
10113 14:47:42.893581
10114 14:47:43.573344 00100000 ################################################################
10115 14:47:43.573846
10116 14:47:44.265536 00180000 ################################################################
10117 14:47:44.266104
10118 14:47:44.978392 00200000 ################################################################
10119 14:47:44.978939
10120 14:47:45.680489 00280000 ################################################################
10121 14:47:45.680969
10122 14:47:46.381576 00300000 ################################################################
10123 14:47:46.382091
10124 14:47:47.079464 00380000 ################################################################
10125 14:47:47.079953
10126 14:47:47.789877 00400000 ################################################################
10127 14:47:47.790372
10128 14:47:48.496264 00480000 ################################################################
10129 14:47:48.496767
10130 14:47:49.193399 00500000 ################################################################
10131 14:47:49.193904
10132 14:47:49.905865 00580000 ################################################################
10133 14:47:49.906450
10134 14:47:50.606693 00600000 ################################################################
10135 14:47:50.607284
10136 14:47:51.292115 00680000 ################################################################
10137 14:47:51.292612
10138 14:47:51.933498 00700000 ################################################################
10139 14:47:51.934093
10140 14:47:52.621097 00780000 ################################################################
10141 14:47:52.621605
10142 14:47:53.301912 00800000 ################################################################
10143 14:47:53.302436
10144 14:47:53.999816 00880000 ################################################################
10145 14:47:54.000327
10146 14:47:54.699432 00900000 ################################################################
10147 14:47:54.699968
10148 14:47:55.413008 00980000 ################################################################
10149 14:47:55.413523
10150 14:47:56.090903 00a00000 ################################################################
10151 14:47:56.091411
10152 14:47:56.803371 00a80000 ################################################################
10153 14:47:56.803868
10154 14:47:57.500340 00b00000 ################################################################
10155 14:47:57.500907
10156 14:47:58.216265 00b80000 ################################################################
10157 14:47:58.216770
10158 14:47:58.930518 00c00000 ################################################################
10159 14:47:58.931017
10160 14:47:59.629817 00c80000 ################################################################
10161 14:47:59.630367
10162 14:48:00.330257 00d00000 ################################################################
10163 14:48:00.330786
10164 14:48:01.033425 00d80000 ################################################################
10165 14:48:01.033981
10166 14:48:01.734478 00e00000 ################################################################
10167 14:48:01.734981
10168 14:48:02.438945 00e80000 ################################################################
10169 14:48:02.439462
10170 14:48:03.134345 00f00000 ################################################################
10171 14:48:03.134917
10172 14:48:03.843285 00f80000 ################################################################
10173 14:48:03.843816
10174 14:48:04.527920 01000000 ################################################################
10175 14:48:04.528424
10176 14:48:05.219191 01080000 ################################################################
10177 14:48:05.219728
10178 14:48:05.929539 01100000 ################################################################
10179 14:48:05.930091
10180 14:48:06.640059 01180000 ################################################################
10181 14:48:06.640568
10182 14:48:07.345232 01200000 ################################################################
10183 14:48:07.345826
10184 14:48:08.068154 01280000 ################################################################
10185 14:48:08.068652
10186 14:48:08.767056 01300000 ################################################################
10187 14:48:08.767722
10188 14:48:09.449487 01380000 ################################################################
10189 14:48:09.449999
10190 14:48:10.134078 01400000 ################################################################
10191 14:48:10.134589
10192 14:48:10.859905 01480000 ################################################################
10193 14:48:10.860395
10194 14:48:11.578896 01500000 ################################################################
10195 14:48:11.579399
10196 14:48:12.302826 01580000 ################################################################
10197 14:48:12.303376
10198 14:48:13.019694 01600000 ################################################################
10199 14:48:13.020199
10200 14:48:13.746031 01680000 ################################################################
10201 14:48:13.746546
10202 14:48:14.463719 01700000 ################################################################
10203 14:48:14.464244
10204 14:48:15.171949 01780000 ################################################################
10205 14:48:15.172456
10206 14:48:15.883961 01800000 ################################################################
10207 14:48:15.884491
10208 14:48:16.602393 01880000 ################################################################
10209 14:48:16.602905
10210 14:48:17.328183 01900000 ################################################################
10211 14:48:17.328743
10212 14:48:18.043754 01980000 ################################################################
10213 14:48:18.044266
10214 14:48:18.733596 01a00000 ################################################################
10215 14:48:18.734272
10216 14:48:19.424729 01a80000 ################################################################
10217 14:48:19.425335
10218 14:48:20.124722 01b00000 ################################################################
10219 14:48:20.125311
10220 14:48:20.839088 01b80000 ################################################################
10221 14:48:20.839624
10222 14:48:21.526192 01c00000 ################################################################
10223 14:48:21.526707
10224 14:48:22.213303 01c80000 ################################################################
10225 14:48:22.213813
10226 14:48:22.910046 01d00000 ################################################################
10227 14:48:22.910717
10228 14:48:23.623986 01d80000 ################################################################
10229 14:48:23.624485
10230 14:48:24.308183 01e00000 ################################################################
10231 14:48:24.308694
10232 14:48:24.991992 01e80000 ################################################################
10233 14:48:24.992501
10234 14:48:25.699384 01f00000 ################################################################
10235 14:48:25.699898
10236 14:48:26.391374 01f80000 ################################################################
10237 14:48:26.391897
10238 14:48:27.107720 02000000 ################################################################
10239 14:48:27.108233
10240 14:48:27.819873 02080000 ################################################################
10241 14:48:27.820380
10242 14:48:28.526949 02100000 ################################################################
10243 14:48:28.527492
10244 14:48:29.235011 02180000 ################################################################
10245 14:48:29.235597
10246 14:48:29.956363 02200000 ################################################################
10247 14:48:29.956857
10248 14:48:30.679021 02280000 ################################################################
10249 14:48:30.679548
10250 14:48:31.385831 02300000 ################################################################
10251 14:48:31.386362
10252 14:48:32.092330 02380000 ################################################################
10253 14:48:32.092834
10254 14:48:32.798791 02400000 ################################################################
10255 14:48:32.799309
10256 14:48:33.524565 02480000 ################################################################
10257 14:48:33.525216
10258 14:48:34.239838 02500000 ################################################################
10259 14:48:34.240333
10260 14:48:34.953272 02580000 ################################################################
10261 14:48:34.953925
10262 14:48:35.677105 02600000 ################################################################
10263 14:48:35.677636
10264 14:48:36.381602 02680000 ################################################################
10265 14:48:36.382112
10266 14:48:37.078795 02700000 ################################################################
10267 14:48:37.079459
10268 14:48:37.765991 02780000 ################################################################
10269 14:48:37.766541
10270 14:48:38.476692 02800000 ################################################################
10271 14:48:38.477306
10272 14:48:39.184559 02880000 ################################################################
10273 14:48:39.185175
10274 14:48:39.898767 02900000 ################################################################
10275 14:48:39.899323
10276 14:48:40.582847 02980000 ################################################################
10277 14:48:40.583412
10278 14:48:41.260932 02a00000 ################################################################
10279 14:48:41.261483
10280 14:48:41.988014 02a80000 ################################################################
10281 14:48:41.988567
10282 14:48:42.714497 02b00000 ################################################################
10283 14:48:42.715007
10284 14:48:43.446646 02b80000 ################################################################
10285 14:48:43.447151
10286 14:48:44.171327 02c00000 ################################################################
10287 14:48:44.171887
10288 14:48:44.879502 02c80000 ################################################################
10289 14:48:44.880038
10290 14:48:45.589125 02d00000 ################################################################
10291 14:48:45.589629
10292 14:48:46.295111 02d80000 ################################################################
10293 14:48:46.295622
10294 14:48:47.022157 02e00000 ################################################################
10295 14:48:47.022857
10296 14:48:47.728329 02e80000 ################################################################
10297 14:48:47.728868
10298 14:48:48.436604 02f00000 ################################################################
10299 14:48:48.437235
10300 14:48:49.142448 02f80000 ################################################################
10301 14:48:49.142958
10302 14:48:49.858361 03000000 ################################################################
10303 14:48:49.858869
10304 14:48:50.574229 03080000 ################################################################
10305 14:48:50.574750
10306 14:48:51.277706 03100000 ################################################################
10307 14:48:51.278246
10308 14:48:51.980004 03180000 ################################################################
10309 14:48:51.980538
10310 14:48:52.697938 03200000 ################################################################
10311 14:48:52.698536
10312 14:48:53.426954 03280000 ################################################################
10313 14:48:53.427454
10314 14:48:54.158796 03300000 ################################################################
10315 14:48:54.159358
10316 14:48:54.612509 03380000 ####################################### done.
10317 14:48:54.613096
10318 14:48:54.616150 The bootfile was 54320466 bytes long.
10319 14:48:54.616601
10320 14:48:54.619571 Sending tftp read request... done.
10321 14:48:54.620051
10322 14:48:54.623342 Waiting for the transfer...
10323 14:48:54.623791
10324 14:48:54.624145 00000000 # done.
10325 14:48:54.624483
10326 14:48:54.629821 Command line loaded dynamically from TFTP file: 14167053/tftp-deploy-4rwsbx_p/kernel/cmdline
10327 14:48:54.630232
10328 14:48:54.643317 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10329 14:48:54.646744
10330 14:48:54.647241 Loading FIT.
10331 14:48:54.647578
10332 14:48:54.649798 Image ramdisk-1 has 41210554 bytes.
10333 14:48:54.650206
10334 14:48:54.653093 Image fdt-1 has 47258 bytes.
10335 14:48:54.653502
10336 14:48:54.653826 Image kernel-1 has 13060619 bytes.
10337 14:48:54.657430
10338 14:48:54.663968 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10339 14:48:54.664481
10340 14:48:54.679809 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10341 14:48:54.680241
10342 14:48:54.686788 Choosing best match conf-1 for compat google,spherion-rev2.
10343 14:48:54.690880
10344 14:48:54.695627 Connected to device vid:did:rid of 1ae0:0028:00
10345 14:48:54.704391
10346 14:48:54.707303 tpm_get_response: command 0x17b, return code 0x0
10347 14:48:54.707715
10348 14:48:54.710285 ec_init: CrosEC protocol v3 supported (256, 248)
10349 14:48:54.715725
10350 14:48:54.718913 tpm_cleanup: add release locality here.
10351 14:48:54.719496
10352 14:48:54.719829 Shutting down all USB controllers.
10353 14:48:54.721732
10354 14:48:54.722139 Removing current net device
10355 14:48:54.722463
10356 14:48:54.728383 Exiting depthcharge with code 4 at timestamp: 109019339
10357 14:48:54.728785
10358 14:48:54.732145 LZMA decompressing kernel-1 to 0x821a6718
10359 14:48:54.732554
10360 14:48:54.735512 LZMA decompressing kernel-1 to 0x40000000
10361 14:48:56.347029
10362 14:48:56.347565 jumping to kernel
10363 14:48:56.349645 end: 2.2.4 bootloader-commands (duration 00:01:21) [common]
10364 14:48:56.350159 start: 2.2.5 auto-login-action (timeout 00:03:04) [common]
10365 14:48:56.350557 Setting prompt string to ['Linux version [0-9]']
10366 14:48:56.350927 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10367 14:48:56.351370 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10368 14:48:56.428885
10369 14:48:56.432111 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10370 14:48:56.436548 start: 2.2.5.1 login-action (timeout 00:03:04) [common]
10371 14:48:56.437187 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10372 14:48:56.437581 Setting prompt string to []
10373 14:48:56.438001 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10374 14:48:56.438478 Using line separator: #'\n'#
10375 14:48:56.438842 No login prompt set.
10376 14:48:56.439177 Parsing kernel messages
10377 14:48:56.439478 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10378 14:48:56.440061 [login-action] Waiting for messages, (timeout 00:03:04)
10379 14:48:56.440421 Waiting using forced prompt support (timeout 00:01:32)
10380 14:48:56.455675 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10381 14:48:56.459083 [ 0.000000] random: crng init done
10382 14:48:56.465993 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10383 14:48:56.468708 [ 0.000000] efi: UEFI not found.
10384 14:48:56.475690 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10385 14:48:56.482111 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10386 14:48:56.491864 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10387 14:48:56.501553 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10388 14:48:56.508325 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10389 14:48:56.515332 [ 0.000000] printk: bootconsole [mtk8250] enabled
10390 14:48:56.518537 [ 0.000000] NUMA: No NUMA configuration found
10391 14:48:56.529368 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10392 14:48:56.531545 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10393 14:48:56.534680 [ 0.000000] Zone ranges:
10394 14:48:56.541416 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10395 14:48:56.544621 [ 0.000000] DMA32 empty
10396 14:48:56.551405 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10397 14:48:56.554940 [ 0.000000] Movable zone start for each node
10398 14:48:56.558072 [ 0.000000] Early memory node ranges
10399 14:48:56.564740 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10400 14:48:56.571267 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10401 14:48:56.578773 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10402 14:48:56.581539 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10403 14:48:56.588372 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10404 14:48:56.594782 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10405 14:48:56.653547 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10406 14:48:56.660188 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10407 14:48:56.666994 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10408 14:48:56.670638 [ 0.000000] psci: probing for conduit method from DT.
10409 14:48:56.677014 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10410 14:48:56.680155 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10411 14:48:56.687049 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10412 14:48:56.689745 [ 0.000000] psci: SMC Calling Convention v1.2
10413 14:48:56.696672 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10414 14:48:56.700198 [ 0.000000] Detected VIPT I-cache on CPU0
10415 14:48:56.706547 [ 0.000000] CPU features: detected: GIC system register CPU interface
10416 14:48:56.713505 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10417 14:48:56.719813 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10418 14:48:56.726765 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10419 14:48:56.732900 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10420 14:48:56.739664 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10421 14:48:56.746112 [ 0.000000] alternatives: applying boot alternatives
10422 14:48:56.750056 [ 0.000000] Fallback order for Node 0: 0
10423 14:48:56.759977 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10424 14:48:56.760524 [ 0.000000] Policy zone: Normal
10425 14:48:56.776331 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10426 14:48:56.786353 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10427 14:48:56.797648 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10428 14:48:56.808155 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10429 14:48:56.814528 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10430 14:48:56.817751 <6>[ 0.000000] software IO TLB: area num 8.
10431 14:48:56.874099 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10432 14:48:57.024146 <6>[ 0.000000] Memory: 7923940K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 428828K reserved, 32768K cma-reserved)
10433 14:48:57.031079 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10434 14:48:57.037513 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10435 14:48:57.041482 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10436 14:48:57.047344 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10437 14:48:57.054103 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10438 14:48:57.057813 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10439 14:48:57.067341 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10440 14:48:57.074476 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10441 14:48:57.077476 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10442 14:48:57.085082 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10443 14:48:57.088510 <6>[ 0.000000] GICv3: 608 SPIs implemented
10444 14:48:57.095059 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10445 14:48:57.098524 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10446 14:48:57.102657 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10447 14:48:57.112297 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10448 14:48:57.122520 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10449 14:48:57.134775 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10450 14:48:57.141465 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10451 14:48:57.150579 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10452 14:48:57.164276 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10453 14:48:57.171333 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10454 14:48:57.177415 <6>[ 0.009179] Console: colour dummy device 80x25
10455 14:48:57.187481 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10456 14:48:57.190872 <6>[ 0.024347] pid_max: default: 32768 minimum: 301
10457 14:48:57.197715 <6>[ 0.029247] LSM: Security Framework initializing
10458 14:48:57.203729 <6>[ 0.034215] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10459 14:48:57.213779 <6>[ 0.042076] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10460 14:48:57.221216 <6>[ 0.051560] cblist_init_generic: Setting adjustable number of callback queues.
10461 14:48:57.227923 <6>[ 0.059004] cblist_init_generic: Setting shift to 3 and lim to 1.
10462 14:48:57.240438 <6>[ 0.065382] cblist_init_generic: Setting adjustable number of callback queues.
10463 14:48:57.241623 <6>[ 0.072809] cblist_init_generic: Setting shift to 3 and lim to 1.
10464 14:48:57.246935 <6>[ 0.079210] rcu: Hierarchical SRCU implementation.
10465 14:48:57.253859 <6>[ 0.084257] rcu: Max phase no-delay instances is 1000.
10466 14:48:57.257247 <6>[ 0.091314] EFI services will not be available.
10467 14:48:57.264353 <6>[ 0.096269] smp: Bringing up secondary CPUs ...
10468 14:48:57.271410 <6>[ 0.101315] Detected VIPT I-cache on CPU1
10469 14:48:57.278990 <6>[ 0.101386] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10470 14:48:57.285471 <6>[ 0.101416] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10471 14:48:57.288321 <6>[ 0.101752] Detected VIPT I-cache on CPU2
10472 14:48:57.295016 <6>[ 0.101800] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10473 14:48:57.301144 <6>[ 0.101816] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10474 14:48:57.308300 <6>[ 0.102077] Detected VIPT I-cache on CPU3
10475 14:48:57.314832 <6>[ 0.102124] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10476 14:48:57.321341 <6>[ 0.102138] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10477 14:48:57.324752 <6>[ 0.102442] CPU features: detected: Spectre-v4
10478 14:48:57.331215 <6>[ 0.102449] CPU features: detected: Spectre-BHB
10479 14:48:57.334818 <6>[ 0.102453] Detected PIPT I-cache on CPU4
10480 14:48:57.341035 <6>[ 0.102513] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10481 14:48:57.349792 <6>[ 0.102530] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10482 14:48:57.354336 <6>[ 0.102820] Detected PIPT I-cache on CPU5
10483 14:48:57.361294 <6>[ 0.102885] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10484 14:48:57.367772 <6>[ 0.102901] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10485 14:48:57.371168 <6>[ 0.103185] Detected PIPT I-cache on CPU6
10486 14:48:57.377803 <6>[ 0.103252] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10487 14:48:57.384702 <6>[ 0.103268] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10488 14:48:57.391080 <6>[ 0.103562] Detected PIPT I-cache on CPU7
10489 14:48:57.397862 <6>[ 0.103629] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10490 14:48:57.404579 <6>[ 0.103644] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10491 14:48:57.407959 <6>[ 0.103691] smp: Brought up 1 node, 8 CPUs
10492 14:48:57.415175 <6>[ 0.245115] SMP: Total of 8 processors activated.
10493 14:48:57.418109 <6>[ 0.250036] CPU features: detected: 32-bit EL0 Support
10494 14:48:57.428474 <6>[ 0.255399] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10495 14:48:57.434292 <6>[ 0.264199] CPU features: detected: Common not Private translations
10496 14:48:57.437677 <6>[ 0.270675] CPU features: detected: CRC32 instructions
10497 14:48:57.444282 <6>[ 0.276060] CPU features: detected: RCpc load-acquire (LDAPR)
10498 14:48:57.451182 <6>[ 0.282020] CPU features: detected: LSE atomic instructions
10499 14:48:57.457589 <6>[ 0.287802] CPU features: detected: Privileged Access Never
10500 14:48:57.461205 <6>[ 0.293617] CPU features: detected: RAS Extension Support
10501 14:48:57.467679 <6>[ 0.299226] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10502 14:48:57.474294 <6>[ 0.306452] CPU: All CPU(s) started at EL2
10503 14:48:57.481651 <6>[ 0.310795] alternatives: applying system-wide alternatives
10504 14:48:57.489567 <6>[ 0.321596] devtmpfs: initialized
10505 14:48:57.502839 <6>[ 0.330527] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10506 14:48:57.511999 <6>[ 0.340490] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10507 14:48:57.518430 <6>[ 0.348504] pinctrl core: initialized pinctrl subsystem
10508 14:48:57.521690 <6>[ 0.355301] DMI not present or invalid.
10509 14:48:57.528320 <6>[ 0.359714] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10510 14:48:57.538412 <6>[ 0.366572] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10511 14:48:57.545240 <6>[ 0.374163] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10512 14:48:57.554855 <6>[ 0.382383] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10513 14:48:57.558067 <6>[ 0.390624] audit: initializing netlink subsys (disabled)
10514 14:48:57.567853 <5>[ 0.396318] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10515 14:48:57.575130 <6>[ 0.397064] thermal_sys: Registered thermal governor 'step_wise'
10516 14:48:57.581892 <6>[ 0.404283] thermal_sys: Registered thermal governor 'power_allocator'
10517 14:48:57.585054 <6>[ 0.410535] cpuidle: using governor menu
10518 14:48:57.591410 <6>[ 0.421495] NET: Registered PF_QIPCRTR protocol family
10519 14:48:57.597937 <6>[ 0.426982] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10520 14:48:57.601861 <6>[ 0.434085] ASID allocator initialised with 32768 entries
10521 14:48:57.608678 <6>[ 0.440717] Serial: AMBA PL011 UART driver
10522 14:48:57.617570 <4>[ 0.449794] Trying to register duplicate clock ID: 134
10523 14:48:57.677974 <6>[ 0.513451] KASLR enabled
10524 14:48:57.693144 <6>[ 0.521322] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10525 14:48:57.700242 <6>[ 0.528334] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10526 14:48:57.706195 <6>[ 0.534823] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10527 14:48:57.712563 <6>[ 0.541829] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10528 14:48:57.718732 <6>[ 0.548315] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10529 14:48:57.725661 <6>[ 0.555321] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10530 14:48:57.732356 <6>[ 0.561810] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10531 14:48:57.738786 <6>[ 0.568817] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10532 14:48:57.742626 <6>[ 0.576286] ACPI: Interpreter disabled.
10533 14:48:57.750992 <6>[ 0.582789] iommu: Default domain type: Translated
10534 14:48:57.757536 <6>[ 0.587937] iommu: DMA domain TLB invalidation policy: strict mode
10535 14:48:57.760577 <5>[ 0.594601] SCSI subsystem initialized
10536 14:48:57.767156 <6>[ 0.598854] usbcore: registered new interface driver usbfs
10537 14:48:57.774017 <6>[ 0.604588] usbcore: registered new interface driver hub
10538 14:48:57.776954 <6>[ 0.610141] usbcore: registered new device driver usb
10539 14:48:57.784297 <6>[ 0.616299] pps_core: LinuxPPS API ver. 1 registered
10540 14:48:57.794840 <6>[ 0.621490] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10541 14:48:57.797910 <6>[ 0.630829] PTP clock support registered
10542 14:48:57.800551 <6>[ 0.635070] EDAC MC: Ver: 3.0.0
10543 14:48:57.807802 <6>[ 0.640298] FPGA manager framework
10544 14:48:57.811624 <6>[ 0.643972] Advanced Linux Sound Architecture Driver Initialized.
10545 14:48:57.815556 <6>[ 0.650751] vgaarb: loaded
10546 14:48:57.822351 <6>[ 0.653904] clocksource: Switched to clocksource arch_sys_counter
10547 14:48:57.828679 <5>[ 0.660352] VFS: Disk quotas dquot_6.6.0
10548 14:48:57.835771 <6>[ 0.664540] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10549 14:48:57.839376 <6>[ 0.671727] pnp: PnP ACPI: disabled
10550 14:48:57.846396 <6>[ 0.678422] NET: Registered PF_INET protocol family
10551 14:48:57.853033 <6>[ 0.684028] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10552 14:48:57.867605 <6>[ 0.696386] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10553 14:48:57.877411 <6>[ 0.705198] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10554 14:48:57.884070 <6>[ 0.713170] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10555 14:48:57.890810 <6>[ 0.721869] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10556 14:48:57.902658 <6>[ 0.731607] TCP: Hash tables configured (established 65536 bind 65536)
10557 14:48:57.910551 <6>[ 0.738470] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10558 14:48:57.916239 <6>[ 0.745670] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10559 14:48:57.922850 <6>[ 0.753366] NET: Registered PF_UNIX/PF_LOCAL protocol family
10560 14:48:57.929451 <6>[ 0.759455] RPC: Registered named UNIX socket transport module.
10561 14:48:57.932663 <6>[ 0.765600] RPC: Registered udp transport module.
10562 14:48:57.938871 <6>[ 0.770533] RPC: Registered tcp transport module.
10563 14:48:57.946286 <6>[ 0.775464] RPC: Registered tcp NFSv4.1 backchannel transport module.
10564 14:48:57.950222 <6>[ 0.782127] PCI: CLS 0 bytes, default 64
10565 14:48:57.952959 <6>[ 0.786461] Unpacking initramfs...
10566 14:48:57.969762 <6>[ 0.798525] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10567 14:48:57.979399 <6>[ 0.807174] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10568 14:48:57.982978 <6>[ 0.816028] kvm [1]: IPA Size Limit: 40 bits
10569 14:48:57.989580 <6>[ 0.820556] kvm [1]: GICv3: no GICV resource entry
10570 14:48:57.993192 <6>[ 0.825574] kvm [1]: disabling GICv2 emulation
10571 14:48:57.999571 <6>[ 0.830259] kvm [1]: GIC system register CPU interface enabled
10572 14:48:58.006287 <6>[ 0.837964] kvm [1]: vgic interrupt IRQ18
10573 14:48:58.009358 <6>[ 0.842330] kvm [1]: VHE mode initialized successfully
10574 14:48:58.016866 <5>[ 0.848718] Initialise system trusted keyrings
10575 14:48:58.023909 <6>[ 0.853516] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10576 14:48:58.030896 <6>[ 0.863522] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10577 14:48:58.037862 <5>[ 0.869920] NFS: Registering the id_resolver key type
10578 14:48:58.041091 <5>[ 0.875216] Key type id_resolver registered
10579 14:48:58.048376 <5>[ 0.879630] Key type id_legacy registered
10580 14:48:58.054347 <6>[ 0.883911] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10581 14:48:58.061217 <6>[ 0.890829] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10582 14:48:58.068759 <6>[ 0.898525] 9p: Installing v9fs 9p2000 file system support
10583 14:48:58.104267 <5>[ 0.936144] Key type asymmetric registered
10584 14:48:58.107388 <5>[ 0.940472] Asymmetric key parser 'x509' registered
10585 14:48:58.117956 <6>[ 0.945627] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10586 14:48:58.120784 <6>[ 0.953240] io scheduler mq-deadline registered
10587 14:48:58.124215 <6>[ 0.957998] io scheduler kyber registered
10588 14:48:58.143224 <6>[ 0.975457] EINJ: ACPI disabled.
10589 14:48:58.176144 <4>[ 1.002103] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10590 14:48:58.186349 <4>[ 1.012735] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 14:48:58.202243 <6>[ 1.033867] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10592 14:48:58.209475 <6>[ 1.041822] printk: console [ttyS0] disabled
10593 14:48:58.238048 <6>[ 1.066462] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10594 14:48:58.244144 <6>[ 1.075936] printk: console [ttyS0] enabled
10595 14:48:58.248223 <6>[ 1.075936] printk: console [ttyS0] enabled
10596 14:48:58.254468 <6>[ 1.084830] printk: bootconsole [mtk8250] disabled
10597 14:48:58.257676 <6>[ 1.084830] printk: bootconsole [mtk8250] disabled
10598 14:48:58.264383 <6>[ 1.095887] SuperH (H)SCI(F) driver initialized
10599 14:48:58.268057 <6>[ 1.101171] msm_serial: driver initialized
10600 14:48:58.281346 <6>[ 1.110164] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10601 14:48:58.291800 <6>[ 1.118708] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10602 14:48:58.297637 <6>[ 1.127251] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10603 14:48:58.308207 <6>[ 1.135880] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10604 14:48:58.314670 <6>[ 1.144587] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10605 14:48:58.324392 <6>[ 1.153309] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10606 14:48:58.335271 <6>[ 1.161849] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10607 14:48:58.341078 <6>[ 1.170657] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10608 14:48:58.351705 <6>[ 1.179200] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10609 14:48:58.363006 <6>[ 1.195091] loop: module loaded
10610 14:48:58.370118 <6>[ 1.201021] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10611 14:48:58.392110 <4>[ 1.224225] mtk-pmic-keys: Failed to locate of_node [id: -1]
10612 14:48:58.399140 <6>[ 1.231090] megasas: 07.719.03.00-rc1
10613 14:48:58.408660 <6>[ 1.240728] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10614 14:48:58.420832 <6>[ 1.253289] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10615 14:48:58.437644 <6>[ 1.270008] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10616 14:48:58.494894 <6>[ 1.319993] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10617 14:48:59.670365 <6>[ 2.502919] Freeing initrd memory: 40240K
10618 14:48:59.682259 <6>[ 2.514764] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10619 14:48:59.693235 <6>[ 2.526027] tun: Universal TUN/TAP device driver, 1.6
10620 14:48:59.696912 <6>[ 2.532122] thunder_xcv, ver 1.0
10621 14:48:59.700367 <6>[ 2.535645] thunder_bgx, ver 1.0
10622 14:48:59.703255 <6>[ 2.539138] nicpf, ver 1.0
10623 14:48:59.713900 <6>[ 2.543195] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10624 14:48:59.717820 <6>[ 2.550672] hns3: Copyright (c) 2017 Huawei Corporation.
10625 14:48:59.720922 <6>[ 2.556261] hclge is initializing
10626 14:48:59.727271 <6>[ 2.559843] e1000: Intel(R) PRO/1000 Network Driver
10627 14:48:59.733957 <6>[ 2.564973] e1000: Copyright (c) 1999-2006 Intel Corporation.
10628 14:48:59.737145 <6>[ 2.570984] e1000e: Intel(R) PRO/1000 Network Driver
10629 14:48:59.743777 <6>[ 2.576200] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10630 14:48:59.750600 <6>[ 2.582390] igb: Intel(R) Gigabit Ethernet Network Driver
10631 14:48:59.757909 <6>[ 2.588039] igb: Copyright (c) 2007-2014 Intel Corporation.
10632 14:48:59.764028 <6>[ 2.593875] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10633 14:48:59.770636 <6>[ 2.600393] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10634 14:48:59.773757 <6>[ 2.606857] sky2: driver version 1.30
10635 14:48:59.781553 <6>[ 2.611822] usbcore: registered new device driver r8152-cfgselector
10636 14:48:59.787420 <6>[ 2.618357] usbcore: registered new interface driver r8152
10637 14:48:59.790553 <6>[ 2.624175] VFIO - User Level meta-driver version: 0.3
10638 14:48:59.800232 <6>[ 2.632434] usbcore: registered new interface driver usb-storage
10639 14:48:59.806668 <6>[ 2.638878] usbcore: registered new device driver onboard-usb-hub
10640 14:48:59.815662 <6>[ 2.648076] mt6397-rtc mt6359-rtc: registered as rtc0
10641 14:48:59.825789 <6>[ 2.653537] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:48:59 UTC (1717512539)
10642 14:48:59.829212 <6>[ 2.663125] i2c_dev: i2c /dev entries driver
10643 14:48:59.845954 <6>[ 2.675127] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10644 14:48:59.853060 <4>[ 2.683864] cpu cpu0: supply cpu not found, using dummy regulator
10645 14:48:59.859066 <4>[ 2.690292] cpu cpu1: supply cpu not found, using dummy regulator
10646 14:48:59.866174 <4>[ 2.696712] cpu cpu2: supply cpu not found, using dummy regulator
10647 14:48:59.872735 <4>[ 2.703114] cpu cpu3: supply cpu not found, using dummy regulator
10648 14:48:59.879773 <4>[ 2.709517] cpu cpu4: supply cpu not found, using dummy regulator
10649 14:48:59.885977 <4>[ 2.715915] cpu cpu5: supply cpu not found, using dummy regulator
10650 14:48:59.892423 <4>[ 2.722313] cpu cpu6: supply cpu not found, using dummy regulator
10651 14:48:59.896527 <4>[ 2.728725] cpu cpu7: supply cpu not found, using dummy regulator
10652 14:48:59.918727 <6>[ 2.750366] cpu cpu0: EM: created perf domain
10653 14:48:59.921595 <6>[ 2.755292] cpu cpu4: EM: created perf domain
10654 14:48:59.928643 <6>[ 2.760929] sdhci: Secure Digital Host Controller Interface driver
10655 14:48:59.935300 <6>[ 2.767360] sdhci: Copyright(c) Pierre Ossman
10656 14:48:59.943140 <6>[ 2.772324] Synopsys Designware Multimedia Card Interface Driver
10657 14:48:59.948645 <6>[ 2.778979] sdhci-pltfm: SDHCI platform and OF driver helper
10658 14:48:59.951874 <6>[ 2.779098] mmc0: CQHCI version 5.10
10659 14:48:59.958207 <6>[ 2.788989] ledtrig-cpu: registered to indicate activity on CPUs
10660 14:48:59.965018 <6>[ 2.795978] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10661 14:48:59.971664 <6>[ 2.803035] usbcore: registered new interface driver usbhid
10662 14:48:59.975156 <6>[ 2.808857] usbhid: USB HID core driver
10663 14:48:59.981587 <6>[ 2.813051] spi_master spi0: will run message pump with realtime priority
10664 14:49:00.029340 <6>[ 2.854862] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10665 14:49:00.049164 <6>[ 2.871380] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10666 14:49:00.052739 <6>[ 2.886620] mmc0: Command Queue Engine enabled
10667 14:49:00.059084 <6>[ 2.887383] cros-ec-spi spi0.0: Chrome EC device registered
10668 14:49:00.066251 <6>[ 2.891370] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10669 14:49:00.072565 <6>[ 2.904483] mmcblk0: mmc0:0001 DA4128 116 GiB
10670 14:49:00.083027 <6>[ 2.911761] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10671 14:49:00.089207 <6>[ 2.915333] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10672 14:49:00.096252 <6>[ 2.922058] NET: Registered PF_PACKET protocol family
10673 14:49:00.099751 <6>[ 2.928587] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10674 14:49:00.105713 <6>[ 2.932340] 9pnet: Installing 9P2000 support
10675 14:49:00.109547 <6>[ 2.938254] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10676 14:49:00.116067 <5>[ 2.942072] Key type dns_resolver registered
10677 14:49:00.120019 <6>[ 2.947941] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10678 14:49:00.126618 <6>[ 2.952203] registered taskstats version 1
10679 14:49:00.129760 <5>[ 2.962684] Loading compiled-in X.509 certificates
10680 14:49:00.161734 <4>[ 2.987328] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10681 14:49:00.171529 <4>[ 2.998074] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10682 14:49:00.186475 <6>[ 3.019066] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10683 14:49:00.193351 <6>[ 3.025802] xhci-mtk 11200000.usb: xHCI Host Controller
10684 14:49:00.200011 <6>[ 3.031307] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10685 14:49:00.210997 <6>[ 3.039164] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10686 14:49:00.216433 <6>[ 3.048603] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10687 14:49:00.224146 <6>[ 3.054710] xhci-mtk 11200000.usb: xHCI Host Controller
10688 14:49:00.230132 <6>[ 3.060198] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10689 14:49:00.237365 <6>[ 3.067947] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10690 14:49:00.243463 <6>[ 3.075849] hub 1-0:1.0: USB hub found
10691 14:49:00.246903 <6>[ 3.079885] hub 1-0:1.0: 1 port detected
10692 14:49:00.256407 <6>[ 3.084201] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10693 14:49:00.259805 <6>[ 3.093017] hub 2-0:1.0: USB hub found
10694 14:49:00.263250 <6>[ 3.097046] hub 2-0:1.0: 1 port detected
10695 14:49:00.272913 <6>[ 3.105719] mtk-msdc 11f70000.mmc: Got CD GPIO
10696 14:49:00.292112 <6>[ 3.121027] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10697 14:49:00.299078 <6>[ 3.129061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10698 14:49:00.308760 <4>[ 3.136985] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10699 14:49:00.318812 <6>[ 3.146564] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10700 14:49:00.325094 <6>[ 3.154643] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10701 14:49:00.332069 <6>[ 3.162665] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10702 14:49:00.342089 <6>[ 3.170589] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10703 14:49:00.348860 <6>[ 3.178406] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10704 14:49:00.358747 <6>[ 3.186223] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10705 14:49:00.368671 <6>[ 3.196650] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10706 14:49:00.376004 <6>[ 3.205016] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10707 14:49:00.384944 <6>[ 3.213360] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10708 14:49:00.391882 <6>[ 3.221699] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10709 14:49:00.401915 <6>[ 3.230038] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10710 14:49:00.408460 <6>[ 3.238376] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10711 14:49:00.418896 <6>[ 3.246721] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10712 14:49:00.424769 <6>[ 3.255060] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10713 14:49:00.434802 <6>[ 3.263397] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10714 14:49:00.441749 <6>[ 3.271736] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10715 14:49:00.451398 <6>[ 3.280074] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10716 14:49:00.458265 <6>[ 3.288415] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10717 14:49:00.468259 <6>[ 3.296754] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10718 14:49:00.475278 <6>[ 3.305091] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10719 14:49:00.485607 <6>[ 3.313428] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10720 14:49:00.492134 <6>[ 3.322161] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10721 14:49:00.498490 <6>[ 3.329336] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10722 14:49:00.505896 <6>[ 3.336100] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10723 14:49:00.511479 <6>[ 3.342868] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10724 14:49:00.518899 <6>[ 3.349803] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10725 14:49:00.528103 <6>[ 3.356674] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10726 14:49:00.538408 <6>[ 3.365811] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10727 14:49:00.548164 <6>[ 3.374932] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10728 14:49:00.554924 <6>[ 3.384226] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10729 14:49:00.565171 <6>[ 3.393693] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10730 14:49:00.574883 <6>[ 3.403160] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10731 14:49:00.585164 <6>[ 3.412282] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10732 14:49:00.594751 <6>[ 3.421748] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10733 14:49:00.604584 <6>[ 3.430867] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10734 14:49:00.614869 <6>[ 3.440161] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10735 14:49:00.624513 <6>[ 3.450322] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10736 14:49:00.634045 <6>[ 3.461994] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10737 14:49:00.672444 <6>[ 3.502065] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10738 14:49:00.827958 <6>[ 3.660315] hub 1-1:1.0: USB hub found
10739 14:49:00.831355 <6>[ 3.664834] hub 1-1:1.0: 4 ports detected
10740 14:49:00.841037 <6>[ 3.673586] hub 1-1:1.0: USB hub found
10741 14:49:00.844102 <6>[ 3.678012] hub 1-1:1.0: 4 ports detected
10742 14:49:00.952960 <6>[ 3.782470] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10743 14:49:00.979024 <6>[ 3.811263] hub 2-1:1.0: USB hub found
10744 14:49:00.981964 <6>[ 3.815706] hub 2-1:1.0: 3 ports detected
10745 14:49:00.991052 <6>[ 3.823413] hub 2-1:1.0: USB hub found
10746 14:49:00.994040 <6>[ 3.827964] hub 2-1:1.0: 3 ports detected
10747 14:49:01.168837 <6>[ 3.998223] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10748 14:49:01.301733 <6>[ 4.134070] hub 1-1.4:1.0: USB hub found
10749 14:49:01.305128 <6>[ 4.138729] hub 1-1.4:1.0: 2 ports detected
10750 14:49:01.315250 <6>[ 4.147466] hub 1-1.4:1.0: USB hub found
10751 14:49:01.319100 <6>[ 4.152095] hub 1-1.4:1.0: 2 ports detected
10752 14:49:01.385581 <6>[ 4.214434] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10753 14:49:01.493844 <6>[ 4.322849] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10754 14:49:01.529847 <4>[ 4.358903] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10755 14:49:01.539372 <4>[ 4.367990] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10756 14:49:01.575132 <6>[ 4.407745] r8152 2-1.3:1.0 eth0: v1.12.13
10757 14:49:01.618227 <6>[ 4.446219] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10758 14:49:01.809143 <6>[ 4.638067] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10759 14:49:03.173172 <6>[ 6.005882] r8152 2-1.3:1.0 eth0: carrier on
10760 14:49:05.920954 <5>[ 6.034017] Sending DHCP requests .., OK
10761 14:49:05.927187 <6>[ 8.758296] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10762 14:49:05.930571 <6>[ 8.766582] IP-Config: Complete:
10763 14:49:05.944523 <6>[ 8.770077] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10764 14:49:05.950577 <6>[ 8.780787] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10765 14:49:05.957302 <6>[ 8.789403] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10766 14:49:05.964249 <6>[ 8.789412] nameserver0=192.168.201.1
10767 14:49:05.968516 <6>[ 8.801555] clk: Disabling unused clocks
10768 14:49:05.970685 <6>[ 8.807060] ALSA device list:
10769 14:49:05.977405 <6>[ 8.810330] No soundcards found.
10770 14:49:05.984958 <6>[ 8.817887] Freeing unused kernel memory: 8512K
10771 14:49:05.988477 <6>[ 8.822873] Run /init as init process
10772 14:49:06.017671 <6>[ 8.850333] NET: Registered PF_INET6 protocol family
10773 14:49:06.023820 <6>[ 8.856957] Segment Routing with IPv6
10774 14:49:06.027153 <6>[ 8.860917] In-situ OAM (IOAM) with IPv6
10775 14:49:06.067678 <30>[ 8.873756] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10776 14:49:06.073907 <30>[ 8.906792] systemd[1]: Detected architecture arm64.
10777 14:49:06.074362
10778 14:49:06.080663 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10779 14:49:06.081159
10780 14:49:06.093421 <30>[ 8.926295] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10781 14:49:06.197823 <30>[ 9.027245] systemd[1]: Queued start job for default target graphical.target.
10782 14:49:06.254647 <30>[ 9.084089] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10783 14:49:06.261165 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10784 14:49:06.281058 <30>[ 9.110831] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10785 14:49:06.290783 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10786 14:49:06.310465 <30>[ 9.139912] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10787 14:49:06.319755 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10788 14:49:06.337949 <30>[ 9.167813] systemd[1]: Created slice user.slice - User and Session Slice.
10789 14:49:06.344407 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10790 14:49:06.368654 <30>[ 9.195055] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10791 14:49:06.378277 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10792 14:49:06.395837 <30>[ 9.222413] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10793 14:49:06.402334 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10794 14:49:06.431436 <30>[ 9.250766] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10795 14:49:06.441320 <30>[ 9.270681] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10796 14:49:06.447054 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10797 14:49:06.464588 <30>[ 9.294231] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10798 14:49:06.470983 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10799 14:49:06.488872 <30>[ 9.318250] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10800 14:49:06.498045 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10801 14:49:06.513080 <30>[ 9.346302] systemd[1]: Reached target paths.target - Path Units.
10802 14:49:06.523268 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10803 14:49:06.541195 <30>[ 9.370638] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10804 14:49:06.547244 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10805 14:49:06.561179 <30>[ 9.394192] systemd[1]: Reached target slices.target - Slice Units.
10806 14:49:06.571025 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10807 14:49:06.585489 <30>[ 9.418679] systemd[1]: Reached target swap.target - Swaps.
10808 14:49:06.592619 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10809 14:49:06.613512 <30>[ 9.442726] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10810 14:49:06.622973 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10811 14:49:06.641708 <30>[ 9.471183] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10812 14:49:06.651336 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10813 14:49:06.671002 <30>[ 9.500185] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10814 14:49:06.680626 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10815 14:49:06.697045 <30>[ 9.526895] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10816 14:49:06.706976 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10817 14:49:06.725921 <30>[ 9.554780] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10818 14:49:06.731657 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10819 14:49:06.749362 <30>[ 9.578881] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10820 14:49:06.759490 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10821 14:49:06.777860 <30>[ 9.607612] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10822 14:49:06.787545 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10823 14:49:06.805700 <30>[ 9.635335] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10824 14:49:06.815478 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10825 14:49:06.856789 <30>[ 9.686268] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10826 14:49:06.863119 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10827 14:49:06.884910 <30>[ 9.714529] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10828 14:49:06.890980 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10829 14:49:06.914677 <30>[ 9.744245] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10830 14:49:06.920822 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10831 14:49:06.946983 <30>[ 9.770462] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10832 14:49:06.960079 <30>[ 9.790013] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10833 14:49:06.970622 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10834 14:49:07.029235 <30>[ 9.858805] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10835 14:49:07.035821 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10836 14:49:07.062996 <30>[ 9.891131] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10837 14:49:07.074697 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 9.905094] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10838 14:49:07.077580 Module dm_mod...
10839 14:49:07.116765 <30>[ 9.946723] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10840 14:49:07.123495 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10841 14:49:07.143693 <30>[ 9.973385] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10842 14:49:07.153812 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10843 14:49:07.173671 <30>[ 10.003890] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10844 14:49:07.181122 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10845 14:49:07.237766 <30>[ 10.066866] systemd[1]: Starting systemd-journald.service - Journal Service...
10846 14:49:07.243666 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10847 14:49:07.268278 <30>[ 10.097552] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10848 14:49:07.274318 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10849 14:49:07.301798 <30>[ 10.127204] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10850 14:49:07.307404 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10851 14:49:07.330249 <30>[ 10.159596] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10852 14:49:07.340317 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10853 14:49:07.360039 <30>[ 10.189640] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10854 14:49:07.366666 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10855 14:49:07.390838 <30>[ 10.221044] systemd[1]: Started systemd-journald.service - Journal Service.
10856 14:49:07.398215 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10857 14:49:07.420828 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10858 14:49:07.437292 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10859 14:49:07.457505 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10860 14:49:07.478170 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10861 14:49:07.502395 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10862 14:49:07.522638 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10863 14:49:07.543061 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10864 14:49:07.564065 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10865 14:49:07.583441 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10866 14:49:07.603134 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10867 14:49:07.625789 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10868 14:49:07.651301 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10869 14:49:07.669369 See 'systemctl status systemd-remount-fs.service' for details.
10870 14:49:07.694959 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10871 14:49:07.720194 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10872 14:49:07.772560 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10873 14:49:07.792845 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10874 14:49:07.811836 Startin<46>[ 10.642163] systemd-journald[183]: Received client request to flush runtime journal.
10875 14:49:07.818684 g [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10876 14:49:07.845225 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10877 14:49:07.872241 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10878 14:49:07.894754 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10879 14:49:07.917636 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10880 14:49:07.937980 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10881 14:49:07.961881 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10882 14:49:07.985656 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10883 14:49:08.044853 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10884 14:49:08.071919 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10885 14:49:08.089159 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10886 14:49:08.104403 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10887 14:49:08.144890 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10888 14:49:08.159762 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10889 14:49:08.189284 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10890 14:49:08.210202 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10891 14:49:08.238199 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10892 14:49:08.314144 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10893 14:49:08.345769 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10894 14:49:08.372957 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10895 14:49:08.413579 <5>[ 11.243822] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10896 14:49:08.437061 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10897 14:49:08.454589 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10898 14:49:08.461063 <5>[ 11.290919] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10899 14:49:08.470802 <5>[ 11.299623] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10900 14:49:08.480204 <4>[ 11.308941] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10901 14:49:08.483956 <6>[ 11.317850] cfg80211: failed to load regulatory.db
10902 14:49:08.494108 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10903 14:49:08.551336 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10904 14:49:08.568661 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10905 14:49:08.585173 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10906 14:49:08.605510 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10907 14:49:08.612596 <6>[ 11.444423] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10908 14:49:08.624890 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10909 14:49:08.628420 <6>[ 11.463170] remoteproc remoteproc0: scp is available
10910 14:49:08.635190 <6>[ 11.468840] remoteproc remoteproc0: powering up scp
10911 14:49:08.645467 <6>[ 11.474363] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10912 14:49:08.652409 <6>[ 11.483156] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10913 14:49:08.658585 [[0;32m OK [<3>[ 11.489187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 14:49:08.668468 0m] Reached targ<3>[ 11.498570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 14:49:08.679056 <3>[ 11.508031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10916 14:49:08.689172 et [0;1;39mtime<6>[ 11.510211] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10917 14:49:08.698476 rs.target[0m - <6>[ 11.525222] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10918 14:49:08.699028 Timer Units.
10919 14:49:08.705405 <3>[ 11.525369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10920 14:49:08.714516 <6>[ 11.535222] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10921 14:49:08.725228 <3>[ 11.544686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 14:49:08.731481 <3>[ 11.544696] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10923 14:49:08.739117 <3>[ 11.544709] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10924 14:49:08.748349 <3>[ 11.544715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10925 14:49:08.751950 <6>[ 11.546700] mc: Linux media interface: v0.10
10926 14:49:08.761430 <3>[ 11.563205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10927 14:49:08.768214 <4>[ 11.582135] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10928 14:49:08.774552 <6>[ 11.582218] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10929 14:49:08.785056 <3>[ 11.597244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 14:49:08.791280 <4>[ 11.606205] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10931 14:49:08.798276 <3>[ 11.613734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10932 14:49:08.804537 <6>[ 11.613787] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10933 14:49:08.811682 <6>[ 11.614183] videodev: Linux video capture interface: v2.00
10934 14:49:08.821520 <6>[ 11.650084] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10935 14:49:08.828251 <3>[ 11.650461] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10936 14:49:08.837925 <6>[ 11.651456] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10937 14:49:08.844679 <6>[ 11.653421] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10938 14:49:08.851463 <6>[ 11.658646] remoteproc remoteproc0: remote processor scp is now up
10939 14:49:08.861199 [[0;32m OK [<3>[ 11.666952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10940 14:49:08.871040 0m] Listening on<6>[ 11.670813] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10941 14:49:08.881507 <6>[ 11.671229] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10942 14:49:08.891417 <4>[ 11.684069] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10943 14:49:08.894038 <4>[ 11.684069] Fallback method does not support PEC.
10944 14:49:08.904107 [0;1;39mdbus.s<6>[ 11.688249] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10945 14:49:08.907765 <6>[ 11.688254] pci_bus 0000:00: root bus resource [bus 00-ff]
10946 14:49:08.917430 ocket[…- D-Bu<6>[ 11.688258] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10947 14:49:08.927991 <6>[ 11.688260] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10948 14:49:08.934457 s System Message<6>[ 11.688286] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10949 14:49:08.940793 <6>[ 11.688300] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10950 14:49:08.947345 <6>[ 11.688362] pci 0000:00:00.0: supports D1 D2
10951 14:49:08.954520 <6>[ 11.688364] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10952 14:49:08.961145 <6>[ 11.689267] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10953 14:49:08.967847 <6>[ 11.689342] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10954 14:49:08.977422 <6>[ 11.689367] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10955 14:49:08.978021 Bus Socket.
10956 14:49:08.984060 <6>[ 11.689383] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10957 14:49:08.990669 <6>[ 11.689398] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10958 14:49:08.997629 <6>[ 11.689502] pci 0000:01:00.0: supports D1 D2
10959 14:49:09.004095 <6>[ 11.689503] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10960 14:49:09.010619 <3>[ 11.689647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10961 14:49:09.020684 <3>[ 11.689651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10962 14:49:09.027298 <3>[ 11.689655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10963 14:49:09.033771 <6>[ 11.702124] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10964 14:49:09.043810 <3>[ 11.711006] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10965 14:49:09.050288 <6>[ 11.719893] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10966 14:49:09.060516 <3>[ 11.733415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10967 14:49:09.067225 <6>[ 11.737546] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10968 14:49:09.077295 <6>[ 11.741687] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10969 14:49:09.080562 <6>[ 11.766590] Bluetooth: Core ver 2.22
10970 14:49:09.087333 <6>[ 11.773530] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10971 14:49:09.093874 <6>[ 11.781012] NET: Registered PF_BLUETOOTH protocol family
10972 14:49:09.100969 <6>[ 11.785480] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10973 14:49:09.107411 <6>[ 11.792319] Bluetooth: HCI device and connection manager initialized
10974 14:49:09.113266 <6>[ 11.792336] Bluetooth: HCI socket layer initialized
10975 14:49:09.119983 <6>[ 11.800606] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10976 14:49:09.127006 <6>[ 11.802061] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10977 14:49:09.140222 <6>[ 11.803793] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10978 14:49:09.146705 <6>[ 11.804138] usbcore: registered new interface driver uvcvideo
10979 14:49:09.153659 <6>[ 11.806836] Bluetooth: L2CAP socket layer initialized
10980 14:49:09.157113 <6>[ 11.814337] pci 0000:00:00.0: PCI bridge to [bus 01]
10981 14:49:09.163977 <6>[ 11.823094] Bluetooth: SCO socket layer initialized
10982 14:49:09.170098 <6>[ 11.830573] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10983 14:49:09.176477 <6>[ 11.831909] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10984 14:49:09.183215 <6>[ 11.897809] usbcore: registered new interface driver btusb
10985 14:49:09.193378 <4>[ 11.899061] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10986 14:49:09.200025 <3>[ 11.899072] Bluetooth: hci0: Failed to load firmware file (-2)
10987 14:49:09.206260 <3>[ 11.899074] Bluetooth: hci0: Failed to set up firmware (-2)
10988 14:49:09.216822 <4>[ 11.899077] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10989 14:49:09.222946 <6>[ 11.906723] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10990 14:49:09.230003 [[0;32m OK [<6>[ 12.060973] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10991 14:49:09.236033 0m] Reached targ<6>[ 12.068533] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10992 14:49:09.239777 et [0;1;39msockets.target[0m - Socket Units.
10993 14:49:09.250730 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10994 14:49:09.285972 <3>[ 12.115887] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 14:49:09.292264 <6>[ 12.118410] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10996 14:49:09.299285 <6>[ 12.132199] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10997 14:49:09.309787 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10998 14:49:09.325100 <6>[ 12.158697] mt7921e 0000:01:00.0: ASIC revision: 79610010
10999 14:49:09.345555 Starting [0;1;39msystemd-logind.se…i<3>[ 12.174862] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 14:49:09.358672 ce[0m - User Login Management..<3>[ 12.187003] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 14:49:09.359213 .
11002 14:49:09.384782 <3>[ 12.214228] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 14:49:09.391700 <3>[ 12.215003] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11004 14:49:09.401286 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11005 14:49:09.432418 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus Sy<6>[ 12.260793] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11006 14:49:09.432970 <6>[ 12.260793]
11007 14:49:09.435627 stem Message Bus.
11008 14:49:09.442317 <3>[ 12.273892] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 14:49:09.459547 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11010 14:49:09.472740 <3>[ 12.303121] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 14:49:09.504487 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m <3>[ 12.332390] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 14:49:09.505092 - User Login Management.
11013 14:49:09.535214 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/system<3>[ 12.363160] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 14:49:09.535950 d-backlight.
11015 14:49:09.551918 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11016 14:49:09.568051 <3>[ 12.397847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 14:49:09.577991 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11018 14:49:09.615191 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11019 14:49:09.639795 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11020 14:49:09.656772 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11021 14:49:09.671428 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11022 14:49:09.690756 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11023 14:49:09.700476 <6>[ 12.529535] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11024 14:49:09.750448 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11025 14:49:09.773227 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11026 14:49:09.797878 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11027 14:49:09.872822 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11028 14:49:09.895479 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11029 14:49:09.917385 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11030 14:49:09.975559
11031 14:49:09.978931 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11032 14:49:09.979384
11033 14:49:09.981743 debian-bookworm-arm64 login: root (automatic login)
11034 14:49:09.982193
11035 14:49:09.994815 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
11036 14:49:09.995354
11037 14:49:10.001381 The programs included with the Debian GNU/Linux system are free software;
11038 14:49:10.008437 the exact distribution terms for each program are described in the
11039 14:49:10.011655 individual files in /usr/share/doc/*/copyright.
11040 14:49:10.012198
11041 14:49:10.018028 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11042 14:49:10.021327 permitted by applicable law.
11043 14:49:10.022758 Matched prompt #10: / #
11045 14:49:10.023825 Setting prompt string to ['/ #']
11046 14:49:10.024282 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11048 14:49:10.025368 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11049 14:49:10.025842 start: 2.2.6 expect-shell-connection (timeout 00:02:50) [common]
11050 14:49:10.026224 Setting prompt string to ['/ #']
11051 14:49:10.026550 Forcing a shell prompt, looking for ['/ #']
11053 14:49:10.077414 / #
11054 14:49:10.078137 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11055 14:49:10.078572 Waiting using forced prompt support (timeout 00:02:30)
11056 14:49:10.084319
11057 14:49:10.085197 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11058 14:49:10.085700 start: 2.2.7 export-device-env (timeout 00:02:50) [common]
11059 14:49:10.086173 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11060 14:49:10.086647 end: 2.2 depthcharge-retry (duration 00:02:10) [common]
11061 14:49:10.087100 end: 2 depthcharge-action (duration 00:02:10) [common]
11062 14:49:10.087572 start: 3 lava-test-retry (timeout 00:07:29) [common]
11063 14:49:10.088011 start: 3.1 lava-test-shell (timeout 00:07:29) [common]
11064 14:49:10.088405 Using namespace: common
11066 14:49:10.189682 / # #
11067 14:49:10.190316 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11068 14:49:10.196467 #
11069 14:49:10.197539 Using /lava-14167053
11071 14:49:10.298773 / # export SHELL=/bin/sh
11072 14:49:10.305445 export SHELL=/bin/sh
11074 14:49:10.407185 / # . /lava-14167053/environment
11075 14:49:10.414073 . /lava-14167053/environment
11077 14:49:10.515759 / # /lava-14167053/bin/lava-test-runner /lava-14167053/0
11078 14:49:10.516407 Test shell timeout: 10s (minimum of the action and connection timeout)
11079 14:49:10.521991 /lava-14167053/bin/lava-test-runner /lava-14167053/0
11080 14:49:10.545948 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11081 14:49:10.552782 + cd /lava-14167053/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11082 14:49:10.553388 + cat uuid
11083 14:49:10.555397 + UUID=14167053_1.5.2.3.1
11084 14:49:10.555846 + set +x
11085 14:49:10.559643 Received signal: <STARTRUN> 0_v4l<6
11087 14:49:10.560702 end: 3.1 lava-test-shell (duration 00:00:00) [common]
11089 14:49:10.561725 lava-test-retry failed: 1 of 1 attempts. 'Invalid signal'
11091 14:49:10.562521 end: 3 lava-test-retry (duration 00:00:00) [common]
11093 14:49:10.563653 Cleaning after the job
11094 14:49:10.564118 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/ramdisk
11095 14:49:10.584674 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/kernel
11096 14:49:10.609922 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/dtb
11097 14:49:10.610190 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167053/tftp-deploy-4rwsbx_p/modules
11098 14:49:10.617327 start: 4.1 power-off (timeout 00:00:30) [common]
11099 14:49:10.617535 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11100 14:49:10.696560 >> Command sent successfully.
11101 14:49:10.706808 Returned 0 in 0 seconds
11102 14:49:10.808142 end: 4.1 power-off (duration 00:00:00) [common]
11104 14:49:10.809785 start: 4.2 read-feedback (timeout 00:10:00) [common]
11105 14:49:10.811066 Listened to connection for namespace 'common' for up to 1s
11121 14:49:10.818020 Listened to connection for namespace 'common' for up to 1s
11122 14:49:11.811761 Finalising connection for namespace 'common'
11123 14:49:11.812428 Disconnecting from shell: Finalise
11124 14:49:11.812815 Bus info : platform:170200�
11125 14:49:11.913877 end: 4.2 read-feedback (duration 00:00:01) [common]
11126 14:49:11.914526 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14167053
11127 14:49:12.016029 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14167053
11128 14:49:12.016220 TestError: A test failed to run, look at the error message.