Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 20
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 13:14:00.576529 lava-dispatcher, installed at version: 2024.05
2 13:14:00.576734 start: 0 validate
3 13:14:00.576848 Start time: 2024-07-18 13:14:00.576842+00:00 (UTC)
4 13:14:00.576988 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:14:00.577175 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:14:00.840337 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:14:00.840496 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 13:14:01.097118 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:14:01.097316 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:14:01.354651 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:14:01.354835 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.96-cip24-23-g9db533125afb0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 13:14:01.615042 validate duration: 1.04
14 13:14:01.615380 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:14:01.615507 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:14:01.615626 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:14:01.615825 Not decompressing ramdisk as can be used compressed.
18 13:14:01.615995 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 13:14:01.616103 saving as /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/ramdisk/rootfs.cpio.gz
20 13:14:01.616201 total size: 39026414 (37 MB)
21 13:14:01.617636 progress 0 % (0 MB)
22 13:14:01.628513 progress 5 % (1 MB)
23 13:14:01.639138 progress 10 % (3 MB)
24 13:14:01.649457 progress 15 % (5 MB)
25 13:14:01.660149 progress 20 % (7 MB)
26 13:14:01.670651 progress 25 % (9 MB)
27 13:14:01.681449 progress 30 % (11 MB)
28 13:14:01.691817 progress 35 % (13 MB)
29 13:14:01.702309 progress 40 % (14 MB)
30 13:14:01.712606 progress 45 % (16 MB)
31 13:14:01.723046 progress 50 % (18 MB)
32 13:14:01.733828 progress 55 % (20 MB)
33 13:14:01.744189 progress 60 % (22 MB)
34 13:14:01.754832 progress 65 % (24 MB)
35 13:14:01.765205 progress 70 % (26 MB)
36 13:14:01.776130 progress 75 % (27 MB)
37 13:14:01.786426 progress 80 % (29 MB)
38 13:14:01.796782 progress 85 % (31 MB)
39 13:14:01.806956 progress 90 % (33 MB)
40 13:14:01.817663 progress 95 % (35 MB)
41 13:14:01.828049 progress 100 % (37 MB)
42 13:14:01.828360 37 MB downloaded in 0.21 s (175.43 MB/s)
43 13:14:01.828574 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:14:01.828937 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:14:01.829047 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:14:01.829191 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:14:01.829366 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 13:14:01.829464 saving as /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/kernel/Image
50 13:14:01.829523 total size: 54813184 (52 MB)
51 13:14:01.829578 No compression specified
52 13:14:01.830874 progress 0 % (0 MB)
53 13:14:01.845735 progress 5 % (2 MB)
54 13:14:01.860935 progress 10 % (5 MB)
55 13:14:01.875936 progress 15 % (7 MB)
56 13:14:01.890349 progress 20 % (10 MB)
57 13:14:01.904903 progress 25 % (13 MB)
58 13:14:01.919319 progress 30 % (15 MB)
59 13:14:01.934000 progress 35 % (18 MB)
60 13:14:01.948705 progress 40 % (20 MB)
61 13:14:01.963449 progress 45 % (23 MB)
62 13:14:01.978235 progress 50 % (26 MB)
63 13:14:01.992812 progress 55 % (28 MB)
64 13:14:02.007344 progress 60 % (31 MB)
65 13:14:02.022015 progress 65 % (34 MB)
66 13:14:02.036370 progress 70 % (36 MB)
67 13:14:02.050889 progress 75 % (39 MB)
68 13:14:02.064967 progress 80 % (41 MB)
69 13:14:02.078921 progress 85 % (44 MB)
70 13:14:02.093242 progress 90 % (47 MB)
71 13:14:02.107235 progress 95 % (49 MB)
72 13:14:02.121008 progress 100 % (52 MB)
73 13:14:02.121320 52 MB downloaded in 0.29 s (179.15 MB/s)
74 13:14:02.121475 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:14:02.121737 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:14:02.121835 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:14:02.121916 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:14:02.122048 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:14:02.122137 saving as /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/dtb/mt8192-asurada-spherion-r0.dtb
81 13:14:02.122219 total size: 47258 (0 MB)
82 13:14:02.122299 No compression specified
83 13:14:02.123820 progress 69 % (0 MB)
84 13:14:02.124103 progress 100 % (0 MB)
85 13:14:02.124275 0 MB downloaded in 0.00 s (21.95 MB/s)
86 13:14:02.124433 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:14:02.124764 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:14:02.124869 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:14:02.124975 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:14:02.125113 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.96-cip24-23-g9db533125afb0/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 13:14:02.125242 saving as /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/modules/modules.tar
93 13:14:02.125322 total size: 8611320 (8 MB)
94 13:14:02.125406 Using unxz to decompress xz
95 13:14:02.127371 progress 0 % (0 MB)
96 13:14:02.148489 progress 5 % (0 MB)
97 13:14:02.173908 progress 10 % (0 MB)
98 13:14:02.200134 progress 15 % (1 MB)
99 13:14:02.226719 progress 20 % (1 MB)
100 13:14:02.252492 progress 25 % (2 MB)
101 13:14:02.277980 progress 30 % (2 MB)
102 13:14:02.300567 progress 35 % (2 MB)
103 13:14:02.329055 progress 40 % (3 MB)
104 13:14:02.356298 progress 45 % (3 MB)
105 13:14:02.382244 progress 50 % (4 MB)
106 13:14:02.408069 progress 55 % (4 MB)
107 13:14:02.433298 progress 60 % (4 MB)
108 13:14:02.457423 progress 65 % (5 MB)
109 13:14:02.483325 progress 70 % (5 MB)
110 13:14:02.511394 progress 75 % (6 MB)
111 13:14:02.539505 progress 80 % (6 MB)
112 13:14:02.564032 progress 85 % (7 MB)
113 13:14:02.588415 progress 90 % (7 MB)
114 13:14:02.612514 progress 95 % (7 MB)
115 13:14:02.635061 progress 100 % (8 MB)
116 13:14:02.640594 8 MB downloaded in 0.52 s (15.94 MB/s)
117 13:14:02.640755 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:14:02.640983 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:14:02.641065 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:14:02.641156 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:14:02.641232 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:14:02.641306 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:14:02.641480 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv
125 13:14:02.641600 makedir: /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin
126 13:14:02.641694 makedir: /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/tests
127 13:14:02.641784 makedir: /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/results
128 13:14:02.641875 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-add-keys
129 13:14:02.642005 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-add-sources
130 13:14:02.642124 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-background-process-start
131 13:14:02.642258 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-background-process-stop
132 13:14:02.642406 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-common-functions
133 13:14:02.642521 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-echo-ipv4
134 13:14:02.642634 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-install-packages
135 13:14:02.642745 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-installed-packages
136 13:14:02.642857 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-os-build
137 13:14:02.642971 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-probe-channel
138 13:14:02.643083 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-probe-ip
139 13:14:02.643247 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-target-ip
140 13:14:02.643362 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-target-mac
141 13:14:02.643475 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-target-storage
142 13:14:02.643588 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-test-case
143 13:14:02.643699 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-test-event
144 13:14:02.643809 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-test-feedback
145 13:14:02.643921 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-test-raise
146 13:14:02.644033 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-test-reference
147 13:14:02.644142 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-test-runner
148 13:14:02.644259 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-test-set
149 13:14:02.644372 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-test-shell
150 13:14:02.644489 Updating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-install-packages (oe)
151 13:14:02.644626 Updating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/bin/lava-installed-packages (oe)
152 13:14:02.644743 Creating /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/environment
153 13:14:02.644832 LAVA metadata
154 13:14:02.644900 - LAVA_JOB_ID=14879020
155 13:14:02.644958 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:14:02.645048 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:14:02.645110 skipped lava-vland-overlay
158 13:14:02.645219 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:14:02.645290 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:14:02.645347 skipped lava-multinode-overlay
161 13:14:02.645416 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:14:02.645487 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:14:02.645553 Loading test definitions
164 13:14:02.645630 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:14:02.645694 Using /lava-14879020 at stage 0
166 13:14:02.645990 uuid=14879020_1.5.2.3.1 testdef=None
167 13:14:02.646071 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:14:02.646146 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:14:02.646647 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:14:02.646847 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:14:02.647413 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:14:02.647632 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:14:02.648179 runner path: /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/0/tests/0_cros-ec test_uuid 14879020_1.5.2.3.1
176 13:14:02.648324 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:14:02.648522 Creating lava-test-runner.conf files
179 13:14:02.648579 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14879020/lava-overlay-4xr175zv/lava-14879020/0 for stage 0
180 13:14:02.648659 - 0_cros-ec
181 13:14:02.648748 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:14:02.648823 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:14:02.655399 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:14:02.655499 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:14:02.655579 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:14:02.655660 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:14:02.655737 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:14:03.749419 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:14:03.749565 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:14:03.749644 extracting modules file /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14879020/extract-overlay-ramdisk-5ysn_ex7/ramdisk
191 13:14:03.994080 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:14:03.994247 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:14:03.994348 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879020/compress-overlay-8emgr05n/overlay-1.5.2.4.tar.gz to ramdisk
194 13:14:03.994410 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14879020/compress-overlay-8emgr05n/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14879020/extract-overlay-ramdisk-5ysn_ex7/ramdisk
195 13:14:04.001231 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:14:04.001364 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:14:04.001463 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:14:04.001541 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:14:04.001610 Building ramdisk /var/lib/lava/dispatcher/tmp/14879020/extract-overlay-ramdisk-5ysn_ex7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14879020/extract-overlay-ramdisk-5ysn_ex7/ramdisk
200 13:14:05.047683 >> 335502 blocks
201 13:14:10.308461 rename /var/lib/lava/dispatcher/tmp/14879020/extract-overlay-ramdisk-5ysn_ex7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/ramdisk/ramdisk.cpio.gz
202 13:14:10.308641 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 13:14:10.308734 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 13:14:10.308812 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 13:14:10.308889 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/kernel/Image']
206 13:14:24.353651 Returned 0 in 14 seconds
207 13:14:24.353836 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/kernel/image.itb
208 13:14:25.129925 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:14:25.130062 output: Created: Thu Jul 18 14:14:24 2024
210 13:14:25.130151 output: Image 0 (kernel-1)
211 13:14:25.130234 output: Description:
212 13:14:25.130316 output: Created: Thu Jul 18 14:14:24 2024
213 13:14:25.130396 output: Type: Kernel Image
214 13:14:25.130477 output: Compression: lzma compressed
215 13:14:25.130559 output: Data Size: 13114469 Bytes = 12807.10 KiB = 12.51 MiB
216 13:14:25.130640 output: Architecture: AArch64
217 13:14:25.130718 output: OS: Linux
218 13:14:25.130798 output: Load Address: 0x00000000
219 13:14:25.130877 output: Entry Point: 0x00000000
220 13:14:25.130954 output: Hash algo: crc32
221 13:14:25.131034 output: Hash value: a47b020b
222 13:14:25.131111 output: Image 1 (fdt-1)
223 13:14:25.131191 output: Description: mt8192-asurada-spherion-r0
224 13:14:25.131267 output: Created: Thu Jul 18 14:14:24 2024
225 13:14:25.131347 output: Type: Flat Device Tree
226 13:14:25.131424 output: Compression: uncompressed
227 13:14:25.131501 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:14:25.131578 output: Architecture: AArch64
229 13:14:25.131658 output: Hash algo: crc32
230 13:14:25.131735 output: Hash value: 0f8e4d2e
231 13:14:25.131811 output: Image 2 (ramdisk-1)
232 13:14:25.131887 output: Description: unavailable
233 13:14:25.131967 output: Created: Thu Jul 18 14:14:24 2024
234 13:14:25.132044 output: Type: RAMDisk Image
235 13:14:25.132121 output: Compression: uncompressed
236 13:14:25.132200 output: Data Size: 52127641 Bytes = 50905.90 KiB = 49.71 MiB
237 13:14:25.132276 output: Architecture: AArch64
238 13:14:25.132356 output: OS: Linux
239 13:14:25.132432 output: Load Address: unavailable
240 13:14:25.132508 output: Entry Point: unavailable
241 13:14:25.132583 output: Hash algo: crc32
242 13:14:25.132662 output: Hash value: 5ae313e6
243 13:14:25.132738 output: Default Configuration: 'conf-1'
244 13:14:25.132814 output: Configuration 0 (conf-1)
245 13:14:25.132890 output: Description: mt8192-asurada-spherion-r0
246 13:14:25.132970 output: Kernel: kernel-1
247 13:14:25.133047 output: Init Ramdisk: ramdisk-1
248 13:14:25.133133 output: FDT: fdt-1
249 13:14:25.133248 output: Loadables: kernel-1
250 13:14:25.133327 output:
251 13:14:25.133460 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 13:14:25.133563 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 13:14:25.133669 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 13:14:25.133772 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 13:14:25.133861 No LXC device requested
256 13:14:25.133964 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:14:25.134066 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 13:14:25.134166 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:14:25.134249 Checking files for TFTP limit of 4294967296 bytes.
260 13:14:25.134754 end: 1 tftp-deploy (duration 00:00:24) [common]
261 13:14:25.134872 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:14:25.134986 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:14:25.135116 substitutions:
264 13:14:25.135205 - {DTB}: 14879020/tftp-deploy-9azu58h2/dtb/mt8192-asurada-spherion-r0.dtb
265 13:14:25.135289 - {INITRD}: 14879020/tftp-deploy-9azu58h2/ramdisk/ramdisk.cpio.gz
266 13:14:25.135375 - {KERNEL}: 14879020/tftp-deploy-9azu58h2/kernel/Image
267 13:14:25.135454 - {LAVA_MAC}: None
268 13:14:25.135538 - {PRESEED_CONFIG}: None
269 13:14:25.135616 - {PRESEED_LOCAL}: None
270 13:14:25.135696 - {RAMDISK}: 14879020/tftp-deploy-9azu58h2/ramdisk/ramdisk.cpio.gz
271 13:14:25.135783 - {ROOT_PART}: None
272 13:14:25.135864 - {ROOT}: None
273 13:14:25.135942 - {SERVER_IP}: 192.168.201.1
274 13:14:25.136022 - {TEE}: None
275 13:14:25.136100 Parsed boot commands:
276 13:14:25.136179 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:14:25.136363 Parsed boot commands: tftpboot 192.168.201.1 14879020/tftp-deploy-9azu58h2/kernel/image.itb 14879020/tftp-deploy-9azu58h2/kernel/cmdline
278 13:14:25.136470 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:14:25.136580 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:14:25.136687 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:14:25.136786 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:14:25.136869 Not connected, no need to disconnect.
283 13:14:25.136964 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:14:25.137066 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:14:25.137187 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 13:14:25.140101 Setting prompt string to ['lava-test: # ']
287 13:14:25.140424 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:14:25.140543 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:14:25.140661 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:14:25.140800 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:14:25.141145 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=reboot']
292 13:14:34.284701 >> Command sent successfully.
293 13:14:34.299857 Returned 0 in 9 seconds
294 13:14:34.300562 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 13:14:34.301925 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 13:14:34.302628 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 13:14:34.303073 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:14:34.303468 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:14:34.304040 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:14:34.306000 [Enter `^Ec?' for help]
302 13:14:35.559038
303 13:14:35.559166
304 13:14:35.559237 F0: 102B 0000
305 13:14:35.559299
306 13:14:35.559356 F3: 1001 0000 [0200]
307 13:14:35.562047
308 13:14:35.562112 F3: 1001 0000
309 13:14:35.562174
310 13:14:35.562225 F7: 102D 0000
311 13:14:35.562276
312 13:14:35.565212 F1: 0000 0000
313 13:14:35.565271
314 13:14:35.565321 V0: 0000 0000 [0001]
315 13:14:35.565375
316 13:14:35.569140 00: 0007 8000
317 13:14:35.569206
318 13:14:35.569257 01: 0000 0000
319 13:14:35.569308
320 13:14:35.571947 BP: 0C00 0209 [0000]
321 13:14:35.572006
322 13:14:35.572056 G0: 1182 0000
323 13:14:35.572105
324 13:14:35.575409 EC: 0000 0021 [4000]
325 13:14:35.575468
326 13:14:35.575524 S7: 0000 0000 [0000]
327 13:14:35.575574
328 13:14:35.579035 CC: 0000 0000 [0001]
329 13:14:35.579100
330 13:14:35.579150 T0: 0000 0040 [010F]
331 13:14:35.579200
332 13:14:35.581944 Jump to BL
333 13:14:35.582003
334 13:14:35.605936
335 13:14:35.606009
336 13:14:35.613468 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 13:14:35.617267 ARM64: Exception handlers installed.
338 13:14:35.620795 ARM64: Testing exception
339 13:14:35.624765 ARM64: Done test exception
340 13:14:35.628346 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 13:14:35.640768 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 13:14:35.647377 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 13:14:35.657468 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 13:14:35.664703 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 13:14:35.671218 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 13:14:35.682190 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 13:14:35.688955 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 13:14:35.709636 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 13:14:35.713189 WDT: Last reset was cold boot
350 13:14:35.717047 SPI1(PAD0) initialized at 2873684 Hz
351 13:14:35.720832 SPI5(PAD0) initialized at 992727 Hz
352 13:14:35.720899 VBOOT: Loading verstage.
353 13:14:35.728409 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 13:14:35.731898 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 13:14:35.735029 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 13:14:35.738400 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 13:14:35.746009 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 13:14:35.752785 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 13:14:35.763535 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 13:14:35.763615
361 13:14:35.763677
362 13:14:35.774007 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 13:14:35.776942 ARM64: Exception handlers installed.
364 13:14:35.780638 ARM64: Testing exception
365 13:14:35.780703 ARM64: Done test exception
366 13:14:35.786924 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 13:14:35.790807 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 13:14:35.804632 Probing TPM: . done!
369 13:14:35.804703 TPM ready after 0 ms
370 13:14:35.811668 Connected to device vid:did:rid of 1ae0:0028:00
371 13:14:35.818047 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 13:14:35.869070 Initialized TPM device CR50 revision 0
373 13:14:35.872647 tlcl_send_startup: Startup return code is 0
374 13:14:35.881088 TPM: setup succeeded
375 13:14:35.892384 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 13:14:35.900948 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 13:14:35.911020 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 13:14:35.920021 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 13:14:35.923175 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 13:14:35.926422 in-header: 03 07 00 00 08 00 00 00
381 13:14:35.929696 in-data: aa e4 47 04 13 02 00 00
382 13:14:35.932958 Chrome EC: UHEPI supported
383 13:14:35.940192 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 13:14:35.953658 in-header: 03 a9 00 00 08 00 00 00
385 13:14:35.957370 in-data: 84 60 60 08 00 00 00 00
386 13:14:35.957442 Phase 1
387 13:14:35.961248 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 13:14:35.968469 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 13:14:35.972209 VB2:vb2_check_recovery() Recovery was requested manually
390 13:14:35.979908 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 13:14:35.983680 Recovery requested (1009000e)
392 13:14:35.990957 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:14:35.996436 tlcl_extend: response is 0
394 13:14:36.005655 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:14:36.011368 tlcl_extend: response is 0
396 13:14:36.018753 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:14:36.038653 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 13:14:36.045947 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:14:36.046051
400 13:14:36.046126
401 13:14:36.053384 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:14:36.057178 ARM64: Exception handlers installed.
403 13:14:36.060828 ARM64: Testing exception
404 13:14:36.063994 ARM64: Done test exception
405 13:14:36.084285 pmic_efuse_setting: Set efuses in 11 msecs
406 13:14:36.087815 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:14:36.091829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:14:36.099693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:14:36.103514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:14:36.107369 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:14:36.110627 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:14:36.118184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:14:36.122285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:14:36.126009 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:14:36.133215 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:14:36.137313 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:14:36.140944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:14:36.144751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:14:36.148266 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:14:36.156373 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:14:36.163797 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:14:36.167374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:14:36.174616 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:14:36.178458 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:14:36.185852 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:14:36.189297 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:14:36.197311 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:14:36.200824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:14:36.208360 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:14:36.212260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:14:36.215505 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:14:36.223251 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:14:36.229646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:14:36.233250 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:14:36.236649 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:14:36.243160 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:14:36.246594 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:14:36.253410 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:14:36.257289 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:14:36.263933 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:14:36.267300 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:14:36.273833 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:14:36.277483 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:14:36.283887 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:14:36.287055 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:14:36.290715 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:14:36.297447 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:14:36.300590 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:14:36.304106 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:14:36.307503 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:14:36.314145 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:14:36.317466 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:14:36.320797 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:14:36.328119 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:14:36.330666 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:14:36.334324 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:14:36.337466 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:14:36.347724 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 13:14:36.354523 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:14:36.361070 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:14:36.367624 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:14:36.377826 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:14:36.380972 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:14:36.384257 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:14:36.390936 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:14:36.397627 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 13:14:36.401105 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:14:36.408209 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 13:14:36.411309 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:14:36.420925 [RTC]rtc_get_frequency_meter,154: input=15, output=773
471 13:14:36.430593 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 13:14:36.440442 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 13:14:36.449803 [RTC]rtc_get_frequency_meter,154: input=17, output=817
474 13:14:36.459357 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 13:14:36.462836 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 13:14:36.466103 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 13:14:36.473475 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 13:14:36.476701 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 13:14:36.479853 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 13:14:36.482901 ADC[4]: Raw value=902139 ID=7
481 13:14:36.486591 ADC[3]: Raw value=213179 ID=1
482 13:14:36.486666 RAM Code: 0x71
483 13:14:36.493159 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 13:14:36.496606 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 13:14:36.506695 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 13:14:36.513082 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 13:14:36.516559 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 13:14:36.519665 in-header: 03 07 00 00 08 00 00 00
489 13:14:36.523223 in-data: aa e4 47 04 13 02 00 00
490 13:14:36.523299 Chrome EC: UHEPI supported
491 13:14:36.529753 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 13:14:36.533331 in-header: 03 a9 00 00 08 00 00 00
493 13:14:36.536589 in-data: 84 60 60 08 00 00 00 00
494 13:14:36.539855 MRC: failed to locate region type 0.
495 13:14:36.547022 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 13:14:36.550006 DRAM-K: Running full calibration
497 13:14:36.556724 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 13:14:36.560374 header.status = 0x0
499 13:14:36.563790 header.version = 0x6 (expected: 0x6)
500 13:14:36.566905 header.size = 0xd00 (expected: 0xd00)
501 13:14:36.566970 header.flags = 0x0
502 13:14:36.573530 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 13:14:36.591299 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
504 13:14:36.597690 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 13:14:36.601225 dram_init: ddr_geometry: 2
506 13:14:36.604393 [EMI] MDL number = 2
507 13:14:36.604462 [EMI] Get MDL freq = 0
508 13:14:36.607920 dram_init: ddr_type: 0
509 13:14:36.607989 is_discrete_lpddr4: 1
510 13:14:36.611145 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 13:14:36.611209
512 13:14:36.611263
513 13:14:36.614549 [Bian_co] ETT version 0.0.0.1
514 13:14:36.621293 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 13:14:36.621359
516 13:14:36.624383 dramc_set_vcore_voltage set vcore to 650000
517 13:14:36.624442 Read voltage for 800, 4
518 13:14:36.627879 Vio18 = 0
519 13:14:36.627941 Vcore = 650000
520 13:14:36.627998 Vdram = 0
521 13:14:36.631001 Vddq = 0
522 13:14:36.631059 Vmddr = 0
523 13:14:36.634803 dram_init: config_dvfs: 1
524 13:14:36.637833 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 13:14:36.644780 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 13:14:36.648098 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 13:14:36.651689 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 13:14:36.654759 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 13:14:36.657936 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 13:14:36.661316 MEM_TYPE=3, freq_sel=18
531 13:14:36.664739 sv_algorithm_assistance_LP4_1600
532 13:14:36.667811 ============ PULL DRAM RESETB DOWN ============
533 13:14:36.671339 ========== PULL DRAM RESETB DOWN end =========
534 13:14:36.678119 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 13:14:36.681571 ===================================
536 13:14:36.681636 LPDDR4 DRAM CONFIGURATION
537 13:14:36.684792 ===================================
538 13:14:36.687874 EX_ROW_EN[0] = 0x0
539 13:14:36.691587 EX_ROW_EN[1] = 0x0
540 13:14:36.691652 LP4Y_EN = 0x0
541 13:14:36.694663 WORK_FSP = 0x0
542 13:14:36.694721 WL = 0x2
543 13:14:36.698089 RL = 0x2
544 13:14:36.698146 BL = 0x2
545 13:14:36.701561 RPST = 0x0
546 13:14:36.701626 RD_PRE = 0x0
547 13:14:36.704717 WR_PRE = 0x1
548 13:14:36.704862 WR_PST = 0x0
549 13:14:36.707953 DBI_WR = 0x0
550 13:14:36.708022 DBI_RD = 0x0
551 13:14:36.711459 OTF = 0x1
552 13:14:36.715061 ===================================
553 13:14:36.718282 ===================================
554 13:14:36.718385 ANA top config
555 13:14:36.721786 ===================================
556 13:14:36.725164 DLL_ASYNC_EN = 0
557 13:14:36.728542 ALL_SLAVE_EN = 1
558 13:14:36.728618 NEW_RANK_MODE = 1
559 13:14:36.731673 DLL_IDLE_MODE = 1
560 13:14:36.734811 LP45_APHY_COMB_EN = 1
561 13:14:36.738192 TX_ODT_DIS = 1
562 13:14:36.741453 NEW_8X_MODE = 1
563 13:14:36.745221 ===================================
564 13:14:36.745317 ===================================
565 13:14:36.748400 data_rate = 1600
566 13:14:36.752020 CKR = 1
567 13:14:36.754947 DQ_P2S_RATIO = 8
568 13:14:36.758382 ===================================
569 13:14:36.761603 CA_P2S_RATIO = 8
570 13:14:36.765306 DQ_CA_OPEN = 0
571 13:14:36.765370 DQ_SEMI_OPEN = 0
572 13:14:36.768137 CA_SEMI_OPEN = 0
573 13:14:36.772064 CA_FULL_RATE = 0
574 13:14:36.775389 DQ_CKDIV4_EN = 1
575 13:14:36.778278 CA_CKDIV4_EN = 1
576 13:14:36.781924 CA_PREDIV_EN = 0
577 13:14:36.781993 PH8_DLY = 0
578 13:14:36.784907 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 13:14:36.788855 DQ_AAMCK_DIV = 4
580 13:14:36.791661 CA_AAMCK_DIV = 4
581 13:14:36.795212 CA_ADMCK_DIV = 4
582 13:14:36.798547 DQ_TRACK_CA_EN = 0
583 13:14:36.798609 CA_PICK = 800
584 13:14:36.801727 CA_MCKIO = 800
585 13:14:36.805379 MCKIO_SEMI = 0
586 13:14:36.808453 PLL_FREQ = 3068
587 13:14:36.812141 DQ_UI_PI_RATIO = 32
588 13:14:36.815163 CA_UI_PI_RATIO = 0
589 13:14:36.818625 ===================================
590 13:14:36.822170 ===================================
591 13:14:36.822235 memory_type:LPDDR4
592 13:14:36.825583 GP_NUM : 10
593 13:14:36.828632 SRAM_EN : 1
594 13:14:36.828698 MD32_EN : 0
595 13:14:36.831956 ===================================
596 13:14:36.835506 [ANA_INIT] >>>>>>>>>>>>>>
597 13:14:36.838690 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 13:14:36.841867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 13:14:36.845548 ===================================
600 13:14:36.848696 data_rate = 1600,PCW = 0X7600
601 13:14:36.852213 ===================================
602 13:14:36.855276 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 13:14:36.859112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 13:14:36.865446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 13:14:36.868855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 13:14:36.872339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 13:14:36.875496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 13:14:36.878731 [ANA_INIT] flow start
609 13:14:36.882200 [ANA_INIT] PLL >>>>>>>>
610 13:14:36.882271 [ANA_INIT] PLL <<<<<<<<
611 13:14:36.885524 [ANA_INIT] MIDPI >>>>>>>>
612 13:14:36.889010 [ANA_INIT] MIDPI <<<<<<<<
613 13:14:36.889101 [ANA_INIT] DLL >>>>>>>>
614 13:14:36.892037 [ANA_INIT] flow end
615 13:14:36.895367 ============ LP4 DIFF to SE enter ============
616 13:14:36.898840 ============ LP4 DIFF to SE exit ============
617 13:14:36.901991 [ANA_INIT] <<<<<<<<<<<<<
618 13:14:36.905713 [Flow] Enable top DCM control >>>>>
619 13:14:36.908726 [Flow] Enable top DCM control <<<<<
620 13:14:36.912336 Enable DLL master slave shuffle
621 13:14:36.919022 ==============================================================
622 13:14:36.919097 Gating Mode config
623 13:14:36.925496 ==============================================================
624 13:14:36.925571 Config description:
625 13:14:36.935623 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 13:14:36.942594 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 13:14:36.949208 SELPH_MODE 0: By rank 1: By Phase
628 13:14:36.952167 ==============================================================
629 13:14:36.955364 GAT_TRACK_EN = 1
630 13:14:36.959029 RX_GATING_MODE = 2
631 13:14:36.962366 RX_GATING_TRACK_MODE = 2
632 13:14:36.965720 SELPH_MODE = 1
633 13:14:36.969223 PICG_EARLY_EN = 1
634 13:14:36.972945 VALID_LAT_VALUE = 1
635 13:14:36.975897 ==============================================================
636 13:14:36.978998 Enter into Gating configuration >>>>
637 13:14:36.982628 Exit from Gating configuration <<<<
638 13:14:36.985629 Enter into DVFS_PRE_config >>>>>
639 13:14:36.999197 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 13:14:37.002849 Exit from DVFS_PRE_config <<<<<
641 13:14:37.002914 Enter into PICG configuration >>>>
642 13:14:37.005782 Exit from PICG configuration <<<<
643 13:14:37.009288 [RX_INPUT] configuration >>>>>
644 13:14:37.012597 [RX_INPUT] configuration <<<<<
645 13:14:37.019049 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 13:14:37.022515 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 13:14:37.029230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 13:14:37.036022 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 13:14:37.042458 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 13:14:37.049204 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 13:14:37.052866 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 13:14:37.056100 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 13:14:37.059038 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 13:14:37.065966 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 13:14:37.069472 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 13:14:37.072459 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 13:14:37.076053 ===================================
658 13:14:37.079409 LPDDR4 DRAM CONFIGURATION
659 13:14:37.083074 ===================================
660 13:14:37.083150 EX_ROW_EN[0] = 0x0
661 13:14:37.085861 EX_ROW_EN[1] = 0x0
662 13:14:37.085925 LP4Y_EN = 0x0
663 13:14:37.089341 WORK_FSP = 0x0
664 13:14:37.092923 WL = 0x2
665 13:14:37.092987 RL = 0x2
666 13:14:37.096079 BL = 0x2
667 13:14:37.096146 RPST = 0x0
668 13:14:37.099990 RD_PRE = 0x0
669 13:14:37.100051 WR_PRE = 0x1
670 13:14:37.103061 WR_PST = 0x0
671 13:14:37.103129 DBI_WR = 0x0
672 13:14:37.106627 DBI_RD = 0x0
673 13:14:37.106702 OTF = 0x1
674 13:14:37.110596 ===================================
675 13:14:37.114567 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 13:14:37.117954 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 13:14:37.121437 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 13:14:37.125048 ===================================
679 13:14:37.129237 LPDDR4 DRAM CONFIGURATION
680 13:14:37.132881 ===================================
681 13:14:37.132951 EX_ROW_EN[0] = 0x10
682 13:14:37.136062 EX_ROW_EN[1] = 0x0
683 13:14:37.136129 LP4Y_EN = 0x0
684 13:14:37.139505 WORK_FSP = 0x0
685 13:14:37.139576 WL = 0x2
686 13:14:37.142686 RL = 0x2
687 13:14:37.142749 BL = 0x2
688 13:14:37.146169 RPST = 0x0
689 13:14:37.146227 RD_PRE = 0x0
690 13:14:37.149617 WR_PRE = 0x1
691 13:14:37.149679 WR_PST = 0x0
692 13:14:37.153340 DBI_WR = 0x0
693 13:14:37.153424 DBI_RD = 0x0
694 13:14:37.156277 OTF = 0x1
695 13:14:37.159869 ===================================
696 13:14:37.166339 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 13:14:37.169694 nWR fixed to 40
698 13:14:37.172866 [ModeRegInit_LP4] CH0 RK0
699 13:14:37.172934 [ModeRegInit_LP4] CH0 RK1
700 13:14:37.176266 [ModeRegInit_LP4] CH1 RK0
701 13:14:37.179570 [ModeRegInit_LP4] CH1 RK1
702 13:14:37.179632 match AC timing 13
703 13:14:37.186402 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 13:14:37.189648 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 13:14:37.192975 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 13:14:37.199562 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 13:14:37.203606 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 13:14:37.203671 [EMI DOE] emi_dcm 0
709 13:14:37.209966 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 13:14:37.210034 ==
711 13:14:37.213320 Dram Type= 6, Freq= 0, CH_0, rank 0
712 13:14:37.216624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 13:14:37.216685 ==
714 13:14:37.223109 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 13:14:37.226545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 13:14:37.237061 [CA 0] Center 38 (7~69) winsize 63
717 13:14:37.240243 [CA 1] Center 38 (7~69) winsize 63
718 13:14:37.243622 [CA 2] Center 35 (5~66) winsize 62
719 13:14:37.247011 [CA 3] Center 35 (5~66) winsize 62
720 13:14:37.250371 [CA 4] Center 34 (4~65) winsize 62
721 13:14:37.254110 [CA 5] Center 34 (3~65) winsize 63
722 13:14:37.254175
723 13:14:37.257631 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 13:14:37.257693
725 13:14:37.261641 [CATrainingPosCal] consider 1 rank data
726 13:14:37.264456 u2DelayCellTimex100 = 270/100 ps
727 13:14:37.268023 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
728 13:14:37.271227 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
729 13:14:37.274764 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
730 13:14:37.278018 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
731 13:14:37.281485 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
732 13:14:37.284773 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
733 13:14:37.288472
734 13:14:37.291507 CA PerBit enable=1, Macro0, CA PI delay=34
735 13:14:37.291575
736 13:14:37.295243 [CBTSetCACLKResult] CA Dly = 34
737 13:14:37.295311 CS Dly: 6 (0~37)
738 13:14:37.295367 ==
739 13:14:37.298237 Dram Type= 6, Freq= 0, CH_0, rank 1
740 13:14:37.301377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 13:14:37.301441 ==
742 13:14:37.308340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 13:14:37.314895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 13:14:37.323442 [CA 0] Center 38 (7~69) winsize 63
745 13:14:37.326872 [CA 1] Center 38 (7~69) winsize 63
746 13:14:37.330096 [CA 2] Center 36 (6~67) winsize 62
747 13:14:37.333768 [CA 3] Center 36 (5~67) winsize 63
748 13:14:37.336885 [CA 4] Center 35 (4~66) winsize 63
749 13:14:37.339821 [CA 5] Center 34 (4~65) winsize 62
750 13:14:37.339882
751 13:14:37.343303 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 13:14:37.343369
753 13:14:37.347079 [CATrainingPosCal] consider 2 rank data
754 13:14:37.350378 u2DelayCellTimex100 = 270/100 ps
755 13:14:37.353541 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 13:14:37.356876 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 13:14:37.363441 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 13:14:37.366996 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 13:14:37.370426 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 13:14:37.373624 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
761 13:14:37.373692
762 13:14:37.376919 CA PerBit enable=1, Macro0, CA PI delay=34
763 13:14:37.376985
764 13:14:37.380228 [CBTSetCACLKResult] CA Dly = 34
765 13:14:37.380289 CS Dly: 6 (0~38)
766 13:14:37.380340
767 13:14:37.383527 ----->DramcWriteLeveling(PI) begin...
768 13:14:37.383591 ==
769 13:14:37.387234 Dram Type= 6, Freq= 0, CH_0, rank 0
770 13:14:37.393502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 13:14:37.393571 ==
772 13:14:37.396861 Write leveling (Byte 0): 32 => 32
773 13:14:37.400379 Write leveling (Byte 1): 28 => 28
774 13:14:37.400444 DramcWriteLeveling(PI) end<-----
775 13:14:37.400501
776 13:14:37.403716 ==
777 13:14:37.407230 Dram Type= 6, Freq= 0, CH_0, rank 0
778 13:14:37.410367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 13:14:37.410464 ==
780 13:14:37.413742 [Gating] SW mode calibration
781 13:14:37.420277 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 13:14:37.424107 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 13:14:37.430281 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
784 13:14:37.433913 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
785 13:14:37.437325 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 13:14:37.443817 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 13:14:37.447193 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 13:14:37.450671 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:14:37.457393 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:14:37.460581 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:14:37.463674 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:14:37.467313 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:14:37.474038 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:14:37.477376 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:14:37.480843 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:14:37.487341 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:14:37.490601 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:14:37.494175 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:14:37.501058 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:14:37.504065 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
801 13:14:37.507563 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
802 13:14:37.514694 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:14:37.517945 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:14:37.520812 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:14:37.524463 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:14:37.530777 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:14:37.534487 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:14:37.537668 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
809 13:14:37.544362 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
810 13:14:37.547721 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
811 13:14:37.551105 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 13:14:37.557769 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 13:14:37.561195 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 13:14:37.564242 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:14:37.571232 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 13:14:37.574543 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
817 13:14:37.577879 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
818 13:14:37.581346 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
819 13:14:37.588464 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 13:14:37.591692 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 13:14:37.594728 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:14:37.601293 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:14:37.604737 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:14:37.608026 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
825 13:14:37.614417 0 11 8 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
826 13:14:37.618360 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
827 13:14:37.621295 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 13:14:37.627999 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 13:14:37.631028 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 13:14:37.634769 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:14:37.641084 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 13:14:37.644623 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 13:14:37.647927 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 13:14:37.654647 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 13:14:37.658017 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 13:14:37.661223 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:14:37.668123 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:14:37.671510 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:14:37.674731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:14:37.677930 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:14:37.685404 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:14:37.689041 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:14:37.692213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:14:37.695787 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:14:37.702388 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:14:37.705931 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:14:37.709043 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:14:37.716211 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 13:14:37.719055 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 13:14:37.722263 Total UI for P1: 0, mck2ui 16
851 13:14:37.725634 best dqsien dly found for B0: ( 0, 14, 4)
852 13:14:37.728959 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 13:14:37.732699 Total UI for P1: 0, mck2ui 16
854 13:14:37.736245 best dqsien dly found for B1: ( 0, 14, 8)
855 13:14:37.739011 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
856 13:14:37.742705 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
857 13:14:37.742776
858 13:14:37.749064 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 13:14:37.752382 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
860 13:14:37.752453 [Gating] SW calibration Done
861 13:14:37.752510 ==
862 13:14:37.756135 Dram Type= 6, Freq= 0, CH_0, rank 0
863 13:14:37.762494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 13:14:37.762567 ==
865 13:14:37.762628 RX Vref Scan: 0
866 13:14:37.762683
867 13:14:37.766138 RX Vref 0 -> 0, step: 1
868 13:14:37.766204
869 13:14:37.769403 RX Delay -130 -> 252, step: 16
870 13:14:37.772328 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 13:14:37.775840 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 13:14:37.779475 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 13:14:37.785807 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 13:14:37.789058 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
875 13:14:37.792952 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 13:14:37.796231 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 13:14:37.799323 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 13:14:37.806061 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 13:14:37.809352 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 13:14:37.813019 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 13:14:37.816413 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 13:14:37.819565 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
883 13:14:37.823222 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 13:14:37.829501 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 13:14:37.832972 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 13:14:37.833069 ==
887 13:14:37.836188 Dram Type= 6, Freq= 0, CH_0, rank 0
888 13:14:37.839401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 13:14:37.839470 ==
890 13:14:37.842973 DQS Delay:
891 13:14:37.843040 DQS0 = 0, DQS1 = 0
892 13:14:37.843096 DQM Delay:
893 13:14:37.846126 DQM0 = 90, DQM1 = 79
894 13:14:37.846184 DQ Delay:
895 13:14:37.849709 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
896 13:14:37.852864 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
897 13:14:37.856468 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 13:14:37.859418 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
899 13:14:37.859478
900 13:14:37.859530
901 13:14:37.859582 ==
902 13:14:37.862823 Dram Type= 6, Freq= 0, CH_0, rank 0
903 13:14:37.869458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 13:14:37.869523 ==
905 13:14:37.869581
906 13:14:37.869634
907 13:14:37.869683 TX Vref Scan disable
908 13:14:37.873222 == TX Byte 0 ==
909 13:14:37.876627 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
910 13:14:37.879752 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
911 13:14:37.883189 == TX Byte 1 ==
912 13:14:37.886872 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
913 13:14:37.890038 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
914 13:14:37.893589 ==
915 13:14:37.896824 Dram Type= 6, Freq= 0, CH_0, rank 0
916 13:14:37.899978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 13:14:37.900042 ==
918 13:14:37.912845 TX Vref=22, minBit 6, minWin=27, winSum=441
919 13:14:37.916097 TX Vref=24, minBit 13, minWin=27, winSum=450
920 13:14:37.919831 TX Vref=26, minBit 0, minWin=28, winSum=454
921 13:14:37.922953 TX Vref=28, minBit 8, minWin=27, winSum=454
922 13:14:37.926221 TX Vref=30, minBit 8, minWin=28, winSum=458
923 13:14:37.929441 TX Vref=32, minBit 3, minWin=28, winSum=455
924 13:14:37.936759 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
925 13:14:37.936826
926 13:14:37.939616 Final TX Range 1 Vref 30
927 13:14:37.939684
928 13:14:37.939740 ==
929 13:14:37.943087 Dram Type= 6, Freq= 0, CH_0, rank 0
930 13:14:37.946409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 13:14:37.946471 ==
932 13:14:37.946524
933 13:14:37.946576
934 13:14:37.949942 TX Vref Scan disable
935 13:14:37.953417 == TX Byte 0 ==
936 13:14:37.956631 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
937 13:14:37.959711 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
938 13:14:37.963344 == TX Byte 1 ==
939 13:14:37.966740 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
940 13:14:37.969802 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
941 13:14:37.969871
942 13:14:37.973105 [DATLAT]
943 13:14:37.973197 Freq=800, CH0 RK0
944 13:14:37.973252
945 13:14:37.977012 DATLAT Default: 0xa
946 13:14:37.977100 0, 0xFFFF, sum = 0
947 13:14:37.980170 1, 0xFFFF, sum = 0
948 13:14:37.980237 2, 0xFFFF, sum = 0
949 13:14:37.983609 3, 0xFFFF, sum = 0
950 13:14:37.983675 4, 0xFFFF, sum = 0
951 13:14:37.986827 5, 0xFFFF, sum = 0
952 13:14:37.986893 6, 0xFFFF, sum = 0
953 13:14:37.990282 7, 0xFFFF, sum = 0
954 13:14:37.990347 8, 0xFFFF, sum = 0
955 13:14:37.993271 9, 0x0, sum = 1
956 13:14:37.993333 10, 0x0, sum = 2
957 13:14:37.996673 11, 0x0, sum = 3
958 13:14:37.996730 12, 0x0, sum = 4
959 13:14:37.999843 best_step = 10
960 13:14:37.999900
961 13:14:37.999950 ==
962 13:14:38.003455 Dram Type= 6, Freq= 0, CH_0, rank 0
963 13:14:38.007099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 13:14:38.007163 ==
965 13:14:38.007215 RX Vref Scan: 1
966 13:14:38.010102
967 13:14:38.010163 Set Vref Range= 32 -> 127
968 13:14:38.010213
969 13:14:38.013434 RX Vref 32 -> 127, step: 1
970 13:14:38.013490
971 13:14:38.017040 RX Delay -95 -> 252, step: 8
972 13:14:38.017096
973 13:14:38.020038 Set Vref, RX VrefLevel [Byte0]: 32
974 13:14:38.023689 [Byte1]: 32
975 13:14:38.023746
976 13:14:38.026799 Set Vref, RX VrefLevel [Byte0]: 33
977 13:14:38.030155 [Byte1]: 33
978 13:14:38.030231
979 13:14:38.033625 Set Vref, RX VrefLevel [Byte0]: 34
980 13:14:38.036896 [Byte1]: 34
981 13:14:38.041011
982 13:14:38.041079 Set Vref, RX VrefLevel [Byte0]: 35
983 13:14:38.044037 [Byte1]: 35
984 13:14:38.048284
985 13:14:38.048371 Set Vref, RX VrefLevel [Byte0]: 36
986 13:14:38.054777 [Byte1]: 36
987 13:14:38.054847
988 13:14:38.058349 Set Vref, RX VrefLevel [Byte0]: 37
989 13:14:38.061305 [Byte1]: 37
990 13:14:38.061395
991 13:14:38.064705 Set Vref, RX VrefLevel [Byte0]: 38
992 13:14:38.068348 [Byte1]: 38
993 13:14:38.068407
994 13:14:38.071586 Set Vref, RX VrefLevel [Byte0]: 39
995 13:14:38.074844 [Byte1]: 39
996 13:14:38.078844
997 13:14:38.078908 Set Vref, RX VrefLevel [Byte0]: 40
998 13:14:38.082264 [Byte1]: 40
999 13:14:38.086199
1000 13:14:38.086260 Set Vref, RX VrefLevel [Byte0]: 41
1001 13:14:38.089831 [Byte1]: 41
1002 13:14:38.093775
1003 13:14:38.093837 Set Vref, RX VrefLevel [Byte0]: 42
1004 13:14:38.097304 [Byte1]: 42
1005 13:14:38.101483
1006 13:14:38.101547 Set Vref, RX VrefLevel [Byte0]: 43
1007 13:14:38.104874 [Byte1]: 43
1008 13:14:38.109202
1009 13:14:38.109291 Set Vref, RX VrefLevel [Byte0]: 44
1010 13:14:38.112553 [Byte1]: 44
1011 13:14:38.116789
1012 13:14:38.116849 Set Vref, RX VrefLevel [Byte0]: 45
1013 13:14:38.119918 [Byte1]: 45
1014 13:14:38.124497
1015 13:14:38.124555 Set Vref, RX VrefLevel [Byte0]: 46
1016 13:14:38.127732 [Byte1]: 46
1017 13:14:38.131822
1018 13:14:38.131881 Set Vref, RX VrefLevel [Byte0]: 47
1019 13:14:38.135152 [Byte1]: 47
1020 13:14:38.139473
1021 13:14:38.139534 Set Vref, RX VrefLevel [Byte0]: 48
1022 13:14:38.142591 [Byte1]: 48
1023 13:14:38.147011
1024 13:14:38.147068 Set Vref, RX VrefLevel [Byte0]: 49
1025 13:14:38.150126 [Byte1]: 49
1026 13:14:38.154658
1027 13:14:38.154717 Set Vref, RX VrefLevel [Byte0]: 50
1028 13:14:38.157939 [Byte1]: 50
1029 13:14:38.162605
1030 13:14:38.162671 Set Vref, RX VrefLevel [Byte0]: 51
1031 13:14:38.165662 [Byte1]: 51
1032 13:14:38.170116
1033 13:14:38.170178 Set Vref, RX VrefLevel [Byte0]: 52
1034 13:14:38.173113 [Byte1]: 52
1035 13:14:38.177318
1036 13:14:38.177380 Set Vref, RX VrefLevel [Byte0]: 53
1037 13:14:38.180505 [Byte1]: 53
1038 13:14:38.184988
1039 13:14:38.185047 Set Vref, RX VrefLevel [Byte0]: 54
1040 13:14:38.188225 [Byte1]: 54
1041 13:14:38.192595
1042 13:14:38.192655 Set Vref, RX VrefLevel [Byte0]: 55
1043 13:14:38.195990 [Byte1]: 55
1044 13:14:38.200186
1045 13:14:38.200243 Set Vref, RX VrefLevel [Byte0]: 56
1046 13:14:38.203869 [Byte1]: 56
1047 13:14:38.208041
1048 13:14:38.208107 Set Vref, RX VrefLevel [Byte0]: 57
1049 13:14:38.211317 [Byte1]: 57
1050 13:14:38.215437
1051 13:14:38.215495 Set Vref, RX VrefLevel [Byte0]: 58
1052 13:14:38.218767 [Byte1]: 58
1053 13:14:38.223044
1054 13:14:38.223122 Set Vref, RX VrefLevel [Byte0]: 59
1055 13:14:38.226712 [Byte1]: 59
1056 13:14:38.230476
1057 13:14:38.230533 Set Vref, RX VrefLevel [Byte0]: 60
1058 13:14:38.233805 [Byte1]: 60
1059 13:14:38.238094
1060 13:14:38.238153 Set Vref, RX VrefLevel [Byte0]: 61
1061 13:14:38.241426 [Byte1]: 61
1062 13:14:38.246303
1063 13:14:38.246360 Set Vref, RX VrefLevel [Byte0]: 62
1064 13:14:38.249220 [Byte1]: 62
1065 13:14:38.253666
1066 13:14:38.253728 Set Vref, RX VrefLevel [Byte0]: 63
1067 13:14:38.256789 [Byte1]: 63
1068 13:14:38.261378
1069 13:14:38.261437 Set Vref, RX VrefLevel [Byte0]: 64
1070 13:14:38.264181 [Byte1]: 64
1071 13:14:38.268718
1072 13:14:38.268778 Set Vref, RX VrefLevel [Byte0]: 65
1073 13:14:38.272189 [Byte1]: 65
1074 13:14:38.276379
1075 13:14:38.276455 Set Vref, RX VrefLevel [Byte0]: 66
1076 13:14:38.279399 [Byte1]: 66
1077 13:14:38.283997
1078 13:14:38.284072 Set Vref, RX VrefLevel [Byte0]: 67
1079 13:14:38.287215 [Byte1]: 67
1080 13:14:38.291593
1081 13:14:38.291667 Set Vref, RX VrefLevel [Byte0]: 68
1082 13:14:38.294957 [Byte1]: 68
1083 13:14:38.298843
1084 13:14:38.298918 Set Vref, RX VrefLevel [Byte0]: 69
1085 13:14:38.302266 [Byte1]: 69
1086 13:14:38.306673
1087 13:14:38.306747 Set Vref, RX VrefLevel [Byte0]: 70
1088 13:14:38.309901 [Byte1]: 70
1089 13:14:38.314346
1090 13:14:38.314423 Set Vref, RX VrefLevel [Byte0]: 71
1091 13:14:38.317671 [Byte1]: 71
1092 13:14:38.321774
1093 13:14:38.321849 Set Vref, RX VrefLevel [Byte0]: 72
1094 13:14:38.325334 [Byte1]: 72
1095 13:14:38.329503
1096 13:14:38.329578 Set Vref, RX VrefLevel [Byte0]: 73
1097 13:14:38.332583 [Byte1]: 73
1098 13:14:38.337114
1099 13:14:38.337195 Set Vref, RX VrefLevel [Byte0]: 74
1100 13:14:38.340472 [Byte1]: 74
1101 13:14:38.344750
1102 13:14:38.344824 Set Vref, RX VrefLevel [Byte0]: 75
1103 13:14:38.348251 [Byte1]: 75
1104 13:14:38.352212
1105 13:14:38.352283 Set Vref, RX VrefLevel [Byte0]: 76
1106 13:14:38.355432 [Byte1]: 76
1107 13:14:38.359665
1108 13:14:38.359729 Set Vref, RX VrefLevel [Byte0]: 77
1109 13:14:38.363137 [Byte1]: 77
1110 13:14:38.367165
1111 13:14:38.367223 Set Vref, RX VrefLevel [Byte0]: 78
1112 13:14:38.370695 [Byte1]: 78
1113 13:14:38.374811
1114 13:14:38.374871 Final RX Vref Byte 0 = 62 to rank0
1115 13:14:38.378290 Final RX Vref Byte 1 = 54 to rank0
1116 13:14:38.381593 Final RX Vref Byte 0 = 62 to rank1
1117 13:14:38.384827 Final RX Vref Byte 1 = 54 to rank1==
1118 13:14:38.388438 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 13:14:38.395033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 13:14:38.395098 ==
1121 13:14:38.395152 DQS Delay:
1122 13:14:38.395204 DQS0 = 0, DQS1 = 0
1123 13:14:38.398110 DQM Delay:
1124 13:14:38.398171 DQM0 = 93, DQM1 = 81
1125 13:14:38.401499 DQ Delay:
1126 13:14:38.404878 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1127 13:14:38.408628 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1128 13:14:38.411510 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1129 13:14:38.415136 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1130 13:14:38.415196
1131 13:14:38.415253
1132 13:14:38.421565 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1133 13:14:38.425004 CH0 RK0: MR19=606, MR18=3E39
1134 13:14:38.431629 CH0_RK0: MR19=0x606, MR18=0x3E39, DQSOSC=394, MR23=63, INC=95, DEC=63
1135 13:14:38.431692
1136 13:14:38.435310 ----->DramcWriteLeveling(PI) begin...
1137 13:14:38.435374 ==
1138 13:14:38.438496 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 13:14:38.441855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 13:14:38.441916 ==
1141 13:14:38.445054 Write leveling (Byte 0): 34 => 34
1142 13:14:38.448727 Write leveling (Byte 1): 28 => 28
1143 13:14:38.451685 DramcWriteLeveling(PI) end<-----
1144 13:14:38.451752
1145 13:14:38.451806 ==
1146 13:14:38.455162 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 13:14:38.458321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 13:14:38.458383 ==
1149 13:14:38.461865 [Gating] SW mode calibration
1150 13:14:38.468761 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 13:14:38.475403 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 13:14:38.478258 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 13:14:38.522431 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 13:14:38.523063 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:14:38.523306 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:14:38.523368 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:14:38.523604 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:14:38.523910 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:14:38.524281 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:14:38.525024 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:14:38.525082 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:14:38.525462 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:14:38.566457 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:14:38.566728 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:14:38.567247 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:14:38.567322 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:14:38.567755 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:14:38.568009 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:14:38.568082 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1170 13:14:38.568321 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:14:38.568382 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:14:38.568736 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:14:38.578172 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:14:38.578430 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:14:38.581006 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:14:38.584371 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:14:38.587883 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1178 13:14:38.591176 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
1179 13:14:38.597906 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 13:14:38.601422 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:14:38.604418 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 13:14:38.610985 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 13:14:38.614900 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 13:14:38.617665 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 13:14:38.624666 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1186 13:14:38.627708 0 10 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
1187 13:14:38.631312 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:14:38.637821 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:14:38.641028 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:14:38.644522 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:14:38.651329 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:14:38.654359 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:14:38.657847 0 11 4 | B1->B0 | 2626 3636 | 1 1 | (0 0) (0 0)
1194 13:14:38.664658 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1195 13:14:38.667844 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:14:38.671179 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:14:38.677742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:14:38.681296 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 13:14:38.684700 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 13:14:38.688017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 13:14:38.694716 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 13:14:38.698048 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 13:14:38.701316 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:14:38.708014 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:14:38.711460 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:14:38.714813 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:14:38.721273 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:14:38.724811 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:14:38.728241 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:14:38.734730 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:14:38.737709 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:14:38.741256 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:14:38.747812 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:14:38.751222 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:14:38.754300 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:14:38.761632 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:14:38.764473 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 13:14:38.767790 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 13:14:38.771263 Total UI for P1: 0, mck2ui 16
1220 13:14:38.774781 best dqsien dly found for B0: ( 0, 14, 4)
1221 13:14:38.778326 Total UI for P1: 0, mck2ui 16
1222 13:14:38.781540 best dqsien dly found for B1: ( 0, 14, 4)
1223 13:14:38.784857 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1224 13:14:38.788150 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1225 13:14:38.788226
1226 13:14:38.791872 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1227 13:14:38.794912 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1228 13:14:38.798038 [Gating] SW calibration Done
1229 13:14:38.798113 ==
1230 13:14:38.801706 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 13:14:38.805226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 13:14:38.808607 ==
1233 13:14:38.808706 RX Vref Scan: 0
1234 13:14:38.808799
1235 13:14:38.811932 RX Vref 0 -> 0, step: 1
1236 13:14:38.812064
1237 13:14:38.815161 RX Delay -130 -> 252, step: 16
1238 13:14:38.818412 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1239 13:14:38.821775 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1240 13:14:38.825072 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1241 13:14:38.828605 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1242 13:14:38.834955 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1243 13:14:38.838491 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1244 13:14:38.841638 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1245 13:14:38.844830 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1246 13:14:38.848004 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1247 13:14:38.851407 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1248 13:14:38.858304 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1249 13:14:38.861655 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1250 13:14:38.865413 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1251 13:14:38.868545 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1252 13:14:38.875161 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1253 13:14:38.878389 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1254 13:14:38.878464 ==
1255 13:14:38.881882 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 13:14:38.884960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 13:14:38.885036 ==
1258 13:14:38.885095 DQS Delay:
1259 13:14:38.888239 DQS0 = 0, DQS1 = 0
1260 13:14:38.888314 DQM Delay:
1261 13:14:38.891848 DQM0 = 87, DQM1 = 80
1262 13:14:38.891922 DQ Delay:
1263 13:14:38.895083 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1264 13:14:38.898456 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1265 13:14:38.901732 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1266 13:14:38.905116 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1267 13:14:38.905229
1268 13:14:38.905288
1269 13:14:38.905343 ==
1270 13:14:38.908411 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 13:14:38.912022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 13:14:38.912098 ==
1273 13:14:38.914972
1274 13:14:38.915047
1275 13:14:38.915105 TX Vref Scan disable
1276 13:14:38.918468 == TX Byte 0 ==
1277 13:14:38.921676 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1278 13:14:38.925478 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1279 13:14:38.928667 == TX Byte 1 ==
1280 13:14:38.932067 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1281 13:14:38.935057 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1282 13:14:38.935132 ==
1283 13:14:38.938941 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 13:14:38.945121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 13:14:38.945234 ==
1286 13:14:38.957862 TX Vref=22, minBit 3, minWin=27, winSum=446
1287 13:14:38.961343 TX Vref=24, minBit 8, minWin=27, winSum=448
1288 13:14:38.964790 TX Vref=26, minBit 8, minWin=27, winSum=452
1289 13:14:38.968076 TX Vref=28, minBit 8, minWin=27, winSum=456
1290 13:14:38.971662 TX Vref=30, minBit 8, minWin=27, winSum=456
1291 13:14:38.974458 TX Vref=32, minBit 8, minWin=28, winSum=458
1292 13:14:38.981436 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1293 13:14:38.981511
1294 13:14:38.984798 Final TX Range 1 Vref 32
1295 13:14:38.984873
1296 13:14:38.984932 ==
1297 13:14:38.988348 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 13:14:38.991256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 13:14:38.991332 ==
1300 13:14:38.991403
1301 13:14:38.994683
1302 13:14:38.994757 TX Vref Scan disable
1303 13:14:38.997860 == TX Byte 0 ==
1304 13:14:39.000975 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1305 13:14:39.004586 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1306 13:14:39.008008 == TX Byte 1 ==
1307 13:14:39.011116 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1308 13:14:39.014585 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1309 13:14:39.018088
1310 13:14:39.018162 [DATLAT]
1311 13:14:39.018220 Freq=800, CH0 RK1
1312 13:14:39.018275
1313 13:14:39.021249 DATLAT Default: 0xa
1314 13:14:39.021323 0, 0xFFFF, sum = 0
1315 13:14:39.024846 1, 0xFFFF, sum = 0
1316 13:14:39.024920 2, 0xFFFF, sum = 0
1317 13:14:39.027781 3, 0xFFFF, sum = 0
1318 13:14:39.027856 4, 0xFFFF, sum = 0
1319 13:14:39.031491 5, 0xFFFF, sum = 0
1320 13:14:39.031566 6, 0xFFFF, sum = 0
1321 13:14:39.034719 7, 0xFFFF, sum = 0
1322 13:14:39.037991 8, 0xFFFF, sum = 0
1323 13:14:39.038066 9, 0x0, sum = 1
1324 13:14:39.038125 10, 0x0, sum = 2
1325 13:14:39.041014 11, 0x0, sum = 3
1326 13:14:39.041112 12, 0x0, sum = 4
1327 13:14:39.044497 best_step = 10
1328 13:14:39.044571
1329 13:14:39.044629 ==
1330 13:14:39.048235 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 13:14:39.051314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 13:14:39.051390 ==
1333 13:14:39.054869 RX Vref Scan: 0
1334 13:14:39.054944
1335 13:14:39.055002 RX Vref 0 -> 0, step: 1
1336 13:14:39.055056
1337 13:14:39.058120 RX Delay -95 -> 252, step: 8
1338 13:14:39.064485 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1339 13:14:39.068151 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1340 13:14:39.071200 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1341 13:14:39.074736 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1342 13:14:39.077888 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1343 13:14:39.084951 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1344 13:14:39.088070 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1345 13:14:39.091409 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1346 13:14:39.094654 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1347 13:14:39.097971 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1348 13:14:39.104766 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1349 13:14:39.107840 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1350 13:14:39.111529 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1351 13:14:39.114971 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1352 13:14:39.118614 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1353 13:14:39.124993 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1354 13:14:39.125068 ==
1355 13:14:39.128149 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 13:14:39.131442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 13:14:39.131517 ==
1358 13:14:39.131575 DQS Delay:
1359 13:14:39.134681 DQS0 = 0, DQS1 = 0
1360 13:14:39.134756 DQM Delay:
1361 13:14:39.138350 DQM0 = 90, DQM1 = 82
1362 13:14:39.138425 DQ Delay:
1363 13:14:39.141468 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1364 13:14:39.144777 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1365 13:14:39.148077 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
1366 13:14:39.151334 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1367 13:14:39.151410
1368 13:14:39.151468
1369 13:14:39.158241 [DQSOSCAuto] RK1, (LSB)MR18= 0x431d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1370 13:14:39.161452 CH0 RK1: MR19=606, MR18=431D
1371 13:14:39.168391 CH0_RK1: MR19=0x606, MR18=0x431D, DQSOSC=393, MR23=63, INC=95, DEC=63
1372 13:14:39.171813 [RxdqsGatingPostProcess] freq 800
1373 13:14:39.178537 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 13:14:39.178614 Pre-setting of DQS Precalculation
1375 13:14:39.184939 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 13:14:39.185016 ==
1377 13:14:39.188283 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 13:14:39.191678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 13:14:39.191754 ==
1380 13:14:39.198236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 13:14:39.204905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 13:14:39.213223 [CA 0] Center 36 (6~67) winsize 62
1383 13:14:39.216285 [CA 1] Center 37 (6~68) winsize 63
1384 13:14:39.219580 [CA 2] Center 35 (5~65) winsize 61
1385 13:14:39.223327 [CA 3] Center 34 (4~65) winsize 62
1386 13:14:39.226734 [CA 4] Center 34 (4~65) winsize 62
1387 13:14:39.229762 [CA 5] Center 34 (4~65) winsize 62
1388 13:14:39.229838
1389 13:14:39.232880 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1390 13:14:39.232955
1391 13:14:39.236547 [CATrainingPosCal] consider 1 rank data
1392 13:14:39.239648 u2DelayCellTimex100 = 270/100 ps
1393 13:14:39.243200 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 13:14:39.246323 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1395 13:14:39.253030 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1396 13:14:39.256443 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 13:14:39.260297 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 13:14:39.263280 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 13:14:39.263356
1400 13:14:39.266519 CA PerBit enable=1, Macro0, CA PI delay=34
1401 13:14:39.266595
1402 13:14:39.270001 [CBTSetCACLKResult] CA Dly = 34
1403 13:14:39.270077 CS Dly: 4 (0~35)
1404 13:14:39.270153 ==
1405 13:14:39.273496 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 13:14:39.279693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 13:14:39.279769 ==
1408 13:14:39.283119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 13:14:39.289970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 13:14:39.299313 [CA 0] Center 37 (7~68) winsize 62
1411 13:14:39.302502 [CA 1] Center 37 (6~68) winsize 63
1412 13:14:39.305992 [CA 2] Center 35 (5~66) winsize 62
1413 13:14:39.309293 [CA 3] Center 34 (4~65) winsize 62
1414 13:14:39.312741 [CA 4] Center 34 (4~65) winsize 62
1415 13:14:39.315945 [CA 5] Center 34 (4~64) winsize 61
1416 13:14:39.316021
1417 13:14:39.319456 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1418 13:14:39.319532
1419 13:14:39.322490 [CATrainingPosCal] consider 2 rank data
1420 13:14:39.326048 u2DelayCellTimex100 = 270/100 ps
1421 13:14:39.329150 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1422 13:14:39.332481 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1423 13:14:39.336226 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1424 13:14:39.342716 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 13:14:39.345976 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 13:14:39.349405 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 13:14:39.349481
1428 13:14:39.352541 CA PerBit enable=1, Macro0, CA PI delay=34
1429 13:14:39.352617
1430 13:14:39.356040 [CBTSetCACLKResult] CA Dly = 34
1431 13:14:39.356116 CS Dly: 5 (0~38)
1432 13:14:39.356176
1433 13:14:39.359258 ----->DramcWriteLeveling(PI) begin...
1434 13:14:39.359335 ==
1435 13:14:39.362741 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 13:14:39.369587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 13:14:39.369663 ==
1438 13:14:39.372644 Write leveling (Byte 0): 27 => 27
1439 13:14:39.376476 Write leveling (Byte 1): 29 => 29
1440 13:14:39.376571 DramcWriteLeveling(PI) end<-----
1441 13:14:39.376654
1442 13:14:39.379370 ==
1443 13:14:39.382622 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 13:14:39.385849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 13:14:39.385909 ==
1446 13:14:39.389370 [Gating] SW mode calibration
1447 13:14:39.396594 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 13:14:39.399521 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 13:14:39.406081 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 13:14:39.409442 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 13:14:39.413077 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:14:39.419194 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:14:39.422570 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:14:39.426150 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:14:39.432854 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:14:39.436220 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:14:39.439453 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:14:39.442846 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:14:39.449617 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:14:39.453171 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:14:39.456884 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:14:39.462933 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:14:39.466163 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:14:39.469820 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:14:39.476142 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 13:14:39.479658 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1467 13:14:39.482936 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:14:39.489823 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:14:39.492776 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:14:39.496351 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:14:39.502876 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:14:39.506185 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:14:39.509619 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:14:39.516267 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
1475 13:14:39.519654 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:14:39.523286 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:14:39.529721 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:14:39.532838 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 13:14:39.536352 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 13:14:39.539628 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 13:14:39.546333 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1482 13:14:39.549812 0 10 4 | B1->B0 | 2d2d 2f2f | 0 0 | (1 1) (0 0)
1483 13:14:39.552985 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:14:39.559813 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:14:39.562918 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:14:39.566227 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:14:39.572932 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:14:39.576323 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:14:39.579510 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:14:39.586374 0 11 4 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (1 1)
1491 13:14:39.589811 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:14:39.592999 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:14:39.599585 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:14:39.602821 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:14:39.606399 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:14:39.613472 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:14:39.616442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1498 13:14:39.620208 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:14:39.623212 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:14:39.629791 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:14:39.633066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:14:39.636557 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:14:39.643079 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:14:39.646910 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:14:39.650250 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:14:39.656466 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:14:39.660083 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:14:39.663337 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:14:39.670062 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:14:39.673325 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:14:39.676806 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:14:39.683416 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:14:39.686743 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:14:39.690120 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1515 13:14:39.693489 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1516 13:14:39.696853 Total UI for P1: 0, mck2ui 16
1517 13:14:39.700587 best dqsien dly found for B0: ( 0, 14, 4)
1518 13:14:39.706692 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 13:14:39.706782 Total UI for P1: 0, mck2ui 16
1520 13:14:39.714095 best dqsien dly found for B1: ( 0, 14, 6)
1521 13:14:39.717083 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1522 13:14:39.720683 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1523 13:14:39.720773
1524 13:14:39.723619 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1525 13:14:39.727088 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 13:14:39.730314 [Gating] SW calibration Done
1527 13:14:39.730393 ==
1528 13:14:39.733353 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 13:14:39.736656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 13:14:39.736750 ==
1531 13:14:39.740089 RX Vref Scan: 0
1532 13:14:39.740181
1533 13:14:39.740263 RX Vref 0 -> 0, step: 1
1534 13:14:39.740342
1535 13:14:39.743513 RX Delay -130 -> 252, step: 16
1536 13:14:39.746889 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1537 13:14:39.753620 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 13:14:39.757445 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 13:14:39.760342 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 13:14:39.763885 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1541 13:14:39.766754 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1542 13:14:39.773651 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1543 13:14:39.777059 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 13:14:39.780902 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 13:14:39.783728 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 13:14:39.787102 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1547 13:14:39.790741 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1548 13:14:39.797358 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 13:14:39.800682 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 13:14:39.803810 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 13:14:39.807542 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1552 13:14:39.807627 ==
1553 13:14:39.810743 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 13:14:39.817372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 13:14:39.817438 ==
1556 13:14:39.817499 DQS Delay:
1557 13:14:39.820882 DQS0 = 0, DQS1 = 0
1558 13:14:39.820977 DQM Delay:
1559 13:14:39.821059 DQM0 = 93, DQM1 = 87
1560 13:14:39.823948 DQ Delay:
1561 13:14:39.827449 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1562 13:14:39.830628 DQ4 =85, DQ5 =101, DQ6 =109, DQ7 =93
1563 13:14:39.833960 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1564 13:14:39.837528 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1565 13:14:39.837593
1566 13:14:39.837646
1567 13:14:39.837718 ==
1568 13:14:39.840968 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 13:14:39.844075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 13:14:39.844161 ==
1571 13:14:39.844241
1572 13:14:39.844328
1573 13:14:39.847736 TX Vref Scan disable
1574 13:14:39.847799 == TX Byte 0 ==
1575 13:14:39.853983 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 13:14:39.857918 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 13:14:39.858015 == TX Byte 1 ==
1578 13:14:39.864267 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1579 13:14:39.867539 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1580 13:14:39.867657 ==
1581 13:14:39.871170 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 13:14:39.874137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 13:14:39.874235 ==
1584 13:14:39.888187 TX Vref=22, minBit 10, minWin=26, winSum=447
1585 13:14:39.891205 TX Vref=24, minBit 8, minWin=27, winSum=450
1586 13:14:39.894842 TX Vref=26, minBit 10, minWin=27, winSum=454
1587 13:14:39.897949 TX Vref=28, minBit 15, minWin=27, winSum=456
1588 13:14:39.901546 TX Vref=30, minBit 8, minWin=27, winSum=456
1589 13:14:39.908246 TX Vref=32, minBit 8, minWin=27, winSum=454
1590 13:14:39.911539 [TxChooseVref] Worse bit 15, Min win 27, Win sum 456, Final Vref 28
1591 13:14:39.911632
1592 13:14:39.914787 Final TX Range 1 Vref 28
1593 13:14:39.914864
1594 13:14:39.914922 ==
1595 13:14:39.917986 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 13:14:39.921384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 13:14:39.921461 ==
1598 13:14:39.925096
1599 13:14:39.925196
1600 13:14:39.925256 TX Vref Scan disable
1601 13:14:39.928409 == TX Byte 0 ==
1602 13:14:39.931854 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 13:14:39.935134 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 13:14:39.938571 == TX Byte 1 ==
1605 13:14:39.941869 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1606 13:14:39.945290 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1607 13:14:39.948645
1608 13:14:39.948719 [DATLAT]
1609 13:14:39.948777 Freq=800, CH1 RK0
1610 13:14:39.948832
1611 13:14:39.951676 DATLAT Default: 0xa
1612 13:14:39.951772 0, 0xFFFF, sum = 0
1613 13:14:39.955275 1, 0xFFFF, sum = 0
1614 13:14:39.955370 2, 0xFFFF, sum = 0
1615 13:14:39.958365 3, 0xFFFF, sum = 0
1616 13:14:39.958467 4, 0xFFFF, sum = 0
1617 13:14:39.961774 5, 0xFFFF, sum = 0
1618 13:14:39.961840 6, 0xFFFF, sum = 0
1619 13:14:39.965060 7, 0xFFFF, sum = 0
1620 13:14:39.965150 8, 0xFFFF, sum = 0
1621 13:14:39.968477 9, 0x0, sum = 1
1622 13:14:39.968538 10, 0x0, sum = 2
1623 13:14:39.972133 11, 0x0, sum = 3
1624 13:14:39.972193 12, 0x0, sum = 4
1625 13:14:39.975056 best_step = 10
1626 13:14:39.975114
1627 13:14:39.975165 ==
1628 13:14:39.978511 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 13:14:39.981660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 13:14:39.981719 ==
1631 13:14:39.985013 RX Vref Scan: 1
1632 13:14:39.985094
1633 13:14:39.985168 Set Vref Range= 32 -> 127
1634 13:14:39.985225
1635 13:14:39.988327 RX Vref 32 -> 127, step: 1
1636 13:14:39.988384
1637 13:14:39.991889 RX Delay -79 -> 252, step: 8
1638 13:14:39.991971
1639 13:14:39.995339 Set Vref, RX VrefLevel [Byte0]: 32
1640 13:14:39.998648 [Byte1]: 32
1641 13:14:39.998705
1642 13:14:40.001849 Set Vref, RX VrefLevel [Byte0]: 33
1643 13:14:40.005193 [Byte1]: 33
1644 13:14:40.008628
1645 13:14:40.008690 Set Vref, RX VrefLevel [Byte0]: 34
1646 13:14:40.012050 [Byte1]: 34
1647 13:14:40.016210
1648 13:14:40.016272 Set Vref, RX VrefLevel [Byte0]: 35
1649 13:14:40.019576 [Byte1]: 35
1650 13:14:40.023754
1651 13:14:40.023830 Set Vref, RX VrefLevel [Byte0]: 36
1652 13:14:40.026629 [Byte1]: 36
1653 13:14:40.031402
1654 13:14:40.031490 Set Vref, RX VrefLevel [Byte0]: 37
1655 13:14:40.034503 [Byte1]: 37
1656 13:14:40.038706
1657 13:14:40.038783 Set Vref, RX VrefLevel [Byte0]: 38
1658 13:14:40.042381 [Byte1]: 38
1659 13:14:40.046093
1660 13:14:40.046187 Set Vref, RX VrefLevel [Byte0]: 39
1661 13:14:40.049745 [Byte1]: 39
1662 13:14:40.053775
1663 13:14:40.053844 Set Vref, RX VrefLevel [Byte0]: 40
1664 13:14:40.057432 [Byte1]: 40
1665 13:14:40.061537
1666 13:14:40.061610 Set Vref, RX VrefLevel [Byte0]: 41
1667 13:14:40.065009 [Byte1]: 41
1668 13:14:40.068835
1669 13:14:40.068901 Set Vref, RX VrefLevel [Byte0]: 42
1670 13:14:40.072150 [Byte1]: 42
1671 13:14:40.076758
1672 13:14:40.076857 Set Vref, RX VrefLevel [Byte0]: 43
1673 13:14:40.079610 [Byte1]: 43
1674 13:14:40.084098
1675 13:14:40.084194 Set Vref, RX VrefLevel [Byte0]: 44
1676 13:14:40.087226 [Byte1]: 44
1677 13:14:40.091806
1678 13:14:40.091891 Set Vref, RX VrefLevel [Byte0]: 45
1679 13:14:40.095034 [Byte1]: 45
1680 13:14:40.099307
1681 13:14:40.099401 Set Vref, RX VrefLevel [Byte0]: 46
1682 13:14:40.102476 [Byte1]: 46
1683 13:14:40.106573
1684 13:14:40.106635 Set Vref, RX VrefLevel [Byte0]: 47
1685 13:14:40.110263 [Byte1]: 47
1686 13:14:40.114517
1687 13:14:40.114586 Set Vref, RX VrefLevel [Byte0]: 48
1688 13:14:40.117397 [Byte1]: 48
1689 13:14:40.121489
1690 13:14:40.121576 Set Vref, RX VrefLevel [Byte0]: 49
1691 13:14:40.125185 [Byte1]: 49
1692 13:14:40.129146
1693 13:14:40.129250 Set Vref, RX VrefLevel [Byte0]: 50
1694 13:14:40.132602 [Byte1]: 50
1695 13:14:40.136768
1696 13:14:40.136854 Set Vref, RX VrefLevel [Byte0]: 51
1697 13:14:40.140156 [Byte1]: 51
1698 13:14:40.144895
1699 13:14:40.144981 Set Vref, RX VrefLevel [Byte0]: 52
1700 13:14:40.147579 [Byte1]: 52
1701 13:14:40.151837
1702 13:14:40.151932 Set Vref, RX VrefLevel [Byte0]: 53
1703 13:14:40.155571 [Byte1]: 53
1704 13:14:40.159723
1705 13:14:40.159816 Set Vref, RX VrefLevel [Byte0]: 54
1706 13:14:40.162721 [Byte1]: 54
1707 13:14:40.167087
1708 13:14:40.167175 Set Vref, RX VrefLevel [Byte0]: 55
1709 13:14:40.170272 [Byte1]: 55
1710 13:14:40.174580
1711 13:14:40.174647 Set Vref, RX VrefLevel [Byte0]: 56
1712 13:14:40.178042 [Byte1]: 56
1713 13:14:40.182151
1714 13:14:40.182215 Set Vref, RX VrefLevel [Byte0]: 57
1715 13:14:40.185318 [Byte1]: 57
1716 13:14:40.189471
1717 13:14:40.189533 Set Vref, RX VrefLevel [Byte0]: 58
1718 13:14:40.193224 [Byte1]: 58
1719 13:14:40.197076
1720 13:14:40.197204 Set Vref, RX VrefLevel [Byte0]: 59
1721 13:14:40.200536 [Byte1]: 59
1722 13:14:40.204636
1723 13:14:40.204722 Set Vref, RX VrefLevel [Byte0]: 60
1724 13:14:40.208246 [Byte1]: 60
1725 13:14:40.212629
1726 13:14:40.212717 Set Vref, RX VrefLevel [Byte0]: 61
1727 13:14:40.215796 [Byte1]: 61
1728 13:14:40.219962
1729 13:14:40.220029 Set Vref, RX VrefLevel [Byte0]: 62
1730 13:14:40.222930 [Byte1]: 62
1731 13:14:40.227550
1732 13:14:40.227612 Set Vref, RX VrefLevel [Byte0]: 63
1733 13:14:40.230550 [Byte1]: 63
1734 13:14:40.234974
1735 13:14:40.235034 Set Vref, RX VrefLevel [Byte0]: 64
1736 13:14:40.238460 [Byte1]: 64
1737 13:14:40.242545
1738 13:14:40.242606 Set Vref, RX VrefLevel [Byte0]: 65
1739 13:14:40.246036 [Byte1]: 65
1740 13:14:40.249747
1741 13:14:40.249808 Set Vref, RX VrefLevel [Byte0]: 66
1742 13:14:40.253062 [Byte1]: 66
1743 13:14:40.257686
1744 13:14:40.257752 Set Vref, RX VrefLevel [Byte0]: 67
1745 13:14:40.261054 [Byte1]: 67
1746 13:14:40.264852
1747 13:14:40.264944 Set Vref, RX VrefLevel [Byte0]: 68
1748 13:14:40.268370 [Byte1]: 68
1749 13:14:40.272456
1750 13:14:40.272550 Set Vref, RX VrefLevel [Byte0]: 69
1751 13:14:40.275887 [Byte1]: 69
1752 13:14:40.280284
1753 13:14:40.280375 Set Vref, RX VrefLevel [Byte0]: 70
1754 13:14:40.283420 [Byte1]: 70
1755 13:14:40.287904
1756 13:14:40.287995 Set Vref, RX VrefLevel [Byte0]: 71
1757 13:14:40.291201 [Byte1]: 71
1758 13:14:40.295431
1759 13:14:40.295517 Set Vref, RX VrefLevel [Byte0]: 72
1760 13:14:40.298639 [Byte1]: 72
1761 13:14:40.302690
1762 13:14:40.302753 Set Vref, RX VrefLevel [Byte0]: 73
1763 13:14:40.306057 [Byte1]: 73
1764 13:14:40.310217
1765 13:14:40.310304 Final RX Vref Byte 0 = 51 to rank0
1766 13:14:40.313753 Final RX Vref Byte 1 = 62 to rank0
1767 13:14:40.317059 Final RX Vref Byte 0 = 51 to rank1
1768 13:14:40.320671 Final RX Vref Byte 1 = 62 to rank1==
1769 13:14:40.323674 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 13:14:40.326941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 13:14:40.330365 ==
1772 13:14:40.330459 DQS Delay:
1773 13:14:40.330520 DQS0 = 0, DQS1 = 0
1774 13:14:40.333681 DQM Delay:
1775 13:14:40.333741 DQM0 = 93, DQM1 = 83
1776 13:14:40.336840 DQ Delay:
1777 13:14:40.340402 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1778 13:14:40.340499 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1779 13:14:40.344044 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1780 13:14:40.347189 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1781 13:14:40.350288
1782 13:14:40.350351
1783 13:14:40.357113 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1784 13:14:40.360702 CH1 RK0: MR19=606, MR18=2F4D
1785 13:14:40.367303 CH1_RK0: MR19=0x606, MR18=0x2F4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1786 13:14:40.367394
1787 13:14:40.370442 ----->DramcWriteLeveling(PI) begin...
1788 13:14:40.370531 ==
1789 13:14:40.374043 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 13:14:40.377318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 13:14:40.377385 ==
1792 13:14:40.380639 Write leveling (Byte 0): 26 => 26
1793 13:14:40.384042 Write leveling (Byte 1): 31 => 31
1794 13:14:40.387164 DramcWriteLeveling(PI) end<-----
1795 13:14:40.387226
1796 13:14:40.387280 ==
1797 13:14:40.390565 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 13:14:40.394373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 13:14:40.394432 ==
1800 13:14:40.397475 [Gating] SW mode calibration
1801 13:14:40.404322 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 13:14:40.410986 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 13:14:40.414163 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1804 13:14:40.417703 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1805 13:14:40.424258 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 13:14:40.427231 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 13:14:40.430667 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 13:14:40.437267 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 13:14:40.440513 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:14:40.444087 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:14:40.447728 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:14:40.454100 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:14:40.457690 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:14:40.460850 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:14:40.467642 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:14:40.470746 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:14:40.474150 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:14:40.480709 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:14:40.484186 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1820 13:14:40.487332 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1821 13:14:40.494377 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:14:40.497630 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:14:40.501130 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:14:40.507564 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:14:40.510854 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:14:40.514265 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:14:40.517501 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:14:40.524249 0 9 4 | B1->B0 | 2525 2423 | 0 1 | (0 0) (0 0)
1829 13:14:40.528190 0 9 8 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
1830 13:14:40.530824 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 13:14:40.537468 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 13:14:40.540865 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 13:14:40.544597 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 13:14:40.550705 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 13:14:40.554154 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 13:14:40.557705 0 10 4 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (1 0)
1837 13:14:40.564179 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:14:40.567539 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:14:40.570844 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:14:40.577847 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:14:40.581209 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:14:40.584277 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:14:40.591207 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:14:40.594322 0 11 4 | B1->B0 | 3636 2828 | 0 0 | (1 1) (0 0)
1845 13:14:40.597763 0 11 8 | B1->B0 | 4545 4040 | 0 0 | (0 0) (1 1)
1846 13:14:40.601404 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 13:14:40.607928 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 13:14:40.611006 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 13:14:40.614850 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 13:14:40.621380 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 13:14:40.624655 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1852 13:14:40.628002 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1853 13:14:40.634744 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 13:14:40.638103 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 13:14:40.641035 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 13:14:40.647919 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 13:14:40.651359 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 13:14:40.654734 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:14:40.661390 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:14:40.664671 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:14:40.667854 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:14:40.674606 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:14:40.678141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:14:40.681328 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:14:40.685027 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:14:40.691466 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:14:40.694996 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:14:40.698453 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1869 13:14:40.705028 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 13:14:40.705119 Total UI for P1: 0, mck2ui 16
1871 13:14:40.711679 best dqsien dly found for B0: ( 0, 14, 4)
1872 13:14:40.711768 Total UI for P1: 0, mck2ui 16
1873 13:14:40.718374 best dqsien dly found for B1: ( 0, 14, 4)
1874 13:14:40.721498 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1875 13:14:40.724912 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1876 13:14:40.724973
1877 13:14:40.728243 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 13:14:40.731624 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1879 13:14:40.735214 [Gating] SW calibration Done
1880 13:14:40.735301 ==
1881 13:14:40.738439 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 13:14:40.741790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 13:14:40.741878 ==
1884 13:14:40.741958 RX Vref Scan: 0
1885 13:14:40.745623
1886 13:14:40.745684 RX Vref 0 -> 0, step: 1
1887 13:14:40.745741
1888 13:14:40.749020 RX Delay -130 -> 252, step: 16
1889 13:14:40.752085 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1890 13:14:40.755128 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1891 13:14:40.762079 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1892 13:14:40.765194 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1893 13:14:40.768815 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1894 13:14:40.771851 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1895 13:14:40.775362 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1896 13:14:40.782165 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1897 13:14:40.785196 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1898 13:14:40.788675 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1899 13:14:40.791981 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1900 13:14:40.795414 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1901 13:14:40.802138 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1902 13:14:40.805681 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1903 13:14:40.809100 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1904 13:14:40.812345 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1905 13:14:40.812408 ==
1906 13:14:40.815637 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 13:14:40.818854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 13:14:40.822640 ==
1909 13:14:40.822725 DQS Delay:
1910 13:14:40.822805 DQS0 = 0, DQS1 = 0
1911 13:14:40.825710 DQM Delay:
1912 13:14:40.825773 DQM0 = 89, DQM1 = 84
1913 13:14:40.828897 DQ Delay:
1914 13:14:40.832137 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1915 13:14:40.832200 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1916 13:14:40.835712 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1917 13:14:40.838956 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1918 13:14:40.842333
1919 13:14:40.842396
1920 13:14:40.842447 ==
1921 13:14:40.845760 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 13:14:40.848680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 13:14:40.848773 ==
1924 13:14:40.848854
1925 13:14:40.848931
1926 13:14:40.852421 TX Vref Scan disable
1927 13:14:40.852513 == TX Byte 0 ==
1928 13:14:40.858763 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1929 13:14:40.862233 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1930 13:14:40.862314 == TX Byte 1 ==
1931 13:14:40.868928 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1932 13:14:40.872262 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1933 13:14:40.872354 ==
1934 13:14:40.875508 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 13:14:40.879116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 13:14:40.879182 ==
1937 13:14:40.892987 TX Vref=22, minBit 8, minWin=27, winSum=449
1938 13:14:40.896039 TX Vref=24, minBit 8, minWin=27, winSum=453
1939 13:14:40.899346 TX Vref=26, minBit 13, minWin=27, winSum=456
1940 13:14:40.903512 TX Vref=28, minBit 8, minWin=28, winSum=460
1941 13:14:40.906123 TX Vref=30, minBit 8, minWin=28, winSum=461
1942 13:14:40.909344 TX Vref=32, minBit 8, minWin=28, winSum=460
1943 13:14:40.916064 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1944 13:14:40.916158
1945 13:14:40.919544 Final TX Range 1 Vref 30
1946 13:14:40.919631
1947 13:14:40.919714 ==
1948 13:14:40.922909 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 13:14:40.926236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 13:14:40.926390 ==
1951 13:14:40.926497
1952 13:14:40.929334
1953 13:14:40.929526 TX Vref Scan disable
1954 13:14:40.932833 == TX Byte 0 ==
1955 13:14:40.935967 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1956 13:14:40.939536 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1957 13:14:40.942792 == TX Byte 1 ==
1958 13:14:40.946368 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1959 13:14:40.949597 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1960 13:14:40.952960
1961 13:14:40.953038 [DATLAT]
1962 13:14:40.953097 Freq=800, CH1 RK1
1963 13:14:40.953193
1964 13:14:40.955879 DATLAT Default: 0xa
1965 13:14:40.955954 0, 0xFFFF, sum = 0
1966 13:14:40.959530 1, 0xFFFF, sum = 0
1967 13:14:40.959608 2, 0xFFFF, sum = 0
1968 13:14:40.963115 3, 0xFFFF, sum = 0
1969 13:14:40.963192 4, 0xFFFF, sum = 0
1970 13:14:40.966525 5, 0xFFFF, sum = 0
1971 13:14:40.969422 6, 0xFFFF, sum = 0
1972 13:14:40.969500 7, 0xFFFF, sum = 0
1973 13:14:40.973333 8, 0xFFFF, sum = 0
1974 13:14:40.973410 9, 0x0, sum = 1
1975 13:14:40.973473 10, 0x0, sum = 2
1976 13:14:40.976152 11, 0x0, sum = 3
1977 13:14:40.976228 12, 0x0, sum = 4
1978 13:14:40.979641 best_step = 10
1979 13:14:40.979716
1980 13:14:40.979775 ==
1981 13:14:40.983023 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 13:14:40.986574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 13:14:40.986651 ==
1984 13:14:40.989111 RX Vref Scan: 0
1985 13:14:40.989208
1986 13:14:40.989266 RX Vref 0 -> 0, step: 1
1987 13:14:40.989321
1988 13:14:40.992674 RX Delay -79 -> 252, step: 8
1989 13:14:40.999296 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
1990 13:14:41.002724 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
1991 13:14:41.005874 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1992 13:14:41.009663 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1993 13:14:41.013106 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
1994 13:14:41.019483 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1995 13:14:41.023209 iDelay=209, Bit 6, Center 100 (1 ~ 200) 200
1996 13:14:41.026159 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
1997 13:14:41.029757 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1998 13:14:41.032968 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1999 13:14:41.036118 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2000 13:14:41.043202 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2001 13:14:41.046467 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2002 13:14:41.049766 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2003 13:14:41.053064 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2004 13:14:41.056344 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2005 13:14:41.059770 ==
2006 13:14:41.063393 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 13:14:41.066574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 13:14:41.066644 ==
2009 13:14:41.066701 DQS Delay:
2010 13:14:41.069670 DQS0 = 0, DQS1 = 0
2011 13:14:41.069755 DQM Delay:
2012 13:14:41.072826 DQM0 = 92, DQM1 = 84
2013 13:14:41.072912 DQ Delay:
2014 13:14:41.076402 DQ0 =92, DQ1 =88, DQ2 =80, DQ3 =88
2015 13:14:41.080180 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =88
2016 13:14:41.082920 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2017 13:14:41.086722 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =92
2018 13:14:41.086787
2019 13:14:41.086841
2020 13:14:41.093085 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2021 13:14:41.096458 CH1 RK1: MR19=606, MR18=3D13
2022 13:14:41.103018 CH1_RK1: MR19=0x606, MR18=0x3D13, DQSOSC=394, MR23=63, INC=95, DEC=63
2023 13:14:41.106317 [RxdqsGatingPostProcess] freq 800
2024 13:14:41.109956 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2025 13:14:41.113018 Pre-setting of DQS Precalculation
2026 13:14:41.119804 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2027 13:14:41.126471 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2028 13:14:41.133016 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2029 13:14:41.133108
2030 13:14:41.133178
2031 13:14:41.136516 [Calibration Summary] 1600 Mbps
2032 13:14:41.136605 CH 0, Rank 0
2033 13:14:41.139786 SW Impedance : PASS
2034 13:14:41.143331 DUTY Scan : NO K
2035 13:14:41.143397 ZQ Calibration : PASS
2036 13:14:41.146839 Jitter Meter : NO K
2037 13:14:41.149585 CBT Training : PASS
2038 13:14:41.149675 Write leveling : PASS
2039 13:14:41.153071 RX DQS gating : PASS
2040 13:14:41.156465 RX DQ/DQS(RDDQC) : PASS
2041 13:14:41.156559 TX DQ/DQS : PASS
2042 13:14:41.159618 RX DATLAT : PASS
2043 13:14:41.163020 RX DQ/DQS(Engine): PASS
2044 13:14:41.163088 TX OE : NO K
2045 13:14:41.166407 All Pass.
2046 13:14:41.166471
2047 13:14:41.166530 CH 0, Rank 1
2048 13:14:41.169645 SW Impedance : PASS
2049 13:14:41.169735 DUTY Scan : NO K
2050 13:14:41.173108 ZQ Calibration : PASS
2051 13:14:41.176922 Jitter Meter : NO K
2052 13:14:41.177013 CBT Training : PASS
2053 13:14:41.179922 Write leveling : PASS
2054 13:14:41.179998 RX DQS gating : PASS
2055 13:14:41.183170 RX DQ/DQS(RDDQC) : PASS
2056 13:14:41.186740 TX DQ/DQS : PASS
2057 13:14:41.186816 RX DATLAT : PASS
2058 13:14:41.189838 RX DQ/DQS(Engine): PASS
2059 13:14:41.193368 TX OE : NO K
2060 13:14:41.193445 All Pass.
2061 13:14:41.193504
2062 13:14:41.193559 CH 1, Rank 0
2063 13:14:41.196586 SW Impedance : PASS
2064 13:14:41.199820 DUTY Scan : NO K
2065 13:14:41.199895 ZQ Calibration : PASS
2066 13:14:41.203244 Jitter Meter : NO K
2067 13:14:41.206691 CBT Training : PASS
2068 13:14:41.206767 Write leveling : PASS
2069 13:14:41.210086 RX DQS gating : PASS
2070 13:14:41.213555 RX DQ/DQS(RDDQC) : PASS
2071 13:14:41.213630 TX DQ/DQS : PASS
2072 13:14:41.216681 RX DATLAT : PASS
2073 13:14:41.216774 RX DQ/DQS(Engine): PASS
2074 13:14:41.220021 TX OE : NO K
2075 13:14:41.220097 All Pass.
2076 13:14:41.220156
2077 13:14:41.223573 CH 1, Rank 1
2078 13:14:41.223648 SW Impedance : PASS
2079 13:14:41.226885 DUTY Scan : NO K
2080 13:14:41.230196 ZQ Calibration : PASS
2081 13:14:41.230271 Jitter Meter : NO K
2082 13:14:41.233313 CBT Training : PASS
2083 13:14:41.237307 Write leveling : PASS
2084 13:14:41.237383 RX DQS gating : PASS
2085 13:14:41.240172 RX DQ/DQS(RDDQC) : PASS
2086 13:14:41.243705 TX DQ/DQS : PASS
2087 13:14:41.243781 RX DATLAT : PASS
2088 13:14:41.246894 RX DQ/DQS(Engine): PASS
2089 13:14:41.246976 TX OE : NO K
2090 13:14:41.250403 All Pass.
2091 13:14:41.250478
2092 13:14:41.250538 DramC Write-DBI off
2093 13:14:41.253367 PER_BANK_REFRESH: Hybrid Mode
2094 13:14:41.256894 TX_TRACKING: ON
2095 13:14:41.260065 [GetDramInforAfterCalByMRR] Vendor 6.
2096 13:14:41.263324 [GetDramInforAfterCalByMRR] Revision 606.
2097 13:14:41.267303 [GetDramInforAfterCalByMRR] Revision 2 0.
2098 13:14:41.267379 MR0 0x3b3b
2099 13:14:41.267437 MR8 0x5151
2100 13:14:41.273525 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 13:14:41.273601
2102 13:14:41.273661 MR0 0x3b3b
2103 13:14:41.273716 MR8 0x5151
2104 13:14:41.276770 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 13:14:41.276845
2106 13:14:41.286845 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2107 13:14:41.290676 [FAST_K] Save calibration result to emmc
2108 13:14:41.293532 [FAST_K] Save calibration result to emmc
2109 13:14:41.296982 dram_init: config_dvfs: 1
2110 13:14:41.300420 dramc_set_vcore_voltage set vcore to 662500
2111 13:14:41.303650 Read voltage for 1200, 2
2112 13:14:41.303726 Vio18 = 0
2113 13:14:41.303785 Vcore = 662500
2114 13:14:41.307157 Vdram = 0
2115 13:14:41.307232 Vddq = 0
2116 13:14:41.307291 Vmddr = 0
2117 13:14:41.313718 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2118 13:14:41.317077 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2119 13:14:41.320178 MEM_TYPE=3, freq_sel=15
2120 13:14:41.323500 sv_algorithm_assistance_LP4_1600
2121 13:14:41.327096 ============ PULL DRAM RESETB DOWN ============
2122 13:14:41.330291 ========== PULL DRAM RESETB DOWN end =========
2123 13:14:41.336825 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 13:14:41.340310 ===================================
2125 13:14:41.343830 LPDDR4 DRAM CONFIGURATION
2126 13:14:41.347187 ===================================
2127 13:14:41.347262 EX_ROW_EN[0] = 0x0
2128 13:14:41.350088 EX_ROW_EN[1] = 0x0
2129 13:14:41.350195 LP4Y_EN = 0x0
2130 13:14:41.353537 WORK_FSP = 0x0
2131 13:14:41.353612 WL = 0x4
2132 13:14:41.356948 RL = 0x4
2133 13:14:41.357023 BL = 0x2
2134 13:14:41.360347 RPST = 0x0
2135 13:14:41.360423 RD_PRE = 0x0
2136 13:14:41.363684 WR_PRE = 0x1
2137 13:14:41.363761 WR_PST = 0x0
2138 13:14:41.366870 DBI_WR = 0x0
2139 13:14:41.366945 DBI_RD = 0x0
2140 13:14:41.370203 OTF = 0x1
2141 13:14:41.373503 ===================================
2142 13:14:41.376924 ===================================
2143 13:14:41.376999 ANA top config
2144 13:14:41.380220 ===================================
2145 13:14:41.383603 DLL_ASYNC_EN = 0
2146 13:14:41.386905 ALL_SLAVE_EN = 0
2147 13:14:41.390716 NEW_RANK_MODE = 1
2148 13:14:41.390793 DLL_IDLE_MODE = 1
2149 13:14:41.393836 LP45_APHY_COMB_EN = 1
2150 13:14:41.397593 TX_ODT_DIS = 1
2151 13:14:41.400308 NEW_8X_MODE = 1
2152 13:14:41.403864 ===================================
2153 13:14:41.407229 ===================================
2154 13:14:41.410461 data_rate = 2400
2155 13:14:41.410536 CKR = 1
2156 13:14:41.413683 DQ_P2S_RATIO = 8
2157 13:14:41.416909 ===================================
2158 13:14:41.420409 CA_P2S_RATIO = 8
2159 13:14:41.423818 DQ_CA_OPEN = 0
2160 13:14:41.426819 DQ_SEMI_OPEN = 0
2161 13:14:41.426911 CA_SEMI_OPEN = 0
2162 13:14:41.430704 CA_FULL_RATE = 0
2163 13:14:41.433762 DQ_CKDIV4_EN = 0
2164 13:14:41.437332 CA_CKDIV4_EN = 0
2165 13:14:41.440556 CA_PREDIV_EN = 0
2166 13:14:41.443855 PH8_DLY = 17
2167 13:14:41.443945 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2168 13:14:41.447171 DQ_AAMCK_DIV = 4
2169 13:14:41.450632 CA_AAMCK_DIV = 4
2170 13:14:41.453816 CA_ADMCK_DIV = 4
2171 13:14:41.457175 DQ_TRACK_CA_EN = 0
2172 13:14:41.460455 CA_PICK = 1200
2173 13:14:41.464242 CA_MCKIO = 1200
2174 13:14:41.464313 MCKIO_SEMI = 0
2175 13:14:41.467172 PLL_FREQ = 2366
2176 13:14:41.470710 DQ_UI_PI_RATIO = 32
2177 13:14:41.474221 CA_UI_PI_RATIO = 0
2178 13:14:41.477494 ===================================
2179 13:14:41.480396 ===================================
2180 13:14:41.483799 memory_type:LPDDR4
2181 13:14:41.483862 GP_NUM : 10
2182 13:14:41.487558 SRAM_EN : 1
2183 13:14:41.487644 MD32_EN : 0
2184 13:14:41.490726 ===================================
2185 13:14:41.493772 [ANA_INIT] >>>>>>>>>>>>>>
2186 13:14:41.497180 <<<<<< [CONFIGURE PHASE]: ANA_TX
2187 13:14:41.500677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2188 13:14:41.503980 ===================================
2189 13:14:41.507271 data_rate = 2400,PCW = 0X5b00
2190 13:14:41.510871 ===================================
2191 13:14:41.513941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2192 13:14:41.517300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 13:14:41.524580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 13:14:41.527538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2195 13:14:41.534519 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2196 13:14:41.537936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2197 13:14:41.538011 [ANA_INIT] flow start
2198 13:14:41.540905 [ANA_INIT] PLL >>>>>>>>
2199 13:14:41.541001 [ANA_INIT] PLL <<<<<<<<
2200 13:14:41.544426 [ANA_INIT] MIDPI >>>>>>>>
2201 13:14:41.547762 [ANA_INIT] MIDPI <<<<<<<<
2202 13:14:41.550974 [ANA_INIT] DLL >>>>>>>>
2203 13:14:41.551064 [ANA_INIT] DLL <<<<<<<<
2204 13:14:41.554220 [ANA_INIT] flow end
2205 13:14:41.557799 ============ LP4 DIFF to SE enter ============
2206 13:14:41.561116 ============ LP4 DIFF to SE exit ============
2207 13:14:41.564961 [ANA_INIT] <<<<<<<<<<<<<
2208 13:14:41.567800 [Flow] Enable top DCM control >>>>>
2209 13:14:41.571012 [Flow] Enable top DCM control <<<<<
2210 13:14:41.574410 Enable DLL master slave shuffle
2211 13:14:41.577588 ==============================================================
2212 13:14:41.581091 Gating Mode config
2213 13:14:41.588057 ==============================================================
2214 13:14:41.588126 Config description:
2215 13:14:41.597904 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2216 13:14:41.604482 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2217 13:14:41.611268 SELPH_MODE 0: By rank 1: By Phase
2218 13:14:41.614438 ==============================================================
2219 13:14:41.617871 GAT_TRACK_EN = 1
2220 13:14:41.621294 RX_GATING_MODE = 2
2221 13:14:41.624402 RX_GATING_TRACK_MODE = 2
2222 13:14:41.628018 SELPH_MODE = 1
2223 13:14:41.631177 PICG_EARLY_EN = 1
2224 13:14:41.634653 VALID_LAT_VALUE = 1
2225 13:14:41.638266 ==============================================================
2226 13:14:41.641748 Enter into Gating configuration >>>>
2227 13:14:41.645120 Exit from Gating configuration <<<<
2228 13:14:41.648337 Enter into DVFS_PRE_config >>>>>
2229 13:14:41.658300 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2230 13:14:41.661348 Exit from DVFS_PRE_config <<<<<
2231 13:14:41.665055 Enter into PICG configuration >>>>
2232 13:14:41.668174 Exit from PICG configuration <<<<
2233 13:14:41.671397 [RX_INPUT] configuration >>>>>
2234 13:14:41.675002 [RX_INPUT] configuration <<<<<
2235 13:14:41.678219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2236 13:14:41.685023 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2237 13:14:41.691967 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 13:14:41.698307 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 13:14:41.704882 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 13:14:41.708631 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 13:14:41.715250 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2242 13:14:41.718625 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2243 13:14:41.721538 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2244 13:14:41.725061 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2245 13:14:41.731565 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2246 13:14:41.735045 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2247 13:14:41.738514 ===================================
2248 13:14:41.741797 LPDDR4 DRAM CONFIGURATION
2249 13:14:41.745132 ===================================
2250 13:14:41.745198 EX_ROW_EN[0] = 0x0
2251 13:14:41.748279 EX_ROW_EN[1] = 0x0
2252 13:14:41.748344 LP4Y_EN = 0x0
2253 13:14:41.751709 WORK_FSP = 0x0
2254 13:14:41.751773 WL = 0x4
2255 13:14:41.755230 RL = 0x4
2256 13:14:41.755318 BL = 0x2
2257 13:14:41.758173 RPST = 0x0
2258 13:14:41.758238 RD_PRE = 0x0
2259 13:14:41.761394 WR_PRE = 0x1
2260 13:14:41.761466 WR_PST = 0x0
2261 13:14:41.764877 DBI_WR = 0x0
2262 13:14:41.764938 DBI_RD = 0x0
2263 13:14:41.768306 OTF = 0x1
2264 13:14:41.771643 ===================================
2265 13:14:41.774991 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2266 13:14:41.778296 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2267 13:14:41.784937 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 13:14:41.788581 ===================================
2269 13:14:41.788646 LPDDR4 DRAM CONFIGURATION
2270 13:14:41.791784 ===================================
2271 13:14:41.795045 EX_ROW_EN[0] = 0x10
2272 13:14:41.798654 EX_ROW_EN[1] = 0x0
2273 13:14:41.798720 LP4Y_EN = 0x0
2274 13:14:41.801731 WORK_FSP = 0x0
2275 13:14:41.801795 WL = 0x4
2276 13:14:41.805213 RL = 0x4
2277 13:14:41.805299 BL = 0x2
2278 13:14:41.808246 RPST = 0x0
2279 13:14:41.808310 RD_PRE = 0x0
2280 13:14:41.812172 WR_PRE = 0x1
2281 13:14:41.812240 WR_PST = 0x0
2282 13:14:41.815267 DBI_WR = 0x0
2283 13:14:41.815354 DBI_RD = 0x0
2284 13:14:41.818488 OTF = 0x1
2285 13:14:41.821937 ===================================
2286 13:14:41.828491 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2287 13:14:41.828578 ==
2288 13:14:41.831903 Dram Type= 6, Freq= 0, CH_0, rank 0
2289 13:14:41.835592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2290 13:14:41.835679 ==
2291 13:14:41.838775 [Duty_Offset_Calibration]
2292 13:14:41.838837 B0:2 B1:0 CA:1
2293 13:14:41.838893
2294 13:14:41.841849 [DutyScan_Calibration_Flow] k_type=0
2295 13:14:41.851595
2296 13:14:41.851681 ==CLK 0==
2297 13:14:41.854548 Final CLK duty delay cell = -4
2298 13:14:41.857634 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2299 13:14:41.861188 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2300 13:14:41.864434 [-4] AVG Duty = 4953%(X100)
2301 13:14:41.864518
2302 13:14:41.867756 CH0 CLK Duty spec in!! Max-Min= 156%
2303 13:14:41.871320 [DutyScan_Calibration_Flow] ====Done====
2304 13:14:41.871381
2305 13:14:41.874401 [DutyScan_Calibration_Flow] k_type=1
2306 13:14:41.889887
2307 13:14:41.889958 ==DQS 0 ==
2308 13:14:41.892958 Final DQS duty delay cell = 0
2309 13:14:41.896486 [0] MAX Duty = 5187%(X100), DQS PI = 30
2310 13:14:41.899991 [0] MIN Duty = 4938%(X100), DQS PI = 0
2311 13:14:41.900059 [0] AVG Duty = 5062%(X100)
2312 13:14:41.903167
2313 13:14:41.903229 ==DQS 1 ==
2314 13:14:41.906614 Final DQS duty delay cell = -4
2315 13:14:41.909814 [-4] MAX Duty = 5124%(X100), DQS PI = 48
2316 13:14:41.913530 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2317 13:14:41.916754 [-4] AVG Duty = 5015%(X100)
2318 13:14:41.916842
2319 13:14:41.919821 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2320 13:14:41.919883
2321 13:14:41.923150 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2322 13:14:41.926760 [DutyScan_Calibration_Flow] ====Done====
2323 13:14:41.926826
2324 13:14:41.929958 [DutyScan_Calibration_Flow] k_type=3
2325 13:14:41.946577
2326 13:14:41.946644 ==DQM 0 ==
2327 13:14:41.950207 Final DQM duty delay cell = 0
2328 13:14:41.953303 [0] MAX Duty = 5062%(X100), DQS PI = 24
2329 13:14:41.956765 [0] MIN Duty = 4813%(X100), DQS PI = 2
2330 13:14:41.956858 [0] AVG Duty = 4937%(X100)
2331 13:14:41.960150
2332 13:14:41.960243 ==DQM 1 ==
2333 13:14:41.963574 Final DQM duty delay cell = 0
2334 13:14:41.966794 [0] MAX Duty = 5187%(X100), DQS PI = 46
2335 13:14:41.970234 [0] MIN Duty = 5000%(X100), DQS PI = 12
2336 13:14:41.970348 [0] AVG Duty = 5093%(X100)
2337 13:14:41.973683
2338 13:14:41.977252 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2339 13:14:41.977354
2340 13:14:41.980118 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2341 13:14:41.983316 [DutyScan_Calibration_Flow] ====Done====
2342 13:14:41.983407
2343 13:14:41.986409 [DutyScan_Calibration_Flow] k_type=2
2344 13:14:42.003140
2345 13:14:42.003233 ==DQ 0 ==
2346 13:14:42.007181 Final DQ duty delay cell = -4
2347 13:14:42.009953 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2348 13:14:42.013339 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2349 13:14:42.016318 [-4] AVG Duty = 4969%(X100)
2350 13:14:42.016388
2351 13:14:42.016445 ==DQ 1 ==
2352 13:14:42.019965 Final DQ duty delay cell = 4
2353 13:14:42.023353 [4] MAX Duty = 5093%(X100), DQS PI = 4
2354 13:14:42.026685 [4] MIN Duty = 5031%(X100), DQS PI = 0
2355 13:14:42.026771 [4] AVG Duty = 5062%(X100)
2356 13:14:42.026851
2357 13:14:42.030015 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2358 13:14:42.032983
2359 13:14:42.036361 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2360 13:14:42.039722 [DutyScan_Calibration_Flow] ====Done====
2361 13:14:42.039784 ==
2362 13:14:42.043038 Dram Type= 6, Freq= 0, CH_1, rank 0
2363 13:14:42.046438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 13:14:42.046534 ==
2365 13:14:42.050074 [Duty_Offset_Calibration]
2366 13:14:42.050142 B0:0 B1:-1 CA:2
2367 13:14:42.050198
2368 13:14:42.053115 [DutyScan_Calibration_Flow] k_type=0
2369 13:14:42.063170
2370 13:14:42.063237 ==CLK 0==
2371 13:14:42.066625 Final CLK duty delay cell = 0
2372 13:14:42.070059 [0] MAX Duty = 5156%(X100), DQS PI = 16
2373 13:14:42.073268 [0] MIN Duty = 4938%(X100), DQS PI = 44
2374 13:14:42.073330 [0] AVG Duty = 5047%(X100)
2375 13:14:42.076471
2376 13:14:42.076534 CH1 CLK Duty spec in!! Max-Min= 218%
2377 13:14:42.083211 [DutyScan_Calibration_Flow] ====Done====
2378 13:14:42.083300
2379 13:14:42.086770 [DutyScan_Calibration_Flow] k_type=1
2380 13:14:42.102529
2381 13:14:42.102596 ==DQS 0 ==
2382 13:14:42.105944 Final DQS duty delay cell = 0
2383 13:14:42.109192 [0] MAX Duty = 5093%(X100), DQS PI = 24
2384 13:14:42.112508 [0] MIN Duty = 4969%(X100), DQS PI = 0
2385 13:14:42.112597 [0] AVG Duty = 5031%(X100)
2386 13:14:42.116080
2387 13:14:42.116144 ==DQS 1 ==
2388 13:14:42.119255 Final DQS duty delay cell = 0
2389 13:14:42.122471 [0] MAX Duty = 5156%(X100), DQS PI = 0
2390 13:14:42.125842 [0] MIN Duty = 4844%(X100), DQS PI = 36
2391 13:14:42.125907 [0] AVG Duty = 5000%(X100)
2392 13:14:42.129251
2393 13:14:42.132450 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2394 13:14:42.132537
2395 13:14:42.135900 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2396 13:14:42.139670 [DutyScan_Calibration_Flow] ====Done====
2397 13:14:42.139733
2398 13:14:42.142521 [DutyScan_Calibration_Flow] k_type=3
2399 13:14:42.158786
2400 13:14:42.158856 ==DQM 0 ==
2401 13:14:42.162217 Final DQM duty delay cell = 4
2402 13:14:42.165925 [4] MAX Duty = 5093%(X100), DQS PI = 20
2403 13:14:42.169056 [4] MIN Duty = 4907%(X100), DQS PI = 46
2404 13:14:42.169149 [4] AVG Duty = 5000%(X100)
2405 13:14:42.172468
2406 13:14:42.172530 ==DQM 1 ==
2407 13:14:42.175944 Final DQM duty delay cell = -4
2408 13:14:42.179228 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2409 13:14:42.182256 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2410 13:14:42.185557 [-4] AVG Duty = 4875%(X100)
2411 13:14:42.185625
2412 13:14:42.189533 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2413 13:14:42.189595
2414 13:14:42.192623 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2415 13:14:42.195650 [DutyScan_Calibration_Flow] ====Done====
2416 13:14:42.195736
2417 13:14:42.198992 [DutyScan_Calibration_Flow] k_type=2
2418 13:14:42.215733
2419 13:14:42.215797 ==DQ 0 ==
2420 13:14:42.219400 Final DQ duty delay cell = 0
2421 13:14:42.222938 [0] MAX Duty = 5062%(X100), DQS PI = 22
2422 13:14:42.226353 [0] MIN Duty = 4938%(X100), DQS PI = 0
2423 13:14:42.226446 [0] AVG Duty = 5000%(X100)
2424 13:14:42.226529
2425 13:14:42.229479 ==DQ 1 ==
2426 13:14:42.233140 Final DQ duty delay cell = 0
2427 13:14:42.235942 [0] MAX Duty = 5031%(X100), DQS PI = 0
2428 13:14:42.239348 [0] MIN Duty = 4813%(X100), DQS PI = 34
2429 13:14:42.239414 [0] AVG Duty = 4922%(X100)
2430 13:14:42.239470
2431 13:14:42.242724 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2432 13:14:42.242789
2433 13:14:42.246078 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2434 13:14:42.252933 [DutyScan_Calibration_Flow] ====Done====
2435 13:14:42.256222 nWR fixed to 30
2436 13:14:42.256317 [ModeRegInit_LP4] CH0 RK0
2437 13:14:42.259670 [ModeRegInit_LP4] CH0 RK1
2438 13:14:42.262890 [ModeRegInit_LP4] CH1 RK0
2439 13:14:42.262957 [ModeRegInit_LP4] CH1 RK1
2440 13:14:42.266156 match AC timing 7
2441 13:14:42.269771 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2442 13:14:42.273353 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2443 13:14:42.279878 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2444 13:14:42.283485 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2445 13:14:42.286314 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2446 13:14:42.289992 ==
2447 13:14:42.293753 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 13:14:42.296523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 13:14:42.296618 ==
2450 13:14:42.300158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2451 13:14:42.306447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2452 13:14:42.316070 [CA 0] Center 38 (8~69) winsize 62
2453 13:14:42.319441 [CA 1] Center 38 (7~69) winsize 63
2454 13:14:42.322274 [CA 2] Center 35 (5~66) winsize 62
2455 13:14:42.325967 [CA 3] Center 35 (4~66) winsize 63
2456 13:14:42.328922 [CA 4] Center 34 (4~65) winsize 62
2457 13:14:42.332742 [CA 5] Center 33 (3~63) winsize 61
2458 13:14:42.332834
2459 13:14:42.335952 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2460 13:14:42.336042
2461 13:14:42.339268 [CATrainingPosCal] consider 1 rank data
2462 13:14:42.342567 u2DelayCellTimex100 = 270/100 ps
2463 13:14:42.345833 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2464 13:14:42.349099 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2465 13:14:42.355651 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2466 13:14:42.359471 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2467 13:14:42.362670 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2468 13:14:42.365806 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2469 13:14:42.365900
2470 13:14:42.369239 CA PerBit enable=1, Macro0, CA PI delay=33
2471 13:14:42.369302
2472 13:14:42.372564 [CBTSetCACLKResult] CA Dly = 33
2473 13:14:42.372626 CS Dly: 6 (0~37)
2474 13:14:42.372680 ==
2475 13:14:42.375909 Dram Type= 6, Freq= 0, CH_0, rank 1
2476 13:14:42.382759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 13:14:42.382856 ==
2478 13:14:42.386214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 13:14:42.392785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2480 13:14:42.401469 [CA 0] Center 39 (8~70) winsize 63
2481 13:14:42.404907 [CA 1] Center 38 (8~69) winsize 62
2482 13:14:42.408103 [CA 2] Center 35 (5~66) winsize 62
2483 13:14:42.411468 [CA 3] Center 35 (5~66) winsize 62
2484 13:14:42.414849 [CA 4] Center 34 (4~65) winsize 62
2485 13:14:42.418170 [CA 5] Center 34 (4~64) winsize 61
2486 13:14:42.418233
2487 13:14:42.421458 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2488 13:14:42.421525
2489 13:14:42.424899 [CATrainingPosCal] consider 2 rank data
2490 13:14:42.428458 u2DelayCellTimex100 = 270/100 ps
2491 13:14:42.431744 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2492 13:14:42.434810 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2493 13:14:42.441552 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 13:14:42.445003 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2495 13:14:42.448355 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2496 13:14:42.452044 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2497 13:14:42.452108
2498 13:14:42.454987 CA PerBit enable=1, Macro0, CA PI delay=33
2499 13:14:42.455050
2500 13:14:42.458238 [CBTSetCACLKResult] CA Dly = 33
2501 13:14:42.458300 CS Dly: 7 (0~39)
2502 13:14:42.458353
2503 13:14:42.461756 ----->DramcWriteLeveling(PI) begin...
2504 13:14:42.461818 ==
2505 13:14:42.464907 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 13:14:42.471765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 13:14:42.471837 ==
2508 13:14:42.474962 Write leveling (Byte 0): 35 => 35
2509 13:14:42.478680 Write leveling (Byte 1): 32 => 32
2510 13:14:42.478746 DramcWriteLeveling(PI) end<-----
2511 13:14:42.478803
2512 13:14:42.481711 ==
2513 13:14:42.485255 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 13:14:42.488301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 13:14:42.488365 ==
2516 13:14:42.491998 [Gating] SW mode calibration
2517 13:14:42.498247 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2518 13:14:42.501887 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2519 13:14:42.508738 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2520 13:14:42.511867 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
2521 13:14:42.515475 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 13:14:42.521824 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 13:14:42.525721 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 13:14:42.529051 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 13:14:42.535534 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2526 13:14:42.538962 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2527 13:14:42.541811 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2528 13:14:42.545586 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2529 13:14:42.552206 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 13:14:42.555855 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 13:14:42.558891 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 13:14:42.565768 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 13:14:42.568587 1 0 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2534 13:14:42.572184 1 0 28 | B1->B0 | 2524 4646 | 1 0 | (0 0) (0 0)
2535 13:14:42.578615 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2536 13:14:42.582174 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 13:14:42.585403 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 13:14:42.592235 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 13:14:42.595571 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 13:14:42.598916 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 13:14:42.605687 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 13:14:42.609301 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 13:14:42.612019 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 13:14:42.615818 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 13:14:42.622170 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 13:14:42.625624 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 13:14:42.628943 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 13:14:42.636033 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 13:14:42.639204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 13:14:42.642514 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 13:14:42.649022 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 13:14:42.652639 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:14:42.655566 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:14:42.662924 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:14:42.665849 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:14:42.669411 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:14:42.675961 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 13:14:42.678990 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2559 13:14:42.682388 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2560 13:14:42.685944 Total UI for P1: 0, mck2ui 16
2561 13:14:42.689407 best dqsien dly found for B0: ( 1, 3, 26)
2562 13:14:42.692656 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 13:14:42.695807 Total UI for P1: 0, mck2ui 16
2564 13:14:42.699340 best dqsien dly found for B1: ( 1, 3, 30)
2565 13:14:42.702695 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2566 13:14:42.706234 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2567 13:14:42.709862
2568 13:14:42.712814 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2569 13:14:42.716067 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2570 13:14:42.719156 [Gating] SW calibration Done
2571 13:14:42.719220 ==
2572 13:14:42.722857 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 13:14:42.726380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 13:14:42.726442 ==
2575 13:14:42.726495 RX Vref Scan: 0
2576 13:14:42.726546
2577 13:14:42.729789 RX Vref 0 -> 0, step: 1
2578 13:14:42.729852
2579 13:14:42.733019 RX Delay -40 -> 252, step: 8
2580 13:14:42.736019 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2581 13:14:42.739524 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2582 13:14:42.742788 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2583 13:14:42.749697 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2584 13:14:42.752853 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2585 13:14:42.756506 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2586 13:14:42.759851 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2587 13:14:42.763487 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2588 13:14:42.769665 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2589 13:14:42.773582 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2590 13:14:42.776419 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2591 13:14:42.779445 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2592 13:14:42.783082 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2593 13:14:42.790051 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2594 13:14:42.793158 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2595 13:14:42.796562 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2596 13:14:42.796648 ==
2597 13:14:42.800023 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 13:14:42.803639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 13:14:42.803725 ==
2600 13:14:42.806235 DQS Delay:
2601 13:14:42.806296 DQS0 = 0, DQS1 = 0
2602 13:14:42.809778 DQM Delay:
2603 13:14:42.809843 DQM0 = 123, DQM1 = 110
2604 13:14:42.809896 DQ Delay:
2605 13:14:42.813278 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2606 13:14:42.816518 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2607 13:14:42.823019 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2608 13:14:42.826762 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2609 13:14:42.826825
2610 13:14:42.826884
2611 13:14:42.826937 ==
2612 13:14:42.829923 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 13:14:42.832999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 13:14:42.833085 ==
2615 13:14:42.833203
2616 13:14:42.833283
2617 13:14:42.836378 TX Vref Scan disable
2618 13:14:42.836441 == TX Byte 0 ==
2619 13:14:42.843655 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2620 13:14:42.846440 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2621 13:14:42.846503 == TX Byte 1 ==
2622 13:14:42.853562 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2623 13:14:42.856757 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2624 13:14:42.856819 ==
2625 13:14:42.860485 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 13:14:42.863726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 13:14:42.863818 ==
2628 13:14:42.876000 TX Vref=22, minBit 3, minWin=23, winSum=399
2629 13:14:42.879591 TX Vref=24, minBit 0, minWin=24, winSum=412
2630 13:14:42.882628 TX Vref=26, minBit 0, minWin=25, winSum=419
2631 13:14:42.886245 TX Vref=28, minBit 3, minWin=25, winSum=418
2632 13:14:42.889444 TX Vref=30, minBit 3, minWin=25, winSum=415
2633 13:14:42.892896 TX Vref=32, minBit 3, minWin=25, winSum=418
2634 13:14:42.899496 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
2635 13:14:42.899566
2636 13:14:42.902909 Final TX Range 1 Vref 26
2637 13:14:42.902978
2638 13:14:42.903031 ==
2639 13:14:42.906456 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 13:14:42.909335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 13:14:42.909401 ==
2642 13:14:42.909455
2643 13:14:42.909506
2644 13:14:42.913025 TX Vref Scan disable
2645 13:14:42.916033 == TX Byte 0 ==
2646 13:14:42.919671 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2647 13:14:42.922987 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2648 13:14:42.926081 == TX Byte 1 ==
2649 13:14:42.929529 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2650 13:14:42.932873 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2651 13:14:42.932936
2652 13:14:42.936461 [DATLAT]
2653 13:14:42.936524 Freq=1200, CH0 RK0
2654 13:14:42.936577
2655 13:14:42.939813 DATLAT Default: 0xd
2656 13:14:42.939878 0, 0xFFFF, sum = 0
2657 13:14:42.942826 1, 0xFFFF, sum = 0
2658 13:14:42.942888 2, 0xFFFF, sum = 0
2659 13:14:42.946351 3, 0xFFFF, sum = 0
2660 13:14:42.946413 4, 0xFFFF, sum = 0
2661 13:14:42.949438 5, 0xFFFF, sum = 0
2662 13:14:42.949499 6, 0xFFFF, sum = 0
2663 13:14:42.952959 7, 0xFFFF, sum = 0
2664 13:14:42.953043 8, 0xFFFF, sum = 0
2665 13:14:42.956387 9, 0xFFFF, sum = 0
2666 13:14:42.956472 10, 0xFFFF, sum = 0
2667 13:14:42.959639 11, 0xFFFF, sum = 0
2668 13:14:42.959706 12, 0x0, sum = 1
2669 13:14:42.962967 13, 0x0, sum = 2
2670 13:14:42.963053 14, 0x0, sum = 3
2671 13:14:42.966676 15, 0x0, sum = 4
2672 13:14:42.966740 best_step = 13
2673 13:14:42.966793
2674 13:14:42.966870 ==
2675 13:14:42.969680 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 13:14:42.976406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 13:14:42.976469 ==
2678 13:14:42.976522 RX Vref Scan: 1
2679 13:14:42.976573
2680 13:14:42.979738 Set Vref Range= 32 -> 127
2681 13:14:42.979819
2682 13:14:42.983329 RX Vref 32 -> 127, step: 1
2683 13:14:42.983413
2684 13:14:42.983495 RX Delay -13 -> 252, step: 4
2685 13:14:42.986544
2686 13:14:42.986630 Set Vref, RX VrefLevel [Byte0]: 32
2687 13:14:42.989795 [Byte1]: 32
2688 13:14:42.994276
2689 13:14:42.994352 Set Vref, RX VrefLevel [Byte0]: 33
2690 13:14:42.998055 [Byte1]: 33
2691 13:14:43.002353
2692 13:14:43.002429 Set Vref, RX VrefLevel [Byte0]: 34
2693 13:14:43.005384 [Byte1]: 34
2694 13:14:43.010311
2695 13:14:43.010428 Set Vref, RX VrefLevel [Byte0]: 35
2696 13:14:43.013544 [Byte1]: 35
2697 13:14:43.018021
2698 13:14:43.018099 Set Vref, RX VrefLevel [Byte0]: 36
2699 13:14:43.021564 [Byte1]: 36
2700 13:14:43.026154
2701 13:14:43.026232 Set Vref, RX VrefLevel [Byte0]: 37
2702 13:14:43.029247 [Byte1]: 37
2703 13:14:43.033719
2704 13:14:43.033798 Set Vref, RX VrefLevel [Byte0]: 38
2705 13:14:43.037483 [Byte1]: 38
2706 13:14:43.041510
2707 13:14:43.041588 Set Vref, RX VrefLevel [Byte0]: 39
2708 13:14:43.044885 [Byte1]: 39
2709 13:14:43.049646
2710 13:14:43.049724 Set Vref, RX VrefLevel [Byte0]: 40
2711 13:14:43.052911 [Byte1]: 40
2712 13:14:43.057740
2713 13:14:43.057819 Set Vref, RX VrefLevel [Byte0]: 41
2714 13:14:43.060770 [Byte1]: 41
2715 13:14:43.065303
2716 13:14:43.065381 Set Vref, RX VrefLevel [Byte0]: 42
2717 13:14:43.068693 [Byte1]: 42
2718 13:14:43.073365
2719 13:14:43.073443 Set Vref, RX VrefLevel [Byte0]: 43
2720 13:14:43.076692 [Byte1]: 43
2721 13:14:43.081308
2722 13:14:43.081385 Set Vref, RX VrefLevel [Byte0]: 44
2723 13:14:43.084204 [Byte1]: 44
2724 13:14:43.089238
2725 13:14:43.089317 Set Vref, RX VrefLevel [Byte0]: 45
2726 13:14:43.092569 [Byte1]: 45
2727 13:14:43.097490
2728 13:14:43.097569 Set Vref, RX VrefLevel [Byte0]: 46
2729 13:14:43.100284 [Byte1]: 46
2730 13:14:43.104832
2731 13:14:43.104910 Set Vref, RX VrefLevel [Byte0]: 47
2732 13:14:43.108076 [Byte1]: 47
2733 13:14:43.112823
2734 13:14:43.112901 Set Vref, RX VrefLevel [Byte0]: 48
2735 13:14:43.116163 [Byte1]: 48
2736 13:14:43.120382
2737 13:14:43.120460 Set Vref, RX VrefLevel [Byte0]: 49
2738 13:14:43.124303 [Byte1]: 49
2739 13:14:43.128334
2740 13:14:43.128412 Set Vref, RX VrefLevel [Byte0]: 50
2741 13:14:43.131854 [Byte1]: 50
2742 13:14:43.136301
2743 13:14:43.136378 Set Vref, RX VrefLevel [Byte0]: 51
2744 13:14:43.139631 [Byte1]: 51
2745 13:14:43.144142
2746 13:14:43.144219 Set Vref, RX VrefLevel [Byte0]: 52
2747 13:14:43.147574 [Byte1]: 52
2748 13:14:43.152447
2749 13:14:43.152524 Set Vref, RX VrefLevel [Byte0]: 53
2750 13:14:43.155369 [Byte1]: 53
2751 13:14:43.160167
2752 13:14:43.160244 Set Vref, RX VrefLevel [Byte0]: 54
2753 13:14:43.163083 [Byte1]: 54
2754 13:14:43.167921
2755 13:14:43.167999 Set Vref, RX VrefLevel [Byte0]: 55
2756 13:14:43.171393 [Byte1]: 55
2757 13:14:43.176370
2758 13:14:43.176447 Set Vref, RX VrefLevel [Byte0]: 56
2759 13:14:43.179288 [Byte1]: 56
2760 13:14:43.183547
2761 13:14:43.183624 Set Vref, RX VrefLevel [Byte0]: 57
2762 13:14:43.187273 [Byte1]: 57
2763 13:14:43.191588
2764 13:14:43.191665 Set Vref, RX VrefLevel [Byte0]: 58
2765 13:14:43.194750 [Byte1]: 58
2766 13:14:43.199563
2767 13:14:43.199641 Set Vref, RX VrefLevel [Byte0]: 59
2768 13:14:43.206103 [Byte1]: 59
2769 13:14:43.206182
2770 13:14:43.209087 Set Vref, RX VrefLevel [Byte0]: 60
2771 13:14:43.212923 [Byte1]: 60
2772 13:14:43.213001
2773 13:14:43.216296 Set Vref, RX VrefLevel [Byte0]: 61
2774 13:14:43.219236 [Byte1]: 61
2775 13:14:43.223359
2776 13:14:43.223437 Set Vref, RX VrefLevel [Byte0]: 62
2777 13:14:43.226332 [Byte1]: 62
2778 13:14:43.231091
2779 13:14:43.231167 Set Vref, RX VrefLevel [Byte0]: 63
2780 13:14:43.234470 [Byte1]: 63
2781 13:14:43.239174
2782 13:14:43.239252 Set Vref, RX VrefLevel [Byte0]: 64
2783 13:14:43.242204 [Byte1]: 64
2784 13:14:43.246761
2785 13:14:43.246838 Set Vref, RX VrefLevel [Byte0]: 65
2786 13:14:43.249897 [Byte1]: 65
2787 13:14:43.254647
2788 13:14:43.254725 Set Vref, RX VrefLevel [Byte0]: 66
2789 13:14:43.257817 [Byte1]: 66
2790 13:14:43.262375
2791 13:14:43.262452 Set Vref, RX VrefLevel [Byte0]: 67
2792 13:14:43.265830 [Byte1]: 67
2793 13:14:43.270505
2794 13:14:43.270585 Set Vref, RX VrefLevel [Byte0]: 68
2795 13:14:43.274052 [Byte1]: 68
2796 13:14:43.278242
2797 13:14:43.278319 Set Vref, RX VrefLevel [Byte0]: 69
2798 13:14:43.281907 [Byte1]: 69
2799 13:14:43.286348
2800 13:14:43.286426 Set Vref, RX VrefLevel [Byte0]: 70
2801 13:14:43.289739 [Byte1]: 70
2802 13:14:43.294144
2803 13:14:43.294222 Final RX Vref Byte 0 = 60 to rank0
2804 13:14:43.297756 Final RX Vref Byte 1 = 49 to rank0
2805 13:14:43.300671 Final RX Vref Byte 0 = 60 to rank1
2806 13:14:43.304330 Final RX Vref Byte 1 = 49 to rank1==
2807 13:14:43.307491 Dram Type= 6, Freq= 0, CH_0, rank 0
2808 13:14:43.314148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 13:14:43.314228 ==
2810 13:14:43.314305 DQS Delay:
2811 13:14:43.314378 DQS0 = 0, DQS1 = 0
2812 13:14:43.317621 DQM Delay:
2813 13:14:43.317699 DQM0 = 123, DQM1 = 108
2814 13:14:43.320915 DQ Delay:
2815 13:14:43.324340 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2816 13:14:43.327781 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2817 13:14:43.330990 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =104
2818 13:14:43.334247 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =116
2819 13:14:43.334325
2820 13:14:43.334417
2821 13:14:43.341002 [DQSOSCAuto] RK0, (LSB)MR18= 0xc09, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2822 13:14:43.344426 CH0 RK0: MR19=404, MR18=C09
2823 13:14:43.350866 CH0_RK0: MR19=0x404, MR18=0xC09, DQSOSC=405, MR23=63, INC=39, DEC=26
2824 13:14:43.350946
2825 13:14:43.354414 ----->DramcWriteLeveling(PI) begin...
2826 13:14:43.354492 ==
2827 13:14:43.357675 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 13:14:43.360989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 13:14:43.361067 ==
2830 13:14:43.364509 Write leveling (Byte 0): 35 => 35
2831 13:14:43.367673 Write leveling (Byte 1): 29 => 29
2832 13:14:43.370965 DramcWriteLeveling(PI) end<-----
2833 13:14:43.371042
2834 13:14:43.371119 ==
2835 13:14:43.374485 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 13:14:43.378205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 13:14:43.380766 ==
2838 13:14:43.380844 [Gating] SW mode calibration
2839 13:14:43.387814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2840 13:14:43.394373 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2841 13:14:43.397687 0 15 0 | B1->B0 | 3232 3434 | 1 0 | (0 0) (0 0)
2842 13:14:43.404275 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 13:14:43.407610 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 13:14:43.411285 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 13:14:43.417677 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 13:14:43.421150 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 13:14:43.424571 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2848 13:14:43.430981 0 15 28 | B1->B0 | 2e2e 2c2c | 0 1 | (0 0) (1 0)
2849 13:14:43.434697 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 13:14:43.437732 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 13:14:43.441068 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 13:14:43.448196 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 13:14:43.451298 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 13:14:43.455003 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 13:14:43.461403 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2856 13:14:43.465073 1 0 28 | B1->B0 | 3e3e 4545 | 0 1 | (0 0) (0 0)
2857 13:14:43.467956 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 13:14:43.474559 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 13:14:43.478128 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 13:14:43.481163 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 13:14:43.488031 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 13:14:43.491477 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 13:14:43.494859 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 13:14:43.501413 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2865 13:14:43.504576 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:14:43.507931 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:14:43.511534 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:14:43.518005 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 13:14:43.521630 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 13:14:43.524883 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 13:14:43.531466 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 13:14:43.534652 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 13:14:43.538194 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 13:14:43.545240 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 13:14:43.548337 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 13:14:43.551613 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 13:14:43.558495 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 13:14:43.561582 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 13:14:43.564799 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 13:14:43.571398 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2881 13:14:43.574983 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 13:14:43.578542 Total UI for P1: 0, mck2ui 16
2883 13:14:43.581446 best dqsien dly found for B0: ( 1, 3, 28)
2884 13:14:43.585018 Total UI for P1: 0, mck2ui 16
2885 13:14:43.588420 best dqsien dly found for B1: ( 1, 3, 30)
2886 13:14:43.591465 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2887 13:14:43.595143 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2888 13:14:43.595221
2889 13:14:43.598149 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2890 13:14:43.601741 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2891 13:14:43.604827 [Gating] SW calibration Done
2892 13:14:43.604905 ==
2893 13:14:43.608389 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 13:14:43.611720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 13:14:43.611799 ==
2896 13:14:43.615025 RX Vref Scan: 0
2897 13:14:43.615103
2898 13:14:43.615180 RX Vref 0 -> 0, step: 1
2899 13:14:43.618282
2900 13:14:43.618360 RX Delay -40 -> 252, step: 8
2901 13:14:43.624941 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2902 13:14:43.628432 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2903 13:14:43.631578 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2904 13:14:43.634961 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2905 13:14:43.638607 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2906 13:14:43.641651 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2907 13:14:43.648463 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2908 13:14:43.651876 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2909 13:14:43.655004 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2910 13:14:43.658334 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2911 13:14:43.661996 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2912 13:14:43.668426 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2913 13:14:43.671572 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2914 13:14:43.675242 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2915 13:14:43.678206 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2916 13:14:43.681752 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2917 13:14:43.685264 ==
2918 13:14:43.688865 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 13:14:43.691697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 13:14:43.691774 ==
2921 13:14:43.691833 DQS Delay:
2922 13:14:43.695240 DQS0 = 0, DQS1 = 0
2923 13:14:43.695315 DQM Delay:
2924 13:14:43.699078 DQM0 = 120, DQM1 = 108
2925 13:14:43.699153 DQ Delay:
2926 13:14:43.702054 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2927 13:14:43.705082 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2928 13:14:43.708564 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2929 13:14:43.711995 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2930 13:14:43.712070
2931 13:14:43.712129
2932 13:14:43.712183 ==
2933 13:14:43.715353 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 13:14:43.718848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 13:14:43.722221 ==
2936 13:14:43.722296
2937 13:14:43.722355
2938 13:14:43.722410 TX Vref Scan disable
2939 13:14:43.725407 == TX Byte 0 ==
2940 13:14:43.728700 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2941 13:14:43.731908 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2942 13:14:43.735581 == TX Byte 1 ==
2943 13:14:43.738845 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2944 13:14:43.742223 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2945 13:14:43.742302 ==
2946 13:14:43.745423 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 13:14:43.752064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 13:14:43.752142 ==
2949 13:14:43.763901 TX Vref=22, minBit 4, minWin=24, winSum=412
2950 13:14:43.766989 TX Vref=24, minBit 4, minWin=24, winSum=420
2951 13:14:43.770354 TX Vref=26, minBit 1, minWin=24, winSum=422
2952 13:14:43.773834 TX Vref=28, minBit 3, minWin=25, winSum=424
2953 13:14:43.776963 TX Vref=30, minBit 2, minWin=25, winSum=428
2954 13:14:43.780383 TX Vref=32, minBit 3, minWin=25, winSum=422
2955 13:14:43.787091 [TxChooseVref] Worse bit 2, Min win 25, Win sum 428, Final Vref 30
2956 13:14:43.787170
2957 13:14:43.790508 Final TX Range 1 Vref 30
2958 13:14:43.790583
2959 13:14:43.790642 ==
2960 13:14:43.793835 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 13:14:43.796862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 13:14:43.796938 ==
2963 13:14:43.796998
2964 13:14:43.800201
2965 13:14:43.800276 TX Vref Scan disable
2966 13:14:43.803682 == TX Byte 0 ==
2967 13:14:43.806917 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2968 13:14:43.810046 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2969 13:14:43.813336 == TX Byte 1 ==
2970 13:14:43.816966 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2971 13:14:43.820164 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2972 13:14:43.820239
2973 13:14:43.823706 [DATLAT]
2974 13:14:43.823786 Freq=1200, CH0 RK1
2975 13:14:43.823963
2976 13:14:43.826820 DATLAT Default: 0xd
2977 13:14:43.826895 0, 0xFFFF, sum = 0
2978 13:14:43.830479 1, 0xFFFF, sum = 0
2979 13:14:43.830556 2, 0xFFFF, sum = 0
2980 13:14:43.833813 3, 0xFFFF, sum = 0
2981 13:14:43.833890 4, 0xFFFF, sum = 0
2982 13:14:43.836908 5, 0xFFFF, sum = 0
2983 13:14:43.836985 6, 0xFFFF, sum = 0
2984 13:14:43.840637 7, 0xFFFF, sum = 0
2985 13:14:43.840714 8, 0xFFFF, sum = 0
2986 13:14:43.843432 9, 0xFFFF, sum = 0
2987 13:14:43.847243 10, 0xFFFF, sum = 0
2988 13:14:43.847320 11, 0xFFFF, sum = 0
2989 13:14:43.850426 12, 0x0, sum = 1
2990 13:14:43.850503 13, 0x0, sum = 2
2991 13:14:43.850564 14, 0x0, sum = 3
2992 13:14:43.853894 15, 0x0, sum = 4
2993 13:14:43.853971 best_step = 13
2994 13:14:43.854029
2995 13:14:43.854083 ==
2996 13:14:43.857143 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 13:14:43.863548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 13:14:43.863625 ==
2999 13:14:43.863685 RX Vref Scan: 0
3000 13:14:43.863739
3001 13:14:43.866722 RX Vref 0 -> 0, step: 1
3002 13:14:43.866797
3003 13:14:43.870616 RX Delay -21 -> 252, step: 4
3004 13:14:43.873660 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3005 13:14:43.876997 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3006 13:14:43.883427 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3007 13:14:43.886898 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3008 13:14:43.890088 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3009 13:14:43.893473 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3010 13:14:43.896977 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3011 13:14:43.903815 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3012 13:14:43.907176 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3013 13:14:43.910261 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3014 13:14:43.913765 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3015 13:14:43.917260 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3016 13:14:43.923872 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3017 13:14:43.927259 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3018 13:14:43.930758 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3019 13:14:43.933696 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3020 13:14:43.933774 ==
3021 13:14:43.936997 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 13:14:43.940554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 13:14:43.943805 ==
3024 13:14:43.943882 DQS Delay:
3025 13:14:43.943960 DQS0 = 0, DQS1 = 0
3026 13:14:43.947090 DQM Delay:
3027 13:14:43.947168 DQM0 = 119, DQM1 = 108
3028 13:14:43.950493 DQ Delay:
3029 13:14:43.953802 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =116
3030 13:14:43.957141 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3031 13:14:43.960491 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3032 13:14:43.964034 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3033 13:14:43.964103
3034 13:14:43.964159
3035 13:14:43.970373 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3036 13:14:43.973820 CH0 RK1: MR19=403, MR18=13F9
3037 13:14:43.980467 CH0_RK1: MR19=0x403, MR18=0x13F9, DQSOSC=402, MR23=63, INC=40, DEC=27
3038 13:14:43.983972 [RxdqsGatingPostProcess] freq 1200
3039 13:14:43.990839 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3040 13:14:43.990918 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 13:14:43.993878 best DQS1 dly(2T, 0.5T) = (0, 11)
3042 13:14:43.997621 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 13:14:44.000549 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3044 13:14:44.003930 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 13:14:44.007506 best DQS1 dly(2T, 0.5T) = (0, 11)
3046 13:14:44.010793 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 13:14:44.014382 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3048 13:14:44.017359 Pre-setting of DQS Precalculation
3049 13:14:44.020602 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3050 13:14:44.024234 ==
3051 13:14:44.024297 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 13:14:44.030756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 13:14:44.030825 ==
3054 13:14:44.034050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3055 13:14:44.040670 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3056 13:14:44.049593 [CA 0] Center 37 (7~68) winsize 62
3057 13:14:44.053310 [CA 1] Center 37 (7~68) winsize 62
3058 13:14:44.056455 [CA 2] Center 35 (5~65) winsize 61
3059 13:14:44.059568 [CA 3] Center 34 (4~65) winsize 62
3060 13:14:44.063087 [CA 4] Center 34 (4~64) winsize 61
3061 13:14:44.066330 [CA 5] Center 33 (3~64) winsize 62
3062 13:14:44.066432
3063 13:14:44.069755 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3064 13:14:44.069831
3065 13:14:44.072924 [CATrainingPosCal] consider 1 rank data
3066 13:14:44.076655 u2DelayCellTimex100 = 270/100 ps
3067 13:14:44.079582 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3068 13:14:44.083233 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3069 13:14:44.090161 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3070 13:14:44.092884 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3071 13:14:44.096579 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3072 13:14:44.099484 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3073 13:14:44.099575
3074 13:14:44.102976 CA PerBit enable=1, Macro0, CA PI delay=33
3075 13:14:44.103067
3076 13:14:44.106613 [CBTSetCACLKResult] CA Dly = 33
3077 13:14:44.106701 CS Dly: 5 (0~36)
3078 13:14:44.106781 ==
3079 13:14:44.109653 Dram Type= 6, Freq= 0, CH_1, rank 1
3080 13:14:44.116258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 13:14:44.116351 ==
3082 13:14:44.119580 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 13:14:44.126259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3084 13:14:44.135429 [CA 0] Center 38 (8~68) winsize 61
3085 13:14:44.138724 [CA 1] Center 38 (7~69) winsize 63
3086 13:14:44.142412 [CA 2] Center 35 (5~66) winsize 62
3087 13:14:44.145279 [CA 3] Center 35 (5~65) winsize 61
3088 13:14:44.148474 [CA 4] Center 34 (4~64) winsize 61
3089 13:14:44.152246 [CA 5] Center 34 (4~64) winsize 61
3090 13:14:44.152311
3091 13:14:44.155468 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3092 13:14:44.155535
3093 13:14:44.158517 [CATrainingPosCal] consider 2 rank data
3094 13:14:44.161903 u2DelayCellTimex100 = 270/100 ps
3095 13:14:44.165191 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3096 13:14:44.171791 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3097 13:14:44.175289 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3098 13:14:44.178581 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3099 13:14:44.181674 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3100 13:14:44.185276 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3101 13:14:44.185366
3102 13:14:44.188674 CA PerBit enable=1, Macro0, CA PI delay=34
3103 13:14:44.188763
3104 13:14:44.191888 [CBTSetCACLKResult] CA Dly = 34
3105 13:14:44.191954 CS Dly: 6 (0~39)
3106 13:14:44.192009
3107 13:14:44.195237 ----->DramcWriteLeveling(PI) begin...
3108 13:14:44.198247 ==
3109 13:14:44.202076 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 13:14:44.205071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 13:14:44.205162 ==
3112 13:14:44.208892 Write leveling (Byte 0): 24 => 24
3113 13:14:44.212177 Write leveling (Byte 1): 28 => 28
3114 13:14:44.215440 DramcWriteLeveling(PI) end<-----
3115 13:14:44.215503
3116 13:14:44.215557 ==
3117 13:14:44.218357 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 13:14:44.222154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 13:14:44.222219 ==
3120 13:14:44.226015 [Gating] SW mode calibration
3121 13:14:44.231627 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3122 13:14:44.238755 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3123 13:14:44.241697 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 13:14:44.244895 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 13:14:44.248388 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 13:14:44.255240 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 13:14:44.258577 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 13:14:44.262234 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3129 13:14:44.268335 0 15 24 | B1->B0 | 2828 2525 | 0 0 | (1 0) (1 0)
3130 13:14:44.271665 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 13:14:44.274810 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 13:14:44.281603 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 13:14:44.285058 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 13:14:44.288586 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 13:14:44.294781 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 13:14:44.297971 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3137 13:14:44.301378 1 0 24 | B1->B0 | 4242 4444 | 1 0 | (0 0) (0 0)
3138 13:14:44.308104 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 13:14:44.311584 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 13:14:44.315064 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 13:14:44.321331 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 13:14:44.325192 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 13:14:44.328295 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 13:14:44.334827 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 13:14:44.338169 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3146 13:14:44.341482 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3147 13:14:44.348294 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:14:44.351390 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:14:44.354899 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:14:44.358168 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:14:44.364957 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 13:14:44.368351 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 13:14:44.371404 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 13:14:44.378218 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 13:14:44.381757 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 13:14:44.385022 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 13:14:44.391406 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 13:14:44.394905 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 13:14:44.398088 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 13:14:44.405045 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3161 13:14:44.408026 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3162 13:14:44.411693 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 13:14:44.414871 Total UI for P1: 0, mck2ui 16
3164 13:14:44.418034 best dqsien dly found for B0: ( 1, 3, 22)
3165 13:14:44.421636 Total UI for P1: 0, mck2ui 16
3166 13:14:44.424855 best dqsien dly found for B1: ( 1, 3, 24)
3167 13:14:44.428217 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3168 13:14:44.431829 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3169 13:14:44.431920
3170 13:14:44.438353 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3171 13:14:44.441349 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3172 13:14:44.441440 [Gating] SW calibration Done
3173 13:14:44.444567 ==
3174 13:14:44.448252 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 13:14:44.451307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 13:14:44.451374 ==
3177 13:14:44.451431 RX Vref Scan: 0
3178 13:14:44.451484
3179 13:14:44.454834 RX Vref 0 -> 0, step: 1
3180 13:14:44.454896
3181 13:14:44.457863 RX Delay -40 -> 252, step: 8
3182 13:14:44.461225 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3183 13:14:44.464812 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3184 13:14:44.471457 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3185 13:14:44.474743 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3186 13:14:44.477893 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3187 13:14:44.481637 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3188 13:14:44.484854 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3189 13:14:44.487851 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3190 13:14:44.494885 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3191 13:14:44.498331 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3192 13:14:44.501302 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3193 13:14:44.504456 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3194 13:14:44.507696 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3195 13:14:44.514343 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3196 13:14:44.517822 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3197 13:14:44.520795 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3198 13:14:44.520884 ==
3199 13:14:44.524466 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 13:14:44.527679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 13:14:44.531129 ==
3202 13:14:44.531195 DQS Delay:
3203 13:14:44.531250 DQS0 = 0, DQS1 = 0
3204 13:14:44.534198 DQM Delay:
3205 13:14:44.534290 DQM0 = 119, DQM1 = 113
3206 13:14:44.537464 DQ Delay:
3207 13:14:44.541082 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3208 13:14:44.544655 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3209 13:14:44.547498 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3210 13:14:44.550651 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3211 13:14:44.550718
3212 13:14:44.550774
3213 13:14:44.550826 ==
3214 13:14:44.554418 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 13:14:44.557622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 13:14:44.557689 ==
3217 13:14:44.557742
3218 13:14:44.557797
3219 13:14:44.560618 TX Vref Scan disable
3220 13:14:44.564228 == TX Byte 0 ==
3221 13:14:44.567587 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3222 13:14:44.571002 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3223 13:14:44.574190 == TX Byte 1 ==
3224 13:14:44.577541 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3225 13:14:44.580895 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3226 13:14:44.580979 ==
3227 13:14:44.584029 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 13:14:44.590775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 13:14:44.590846 ==
3230 13:14:44.600901 TX Vref=22, minBit 1, minWin=24, winSum=406
3231 13:14:44.604110 TX Vref=24, minBit 1, minWin=25, winSum=408
3232 13:14:44.607575 TX Vref=26, minBit 1, minWin=25, winSum=410
3233 13:14:44.610782 TX Vref=28, minBit 8, minWin=25, winSum=419
3234 13:14:44.614293 TX Vref=30, minBit 10, minWin=25, winSum=420
3235 13:14:44.620882 TX Vref=32, minBit 1, minWin=26, winSum=425
3236 13:14:44.624185 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 32
3237 13:14:44.624250
3238 13:14:44.627785 Final TX Range 1 Vref 32
3239 13:14:44.627873
3240 13:14:44.627953 ==
3241 13:14:44.630961 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 13:14:44.634070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 13:14:44.634158 ==
3244 13:14:44.637603
3245 13:14:44.637665
3246 13:14:44.637726 TX Vref Scan disable
3247 13:14:44.640752 == TX Byte 0 ==
3248 13:14:44.644102 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3249 13:14:44.647711 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3250 13:14:44.651124 == TX Byte 1 ==
3251 13:14:44.654338 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3252 13:14:44.657371 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3253 13:14:44.660694
3254 13:14:44.660785 [DATLAT]
3255 13:14:44.660867 Freq=1200, CH1 RK0
3256 13:14:44.660947
3257 13:14:44.664011 DATLAT Default: 0xd
3258 13:14:44.664095 0, 0xFFFF, sum = 0
3259 13:14:44.667903 1, 0xFFFF, sum = 0
3260 13:14:44.667997 2, 0xFFFF, sum = 0
3261 13:14:44.671132 3, 0xFFFF, sum = 0
3262 13:14:44.674367 4, 0xFFFF, sum = 0
3263 13:14:44.674437 5, 0xFFFF, sum = 0
3264 13:14:44.677606 6, 0xFFFF, sum = 0
3265 13:14:44.677671 7, 0xFFFF, sum = 0
3266 13:14:44.680965 8, 0xFFFF, sum = 0
3267 13:14:44.681029 9, 0xFFFF, sum = 0
3268 13:14:44.683926 10, 0xFFFF, sum = 0
3269 13:14:44.684015 11, 0xFFFF, sum = 0
3270 13:14:44.687216 12, 0x0, sum = 1
3271 13:14:44.687280 13, 0x0, sum = 2
3272 13:14:44.690832 14, 0x0, sum = 3
3273 13:14:44.690896 15, 0x0, sum = 4
3274 13:14:44.690955 best_step = 13
3275 13:14:44.693948
3276 13:14:44.694009 ==
3277 13:14:44.697089 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 13:14:44.701023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 13:14:44.701110 ==
3280 13:14:44.701236 RX Vref Scan: 1
3281 13:14:44.701291
3282 13:14:44.703938 Set Vref Range= 32 -> 127
3283 13:14:44.704004
3284 13:14:44.707524 RX Vref 32 -> 127, step: 1
3285 13:14:44.707585
3286 13:14:44.710825 RX Delay -13 -> 252, step: 4
3287 13:14:44.710886
3288 13:14:44.713887 Set Vref, RX VrefLevel [Byte0]: 32
3289 13:14:44.717407 [Byte1]: 32
3290 13:14:44.717493
3291 13:14:44.720685 Set Vref, RX VrefLevel [Byte0]: 33
3292 13:14:44.723913 [Byte1]: 33
3293 13:14:44.723976
3294 13:14:44.727580 Set Vref, RX VrefLevel [Byte0]: 34
3295 13:14:44.730771 [Byte1]: 34
3296 13:14:44.735226
3297 13:14:44.735316 Set Vref, RX VrefLevel [Byte0]: 35
3298 13:14:44.738590 [Byte1]: 35
3299 13:14:44.743528
3300 13:14:44.743600 Set Vref, RX VrefLevel [Byte0]: 36
3301 13:14:44.746328 [Byte1]: 36
3302 13:14:44.750940
3303 13:14:44.751012 Set Vref, RX VrefLevel [Byte0]: 37
3304 13:14:44.754020 [Byte1]: 37
3305 13:14:44.758934
3306 13:14:44.759024 Set Vref, RX VrefLevel [Byte0]: 38
3307 13:14:44.762031 [Byte1]: 38
3308 13:14:44.766604
3309 13:14:44.766671 Set Vref, RX VrefLevel [Byte0]: 39
3310 13:14:44.769756 [Byte1]: 39
3311 13:14:44.774548
3312 13:14:44.774617 Set Vref, RX VrefLevel [Byte0]: 40
3313 13:14:44.778046 [Byte1]: 40
3314 13:14:44.782418
3315 13:14:44.782508 Set Vref, RX VrefLevel [Byte0]: 41
3316 13:14:44.785926 [Byte1]: 41
3317 13:14:44.790593
3318 13:14:44.790654 Set Vref, RX VrefLevel [Byte0]: 42
3319 13:14:44.793498 [Byte1]: 42
3320 13:14:44.798026
3321 13:14:44.798096 Set Vref, RX VrefLevel [Byte0]: 43
3322 13:14:44.801889 [Byte1]: 43
3323 13:14:44.806172
3324 13:14:44.806246 Set Vref, RX VrefLevel [Byte0]: 44
3325 13:14:44.809339 [Byte1]: 44
3326 13:14:44.814167
3327 13:14:44.814242 Set Vref, RX VrefLevel [Byte0]: 45
3328 13:14:44.817143 [Byte1]: 45
3329 13:14:44.821725
3330 13:14:44.821799 Set Vref, RX VrefLevel [Byte0]: 46
3331 13:14:44.825160 [Byte1]: 46
3332 13:14:44.829702
3333 13:14:44.829776 Set Vref, RX VrefLevel [Byte0]: 47
3334 13:14:44.832990 [Byte1]: 47
3335 13:14:44.837714
3336 13:14:44.837789 Set Vref, RX VrefLevel [Byte0]: 48
3337 13:14:44.840999 [Byte1]: 48
3338 13:14:44.845621
3339 13:14:44.845696 Set Vref, RX VrefLevel [Byte0]: 49
3340 13:14:44.848811 [Byte1]: 49
3341 13:14:44.853323
3342 13:14:44.853398 Set Vref, RX VrefLevel [Byte0]: 50
3343 13:14:44.857058 [Byte1]: 50
3344 13:14:44.861218
3345 13:14:44.861293 Set Vref, RX VrefLevel [Byte0]: 51
3346 13:14:44.864685 [Byte1]: 51
3347 13:14:44.869288
3348 13:14:44.869362 Set Vref, RX VrefLevel [Byte0]: 52
3349 13:14:44.872615 [Byte1]: 52
3350 13:14:44.877371
3351 13:14:44.877446 Set Vref, RX VrefLevel [Byte0]: 53
3352 13:14:44.880793 [Byte1]: 53
3353 13:14:44.884735
3354 13:14:44.884810 Set Vref, RX VrefLevel [Byte0]: 54
3355 13:14:44.888083 [Byte1]: 54
3356 13:14:44.892555
3357 13:14:44.892630 Set Vref, RX VrefLevel [Byte0]: 55
3358 13:14:44.896219 [Byte1]: 55
3359 13:14:44.900841
3360 13:14:44.900916 Set Vref, RX VrefLevel [Byte0]: 56
3361 13:14:44.903758 [Byte1]: 56
3362 13:14:44.908867
3363 13:14:44.908945 Set Vref, RX VrefLevel [Byte0]: 57
3364 13:14:44.911743 [Byte1]: 57
3365 13:14:44.916499
3366 13:14:44.916575 Set Vref, RX VrefLevel [Byte0]: 58
3367 13:14:44.919800 [Byte1]: 58
3368 13:14:44.924359
3369 13:14:44.924434 Set Vref, RX VrefLevel [Byte0]: 59
3370 13:14:44.927703 [Byte1]: 59
3371 13:14:44.932168
3372 13:14:44.932244 Set Vref, RX VrefLevel [Byte0]: 60
3373 13:14:44.935828 [Byte1]: 60
3374 13:14:44.940018
3375 13:14:44.940093 Set Vref, RX VrefLevel [Byte0]: 61
3376 13:14:44.943579 [Byte1]: 61
3377 13:14:44.947862
3378 13:14:44.947938 Set Vref, RX VrefLevel [Byte0]: 62
3379 13:14:44.951388 [Byte1]: 62
3380 13:14:44.955809
3381 13:14:44.955884 Set Vref, RX VrefLevel [Byte0]: 63
3382 13:14:44.959327 [Byte1]: 63
3383 13:14:44.963929
3384 13:14:44.964005 Set Vref, RX VrefLevel [Byte0]: 64
3385 13:14:44.967341 [Byte1]: 64
3386 13:14:44.971671
3387 13:14:44.971746 Set Vref, RX VrefLevel [Byte0]: 65
3388 13:14:44.974998 [Byte1]: 65
3389 13:14:44.979541
3390 13:14:44.979617 Set Vref, RX VrefLevel [Byte0]: 66
3391 13:14:44.982745 [Byte1]: 66
3392 13:14:44.987646
3393 13:14:44.987721 Set Vref, RX VrefLevel [Byte0]: 67
3394 13:14:44.990913 [Byte1]: 67
3395 13:14:44.995351
3396 13:14:44.995426 Set Vref, RX VrefLevel [Byte0]: 68
3397 13:14:44.998877 [Byte1]: 68
3398 13:14:45.003377
3399 13:14:45.003452 Final RX Vref Byte 0 = 52 to rank0
3400 13:14:45.006460 Final RX Vref Byte 1 = 50 to rank0
3401 13:14:45.010243 Final RX Vref Byte 0 = 52 to rank1
3402 13:14:45.013471 Final RX Vref Byte 1 = 50 to rank1==
3403 13:14:45.016329 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 13:14:45.023028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 13:14:45.023105 ==
3406 13:14:45.023165 DQS Delay:
3407 13:14:45.026501 DQS0 = 0, DQS1 = 0
3408 13:14:45.026576 DQM Delay:
3409 13:14:45.026635 DQM0 = 119, DQM1 = 111
3410 13:14:45.030129 DQ Delay:
3411 13:14:45.032849 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3412 13:14:45.036542 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3413 13:14:45.039756 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3414 13:14:45.042985 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3415 13:14:45.043084
3416 13:14:45.043169
3417 13:14:45.052764 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3418 13:14:45.052841 CH1 RK0: MR19=404, MR18=417
3419 13:14:45.059390 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3420 13:14:45.059466
3421 13:14:45.062598 ----->DramcWriteLeveling(PI) begin...
3422 13:14:45.062675 ==
3423 13:14:45.066178 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 13:14:45.072843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 13:14:45.072920 ==
3426 13:14:45.076228 Write leveling (Byte 0): 25 => 25
3427 13:14:45.076306 Write leveling (Byte 1): 28 => 28
3428 13:14:45.078984 DramcWriteLeveling(PI) end<-----
3429 13:14:45.079077
3430 13:14:45.082542 ==
3431 13:14:45.082639 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 13:14:45.089099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 13:14:45.089237 ==
3434 13:14:45.092539 [Gating] SW mode calibration
3435 13:14:45.099328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 13:14:45.102614 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 13:14:45.109492 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 13:14:45.112849 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 13:14:45.116016 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 13:14:45.122605 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 13:14:45.126180 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 13:14:45.129247 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3443 13:14:45.136017 0 15 24 | B1->B0 | 2727 3434 | 0 0 | (1 0) (1 0)
3444 13:14:45.139265 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 1)
3445 13:14:45.142575 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 13:14:45.146442 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 13:14:45.152760 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 13:14:45.155859 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 13:14:45.159270 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 13:14:45.165882 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3451 13:14:45.169470 1 0 24 | B1->B0 | 3c3c 2c2c | 0 0 | (0 0) (1 1)
3452 13:14:45.172698 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 13:14:45.179433 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 13:14:45.182700 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 13:14:45.185859 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 13:14:45.192467 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 13:14:45.196012 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 13:14:45.199353 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 13:14:45.206021 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3460 13:14:45.209307 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3461 13:14:45.212262 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 13:14:45.219210 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 13:14:45.222719 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 13:14:45.225590 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 13:14:45.232328 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 13:14:45.235578 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 13:14:45.238753 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 13:14:45.245592 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 13:14:45.248954 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 13:14:45.252123 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 13:14:45.258828 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 13:14:45.262072 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 13:14:45.265787 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 13:14:45.272676 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 13:14:45.275435 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 13:14:45.278787 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3477 13:14:45.285524 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 13:14:45.285616 Total UI for P1: 0, mck2ui 16
3479 13:14:45.288832 best dqsien dly found for B0: ( 1, 3, 26)
3480 13:14:45.292143 Total UI for P1: 0, mck2ui 16
3481 13:14:45.295680 best dqsien dly found for B1: ( 1, 3, 26)
3482 13:14:45.298770 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3483 13:14:45.305370 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3484 13:14:45.305441
3485 13:14:45.308617 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 13:14:45.312085 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3487 13:14:45.315335 [Gating] SW calibration Done
3488 13:14:45.315400 ==
3489 13:14:45.318581 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 13:14:45.321874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 13:14:45.321945 ==
3492 13:14:45.322001 RX Vref Scan: 0
3493 13:14:45.325320
3494 13:14:45.325407 RX Vref 0 -> 0, step: 1
3495 13:14:45.325486
3496 13:14:45.328619 RX Delay -40 -> 252, step: 8
3497 13:14:45.331996 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3498 13:14:45.335388 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3499 13:14:45.342072 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3500 13:14:45.345250 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3501 13:14:45.349100 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3502 13:14:45.351878 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3503 13:14:45.355322 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3504 13:14:45.361728 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3505 13:14:45.365710 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3506 13:14:45.368844 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3507 13:14:45.371821 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3508 13:14:45.375440 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3509 13:14:45.382040 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3510 13:14:45.385466 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3511 13:14:45.388615 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3512 13:14:45.392151 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3513 13:14:45.392241 ==
3514 13:14:45.395567 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 13:14:45.401888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 13:14:45.401981 ==
3517 13:14:45.402040 DQS Delay:
3518 13:14:45.402094 DQS0 = 0, DQS1 = 0
3519 13:14:45.405415 DQM Delay:
3520 13:14:45.405502 DQM0 = 119, DQM1 = 113
3521 13:14:45.408621 DQ Delay:
3522 13:14:45.412024 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3523 13:14:45.415439 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3524 13:14:45.418624 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3525 13:14:45.421988 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3526 13:14:45.422055
3527 13:14:45.422112
3528 13:14:45.422164 ==
3529 13:14:45.425058 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 13:14:45.428667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 13:14:45.428755 ==
3532 13:14:45.428837
3533 13:14:45.431886
3534 13:14:45.431971 TX Vref Scan disable
3535 13:14:45.435245 == TX Byte 0 ==
3536 13:14:45.438315 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3537 13:14:45.441960 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3538 13:14:45.445347 == TX Byte 1 ==
3539 13:14:45.448557 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3540 13:14:45.452168 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3541 13:14:45.452233 ==
3542 13:14:45.455085 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 13:14:45.461771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 13:14:45.461842 ==
3545 13:14:45.472559 TX Vref=22, minBit 1, minWin=25, winSum=412
3546 13:14:45.475972 TX Vref=24, minBit 8, minWin=25, winSum=421
3547 13:14:45.479424 TX Vref=26, minBit 11, minWin=25, winSum=424
3548 13:14:45.483009 TX Vref=28, minBit 10, minWin=25, winSum=426
3549 13:14:45.486116 TX Vref=30, minBit 3, minWin=26, winSum=427
3550 13:14:45.489395 TX Vref=32, minBit 9, minWin=25, winSum=426
3551 13:14:45.495887 [TxChooseVref] Worse bit 3, Min win 26, Win sum 427, Final Vref 30
3552 13:14:45.496009
3553 13:14:45.499191 Final TX Range 1 Vref 30
3554 13:14:45.499313
3555 13:14:45.499397 ==
3556 13:14:45.502797 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 13:14:45.506210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 13:14:45.506372 ==
3559 13:14:45.506494
3560 13:14:45.506592
3561 13:14:45.509801 TX Vref Scan disable
3562 13:14:45.512611 == TX Byte 0 ==
3563 13:14:45.515801 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 13:14:45.519046 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 13:14:45.522647 == TX Byte 1 ==
3566 13:14:45.526131 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 13:14:45.529258 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 13:14:45.529328
3569 13:14:45.532874 [DATLAT]
3570 13:14:45.532938 Freq=1200, CH1 RK1
3571 13:14:45.532993
3572 13:14:45.536037 DATLAT Default: 0xd
3573 13:14:45.536101 0, 0xFFFF, sum = 0
3574 13:14:45.539332 1, 0xFFFF, sum = 0
3575 13:14:45.539395 2, 0xFFFF, sum = 0
3576 13:14:45.542269 3, 0xFFFF, sum = 0
3577 13:14:45.542334 4, 0xFFFF, sum = 0
3578 13:14:45.545525 5, 0xFFFF, sum = 0
3579 13:14:45.545593 6, 0xFFFF, sum = 0
3580 13:14:45.549334 7, 0xFFFF, sum = 0
3581 13:14:45.552619 8, 0xFFFF, sum = 0
3582 13:14:45.552681 9, 0xFFFF, sum = 0
3583 13:14:45.556269 10, 0xFFFF, sum = 0
3584 13:14:45.556334 11, 0xFFFF, sum = 0
3585 13:14:45.559221 12, 0x0, sum = 1
3586 13:14:45.559287 13, 0x0, sum = 2
3587 13:14:45.562364 14, 0x0, sum = 3
3588 13:14:45.562431 15, 0x0, sum = 4
3589 13:14:45.562486 best_step = 13
3590 13:14:45.562538
3591 13:14:45.565587 ==
3592 13:14:45.569081 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 13:14:45.572248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 13:14:45.572310 ==
3595 13:14:45.572364 RX Vref Scan: 0
3596 13:14:45.572424
3597 13:14:45.575958 RX Vref 0 -> 0, step: 1
3598 13:14:45.576023
3599 13:14:45.578980 RX Delay -13 -> 252, step: 4
3600 13:14:45.582111 iDelay=195, Bit 0, Center 124 (67 ~ 182) 116
3601 13:14:45.589056 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3602 13:14:45.592381 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3603 13:14:45.595689 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3604 13:14:45.598925 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3605 13:14:45.602367 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3606 13:14:45.605833 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3607 13:14:45.612016 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3608 13:14:45.615606 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3609 13:14:45.618956 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3610 13:14:45.622781 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3611 13:14:45.625424 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3612 13:14:45.632195 iDelay=195, Bit 12, Center 120 (55 ~ 186) 132
3613 13:14:45.635553 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3614 13:14:45.639124 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3615 13:14:45.642263 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3616 13:14:45.642339 ==
3617 13:14:45.645874 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 13:14:45.652591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 13:14:45.652668 ==
3620 13:14:45.652728 DQS Delay:
3621 13:14:45.655473 DQS0 = 0, DQS1 = 0
3622 13:14:45.655548 DQM Delay:
3623 13:14:45.659135 DQM0 = 119, DQM1 = 112
3624 13:14:45.659210 DQ Delay:
3625 13:14:45.662011 DQ0 =124, DQ1 =114, DQ2 =108, DQ3 =116
3626 13:14:45.665634 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3627 13:14:45.668838 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3628 13:14:45.672106 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =122
3629 13:14:45.672182
3630 13:14:45.672241
3631 13:14:45.681880 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3632 13:14:45.681957 CH1 RK1: MR19=403, MR18=CF1
3633 13:14:45.688977 CH1_RK1: MR19=0x403, MR18=0xCF1, DQSOSC=405, MR23=63, INC=39, DEC=26
3634 13:14:45.692059 [RxdqsGatingPostProcess] freq 1200
3635 13:14:45.698492 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 13:14:45.702093 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 13:14:45.705065 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 13:14:45.708619 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 13:14:45.712199 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 13:14:45.712275 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 13:14:45.715113 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 13:14:45.718641 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 13:14:45.721965 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 13:14:45.726041 Pre-setting of DQS Precalculation
3645 13:14:45.731900 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 13:14:45.738489 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 13:14:45.745221 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 13:14:45.745297
3649 13:14:45.745357
3650 13:14:45.748288 [Calibration Summary] 2400 Mbps
3651 13:14:45.748364 CH 0, Rank 0
3652 13:14:45.751691 SW Impedance : PASS
3653 13:14:45.755297 DUTY Scan : NO K
3654 13:14:45.755373 ZQ Calibration : PASS
3655 13:14:45.758293 Jitter Meter : NO K
3656 13:14:45.761504 CBT Training : PASS
3657 13:14:45.761580 Write leveling : PASS
3658 13:14:45.764866 RX DQS gating : PASS
3659 13:14:45.768327 RX DQ/DQS(RDDQC) : PASS
3660 13:14:45.768402 TX DQ/DQS : PASS
3661 13:14:45.771944 RX DATLAT : PASS
3662 13:14:45.775238 RX DQ/DQS(Engine): PASS
3663 13:14:45.775314 TX OE : NO K
3664 13:14:45.778549 All Pass.
3665 13:14:45.778624
3666 13:14:45.778686 CH 0, Rank 1
3667 13:14:45.781732 SW Impedance : PASS
3668 13:14:45.781808 DUTY Scan : NO K
3669 13:14:45.785114 ZQ Calibration : PASS
3670 13:14:45.788562 Jitter Meter : NO K
3671 13:14:45.788638 CBT Training : PASS
3672 13:14:45.791712 Write leveling : PASS
3673 13:14:45.794604 RX DQS gating : PASS
3674 13:14:45.794679 RX DQ/DQS(RDDQC) : PASS
3675 13:14:45.798078 TX DQ/DQS : PASS
3676 13:14:45.798178 RX DATLAT : PASS
3677 13:14:45.801646 RX DQ/DQS(Engine): PASS
3678 13:14:45.805013 TX OE : NO K
3679 13:14:45.805113 All Pass.
3680 13:14:45.805218
3681 13:14:45.805274 CH 1, Rank 0
3682 13:14:45.808247 SW Impedance : PASS
3683 13:14:45.811530 DUTY Scan : NO K
3684 13:14:45.811605 ZQ Calibration : PASS
3685 13:14:45.814592 Jitter Meter : NO K
3686 13:14:45.818357 CBT Training : PASS
3687 13:14:45.818445 Write leveling : PASS
3688 13:14:45.821590 RX DQS gating : PASS
3689 13:14:45.824910 RX DQ/DQS(RDDQC) : PASS
3690 13:14:45.824986 TX DQ/DQS : PASS
3691 13:14:45.827965 RX DATLAT : PASS
3692 13:14:45.831498 RX DQ/DQS(Engine): PASS
3693 13:14:45.831578 TX OE : NO K
3694 13:14:45.834756 All Pass.
3695 13:14:45.834831
3696 13:14:45.834892 CH 1, Rank 1
3697 13:14:45.838375 SW Impedance : PASS
3698 13:14:45.838451 DUTY Scan : NO K
3699 13:14:45.841490 ZQ Calibration : PASS
3700 13:14:45.844811 Jitter Meter : NO K
3701 13:14:45.844887 CBT Training : PASS
3702 13:14:45.848284 Write leveling : PASS
3703 13:14:45.848359 RX DQS gating : PASS
3704 13:14:45.851320 RX DQ/DQS(RDDQC) : PASS
3705 13:14:45.854723 TX DQ/DQS : PASS
3706 13:14:45.854798 RX DATLAT : PASS
3707 13:14:45.857968 RX DQ/DQS(Engine): PASS
3708 13:14:45.861439 TX OE : NO K
3709 13:14:45.861515 All Pass.
3710 13:14:45.861574
3711 13:14:45.864483 DramC Write-DBI off
3712 13:14:45.864559 PER_BANK_REFRESH: Hybrid Mode
3713 13:14:45.868050 TX_TRACKING: ON
3714 13:14:45.874711 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 13:14:45.881367 [FAST_K] Save calibration result to emmc
3716 13:14:45.884639 dramc_set_vcore_voltage set vcore to 650000
3717 13:14:45.884715 Read voltage for 600, 5
3718 13:14:45.887915 Vio18 = 0
3719 13:14:45.887990 Vcore = 650000
3720 13:14:45.888048 Vdram = 0
3721 13:14:45.891706 Vddq = 0
3722 13:14:45.891782 Vmddr = 0
3723 13:14:45.894391 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 13:14:45.901145 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 13:14:45.904655 MEM_TYPE=3, freq_sel=19
3726 13:14:45.908164 sv_algorithm_assistance_LP4_1600
3727 13:14:45.911313 ============ PULL DRAM RESETB DOWN ============
3728 13:14:45.914291 ========== PULL DRAM RESETB DOWN end =========
3729 13:14:45.921497 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 13:14:45.924435 ===================================
3731 13:14:45.924512 LPDDR4 DRAM CONFIGURATION
3732 13:14:45.927708 ===================================
3733 13:14:45.931363 EX_ROW_EN[0] = 0x0
3734 13:14:45.931438 EX_ROW_EN[1] = 0x0
3735 13:14:45.934254 LP4Y_EN = 0x0
3736 13:14:45.934330 WORK_FSP = 0x0
3737 13:14:45.938000 WL = 0x2
3738 13:14:45.941407 RL = 0x2
3739 13:14:45.941482 BL = 0x2
3740 13:14:45.944578 RPST = 0x0
3741 13:14:45.944654 RD_PRE = 0x0
3742 13:14:45.947962 WR_PRE = 0x1
3743 13:14:45.948038 WR_PST = 0x0
3744 13:14:45.951174 DBI_WR = 0x0
3745 13:14:45.951250 DBI_RD = 0x0
3746 13:14:45.954460 OTF = 0x1
3747 13:14:45.957693 ===================================
3748 13:14:45.960950 ===================================
3749 13:14:45.961049 ANA top config
3750 13:14:45.964717 ===================================
3751 13:14:45.967645 DLL_ASYNC_EN = 0
3752 13:14:45.971617 ALL_SLAVE_EN = 1
3753 13:14:45.971693 NEW_RANK_MODE = 1
3754 13:14:45.974800 DLL_IDLE_MODE = 1
3755 13:14:45.977594 LP45_APHY_COMB_EN = 1
3756 13:14:45.980992 TX_ODT_DIS = 1
3757 13:14:45.981092 NEW_8X_MODE = 1
3758 13:14:45.984849 ===================================
3759 13:14:45.987682 ===================================
3760 13:14:45.991029 data_rate = 1200
3761 13:14:45.994100 CKR = 1
3762 13:14:45.997541 DQ_P2S_RATIO = 8
3763 13:14:46.001158 ===================================
3764 13:14:46.004248 CA_P2S_RATIO = 8
3765 13:14:46.007381 DQ_CA_OPEN = 0
3766 13:14:46.007457 DQ_SEMI_OPEN = 0
3767 13:14:46.010684 CA_SEMI_OPEN = 0
3768 13:14:46.014338 CA_FULL_RATE = 0
3769 13:14:46.017234 DQ_CKDIV4_EN = 1
3770 13:14:46.020636 CA_CKDIV4_EN = 1
3771 13:14:46.024295 CA_PREDIV_EN = 0
3772 13:14:46.024372 PH8_DLY = 0
3773 13:14:46.027473 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 13:14:46.030892 DQ_AAMCK_DIV = 4
3775 13:14:46.034092 CA_AAMCK_DIV = 4
3776 13:14:46.037681 CA_ADMCK_DIV = 4
3777 13:14:46.040965 DQ_TRACK_CA_EN = 0
3778 13:14:46.041041 CA_PICK = 600
3779 13:14:46.043906 CA_MCKIO = 600
3780 13:14:46.047434 MCKIO_SEMI = 0
3781 13:14:46.050716 PLL_FREQ = 2288
3782 13:14:46.054248 DQ_UI_PI_RATIO = 32
3783 13:14:46.057455 CA_UI_PI_RATIO = 0
3784 13:14:46.060831 ===================================
3785 13:14:46.063999 ===================================
3786 13:14:46.067362 memory_type:LPDDR4
3787 13:14:46.067438 GP_NUM : 10
3788 13:14:46.070504 SRAM_EN : 1
3789 13:14:46.070610 MD32_EN : 0
3790 13:14:46.073828 ===================================
3791 13:14:46.077309 [ANA_INIT] >>>>>>>>>>>>>>
3792 13:14:46.080918 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 13:14:46.084002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 13:14:46.087210 ===================================
3795 13:14:46.090768 data_rate = 1200,PCW = 0X5800
3796 13:14:46.093912 ===================================
3797 13:14:46.097030 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 13:14:46.100670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 13:14:46.107244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 13:14:46.110858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 13:14:46.113938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 13:14:46.120463 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 13:14:46.120540 [ANA_INIT] flow start
3804 13:14:46.123809 [ANA_INIT] PLL >>>>>>>>
3805 13:14:46.123885 [ANA_INIT] PLL <<<<<<<<
3806 13:14:46.127144 [ANA_INIT] MIDPI >>>>>>>>
3807 13:14:46.130671 [ANA_INIT] MIDPI <<<<<<<<
3808 13:14:46.133709 [ANA_INIT] DLL >>>>>>>>
3809 13:14:46.133832 [ANA_INIT] flow end
3810 13:14:46.137491 ============ LP4 DIFF to SE enter ============
3811 13:14:46.143686 ============ LP4 DIFF to SE exit ============
3812 13:14:46.143790 [ANA_INIT] <<<<<<<<<<<<<
3813 13:14:46.147237 [Flow] Enable top DCM control >>>>>
3814 13:14:46.150159 [Flow] Enable top DCM control <<<<<
3815 13:14:46.153505 Enable DLL master slave shuffle
3816 13:14:46.160063 ==============================================================
3817 13:14:46.160155 Gating Mode config
3818 13:14:46.166950 ==============================================================
3819 13:14:46.170415 Config description:
3820 13:14:46.180428 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 13:14:46.186742 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 13:14:46.190071 SELPH_MODE 0: By rank 1: By Phase
3823 13:14:46.196773 ==============================================================
3824 13:14:46.200245 GAT_TRACK_EN = 1
3825 13:14:46.200321 RX_GATING_MODE = 2
3826 13:14:46.203400 RX_GATING_TRACK_MODE = 2
3827 13:14:46.206816 SELPH_MODE = 1
3828 13:14:46.209975 PICG_EARLY_EN = 1
3829 13:14:46.213846 VALID_LAT_VALUE = 1
3830 13:14:46.220675 ==============================================================
3831 13:14:46.223612 Enter into Gating configuration >>>>
3832 13:14:46.227084 Exit from Gating configuration <<<<
3833 13:14:46.230048 Enter into DVFS_PRE_config >>>>>
3834 13:14:46.239852 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 13:14:46.243218 Exit from DVFS_PRE_config <<<<<
3836 13:14:46.246711 Enter into PICG configuration >>>>
3837 13:14:46.250286 Exit from PICG configuration <<<<
3838 13:14:46.253349 [RX_INPUT] configuration >>>>>
3839 13:14:46.256787 [RX_INPUT] configuration <<<<<
3840 13:14:46.259930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 13:14:46.266467 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 13:14:46.273398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 13:14:46.276464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 13:14:46.283306 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 13:14:46.289986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 13:14:46.293239 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 13:14:46.296402 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 13:14:46.303216 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 13:14:46.306604 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 13:14:46.310158 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 13:14:46.316532 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 13:14:46.319696 ===================================
3853 13:14:46.319772 LPDDR4 DRAM CONFIGURATION
3854 13:14:46.323418 ===================================
3855 13:14:46.326439 EX_ROW_EN[0] = 0x0
3856 13:14:46.329687 EX_ROW_EN[1] = 0x0
3857 13:14:46.329763 LP4Y_EN = 0x0
3858 13:14:46.333262 WORK_FSP = 0x0
3859 13:14:46.333338 WL = 0x2
3860 13:14:46.336390 RL = 0x2
3861 13:14:46.336465 BL = 0x2
3862 13:14:46.339821 RPST = 0x0
3863 13:14:46.339897 RD_PRE = 0x0
3864 13:14:46.343384 WR_PRE = 0x1
3865 13:14:46.343460 WR_PST = 0x0
3866 13:14:46.346335 DBI_WR = 0x0
3867 13:14:46.346411 DBI_RD = 0x0
3868 13:14:46.350231 OTF = 0x1
3869 13:14:46.353001 ===================================
3870 13:14:46.356338 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 13:14:46.360166 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 13:14:46.366747 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 13:14:46.370008 ===================================
3874 13:14:46.370085 LPDDR4 DRAM CONFIGURATION
3875 13:14:46.373259 ===================================
3876 13:14:46.376408 EX_ROW_EN[0] = 0x10
3877 13:14:46.376484 EX_ROW_EN[1] = 0x0
3878 13:14:46.380283 LP4Y_EN = 0x0
3879 13:14:46.380358 WORK_FSP = 0x0
3880 13:14:46.383073 WL = 0x2
3881 13:14:46.383138 RL = 0x2
3882 13:14:46.386373 BL = 0x2
3883 13:14:46.389728 RPST = 0x0
3884 13:14:46.389802 RD_PRE = 0x0
3885 13:14:46.393069 WR_PRE = 0x1
3886 13:14:46.393168 WR_PST = 0x0
3887 13:14:46.396522 DBI_WR = 0x0
3888 13:14:46.396597 DBI_RD = 0x0
3889 13:14:46.399531 OTF = 0x1
3890 13:14:46.402875 ===================================
3891 13:14:46.406422 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 13:14:46.411859 nWR fixed to 30
3893 13:14:46.414871 [ModeRegInit_LP4] CH0 RK0
3894 13:14:46.414947 [ModeRegInit_LP4] CH0 RK1
3895 13:14:46.418371 [ModeRegInit_LP4] CH1 RK0
3896 13:14:46.421816 [ModeRegInit_LP4] CH1 RK1
3897 13:14:46.421891 match AC timing 17
3898 13:14:46.428272 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 13:14:46.432165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 13:14:46.435061 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 13:14:46.441511 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 13:14:46.445003 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 13:14:46.445079 ==
3904 13:14:46.448334 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 13:14:46.451540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 13:14:46.451616 ==
3907 13:14:46.458268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 13:14:46.464921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3909 13:14:46.468185 [CA 0] Center 36 (5~67) winsize 63
3910 13:14:46.471638 [CA 1] Center 36 (6~67) winsize 62
3911 13:14:46.475095 [CA 2] Center 34 (4~65) winsize 62
3912 13:14:46.478119 [CA 3] Center 34 (4~65) winsize 62
3913 13:14:46.481816 [CA 4] Center 34 (3~65) winsize 63
3914 13:14:46.484864 [CA 5] Center 33 (3~64) winsize 62
3915 13:14:46.484940
3916 13:14:46.488116 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3917 13:14:46.488191
3918 13:14:46.491452 [CATrainingPosCal] consider 1 rank data
3919 13:14:46.494765 u2DelayCellTimex100 = 270/100 ps
3920 13:14:46.497895 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3921 13:14:46.501387 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3922 13:14:46.504502 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3923 13:14:46.508005 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3924 13:14:46.511229 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3925 13:14:46.518067 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3926 13:14:46.518147
3927 13:14:46.521401 CA PerBit enable=1, Macro0, CA PI delay=33
3928 13:14:46.521477
3929 13:14:46.524528 [CBTSetCACLKResult] CA Dly = 33
3930 13:14:46.524603 CS Dly: 4 (0~35)
3931 13:14:46.524661 ==
3932 13:14:46.528027 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 13:14:46.531106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 13:14:46.531183 ==
3935 13:14:46.538202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 13:14:46.544752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3937 13:14:46.548307 [CA 0] Center 36 (6~67) winsize 62
3938 13:14:46.551214 [CA 1] Center 36 (6~67) winsize 62
3939 13:14:46.554782 [CA 2] Center 35 (5~66) winsize 62
3940 13:14:46.557825 [CA 3] Center 34 (4~65) winsize 62
3941 13:14:46.561413 [CA 4] Center 34 (3~65) winsize 63
3942 13:14:46.564673 [CA 5] Center 34 (3~65) winsize 63
3943 13:14:46.564750
3944 13:14:46.567944 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3945 13:14:46.568019
3946 13:14:46.571293 [CATrainingPosCal] consider 2 rank data
3947 13:14:46.574874 u2DelayCellTimex100 = 270/100 ps
3948 13:14:46.578026 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3949 13:14:46.581809 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3950 13:14:46.584710 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3951 13:14:46.588185 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 13:14:46.591429 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3953 13:14:46.598612 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 13:14:46.598688
3955 13:14:46.601180 CA PerBit enable=1, Macro0, CA PI delay=33
3956 13:14:46.601256
3957 13:14:46.604837 [CBTSetCACLKResult] CA Dly = 33
3958 13:14:46.604913 CS Dly: 5 (0~37)
3959 13:14:46.605020
3960 13:14:46.608114 ----->DramcWriteLeveling(PI) begin...
3961 13:14:46.608191 ==
3962 13:14:46.612294 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 13:14:46.617769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 13:14:46.617847 ==
3965 13:14:46.621384 Write leveling (Byte 0): 35 => 35
3966 13:14:46.621487 Write leveling (Byte 1): 30 => 30
3967 13:14:46.624416 DramcWriteLeveling(PI) end<-----
3968 13:14:46.624490
3969 13:14:46.624548 ==
3970 13:14:46.627953 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 13:14:46.634715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 13:14:46.634791 ==
3973 13:14:46.638039 [Gating] SW mode calibration
3974 13:14:46.644668 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 13:14:46.647822 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 13:14:46.654264 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 13:14:46.658038 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 13:14:46.661401 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 13:14:46.667955 0 9 12 | B1->B0 | 3030 2c2c | 0 1 | (0 0) (1 1)
3980 13:14:46.670994 0 9 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
3981 13:14:46.674403 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 13:14:46.680958 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 13:14:46.684063 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 13:14:46.687464 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 13:14:46.694504 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 13:14:46.697460 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3987 13:14:46.700862 0 10 12 | B1->B0 | 2b2b 3d3d | 0 1 | (0 0) (0 0)
3988 13:14:46.707469 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3989 13:14:46.710811 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 13:14:46.714038 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 13:14:46.717527 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 13:14:46.724057 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 13:14:46.727459 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 13:14:46.730662 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3995 13:14:46.737339 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3996 13:14:46.740358 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 13:14:46.743695 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 13:14:46.750700 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 13:14:46.754115 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 13:14:46.757064 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 13:14:46.763822 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 13:14:46.767087 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 13:14:46.770238 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 13:14:46.776826 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 13:14:46.780292 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 13:14:46.783488 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 13:14:46.790097 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 13:14:46.793856 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 13:14:46.796983 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 13:14:46.803601 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 13:14:46.806670 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4012 13:14:46.810083 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 13:14:46.813256 Total UI for P1: 0, mck2ui 16
4014 13:14:46.816766 best dqsien dly found for B0: ( 0, 13, 12)
4015 13:14:46.820241 Total UI for P1: 0, mck2ui 16
4016 13:14:46.823412 best dqsien dly found for B1: ( 0, 13, 12)
4017 13:14:46.826894 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4018 13:14:46.830075 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4019 13:14:46.830151
4020 13:14:46.836958 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4021 13:14:46.840182 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4022 13:14:46.840258 [Gating] SW calibration Done
4023 13:14:46.843555 ==
4024 13:14:46.846744 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 13:14:46.850212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 13:14:46.850289 ==
4027 13:14:46.850349 RX Vref Scan: 0
4028 13:14:46.850404
4029 13:14:46.853317 RX Vref 0 -> 0, step: 1
4030 13:14:46.853393
4031 13:14:46.856706 RX Delay -230 -> 252, step: 16
4032 13:14:46.859987 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4033 13:14:46.863369 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4034 13:14:46.869923 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 13:14:46.873599 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4036 13:14:46.876796 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4037 13:14:46.880038 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4038 13:14:46.883463 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4039 13:14:46.890037 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4040 13:14:46.893169 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4041 13:14:46.896502 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4042 13:14:46.899712 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4043 13:14:46.906519 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4044 13:14:46.909863 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4045 13:14:46.913183 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4046 13:14:46.916443 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4047 13:14:46.923317 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4048 13:14:46.923397 ==
4049 13:14:46.926688 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 13:14:46.930172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 13:14:46.930249 ==
4052 13:14:46.930308 DQS Delay:
4053 13:14:46.933094 DQS0 = 0, DQS1 = 0
4054 13:14:46.933218 DQM Delay:
4055 13:14:46.936452 DQM0 = 51, DQM1 = 41
4056 13:14:46.936528 DQ Delay:
4057 13:14:46.940011 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4058 13:14:46.943405 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4059 13:14:46.946600 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4060 13:14:46.949796 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4061 13:14:46.949872
4062 13:14:46.949931
4063 13:14:46.949984 ==
4064 13:14:46.953176 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 13:14:46.956355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 13:14:46.956431 ==
4067 13:14:46.956490
4068 13:14:46.959599
4069 13:14:46.959675 TX Vref Scan disable
4070 13:14:46.962964 == TX Byte 0 ==
4071 13:14:46.966478 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4072 13:14:46.969949 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4073 13:14:46.972888 == TX Byte 1 ==
4074 13:14:46.976452 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4075 13:14:46.979893 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4076 13:14:46.979969 ==
4077 13:14:46.983152 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 13:14:46.989948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 13:14:46.990024 ==
4080 13:14:46.990083
4081 13:14:46.990137
4082 13:14:46.990189 TX Vref Scan disable
4083 13:14:46.994364 == TX Byte 0 ==
4084 13:14:46.997887 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4085 13:14:47.001214 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4086 13:14:47.004332 == TX Byte 1 ==
4087 13:14:47.007887 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4088 13:14:47.011581 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4089 13:14:47.011657
4090 13:14:47.014528 [DATLAT]
4091 13:14:47.014604 Freq=600, CH0 RK0
4092 13:14:47.014666
4093 13:14:47.018047 DATLAT Default: 0x9
4094 13:14:47.018146 0, 0xFFFF, sum = 0
4095 13:14:47.021564 1, 0xFFFF, sum = 0
4096 13:14:47.021641 2, 0xFFFF, sum = 0
4097 13:14:47.024707 3, 0xFFFF, sum = 0
4098 13:14:47.024783 4, 0xFFFF, sum = 0
4099 13:14:47.027871 5, 0xFFFF, sum = 0
4100 13:14:47.027948 6, 0xFFFF, sum = 0
4101 13:14:47.031543 7, 0xFFFF, sum = 0
4102 13:14:47.031620 8, 0x0, sum = 1
4103 13:14:47.034706 9, 0x0, sum = 2
4104 13:14:47.034782 10, 0x0, sum = 3
4105 13:14:47.037852 11, 0x0, sum = 4
4106 13:14:47.037929 best_step = 9
4107 13:14:47.037988
4108 13:14:47.038042 ==
4109 13:14:47.041534 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 13:14:47.047938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 13:14:47.048016 ==
4112 13:14:47.048075 RX Vref Scan: 1
4113 13:14:47.048131
4114 13:14:47.051534 RX Vref 0 -> 0, step: 1
4115 13:14:47.051609
4116 13:14:47.054817 RX Delay -179 -> 252, step: 8
4117 13:14:47.054894
4118 13:14:47.058053 Set Vref, RX VrefLevel [Byte0]: 60
4119 13:14:47.061382 [Byte1]: 49
4120 13:14:47.061482
4121 13:14:47.064622 Final RX Vref Byte 0 = 60 to rank0
4122 13:14:47.067871 Final RX Vref Byte 1 = 49 to rank0
4123 13:14:47.070981 Final RX Vref Byte 0 = 60 to rank1
4124 13:14:47.074763 Final RX Vref Byte 1 = 49 to rank1==
4125 13:14:47.077900 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 13:14:47.081030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 13:14:47.081108 ==
4128 13:14:47.084555 DQS Delay:
4129 13:14:47.084630 DQS0 = 0, DQS1 = 0
4130 13:14:47.084689 DQM Delay:
4131 13:14:47.087621 DQM0 = 49, DQM1 = 39
4132 13:14:47.087697 DQ Delay:
4133 13:14:47.091196 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4134 13:14:47.094280 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4135 13:14:47.097789 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4136 13:14:47.101096 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4137 13:14:47.101214
4138 13:14:47.101273
4139 13:14:47.110945 [DQSOSCAuto] RK0, (LSB)MR18= 0x635d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4140 13:14:47.111022 CH0 RK0: MR19=808, MR18=635D
4141 13:14:47.118048 CH0_RK0: MR19=0x808, MR18=0x635D, DQSOSC=391, MR23=63, INC=171, DEC=114
4142 13:14:47.118123
4143 13:14:47.120990 ----->DramcWriteLeveling(PI) begin...
4144 13:14:47.121066 ==
4145 13:14:47.124457 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 13:14:47.131105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 13:14:47.131182 ==
4148 13:14:47.134376 Write leveling (Byte 0): 33 => 33
4149 13:14:47.137631 Write leveling (Byte 1): 31 => 31
4150 13:14:47.137706 DramcWriteLeveling(PI) end<-----
4151 13:14:47.140763
4152 13:14:47.140837 ==
4153 13:14:47.144067 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 13:14:47.147576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 13:14:47.147651 ==
4156 13:14:47.150850 [Gating] SW mode calibration
4157 13:14:47.157606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 13:14:47.160949 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 13:14:47.167555 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 13:14:47.171060 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 13:14:47.174513 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4162 13:14:47.180863 0 9 12 | B1->B0 | 3232 2d2d | 0 0 | (1 1) (1 0)
4163 13:14:47.183899 0 9 16 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4164 13:14:47.187661 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 13:14:47.193899 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 13:14:47.197630 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 13:14:47.200807 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 13:14:47.207437 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 13:14:47.210812 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 13:14:47.214178 0 10 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (0 0)
4171 13:14:47.220739 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4172 13:14:47.223932 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 13:14:47.227253 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 13:14:47.233909 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 13:14:47.237351 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 13:14:47.240595 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 13:14:47.247396 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 13:14:47.250933 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 13:14:47.253821 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4180 13:14:47.260675 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 13:14:47.264037 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 13:14:47.267122 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 13:14:47.270780 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 13:14:47.277145 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 13:14:47.280553 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 13:14:47.283858 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 13:14:47.290605 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 13:14:47.293644 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 13:14:47.296906 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 13:14:47.303767 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 13:14:47.307322 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 13:14:47.310278 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 13:14:47.317367 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 13:14:47.320675 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4195 13:14:47.323829 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 13:14:47.327377 Total UI for P1: 0, mck2ui 16
4197 13:14:47.330417 best dqsien dly found for B0: ( 0, 13, 12)
4198 13:14:47.333987 Total UI for P1: 0, mck2ui 16
4199 13:14:47.336956 best dqsien dly found for B1: ( 0, 13, 14)
4200 13:14:47.340159 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4201 13:14:47.343721 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4202 13:14:47.343796
4203 13:14:47.350139 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4204 13:14:47.353506 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4205 13:14:47.356934 [Gating] SW calibration Done
4206 13:14:47.357010 ==
4207 13:14:47.360220 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 13:14:47.363894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 13:14:47.363970 ==
4210 13:14:47.364030 RX Vref Scan: 0
4211 13:14:47.364085
4212 13:14:47.367009 RX Vref 0 -> 0, step: 1
4213 13:14:47.367085
4214 13:14:47.370570 RX Delay -230 -> 252, step: 16
4215 13:14:47.373456 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4216 13:14:47.377242 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4217 13:14:47.383914 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4218 13:14:47.386874 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4219 13:14:47.390207 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4220 13:14:47.393349 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4221 13:14:47.396890 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4222 13:14:47.403407 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4223 13:14:47.407272 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4224 13:14:47.410217 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4225 13:14:47.413489 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4226 13:14:47.420170 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4227 13:14:47.423486 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4228 13:14:47.426772 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4229 13:14:47.430001 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4230 13:14:47.436604 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4231 13:14:47.436680 ==
4232 13:14:47.439869 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 13:14:47.443272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 13:14:47.443348 ==
4235 13:14:47.443406 DQS Delay:
4236 13:14:47.446971 DQS0 = 0, DQS1 = 0
4237 13:14:47.447046 DQM Delay:
4238 13:14:47.450107 DQM0 = 47, DQM1 = 41
4239 13:14:47.450181 DQ Delay:
4240 13:14:47.453224 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4241 13:14:47.456580 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4242 13:14:47.459768 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4243 13:14:47.463546 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4244 13:14:47.463648
4245 13:14:47.463731
4246 13:14:47.463805 ==
4247 13:14:47.466816 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 13:14:47.470255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 13:14:47.470331 ==
4250 13:14:47.470390
4251 13:14:47.470445
4252 13:14:47.473553 TX Vref Scan disable
4253 13:14:47.476653 == TX Byte 0 ==
4254 13:14:47.480437 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4255 13:14:47.483396 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4256 13:14:47.486575 == TX Byte 1 ==
4257 13:14:47.489960 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4258 13:14:47.493787 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4259 13:14:47.493864 ==
4260 13:14:47.496657 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 13:14:47.503131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 13:14:47.503210 ==
4263 13:14:47.503269
4264 13:14:47.503324
4265 13:14:47.503376 TX Vref Scan disable
4266 13:14:47.508117 == TX Byte 0 ==
4267 13:14:47.511212 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4268 13:14:47.517978 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4269 13:14:47.518054 == TX Byte 1 ==
4270 13:14:47.520959 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4271 13:14:47.527718 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4272 13:14:47.527794
4273 13:14:47.527853 [DATLAT]
4274 13:14:47.527907 Freq=600, CH0 RK1
4275 13:14:47.527959
4276 13:14:47.531281 DATLAT Default: 0x9
4277 13:14:47.531357 0, 0xFFFF, sum = 0
4278 13:14:47.534208 1, 0xFFFF, sum = 0
4279 13:14:47.534285 2, 0xFFFF, sum = 0
4280 13:14:47.537821 3, 0xFFFF, sum = 0
4281 13:14:47.540841 4, 0xFFFF, sum = 0
4282 13:14:47.540917 5, 0xFFFF, sum = 0
4283 13:14:47.544199 6, 0xFFFF, sum = 0
4284 13:14:47.544276 7, 0xFFFF, sum = 0
4285 13:14:47.548055 8, 0x0, sum = 1
4286 13:14:47.548132 9, 0x0, sum = 2
4287 13:14:47.548192 10, 0x0, sum = 3
4288 13:14:47.550828 11, 0x0, sum = 4
4289 13:14:47.550904 best_step = 9
4290 13:14:47.550963
4291 13:14:47.551017 ==
4292 13:14:47.554215 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 13:14:47.561078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 13:14:47.561195 ==
4295 13:14:47.561254 RX Vref Scan: 0
4296 13:14:47.561309
4297 13:14:47.564531 RX Vref 0 -> 0, step: 1
4298 13:14:47.564606
4299 13:14:47.567499 RX Delay -179 -> 252, step: 8
4300 13:14:47.570947 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4301 13:14:47.577637 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4302 13:14:47.581055 iDelay=205, Bit 2, Center 44 (-107 ~ 196) 304
4303 13:14:47.584191 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4304 13:14:47.587630 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4305 13:14:47.590947 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4306 13:14:47.597777 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4307 13:14:47.601151 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4308 13:14:47.604411 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4309 13:14:47.607681 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4310 13:14:47.610954 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4311 13:14:47.617815 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4312 13:14:47.620974 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4313 13:14:47.624214 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4314 13:14:47.628138 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4315 13:14:47.631239 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4316 13:14:47.634658 ==
4317 13:14:47.637801 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 13:14:47.641079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 13:14:47.641164 ==
4320 13:14:47.641224 DQS Delay:
4321 13:14:47.644865 DQS0 = 0, DQS1 = 0
4322 13:14:47.644939 DQM Delay:
4323 13:14:47.647772 DQM0 = 47, DQM1 = 40
4324 13:14:47.647847 DQ Delay:
4325 13:14:47.651315 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4326 13:14:47.654295 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4327 13:14:47.657769 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4328 13:14:47.660833 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4329 13:14:47.660908
4330 13:14:47.660967
4331 13:14:47.667641 [DQSOSCAuto] RK1, (LSB)MR18= 0x6531, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4332 13:14:47.671139 CH0 RK1: MR19=808, MR18=6531
4333 13:14:47.677749 CH0_RK1: MR19=0x808, MR18=0x6531, DQSOSC=390, MR23=63, INC=172, DEC=114
4334 13:14:47.681266 [RxdqsGatingPostProcess] freq 600
4335 13:14:47.687712 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4336 13:14:47.687787 Pre-setting of DQS Precalculation
4337 13:14:47.694503 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4338 13:14:47.694578 ==
4339 13:14:47.697864 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 13:14:47.701087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 13:14:47.701169 ==
4342 13:14:47.707799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4343 13:14:47.714067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4344 13:14:47.717536 [CA 0] Center 35 (5~66) winsize 62
4345 13:14:47.720907 [CA 1] Center 35 (5~66) winsize 62
4346 13:14:47.724465 [CA 2] Center 34 (3~65) winsize 63
4347 13:14:47.727984 [CA 3] Center 33 (3~64) winsize 62
4348 13:14:47.731133 [CA 4] Center 34 (3~65) winsize 63
4349 13:14:47.734272 [CA 5] Center 33 (3~64) winsize 62
4350 13:14:47.734348
4351 13:14:47.737753 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4352 13:14:47.737828
4353 13:14:47.740938 [CATrainingPosCal] consider 1 rank data
4354 13:14:47.744297 u2DelayCellTimex100 = 270/100 ps
4355 13:14:47.747755 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4356 13:14:47.750784 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4357 13:14:47.754420 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4358 13:14:47.757837 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4359 13:14:47.760907 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4360 13:14:47.764381 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4361 13:14:47.764456
4362 13:14:47.767598 CA PerBit enable=1, Macro0, CA PI delay=33
4363 13:14:47.771028
4364 13:14:47.771102 [CBTSetCACLKResult] CA Dly = 33
4365 13:14:47.774477 CS Dly: 4 (0~35)
4366 13:14:47.774551 ==
4367 13:14:47.777532 Dram Type= 6, Freq= 0, CH_1, rank 1
4368 13:14:47.781158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 13:14:47.781234 ==
4370 13:14:47.787731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 13:14:47.794374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4372 13:14:47.797541 [CA 0] Center 35 (5~66) winsize 62
4373 13:14:47.801018 [CA 1] Center 35 (5~66) winsize 62
4374 13:14:47.804149 [CA 2] Center 34 (4~65) winsize 62
4375 13:14:47.807998 [CA 3] Center 34 (4~64) winsize 61
4376 13:14:47.810973 [CA 4] Center 34 (4~64) winsize 61
4377 13:14:47.814258 [CA 5] Center 33 (3~64) winsize 62
4378 13:14:47.814349
4379 13:14:47.817508 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4380 13:14:47.817579
4381 13:14:47.820794 [CATrainingPosCal] consider 2 rank data
4382 13:14:47.824401 u2DelayCellTimex100 = 270/100 ps
4383 13:14:47.827742 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4384 13:14:47.831182 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 13:14:47.834156 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 13:14:47.837749 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4387 13:14:47.840648 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4388 13:14:47.843964 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 13:14:47.844032
4390 13:14:47.851053 CA PerBit enable=1, Macro0, CA PI delay=33
4391 13:14:47.851123
4392 13:14:47.851200 [CBTSetCACLKResult] CA Dly = 33
4393 13:14:47.854236 CS Dly: 5 (0~37)
4394 13:14:47.854301
4395 13:14:47.857235 ----->DramcWriteLeveling(PI) begin...
4396 13:14:47.857325 ==
4397 13:14:47.860580 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 13:14:47.864111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 13:14:47.864204 ==
4400 13:14:47.867706 Write leveling (Byte 0): 31 => 31
4401 13:14:47.870799 Write leveling (Byte 1): 32 => 32
4402 13:14:47.874432 DramcWriteLeveling(PI) end<-----
4403 13:14:47.874499
4404 13:14:47.874572 ==
4405 13:14:47.877160 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 13:14:47.880759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 13:14:47.883847 ==
4408 13:14:47.883939 [Gating] SW mode calibration
4409 13:14:47.893817 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4410 13:14:47.897383 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4411 13:14:47.900665 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 13:14:47.907061 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 13:14:47.910618 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4414 13:14:47.914150 0 9 12 | B1->B0 | 2a2a 2e2e | 0 0 | (1 0) (1 1)
4415 13:14:47.920498 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 13:14:47.923864 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 13:14:47.926872 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 13:14:47.933800 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 13:14:47.936882 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 13:14:47.940628 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 13:14:47.947088 0 10 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4422 13:14:47.950740 0 10 12 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
4423 13:14:47.953663 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 13:14:47.960462 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 13:14:47.963785 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 13:14:47.967527 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 13:14:47.973715 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 13:14:47.976944 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 13:14:47.980316 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 13:14:47.983505 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4431 13:14:47.990197 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 13:14:47.993563 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 13:14:47.997400 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 13:14:48.003726 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 13:14:48.006674 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 13:14:48.010166 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 13:14:48.016858 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 13:14:48.020562 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 13:14:48.023740 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 13:14:48.030025 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 13:14:48.033439 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 13:14:48.036723 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 13:14:48.043317 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 13:14:48.046702 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 13:14:48.050086 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4446 13:14:48.056765 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4447 13:14:48.060219 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 13:14:48.063292 Total UI for P1: 0, mck2ui 16
4449 13:14:48.066822 best dqsien dly found for B0: ( 0, 13, 10)
4450 13:14:48.070113 Total UI for P1: 0, mck2ui 16
4451 13:14:48.073512 best dqsien dly found for B1: ( 0, 13, 12)
4452 13:14:48.077077 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4453 13:14:48.080209 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4454 13:14:48.080316
4455 13:14:48.083297 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4456 13:14:48.087043 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4457 13:14:48.090116 [Gating] SW calibration Done
4458 13:14:48.090241 ==
4459 13:14:48.093191 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 13:14:48.096844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 13:14:48.100188 ==
4462 13:14:48.100348 RX Vref Scan: 0
4463 13:14:48.100472
4464 13:14:48.103727 RX Vref 0 -> 0, step: 1
4465 13:14:48.103911
4466 13:14:48.107094 RX Delay -230 -> 252, step: 16
4467 13:14:48.110240 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4468 13:14:48.113378 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4469 13:14:48.116780 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4470 13:14:48.123218 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4471 13:14:48.126943 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4472 13:14:48.129766 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4473 13:14:48.133144 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4474 13:14:48.136753 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4475 13:14:48.142965 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4476 13:14:48.146547 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4477 13:14:48.149928 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4478 13:14:48.152898 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4479 13:14:48.160049 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4480 13:14:48.163113 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4481 13:14:48.166564 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4482 13:14:48.169795 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4483 13:14:48.169871 ==
4484 13:14:48.172933 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 13:14:48.179910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 13:14:48.179986 ==
4487 13:14:48.180045 DQS Delay:
4488 13:14:48.182943 DQS0 = 0, DQS1 = 0
4489 13:14:48.183019 DQM Delay:
4490 13:14:48.183079 DQM0 = 51, DQM1 = 43
4491 13:14:48.186295 DQ Delay:
4492 13:14:48.190056 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4493 13:14:48.192757 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4494 13:14:48.196441 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4495 13:14:48.199668 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4496 13:14:48.199743
4497 13:14:48.199802
4498 13:14:48.199857 ==
4499 13:14:48.202857 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 13:14:48.206321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 13:14:48.206424 ==
4502 13:14:48.206493
4503 13:14:48.206548
4504 13:14:48.209449 TX Vref Scan disable
4505 13:14:48.209524 == TX Byte 0 ==
4506 13:14:48.216569 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4507 13:14:48.219312 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4508 13:14:48.219411 == TX Byte 1 ==
4509 13:14:48.226101 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4510 13:14:48.229532 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4511 13:14:48.229648 ==
4512 13:14:48.232701 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 13:14:48.236380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 13:14:48.236497 ==
4515 13:14:48.236589
4516 13:14:48.239466
4517 13:14:48.239566 TX Vref Scan disable
4518 13:14:48.242688 == TX Byte 0 ==
4519 13:14:48.246283 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4520 13:14:48.249626 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4521 13:14:48.252849 == TX Byte 1 ==
4522 13:14:48.256396 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4523 13:14:48.259830 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4524 13:14:48.262909
4525 13:14:48.262984 [DATLAT]
4526 13:14:48.263045 Freq=600, CH1 RK0
4527 13:14:48.263104
4528 13:14:48.266447 DATLAT Default: 0x9
4529 13:14:48.266523 0, 0xFFFF, sum = 0
4530 13:14:48.269775 1, 0xFFFF, sum = 0
4531 13:14:48.269852 2, 0xFFFF, sum = 0
4532 13:14:48.273344 3, 0xFFFF, sum = 0
4533 13:14:48.273421 4, 0xFFFF, sum = 0
4534 13:14:48.276233 5, 0xFFFF, sum = 0
4535 13:14:48.276310 6, 0xFFFF, sum = 0
4536 13:14:48.279428 7, 0xFFFF, sum = 0
4537 13:14:48.279506 8, 0x0, sum = 1
4538 13:14:48.282773 9, 0x0, sum = 2
4539 13:14:48.282850 10, 0x0, sum = 3
4540 13:14:48.286214 11, 0x0, sum = 4
4541 13:14:48.286292 best_step = 9
4542 13:14:48.286350
4543 13:14:48.286405 ==
4544 13:14:48.289585 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 13:14:48.296098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 13:14:48.296175 ==
4547 13:14:48.296234 RX Vref Scan: 1
4548 13:14:48.296290
4549 13:14:48.299631 RX Vref 0 -> 0, step: 1
4550 13:14:48.299706
4551 13:14:48.302945 RX Delay -163 -> 252, step: 8
4552 13:14:48.303020
4553 13:14:48.306193 Set Vref, RX VrefLevel [Byte0]: 52
4554 13:14:48.309487 [Byte1]: 50
4555 13:14:48.309583
4556 13:14:48.312878 Final RX Vref Byte 0 = 52 to rank0
4557 13:14:48.316216 Final RX Vref Byte 1 = 50 to rank0
4558 13:14:48.319588 Final RX Vref Byte 0 = 52 to rank1
4559 13:14:48.322848 Final RX Vref Byte 1 = 50 to rank1==
4560 13:14:48.326160 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 13:14:48.329432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 13:14:48.329523 ==
4563 13:14:48.332666 DQS Delay:
4564 13:14:48.332750 DQS0 = 0, DQS1 = 0
4565 13:14:48.332805 DQM Delay:
4566 13:14:48.336044 DQM0 = 48, DQM1 = 41
4567 13:14:48.336131 DQ Delay:
4568 13:14:48.339521 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4569 13:14:48.342747 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4570 13:14:48.346107 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4571 13:14:48.349474 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =48
4572 13:14:48.349536
4573 13:14:48.349588
4574 13:14:48.359547 [DQSOSCAuto] RK0, (LSB)MR18= 0x5178, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4575 13:14:48.359614 CH1 RK0: MR19=808, MR18=5178
4576 13:14:48.366388 CH1_RK0: MR19=0x808, MR18=0x5178, DQSOSC=387, MR23=63, INC=175, DEC=116
4577 13:14:48.366458
4578 13:14:48.369449 ----->DramcWriteLeveling(PI) begin...
4579 13:14:48.369514 ==
4580 13:14:48.372880 Dram Type= 6, Freq= 0, CH_1, rank 1
4581 13:14:48.379962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 13:14:48.380035 ==
4583 13:14:48.382847 Write leveling (Byte 0): 28 => 28
4584 13:14:48.386134 Write leveling (Byte 1): 30 => 30
4585 13:14:48.386197 DramcWriteLeveling(PI) end<-----
4586 13:14:48.386256
4587 13:14:48.389455 ==
4588 13:14:48.393010 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 13:14:48.396261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 13:14:48.396347 ==
4591 13:14:48.399539 [Gating] SW mode calibration
4592 13:14:48.406122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4593 13:14:48.409369 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4594 13:14:48.416198 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 13:14:48.419460 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 13:14:48.422660 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4597 13:14:48.429394 0 9 12 | B1->B0 | 2c2c 3232 | 1 1 | (1 0) (1 0)
4598 13:14:48.432785 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 13:14:48.436115 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 13:14:48.442684 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 13:14:48.446004 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 13:14:48.449643 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 13:14:48.455931 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 13:14:48.459456 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 13:14:48.462878 0 10 12 | B1->B0 | 4040 3030 | 0 0 | (0 0) (1 1)
4606 13:14:48.469375 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 13:14:48.472652 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 13:14:48.476111 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 13:14:48.479184 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 13:14:48.485979 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 13:14:48.489163 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 13:14:48.492399 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 13:14:48.499596 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4614 13:14:48.502564 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 13:14:48.505773 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 13:14:48.512953 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 13:14:48.515799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 13:14:48.519419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 13:14:48.526345 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 13:14:48.529005 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 13:14:48.532386 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 13:14:48.538985 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 13:14:48.542662 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 13:14:48.545891 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 13:14:48.552485 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 13:14:48.555747 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 13:14:48.558922 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 13:14:48.565657 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4629 13:14:48.568853 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4630 13:14:48.572119 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 13:14:48.575784 Total UI for P1: 0, mck2ui 16
4632 13:14:48.578979 best dqsien dly found for B0: ( 0, 13, 12)
4633 13:14:48.582157 Total UI for P1: 0, mck2ui 16
4634 13:14:48.585428 best dqsien dly found for B1: ( 0, 13, 10)
4635 13:14:48.589016 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4636 13:14:48.592311 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4637 13:14:48.592379
4638 13:14:48.598651 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4639 13:14:48.601999 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4640 13:14:48.602086 [Gating] SW calibration Done
4641 13:14:48.605675 ==
4642 13:14:48.608979 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 13:14:48.612329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 13:14:48.612392 ==
4645 13:14:48.612445 RX Vref Scan: 0
4646 13:14:48.612497
4647 13:14:48.615429 RX Vref 0 -> 0, step: 1
4648 13:14:48.615490
4649 13:14:48.618601 RX Delay -230 -> 252, step: 16
4650 13:14:48.622368 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4651 13:14:48.625301 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4652 13:14:48.631880 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4653 13:14:48.635237 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4654 13:14:48.638430 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4655 13:14:48.641981 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4656 13:14:48.645158 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4657 13:14:48.651922 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4658 13:14:48.655341 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4659 13:14:48.658543 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4660 13:14:48.661733 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4661 13:14:48.668533 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4662 13:14:48.672404 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4663 13:14:48.675090 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4664 13:14:48.678991 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4665 13:14:48.685106 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4666 13:14:48.685205 ==
4667 13:14:48.688355 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 13:14:48.692257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 13:14:48.692334 ==
4670 13:14:48.692394 DQS Delay:
4671 13:14:48.695198 DQS0 = 0, DQS1 = 0
4672 13:14:48.695274 DQM Delay:
4673 13:14:48.698494 DQM0 = 51, DQM1 = 46
4674 13:14:48.698569 DQ Delay:
4675 13:14:48.701778 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4676 13:14:48.705110 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4677 13:14:48.708759 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4678 13:14:48.712195 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4679 13:14:48.712269
4680 13:14:48.712328
4681 13:14:48.712383 ==
4682 13:14:48.715309 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 13:14:48.718596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 13:14:48.718672 ==
4685 13:14:48.718731
4686 13:14:48.718784
4687 13:14:48.721669 TX Vref Scan disable
4688 13:14:48.725118 == TX Byte 0 ==
4689 13:14:48.728911 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4690 13:14:48.732175 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4691 13:14:48.735276 == TX Byte 1 ==
4692 13:14:48.738751 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4693 13:14:48.741827 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4694 13:14:48.741903 ==
4695 13:14:48.745310 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 13:14:48.751798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 13:14:48.751874 ==
4698 13:14:48.751933
4699 13:14:48.751987
4700 13:14:48.752039 TX Vref Scan disable
4701 13:14:48.755849 == TX Byte 0 ==
4702 13:14:48.758949 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4703 13:14:48.765604 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4704 13:14:48.765681 == TX Byte 1 ==
4705 13:14:48.769490 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4706 13:14:48.775583 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4707 13:14:48.775659
4708 13:14:48.775733 [DATLAT]
4709 13:14:48.775808 Freq=600, CH1 RK1
4710 13:14:48.775897
4711 13:14:48.779025 DATLAT Default: 0x9
4712 13:14:48.779093 0, 0xFFFF, sum = 0
4713 13:14:48.782271 1, 0xFFFF, sum = 0
4714 13:14:48.782362 2, 0xFFFF, sum = 0
4715 13:14:48.785610 3, 0xFFFF, sum = 0
4716 13:14:48.788947 4, 0xFFFF, sum = 0
4717 13:14:48.789017 5, 0xFFFF, sum = 0
4718 13:14:48.792357 6, 0xFFFF, sum = 0
4719 13:14:48.792428 7, 0xFFFF, sum = 0
4720 13:14:48.795500 8, 0x0, sum = 1
4721 13:14:48.795579 9, 0x0, sum = 2
4722 13:14:48.795640 10, 0x0, sum = 3
4723 13:14:48.798916 11, 0x0, sum = 4
4724 13:14:48.798993 best_step = 9
4725 13:14:48.799052
4726 13:14:48.799106 ==
4727 13:14:48.802441 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 13:14:48.808785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 13:14:48.808862 ==
4730 13:14:48.808922 RX Vref Scan: 0
4731 13:14:48.808977
4732 13:14:48.812212 RX Vref 0 -> 0, step: 1
4733 13:14:48.812288
4734 13:14:48.815465 RX Delay -163 -> 252, step: 8
4735 13:14:48.819074 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4736 13:14:48.825457 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4737 13:14:48.828810 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4738 13:14:48.832283 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4739 13:14:48.835247 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4740 13:14:48.838877 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4741 13:14:48.845339 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4742 13:14:48.848896 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4743 13:14:48.852152 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4744 13:14:48.855816 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4745 13:14:48.858878 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4746 13:14:48.865864 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4747 13:14:48.868956 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4748 13:14:48.872058 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4749 13:14:48.875470 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4750 13:14:48.878901 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4751 13:14:48.882427 ==
4752 13:14:48.885560 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 13:14:48.888672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 13:14:48.888749 ==
4755 13:14:48.888810 DQS Delay:
4756 13:14:48.892154 DQS0 = 0, DQS1 = 0
4757 13:14:48.892231 DQM Delay:
4758 13:14:48.895574 DQM0 = 49, DQM1 = 43
4759 13:14:48.895651 DQ Delay:
4760 13:14:48.898773 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4761 13:14:48.902045 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4762 13:14:48.905211 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4763 13:14:48.908894 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4764 13:14:48.908993
4765 13:14:48.909086
4766 13:14:48.915661 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4767 13:14:48.918601 CH1 RK1: MR19=808, MR18=5B22
4768 13:14:48.925326 CH1_RK1: MR19=0x808, MR18=0x5B22, DQSOSC=392, MR23=63, INC=170, DEC=113
4769 13:14:48.928987 [RxdqsGatingPostProcess] freq 600
4770 13:14:48.935516 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4771 13:14:48.935609 Pre-setting of DQS Precalculation
4772 13:14:48.942225 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4773 13:14:48.948725 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4774 13:14:48.955546 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4775 13:14:48.955629
4776 13:14:48.955703
4777 13:14:48.958719 [Calibration Summary] 1200 Mbps
4778 13:14:48.962296 CH 0, Rank 0
4779 13:14:48.962362 SW Impedance : PASS
4780 13:14:48.965311 DUTY Scan : NO K
4781 13:14:48.965383 ZQ Calibration : PASS
4782 13:14:48.968516 Jitter Meter : NO K
4783 13:14:48.971863 CBT Training : PASS
4784 13:14:48.971931 Write leveling : PASS
4785 13:14:48.975516 RX DQS gating : PASS
4786 13:14:48.978463 RX DQ/DQS(RDDQC) : PASS
4787 13:14:48.978529 TX DQ/DQS : PASS
4788 13:14:48.981885 RX DATLAT : PASS
4789 13:14:48.985025 RX DQ/DQS(Engine): PASS
4790 13:14:48.985114 TX OE : NO K
4791 13:14:48.988512 All Pass.
4792 13:14:48.988602
4793 13:14:48.988689 CH 0, Rank 1
4794 13:14:48.991829 SW Impedance : PASS
4795 13:14:48.991894 DUTY Scan : NO K
4796 13:14:48.994971 ZQ Calibration : PASS
4797 13:14:48.998450 Jitter Meter : NO K
4798 13:14:48.998515 CBT Training : PASS
4799 13:14:49.001878 Write leveling : PASS
4800 13:14:49.005479 RX DQS gating : PASS
4801 13:14:49.005549 RX DQ/DQS(RDDQC) : PASS
4802 13:14:49.008617 TX DQ/DQS : PASS
4803 13:14:49.008684 RX DATLAT : PASS
4804 13:14:49.012157 RX DQ/DQS(Engine): PASS
4805 13:14:49.015357 TX OE : NO K
4806 13:14:49.015446 All Pass.
4807 13:14:49.015517
4808 13:14:49.015586 CH 1, Rank 0
4809 13:14:49.019090 SW Impedance : PASS
4810 13:14:49.021820 DUTY Scan : NO K
4811 13:14:49.021911 ZQ Calibration : PASS
4812 13:14:49.025027 Jitter Meter : NO K
4813 13:14:49.028416 CBT Training : PASS
4814 13:14:49.028486 Write leveling : PASS
4815 13:14:49.032144 RX DQS gating : PASS
4816 13:14:49.034808 RX DQ/DQS(RDDQC) : PASS
4817 13:14:49.034889 TX DQ/DQS : PASS
4818 13:14:49.038303 RX DATLAT : PASS
4819 13:14:49.041768 RX DQ/DQS(Engine): PASS
4820 13:14:49.041837 TX OE : NO K
4821 13:14:49.044801 All Pass.
4822 13:14:49.044888
4823 13:14:49.044975 CH 1, Rank 1
4824 13:14:49.048694 SW Impedance : PASS
4825 13:14:49.048782 DUTY Scan : NO K
4826 13:14:49.051811 ZQ Calibration : PASS
4827 13:14:49.054978 Jitter Meter : NO K
4828 13:14:49.055066 CBT Training : PASS
4829 13:14:49.058504 Write leveling : PASS
4830 13:14:49.058573 RX DQS gating : PASS
4831 13:14:49.061952 RX DQ/DQS(RDDQC) : PASS
4832 13:14:49.065164 TX DQ/DQS : PASS
4833 13:14:49.065241 RX DATLAT : PASS
4834 13:14:49.068181 RX DQ/DQS(Engine): PASS
4835 13:14:49.071685 TX OE : NO K
4836 13:14:49.071761 All Pass.
4837 13:14:49.071820
4838 13:14:49.074876 DramC Write-DBI off
4839 13:14:49.074977 PER_BANK_REFRESH: Hybrid Mode
4840 13:14:49.078244 TX_TRACKING: ON
4841 13:14:49.084868 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4842 13:14:49.091927 [FAST_K] Save calibration result to emmc
4843 13:14:49.095011 dramc_set_vcore_voltage set vcore to 662500
4844 13:14:49.095080 Read voltage for 933, 3
4845 13:14:49.098235 Vio18 = 0
4846 13:14:49.098301 Vcore = 662500
4847 13:14:49.098372 Vdram = 0
4848 13:14:49.102198 Vddq = 0
4849 13:14:49.102288 Vmddr = 0
4850 13:14:49.105114 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4851 13:14:49.111638 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4852 13:14:49.114942 MEM_TYPE=3, freq_sel=17
4853 13:14:49.118216 sv_algorithm_assistance_LP4_1600
4854 13:14:49.121450 ============ PULL DRAM RESETB DOWN ============
4855 13:14:49.124854 ========== PULL DRAM RESETB DOWN end =========
4856 13:14:49.131692 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4857 13:14:49.131786 ===================================
4858 13:14:49.134955 LPDDR4 DRAM CONFIGURATION
4859 13:14:49.138406 ===================================
4860 13:14:49.141526 EX_ROW_EN[0] = 0x0
4861 13:14:49.141597 EX_ROW_EN[1] = 0x0
4862 13:14:49.144792 LP4Y_EN = 0x0
4863 13:14:49.144883 WORK_FSP = 0x0
4864 13:14:49.148321 WL = 0x3
4865 13:14:49.148385 RL = 0x3
4866 13:14:49.151410 BL = 0x2
4867 13:14:49.151482 RPST = 0x0
4868 13:14:49.155011 RD_PRE = 0x0
4869 13:14:49.155076 WR_PRE = 0x1
4870 13:14:49.157990 WR_PST = 0x0
4871 13:14:49.161413 DBI_WR = 0x0
4872 13:14:49.161479 DBI_RD = 0x0
4873 13:14:49.165050 OTF = 0x1
4874 13:14:49.168593 ===================================
4875 13:14:49.171903 ===================================
4876 13:14:49.171971 ANA top config
4877 13:14:49.174621 ===================================
4878 13:14:49.178285 DLL_ASYNC_EN = 0
4879 13:14:49.178373 ALL_SLAVE_EN = 1
4880 13:14:49.181670 NEW_RANK_MODE = 1
4881 13:14:49.184646 DLL_IDLE_MODE = 1
4882 13:14:49.188022 LP45_APHY_COMB_EN = 1
4883 13:14:49.191375 TX_ODT_DIS = 1
4884 13:14:49.191464 NEW_8X_MODE = 1
4885 13:14:49.194668 ===================================
4886 13:14:49.197996 ===================================
4887 13:14:49.201066 data_rate = 1866
4888 13:14:49.204717 CKR = 1
4889 13:14:49.207682 DQ_P2S_RATIO = 8
4890 13:14:49.211577 ===================================
4891 13:14:49.214416 CA_P2S_RATIO = 8
4892 13:14:49.218004 DQ_CA_OPEN = 0
4893 13:14:49.218092 DQ_SEMI_OPEN = 0
4894 13:14:49.221019 CA_SEMI_OPEN = 0
4895 13:14:49.224423 CA_FULL_RATE = 0
4896 13:14:49.227855 DQ_CKDIV4_EN = 1
4897 13:14:49.231096 CA_CKDIV4_EN = 1
4898 13:14:49.234343 CA_PREDIV_EN = 0
4899 13:14:49.234433 PH8_DLY = 0
4900 13:14:49.237729 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4901 13:14:49.241087 DQ_AAMCK_DIV = 4
4902 13:14:49.244486 CA_AAMCK_DIV = 4
4903 13:14:49.247694 CA_ADMCK_DIV = 4
4904 13:14:49.250899 DQ_TRACK_CA_EN = 0
4905 13:14:49.250992 CA_PICK = 933
4906 13:14:49.254197 CA_MCKIO = 933
4907 13:14:49.257508 MCKIO_SEMI = 0
4908 13:14:49.260930 PLL_FREQ = 3732
4909 13:14:49.264327 DQ_UI_PI_RATIO = 32
4910 13:14:49.267641 CA_UI_PI_RATIO = 0
4911 13:14:49.271221 ===================================
4912 13:14:49.274196 ===================================
4913 13:14:49.274266 memory_type:LPDDR4
4914 13:14:49.277547 GP_NUM : 10
4915 13:14:49.280746 SRAM_EN : 1
4916 13:14:49.280809 MD32_EN : 0
4917 13:14:49.284431 ===================================
4918 13:14:49.287702 [ANA_INIT] >>>>>>>>>>>>>>
4919 13:14:49.290785 <<<<<< [CONFIGURE PHASE]: ANA_TX
4920 13:14:49.294184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4921 13:14:49.297350 ===================================
4922 13:14:49.301048 data_rate = 1866,PCW = 0X8f00
4923 13:14:49.304264 ===================================
4924 13:14:49.307700 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4925 13:14:49.310752 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 13:14:49.317274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 13:14:49.320760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4928 13:14:49.327514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4929 13:14:49.331008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4930 13:14:49.331084 [ANA_INIT] flow start
4931 13:14:49.334120 [ANA_INIT] PLL >>>>>>>>
4932 13:14:49.337487 [ANA_INIT] PLL <<<<<<<<
4933 13:14:49.337562 [ANA_INIT] MIDPI >>>>>>>>
4934 13:14:49.340683 [ANA_INIT] MIDPI <<<<<<<<
4935 13:14:49.343936 [ANA_INIT] DLL >>>>>>>>
4936 13:14:49.344011 [ANA_INIT] flow end
4937 13:14:49.347285 ============ LP4 DIFF to SE enter ============
4938 13:14:49.354111 ============ LP4 DIFF to SE exit ============
4939 13:14:49.354187 [ANA_INIT] <<<<<<<<<<<<<
4940 13:14:49.357566 [Flow] Enable top DCM control >>>>>
4941 13:14:49.360572 [Flow] Enable top DCM control <<<<<
4942 13:14:49.364050 Enable DLL master slave shuffle
4943 13:14:49.370986 ==============================================================
4944 13:14:49.371063 Gating Mode config
4945 13:14:49.377394 ==============================================================
4946 13:14:49.380497 Config description:
4947 13:14:49.391078 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4948 13:14:49.397601 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4949 13:14:49.400496 SELPH_MODE 0: By rank 1: By Phase
4950 13:14:49.407262 ==============================================================
4951 13:14:49.410597 GAT_TRACK_EN = 1
4952 13:14:49.410672 RX_GATING_MODE = 2
4953 13:14:49.414106 RX_GATING_TRACK_MODE = 2
4954 13:14:49.417727 SELPH_MODE = 1
4955 13:14:49.420461 PICG_EARLY_EN = 1
4956 13:14:49.424304 VALID_LAT_VALUE = 1
4957 13:14:49.430787 ==============================================================
4958 13:14:49.434336 Enter into Gating configuration >>>>
4959 13:14:49.437251 Exit from Gating configuration <<<<
4960 13:14:49.440858 Enter into DVFS_PRE_config >>>>>
4961 13:14:49.450707 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4962 13:14:49.453709 Exit from DVFS_PRE_config <<<<<
4963 13:14:49.457430 Enter into PICG configuration >>>>
4964 13:14:49.460447 Exit from PICG configuration <<<<
4965 13:14:49.463740 [RX_INPUT] configuration >>>>>
4966 13:14:49.467198 [RX_INPUT] configuration <<<<<
4967 13:14:49.470469 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4968 13:14:49.477107 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4969 13:14:49.483935 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 13:14:49.487413 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 13:14:49.493641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 13:14:49.500284 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 13:14:49.503764 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4974 13:14:49.507039 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4975 13:14:49.513784 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4976 13:14:49.517245 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4977 13:14:49.520340 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4978 13:14:49.526872 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4979 13:14:49.530283 ===================================
4980 13:14:49.530351 LPDDR4 DRAM CONFIGURATION
4981 13:14:49.533601 ===================================
4982 13:14:49.537368 EX_ROW_EN[0] = 0x0
4983 13:14:49.540415 EX_ROW_EN[1] = 0x0
4984 13:14:49.540504 LP4Y_EN = 0x0
4985 13:14:49.543610 WORK_FSP = 0x0
4986 13:14:49.543676 WL = 0x3
4987 13:14:49.547259 RL = 0x3
4988 13:14:49.547325 BL = 0x2
4989 13:14:49.550247 RPST = 0x0
4990 13:14:49.550315 RD_PRE = 0x0
4991 13:14:49.553803 WR_PRE = 0x1
4992 13:14:49.553870 WR_PST = 0x0
4993 13:14:49.556843 DBI_WR = 0x0
4994 13:14:49.556934 DBI_RD = 0x0
4995 13:14:49.560441 OTF = 0x1
4996 13:14:49.563874 ===================================
4997 13:14:49.567429 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4998 13:14:49.570489 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4999 13:14:49.573982 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 13:14:49.577235 ===================================
5001 13:14:49.580503 LPDDR4 DRAM CONFIGURATION
5002 13:14:49.583698 ===================================
5003 13:14:49.586961 EX_ROW_EN[0] = 0x10
5004 13:14:49.587031 EX_ROW_EN[1] = 0x0
5005 13:14:49.590533 LP4Y_EN = 0x0
5006 13:14:49.590602 WORK_FSP = 0x0
5007 13:14:49.593839 WL = 0x3
5008 13:14:49.593905 RL = 0x3
5009 13:14:49.597205 BL = 0x2
5010 13:14:49.597271 RPST = 0x0
5011 13:14:49.600654 RD_PRE = 0x0
5012 13:14:49.600718 WR_PRE = 0x1
5013 13:14:49.603868 WR_PST = 0x0
5014 13:14:49.603958 DBI_WR = 0x0
5015 13:14:49.607226 DBI_RD = 0x0
5016 13:14:49.610278 OTF = 0x1
5017 13:14:49.613657 ===================================
5018 13:14:49.616822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5019 13:14:49.622401 nWR fixed to 30
5020 13:14:49.625489 [ModeRegInit_LP4] CH0 RK0
5021 13:14:49.625572 [ModeRegInit_LP4] CH0 RK1
5022 13:14:49.628705 [ModeRegInit_LP4] CH1 RK0
5023 13:14:49.632485 [ModeRegInit_LP4] CH1 RK1
5024 13:14:49.632552 match AC timing 9
5025 13:14:49.639258 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5026 13:14:49.641992 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5027 13:14:49.645307 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5028 13:14:49.651903 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5029 13:14:49.655186 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5030 13:14:49.655257 ==
5031 13:14:49.658784 Dram Type= 6, Freq= 0, CH_0, rank 0
5032 13:14:49.661978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5033 13:14:49.662046 ==
5034 13:14:49.668499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5035 13:14:49.675736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5036 13:14:49.678360 [CA 0] Center 38 (7~69) winsize 63
5037 13:14:49.682187 [CA 1] Center 38 (8~69) winsize 62
5038 13:14:49.685306 [CA 2] Center 35 (5~66) winsize 62
5039 13:14:49.688511 [CA 3] Center 35 (5~65) winsize 61
5040 13:14:49.692042 [CA 4] Center 34 (4~65) winsize 62
5041 13:14:49.695237 [CA 5] Center 33 (3~64) winsize 62
5042 13:14:49.695329
5043 13:14:49.698991 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5044 13:14:49.699060
5045 13:14:49.702101 [CATrainingPosCal] consider 1 rank data
5046 13:14:49.705148 u2DelayCellTimex100 = 270/100 ps
5047 13:14:49.708887 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5048 13:14:49.712325 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5049 13:14:49.715244 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5050 13:14:49.718412 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5051 13:14:49.721769 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5052 13:14:49.725428 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5053 13:14:49.728883
5054 13:14:49.732024 CA PerBit enable=1, Macro0, CA PI delay=33
5055 13:14:49.732097
5056 13:14:49.735030 [CBTSetCACLKResult] CA Dly = 33
5057 13:14:49.735121 CS Dly: 7 (0~38)
5058 13:14:49.735194 ==
5059 13:14:49.738320 Dram Type= 6, Freq= 0, CH_0, rank 1
5060 13:14:49.741585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 13:14:49.741657 ==
5062 13:14:49.748355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 13:14:49.755028 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5064 13:14:49.758475 [CA 0] Center 38 (8~69) winsize 62
5065 13:14:49.761594 [CA 1] Center 38 (8~69) winsize 62
5066 13:14:49.765011 [CA 2] Center 36 (6~66) winsize 61
5067 13:14:49.768366 [CA 3] Center 35 (5~66) winsize 62
5068 13:14:49.771533 [CA 4] Center 34 (4~65) winsize 62
5069 13:14:49.774774 [CA 5] Center 34 (4~65) winsize 62
5070 13:14:49.774844
5071 13:14:49.778150 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5072 13:14:49.778219
5073 13:14:49.781756 [CATrainingPosCal] consider 2 rank data
5074 13:14:49.784934 u2DelayCellTimex100 = 270/100 ps
5075 13:14:49.788285 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5076 13:14:49.791653 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5077 13:14:49.795023 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5078 13:14:49.798218 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5079 13:14:49.801665 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5080 13:14:49.808163 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5081 13:14:49.808234
5082 13:14:49.811660 CA PerBit enable=1, Macro0, CA PI delay=34
5083 13:14:49.811731
5084 13:14:49.814879 [CBTSetCACLKResult] CA Dly = 34
5085 13:14:49.814949 CS Dly: 7 (0~39)
5086 13:14:49.815021
5087 13:14:49.818025 ----->DramcWriteLeveling(PI) begin...
5088 13:14:49.818094 ==
5089 13:14:49.821634 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 13:14:49.828586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 13:14:49.828659 ==
5092 13:14:49.831545 Write leveling (Byte 0): 33 => 33
5093 13:14:49.831637 Write leveling (Byte 1): 29 => 29
5094 13:14:49.834857 DramcWriteLeveling(PI) end<-----
5095 13:14:49.834927
5096 13:14:49.834998 ==
5097 13:14:49.838288 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 13:14:49.844923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 13:14:49.845016 ==
5100 13:14:49.847788 [Gating] SW mode calibration
5101 13:14:49.854510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5102 13:14:49.857773 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5103 13:14:49.864691 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5104 13:14:49.867914 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 13:14:49.871719 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 13:14:49.878353 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 13:14:49.881481 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 13:14:49.884550 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 13:14:49.891047 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
5110 13:14:49.894574 0 14 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
5111 13:14:49.897955 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
5112 13:14:49.901506 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 13:14:49.907683 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 13:14:49.911228 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 13:14:49.914548 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 13:14:49.921350 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 13:14:49.924526 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5118 13:14:49.927940 0 15 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
5119 13:14:49.934940 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 13:14:49.937979 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 13:14:49.941095 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 13:14:49.948154 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 13:14:49.951308 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 13:14:49.954450 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 13:14:49.961061 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5126 13:14:49.964435 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5127 13:14:49.967773 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 13:14:49.974666 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 13:14:49.977657 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 13:14:49.981292 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 13:14:49.987645 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 13:14:49.990960 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 13:14:49.994358 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 13:14:50.001057 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 13:14:50.004360 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 13:14:50.007886 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 13:14:50.014634 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 13:14:50.017671 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 13:14:50.021109 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 13:14:50.024458 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 13:14:50.031043 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5142 13:14:50.034285 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5143 13:14:50.037843 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 13:14:50.041444 Total UI for P1: 0, mck2ui 16
5145 13:14:50.044526 best dqsien dly found for B0: ( 1, 2, 26)
5146 13:14:50.051109 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 13:14:50.051190 Total UI for P1: 0, mck2ui 16
5148 13:14:50.057745 best dqsien dly found for B1: ( 1, 3, 0)
5149 13:14:50.061102 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5150 13:14:50.064389 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5151 13:14:50.064480
5152 13:14:50.067651 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5153 13:14:50.070755 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5154 13:14:50.074198 [Gating] SW calibration Done
5155 13:14:50.074282 ==
5156 13:14:50.077381 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 13:14:50.080715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 13:14:50.080811 ==
5159 13:14:50.083858 RX Vref Scan: 0
5160 13:14:50.083924
5161 13:14:50.083998 RX Vref 0 -> 0, step: 1
5162 13:14:50.084086
5163 13:14:50.087304 RX Delay -80 -> 252, step: 8
5164 13:14:50.094063 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5165 13:14:50.097190 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5166 13:14:50.100965 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5167 13:14:50.103819 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5168 13:14:50.107704 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5169 13:14:50.110520 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5170 13:14:50.113903 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5171 13:14:50.120879 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5172 13:14:50.123941 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5173 13:14:50.127403 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5174 13:14:50.130497 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5175 13:14:50.134064 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5176 13:14:50.140853 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5177 13:14:50.143723 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5178 13:14:50.147050 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5179 13:14:50.150858 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5180 13:14:50.150952 ==
5181 13:14:50.153832 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 13:14:50.157541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 13:14:50.157633 ==
5184 13:14:50.160333 DQS Delay:
5185 13:14:50.160398 DQS0 = 0, DQS1 = 0
5186 13:14:50.164059 DQM Delay:
5187 13:14:50.164150 DQM0 = 105, DQM1 = 90
5188 13:14:50.164222 DQ Delay:
5189 13:14:50.167070 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5190 13:14:50.170428 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5191 13:14:50.173793 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5192 13:14:50.177369 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5193 13:14:50.180510
5194 13:14:50.180583
5195 13:14:50.180641 ==
5196 13:14:50.183993 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 13:14:50.187341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 13:14:50.187416 ==
5199 13:14:50.187474
5200 13:14:50.187528
5201 13:14:50.190434 TX Vref Scan disable
5202 13:14:50.190507 == TX Byte 0 ==
5203 13:14:50.197040 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5204 13:14:50.200475 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5205 13:14:50.200574 == TX Byte 1 ==
5206 13:14:50.207284 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5207 13:14:50.210294 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5208 13:14:50.210369 ==
5209 13:14:50.213375 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 13:14:50.216990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 13:14:50.217089 ==
5212 13:14:50.217215
5213 13:14:50.217287
5214 13:14:50.220092 TX Vref Scan disable
5215 13:14:50.223808 == TX Byte 0 ==
5216 13:14:50.226728 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5217 13:14:50.230393 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5218 13:14:50.233339 == TX Byte 1 ==
5219 13:14:50.237051 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5220 13:14:50.240770 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5221 13:14:50.240862
5222 13:14:50.243682 [DATLAT]
5223 13:14:50.243747 Freq=933, CH0 RK0
5224 13:14:50.243803
5225 13:14:50.246864 DATLAT Default: 0xd
5226 13:14:50.246929 0, 0xFFFF, sum = 0
5227 13:14:50.250112 1, 0xFFFF, sum = 0
5228 13:14:50.250178 2, 0xFFFF, sum = 0
5229 13:14:50.253385 3, 0xFFFF, sum = 0
5230 13:14:50.253451 4, 0xFFFF, sum = 0
5231 13:14:50.257247 5, 0xFFFF, sum = 0
5232 13:14:50.257338 6, 0xFFFF, sum = 0
5233 13:14:50.260457 7, 0xFFFF, sum = 0
5234 13:14:50.260547 8, 0xFFFF, sum = 0
5235 13:14:50.263421 9, 0xFFFF, sum = 0
5236 13:14:50.263484 10, 0x0, sum = 1
5237 13:14:50.266919 11, 0x0, sum = 2
5238 13:14:50.266988 12, 0x0, sum = 3
5239 13:14:50.270334 13, 0x0, sum = 4
5240 13:14:50.270426 best_step = 11
5241 13:14:50.270511
5242 13:14:50.270596 ==
5243 13:14:50.273761 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 13:14:50.280481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 13:14:50.280548 ==
5246 13:14:50.280603 RX Vref Scan: 1
5247 13:14:50.280660
5248 13:14:50.283462 RX Vref 0 -> 0, step: 1
5249 13:14:50.283522
5250 13:14:50.286706 RX Delay -53 -> 252, step: 4
5251 13:14:50.286794
5252 13:14:50.290098 Set Vref, RX VrefLevel [Byte0]: 60
5253 13:14:50.293306 [Byte1]: 49
5254 13:14:50.293374
5255 13:14:50.296779 Final RX Vref Byte 0 = 60 to rank0
5256 13:14:50.300307 Final RX Vref Byte 1 = 49 to rank0
5257 13:14:50.303847 Final RX Vref Byte 0 = 60 to rank1
5258 13:14:50.306766 Final RX Vref Byte 1 = 49 to rank1==
5259 13:14:50.309769 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 13:14:50.313487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 13:14:50.313562 ==
5262 13:14:50.316665 DQS Delay:
5263 13:14:50.316801 DQS0 = 0, DQS1 = 0
5264 13:14:50.316892 DQM Delay:
5265 13:14:50.319861 DQM0 = 107, DQM1 = 92
5266 13:14:50.319957 DQ Delay:
5267 13:14:50.323216 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5268 13:14:50.326770 DQ4 =106, DQ5 =98, DQ6 =118, DQ7 =114
5269 13:14:50.330061 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5270 13:14:50.333343 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =100
5271 13:14:50.333412
5272 13:14:50.333469
5273 13:14:50.343581 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5274 13:14:50.346810 CH0 RK0: MR19=505, MR18=2420
5275 13:14:50.353544 CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42
5276 13:14:50.353619
5277 13:14:50.356782 ----->DramcWriteLeveling(PI) begin...
5278 13:14:50.356848 ==
5279 13:14:50.359994 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 13:14:50.363377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 13:14:50.363448 ==
5282 13:14:50.366686 Write leveling (Byte 0): 32 => 32
5283 13:14:50.370221 Write leveling (Byte 1): 29 => 29
5284 13:14:50.373354 DramcWriteLeveling(PI) end<-----
5285 13:14:50.373423
5286 13:14:50.373482 ==
5287 13:14:50.376826 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 13:14:50.379952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 13:14:50.380015 ==
5290 13:14:50.383532 [Gating] SW mode calibration
5291 13:14:50.390094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5292 13:14:50.396897 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5293 13:14:50.400236 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 13:14:50.403621 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 13:14:50.410337 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 13:14:50.413696 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 13:14:50.416679 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 13:14:50.420059 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 13:14:50.426803 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5300 13:14:50.430035 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5301 13:14:50.433275 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 13:14:50.439909 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 13:14:50.443555 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 13:14:50.446606 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 13:14:50.453284 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 13:14:50.456981 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 13:14:50.460587 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 13:14:50.466618 0 15 28 | B1->B0 | 3636 3f3f | 0 0 | (1 1) (0 0)
5309 13:14:50.469929 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 13:14:50.473387 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 13:14:50.479946 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 13:14:50.483927 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 13:14:50.486887 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 13:14:50.493399 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 13:14:50.496591 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5316 13:14:50.499947 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5317 13:14:50.506875 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5318 13:14:50.510403 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 13:14:50.513484 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 13:14:50.520388 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 13:14:50.523212 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 13:14:50.526467 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 13:14:50.533068 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 13:14:50.536830 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 13:14:50.539646 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 13:14:50.546081 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 13:14:50.549731 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 13:14:50.553236 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 13:14:50.559964 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 13:14:50.563007 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 13:14:50.566626 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 13:14:50.572954 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5333 13:14:50.576241 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 13:14:50.579597 Total UI for P1: 0, mck2ui 16
5335 13:14:50.582624 best dqsien dly found for B0: ( 1, 2, 28)
5336 13:14:50.586116 Total UI for P1: 0, mck2ui 16
5337 13:14:50.589580 best dqsien dly found for B1: ( 1, 2, 28)
5338 13:14:50.592648 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5339 13:14:50.596300 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5340 13:14:50.596368
5341 13:14:50.599500 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5342 13:14:50.602729 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5343 13:14:50.606007 [Gating] SW calibration Done
5344 13:14:50.606098 ==
5345 13:14:50.609107 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 13:14:50.612999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 13:14:50.613070 ==
5348 13:14:50.616086 RX Vref Scan: 0
5349 13:14:50.616163
5350 13:14:50.619474 RX Vref 0 -> 0, step: 1
5351 13:14:50.619539
5352 13:14:50.619598 RX Delay -80 -> 252, step: 8
5353 13:14:50.625991 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5354 13:14:50.629086 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5355 13:14:50.632662 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5356 13:14:50.635947 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5357 13:14:50.639397 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5358 13:14:50.642322 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5359 13:14:50.649072 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5360 13:14:50.652640 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5361 13:14:50.655782 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5362 13:14:50.659142 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5363 13:14:50.662379 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5364 13:14:50.665623 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5365 13:14:50.672308 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5366 13:14:50.675576 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5367 13:14:50.678849 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5368 13:14:50.682009 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5369 13:14:50.682074 ==
5370 13:14:50.685515 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 13:14:50.692343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 13:14:50.692412 ==
5373 13:14:50.692469 DQS Delay:
5374 13:14:50.692522 DQS0 = 0, DQS1 = 0
5375 13:14:50.695587 DQM Delay:
5376 13:14:50.695654 DQM0 = 104, DQM1 = 90
5377 13:14:50.698946 DQ Delay:
5378 13:14:50.702458 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5379 13:14:50.705628 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5380 13:14:50.709013 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5381 13:14:50.712088 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5382 13:14:50.712176
5383 13:14:50.712256
5384 13:14:50.712338 ==
5385 13:14:50.715647 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 13:14:50.718729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 13:14:50.718797 ==
5388 13:14:50.718852
5389 13:14:50.718904
5390 13:14:50.722242 TX Vref Scan disable
5391 13:14:50.722308 == TX Byte 0 ==
5392 13:14:50.728910 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5393 13:14:50.731867 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5394 13:14:50.731958 == TX Byte 1 ==
5395 13:14:50.738630 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5396 13:14:50.741756 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5397 13:14:50.741823 ==
5398 13:14:50.745468 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 13:14:50.748412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 13:14:50.748501 ==
5401 13:14:50.748582
5402 13:14:50.751949
5403 13:14:50.752034 TX Vref Scan disable
5404 13:14:50.755136 == TX Byte 0 ==
5405 13:14:50.758546 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5406 13:14:50.762107 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5407 13:14:50.765329 == TX Byte 1 ==
5408 13:14:50.768675 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5409 13:14:50.771801 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5410 13:14:50.775149
5411 13:14:50.775236 [DATLAT]
5412 13:14:50.775317 Freq=933, CH0 RK1
5413 13:14:50.775400
5414 13:14:50.778535 DATLAT Default: 0xb
5415 13:14:50.778596 0, 0xFFFF, sum = 0
5416 13:14:50.782182 1, 0xFFFF, sum = 0
5417 13:14:50.782244 2, 0xFFFF, sum = 0
5418 13:14:50.784941 3, 0xFFFF, sum = 0
5419 13:14:50.785003 4, 0xFFFF, sum = 0
5420 13:14:50.788837 5, 0xFFFF, sum = 0
5421 13:14:50.791720 6, 0xFFFF, sum = 0
5422 13:14:50.791793 7, 0xFFFF, sum = 0
5423 13:14:50.795212 8, 0xFFFF, sum = 0
5424 13:14:50.795275 9, 0xFFFF, sum = 0
5425 13:14:50.798224 10, 0x0, sum = 1
5426 13:14:50.798311 11, 0x0, sum = 2
5427 13:14:50.801573 12, 0x0, sum = 3
5428 13:14:50.801637 13, 0x0, sum = 4
5429 13:14:50.801692 best_step = 11
5430 13:14:50.801743
5431 13:14:50.805214 ==
5432 13:14:50.805298 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 13:14:50.811846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 13:14:50.811938 ==
5435 13:14:50.812021 RX Vref Scan: 0
5436 13:14:50.812106
5437 13:14:50.815364 RX Vref 0 -> 0, step: 1
5438 13:14:50.815426
5439 13:14:50.818209 RX Delay -53 -> 252, step: 4
5440 13:14:50.821772 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5441 13:14:50.828440 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5442 13:14:50.831651 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5443 13:14:50.834958 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5444 13:14:50.838189 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5445 13:14:50.841415 iDelay=199, Bit 5, Center 100 (15 ~ 186) 172
5446 13:14:50.848191 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5447 13:14:50.851912 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5448 13:14:50.855162 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5449 13:14:50.858261 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5450 13:14:50.861802 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5451 13:14:50.865054 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5452 13:14:50.871660 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5453 13:14:50.875000 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5454 13:14:50.878386 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5455 13:14:50.881701 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5456 13:14:50.881767 ==
5457 13:14:50.885170 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 13:14:50.891611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 13:14:50.891704 ==
5460 13:14:50.891787 DQS Delay:
5461 13:14:50.891871 DQS0 = 0, DQS1 = 0
5462 13:14:50.894990 DQM Delay:
5463 13:14:50.895057 DQM0 = 104, DQM1 = 92
5464 13:14:50.898054 DQ Delay:
5465 13:14:50.901386 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5466 13:14:50.905006 DQ4 =104, DQ5 =100, DQ6 =112, DQ7 =112
5467 13:14:50.908413 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5468 13:14:50.911302 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5469 13:14:50.911394
5470 13:14:50.911477
5471 13:14:50.918114 [DQSOSCAuto] RK1, (LSB)MR18= 0x300f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
5472 13:14:50.921613 CH0 RK1: MR19=505, MR18=300F
5473 13:14:50.927916 CH0_RK1: MR19=0x505, MR18=0x300F, DQSOSC=406, MR23=63, INC=65, DEC=43
5474 13:14:50.931461 [RxdqsGatingPostProcess] freq 933
5475 13:14:50.934895 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5476 13:14:50.937877 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 13:14:50.941589 best DQS1 dly(2T, 0.5T) = (0, 11)
5478 13:14:50.944856 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 13:14:50.947917 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5480 13:14:50.951578 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 13:14:50.955032 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 13:14:50.958383 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 13:14:50.961239 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 13:14:50.964728 Pre-setting of DQS Precalculation
5485 13:14:50.967941 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5486 13:14:50.971543 ==
5487 13:14:50.974601 Dram Type= 6, Freq= 0, CH_1, rank 0
5488 13:14:50.978374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 13:14:50.978443 ==
5490 13:14:50.981274 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5491 13:14:50.988244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5492 13:14:50.991686 [CA 0] Center 36 (6~67) winsize 62
5493 13:14:50.995071 [CA 1] Center 37 (7~68) winsize 62
5494 13:14:50.998208 [CA 2] Center 35 (5~66) winsize 62
5495 13:14:51.001306 [CA 3] Center 34 (4~65) winsize 62
5496 13:14:51.004834 [CA 4] Center 34 (4~65) winsize 62
5497 13:14:51.007813 [CA 5] Center 34 (4~65) winsize 62
5498 13:14:51.007884
5499 13:14:51.011466 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5500 13:14:51.011531
5501 13:14:51.014872 [CATrainingPosCal] consider 1 rank data
5502 13:14:51.018086 u2DelayCellTimex100 = 270/100 ps
5503 13:14:51.021484 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5504 13:14:51.024608 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5505 13:14:51.031361 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5506 13:14:51.034753 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5507 13:14:51.037874 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5508 13:14:51.041425 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5509 13:14:51.041523
5510 13:14:51.045065 CA PerBit enable=1, Macro0, CA PI delay=34
5511 13:14:51.045159
5512 13:14:51.048087 [CBTSetCACLKResult] CA Dly = 34
5513 13:14:51.048167 CS Dly: 5 (0~36)
5514 13:14:51.048223 ==
5515 13:14:51.051723 Dram Type= 6, Freq= 0, CH_1, rank 1
5516 13:14:51.057890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 13:14:51.057960 ==
5518 13:14:51.061339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 13:14:51.067930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5520 13:14:51.071285 [CA 0] Center 37 (7~68) winsize 62
5521 13:14:51.074615 [CA 1] Center 37 (7~68) winsize 62
5522 13:14:51.077887 [CA 2] Center 36 (6~66) winsize 61
5523 13:14:51.081599 [CA 3] Center 35 (5~65) winsize 61
5524 13:14:51.084557 [CA 4] Center 35 (5~65) winsize 61
5525 13:14:51.088125 [CA 5] Center 34 (5~64) winsize 60
5526 13:14:51.088191
5527 13:14:51.091665 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5528 13:14:51.091730
5529 13:14:51.094918 [CATrainingPosCal] consider 2 rank data
5530 13:14:51.098504 u2DelayCellTimex100 = 270/100 ps
5531 13:14:51.101617 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5532 13:14:51.105264 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5533 13:14:51.111603 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5534 13:14:51.114872 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5535 13:14:51.118020 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5536 13:14:51.121156 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5537 13:14:51.121217
5538 13:14:51.124922 CA PerBit enable=1, Macro0, CA PI delay=34
5539 13:14:51.125011
5540 13:14:51.128164 [CBTSetCACLKResult] CA Dly = 34
5541 13:14:51.128228 CS Dly: 6 (0~39)
5542 13:14:51.128281
5543 13:14:51.134980 ----->DramcWriteLeveling(PI) begin...
5544 13:14:51.135048 ==
5545 13:14:51.138021 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 13:14:51.141086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 13:14:51.141215 ==
5548 13:14:51.144568 Write leveling (Byte 0): 26 => 26
5549 13:14:51.148032 Write leveling (Byte 1): 27 => 27
5550 13:14:51.151150 DramcWriteLeveling(PI) end<-----
5551 13:14:51.151216
5552 13:14:51.151270 ==
5553 13:14:51.154446 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 13:14:51.158102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 13:14:51.158168 ==
5556 13:14:51.161348 [Gating] SW mode calibration
5557 13:14:51.167551 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5558 13:14:51.174656 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5559 13:14:51.177746 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 13:14:51.181149 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 13:14:51.187955 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 13:14:51.191124 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 13:14:51.194496 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 13:14:51.197617 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5565 13:14:51.204431 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5566 13:14:51.207830 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5567 13:14:51.210695 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 13:14:51.217843 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 13:14:51.220663 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 13:14:51.223993 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 13:14:51.230777 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 13:14:51.234229 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 13:14:51.237208 0 15 24 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
5574 13:14:51.243875 0 15 28 | B1->B0 | 3c3c 3939 | 1 0 | (0 0) (0 0)
5575 13:14:51.247265 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 13:14:51.250783 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 13:14:51.257275 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 13:14:51.260586 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 13:14:51.263787 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 13:14:51.270450 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5581 13:14:51.273749 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5582 13:14:51.277207 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 13:14:51.283726 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 13:14:51.286976 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 13:14:51.290398 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 13:14:51.297344 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 13:14:51.300222 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 13:14:51.304056 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 13:14:51.310432 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 13:14:51.314070 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 13:14:51.316996 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 13:14:51.323973 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 13:14:51.327614 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 13:14:51.330548 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 13:14:51.337292 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 13:14:51.340273 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5597 13:14:51.343780 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5598 13:14:51.350359 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5599 13:14:51.350518 Total UI for P1: 0, mck2ui 16
5600 13:14:51.353526 best dqsien dly found for B0: ( 1, 2, 22)
5601 13:14:51.360261 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 13:14:51.363703 Total UI for P1: 0, mck2ui 16
5603 13:14:51.366966 best dqsien dly found for B1: ( 1, 2, 26)
5604 13:14:51.370597 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5605 13:14:51.373764 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5606 13:14:51.373858
5607 13:14:51.376961 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5608 13:14:51.380509 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5609 13:14:51.383669 [Gating] SW calibration Done
5610 13:14:51.383776 ==
5611 13:14:51.387071 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 13:14:51.390659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 13:14:51.390759 ==
5614 13:14:51.393703 RX Vref Scan: 0
5615 13:14:51.393770
5616 13:14:51.393825 RX Vref 0 -> 0, step: 1
5617 13:14:51.397042
5618 13:14:51.397152 RX Delay -80 -> 252, step: 8
5619 13:14:51.403991 iDelay=208, Bit 0, Center 111 (32 ~ 191) 160
5620 13:14:51.407132 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5621 13:14:51.410280 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5622 13:14:51.413698 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5623 13:14:51.417448 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5624 13:14:51.420200 iDelay=208, Bit 5, Center 115 (32 ~ 199) 168
5625 13:14:51.427136 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5626 13:14:51.430128 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5627 13:14:51.433534 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5628 13:14:51.436868 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5629 13:14:51.440117 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5630 13:14:51.443624 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5631 13:14:51.450263 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5632 13:14:51.453384 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5633 13:14:51.456638 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5634 13:14:51.460323 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5635 13:14:51.460386 ==
5636 13:14:51.463272 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 13:14:51.469930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 13:14:51.470009 ==
5639 13:14:51.470069 DQS Delay:
5640 13:14:51.473171 DQS0 = 0, DQS1 = 0
5641 13:14:51.473273 DQM Delay:
5642 13:14:51.473335 DQM0 = 106, DQM1 = 97
5643 13:14:51.476628 DQ Delay:
5644 13:14:51.479813 DQ0 =111, DQ1 =99, DQ2 =95, DQ3 =103
5645 13:14:51.483177 DQ4 =103, DQ5 =115, DQ6 =119, DQ7 =103
5646 13:14:51.486568 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5647 13:14:51.489929 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =99
5648 13:14:51.490016
5649 13:14:51.490088
5650 13:14:51.490155 ==
5651 13:14:51.493307 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 13:14:51.496554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 13:14:51.496621 ==
5654 13:14:51.496676
5655 13:14:51.496729
5656 13:14:51.499856 TX Vref Scan disable
5657 13:14:51.503290 == TX Byte 0 ==
5658 13:14:51.506781 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5659 13:14:51.509947 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5660 13:14:51.513243 == TX Byte 1 ==
5661 13:14:51.516599 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5662 13:14:51.520078 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5663 13:14:51.520154 ==
5664 13:14:51.523178 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 13:14:51.526628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 13:14:51.529783 ==
5667 13:14:51.529858
5668 13:14:51.529917
5669 13:14:51.529971 TX Vref Scan disable
5670 13:14:51.534016 == TX Byte 0 ==
5671 13:14:51.537184 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5672 13:14:51.543643 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5673 13:14:51.543719 == TX Byte 1 ==
5674 13:14:51.546835 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5675 13:14:51.553501 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5676 13:14:51.553576
5677 13:14:51.553635 [DATLAT]
5678 13:14:51.553690 Freq=933, CH1 RK0
5679 13:14:51.553743
5680 13:14:51.556791 DATLAT Default: 0xd
5681 13:14:51.556872 0, 0xFFFF, sum = 0
5682 13:14:51.560874 1, 0xFFFF, sum = 0
5683 13:14:51.561025 2, 0xFFFF, sum = 0
5684 13:14:51.564257 3, 0xFFFF, sum = 0
5685 13:14:51.566918 4, 0xFFFF, sum = 0
5686 13:14:51.567076 5, 0xFFFF, sum = 0
5687 13:14:51.570296 6, 0xFFFF, sum = 0
5688 13:14:51.570456 7, 0xFFFF, sum = 0
5689 13:14:51.573343 8, 0xFFFF, sum = 0
5690 13:14:51.573510 9, 0xFFFF, sum = 0
5691 13:14:51.576969 10, 0x0, sum = 1
5692 13:14:51.577167 11, 0x0, sum = 2
5693 13:14:51.580734 12, 0x0, sum = 3
5694 13:14:51.580926 13, 0x0, sum = 4
5695 13:14:51.581035 best_step = 11
5696 13:14:51.581149
5697 13:14:51.583463 ==
5698 13:14:51.586853 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 13:14:51.590330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 13:14:51.590541 ==
5701 13:14:51.590679 RX Vref Scan: 1
5702 13:14:51.590801
5703 13:14:51.594043 RX Vref 0 -> 0, step: 1
5704 13:14:51.594268
5705 13:14:51.596812 RX Delay -45 -> 252, step: 4
5706 13:14:51.597029
5707 13:14:51.600608 Set Vref, RX VrefLevel [Byte0]: 52
5708 13:14:51.603650 [Byte1]: 50
5709 13:14:51.603913
5710 13:14:51.607082 Final RX Vref Byte 0 = 52 to rank0
5711 13:14:51.610299 Final RX Vref Byte 1 = 50 to rank0
5712 13:14:51.613981 Final RX Vref Byte 0 = 52 to rank1
5713 13:14:51.617311 Final RX Vref Byte 1 = 50 to rank1==
5714 13:14:51.620764 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 13:14:51.623705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 13:14:51.624143 ==
5717 13:14:51.627245 DQS Delay:
5718 13:14:51.627707 DQS0 = 0, DQS1 = 0
5719 13:14:51.630285 DQM Delay:
5720 13:14:51.630709 DQM0 = 107, DQM1 = 100
5721 13:14:51.631047 DQ Delay:
5722 13:14:51.637384 DQ0 =110, DQ1 =102, DQ2 =100, DQ3 =106
5723 13:14:51.640342 DQ4 =108, DQ5 =116, DQ6 =116, DQ7 =104
5724 13:14:51.643950 DQ8 =90, DQ9 =90, DQ10 =104, DQ11 =96
5725 13:14:51.647408 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =104
5726 13:14:51.647855
5727 13:14:51.648194
5728 13:14:51.654006 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5729 13:14:51.657297 CH1 RK0: MR19=505, MR18=1A32
5730 13:14:51.664309 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5731 13:14:51.664815
5732 13:14:51.667343 ----->DramcWriteLeveling(PI) begin...
5733 13:14:51.667858 ==
5734 13:14:51.670917 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 13:14:51.673524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 13:14:51.673959 ==
5737 13:14:51.676908 Write leveling (Byte 0): 29 => 29
5738 13:14:51.680557 Write leveling (Byte 1): 29 => 29
5739 13:14:51.684286 DramcWriteLeveling(PI) end<-----
5740 13:14:51.684794
5741 13:14:51.685165 ==
5742 13:14:51.687008 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 13:14:51.690631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 13:14:51.691149 ==
5745 13:14:51.694195 [Gating] SW mode calibration
5746 13:14:51.700684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5747 13:14:51.707458 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5748 13:14:51.710251 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5749 13:14:51.717288 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 13:14:51.720851 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 13:14:51.723890 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 13:14:51.730571 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 13:14:51.733856 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 13:14:51.736687 0 14 24 | B1->B0 | 2f2f 3333 | 1 1 | (1 1) (1 0)
5755 13:14:51.743698 0 14 28 | B1->B0 | 2626 2e2e | 1 0 | (1 0) (1 1)
5756 13:14:51.746450 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5757 13:14:51.750676 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 13:14:51.757097 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 13:14:51.760187 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 13:14:51.763486 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 13:14:51.770191 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 13:14:51.773817 0 15 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5763 13:14:51.776728 0 15 28 | B1->B0 | 3f3f 3535 | 0 0 | (0 0) (0 0)
5764 13:14:51.783340 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 13:14:51.786259 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 13:14:51.789645 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 13:14:51.796269 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 13:14:51.799879 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 13:14:51.803178 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 13:14:51.806216 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 13:14:51.813282 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5772 13:14:51.816424 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 13:14:51.820109 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 13:14:51.826107 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 13:14:51.829766 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 13:14:51.832892 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 13:14:51.839741 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 13:14:51.843168 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 13:14:51.846099 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 13:14:51.853080 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 13:14:51.855877 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 13:14:51.859686 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 13:14:51.866102 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 13:14:51.869564 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 13:14:51.872840 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 13:14:51.880071 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5787 13:14:51.882880 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 13:14:51.886312 Total UI for P1: 0, mck2ui 16
5789 13:14:51.889562 best dqsien dly found for B0: ( 1, 2, 24)
5790 13:14:51.892765 Total UI for P1: 0, mck2ui 16
5791 13:14:51.896110 best dqsien dly found for B1: ( 1, 2, 24)
5792 13:14:51.899121 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5793 13:14:51.902599 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5794 13:14:51.903100
5795 13:14:51.906086 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5796 13:14:51.909522 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5797 13:14:51.912889 [Gating] SW calibration Done
5798 13:14:51.913436 ==
5799 13:14:51.916342 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 13:14:51.919572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 13:14:51.922833 ==
5802 13:14:51.923331 RX Vref Scan: 0
5803 13:14:51.923664
5804 13:14:51.926104 RX Vref 0 -> 0, step: 1
5805 13:14:51.926530
5806 13:14:51.926862 RX Delay -80 -> 252, step: 8
5807 13:14:51.932868 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5808 13:14:51.936413 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5809 13:14:51.939522 iDelay=200, Bit 2, Center 95 (16 ~ 175) 160
5810 13:14:51.943213 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5811 13:14:51.946059 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5812 13:14:51.953044 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5813 13:14:51.955961 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5814 13:14:51.959503 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5815 13:14:51.962858 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5816 13:14:51.965997 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5817 13:14:51.969744 iDelay=200, Bit 10, Center 99 (16 ~ 183) 168
5818 13:14:51.976353 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5819 13:14:51.979512 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5820 13:14:51.982847 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5821 13:14:51.986129 iDelay=200, Bit 14, Center 103 (16 ~ 191) 176
5822 13:14:51.993015 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5823 13:14:51.993568 ==
5824 13:14:51.996429 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 13:14:51.999433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 13:14:51.999858 ==
5827 13:14:52.000187 DQS Delay:
5828 13:14:52.002905 DQS0 = 0, DQS1 = 0
5829 13:14:52.003328 DQM Delay:
5830 13:14:52.005853 DQM0 = 105, DQM1 = 97
5831 13:14:52.006275 DQ Delay:
5832 13:14:52.009631 DQ0 =111, DQ1 =99, DQ2 =95, DQ3 =103
5833 13:14:52.013333 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =103
5834 13:14:52.016158 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5835 13:14:52.019572 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5836 13:14:52.020072
5837 13:14:52.020402
5838 13:14:52.020707 ==
5839 13:14:52.022926 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 13:14:52.025866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 13:14:52.029427 ==
5842 13:14:52.029929
5843 13:14:52.030261
5844 13:14:52.030611 TX Vref Scan disable
5845 13:14:52.032611 == TX Byte 0 ==
5846 13:14:52.036172 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5847 13:14:52.039259 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5848 13:14:52.042593 == TX Byte 1 ==
5849 13:14:52.045767 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5850 13:14:52.049246 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5851 13:14:52.052595 ==
5852 13:14:52.055926 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 13:14:52.059169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 13:14:52.059594 ==
5855 13:14:52.060053
5856 13:14:52.060584
5857 13:14:52.062370 TX Vref Scan disable
5858 13:14:52.062789 == TX Byte 0 ==
5859 13:14:52.069174 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 13:14:52.072167 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 13:14:52.072594 == TX Byte 1 ==
5862 13:14:52.078974 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5863 13:14:52.082213 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5864 13:14:52.082690
5865 13:14:52.083025 [DATLAT]
5866 13:14:52.085715 Freq=933, CH1 RK1
5867 13:14:52.086295
5868 13:14:52.086792 DATLAT Default: 0xb
5869 13:14:52.088973 0, 0xFFFF, sum = 0
5870 13:14:52.089648 1, 0xFFFF, sum = 0
5871 13:14:52.092418 2, 0xFFFF, sum = 0
5872 13:14:52.092857 3, 0xFFFF, sum = 0
5873 13:14:52.095658 4, 0xFFFF, sum = 0
5874 13:14:52.096083 5, 0xFFFF, sum = 0
5875 13:14:52.099321 6, 0xFFFF, sum = 0
5876 13:14:52.099832 7, 0xFFFF, sum = 0
5877 13:14:52.102514 8, 0xFFFF, sum = 0
5878 13:14:52.103021 9, 0xFFFF, sum = 0
5879 13:14:52.105668 10, 0x0, sum = 1
5880 13:14:52.106095 11, 0x0, sum = 2
5881 13:14:52.109198 12, 0x0, sum = 3
5882 13:14:52.109713 13, 0x0, sum = 4
5883 13:14:52.112274 best_step = 11
5884 13:14:52.112693
5885 13:14:52.113020 ==
5886 13:14:52.116034 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 13:14:52.119193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 13:14:52.119620 ==
5889 13:14:52.122976 RX Vref Scan: 0
5890 13:14:52.123472
5891 13:14:52.123803 RX Vref 0 -> 0, step: 1
5892 13:14:52.124108
5893 13:14:52.125675 RX Delay -53 -> 252, step: 4
5894 13:14:52.133318 iDelay=199, Bit 0, Center 112 (39 ~ 186) 148
5895 13:14:52.136371 iDelay=199, Bit 1, Center 102 (27 ~ 178) 152
5896 13:14:52.139282 iDelay=199, Bit 2, Center 96 (19 ~ 174) 156
5897 13:14:52.143074 iDelay=199, Bit 3, Center 106 (27 ~ 186) 160
5898 13:14:52.146111 iDelay=199, Bit 4, Center 108 (31 ~ 186) 156
5899 13:14:52.153314 iDelay=199, Bit 5, Center 118 (39 ~ 198) 160
5900 13:14:52.156338 iDelay=199, Bit 6, Center 116 (39 ~ 194) 156
5901 13:14:52.159484 iDelay=199, Bit 7, Center 106 (31 ~ 182) 152
5902 13:14:52.162979 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5903 13:14:52.166645 iDelay=199, Bit 9, Center 90 (11 ~ 170) 160
5904 13:14:52.169871 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5905 13:14:52.176281 iDelay=199, Bit 11, Center 96 (15 ~ 178) 164
5906 13:14:52.179632 iDelay=199, Bit 12, Center 108 (27 ~ 190) 164
5907 13:14:52.182713 iDelay=199, Bit 13, Center 104 (23 ~ 186) 164
5908 13:14:52.186481 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5909 13:14:52.192994 iDelay=199, Bit 15, Center 108 (27 ~ 190) 164
5910 13:14:52.193566 ==
5911 13:14:52.196315 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 13:14:52.199582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 13:14:52.200086 ==
5914 13:14:52.200420 DQS Delay:
5915 13:14:52.203295 DQS0 = 0, DQS1 = 0
5916 13:14:52.203794 DQM Delay:
5917 13:14:52.206321 DQM0 = 108, DQM1 = 99
5918 13:14:52.206745 DQ Delay:
5919 13:14:52.209485 DQ0 =112, DQ1 =102, DQ2 =96, DQ3 =106
5920 13:14:52.212590 DQ4 =108, DQ5 =118, DQ6 =116, DQ7 =106
5921 13:14:52.216551 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =96
5922 13:14:52.219468 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =108
5923 13:14:52.219966
5924 13:14:52.220300
5925 13:14:52.229396 [DQSOSCAuto] RK1, (LSB)MR18= 0x2705, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5926 13:14:52.232745 CH1 RK1: MR19=505, MR18=2705
5927 13:14:52.235851 CH1_RK1: MR19=0x505, MR18=0x2705, DQSOSC=409, MR23=63, INC=64, DEC=43
5928 13:14:52.239560 [RxdqsGatingPostProcess] freq 933
5929 13:14:52.246267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5930 13:14:52.249422 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 13:14:52.252595 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 13:14:52.255456 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 13:14:52.259168 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 13:14:52.262472 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 13:14:52.265689 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 13:14:52.269183 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 13:14:52.272684 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 13:14:52.273112 Pre-setting of DQS Precalculation
5939 13:14:52.278904 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5940 13:14:52.285800 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5941 13:14:52.292453 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5942 13:14:52.292965
5943 13:14:52.293424
5944 13:14:52.295942 [Calibration Summary] 1866 Mbps
5945 13:14:52.298871 CH 0, Rank 0
5946 13:14:52.299293 SW Impedance : PASS
5947 13:14:52.302446 DUTY Scan : NO K
5948 13:14:52.306107 ZQ Calibration : PASS
5949 13:14:52.306605 Jitter Meter : NO K
5950 13:14:52.309408 CBT Training : PASS
5951 13:14:52.309908 Write leveling : PASS
5952 13:14:52.312243 RX DQS gating : PASS
5953 13:14:52.315827 RX DQ/DQS(RDDQC) : PASS
5954 13:14:52.316326 TX DQ/DQS : PASS
5955 13:14:52.319345 RX DATLAT : PASS
5956 13:14:52.322426 RX DQ/DQS(Engine): PASS
5957 13:14:52.322926 TX OE : NO K
5958 13:14:52.325994 All Pass.
5959 13:14:52.326491
5960 13:14:52.326827 CH 0, Rank 1
5961 13:14:52.328886 SW Impedance : PASS
5962 13:14:52.329347 DUTY Scan : NO K
5963 13:14:52.332468 ZQ Calibration : PASS
5964 13:14:52.335637 Jitter Meter : NO K
5965 13:14:52.336160 CBT Training : PASS
5966 13:14:52.338760 Write leveling : PASS
5967 13:14:52.342596 RX DQS gating : PASS
5968 13:14:52.343102 RX DQ/DQS(RDDQC) : PASS
5969 13:14:52.345843 TX DQ/DQS : PASS
5970 13:14:52.349684 RX DATLAT : PASS
5971 13:14:52.350185 RX DQ/DQS(Engine): PASS
5972 13:14:52.352512 TX OE : NO K
5973 13:14:52.353014 All Pass.
5974 13:14:52.353412
5975 13:14:52.355734 CH 1, Rank 0
5976 13:14:52.356157 SW Impedance : PASS
5977 13:14:52.359478 DUTY Scan : NO K
5978 13:14:52.359983 ZQ Calibration : PASS
5979 13:14:52.362527 Jitter Meter : NO K
5980 13:14:52.365882 CBT Training : PASS
5981 13:14:52.366385 Write leveling : PASS
5982 13:14:52.369022 RX DQS gating : PASS
5983 13:14:52.372585 RX DQ/DQS(RDDQC) : PASS
5984 13:14:52.373014 TX DQ/DQS : PASS
5985 13:14:52.375688 RX DATLAT : PASS
5986 13:14:52.378922 RX DQ/DQS(Engine): PASS
5987 13:14:52.379479 TX OE : NO K
5988 13:14:52.382078 All Pass.
5989 13:14:52.382502
5990 13:14:52.382835 CH 1, Rank 1
5991 13:14:52.385465 SW Impedance : PASS
5992 13:14:52.385891 DUTY Scan : NO K
5993 13:14:52.388887 ZQ Calibration : PASS
5994 13:14:52.392203 Jitter Meter : NO K
5995 13:14:52.392787 CBT Training : PASS
5996 13:14:52.395342 Write leveling : PASS
5997 13:14:52.398691 RX DQS gating : PASS
5998 13:14:52.399184 RX DQ/DQS(RDDQC) : PASS
5999 13:14:52.402139 TX DQ/DQS : PASS
6000 13:14:52.402840 RX DATLAT : PASS
6001 13:14:52.405243 RX DQ/DQS(Engine): PASS
6002 13:14:52.408794 TX OE : NO K
6003 13:14:52.409509 All Pass.
6004 13:14:52.410117
6005 13:14:52.412070 DramC Write-DBI off
6006 13:14:52.412561 PER_BANK_REFRESH: Hybrid Mode
6007 13:14:52.415339 TX_TRACKING: ON
6008 13:14:52.422648 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6009 13:14:52.429101 [FAST_K] Save calibration result to emmc
6010 13:14:52.432165 dramc_set_vcore_voltage set vcore to 650000
6011 13:14:52.432591 Read voltage for 400, 6
6012 13:14:52.435480 Vio18 = 0
6013 13:14:52.435904 Vcore = 650000
6014 13:14:52.436234 Vdram = 0
6015 13:14:52.439134 Vddq = 0
6016 13:14:52.439558 Vmddr = 0
6017 13:14:52.442108 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6018 13:14:52.448983 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6019 13:14:52.452399 MEM_TYPE=3, freq_sel=20
6020 13:14:52.455789 sv_algorithm_assistance_LP4_800
6021 13:14:52.458912 ============ PULL DRAM RESETB DOWN ============
6022 13:14:52.462067 ========== PULL DRAM RESETB DOWN end =========
6023 13:14:52.465812 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6024 13:14:52.468927 ===================================
6025 13:14:52.472384 LPDDR4 DRAM CONFIGURATION
6026 13:14:52.475612 ===================================
6027 13:14:52.479145 EX_ROW_EN[0] = 0x0
6028 13:14:52.479785 EX_ROW_EN[1] = 0x0
6029 13:14:52.482239 LP4Y_EN = 0x0
6030 13:14:52.482663 WORK_FSP = 0x0
6031 13:14:52.485650 WL = 0x2
6032 13:14:52.486143 RL = 0x2
6033 13:14:52.488535 BL = 0x2
6034 13:14:52.488969 RPST = 0x0
6035 13:14:52.492522 RD_PRE = 0x0
6036 13:14:52.495734 WR_PRE = 0x1
6037 13:14:52.496236 WR_PST = 0x0
6038 13:14:52.498870 DBI_WR = 0x0
6039 13:14:52.499372 DBI_RD = 0x0
6040 13:14:52.502226 OTF = 0x1
6041 13:14:52.505535 ===================================
6042 13:14:52.508932 ===================================
6043 13:14:52.509412 ANA top config
6044 13:14:52.511904 ===================================
6045 13:14:52.515425 DLL_ASYNC_EN = 0
6046 13:14:52.515924 ALL_SLAVE_EN = 1
6047 13:14:52.519019 NEW_RANK_MODE = 1
6048 13:14:52.522261 DLL_IDLE_MODE = 1
6049 13:14:52.525596 LP45_APHY_COMB_EN = 1
6050 13:14:52.528737 TX_ODT_DIS = 1
6051 13:14:52.529191 NEW_8X_MODE = 1
6052 13:14:52.532300 ===================================
6053 13:14:52.535194 ===================================
6054 13:14:52.538650 data_rate = 800
6055 13:14:52.542020 CKR = 1
6056 13:14:52.545331 DQ_P2S_RATIO = 4
6057 13:14:52.548653 ===================================
6058 13:14:52.552200 CA_P2S_RATIO = 4
6059 13:14:52.555344 DQ_CA_OPEN = 0
6060 13:14:52.555773 DQ_SEMI_OPEN = 1
6061 13:14:52.558761 CA_SEMI_OPEN = 1
6062 13:14:52.561820 CA_FULL_RATE = 0
6063 13:14:52.565509 DQ_CKDIV4_EN = 0
6064 13:14:52.568525 CA_CKDIV4_EN = 1
6065 13:14:52.571803 CA_PREDIV_EN = 0
6066 13:14:52.572307 PH8_DLY = 0
6067 13:14:52.575200 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6068 13:14:52.578639 DQ_AAMCK_DIV = 0
6069 13:14:52.581902 CA_AAMCK_DIV = 0
6070 13:14:52.584814 CA_ADMCK_DIV = 4
6071 13:14:52.588552 DQ_TRACK_CA_EN = 0
6072 13:14:52.589057 CA_PICK = 800
6073 13:14:52.591975 CA_MCKIO = 400
6074 13:14:52.595392 MCKIO_SEMI = 400
6075 13:14:52.598195 PLL_FREQ = 3016
6076 13:14:52.601576 DQ_UI_PI_RATIO = 32
6077 13:14:52.604781 CA_UI_PI_RATIO = 32
6078 13:14:52.608259 ===================================
6079 13:14:52.611761 ===================================
6080 13:14:52.615316 memory_type:LPDDR4
6081 13:14:52.615817 GP_NUM : 10
6082 13:14:52.618192 SRAM_EN : 1
6083 13:14:52.618621 MD32_EN : 0
6084 13:14:52.621794 ===================================
6085 13:14:52.625099 [ANA_INIT] >>>>>>>>>>>>>>
6086 13:14:52.628568 <<<<<< [CONFIGURE PHASE]: ANA_TX
6087 13:14:52.632001 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6088 13:14:52.635350 ===================================
6089 13:14:52.638015 data_rate = 800,PCW = 0X7400
6090 13:14:52.642180 ===================================
6091 13:14:52.645000 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6092 13:14:52.648893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 13:14:52.661765 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 13:14:52.665280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6095 13:14:52.668839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6096 13:14:52.671790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6097 13:14:52.674950 [ANA_INIT] flow start
6098 13:14:52.678360 [ANA_INIT] PLL >>>>>>>>
6099 13:14:52.678797 [ANA_INIT] PLL <<<<<<<<
6100 13:14:52.681630 [ANA_INIT] MIDPI >>>>>>>>
6101 13:14:52.685059 [ANA_INIT] MIDPI <<<<<<<<
6102 13:14:52.685612 [ANA_INIT] DLL >>>>>>>>
6103 13:14:52.688754 [ANA_INIT] flow end
6104 13:14:52.691740 ============ LP4 DIFF to SE enter ============
6105 13:14:52.695179 ============ LP4 DIFF to SE exit ============
6106 13:14:52.698395 [ANA_INIT] <<<<<<<<<<<<<
6107 13:14:52.701574 [Flow] Enable top DCM control >>>>>
6108 13:14:52.705017 [Flow] Enable top DCM control <<<<<
6109 13:14:52.708204 Enable DLL master slave shuffle
6110 13:14:52.714973 ==============================================================
6111 13:14:52.715474 Gating Mode config
6112 13:14:52.722055 ==============================================================
6113 13:14:52.722569 Config description:
6114 13:14:52.731411 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6115 13:14:52.738231 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6116 13:14:52.744857 SELPH_MODE 0: By rank 1: By Phase
6117 13:14:52.748316 ==============================================================
6118 13:14:52.751386 GAT_TRACK_EN = 0
6119 13:14:52.755187 RX_GATING_MODE = 2
6120 13:14:52.757915 RX_GATING_TRACK_MODE = 2
6121 13:14:52.761500 SELPH_MODE = 1
6122 13:14:52.764988 PICG_EARLY_EN = 1
6123 13:14:52.768345 VALID_LAT_VALUE = 1
6124 13:14:52.774573 ==============================================================
6125 13:14:52.777985 Enter into Gating configuration >>>>
6126 13:14:52.781391 Exit from Gating configuration <<<<
6127 13:14:52.784218 Enter into DVFS_PRE_config >>>>>
6128 13:14:52.794660 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6129 13:14:52.798082 Exit from DVFS_PRE_config <<<<<
6130 13:14:52.801159 Enter into PICG configuration >>>>
6131 13:14:52.804523 Exit from PICG configuration <<<<
6132 13:14:52.807862 [RX_INPUT] configuration >>>>>
6133 13:14:52.808386 [RX_INPUT] configuration <<<<<
6134 13:14:52.814921 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6135 13:14:52.821291 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6136 13:14:52.824715 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 13:14:52.830823 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 13:14:52.837627 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 13:14:52.844162 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 13:14:52.847303 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6141 13:14:52.851012 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6142 13:14:52.857311 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6143 13:14:52.861087 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6144 13:14:52.864337 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6145 13:14:52.870816 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 13:14:52.874111 ===================================
6147 13:14:52.874591 LPDDR4 DRAM CONFIGURATION
6148 13:14:52.877154 ===================================
6149 13:14:52.880928 EX_ROW_EN[0] = 0x0
6150 13:14:52.881482 EX_ROW_EN[1] = 0x0
6151 13:14:52.883861 LP4Y_EN = 0x0
6152 13:14:52.884283 WORK_FSP = 0x0
6153 13:14:52.887260 WL = 0x2
6154 13:14:52.887681 RL = 0x2
6155 13:14:52.890805 BL = 0x2
6156 13:14:52.893879 RPST = 0x0
6157 13:14:52.894305 RD_PRE = 0x0
6158 13:14:52.897457 WR_PRE = 0x1
6159 13:14:52.898046 WR_PST = 0x0
6160 13:14:52.900889 DBI_WR = 0x0
6161 13:14:52.901422 DBI_RD = 0x0
6162 13:14:52.904037 OTF = 0x1
6163 13:14:52.907566 ===================================
6164 13:14:52.910512 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6165 13:14:52.913618 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6166 13:14:52.917396 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6167 13:14:52.920407 ===================================
6168 13:14:52.924056 LPDDR4 DRAM CONFIGURATION
6169 13:14:52.927015 ===================================
6170 13:14:52.930389 EX_ROW_EN[0] = 0x10
6171 13:14:52.930865 EX_ROW_EN[1] = 0x0
6172 13:14:52.933953 LP4Y_EN = 0x0
6173 13:14:52.934464 WORK_FSP = 0x0
6174 13:14:52.937515 WL = 0x2
6175 13:14:52.938028 RL = 0x2
6176 13:14:52.941058 BL = 0x2
6177 13:14:52.941733 RPST = 0x0
6178 13:14:52.943672 RD_PRE = 0x0
6179 13:14:52.944098 WR_PRE = 0x1
6180 13:14:52.947539 WR_PST = 0x0
6181 13:14:52.948058 DBI_WR = 0x0
6182 13:14:52.950713 DBI_RD = 0x0
6183 13:14:52.953932 OTF = 0x1
6184 13:14:52.954437 ===================================
6185 13:14:52.960501 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6186 13:14:52.965757 nWR fixed to 30
6187 13:14:52.969041 [ModeRegInit_LP4] CH0 RK0
6188 13:14:52.969576 [ModeRegInit_LP4] CH0 RK1
6189 13:14:52.972420 [ModeRegInit_LP4] CH1 RK0
6190 13:14:52.975641 [ModeRegInit_LP4] CH1 RK1
6191 13:14:52.976067 match AC timing 19
6192 13:14:52.982721 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6193 13:14:52.985623 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6194 13:14:52.989159 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6195 13:14:52.996089 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6196 13:14:52.999163 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6197 13:14:52.999586 ==
6198 13:14:53.002585 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 13:14:53.005808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6200 13:14:53.006315 ==
6201 13:14:53.012145 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6202 13:14:53.018708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6203 13:14:53.022239 [CA 0] Center 36 (8~64) winsize 57
6204 13:14:53.025369 [CA 1] Center 36 (8~64) winsize 57
6205 13:14:53.028606 [CA 2] Center 36 (8~64) winsize 57
6206 13:14:53.029110 [CA 3] Center 36 (8~64) winsize 57
6207 13:14:53.032075 [CA 4] Center 36 (8~64) winsize 57
6208 13:14:53.035119 [CA 5] Center 36 (8~64) winsize 57
6209 13:14:53.035545
6210 13:14:53.038604 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6211 13:14:53.042056
6212 13:14:53.045621 [CATrainingPosCal] consider 1 rank data
6213 13:14:53.048804 u2DelayCellTimex100 = 270/100 ps
6214 13:14:53.052243 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 13:14:53.055086 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 13:14:53.058341 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 13:14:53.061816 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 13:14:53.065353 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 13:14:53.068562 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 13:14:53.069301
6221 13:14:53.072285 CA PerBit enable=1, Macro0, CA PI delay=36
6222 13:14:53.072796
6223 13:14:53.075362 [CBTSetCACLKResult] CA Dly = 36
6224 13:14:53.078299 CS Dly: 1 (0~32)
6225 13:14:53.078733 ==
6226 13:14:53.081841 Dram Type= 6, Freq= 0, CH_0, rank 1
6227 13:14:53.085023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 13:14:53.085613 ==
6229 13:14:53.091779 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 13:14:53.095161 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6231 13:14:53.098589 [CA 0] Center 36 (8~64) winsize 57
6232 13:14:53.101741 [CA 1] Center 36 (8~64) winsize 57
6233 13:14:53.105307 [CA 2] Center 36 (8~64) winsize 57
6234 13:14:53.108696 [CA 3] Center 36 (8~64) winsize 57
6235 13:14:53.111314 [CA 4] Center 36 (8~64) winsize 57
6236 13:14:53.115075 [CA 5] Center 36 (8~64) winsize 57
6237 13:14:53.115584
6238 13:14:53.118259 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6239 13:14:53.118691
6240 13:14:53.121611 [CATrainingPosCal] consider 2 rank data
6241 13:14:53.124689 u2DelayCellTimex100 = 270/100 ps
6242 13:14:53.128359 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 13:14:53.131231 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 13:14:53.138277 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 13:14:53.141594 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 13:14:53.144838 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 13:14:53.147789 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 13:14:53.148216
6249 13:14:53.151235 CA PerBit enable=1, Macro0, CA PI delay=36
6250 13:14:53.151680
6251 13:14:53.154293 [CBTSetCACLKResult] CA Dly = 36
6252 13:14:53.154721 CS Dly: 1 (0~32)
6253 13:14:53.155061
6254 13:14:53.157601 ----->DramcWriteLeveling(PI) begin...
6255 13:14:53.161058 ==
6256 13:14:53.164597 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 13:14:53.168079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 13:14:53.168595 ==
6259 13:14:53.171319 Write leveling (Byte 0): 40 => 8
6260 13:14:53.174844 Write leveling (Byte 1): 32 => 0
6261 13:14:53.177605 DramcWriteLeveling(PI) end<-----
6262 13:14:53.178183
6263 13:14:53.178533 ==
6264 13:14:53.181605 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 13:14:53.184521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 13:14:53.185027 ==
6267 13:14:53.187882 [Gating] SW mode calibration
6268 13:14:53.194843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6269 13:14:53.197796 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6270 13:14:53.204770 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 13:14:53.208272 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 13:14:53.211064 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 13:14:53.217837 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 13:14:53.221042 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 13:14:53.224514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 13:14:53.230855 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 13:14:53.234441 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 13:14:53.237449 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 13:14:53.241232 Total UI for P1: 0, mck2ui 16
6280 13:14:53.244324 best dqsien dly found for B0: ( 0, 14, 24)
6281 13:14:53.247478 Total UI for P1: 0, mck2ui 16
6282 13:14:53.250844 best dqsien dly found for B1: ( 0, 14, 24)
6283 13:14:53.254114 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6284 13:14:53.258098 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6285 13:14:53.260900
6286 13:14:53.264140 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 13:14:53.267369 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 13:14:53.271089 [Gating] SW calibration Done
6289 13:14:53.271595 ==
6290 13:14:53.273991 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 13:14:53.277019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 13:14:53.277625 ==
6293 13:14:53.278003 RX Vref Scan: 0
6294 13:14:53.280784
6295 13:14:53.281346 RX Vref 0 -> 0, step: 1
6296 13:14:53.281689
6297 13:14:53.284375 RX Delay -410 -> 252, step: 16
6298 13:14:53.287346 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6299 13:14:53.294051 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6300 13:14:53.297581 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6301 13:14:53.301103 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6302 13:14:53.304097 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6303 13:14:53.310693 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6304 13:14:53.313994 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6305 13:14:53.317222 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6306 13:14:53.320838 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6307 13:14:53.326951 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6308 13:14:53.330501 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6309 13:14:53.333741 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6310 13:14:53.337284 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6311 13:14:53.343909 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6312 13:14:53.347297 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6313 13:14:53.350391 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6314 13:14:53.350863 ==
6315 13:14:53.353511 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 13:14:53.356926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 13:14:53.360516 ==
6318 13:14:53.361022 DQS Delay:
6319 13:14:53.361415 DQS0 = 27, DQS1 = 43
6320 13:14:53.363745 DQM Delay:
6321 13:14:53.364169 DQM0 = 11, DQM1 = 13
6322 13:14:53.367127 DQ Delay:
6323 13:14:53.367633 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6324 13:14:53.370885 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6325 13:14:53.373801 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6326 13:14:53.376972 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6327 13:14:53.377448
6328 13:14:53.378001
6329 13:14:53.380532 ==
6330 13:14:53.381034 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 13:14:53.387231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 13:14:53.387725 ==
6333 13:14:53.388057
6334 13:14:53.388360
6335 13:14:53.390707 TX Vref Scan disable
6336 13:14:53.391209 == TX Byte 0 ==
6337 13:14:53.393829 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 13:14:53.400120 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 13:14:53.400630 == TX Byte 1 ==
6340 13:14:53.403406 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6341 13:14:53.410064 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6342 13:14:53.410555 ==
6343 13:14:53.413547 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 13:14:53.417065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 13:14:53.417602 ==
6346 13:14:53.417940
6347 13:14:53.418266
6348 13:14:53.420233 TX Vref Scan disable
6349 13:14:53.420735 == TX Byte 0 ==
6350 13:14:53.423584 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 13:14:53.430390 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 13:14:53.430878 == TX Byte 1 ==
6353 13:14:53.433863 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6354 13:14:53.439873 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6355 13:14:53.440338
6356 13:14:53.440944 [DATLAT]
6357 13:14:53.441542 Freq=400, CH0 RK0
6358 13:14:53.441880
6359 13:14:53.443163 DATLAT Default: 0xf
6360 13:14:53.446715 0, 0xFFFF, sum = 0
6361 13:14:53.447185 1, 0xFFFF, sum = 0
6362 13:14:53.450173 2, 0xFFFF, sum = 0
6363 13:14:53.450644 3, 0xFFFF, sum = 0
6364 13:14:53.453754 4, 0xFFFF, sum = 0
6365 13:14:53.454182 5, 0xFFFF, sum = 0
6366 13:14:53.456530 6, 0xFFFF, sum = 0
6367 13:14:53.456975 7, 0xFFFF, sum = 0
6368 13:14:53.459735 8, 0xFFFF, sum = 0
6369 13:14:53.460164 9, 0xFFFF, sum = 0
6370 13:14:53.463305 10, 0xFFFF, sum = 0
6371 13:14:53.464009 11, 0xFFFF, sum = 0
6372 13:14:53.466780 12, 0xFFFF, sum = 0
6373 13:14:53.467345 13, 0x0, sum = 1
6374 13:14:53.470094 14, 0x0, sum = 2
6375 13:14:53.470785 15, 0x0, sum = 3
6376 13:14:53.473239 16, 0x0, sum = 4
6377 13:14:53.473666 best_step = 14
6378 13:14:53.473989
6379 13:14:53.474285 ==
6380 13:14:53.476713 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 13:14:53.483720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 13:14:53.484223 ==
6383 13:14:53.484555 RX Vref Scan: 1
6384 13:14:53.484859
6385 13:14:53.486637 RX Vref 0 -> 0, step: 1
6386 13:14:53.487070
6387 13:14:53.490055 RX Delay -327 -> 252, step: 8
6388 13:14:53.490479
6389 13:14:53.493371 Set Vref, RX VrefLevel [Byte0]: 60
6390 13:14:53.496544 [Byte1]: 49
6391 13:14:53.496968
6392 13:14:53.500310 Final RX Vref Byte 0 = 60 to rank0
6393 13:14:53.503528 Final RX Vref Byte 1 = 49 to rank0
6394 13:14:53.507140 Final RX Vref Byte 0 = 60 to rank1
6395 13:14:53.509757 Final RX Vref Byte 1 = 49 to rank1==
6396 13:14:53.513442 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 13:14:53.517057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 13:14:53.517598 ==
6399 13:14:53.520159 DQS Delay:
6400 13:14:53.520660 DQS0 = 28, DQS1 = 48
6401 13:14:53.523194 DQM Delay:
6402 13:14:53.523617 DQM0 = 11, DQM1 = 15
6403 13:14:53.523949 DQ Delay:
6404 13:14:53.526844 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6405 13:14:53.530331 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6406 13:14:53.533549 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6407 13:14:53.537009 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6408 13:14:53.537553
6409 13:14:53.537884
6410 13:14:53.546728 [DQSOSCAuto] RK0, (LSB)MR18= 0xbab2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 386 ps
6411 13:14:53.550667 CH0 RK0: MR19=C0C, MR18=BAB2
6412 13:14:53.553709 CH0_RK0: MR19=0xC0C, MR18=0xBAB2, DQSOSC=386, MR23=63, INC=396, DEC=264
6413 13:14:53.556580 ==
6414 13:14:53.557089 Dram Type= 6, Freq= 0, CH_0, rank 1
6415 13:14:53.563678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 13:14:53.564198 ==
6417 13:14:53.566670 [Gating] SW mode calibration
6418 13:14:53.573204 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 13:14:53.576268 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6420 13:14:53.582997 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 13:14:53.586357 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 13:14:53.589879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 13:14:53.596638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 13:14:53.600137 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 13:14:53.603637 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 13:14:53.609465 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 13:14:53.613215 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 13:14:53.616695 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 13:14:53.620037 Total UI for P1: 0, mck2ui 16
6430 13:14:53.623249 best dqsien dly found for B0: ( 0, 14, 24)
6431 13:14:53.626539 Total UI for P1: 0, mck2ui 16
6432 13:14:53.629928 best dqsien dly found for B1: ( 0, 14, 24)
6433 13:14:53.633024 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6434 13:14:53.636352 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6435 13:14:53.636851
6436 13:14:53.639495 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 13:14:53.646306 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 13:14:53.646803 [Gating] SW calibration Done
6439 13:14:53.647131 ==
6440 13:14:53.649979 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 13:14:53.656329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 13:14:53.656854 ==
6443 13:14:53.657230 RX Vref Scan: 0
6444 13:14:53.657548
6445 13:14:53.659626 RX Vref 0 -> 0, step: 1
6446 13:14:53.660209
6447 13:14:53.663165 RX Delay -410 -> 252, step: 16
6448 13:14:53.666946 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6449 13:14:53.670307 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6450 13:14:53.676546 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6451 13:14:53.679556 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6452 13:14:53.682576 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6453 13:14:53.686304 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6454 13:14:53.692616 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6455 13:14:53.695961 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6456 13:14:53.699762 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6457 13:14:53.702750 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6458 13:14:53.709486 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6459 13:14:53.712778 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6460 13:14:53.716497 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6461 13:14:53.719562 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6462 13:14:53.726105 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6463 13:14:53.729368 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6464 13:14:53.729795 ==
6465 13:14:53.732995 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 13:14:53.735881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 13:14:53.736315 ==
6468 13:14:53.739302 DQS Delay:
6469 13:14:53.739728 DQS0 = 27, DQS1 = 43
6470 13:14:53.742997 DQM Delay:
6471 13:14:53.743506 DQM0 = 9, DQM1 = 14
6472 13:14:53.743847 DQ Delay:
6473 13:14:53.746198 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6474 13:14:53.749341 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6475 13:14:53.752809 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6476 13:14:53.756145 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6477 13:14:53.756658
6478 13:14:53.757024
6479 13:14:53.757400 ==
6480 13:14:53.759465 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 13:14:53.762843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 13:14:53.766450 ==
6483 13:14:53.766956
6484 13:14:53.767290
6485 13:14:53.767596 TX Vref Scan disable
6486 13:14:53.768920 == TX Byte 0 ==
6487 13:14:53.772817 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6488 13:14:53.775932 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6489 13:14:53.779415 == TX Byte 1 ==
6490 13:14:53.782978 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6491 13:14:53.785812 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6492 13:14:53.786238 ==
6493 13:14:53.789249 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 13:14:53.795586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 13:14:53.796097 ==
6496 13:14:53.796433
6497 13:14:53.796739
6498 13:14:53.797237 TX Vref Scan disable
6499 13:14:53.799135 == TX Byte 0 ==
6500 13:14:53.802683 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6501 13:14:53.805626 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6502 13:14:53.809036 == TX Byte 1 ==
6503 13:14:53.812498 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6504 13:14:53.815973 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6505 13:14:53.816486
6506 13:14:53.819198 [DATLAT]
6507 13:14:53.819703 Freq=400, CH0 RK1
6508 13:14:53.820038
6509 13:14:53.822801 DATLAT Default: 0xe
6510 13:14:53.823312 0, 0xFFFF, sum = 0
6511 13:14:53.826120 1, 0xFFFF, sum = 0
6512 13:14:53.826629 2, 0xFFFF, sum = 0
6513 13:14:53.829096 3, 0xFFFF, sum = 0
6514 13:14:53.829580 4, 0xFFFF, sum = 0
6515 13:14:53.832193 5, 0xFFFF, sum = 0
6516 13:14:53.832622 6, 0xFFFF, sum = 0
6517 13:14:53.835893 7, 0xFFFF, sum = 0
6518 13:14:53.836476 8, 0xFFFF, sum = 0
6519 13:14:53.839071 9, 0xFFFF, sum = 0
6520 13:14:53.839503 10, 0xFFFF, sum = 0
6521 13:14:53.842018 11, 0xFFFF, sum = 0
6522 13:14:53.842445 12, 0xFFFF, sum = 0
6523 13:14:53.845477 13, 0x0, sum = 1
6524 13:14:53.845909 14, 0x0, sum = 2
6525 13:14:53.848782 15, 0x0, sum = 3
6526 13:14:53.849252 16, 0x0, sum = 4
6527 13:14:53.852248 best_step = 14
6528 13:14:53.852679
6529 13:14:53.853070 ==
6530 13:14:53.855507 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 13:14:53.858700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 13:14:53.859126 ==
6533 13:14:53.862482 RX Vref Scan: 0
6534 13:14:53.862901
6535 13:14:53.863232 RX Vref 0 -> 0, step: 1
6536 13:14:53.863540
6537 13:14:53.865582 RX Delay -327 -> 252, step: 8
6538 13:14:53.873061 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6539 13:14:53.876846 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6540 13:14:53.879863 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6541 13:14:53.883438 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6542 13:14:53.890456 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6543 13:14:53.893695 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6544 13:14:53.896878 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6545 13:14:53.899965 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6546 13:14:53.906504 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6547 13:14:53.910291 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6548 13:14:53.913376 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6549 13:14:53.917063 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6550 13:14:53.923550 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6551 13:14:53.926961 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6552 13:14:53.929940 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6553 13:14:53.933343 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6554 13:14:53.936545 ==
6555 13:14:53.939939 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 13:14:53.943371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 13:14:53.943549 ==
6558 13:14:53.943688 DQS Delay:
6559 13:14:53.946706 DQS0 = 28, DQS1 = 44
6560 13:14:53.946895 DQM Delay:
6561 13:14:53.949973 DQM0 = 9, DQM1 = 16
6562 13:14:53.950115 DQ Delay:
6563 13:14:53.953018 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6564 13:14:53.956102 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6565 13:14:53.959546 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6566 13:14:53.962959 DQ12 =20, DQ13 =24, DQ14 =28, DQ15 =24
6567 13:14:53.963109
6568 13:14:53.963224
6569 13:14:53.969686 [DQSOSCAuto] RK1, (LSB)MR18= 0xc577, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6570 13:14:53.973061 CH0 RK1: MR19=C0C, MR18=C577
6571 13:14:53.979821 CH0_RK1: MR19=0xC0C, MR18=0xC577, DQSOSC=385, MR23=63, INC=398, DEC=265
6572 13:14:53.982963 [RxdqsGatingPostProcess] freq 400
6573 13:14:53.986314 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6574 13:14:53.989584 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 13:14:53.993100 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 13:14:53.996516 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 13:14:53.999587 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 13:14:54.003136 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 13:14:54.006302 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 13:14:54.009147 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 13:14:54.012558 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 13:14:54.016198 Pre-setting of DQS Precalculation
6583 13:14:54.019445 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6584 13:14:54.022944 ==
6585 13:14:54.026199 Dram Type= 6, Freq= 0, CH_1, rank 0
6586 13:14:54.029368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 13:14:54.029486 ==
6588 13:14:54.032477 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6589 13:14:54.039082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6590 13:14:54.042137 [CA 0] Center 36 (8~64) winsize 57
6591 13:14:54.045821 [CA 1] Center 36 (8~64) winsize 57
6592 13:14:54.048953 [CA 2] Center 36 (8~64) winsize 57
6593 13:14:54.052317 [CA 3] Center 36 (8~64) winsize 57
6594 13:14:54.055503 [CA 4] Center 36 (8~64) winsize 57
6595 13:14:54.058940 [CA 5] Center 36 (8~64) winsize 57
6596 13:14:54.059007
6597 13:14:54.062324 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6598 13:14:54.062396
6599 13:14:54.065496 [CATrainingPosCal] consider 1 rank data
6600 13:14:54.069119 u2DelayCellTimex100 = 270/100 ps
6601 13:14:54.072614 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 13:14:54.075682 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 13:14:54.078721 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 13:14:54.082085 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 13:14:54.088854 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 13:14:54.092461 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 13:14:54.092573
6608 13:14:54.095555 CA PerBit enable=1, Macro0, CA PI delay=36
6609 13:14:54.095668
6610 13:14:54.098845 [CBTSetCACLKResult] CA Dly = 36
6611 13:14:54.098969 CS Dly: 1 (0~32)
6612 13:14:54.099066 ==
6613 13:14:54.102241 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 13:14:54.105523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 13:14:54.108760 ==
6616 13:14:54.112306 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 13:14:54.118838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6618 13:14:54.122137 [CA 0] Center 36 (8~64) winsize 57
6619 13:14:54.125562 [CA 1] Center 36 (8~64) winsize 57
6620 13:14:54.129018 [CA 2] Center 36 (8~64) winsize 57
6621 13:14:54.132300 [CA 3] Center 36 (8~64) winsize 57
6622 13:14:54.135504 [CA 4] Center 36 (8~64) winsize 57
6623 13:14:54.138756 [CA 5] Center 36 (8~64) winsize 57
6624 13:14:54.138963
6625 13:14:54.142148 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6626 13:14:54.142371
6627 13:14:54.145592 [CATrainingPosCal] consider 2 rank data
6628 13:14:54.149270 u2DelayCellTimex100 = 270/100 ps
6629 13:14:54.152331 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 13:14:54.155954 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 13:14:54.158830 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 13:14:54.162605 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 13:14:54.165950 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 13:14:54.169485 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 13:14:54.170057
6636 13:14:54.176165 CA PerBit enable=1, Macro0, CA PI delay=36
6637 13:14:54.176602
6638 13:14:54.176967 [CBTSetCACLKResult] CA Dly = 36
6639 13:14:54.179310 CS Dly: 1 (0~32)
6640 13:14:54.179733
6641 13:14:54.182572 ----->DramcWriteLeveling(PI) begin...
6642 13:14:54.183000 ==
6643 13:14:54.185900 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 13:14:54.188946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 13:14:54.189481 ==
6646 13:14:54.192410 Write leveling (Byte 0): 40 => 8
6647 13:14:54.195601 Write leveling (Byte 1): 32 => 0
6648 13:14:54.198873 DramcWriteLeveling(PI) end<-----
6649 13:14:54.199377
6650 13:14:54.199712 ==
6651 13:14:54.202274 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 13:14:54.205643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 13:14:54.206067 ==
6654 13:14:54.209698 [Gating] SW mode calibration
6655 13:14:54.216250 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6656 13:14:54.222109 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6657 13:14:54.225759 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 13:14:54.232257 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 13:14:54.235609 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 13:14:54.238818 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 13:14:54.245385 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 13:14:54.249009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 13:14:54.252004 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 13:14:54.258814 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 13:14:54.262107 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 13:14:54.265231 Total UI for P1: 0, mck2ui 16
6667 13:14:54.269061 best dqsien dly found for B0: ( 0, 14, 24)
6668 13:14:54.271897 Total UI for P1: 0, mck2ui 16
6669 13:14:54.275397 best dqsien dly found for B1: ( 0, 14, 24)
6670 13:14:54.278802 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6671 13:14:54.282421 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6672 13:14:54.282847
6673 13:14:54.285559 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 13:14:54.288866 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 13:14:54.292782 [Gating] SW calibration Done
6676 13:14:54.293247 ==
6677 13:14:54.295679 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 13:14:54.298818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 13:14:54.299114 ==
6680 13:14:54.302026 RX Vref Scan: 0
6681 13:14:54.302306
6682 13:14:54.302483 RX Vref 0 -> 0, step: 1
6683 13:14:54.305466
6684 13:14:54.305702 RX Delay -410 -> 252, step: 16
6685 13:14:54.311899 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6686 13:14:54.315419 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6687 13:14:54.319145 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6688 13:14:54.322501 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6689 13:14:54.328899 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6690 13:14:54.331888 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6691 13:14:54.335872 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6692 13:14:54.338887 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6693 13:14:54.345528 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6694 13:14:54.348482 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6695 13:14:54.351872 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6696 13:14:54.355213 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6697 13:14:54.362449 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6698 13:14:54.365475 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6699 13:14:54.369013 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6700 13:14:54.372232 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6701 13:14:54.375580 ==
6702 13:14:54.379350 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 13:14:54.382162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 13:14:54.382663 ==
6705 13:14:54.383006 DQS Delay:
6706 13:14:54.385409 DQS0 = 27, DQS1 = 43
6707 13:14:54.385865 DQM Delay:
6708 13:14:54.389014 DQM0 = 6, DQM1 = 16
6709 13:14:54.389494 DQ Delay:
6710 13:14:54.392189 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6711 13:14:54.395506 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6712 13:14:54.399153 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6713 13:14:54.402239 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6714 13:14:54.402669
6715 13:14:54.403003
6716 13:14:54.403308 ==
6717 13:14:54.405502 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 13:14:54.408527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 13:14:54.408954 ==
6720 13:14:54.409335
6721 13:14:54.409652
6722 13:14:54.412003 TX Vref Scan disable
6723 13:14:54.412424 == TX Byte 0 ==
6724 13:14:54.419128 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 13:14:54.421930 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 13:14:54.422332 == TX Byte 1 ==
6727 13:14:54.428609 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6728 13:14:54.431871 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6729 13:14:54.432099 ==
6730 13:14:54.435087 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 13:14:54.438478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 13:14:54.438554 ==
6733 13:14:54.438613
6734 13:14:54.438666
6735 13:14:54.441478 TX Vref Scan disable
6736 13:14:54.441553 == TX Byte 0 ==
6737 13:14:54.448144 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 13:14:54.451517 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 13:14:54.451592 == TX Byte 1 ==
6740 13:14:54.458169 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6741 13:14:54.461654 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6742 13:14:54.461752
6743 13:14:54.461825 [DATLAT]
6744 13:14:54.465452 Freq=400, CH1 RK0
6745 13:14:54.465527
6746 13:14:54.465585 DATLAT Default: 0xf
6747 13:14:54.468491 0, 0xFFFF, sum = 0
6748 13:14:54.468567 1, 0xFFFF, sum = 0
6749 13:14:54.471540 2, 0xFFFF, sum = 0
6750 13:14:54.471616 3, 0xFFFF, sum = 0
6751 13:14:54.474922 4, 0xFFFF, sum = 0
6752 13:14:54.474999 5, 0xFFFF, sum = 0
6753 13:14:54.478392 6, 0xFFFF, sum = 0
6754 13:14:54.478494 7, 0xFFFF, sum = 0
6755 13:14:54.481621 8, 0xFFFF, sum = 0
6756 13:14:54.481694 9, 0xFFFF, sum = 0
6757 13:14:54.484855 10, 0xFFFF, sum = 0
6758 13:14:54.488863 11, 0xFFFF, sum = 0
6759 13:14:54.488999 12, 0xFFFF, sum = 0
6760 13:14:54.489105 13, 0x0, sum = 1
6761 13:14:54.491470 14, 0x0, sum = 2
6762 13:14:54.491564 15, 0x0, sum = 3
6763 13:14:54.495466 16, 0x0, sum = 4
6764 13:14:54.495535 best_step = 14
6765 13:14:54.495591
6766 13:14:54.495645 ==
6767 13:14:54.498381 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 13:14:54.505111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 13:14:54.505210 ==
6770 13:14:54.505301 RX Vref Scan: 1
6771 13:14:54.505355
6772 13:14:54.508468 RX Vref 0 -> 0, step: 1
6773 13:14:54.508569
6774 13:14:54.512094 RX Delay -327 -> 252, step: 8
6775 13:14:54.512170
6776 13:14:54.515147 Set Vref, RX VrefLevel [Byte0]: 52
6777 13:14:54.518445 [Byte1]: 50
6778 13:14:54.521429
6779 13:14:54.521520 Final RX Vref Byte 0 = 52 to rank0
6780 13:14:54.525346 Final RX Vref Byte 1 = 50 to rank0
6781 13:14:54.528410 Final RX Vref Byte 0 = 52 to rank1
6782 13:14:54.531560 Final RX Vref Byte 1 = 50 to rank1==
6783 13:14:54.534848 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 13:14:54.541678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 13:14:54.541814 ==
6786 13:14:54.541939 DQS Delay:
6787 13:14:54.544641 DQS0 = 32, DQS1 = 40
6788 13:14:54.544777 DQM Delay:
6789 13:14:54.544896 DQM0 = 11, DQM1 = 12
6790 13:14:54.548230 DQ Delay:
6791 13:14:54.551329 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6792 13:14:54.551432 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6793 13:14:54.554949 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6794 13:14:54.558017 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6795 13:14:54.558106
6796 13:14:54.558192
6797 13:14:54.567831 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0db, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 389 ps
6798 13:14:54.571632 CH1 RK0: MR19=C0C, MR18=A0DB
6799 13:14:54.577894 CH1_RK0: MR19=0xC0C, MR18=0xA0DB, DQSOSC=382, MR23=63, INC=404, DEC=269
6800 13:14:54.577968 ==
6801 13:14:54.581303 Dram Type= 6, Freq= 0, CH_1, rank 1
6802 13:14:54.584511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 13:14:54.584587 ==
6804 13:14:54.587974 [Gating] SW mode calibration
6805 13:14:54.594507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6806 13:14:54.600848 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6807 13:14:54.604073 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 13:14:54.607649 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 13:14:54.614285 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 13:14:54.617910 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 13:14:54.621214 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 13:14:54.624459 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 13:14:54.631129 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 13:14:54.634672 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 13:14:54.637707 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 13:14:54.640905 Total UI for P1: 0, mck2ui 16
6817 13:14:54.644345 best dqsien dly found for B0: ( 0, 14, 24)
6818 13:14:54.647811 Total UI for P1: 0, mck2ui 16
6819 13:14:54.651112 best dqsien dly found for B1: ( 0, 14, 24)
6820 13:14:54.654115 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6821 13:14:54.660785 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6822 13:14:54.660860
6823 13:14:54.663949 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 13:14:54.667816 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 13:14:54.671005 [Gating] SW calibration Done
6826 13:14:54.671079 ==
6827 13:14:54.673902 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 13:14:54.677357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 13:14:54.677433 ==
6830 13:14:54.677492 RX Vref Scan: 0
6831 13:14:54.681171
6832 13:14:54.681246 RX Vref 0 -> 0, step: 1
6833 13:14:54.681305
6834 13:14:54.684103 RX Delay -410 -> 252, step: 16
6835 13:14:54.687175 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6836 13:14:54.693829 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6837 13:14:54.697498 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6838 13:14:54.700688 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6839 13:14:54.704144 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6840 13:14:54.710656 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6841 13:14:54.714226 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6842 13:14:54.717562 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6843 13:14:54.720803 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6844 13:14:54.727428 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6845 13:14:54.730801 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6846 13:14:54.734576 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6847 13:14:54.737776 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6848 13:14:54.744611 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6849 13:14:54.747947 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6850 13:14:54.751082 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6851 13:14:54.751502 ==
6852 13:14:54.754680 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 13:14:54.758379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 13:14:54.761039 ==
6855 13:14:54.761521 DQS Delay:
6856 13:14:54.761862 DQS0 = 35, DQS1 = 43
6857 13:14:54.764302 DQM Delay:
6858 13:14:54.764738 DQM0 = 16, DQM1 = 20
6859 13:14:54.767750 DQ Delay:
6860 13:14:54.770963 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6861 13:14:54.771545 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6862 13:14:54.774257 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6863 13:14:54.777456 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6864 13:14:54.777985
6865 13:14:54.780828
6866 13:14:54.781316 ==
6867 13:14:54.784104 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 13:14:54.787802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 13:14:54.788256 ==
6870 13:14:54.788692
6871 13:14:54.789111
6872 13:14:54.790639 TX Vref Scan disable
6873 13:14:54.791084 == TX Byte 0 ==
6874 13:14:54.794063 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6875 13:14:54.800637 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6876 13:14:54.800867 == TX Byte 1 ==
6877 13:14:54.804074 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6878 13:14:54.810891 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6879 13:14:54.811111 ==
6880 13:14:54.814117 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 13:14:54.817179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 13:14:54.817399 ==
6883 13:14:54.817572
6884 13:14:54.817731
6885 13:14:54.821076 TX Vref Scan disable
6886 13:14:54.821331 == TX Byte 0 ==
6887 13:14:54.823953 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6888 13:14:54.830770 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6889 13:14:54.830992 == TX Byte 1 ==
6890 13:14:54.834006 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6891 13:14:54.840428 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6892 13:14:54.840647
6893 13:14:54.840818 [DATLAT]
6894 13:14:54.840977 Freq=400, CH1 RK1
6895 13:14:54.841147
6896 13:14:54.843747 DATLAT Default: 0xe
6897 13:14:54.847007 0, 0xFFFF, sum = 0
6898 13:14:54.847252 1, 0xFFFF, sum = 0
6899 13:14:54.850553 2, 0xFFFF, sum = 0
6900 13:14:54.850775 3, 0xFFFF, sum = 0
6901 13:14:54.854270 4, 0xFFFF, sum = 0
6902 13:14:54.854570 5, 0xFFFF, sum = 0
6903 13:14:54.857260 6, 0xFFFF, sum = 0
6904 13:14:54.857502 7, 0xFFFF, sum = 0
6905 13:14:54.860742 8, 0xFFFF, sum = 0
6906 13:14:54.860981 9, 0xFFFF, sum = 0
6907 13:14:54.863861 10, 0xFFFF, sum = 0
6908 13:14:54.864084 11, 0xFFFF, sum = 0
6909 13:14:54.867011 12, 0xFFFF, sum = 0
6910 13:14:54.867236 13, 0x0, sum = 1
6911 13:14:54.870458 14, 0x0, sum = 2
6912 13:14:54.870682 15, 0x0, sum = 3
6913 13:14:54.873879 16, 0x0, sum = 4
6914 13:14:54.874104 best_step = 14
6915 13:14:54.874278
6916 13:14:54.874438 ==
6917 13:14:54.877303 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 13:14:54.880992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 13:14:54.883666 ==
6920 13:14:54.883886 RX Vref Scan: 0
6921 13:14:54.884070
6922 13:14:54.887239 RX Vref 0 -> 0, step: 1
6923 13:14:54.887467
6924 13:14:54.890466 RX Delay -327 -> 252, step: 8
6925 13:14:54.893738 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6926 13:14:54.900441 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6927 13:14:54.903650 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6928 13:14:54.907092 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6929 13:14:54.910329 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6930 13:14:54.916763 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6931 13:14:54.920222 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6932 13:14:54.923374 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6933 13:14:54.926689 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6934 13:14:54.933561 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6935 13:14:54.937211 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6936 13:14:54.940554 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6937 13:14:54.943603 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6938 13:14:54.950272 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6939 13:14:54.953651 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6940 13:14:54.956698 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6941 13:14:54.956929 ==
6942 13:14:54.960615 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 13:14:54.966644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 13:14:54.966877 ==
6945 13:14:54.967105 DQS Delay:
6946 13:14:54.970270 DQS0 = 32, DQS1 = 36
6947 13:14:54.970500 DQM Delay:
6948 13:14:54.970728 DQM0 = 12, DQM1 = 11
6949 13:14:54.973758 DQ Delay:
6950 13:14:54.976900 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6951 13:14:54.980267 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6952 13:14:54.980496 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6953 13:14:54.983496 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6954 13:14:54.986716
6955 13:14:54.986937
6956 13:14:54.993699 [DQSOSCAuto] RK1, (LSB)MR18= 0xb15a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6957 13:14:54.996604 CH1 RK1: MR19=C0C, MR18=B15A
6958 13:14:55.003341 CH1_RK1: MR19=0xC0C, MR18=0xB15A, DQSOSC=387, MR23=63, INC=394, DEC=262
6959 13:14:55.006641 [RxdqsGatingPostProcess] freq 400
6960 13:14:55.010296 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6961 13:14:55.013580 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 13:14:55.016576 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 13:14:55.020060 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 13:14:55.023475 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 13:14:55.026713 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 13:14:55.030257 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 13:14:55.033247 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 13:14:55.036843 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 13:14:55.040066 Pre-setting of DQS Precalculation
6970 13:14:55.043296 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6971 13:14:55.049966 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6972 13:14:55.060081 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6973 13:14:55.060160
6974 13:14:55.060222
6975 13:14:55.060279 [Calibration Summary] 800 Mbps
6976 13:14:55.063497 CH 0, Rank 0
6977 13:14:55.063572 SW Impedance : PASS
6978 13:14:55.066498 DUTY Scan : NO K
6979 13:14:55.070243 ZQ Calibration : PASS
6980 13:14:55.070322 Jitter Meter : NO K
6981 13:14:55.073327 CBT Training : PASS
6982 13:14:55.076432 Write leveling : PASS
6983 13:14:55.076511 RX DQS gating : PASS
6984 13:14:55.079996 RX DQ/DQS(RDDQC) : PASS
6985 13:14:55.083339 TX DQ/DQS : PASS
6986 13:14:55.083417 RX DATLAT : PASS
6987 13:14:55.086501 RX DQ/DQS(Engine): PASS
6988 13:14:55.089803 TX OE : NO K
6989 13:14:55.089905 All Pass.
6990 13:14:55.089999
6991 13:14:55.090073 CH 0, Rank 1
6992 13:14:55.093007 SW Impedance : PASS
6993 13:14:55.096619 DUTY Scan : NO K
6994 13:14:55.096698 ZQ Calibration : PASS
6995 13:14:55.099745 Jitter Meter : NO K
6996 13:14:55.103106 CBT Training : PASS
6997 13:14:55.103184 Write leveling : NO K
6998 13:14:55.106436 RX DQS gating : PASS
6999 13:14:55.106515 RX DQ/DQS(RDDQC) : PASS
7000 13:14:55.110297 TX DQ/DQS : PASS
7001 13:14:55.113262 RX DATLAT : PASS
7002 13:14:55.113340 RX DQ/DQS(Engine): PASS
7003 13:14:55.116782 TX OE : NO K
7004 13:14:55.116860 All Pass.
7005 13:14:55.116937
7006 13:14:55.119817 CH 1, Rank 0
7007 13:14:55.119895 SW Impedance : PASS
7008 13:14:55.123029 DUTY Scan : NO K
7009 13:14:55.126969 ZQ Calibration : PASS
7010 13:14:55.127047 Jitter Meter : NO K
7011 13:14:55.130185 CBT Training : PASS
7012 13:14:55.133372 Write leveling : PASS
7013 13:14:55.133450 RX DQS gating : PASS
7014 13:14:55.137174 RX DQ/DQS(RDDQC) : PASS
7015 13:14:55.139791 TX DQ/DQS : PASS
7016 13:14:55.139869 RX DATLAT : PASS
7017 13:14:55.143011 RX DQ/DQS(Engine): PASS
7018 13:14:55.146396 TX OE : NO K
7019 13:14:55.146497 All Pass.
7020 13:14:55.146574
7021 13:14:55.146668 CH 1, Rank 1
7022 13:14:55.150065 SW Impedance : PASS
7023 13:14:55.153019 DUTY Scan : NO K
7024 13:14:55.153133 ZQ Calibration : PASS
7025 13:14:55.156662 Jitter Meter : NO K
7026 13:14:55.156754 CBT Training : PASS
7027 13:14:55.159594 Write leveling : NO K
7028 13:14:55.162664 RX DQS gating : PASS
7029 13:14:55.162794 RX DQ/DQS(RDDQC) : PASS
7030 13:14:55.166238 TX DQ/DQS : PASS
7031 13:14:55.169522 RX DATLAT : PASS
7032 13:14:55.169622 RX DQ/DQS(Engine): PASS
7033 13:14:55.172766 TX OE : NO K
7034 13:14:55.172832 All Pass.
7035 13:14:55.172886
7036 13:14:55.176167 DramC Write-DBI off
7037 13:14:55.179279 PER_BANK_REFRESH: Hybrid Mode
7038 13:14:55.179357 TX_TRACKING: ON
7039 13:14:55.189325 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7040 13:14:55.192768 [FAST_K] Save calibration result to emmc
7041 13:14:55.196021 dramc_set_vcore_voltage set vcore to 725000
7042 13:14:55.199511 Read voltage for 1600, 0
7043 13:14:55.199589 Vio18 = 0
7044 13:14:55.202908 Vcore = 725000
7045 13:14:55.202992 Vdram = 0
7046 13:14:55.203075 Vddq = 0
7047 13:14:55.203153 Vmddr = 0
7048 13:14:55.209550 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7049 13:14:55.213260 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7050 13:14:55.216390 MEM_TYPE=3, freq_sel=13
7051 13:14:55.219509 sv_algorithm_assistance_LP4_3733
7052 13:14:55.222784 ============ PULL DRAM RESETB DOWN ============
7053 13:14:55.226240 ========== PULL DRAM RESETB DOWN end =========
7054 13:14:55.232677 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7055 13:14:55.236108 ===================================
7056 13:14:55.239440 LPDDR4 DRAM CONFIGURATION
7057 13:14:55.243121 ===================================
7058 13:14:55.243354 EX_ROW_EN[0] = 0x0
7059 13:14:55.246335 EX_ROW_EN[1] = 0x0
7060 13:14:55.246619 LP4Y_EN = 0x0
7061 13:14:55.249929 WORK_FSP = 0x1
7062 13:14:55.250148 WL = 0x5
7063 13:14:55.252918 RL = 0x5
7064 13:14:55.253242 BL = 0x2
7065 13:14:55.256167 RPST = 0x0
7066 13:14:55.256468 RD_PRE = 0x0
7067 13:14:55.259712 WR_PRE = 0x1
7068 13:14:55.260003 WR_PST = 0x1
7069 13:14:55.262982 DBI_WR = 0x0
7070 13:14:55.263274 DBI_RD = 0x0
7071 13:14:55.266219 OTF = 0x1
7072 13:14:55.269316 ===================================
7073 13:14:55.272915 ===================================
7074 13:14:55.273154 ANA top config
7075 13:14:55.276472 ===================================
7076 13:14:55.279658 DLL_ASYNC_EN = 0
7077 13:14:55.282839 ALL_SLAVE_EN = 0
7078 13:14:55.286108 NEW_RANK_MODE = 1
7079 13:14:55.286329 DLL_IDLE_MODE = 1
7080 13:14:55.289715 LP45_APHY_COMB_EN = 1
7081 13:14:55.293300 TX_ODT_DIS = 0
7082 13:14:55.296236 NEW_8X_MODE = 1
7083 13:14:55.299541 ===================================
7084 13:14:55.302528 ===================================
7085 13:14:55.306344 data_rate = 3200
7086 13:14:55.306620 CKR = 1
7087 13:14:55.309467 DQ_P2S_RATIO = 8
7088 13:14:55.312754 ===================================
7089 13:14:55.316152 CA_P2S_RATIO = 8
7090 13:14:55.319535 DQ_CA_OPEN = 0
7091 13:14:55.323095 DQ_SEMI_OPEN = 0
7092 13:14:55.326231 CA_SEMI_OPEN = 0
7093 13:14:55.326450 CA_FULL_RATE = 0
7094 13:14:55.329255 DQ_CKDIV4_EN = 0
7095 13:14:55.332608 CA_CKDIV4_EN = 0
7096 13:14:55.336239 CA_PREDIV_EN = 0
7097 13:14:55.339596 PH8_DLY = 12
7098 13:14:55.342887 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7099 13:14:55.343127 DQ_AAMCK_DIV = 4
7100 13:14:55.346190 CA_AAMCK_DIV = 4
7101 13:14:55.350064 CA_ADMCK_DIV = 4
7102 13:14:55.352652 DQ_TRACK_CA_EN = 0
7103 13:14:55.356365 CA_PICK = 1600
7104 13:14:55.359566 CA_MCKIO = 1600
7105 13:14:55.363302 MCKIO_SEMI = 0
7106 13:14:55.363905 PLL_FREQ = 3068
7107 13:14:55.366240 DQ_UI_PI_RATIO = 32
7108 13:14:55.369805 CA_UI_PI_RATIO = 0
7109 13:14:55.372907 ===================================
7110 13:14:55.376504 ===================================
7111 13:14:55.379589 memory_type:LPDDR4
7112 13:14:55.380125 GP_NUM : 10
7113 13:14:55.382936 SRAM_EN : 1
7114 13:14:55.386572 MD32_EN : 0
7115 13:14:55.389707 ===================================
7116 13:14:55.390306 [ANA_INIT] >>>>>>>>>>>>>>
7117 13:14:55.393089 <<<<<< [CONFIGURE PHASE]: ANA_TX
7118 13:14:55.396445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7119 13:14:55.400066 ===================================
7120 13:14:55.403142 data_rate = 3200,PCW = 0X7600
7121 13:14:55.406479 ===================================
7122 13:14:55.409638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7123 13:14:55.416406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 13:14:55.419906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 13:14:55.426250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7126 13:14:55.429701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7127 13:14:55.432931 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7128 13:14:55.433431 [ANA_INIT] flow start
7129 13:14:55.436652 [ANA_INIT] PLL >>>>>>>>
7130 13:14:55.439888 [ANA_INIT] PLL <<<<<<<<
7131 13:14:55.440319 [ANA_INIT] MIDPI >>>>>>>>
7132 13:14:55.443015 [ANA_INIT] MIDPI <<<<<<<<
7133 13:14:55.446713 [ANA_INIT] DLL >>>>>>>>
7134 13:14:55.449927 [ANA_INIT] DLL <<<<<<<<
7135 13:14:55.450362 [ANA_INIT] flow end
7136 13:14:55.453042 ============ LP4 DIFF to SE enter ============
7137 13:14:55.460224 ============ LP4 DIFF to SE exit ============
7138 13:14:55.460657 [ANA_INIT] <<<<<<<<<<<<<
7139 13:14:55.463338 [Flow] Enable top DCM control >>>>>
7140 13:14:55.466842 [Flow] Enable top DCM control <<<<<
7141 13:14:55.470260 Enable DLL master slave shuffle
7142 13:14:55.476968 ==============================================================
7143 13:14:55.477441 Gating Mode config
7144 13:14:55.483202 ==============================================================
7145 13:14:55.486981 Config description:
7146 13:14:55.493267 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7147 13:14:55.500154 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7148 13:14:55.506914 SELPH_MODE 0: By rank 1: By Phase
7149 13:14:55.513689 ==============================================================
7150 13:14:55.514498 GAT_TRACK_EN = 1
7151 13:14:55.516822 RX_GATING_MODE = 2
7152 13:14:55.519967 RX_GATING_TRACK_MODE = 2
7153 13:14:55.523211 SELPH_MODE = 1
7154 13:14:55.526295 PICG_EARLY_EN = 1
7155 13:14:55.529409 VALID_LAT_VALUE = 1
7156 13:14:55.536448 ==============================================================
7157 13:14:55.539556 Enter into Gating configuration >>>>
7158 13:14:55.542923 Exit from Gating configuration <<<<
7159 13:14:55.546181 Enter into DVFS_PRE_config >>>>>
7160 13:14:55.556046 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7161 13:14:55.559798 Exit from DVFS_PRE_config <<<<<
7162 13:14:55.563014 Enter into PICG configuration >>>>
7163 13:14:55.566169 Exit from PICG configuration <<<<
7164 13:14:55.569813 [RX_INPUT] configuration >>>>>
7165 13:14:55.570242 [RX_INPUT] configuration <<<<<
7166 13:14:55.576378 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7167 13:14:55.583149 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7168 13:14:55.586205 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 13:14:55.593120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 13:14:55.599591 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 13:14:55.606464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 13:14:55.609788 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7173 13:14:55.613048 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7174 13:14:55.619694 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7175 13:14:55.623250 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7176 13:14:55.626387 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7177 13:14:55.632981 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7178 13:14:55.636610 ===================================
7179 13:14:55.637115 LPDDR4 DRAM CONFIGURATION
7180 13:14:55.639894 ===================================
7181 13:14:55.642633 EX_ROW_EN[0] = 0x0
7182 13:14:55.643066 EX_ROW_EN[1] = 0x0
7183 13:14:55.646160 LP4Y_EN = 0x0
7184 13:14:55.646665 WORK_FSP = 0x1
7185 13:14:55.650149 WL = 0x5
7186 13:14:55.650651 RL = 0x5
7187 13:14:55.652965 BL = 0x2
7188 13:14:55.656071 RPST = 0x0
7189 13:14:55.656569 RD_PRE = 0x0
7190 13:14:55.660034 WR_PRE = 0x1
7191 13:14:55.660554 WR_PST = 0x1
7192 13:14:55.662829 DBI_WR = 0x0
7193 13:14:55.663253 DBI_RD = 0x0
7194 13:14:55.665833 OTF = 0x1
7195 13:14:55.669236 ===================================
7196 13:14:55.672734 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7197 13:14:55.676278 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7198 13:14:55.679462 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7199 13:14:55.682838 ===================================
7200 13:14:55.686248 LPDDR4 DRAM CONFIGURATION
7201 13:14:55.689801 ===================================
7202 13:14:55.692583 EX_ROW_EN[0] = 0x10
7203 13:14:55.693099 EX_ROW_EN[1] = 0x0
7204 13:14:55.696244 LP4Y_EN = 0x0
7205 13:14:55.696742 WORK_FSP = 0x1
7206 13:14:55.699341 WL = 0x5
7207 13:14:55.699764 RL = 0x5
7208 13:14:55.702944 BL = 0x2
7209 13:14:55.703448 RPST = 0x0
7210 13:14:55.706245 RD_PRE = 0x0
7211 13:14:55.706743 WR_PRE = 0x1
7212 13:14:55.709896 WR_PST = 0x1
7213 13:14:55.710397 DBI_WR = 0x0
7214 13:14:55.712781 DBI_RD = 0x0
7215 13:14:55.713322 OTF = 0x1
7216 13:14:55.716211 ===================================
7217 13:14:55.722928 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7218 13:14:55.723430 ==
7219 13:14:55.726317 Dram Type= 6, Freq= 0, CH_0, rank 0
7220 13:14:55.732748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7221 13:14:55.733307 ==
7222 13:14:55.733649 [Duty_Offset_Calibration]
7223 13:14:55.736047 B0:2 B1:0 CA:1
7224 13:14:55.736483
7225 13:14:55.739384 [DutyScan_Calibration_Flow] k_type=0
7226 13:14:55.747908
7227 13:14:55.748392 ==CLK 0==
7228 13:14:55.750984 Final CLK duty delay cell = -4
7229 13:14:55.754427 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7230 13:14:55.758079 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7231 13:14:55.761213 [-4] AVG Duty = 4906%(X100)
7232 13:14:55.761736
7233 13:14:55.764508 CH0 CLK Duty spec in!! Max-Min= 187%
7234 13:14:55.767699 [DutyScan_Calibration_Flow] ====Done====
7235 13:14:55.768165
7236 13:14:55.770893 [DutyScan_Calibration_Flow] k_type=1
7237 13:14:55.787022
7238 13:14:55.787659 ==DQS 0 ==
7239 13:14:55.790337 Final DQS duty delay cell = 0
7240 13:14:55.794246 [0] MAX Duty = 5249%(X100), DQS PI = 34
7241 13:14:55.797186 [0] MIN Duty = 4969%(X100), DQS PI = 0
7242 13:14:55.797490 [0] AVG Duty = 5109%(X100)
7243 13:14:55.800265
7244 13:14:55.800557 ==DQS 1 ==
7245 13:14:55.803612 Final DQS duty delay cell = -4
7246 13:14:55.806897 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7247 13:14:55.810476 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7248 13:14:55.813690 [-4] AVG Duty = 4969%(X100)
7249 13:14:55.813834
7250 13:14:55.816714 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7251 13:14:55.816904
7252 13:14:55.820269 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7253 13:14:55.823357 [DutyScan_Calibration_Flow] ====Done====
7254 13:14:55.823502
7255 13:14:55.827154 [DutyScan_Calibration_Flow] k_type=3
7256 13:14:55.844361
7257 13:14:55.844505 ==DQM 0 ==
7258 13:14:55.847599 Final DQM duty delay cell = 0
7259 13:14:55.851001 [0] MAX Duty = 5062%(X100), DQS PI = 10
7260 13:14:55.854331 [0] MIN Duty = 4813%(X100), DQS PI = 50
7261 13:14:55.857590 [0] AVG Duty = 4937%(X100)
7262 13:14:55.857734
7263 13:14:55.857846 ==DQM 1 ==
7264 13:14:55.860780 Final DQM duty delay cell = 0
7265 13:14:55.864225 [0] MAX Duty = 5249%(X100), DQS PI = 30
7266 13:14:55.867421 [0] MIN Duty = 5000%(X100), DQS PI = 20
7267 13:14:55.870749 [0] AVG Duty = 5124%(X100)
7268 13:14:55.870905
7269 13:14:55.874100 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7270 13:14:55.874245
7271 13:14:55.877464 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7272 13:14:55.881307 [DutyScan_Calibration_Flow] ====Done====
7273 13:14:55.881504
7274 13:14:55.884071 [DutyScan_Calibration_Flow] k_type=2
7275 13:14:55.901527
7276 13:14:55.901692 ==DQ 0 ==
7277 13:14:55.905058 Final DQ duty delay cell = 0
7278 13:14:55.908491 [0] MAX Duty = 5124%(X100), DQS PI = 34
7279 13:14:55.911804 [0] MIN Duty = 5000%(X100), DQS PI = 0
7280 13:14:55.911998 [0] AVG Duty = 5062%(X100)
7281 13:14:55.912163
7282 13:14:55.914719 ==DQ 1 ==
7283 13:14:55.918032 Final DQ duty delay cell = 0
7284 13:14:55.921420 [0] MAX Duty = 4969%(X100), DQS PI = 44
7285 13:14:55.924606 [0] MIN Duty = 4875%(X100), DQS PI = 10
7286 13:14:55.924749 [0] AVG Duty = 4922%(X100)
7287 13:14:55.924861
7288 13:14:55.928580 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7289 13:14:55.931354
7290 13:14:55.934532 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7291 13:14:55.938538 [DutyScan_Calibration_Flow] ====Done====
7292 13:14:55.938687 ==
7293 13:14:55.941039 Dram Type= 6, Freq= 0, CH_1, rank 0
7294 13:14:55.944693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 13:14:55.944837 ==
7296 13:14:55.947949 [Duty_Offset_Calibration]
7297 13:14:55.948092 B0:0 B1:-1 CA:2
7298 13:14:55.948205
7299 13:14:55.951546 [DutyScan_Calibration_Flow] k_type=0
7300 13:14:55.961860
7301 13:14:55.962121 ==CLK 0==
7302 13:14:55.965046 Final CLK duty delay cell = 0
7303 13:14:55.968440 [0] MAX Duty = 5156%(X100), DQS PI = 10
7304 13:14:55.972156 [0] MIN Duty = 4906%(X100), DQS PI = 46
7305 13:14:55.972447 [0] AVG Duty = 5031%(X100)
7306 13:14:55.975520
7307 13:14:55.978682 CH1 CLK Duty spec in!! Max-Min= 250%
7308 13:14:55.981829 [DutyScan_Calibration_Flow] ====Done====
7309 13:14:55.982121
7310 13:14:55.985268 [DutyScan_Calibration_Flow] k_type=1
7311 13:14:56.001898
7312 13:14:56.002401 ==DQS 0 ==
7313 13:14:56.005279 Final DQS duty delay cell = 0
7314 13:14:56.008500 [0] MAX Duty = 5093%(X100), DQS PI = 24
7315 13:14:56.011424 [0] MIN Duty = 4969%(X100), DQS PI = 0
7316 13:14:56.015193 [0] AVG Duty = 5031%(X100)
7317 13:14:56.015613
7318 13:14:56.015936 ==DQS 1 ==
7319 13:14:56.018481 Final DQS duty delay cell = 0
7320 13:14:56.021596 [0] MAX Duty = 5156%(X100), DQS PI = 0
7321 13:14:56.024902 [0] MIN Duty = 4844%(X100), DQS PI = 34
7322 13:14:56.028013 [0] AVG Duty = 5000%(X100)
7323 13:14:56.028576
7324 13:14:56.031621 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7325 13:14:56.032041
7326 13:14:56.034627 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7327 13:14:56.038259 [DutyScan_Calibration_Flow] ====Done====
7328 13:14:56.038679
7329 13:14:56.041386 [DutyScan_Calibration_Flow] k_type=3
7330 13:14:56.059495
7331 13:14:56.059997 ==DQM 0 ==
7332 13:14:56.062882 Final DQM duty delay cell = 4
7333 13:14:56.066161 [4] MAX Duty = 5125%(X100), DQS PI = 22
7334 13:14:56.069400 [4] MIN Duty = 4969%(X100), DQS PI = 46
7335 13:14:56.069697 [4] AVG Duty = 5047%(X100)
7336 13:14:56.072376
7337 13:14:56.072615 ==DQM 1 ==
7338 13:14:56.075882 Final DQM duty delay cell = 0
7339 13:14:56.079183 [0] MAX Duty = 5281%(X100), DQS PI = 58
7340 13:14:56.082635 [0] MIN Duty = 4876%(X100), DQS PI = 34
7341 13:14:56.082783 [0] AVG Duty = 5078%(X100)
7342 13:14:56.085631
7343 13:14:56.089145 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7344 13:14:56.089267
7345 13:14:56.092424 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7346 13:14:56.096044 [DutyScan_Calibration_Flow] ====Done====
7347 13:14:56.096176
7348 13:14:56.099081 [DutyScan_Calibration_Flow] k_type=2
7349 13:14:56.115816
7350 13:14:56.115896 ==DQ 0 ==
7351 13:14:56.119071 Final DQ duty delay cell = 0
7352 13:14:56.122273 [0] MAX Duty = 5093%(X100), DQS PI = 22
7353 13:14:56.125753 [0] MIN Duty = 4969%(X100), DQS PI = 0
7354 13:14:56.125827 [0] AVG Duty = 5031%(X100)
7355 13:14:56.128978
7356 13:14:56.129067 ==DQ 1 ==
7357 13:14:56.132463 Final DQ duty delay cell = 0
7358 13:14:56.135859 [0] MAX Duty = 5062%(X100), DQS PI = 2
7359 13:14:56.138943 [0] MIN Duty = 4844%(X100), DQS PI = 32
7360 13:14:56.139011 [0] AVG Duty = 4953%(X100)
7361 13:14:56.139068
7362 13:14:56.142287 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7363 13:14:56.142361
7364 13:14:56.148969 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7365 13:14:56.152118 [DutyScan_Calibration_Flow] ====Done====
7366 13:14:56.155906 nWR fixed to 30
7367 13:14:56.155981 [ModeRegInit_LP4] CH0 RK0
7368 13:14:56.158857 [ModeRegInit_LP4] CH0 RK1
7369 13:14:56.162351 [ModeRegInit_LP4] CH1 RK0
7370 13:14:56.162426 [ModeRegInit_LP4] CH1 RK1
7371 13:14:56.165843 match AC timing 5
7372 13:14:56.168948 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7373 13:14:56.172520 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7374 13:14:56.178896 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7375 13:14:56.182375 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7376 13:14:56.189511 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7377 13:14:56.189601 [MiockJmeterHQA]
7378 13:14:56.189667
7379 13:14:56.192649 [DramcMiockJmeter] u1RxGatingPI = 0
7380 13:14:56.196094 0 : 4370, 4142
7381 13:14:56.196189 4 : 4253, 4027
7382 13:14:56.196264 8 : 4253, 4027
7383 13:14:56.199348 12 : 4363, 4137
7384 13:14:56.199452 16 : 4255, 4029
7385 13:14:56.203146 20 : 4363, 4138
7386 13:14:56.203320 24 : 4253, 4026
7387 13:14:56.206028 28 : 4252, 4027
7388 13:14:56.206173 32 : 4252, 4027
7389 13:14:56.206266 36 : 4253, 4026
7390 13:14:56.209383 40 : 4363, 4138
7391 13:14:56.209572 44 : 4253, 4027
7392 13:14:56.213066 48 : 4252, 4027
7393 13:14:56.213285 52 : 4253, 4027
7394 13:14:56.216412 56 : 4252, 4027
7395 13:14:56.216649 60 : 4253, 4027
7396 13:14:56.216779 64 : 4360, 4138
7397 13:14:56.219386 68 : 4363, 4137
7398 13:14:56.219607 72 : 4364, 4140
7399 13:14:56.222622 76 : 4250, 4026
7400 13:14:56.222859 80 : 4250, 4027
7401 13:14:56.225914 84 : 4250, 4027
7402 13:14:56.226101 88 : 4250, 3894
7403 13:14:56.229033 92 : 4360, 0
7404 13:14:56.229272 96 : 4250, 0
7405 13:14:56.229451 100 : 4253, 0
7406 13:14:56.233056 104 : 4360, 0
7407 13:14:56.233536 108 : 4360, 0
7408 13:14:56.233880 112 : 4363, 0
7409 13:14:56.236182 116 : 4250, 0
7410 13:14:56.236686 120 : 4360, 0
7411 13:14:56.239584 124 : 4250, 0
7412 13:14:56.240089 128 : 4250, 0
7413 13:14:56.240431 132 : 4250, 0
7414 13:14:56.242884 136 : 4250, 0
7415 13:14:56.243317 140 : 4253, 0
7416 13:14:56.246178 144 : 4250, 0
7417 13:14:56.246686 148 : 4250, 0
7418 13:14:56.247026 152 : 4255, 0
7419 13:14:56.249790 156 : 4360, 0
7420 13:14:56.250300 160 : 4250, 0
7421 13:14:56.252814 164 : 4361, 0
7422 13:14:56.253276 168 : 4250, 0
7423 13:14:56.253618 172 : 4250, 0
7424 13:14:56.256154 176 : 4250, 0
7425 13:14:56.256662 180 : 4250, 0
7426 13:14:56.259778 184 : 4250, 0
7427 13:14:56.260286 188 : 4250, 0
7428 13:14:56.260630 192 : 4253, 0
7429 13:14:56.262436 196 : 4250, 0
7430 13:14:56.262867 200 : 4250, 8
7431 13:14:56.266185 204 : 4255, 2264
7432 13:14:56.266620 208 : 4250, 4027
7433 13:14:56.266960 212 : 4250, 4027
7434 13:14:56.269410 216 : 4363, 4140
7435 13:14:56.269875 220 : 4250, 4027
7436 13:14:56.272481 224 : 4250, 4027
7437 13:14:56.272911 228 : 4360, 4138
7438 13:14:56.275882 232 : 4360, 4138
7439 13:14:56.276385 236 : 4250, 4027
7440 13:14:56.279029 240 : 4250, 4027
7441 13:14:56.279463 244 : 4250, 4027
7442 13:14:56.282409 248 : 4250, 4027
7443 13:14:56.282842 252 : 4250, 4027
7444 13:14:56.285512 256 : 4360, 4137
7445 13:14:56.285947 260 : 4250, 4027
7446 13:14:56.288865 264 : 4250, 4027
7447 13:14:56.289326 268 : 4360, 4137
7448 13:14:56.292222 272 : 4250, 4027
7449 13:14:56.292726 276 : 4250, 4027
7450 13:14:56.293069 280 : 4361, 4138
7451 13:14:56.295464 284 : 4361, 4138
7452 13:14:56.295895 288 : 4250, 4027
7453 13:14:56.299062 292 : 4250, 4026
7454 13:14:56.299492 296 : 4250, 4027
7455 13:14:56.302172 300 : 4250, 4027
7456 13:14:56.302681 304 : 4250, 4026
7457 13:14:56.305559 308 : 4360, 4138
7458 13:14:56.305991 312 : 4250, 3997
7459 13:14:56.308676 316 : 4250, 2043
7460 13:14:56.309104
7461 13:14:56.309476 MIOCK jitter meter ch=0
7462 13:14:56.309789
7463 13:14:56.311854 1T = (316-92) = 224 dly cells
7464 13:14:56.318743 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7465 13:14:56.319257 ==
7466 13:14:56.321880 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 13:14:56.325241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7468 13:14:56.325665 ==
7469 13:14:56.331910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7470 13:14:56.335310 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7471 13:14:56.339071 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7472 13:14:56.345598 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7473 13:14:56.355131 [CA 0] Center 43 (13~73) winsize 61
7474 13:14:56.358871 [CA 1] Center 43 (13~73) winsize 61
7475 13:14:56.362076 [CA 2] Center 38 (8~68) winsize 61
7476 13:14:56.365002 [CA 3] Center 37 (8~67) winsize 60
7477 13:14:56.368744 [CA 4] Center 36 (6~66) winsize 61
7478 13:14:56.371975 [CA 5] Center 35 (5~65) winsize 61
7479 13:14:56.372478
7480 13:14:56.375443 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7481 13:14:56.375953
7482 13:14:56.378644 [CATrainingPosCal] consider 1 rank data
7483 13:14:56.381523 u2DelayCellTimex100 = 290/100 ps
7484 13:14:56.385087 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7485 13:14:56.391365 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7486 13:14:56.394982 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7487 13:14:56.398129 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7488 13:14:56.401459 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7489 13:14:56.405381 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7490 13:14:56.405881
7491 13:14:56.408543 CA PerBit enable=1, Macro0, CA PI delay=35
7492 13:14:56.409052
7493 13:14:56.411843 [CBTSetCACLKResult] CA Dly = 35
7494 13:14:56.415160 CS Dly: 9 (0~40)
7495 13:14:56.418772 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7496 13:14:56.421742 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7497 13:14:56.422250 ==
7498 13:14:56.424586 Dram Type= 6, Freq= 0, CH_0, rank 1
7499 13:14:56.428666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7500 13:14:56.431706 ==
7501 13:14:56.435090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7502 13:14:56.438232 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7503 13:14:56.444830 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7504 13:14:56.448150 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7505 13:14:56.458752 [CA 0] Center 43 (13~73) winsize 61
7506 13:14:56.461656 [CA 1] Center 43 (13~73) winsize 61
7507 13:14:56.465436 [CA 2] Center 38 (8~68) winsize 61
7508 13:14:56.468821 [CA 3] Center 38 (8~68) winsize 61
7509 13:14:56.472329 [CA 4] Center 36 (6~66) winsize 61
7510 13:14:56.475596 [CA 5] Center 36 (6~66) winsize 61
7511 13:14:56.476103
7512 13:14:56.478703 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7513 13:14:56.479243
7514 13:14:56.482264 [CATrainingPosCal] consider 2 rank data
7515 13:14:56.485194 u2DelayCellTimex100 = 290/100 ps
7516 13:14:56.489116 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7517 13:14:56.495561 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7518 13:14:56.498519 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7519 13:14:56.501453 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7520 13:14:56.505002 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7521 13:14:56.507907 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7522 13:14:56.508103
7523 13:14:56.511346 CA PerBit enable=1, Macro0, CA PI delay=35
7524 13:14:56.511541
7525 13:14:56.514581 [CBTSetCACLKResult] CA Dly = 35
7526 13:14:56.518371 CS Dly: 11 (0~44)
7527 13:14:56.521608 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7528 13:14:56.525075 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7529 13:14:56.525287
7530 13:14:56.528434 ----->DramcWriteLeveling(PI) begin...
7531 13:14:56.528745 ==
7532 13:14:56.531828 Dram Type= 6, Freq= 0, CH_0, rank 0
7533 13:14:56.535035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 13:14:56.538182 ==
7535 13:14:56.538477 Write leveling (Byte 0): 38 => 38
7536 13:14:56.541545 Write leveling (Byte 1): 31 => 31
7537 13:14:56.544884 DramcWriteLeveling(PI) end<-----
7538 13:14:56.545253
7539 13:14:56.545527 ==
7540 13:14:56.548149 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 13:14:56.554910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 13:14:56.555228 ==
7543 13:14:56.555594 [Gating] SW mode calibration
7544 13:14:56.565220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7545 13:14:56.568066 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7546 13:14:56.571511 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 13:14:56.578055 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 13:14:56.581836 1 4 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7549 13:14:56.584969 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7550 13:14:56.591784 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7551 13:14:56.594928 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7552 13:14:56.598359 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 13:14:56.605231 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 13:14:56.608666 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 13:14:56.611702 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 13:14:56.618178 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7557 13:14:56.621785 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7558 13:14:56.625417 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7559 13:14:56.632149 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7560 13:14:56.634743 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 13:14:56.638452 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 13:14:56.645355 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 13:14:56.648347 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7564 13:14:56.651683 1 6 8 | B1->B0 | 2323 403f | 0 1 | (0 0) (0 0)
7565 13:14:56.658272 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7566 13:14:56.661582 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7567 13:14:56.664966 1 6 20 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
7568 13:14:56.668085 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 13:14:56.674925 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 13:14:56.678334 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 13:14:56.681727 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 13:14:56.688381 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7573 13:14:56.691856 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7574 13:14:56.694897 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 13:14:56.701774 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7576 13:14:56.704967 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7577 13:14:56.708273 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 13:14:56.714552 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 13:14:56.717859 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 13:14:56.721699 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 13:14:56.728457 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 13:14:56.731755 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 13:14:56.734644 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 13:14:56.741170 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 13:14:56.744606 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 13:14:56.748008 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 13:14:56.754587 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 13:14:56.757798 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 13:14:56.760758 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7590 13:14:56.768039 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7591 13:14:56.768209 Total UI for P1: 0, mck2ui 16
7592 13:14:56.774602 best dqsien dly found for B0: ( 1, 9, 8)
7593 13:14:56.777576 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7594 13:14:56.780654 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 13:14:56.787571 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 13:14:56.787697 Total UI for P1: 0, mck2ui 16
7597 13:14:56.790806 best dqsien dly found for B1: ( 1, 9, 22)
7598 13:14:56.794002 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7599 13:14:56.800750 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7600 13:14:56.800912
7601 13:14:56.804073 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7602 13:14:56.807909 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7603 13:14:56.810713 [Gating] SW calibration Done
7604 13:14:56.810836 ==
7605 13:14:56.814040 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 13:14:56.817505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 13:14:56.817635 ==
7608 13:14:56.820663 RX Vref Scan: 0
7609 13:14:56.820824
7610 13:14:56.820964 RX Vref 0 -> 0, step: 1
7611 13:14:56.821099
7612 13:14:56.823680 RX Delay 0 -> 252, step: 8
7613 13:14:56.827083 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7614 13:14:56.830347 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7615 13:14:56.837051 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7616 13:14:56.840940 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7617 13:14:56.844172 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7618 13:14:56.847404 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7619 13:14:56.850428 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7620 13:14:56.857252 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7621 13:14:56.860707 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7622 13:14:56.863714 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7623 13:14:56.867147 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7624 13:14:56.870541 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7625 13:14:56.877337 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7626 13:14:56.880557 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7627 13:14:56.883681 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7628 13:14:56.887067 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7629 13:14:56.887143 ==
7630 13:14:56.890317 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 13:14:56.894224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 13:14:56.897013 ==
7633 13:14:56.897089 DQS Delay:
7634 13:14:56.897155 DQS0 = 0, DQS1 = 0
7635 13:14:56.900531 DQM Delay:
7636 13:14:56.900607 DQM0 = 138, DQM1 = 126
7637 13:14:56.904053 DQ Delay:
7638 13:14:56.907455 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7639 13:14:56.910488 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7640 13:14:56.914023 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
7641 13:14:56.917478 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7642 13:14:56.917553
7643 13:14:56.917611
7644 13:14:56.917666 ==
7645 13:14:56.920939 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 13:14:56.924355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 13:14:56.924431 ==
7648 13:14:56.924491
7649 13:14:56.927620
7650 13:14:56.928020 TX Vref Scan disable
7651 13:14:56.930855 == TX Byte 0 ==
7652 13:14:56.934126 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7653 13:14:56.937198 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7654 13:14:56.940990 == TX Byte 1 ==
7655 13:14:56.944624 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7656 13:14:56.947576 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7657 13:14:56.948028 ==
7658 13:14:56.950827 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 13:14:56.957391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 13:14:56.957781 ==
7661 13:14:56.969755
7662 13:14:56.973015 TX Vref early break, caculate TX vref
7663 13:14:56.976500 TX Vref=16, minBit 12, minWin=22, winSum=380
7664 13:14:56.979542 TX Vref=18, minBit 7, minWin=23, winSum=386
7665 13:14:56.982881 TX Vref=20, minBit 7, minWin=23, winSum=396
7666 13:14:56.986411 TX Vref=22, minBit 4, minWin=24, winSum=406
7667 13:14:56.989398 TX Vref=24, minBit 0, minWin=25, winSum=415
7668 13:14:56.996454 TX Vref=26, minBit 4, minWin=25, winSum=423
7669 13:14:56.999691 TX Vref=28, minBit 12, minWin=25, winSum=427
7670 13:14:57.002977 TX Vref=30, minBit 0, minWin=26, winSum=424
7671 13:14:57.005870 TX Vref=32, minBit 0, minWin=25, winSum=415
7672 13:14:57.009526 TX Vref=34, minBit 8, minWin=24, winSum=403
7673 13:14:57.015965 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
7674 13:14:57.016453
7675 13:14:57.019435 Final TX Range 0 Vref 30
7676 13:14:57.019996
7677 13:14:57.020495 ==
7678 13:14:57.023061 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 13:14:57.025833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 13:14:57.026262 ==
7681 13:14:57.026599
7682 13:14:57.026906
7683 13:14:57.029173 TX Vref Scan disable
7684 13:14:57.036006 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7685 13:14:57.036434 == TX Byte 0 ==
7686 13:14:57.039124 u2DelayCellOfst[0]=13 cells (4 PI)
7687 13:14:57.042677 u2DelayCellOfst[1]=20 cells (6 PI)
7688 13:14:57.045889 u2DelayCellOfst[2]=13 cells (4 PI)
7689 13:14:57.049371 u2DelayCellOfst[3]=13 cells (4 PI)
7690 13:14:57.052345 u2DelayCellOfst[4]=10 cells (3 PI)
7691 13:14:57.055806 u2DelayCellOfst[5]=0 cells (0 PI)
7692 13:14:57.059109 u2DelayCellOfst[6]=20 cells (6 PI)
7693 13:14:57.062479 u2DelayCellOfst[7]=16 cells (5 PI)
7694 13:14:57.065512 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7695 13:14:57.069055 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7696 13:14:57.072508 == TX Byte 1 ==
7697 13:14:57.076260 u2DelayCellOfst[8]=0 cells (0 PI)
7698 13:14:57.076681 u2DelayCellOfst[9]=0 cells (0 PI)
7699 13:14:57.078981 u2DelayCellOfst[10]=6 cells (2 PI)
7700 13:14:57.082244 u2DelayCellOfst[11]=3 cells (1 PI)
7701 13:14:57.085432 u2DelayCellOfst[12]=13 cells (4 PI)
7702 13:14:57.088582 u2DelayCellOfst[13]=10 cells (3 PI)
7703 13:14:57.091997 u2DelayCellOfst[14]=16 cells (5 PI)
7704 13:14:57.095511 u2DelayCellOfst[15]=10 cells (3 PI)
7705 13:14:57.098674 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7706 13:14:57.105580 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7707 13:14:57.105727 DramC Write-DBI on
7708 13:14:57.105842 ==
7709 13:14:57.108467 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 13:14:57.112272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 13:14:57.115290 ==
7712 13:14:57.115366
7713 13:14:57.115424
7714 13:14:57.115478 TX Vref Scan disable
7715 13:14:57.118853 == TX Byte 0 ==
7716 13:14:57.122292 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7717 13:14:57.125645 == TX Byte 1 ==
7718 13:14:57.129033 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7719 13:14:57.132478 DramC Write-DBI off
7720 13:14:57.132554
7721 13:14:57.132612 [DATLAT]
7722 13:14:57.132667 Freq=1600, CH0 RK0
7723 13:14:57.132720
7724 13:14:57.135752 DATLAT Default: 0xf
7725 13:14:57.135828 0, 0xFFFF, sum = 0
7726 13:14:57.138890 1, 0xFFFF, sum = 0
7727 13:14:57.138967 2, 0xFFFF, sum = 0
7728 13:14:57.142687 3, 0xFFFF, sum = 0
7729 13:14:57.145341 4, 0xFFFF, sum = 0
7730 13:14:57.145418 5, 0xFFFF, sum = 0
7731 13:14:57.148813 6, 0xFFFF, sum = 0
7732 13:14:57.148890 7, 0xFFFF, sum = 0
7733 13:14:57.151855 8, 0xFFFF, sum = 0
7734 13:14:57.151932 9, 0xFFFF, sum = 0
7735 13:14:57.155295 10, 0xFFFF, sum = 0
7736 13:14:57.155372 11, 0xFFFF, sum = 0
7737 13:14:57.158717 12, 0xFFFF, sum = 0
7738 13:14:57.158795 13, 0xFFFF, sum = 0
7739 13:14:57.162101 14, 0x0, sum = 1
7740 13:14:57.162177 15, 0x0, sum = 2
7741 13:14:57.165774 16, 0x0, sum = 3
7742 13:14:57.165851 17, 0x0, sum = 4
7743 13:14:57.168651 best_step = 15
7744 13:14:57.168727
7745 13:14:57.168785 ==
7746 13:14:57.172019 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 13:14:57.175468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 13:14:57.175545 ==
7749 13:14:57.175604 RX Vref Scan: 1
7750 13:14:57.178979
7751 13:14:57.179068 Set Vref Range= 24 -> 127
7752 13:14:57.179128
7753 13:14:57.181947 RX Vref 24 -> 127, step: 1
7754 13:14:57.182022
7755 13:14:57.185292 RX Delay 19 -> 252, step: 4
7756 13:14:57.185368
7757 13:14:57.188684 Set Vref, RX VrefLevel [Byte0]: 24
7758 13:14:57.191778 [Byte1]: 24
7759 13:14:57.191856
7760 13:14:57.195181 Set Vref, RX VrefLevel [Byte0]: 25
7761 13:14:57.198707 [Byte1]: 25
7762 13:14:57.198782
7763 13:14:57.202258 Set Vref, RX VrefLevel [Byte0]: 26
7764 13:14:57.205462 [Byte1]: 26
7765 13:14:57.209065
7766 13:14:57.209147 Set Vref, RX VrefLevel [Byte0]: 27
7767 13:14:57.212746 [Byte1]: 27
7768 13:14:57.216870
7769 13:14:57.216945 Set Vref, RX VrefLevel [Byte0]: 28
7770 13:14:57.219982 [Byte1]: 28
7771 13:14:57.224367
7772 13:14:57.224445 Set Vref, RX VrefLevel [Byte0]: 29
7773 13:14:57.227738 [Byte1]: 29
7774 13:14:57.232423
7775 13:14:57.232572 Set Vref, RX VrefLevel [Byte0]: 30
7776 13:14:57.235405 [Byte1]: 30
7777 13:14:57.239662
7778 13:14:57.239819 Set Vref, RX VrefLevel [Byte0]: 31
7779 13:14:57.243324 [Byte1]: 31
7780 13:14:57.247379
7781 13:14:57.247554 Set Vref, RX VrefLevel [Byte0]: 32
7782 13:14:57.251030 [Byte1]: 32
7783 13:14:57.254934
7784 13:14:57.255123 Set Vref, RX VrefLevel [Byte0]: 33
7785 13:14:57.258226 [Byte1]: 33
7786 13:14:57.262382
7787 13:14:57.262607 Set Vref, RX VrefLevel [Byte0]: 34
7788 13:14:57.265644 [Byte1]: 34
7789 13:14:57.270438
7790 13:14:57.270702 Set Vref, RX VrefLevel [Byte0]: 35
7791 13:14:57.273474 [Byte1]: 35
7792 13:14:57.277632
7793 13:14:57.277907 Set Vref, RX VrefLevel [Byte0]: 36
7794 13:14:57.281073 [Byte1]: 36
7795 13:14:57.285754
7796 13:14:57.286191 Set Vref, RX VrefLevel [Byte0]: 37
7797 13:14:57.288865 [Byte1]: 37
7798 13:14:57.293216
7799 13:14:57.293848 Set Vref, RX VrefLevel [Byte0]: 38
7800 13:14:57.296745 [Byte1]: 38
7801 13:14:57.300293
7802 13:14:57.300719 Set Vref, RX VrefLevel [Byte0]: 39
7803 13:14:57.304039 [Byte1]: 39
7804 13:14:57.308184
7805 13:14:57.308686 Set Vref, RX VrefLevel [Byte0]: 40
7806 13:14:57.311530 [Byte1]: 40
7807 13:14:57.315301
7808 13:14:57.315721 Set Vref, RX VrefLevel [Byte0]: 41
7809 13:14:57.318881 [Byte1]: 41
7810 13:14:57.322912
7811 13:14:57.323337 Set Vref, RX VrefLevel [Byte0]: 42
7812 13:14:57.326158 [Byte1]: 42
7813 13:14:57.330717
7814 13:14:57.331143 Set Vref, RX VrefLevel [Byte0]: 43
7815 13:14:57.334038 [Byte1]: 43
7816 13:14:57.338279
7817 13:14:57.338703 Set Vref, RX VrefLevel [Byte0]: 44
7818 13:14:57.341917 [Byte1]: 44
7819 13:14:57.345882
7820 13:14:57.346309 Set Vref, RX VrefLevel [Byte0]: 45
7821 13:14:57.349363 [Byte1]: 45
7822 13:14:57.353763
7823 13:14:57.354277 Set Vref, RX VrefLevel [Byte0]: 46
7824 13:14:57.356674 [Byte1]: 46
7825 13:14:57.361208
7826 13:14:57.361718 Set Vref, RX VrefLevel [Byte0]: 47
7827 13:14:57.364217 [Byte1]: 47
7828 13:14:57.368684
7829 13:14:57.369224 Set Vref, RX VrefLevel [Byte0]: 48
7830 13:14:57.371802 [Byte1]: 48
7831 13:14:57.376006
7832 13:14:57.376430 Set Vref, RX VrefLevel [Byte0]: 49
7833 13:14:57.380242 [Byte1]: 49
7834 13:14:57.384128
7835 13:14:57.384637 Set Vref, RX VrefLevel [Byte0]: 50
7836 13:14:57.387188 [Byte1]: 50
7837 13:14:57.391597
7838 13:14:57.392120 Set Vref, RX VrefLevel [Byte0]: 51
7839 13:14:57.394924 [Byte1]: 51
7840 13:14:57.398941
7841 13:14:57.399442 Set Vref, RX VrefLevel [Byte0]: 52
7842 13:14:57.402196 [Byte1]: 52
7843 13:14:57.406508
7844 13:14:57.407013 Set Vref, RX VrefLevel [Byte0]: 53
7845 13:14:57.409865 [Byte1]: 53
7846 13:14:57.414004
7847 13:14:57.414513 Set Vref, RX VrefLevel [Byte0]: 54
7848 13:14:57.417409 [Byte1]: 54
7849 13:14:57.421508
7850 13:14:57.421935 Set Vref, RX VrefLevel [Byte0]: 55
7851 13:14:57.424910 [Byte1]: 55
7852 13:14:57.429159
7853 13:14:57.429697 Set Vref, RX VrefLevel [Byte0]: 56
7854 13:14:57.432345 [Byte1]: 56
7855 13:14:57.436372
7856 13:14:57.436832 Set Vref, RX VrefLevel [Byte0]: 57
7857 13:14:57.439762 [Byte1]: 57
7858 13:14:57.444989
7859 13:14:57.445530 Set Vref, RX VrefLevel [Byte0]: 58
7860 13:14:57.447923 [Byte1]: 58
7861 13:14:57.452041
7862 13:14:57.452540 Set Vref, RX VrefLevel [Byte0]: 59
7863 13:14:57.455682 [Byte1]: 59
7864 13:14:57.459706
7865 13:14:57.460207 Set Vref, RX VrefLevel [Byte0]: 60
7866 13:14:57.462742 [Byte1]: 60
7867 13:14:57.467121
7868 13:14:57.467616 Set Vref, RX VrefLevel [Byte0]: 61
7869 13:14:57.470145 [Byte1]: 61
7870 13:14:57.474782
7871 13:14:57.478028 Set Vref, RX VrefLevel [Byte0]: 62
7872 13:14:57.481341 [Byte1]: 62
7873 13:14:57.481841
7874 13:14:57.484595 Set Vref, RX VrefLevel [Byte0]: 63
7875 13:14:57.488088 [Byte1]: 63
7876 13:14:57.488591
7877 13:14:57.491127 Set Vref, RX VrefLevel [Byte0]: 64
7878 13:14:57.494429 [Byte1]: 64
7879 13:14:57.494854
7880 13:14:57.497773 Set Vref, RX VrefLevel [Byte0]: 65
7881 13:14:57.500988 [Byte1]: 65
7882 13:14:57.505464
7883 13:14:57.505983 Set Vref, RX VrefLevel [Byte0]: 66
7884 13:14:57.508298 [Byte1]: 66
7885 13:14:57.512749
7886 13:14:57.513299 Set Vref, RX VrefLevel [Byte0]: 67
7887 13:14:57.516132 [Byte1]: 67
7888 13:14:57.520160
7889 13:14:57.520588 Set Vref, RX VrefLevel [Byte0]: 68
7890 13:14:57.523671 [Byte1]: 68
7891 13:14:57.527620
7892 13:14:57.528045 Set Vref, RX VrefLevel [Byte0]: 69
7893 13:14:57.531198 [Byte1]: 69
7894 13:14:57.535628
7895 13:14:57.536137 Set Vref, RX VrefLevel [Byte0]: 70
7896 13:14:57.538849 [Byte1]: 70
7897 13:14:57.543275
7898 13:14:57.543839 Set Vref, RX VrefLevel [Byte0]: 71
7899 13:14:57.545968 [Byte1]: 71
7900 13:14:57.550333
7901 13:14:57.550846 Set Vref, RX VrefLevel [Byte0]: 72
7902 13:14:57.553606 [Byte1]: 72
7903 13:14:57.557586
7904 13:14:57.558010 Set Vref, RX VrefLevel [Byte0]: 73
7905 13:14:57.561284 [Byte1]: 73
7906 13:14:57.565190
7907 13:14:57.565618 Set Vref, RX VrefLevel [Byte0]: 74
7908 13:14:57.568665 [Byte1]: 74
7909 13:14:57.573174
7910 13:14:57.573604 Set Vref, RX VrefLevel [Byte0]: 75
7911 13:14:57.576146 [Byte1]: 75
7912 13:14:57.580492
7913 13:14:57.580918 Set Vref, RX VrefLevel [Byte0]: 76
7914 13:14:57.584280 [Byte1]: 76
7915 13:14:57.588027
7916 13:14:57.588450 Set Vref, RX VrefLevel [Byte0]: 77
7917 13:14:57.591743 [Byte1]: 77
7918 13:14:57.595959
7919 13:14:57.596419 Set Vref, RX VrefLevel [Byte0]: 78
7920 13:14:57.599166 [Byte1]: 78
7921 13:14:57.603259
7922 13:14:57.603750 Set Vref, RX VrefLevel [Byte0]: 79
7923 13:14:57.606454 [Byte1]: 79
7924 13:14:57.610995
7925 13:14:57.611420 Set Vref, RX VrefLevel [Byte0]: 80
7926 13:14:57.614438 [Byte1]: 80
7927 13:14:57.618596
7928 13:14:57.619019 Final RX Vref Byte 0 = 60 to rank0
7929 13:14:57.621869 Final RX Vref Byte 1 = 62 to rank0
7930 13:14:57.625208 Final RX Vref Byte 0 = 60 to rank1
7931 13:14:57.628147 Final RX Vref Byte 1 = 62 to rank1==
7932 13:14:57.631764 Dram Type= 6, Freq= 0, CH_0, rank 0
7933 13:14:57.638728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7934 13:14:57.639240 ==
7935 13:14:57.639583 DQS Delay:
7936 13:14:57.639901 DQS0 = 0, DQS1 = 0
7937 13:14:57.641894 DQM Delay:
7938 13:14:57.642280 DQM0 = 136, DQM1 = 125
7939 13:14:57.645274 DQ Delay:
7940 13:14:57.648361 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =132
7941 13:14:57.652118 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =144
7942 13:14:57.655361 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
7943 13:14:57.658821 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7944 13:14:57.659327
7945 13:14:57.659665
7946 13:14:57.659975
7947 13:14:57.661762 [DramC_TX_OE_Calibration] TA2
7948 13:14:57.665033 Original DQ_B0 (3 6) =30, OEN = 27
7949 13:14:57.668744 Original DQ_B1 (3 6) =30, OEN = 27
7950 13:14:57.671601 24, 0x0, End_B0=24 End_B1=24
7951 13:14:57.672055 25, 0x0, End_B0=25 End_B1=25
7952 13:14:57.675074 26, 0x0, End_B0=26 End_B1=26
7953 13:14:57.678270 27, 0x0, End_B0=27 End_B1=27
7954 13:14:57.681829 28, 0x0, End_B0=28 End_B1=28
7955 13:14:57.682264 29, 0x0, End_B0=29 End_B1=29
7956 13:14:57.685014 30, 0x0, End_B0=30 End_B1=30
7957 13:14:57.688525 31, 0x4141, End_B0=30 End_B1=30
7958 13:14:57.692360 Byte0 end_step=30 best_step=27
7959 13:14:57.695514 Byte1 end_step=30 best_step=27
7960 13:14:57.698418 Byte0 TX OE(2T, 0.5T) = (3, 3)
7961 13:14:57.698943 Byte1 TX OE(2T, 0.5T) = (3, 3)
7962 13:14:57.699281
7963 13:14:57.701679
7964 13:14:57.708509 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7965 13:14:57.711765 CH0 RK0: MR19=303, MR18=1D1B
7966 13:14:57.718366 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7967 13:14:57.718861
7968 13:14:57.721599 ----->DramcWriteLeveling(PI) begin...
7969 13:14:57.722033 ==
7970 13:14:57.725072 Dram Type= 6, Freq= 0, CH_0, rank 1
7971 13:14:57.728312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7972 13:14:57.728748 ==
7973 13:14:57.731019 Write leveling (Byte 0): 38 => 38
7974 13:14:57.734608 Write leveling (Byte 1): 28 => 28
7975 13:14:57.737512 DramcWriteLeveling(PI) end<-----
7976 13:14:57.737602
7977 13:14:57.737662 ==
7978 13:14:57.741073 Dram Type= 6, Freq= 0, CH_0, rank 1
7979 13:14:57.744393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 13:14:57.744470 ==
7981 13:14:57.747494 [Gating] SW mode calibration
7982 13:14:57.754671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7983 13:14:57.761322 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7984 13:14:57.764731 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 13:14:57.767687 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 13:14:57.774387 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7987 13:14:57.777783 1 4 12 | B1->B0 | 2424 3232 | 0 1 | (1 1) (1 1)
7988 13:14:57.780988 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7989 13:14:57.787559 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 13:14:57.791115 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 13:14:57.794317 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 13:14:57.801014 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 13:14:57.804525 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 13:14:57.808153 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7995 13:14:57.814678 1 5 12 | B1->B0 | 3434 2929 | 0 0 | (0 1) (0 0)
7996 13:14:57.817900 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7997 13:14:57.821015 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 13:14:57.827951 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 13:14:57.830946 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 13:14:57.834391 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 13:14:57.840618 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 13:14:57.844033 1 6 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8003 13:14:57.847613 1 6 12 | B1->B0 | 2e2e 4343 | 0 1 | (0 0) (0 0)
8004 13:14:57.854061 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 13:14:57.857463 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 13:14:57.860945 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 13:14:57.864086 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 13:14:57.870800 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 13:14:57.874608 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 13:14:57.877476 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 13:14:57.883964 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8012 13:14:57.887489 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 13:14:57.891159 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 13:14:57.897467 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 13:14:57.900672 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 13:14:57.904330 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 13:14:57.911067 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 13:14:57.914264 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 13:14:57.917506 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 13:14:57.924381 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 13:14:57.927586 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 13:14:57.931120 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 13:14:57.937958 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 13:14:57.940950 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 13:14:57.944362 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 13:14:57.951297 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8027 13:14:57.954507 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8028 13:14:57.957819 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8029 13:14:57.961500 Total UI for P1: 0, mck2ui 16
8030 13:14:57.964867 best dqsien dly found for B0: ( 1, 9, 10)
8031 13:14:57.967656 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 13:14:57.971169 Total UI for P1: 0, mck2ui 16
8033 13:14:57.974087 best dqsien dly found for B1: ( 1, 9, 14)
8034 13:14:57.981176 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8035 13:14:57.984301 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8036 13:14:57.984815
8037 13:14:57.987317 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8038 13:14:57.991560 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8039 13:14:57.993871 [Gating] SW calibration Done
8040 13:14:57.994300 ==
8041 13:14:57.997199 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 13:14:58.000862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 13:14:58.001409 ==
8044 13:14:58.003892 RX Vref Scan: 0
8045 13:14:58.004318
8046 13:14:58.004650 RX Vref 0 -> 0, step: 1
8047 13:14:58.004961
8048 13:14:58.007483 RX Delay 0 -> 252, step: 8
8049 13:14:58.011104 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8050 13:14:58.017376 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8051 13:14:58.020702 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8052 13:14:58.023783 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8053 13:14:58.027317 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8054 13:14:58.030863 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8055 13:14:58.034176 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8056 13:14:58.040573 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8057 13:14:58.044346 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8058 13:14:58.047589 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8059 13:14:58.050834 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8060 13:14:58.053714 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8061 13:14:58.061027 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8062 13:14:58.064363 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8063 13:14:58.067011 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8064 13:14:58.070893 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8065 13:14:58.071436 ==
8066 13:14:58.073699 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 13:14:58.080697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 13:14:58.081228 ==
8069 13:14:58.081568 DQS Delay:
8070 13:14:58.083852 DQS0 = 0, DQS1 = 0
8071 13:14:58.084281 DQM Delay:
8072 13:14:58.087286 DQM0 = 135, DQM1 = 125
8073 13:14:58.087790 DQ Delay:
8074 13:14:58.090315 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8075 13:14:58.094079 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8076 13:14:58.097200 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
8077 13:14:58.100410 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8078 13:14:58.100835
8079 13:14:58.101201
8080 13:14:58.101516 ==
8081 13:14:58.103755 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 13:14:58.110403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 13:14:58.110894 ==
8084 13:14:58.111229
8085 13:14:58.111532
8086 13:14:58.111825 TX Vref Scan disable
8087 13:14:58.113755 == TX Byte 0 ==
8088 13:14:58.117178 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8089 13:14:58.123739 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8090 13:14:58.124238 == TX Byte 1 ==
8091 13:14:58.127383 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8092 13:14:58.133857 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8093 13:14:58.134343 ==
8094 13:14:58.137345 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 13:14:58.140552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 13:14:58.141065 ==
8097 13:14:58.155235
8098 13:14:58.158543 TX Vref early break, caculate TX vref
8099 13:14:58.162127 TX Vref=16, minBit 0, minWin=23, winSum=389
8100 13:14:58.165204 TX Vref=18, minBit 0, minWin=24, winSum=399
8101 13:14:58.168306 TX Vref=20, minBit 8, minWin=24, winSum=407
8102 13:14:58.172048 TX Vref=22, minBit 0, minWin=25, winSum=416
8103 13:14:58.175397 TX Vref=24, minBit 8, minWin=25, winSum=425
8104 13:14:58.181359 TX Vref=26, minBit 8, minWin=25, winSum=426
8105 13:14:58.185193 TX Vref=28, minBit 0, minWin=26, winSum=429
8106 13:14:58.188417 TX Vref=30, minBit 8, minWin=25, winSum=423
8107 13:14:58.191842 TX Vref=32, minBit 6, minWin=25, winSum=420
8108 13:14:58.194921 TX Vref=34, minBit 0, minWin=25, winSum=408
8109 13:14:58.197976 TX Vref=36, minBit 2, minWin=24, winSum=398
8110 13:14:58.204674 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8111 13:14:58.205106
8112 13:14:58.208512 Final TX Range 0 Vref 28
8113 13:14:58.209022
8114 13:14:58.209417 ==
8115 13:14:58.211329 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 13:14:58.214878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 13:14:58.215380 ==
8118 13:14:58.215717
8119 13:14:58.218034
8120 13:14:58.218463 TX Vref Scan disable
8121 13:14:58.224685 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8122 13:14:58.225246 == TX Byte 0 ==
8123 13:14:58.228073 u2DelayCellOfst[0]=13 cells (4 PI)
8124 13:14:58.231267 u2DelayCellOfst[1]=20 cells (6 PI)
8125 13:14:58.234364 u2DelayCellOfst[2]=13 cells (4 PI)
8126 13:14:58.237759 u2DelayCellOfst[3]=13 cells (4 PI)
8127 13:14:58.241380 u2DelayCellOfst[4]=10 cells (3 PI)
8128 13:14:58.244678 u2DelayCellOfst[5]=0 cells (0 PI)
8129 13:14:58.248376 u2DelayCellOfst[6]=20 cells (6 PI)
8130 13:14:58.251491 u2DelayCellOfst[7]=20 cells (6 PI)
8131 13:14:58.254311 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8132 13:14:58.257797 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8133 13:14:58.261401 == TX Byte 1 ==
8134 13:14:58.264561 u2DelayCellOfst[8]=0 cells (0 PI)
8135 13:14:58.267398 u2DelayCellOfst[9]=3 cells (1 PI)
8136 13:14:58.270964 u2DelayCellOfst[10]=6 cells (2 PI)
8137 13:14:58.274534 u2DelayCellOfst[11]=3 cells (1 PI)
8138 13:14:58.275076 u2DelayCellOfst[12]=13 cells (4 PI)
8139 13:14:58.277631 u2DelayCellOfst[13]=13 cells (4 PI)
8140 13:14:58.280609 u2DelayCellOfst[14]=13 cells (4 PI)
8141 13:14:58.284578 u2DelayCellOfst[15]=10 cells (3 PI)
8142 13:14:58.290842 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8143 13:14:58.294080 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8144 13:14:58.294591 DramC Write-DBI on
8145 13:14:58.297856 ==
8146 13:14:58.298379 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 13:14:58.304095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 13:14:58.304828 ==
8149 13:14:58.305257
8150 13:14:58.305647
8151 13:14:58.307188 TX Vref Scan disable
8152 13:14:58.307619 == TX Byte 0 ==
8153 13:14:58.313827 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8154 13:14:58.314308 == TX Byte 1 ==
8155 13:14:58.317340 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8156 13:14:58.320479 DramC Write-DBI off
8157 13:14:58.320990
8158 13:14:58.321367 [DATLAT]
8159 13:14:58.323877 Freq=1600, CH0 RK1
8160 13:14:58.324377
8161 13:14:58.324716 DATLAT Default: 0xf
8162 13:14:58.327260 0, 0xFFFF, sum = 0
8163 13:14:58.327783 1, 0xFFFF, sum = 0
8164 13:14:58.330134 2, 0xFFFF, sum = 0
8165 13:14:58.330567 3, 0xFFFF, sum = 0
8166 13:14:58.333520 4, 0xFFFF, sum = 0
8167 13:14:58.336990 5, 0xFFFF, sum = 0
8168 13:14:58.337472 6, 0xFFFF, sum = 0
8169 13:14:58.340038 7, 0xFFFF, sum = 0
8170 13:14:58.340536 8, 0xFFFF, sum = 0
8171 13:14:58.343358 9, 0xFFFF, sum = 0
8172 13:14:58.343796 10, 0xFFFF, sum = 0
8173 13:14:58.346943 11, 0xFFFF, sum = 0
8174 13:14:58.347380 12, 0xFFFF, sum = 0
8175 13:14:58.350025 13, 0xFFFF, sum = 0
8176 13:14:58.350460 14, 0x0, sum = 1
8177 13:14:58.353335 15, 0x0, sum = 2
8178 13:14:58.353898 16, 0x0, sum = 3
8179 13:14:58.356842 17, 0x0, sum = 4
8180 13:14:58.357315 best_step = 15
8181 13:14:58.357657
8182 13:14:58.357936 ==
8183 13:14:58.360217 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 13:14:58.363910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 13:14:58.366802 ==
8186 13:14:58.367232 RX Vref Scan: 0
8187 13:14:58.367578
8188 13:14:58.369891 RX Vref 0 -> 0, step: 1
8189 13:14:58.370317
8190 13:14:58.370649 RX Delay 19 -> 252, step: 4
8191 13:14:58.377653 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8192 13:14:58.381102 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8193 13:14:58.384219 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8194 13:14:58.387828 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8195 13:14:58.390942 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8196 13:14:58.397421 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8197 13:14:58.400589 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8198 13:14:58.404190 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8199 13:14:58.407538 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8200 13:14:58.410763 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8201 13:14:58.417340 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8202 13:14:58.420614 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8203 13:14:58.424061 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8204 13:14:58.426955 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8205 13:14:58.430426 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8206 13:14:58.437072 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8207 13:14:58.437621 ==
8208 13:14:58.440789 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 13:14:58.443666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 13:14:58.444100 ==
8211 13:14:58.444505 DQS Delay:
8212 13:14:58.447298 DQS0 = 0, DQS1 = 0
8213 13:14:58.447807 DQM Delay:
8214 13:14:58.450700 DQM0 = 133, DQM1 = 123
8215 13:14:58.451204 DQ Delay:
8216 13:14:58.453604 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8217 13:14:58.456819 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8218 13:14:58.460569 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8219 13:14:58.464031 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8220 13:14:58.467012
8221 13:14:58.467439
8222 13:14:58.467773
8223 13:14:58.468083 [DramC_TX_OE_Calibration] TA2
8224 13:14:58.469864 Original DQ_B0 (3 6) =30, OEN = 27
8225 13:14:58.473512 Original DQ_B1 (3 6) =30, OEN = 27
8226 13:14:58.477061 24, 0x0, End_B0=24 End_B1=24
8227 13:14:58.480181 25, 0x0, End_B0=25 End_B1=25
8228 13:14:58.483595 26, 0x0, End_B0=26 End_B1=26
8229 13:14:58.484170 27, 0x0, End_B0=27 End_B1=27
8230 13:14:58.486991 28, 0x0, End_B0=28 End_B1=28
8231 13:14:58.490079 29, 0x0, End_B0=29 End_B1=29
8232 13:14:58.493758 30, 0x0, End_B0=30 End_B1=30
8233 13:14:58.496815 31, 0x4141, End_B0=30 End_B1=30
8234 13:14:58.497304 Byte0 end_step=30 best_step=27
8235 13:14:58.500136 Byte1 end_step=30 best_step=27
8236 13:14:58.503463 Byte0 TX OE(2T, 0.5T) = (3, 3)
8237 13:14:58.507141 Byte1 TX OE(2T, 0.5T) = (3, 3)
8238 13:14:58.507649
8239 13:14:58.507986
8240 13:14:58.513968 [DQSOSCAuto] RK1, (LSB)MR18= 0x210d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8241 13:14:58.516865 CH0 RK1: MR19=303, MR18=210D
8242 13:14:58.523230 CH0_RK1: MR19=0x303, MR18=0x210D, DQSOSC=393, MR23=63, INC=23, DEC=15
8243 13:14:58.527003 [RxdqsGatingPostProcess] freq 1600
8244 13:14:58.533224 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8245 13:14:58.537106 best DQS0 dly(2T, 0.5T) = (1, 1)
8246 13:14:58.539757 best DQS1 dly(2T, 0.5T) = (1, 1)
8247 13:14:58.540189 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8248 13:14:58.543158 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8249 13:14:58.546464 best DQS0 dly(2T, 0.5T) = (1, 1)
8250 13:14:58.550642 best DQS1 dly(2T, 0.5T) = (1, 1)
8251 13:14:58.553436 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8252 13:14:58.556437 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8253 13:14:58.560206 Pre-setting of DQS Precalculation
8254 13:14:58.567138 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8255 13:14:58.567645 ==
8256 13:14:58.569597 Dram Type= 6, Freq= 0, CH_1, rank 0
8257 13:14:58.573355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 13:14:58.573856 ==
8259 13:14:58.580083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8260 13:14:58.583722 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8261 13:14:58.586691 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8262 13:14:58.593454 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8263 13:14:58.601540 [CA 0] Center 41 (12~71) winsize 60
8264 13:14:58.604940 [CA 1] Center 42 (12~72) winsize 61
8265 13:14:58.608230 [CA 2] Center 38 (9~68) winsize 60
8266 13:14:58.611205 [CA 3] Center 37 (8~67) winsize 60
8267 13:14:58.615066 [CA 4] Center 37 (8~67) winsize 60
8268 13:14:58.618027 [CA 5] Center 37 (7~67) winsize 61
8269 13:14:58.618533
8270 13:14:58.621579 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8271 13:14:58.622077
8272 13:14:58.624394 [CATrainingPosCal] consider 1 rank data
8273 13:14:58.628134 u2DelayCellTimex100 = 290/100 ps
8274 13:14:58.634424 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8275 13:14:58.637777 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8276 13:14:58.641072 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8277 13:14:58.644189 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8278 13:14:58.647702 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8279 13:14:58.650850 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8280 13:14:58.651283
8281 13:14:58.654407 CA PerBit enable=1, Macro0, CA PI delay=37
8282 13:14:58.654896
8283 13:14:58.657786 [CBTSetCACLKResult] CA Dly = 37
8284 13:14:58.660980 CS Dly: 9 (0~40)
8285 13:14:58.664047 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8286 13:14:58.667516 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8287 13:14:58.667905 ==
8288 13:14:58.670938 Dram Type= 6, Freq= 0, CH_1, rank 1
8289 13:14:58.673806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 13:14:58.677972 ==
8291 13:14:58.680418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8292 13:14:58.683906 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8293 13:14:58.690780 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8294 13:14:58.694159 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8295 13:14:58.704519 [CA 0] Center 43 (14~72) winsize 59
8296 13:14:58.707689 [CA 1] Center 42 (12~72) winsize 61
8297 13:14:58.710890 [CA 2] Center 38 (9~68) winsize 60
8298 13:14:58.714016 [CA 3] Center 38 (9~67) winsize 59
8299 13:14:58.718161 [CA 4] Center 37 (8~67) winsize 60
8300 13:14:58.721064 [CA 5] Center 37 (8~67) winsize 60
8301 13:14:58.721532
8302 13:14:58.724741 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8303 13:14:58.725154
8304 13:14:58.728077 [CATrainingPosCal] consider 2 rank data
8305 13:14:58.731491 u2DelayCellTimex100 = 290/100 ps
8306 13:14:58.734477 CA0 delay=42 (14~71),Diff = 5 PI (16 cell)
8307 13:14:58.740971 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8308 13:14:58.744469 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8309 13:14:58.747645 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8310 13:14:58.750820 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8311 13:14:58.754521 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8312 13:14:58.754902
8313 13:14:58.757399 CA PerBit enable=1, Macro0, CA PI delay=37
8314 13:14:58.757782
8315 13:14:58.760976 [CBTSetCACLKResult] CA Dly = 37
8316 13:14:58.764325 CS Dly: 10 (0~42)
8317 13:14:58.767798 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8318 13:14:58.771421 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8319 13:14:58.771889
8320 13:14:58.774278 ----->DramcWriteLeveling(PI) begin...
8321 13:14:58.774668 ==
8322 13:14:58.778063 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 13:14:58.780895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 13:14:58.784253 ==
8325 13:14:58.784745 Write leveling (Byte 0): 23 => 23
8326 13:14:58.787552 Write leveling (Byte 1): 29 => 29
8327 13:14:58.790859 DramcWriteLeveling(PI) end<-----
8328 13:14:58.791283
8329 13:14:58.791616 ==
8330 13:14:58.794619 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 13:14:58.800642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 13:14:58.801172 ==
8333 13:14:58.801512 [Gating] SW mode calibration
8334 13:14:58.811370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8335 13:14:58.814743 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8336 13:14:58.817556 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 13:14:58.824154 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 13:14:58.827456 1 4 8 | B1->B0 | 2525 3030 | 0 0 | (0 0) (1 1)
8339 13:14:58.831561 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 13:14:58.837770 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 13:14:58.840634 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 13:14:58.844381 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 13:14:58.850642 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 13:14:58.854632 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 13:14:58.857293 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8346 13:14:58.864012 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
8347 13:14:58.867195 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8348 13:14:58.870367 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 13:14:58.877337 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 13:14:58.880675 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 13:14:58.884198 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 13:14:58.890541 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 13:14:58.894043 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8354 13:14:58.897929 1 6 8 | B1->B0 | 2f2f 4444 | 0 0 | (0 0) (0 0)
8355 13:14:58.903885 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 13:14:58.907416 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 13:14:58.910601 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 13:14:58.917047 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 13:14:58.920260 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 13:14:58.923861 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 13:14:58.930898 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 13:14:58.934106 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8363 13:14:58.937255 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8364 13:14:58.940918 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 13:14:58.947200 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 13:14:58.950814 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 13:14:58.954177 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 13:14:58.960872 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 13:14:58.964254 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 13:14:58.967315 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 13:14:58.973746 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 13:14:58.977667 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 13:14:58.980414 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 13:14:58.986958 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 13:14:58.990550 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 13:14:58.993939 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 13:14:59.000733 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8378 13:14:59.003955 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8379 13:14:59.007158 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8380 13:14:59.010614 Total UI for P1: 0, mck2ui 16
8381 13:14:59.013809 best dqsien dly found for B0: ( 1, 9, 6)
8382 13:14:59.020657 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 13:14:59.021212 Total UI for P1: 0, mck2ui 16
8384 13:14:59.024497 best dqsien dly found for B1: ( 1, 9, 10)
8385 13:14:59.027389 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8386 13:14:59.034512 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8387 13:14:59.035012
8388 13:14:59.037559 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8389 13:14:59.040398 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8390 13:14:59.043694 [Gating] SW calibration Done
8391 13:14:59.044120 ==
8392 13:14:59.047470 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 13:14:59.050575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 13:14:59.051009 ==
8395 13:14:59.054092 RX Vref Scan: 0
8396 13:14:59.054593
8397 13:14:59.054932 RX Vref 0 -> 0, step: 1
8398 13:14:59.055245
8399 13:14:59.057294 RX Delay 0 -> 252, step: 8
8400 13:14:59.060854 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8401 13:14:59.064157 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8402 13:14:59.070702 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8403 13:14:59.073821 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8404 13:14:59.077003 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8405 13:14:59.080492 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8406 13:14:59.083991 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8407 13:14:59.087449 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8408 13:14:59.093845 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8409 13:14:59.097038 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8410 13:14:59.100494 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8411 13:14:59.103499 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8412 13:14:59.110161 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8413 13:14:59.113547 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8414 13:14:59.116921 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8415 13:14:59.120254 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8416 13:14:59.120753 ==
8417 13:14:59.123866 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 13:14:59.130435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 13:14:59.130944 ==
8420 13:14:59.131283 DQS Delay:
8421 13:14:59.131595 DQS0 = 0, DQS1 = 0
8422 13:14:59.133856 DQM Delay:
8423 13:14:59.134360 DQM0 = 139, DQM1 = 130
8424 13:14:59.136916 DQ Delay:
8425 13:14:59.139966 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8426 13:14:59.143688 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8427 13:14:59.146899 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8428 13:14:59.150090 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =139
8429 13:14:59.150595
8430 13:14:59.150933
8431 13:14:59.151246 ==
8432 13:14:59.153292 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 13:14:59.156701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 13:14:59.157159 ==
8435 13:14:59.159929
8436 13:14:59.160427
8437 13:14:59.160766 TX Vref Scan disable
8438 13:14:59.163669 == TX Byte 0 ==
8439 13:14:59.167150 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8440 13:14:59.170494 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8441 13:14:59.174017 == TX Byte 1 ==
8442 13:14:59.176524 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8443 13:14:59.180127 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8444 13:14:59.180634 ==
8445 13:14:59.183532 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 13:14:59.189871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 13:14:59.190341 ==
8448 13:14:59.202078
8449 13:14:59.205275 TX Vref early break, caculate TX vref
8450 13:14:59.208677 TX Vref=16, minBit 15, minWin=21, winSum=367
8451 13:14:59.212138 TX Vref=18, minBit 15, minWin=22, winSum=382
8452 13:14:59.215248 TX Vref=20, minBit 10, minWin=23, winSum=387
8453 13:14:59.218664 TX Vref=22, minBit 1, minWin=24, winSum=401
8454 13:14:59.221871 TX Vref=24, minBit 15, minWin=24, winSum=412
8455 13:14:59.229097 TX Vref=26, minBit 11, minWin=25, winSum=418
8456 13:14:59.232114 TX Vref=28, minBit 10, minWin=25, winSum=421
8457 13:14:59.235422 TX Vref=30, minBit 9, minWin=25, winSum=414
8458 13:14:59.238631 TX Vref=32, minBit 10, minWin=24, winSum=408
8459 13:14:59.242278 TX Vref=34, minBit 10, minWin=23, winSum=397
8460 13:14:59.248550 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 28
8461 13:14:59.249055
8462 13:14:59.251646 Final TX Range 0 Vref 28
8463 13:14:59.252107
8464 13:14:59.252447 ==
8465 13:14:59.255575 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 13:14:59.258609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 13:14:59.259046 ==
8468 13:14:59.259381
8469 13:14:59.259689
8470 13:14:59.261823 TX Vref Scan disable
8471 13:14:59.268720 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8472 13:14:59.269274 == TX Byte 0 ==
8473 13:14:59.272092 u2DelayCellOfst[0]=16 cells (5 PI)
8474 13:14:59.274956 u2DelayCellOfst[1]=6 cells (2 PI)
8475 13:14:59.278533 u2DelayCellOfst[2]=0 cells (0 PI)
8476 13:14:59.281895 u2DelayCellOfst[3]=3 cells (1 PI)
8477 13:14:59.285493 u2DelayCellOfst[4]=6 cells (2 PI)
8478 13:14:59.288362 u2DelayCellOfst[5]=16 cells (5 PI)
8479 13:14:59.291589 u2DelayCellOfst[6]=16 cells (5 PI)
8480 13:14:59.295432 u2DelayCellOfst[7]=6 cells (2 PI)
8481 13:14:59.298770 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8482 13:14:59.301997 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8483 13:14:59.304917 == TX Byte 1 ==
8484 13:14:59.308346 u2DelayCellOfst[8]=0 cells (0 PI)
8485 13:14:59.308866 u2DelayCellOfst[9]=0 cells (0 PI)
8486 13:14:59.311434 u2DelayCellOfst[10]=10 cells (3 PI)
8487 13:14:59.314772 u2DelayCellOfst[11]=0 cells (0 PI)
8488 13:14:59.318194 u2DelayCellOfst[12]=13 cells (4 PI)
8489 13:14:59.321485 u2DelayCellOfst[13]=13 cells (4 PI)
8490 13:14:59.324866 u2DelayCellOfst[14]=13 cells (4 PI)
8491 13:14:59.327845 u2DelayCellOfst[15]=13 cells (4 PI)
8492 13:14:59.331527 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8493 13:14:59.338149 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8494 13:14:59.338678 DramC Write-DBI on
8495 13:14:59.339021 ==
8496 13:14:59.341469 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 13:14:59.348426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 13:14:59.348935 ==
8499 13:14:59.349316
8500 13:14:59.349665
8501 13:14:59.349995 TX Vref Scan disable
8502 13:14:59.352423 == TX Byte 0 ==
8503 13:14:59.355048 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8504 13:14:59.358669 == TX Byte 1 ==
8505 13:14:59.362103 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8506 13:14:59.365474 DramC Write-DBI off
8507 13:14:59.365979
8508 13:14:59.366316 [DATLAT]
8509 13:14:59.366629 Freq=1600, CH1 RK0
8510 13:14:59.366933
8511 13:14:59.368570 DATLAT Default: 0xf
8512 13:14:59.368998 0, 0xFFFF, sum = 0
8513 13:14:59.371773 1, 0xFFFF, sum = 0
8514 13:14:59.374956 2, 0xFFFF, sum = 0
8515 13:14:59.375466 3, 0xFFFF, sum = 0
8516 13:14:59.378377 4, 0xFFFF, sum = 0
8517 13:14:59.378885 5, 0xFFFF, sum = 0
8518 13:14:59.381829 6, 0xFFFF, sum = 0
8519 13:14:59.382335 7, 0xFFFF, sum = 0
8520 13:14:59.385246 8, 0xFFFF, sum = 0
8521 13:14:59.385757 9, 0xFFFF, sum = 0
8522 13:14:59.388347 10, 0xFFFF, sum = 0
8523 13:14:59.388779 11, 0xFFFF, sum = 0
8524 13:14:59.391540 12, 0xFFFF, sum = 0
8525 13:14:59.391969 13, 0xFFFF, sum = 0
8526 13:14:59.395246 14, 0x0, sum = 1
8527 13:14:59.395754 15, 0x0, sum = 2
8528 13:14:59.398053 16, 0x0, sum = 3
8529 13:14:59.398484 17, 0x0, sum = 4
8530 13:14:59.402071 best_step = 15
8531 13:14:59.402587
8532 13:14:59.402920 ==
8533 13:14:59.404967 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 13:14:59.408196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 13:14:59.408707 ==
8536 13:14:59.411434 RX Vref Scan: 1
8537 13:14:59.411862
8538 13:14:59.412196 Set Vref Range= 24 -> 127
8539 13:14:59.412507
8540 13:14:59.414739 RX Vref 24 -> 127, step: 1
8541 13:14:59.415165
8542 13:14:59.418179 RX Delay 19 -> 252, step: 4
8543 13:14:59.418678
8544 13:14:59.421627 Set Vref, RX VrefLevel [Byte0]: 24
8545 13:14:59.425059 [Byte1]: 24
8546 13:14:59.425633
8547 13:14:59.428371 Set Vref, RX VrefLevel [Byte0]: 25
8548 13:14:59.431568 [Byte1]: 25
8549 13:14:59.432076
8550 13:14:59.434440 Set Vref, RX VrefLevel [Byte0]: 26
8551 13:14:59.438052 [Byte1]: 26
8552 13:14:59.442234
8553 13:14:59.442677 Set Vref, RX VrefLevel [Byte0]: 27
8554 13:14:59.445274 [Byte1]: 27
8555 13:14:59.449739
8556 13:14:59.450240 Set Vref, RX VrefLevel [Byte0]: 28
8557 13:14:59.453030 [Byte1]: 28
8558 13:14:59.457166
8559 13:14:59.457611 Set Vref, RX VrefLevel [Byte0]: 29
8560 13:14:59.460390 [Byte1]: 29
8561 13:14:59.465271
8562 13:14:59.465772 Set Vref, RX VrefLevel [Byte0]: 30
8563 13:14:59.468109 [Byte1]: 30
8564 13:14:59.472584
8565 13:14:59.473078 Set Vref, RX VrefLevel [Byte0]: 31
8566 13:14:59.476184 [Byte1]: 31
8567 13:14:59.480371
8568 13:14:59.480881 Set Vref, RX VrefLevel [Byte0]: 32
8569 13:14:59.483411 [Byte1]: 32
8570 13:14:59.487425
8571 13:14:59.487919 Set Vref, RX VrefLevel [Byte0]: 33
8572 13:14:59.490825 [Byte1]: 33
8573 13:14:59.495076
8574 13:14:59.495504 Set Vref, RX VrefLevel [Byte0]: 34
8575 13:14:59.498296 [Byte1]: 34
8576 13:14:59.502449
8577 13:14:59.502875 Set Vref, RX VrefLevel [Byte0]: 35
8578 13:14:59.506135 [Byte1]: 35
8579 13:14:59.510195
8580 13:14:59.510706 Set Vref, RX VrefLevel [Byte0]: 36
8581 13:14:59.513767 [Byte1]: 36
8582 13:14:59.518107
8583 13:14:59.518608 Set Vref, RX VrefLevel [Byte0]: 37
8584 13:14:59.521088 [Byte1]: 37
8585 13:14:59.525232
8586 13:14:59.525754 Set Vref, RX VrefLevel [Byte0]: 38
8587 13:14:59.528831 [Byte1]: 38
8588 13:14:59.533223
8589 13:14:59.533722 Set Vref, RX VrefLevel [Byte0]: 39
8590 13:14:59.536320 [Byte1]: 39
8591 13:14:59.540476
8592 13:14:59.540975 Set Vref, RX VrefLevel [Byte0]: 40
8593 13:14:59.544106 [Byte1]: 40
8594 13:14:59.548226
8595 13:14:59.548727 Set Vref, RX VrefLevel [Byte0]: 41
8596 13:14:59.551121 [Byte1]: 41
8597 13:14:59.556039
8598 13:14:59.556539 Set Vref, RX VrefLevel [Byte0]: 42
8599 13:14:59.558891 [Byte1]: 42
8600 13:14:59.563404
8601 13:14:59.564050 Set Vref, RX VrefLevel [Byte0]: 43
8602 13:14:59.566494 [Byte1]: 43
8603 13:14:59.570546
8604 13:14:59.570972 Set Vref, RX VrefLevel [Byte0]: 44
8605 13:14:59.573911 [Byte1]: 44
8606 13:14:59.578365
8607 13:14:59.578871 Set Vref, RX VrefLevel [Byte0]: 45
8608 13:14:59.582037 [Byte1]: 45
8609 13:14:59.586111
8610 13:14:59.586618 Set Vref, RX VrefLevel [Byte0]: 46
8611 13:14:59.589525 [Byte1]: 46
8612 13:14:59.593661
8613 13:14:59.594169 Set Vref, RX VrefLevel [Byte0]: 47
8614 13:14:59.597272 [Byte1]: 47
8615 13:14:59.601044
8616 13:14:59.601588 Set Vref, RX VrefLevel [Byte0]: 48
8617 13:14:59.604341 [Byte1]: 48
8618 13:14:59.608924
8619 13:14:59.609481 Set Vref, RX VrefLevel [Byte0]: 49
8620 13:14:59.612271 [Byte1]: 49
8621 13:14:59.616264
8622 13:14:59.616770 Set Vref, RX VrefLevel [Byte0]: 50
8623 13:14:59.619990 [Byte1]: 50
8624 13:14:59.624346
8625 13:14:59.624852 Set Vref, RX VrefLevel [Byte0]: 51
8626 13:14:59.626873 [Byte1]: 51
8627 13:14:59.631369
8628 13:14:59.631902 Set Vref, RX VrefLevel [Byte0]: 52
8629 13:14:59.634880 [Byte1]: 52
8630 13:14:59.639439
8631 13:14:59.639950 Set Vref, RX VrefLevel [Byte0]: 53
8632 13:14:59.642408 [Byte1]: 53
8633 13:14:59.646805
8634 13:14:59.647315 Set Vref, RX VrefLevel [Byte0]: 54
8635 13:14:59.650181 [Byte1]: 54
8636 13:14:59.654073
8637 13:14:59.654576 Set Vref, RX VrefLevel [Byte0]: 55
8638 13:14:59.657465 [Byte1]: 55
8639 13:14:59.661847
8640 13:14:59.662354 Set Vref, RX VrefLevel [Byte0]: 56
8641 13:14:59.665251 [Byte1]: 56
8642 13:14:59.669333
8643 13:14:59.669756 Set Vref, RX VrefLevel [Byte0]: 57
8644 13:14:59.672884 [Byte1]: 57
8645 13:14:59.676578
8646 13:14:59.677015 Set Vref, RX VrefLevel [Byte0]: 58
8647 13:14:59.680196 [Byte1]: 58
8648 13:14:59.684315
8649 13:14:59.684825 Set Vref, RX VrefLevel [Byte0]: 59
8650 13:14:59.687829 [Byte1]: 59
8651 13:14:59.692686
8652 13:14:59.693225 Set Vref, RX VrefLevel [Byte0]: 60
8653 13:14:59.695754 [Byte1]: 60
8654 13:14:59.699656
8655 13:14:59.700222 Set Vref, RX VrefLevel [Byte0]: 61
8656 13:14:59.702879 [Byte1]: 61
8657 13:14:59.706828
8658 13:14:59.707255 Set Vref, RX VrefLevel [Byte0]: 62
8659 13:14:59.710356 [Byte1]: 62
8660 13:14:59.714443
8661 13:14:59.714871 Set Vref, RX VrefLevel [Byte0]: 63
8662 13:14:59.718355 [Byte1]: 63
8663 13:14:59.722033
8664 13:14:59.722484 Set Vref, RX VrefLevel [Byte0]: 64
8665 13:14:59.725590 [Byte1]: 64
8666 13:14:59.729968
8667 13:14:59.730651 Set Vref, RX VrefLevel [Byte0]: 65
8668 13:14:59.732731 [Byte1]: 65
8669 13:14:59.737429
8670 13:14:59.737940 Set Vref, RX VrefLevel [Byte0]: 66
8671 13:14:59.740864 [Byte1]: 66
8672 13:14:59.744738
8673 13:14:59.745122 Set Vref, RX VrefLevel [Byte0]: 67
8674 13:14:59.748085 [Byte1]: 67
8675 13:14:59.752970
8676 13:14:59.753387 Set Vref, RX VrefLevel [Byte0]: 68
8677 13:14:59.755955 [Byte1]: 68
8678 13:14:59.760352
8679 13:14:59.760813 Set Vref, RX VrefLevel [Byte0]: 69
8680 13:14:59.764138 [Byte1]: 69
8681 13:14:59.768100
8682 13:14:59.768580 Set Vref, RX VrefLevel [Byte0]: 70
8683 13:14:59.771382 [Byte1]: 70
8684 13:14:59.775259
8685 13:14:59.775646 Set Vref, RX VrefLevel [Byte0]: 71
8686 13:14:59.778932 [Byte1]: 71
8687 13:14:59.783169
8688 13:14:59.783633 Set Vref, RX VrefLevel [Byte0]: 72
8689 13:14:59.786363 [Byte1]: 72
8690 13:14:59.790550
8691 13:14:59.791013 Set Vref, RX VrefLevel [Byte0]: 73
8692 13:14:59.793768 [Byte1]: 73
8693 13:14:59.797896
8694 13:14:59.798355 Final RX Vref Byte 0 = 59 to rank0
8695 13:14:59.801066 Final RX Vref Byte 1 = 64 to rank0
8696 13:14:59.804786 Final RX Vref Byte 0 = 59 to rank1
8697 13:14:59.807781 Final RX Vref Byte 1 = 64 to rank1==
8698 13:14:59.811203 Dram Type= 6, Freq= 0, CH_1, rank 0
8699 13:14:59.817888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8700 13:14:59.818394 ==
8701 13:14:59.818736 DQS Delay:
8702 13:14:59.819048 DQS0 = 0, DQS1 = 0
8703 13:14:59.821327 DQM Delay:
8704 13:14:59.821832 DQM0 = 135, DQM1 = 128
8705 13:14:59.824330 DQ Delay:
8706 13:14:59.827873 DQ0 =140, DQ1 =130, DQ2 =122, DQ3 =132
8707 13:14:59.831664 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =132
8708 13:14:59.834678 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8709 13:14:59.838127 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =134
8710 13:14:59.838631
8711 13:14:59.838970
8712 13:14:59.839278
8713 13:14:59.840970 [DramC_TX_OE_Calibration] TA2
8714 13:14:59.844545 Original DQ_B0 (3 6) =30, OEN = 27
8715 13:14:59.848043 Original DQ_B1 (3 6) =30, OEN = 27
8716 13:14:59.851226 24, 0x0, End_B0=24 End_B1=24
8717 13:14:59.851738 25, 0x0, End_B0=25 End_B1=25
8718 13:14:59.854489 26, 0x0, End_B0=26 End_B1=26
8719 13:14:59.857889 27, 0x0, End_B0=27 End_B1=27
8720 13:14:59.861463 28, 0x0, End_B0=28 End_B1=28
8721 13:14:59.864317 29, 0x0, End_B0=29 End_B1=29
8722 13:14:59.864831 30, 0x0, End_B0=30 End_B1=30
8723 13:14:59.867798 31, 0x4141, End_B0=30 End_B1=30
8724 13:14:59.870748 Byte0 end_step=30 best_step=27
8725 13:14:59.874305 Byte1 end_step=30 best_step=27
8726 13:14:59.877559 Byte0 TX OE(2T, 0.5T) = (3, 3)
8727 13:14:59.880538 Byte1 TX OE(2T, 0.5T) = (3, 3)
8728 13:14:59.880915
8729 13:14:59.881281
8730 13:14:59.887560 [DQSOSCAuto] RK0, (LSB)MR18= 0x1726, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 398 ps
8731 13:14:59.891167 CH1 RK0: MR19=303, MR18=1726
8732 13:14:59.897539 CH1_RK0: MR19=0x303, MR18=0x1726, DQSOSC=390, MR23=63, INC=24, DEC=16
8733 13:14:59.898047
8734 13:14:59.901061 ----->DramcWriteLeveling(PI) begin...
8735 13:14:59.901638 ==
8736 13:14:59.903964 Dram Type= 6, Freq= 0, CH_1, rank 1
8737 13:14:59.907607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 13:14:59.908116 ==
8739 13:14:59.910579 Write leveling (Byte 0): 24 => 24
8740 13:14:59.914201 Write leveling (Byte 1): 27 => 27
8741 13:14:59.917682 DramcWriteLeveling(PI) end<-----
8742 13:14:59.918186
8743 13:14:59.918520 ==
8744 13:14:59.921268 Dram Type= 6, Freq= 0, CH_1, rank 1
8745 13:14:59.923802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 13:14:59.924250 ==
8747 13:14:59.927282 [Gating] SW mode calibration
8748 13:14:59.934201 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8749 13:14:59.941181 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8750 13:14:59.944710 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 13:14:59.947605 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 13:14:59.953935 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
8753 13:14:59.957509 1 4 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8754 13:14:59.961113 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8755 13:14:59.967686 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 13:14:59.970996 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 13:14:59.974693 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 13:14:59.980914 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 13:14:59.984274 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 13:14:59.987282 1 5 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 0)
8761 13:14:59.994114 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (1 0) (0 1)
8762 13:14:59.997009 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 13:15:00.000766 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 13:15:00.007058 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 13:15:00.010797 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 13:15:00.013794 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 13:15:00.020771 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 13:15:00.023753 1 6 8 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
8769 13:15:00.027139 1 6 12 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
8770 13:15:00.034074 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 13:15:00.037115 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 13:15:00.040520 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 13:15:00.044097 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 13:15:00.050575 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 13:15:00.053777 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 13:15:00.057278 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8777 13:15:00.063827 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8778 13:15:00.066822 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8779 13:15:00.070479 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 13:15:00.077344 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 13:15:00.080540 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 13:15:00.083785 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 13:15:00.090585 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 13:15:00.093285 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 13:15:00.097085 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 13:15:00.103775 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 13:15:00.106957 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 13:15:00.110271 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 13:15:00.116864 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 13:15:00.120453 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 13:15:00.123579 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 13:15:00.130513 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8793 13:15:00.133693 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8794 13:15:00.137473 Total UI for P1: 0, mck2ui 16
8795 13:15:00.140519 best dqsien dly found for B1: ( 1, 9, 10)
8796 13:15:00.143678 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8797 13:15:00.150607 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 13:15:00.151109 Total UI for P1: 0, mck2ui 16
8799 13:15:00.156861 best dqsien dly found for B0: ( 1, 9, 12)
8800 13:15:00.160227 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8801 13:15:00.163840 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8802 13:15:00.164358
8803 13:15:00.166563 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8804 13:15:00.169855 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8805 13:15:00.173604 [Gating] SW calibration Done
8806 13:15:00.174105 ==
8807 13:15:00.176844 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 13:15:00.180811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 13:15:00.181367 ==
8810 13:15:00.183985 RX Vref Scan: 0
8811 13:15:00.184484
8812 13:15:00.184820 RX Vref 0 -> 0, step: 1
8813 13:15:00.185177
8814 13:15:00.186578 RX Delay 0 -> 252, step: 8
8815 13:15:00.190125 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8816 13:15:00.196703 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8817 13:15:00.199837 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8818 13:15:00.203161 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8819 13:15:00.206477 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8820 13:15:00.209763 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8821 13:15:00.216700 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8822 13:15:00.220011 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8823 13:15:00.223055 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8824 13:15:00.226208 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8825 13:15:00.229387 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8826 13:15:00.236585 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8827 13:15:00.239818 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8828 13:15:00.242923 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8829 13:15:00.246570 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8830 13:15:00.249578 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8831 13:15:00.253033 ==
8832 13:15:00.256187 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 13:15:00.259289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 13:15:00.259723 ==
8835 13:15:00.260060 DQS Delay:
8836 13:15:00.262935 DQS0 = 0, DQS1 = 0
8837 13:15:00.263440 DQM Delay:
8838 13:15:00.265830 DQM0 = 139, DQM1 = 131
8839 13:15:00.266261 DQ Delay:
8840 13:15:00.269572 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8841 13:15:00.272687 DQ4 =139, DQ5 =151, DQ6 =147, DQ7 =139
8842 13:15:00.276194 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8843 13:15:00.279043 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8844 13:15:00.279530
8845 13:15:00.280009
8846 13:15:00.280489 ==
8847 13:15:00.282953 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 13:15:00.289335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 13:15:00.289846 ==
8850 13:15:00.290184
8851 13:15:00.290495
8852 13:15:00.290794 TX Vref Scan disable
8853 13:15:00.292945 == TX Byte 0 ==
8854 13:15:00.296316 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8855 13:15:00.300197 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8856 13:15:00.303001 == TX Byte 1 ==
8857 13:15:00.306608 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8858 13:15:00.309505 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8859 13:15:00.312975 ==
8860 13:15:00.316450 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 13:15:00.319750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 13:15:00.320258 ==
8863 13:15:00.332692
8864 13:15:00.336323 TX Vref early break, caculate TX vref
8865 13:15:00.339328 TX Vref=16, minBit 9, minWin=23, winSum=393
8866 13:15:00.342533 TX Vref=18, minBit 9, minWin=23, winSum=399
8867 13:15:00.346367 TX Vref=20, minBit 13, minWin=24, winSum=409
8868 13:15:00.349590 TX Vref=22, minBit 9, minWin=25, winSum=419
8869 13:15:00.353031 TX Vref=24, minBit 9, minWin=25, winSum=419
8870 13:15:00.359528 TX Vref=26, minBit 9, minWin=25, winSum=431
8871 13:15:00.363013 TX Vref=28, minBit 0, minWin=26, winSum=431
8872 13:15:00.366221 TX Vref=30, minBit 0, minWin=26, winSum=425
8873 13:15:00.369443 TX Vref=32, minBit 0, minWin=25, winSum=416
8874 13:15:00.372722 TX Vref=34, minBit 0, minWin=25, winSum=410
8875 13:15:00.376238 TX Vref=36, minBit 0, minWin=24, winSum=402
8876 13:15:00.383199 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8877 13:15:00.383715
8878 13:15:00.385769 Final TX Range 0 Vref 28
8879 13:15:00.386210
8880 13:15:00.386643 ==
8881 13:15:00.389540 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 13:15:00.392959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 13:15:00.393538 ==
8884 13:15:00.393976
8885 13:15:00.394385
8886 13:15:00.396020 TX Vref Scan disable
8887 13:15:00.403309 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8888 13:15:00.403823 == TX Byte 0 ==
8889 13:15:00.405913 u2DelayCellOfst[0]=13 cells (4 PI)
8890 13:15:00.409337 u2DelayCellOfst[1]=10 cells (3 PI)
8891 13:15:00.412946 u2DelayCellOfst[2]=0 cells (0 PI)
8892 13:15:00.416413 u2DelayCellOfst[3]=3 cells (1 PI)
8893 13:15:00.419469 u2DelayCellOfst[4]=6 cells (2 PI)
8894 13:15:00.423078 u2DelayCellOfst[5]=16 cells (5 PI)
8895 13:15:00.426581 u2DelayCellOfst[6]=16 cells (5 PI)
8896 13:15:00.429619 u2DelayCellOfst[7]=3 cells (1 PI)
8897 13:15:00.432811 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8898 13:15:00.436024 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8899 13:15:00.439318 == TX Byte 1 ==
8900 13:15:00.439747 u2DelayCellOfst[8]=0 cells (0 PI)
8901 13:15:00.442641 u2DelayCellOfst[9]=3 cells (1 PI)
8902 13:15:00.445570 u2DelayCellOfst[10]=10 cells (3 PI)
8903 13:15:00.449115 u2DelayCellOfst[11]=6 cells (2 PI)
8904 13:15:00.452016 u2DelayCellOfst[12]=13 cells (4 PI)
8905 13:15:00.455636 u2DelayCellOfst[13]=13 cells (4 PI)
8906 13:15:00.458880 u2DelayCellOfst[14]=16 cells (5 PI)
8907 13:15:00.462373 u2DelayCellOfst[15]=16 cells (5 PI)
8908 13:15:00.465476 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8909 13:15:00.471913 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8910 13:15:00.472000 DramC Write-DBI on
8911 13:15:00.472079 ==
8912 13:15:00.475172 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 13:15:00.478886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 13:15:00.482298 ==
8915 13:15:00.482379
8916 13:15:00.482455
8917 13:15:00.482527 TX Vref Scan disable
8918 13:15:00.485790 == TX Byte 0 ==
8919 13:15:00.488909 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8920 13:15:00.492567 == TX Byte 1 ==
8921 13:15:00.495501 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8922 13:15:00.498795 DramC Write-DBI off
8923 13:15:00.498874
8924 13:15:00.498951 [DATLAT]
8925 13:15:00.499024 Freq=1600, CH1 RK1
8926 13:15:00.499095
8927 13:15:00.502441 DATLAT Default: 0xf
8928 13:15:00.502520 0, 0xFFFF, sum = 0
8929 13:15:00.505615 1, 0xFFFF, sum = 0
8930 13:15:00.505698 2, 0xFFFF, sum = 0
8931 13:15:00.508741 3, 0xFFFF, sum = 0
8932 13:15:00.512306 4, 0xFFFF, sum = 0
8933 13:15:00.512394 5, 0xFFFF, sum = 0
8934 13:15:00.515366 6, 0xFFFF, sum = 0
8935 13:15:00.515446 7, 0xFFFF, sum = 0
8936 13:15:00.519076 8, 0xFFFF, sum = 0
8937 13:15:00.519157 9, 0xFFFF, sum = 0
8938 13:15:00.522092 10, 0xFFFF, sum = 0
8939 13:15:00.522173 11, 0xFFFF, sum = 0
8940 13:15:00.525354 12, 0xFFFF, sum = 0
8941 13:15:00.525434 13, 0xFFFF, sum = 0
8942 13:15:00.528676 14, 0x0, sum = 1
8943 13:15:00.528755 15, 0x0, sum = 2
8944 13:15:00.531907 16, 0x0, sum = 3
8945 13:15:00.531989 17, 0x0, sum = 4
8946 13:15:00.535468 best_step = 15
8947 13:15:00.535553
8948 13:15:00.535632 ==
8949 13:15:00.538994 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 13:15:00.542350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 13:15:00.542433 ==
8952 13:15:00.545381 RX Vref Scan: 0
8953 13:15:00.545462
8954 13:15:00.545540 RX Vref 0 -> 0, step: 1
8955 13:15:00.545614
8956 13:15:00.548729 RX Delay 19 -> 252, step: 4
8957 13:15:00.552085 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8958 13:15:00.558587 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8959 13:15:00.561849 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8960 13:15:00.564968 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8961 13:15:00.568627 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8962 13:15:00.571653 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8963 13:15:00.575625 iDelay=195, Bit 6, Center 146 (99 ~ 194) 96
8964 13:15:00.582129 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8965 13:15:00.585316 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8966 13:15:00.589005 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8967 13:15:00.591906 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8968 13:15:00.595414 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8969 13:15:00.602039 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8970 13:15:00.605518 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8971 13:15:00.608672 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8972 13:15:00.611985 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8973 13:15:00.612064 ==
8974 13:15:00.615277 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 13:15:00.622154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 13:15:00.622290 ==
8977 13:15:00.622371 DQS Delay:
8978 13:15:00.622444 DQS0 = 0, DQS1 = 0
8979 13:15:00.625169 DQM Delay:
8980 13:15:00.625247 DQM0 = 134, DQM1 = 129
8981 13:15:00.629164 DQ Delay:
8982 13:15:00.631726 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8983 13:15:00.635332 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =132
8984 13:15:00.638357 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
8985 13:15:00.641906 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =140
8986 13:15:00.641989
8987 13:15:00.642071
8988 13:15:00.642148
8989 13:15:00.645232 [DramC_TX_OE_Calibration] TA2
8990 13:15:00.648399 Original DQ_B0 (3 6) =30, OEN = 27
8991 13:15:00.651852 Original DQ_B1 (3 6) =30, OEN = 27
8992 13:15:00.655221 24, 0x0, End_B0=24 End_B1=24
8993 13:15:00.655301 25, 0x0, End_B0=25 End_B1=25
8994 13:15:00.658607 26, 0x0, End_B0=26 End_B1=26
8995 13:15:00.661767 27, 0x0, End_B0=27 End_B1=27
8996 13:15:00.665295 28, 0x0, End_B0=28 End_B1=28
8997 13:15:00.665385 29, 0x0, End_B0=29 End_B1=29
8998 13:15:00.668359 30, 0x0, End_B0=30 End_B1=30
8999 13:15:00.671568 31, 0x4141, End_B0=30 End_B1=30
9000 13:15:00.675185 Byte0 end_step=30 best_step=27
9001 13:15:00.678045 Byte1 end_step=30 best_step=27
9002 13:15:00.681849 Byte0 TX OE(2T, 0.5T) = (3, 3)
9003 13:15:00.684709 Byte1 TX OE(2T, 0.5T) = (3, 3)
9004 13:15:00.684798
9005 13:15:00.684887
9006 13:15:00.692283 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
9007 13:15:00.694928 CH1 RK1: MR19=303, MR18=1F0A
9008 13:15:00.701586 CH1_RK1: MR19=0x303, MR18=0x1F0A, DQSOSC=394, MR23=63, INC=23, DEC=15
9009 13:15:00.705194 [RxdqsGatingPostProcess] freq 1600
9010 13:15:00.708168 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9011 13:15:00.711456 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 13:15:00.715075 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 13:15:00.718630 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 13:15:00.721993 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 13:15:00.725044 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 13:15:00.728344 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 13:15:00.731793 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 13:15:00.735345 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 13:15:00.739018 Pre-setting of DQS Precalculation
9020 13:15:00.741953 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9021 13:15:00.748674 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9022 13:15:00.755071 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9023 13:15:00.758242
9024 13:15:00.758744
9025 13:15:00.759408 [Calibration Summary] 3200 Mbps
9026 13:15:00.761897 CH 0, Rank 0
9027 13:15:00.762338 SW Impedance : PASS
9028 13:15:00.764997 DUTY Scan : NO K
9029 13:15:00.768380 ZQ Calibration : PASS
9030 13:15:00.768791 Jitter Meter : NO K
9031 13:15:00.771453 CBT Training : PASS
9032 13:15:00.774971 Write leveling : PASS
9033 13:15:00.775370 RX DQS gating : PASS
9034 13:15:00.778209 RX DQ/DQS(RDDQC) : PASS
9035 13:15:00.781623 TX DQ/DQS : PASS
9036 13:15:00.782026 RX DATLAT : PASS
9037 13:15:00.785379 RX DQ/DQS(Engine): PASS
9038 13:15:00.788440 TX OE : PASS
9039 13:15:00.788825 All Pass.
9040 13:15:00.789122
9041 13:15:00.789450 CH 0, Rank 1
9042 13:15:00.791665 SW Impedance : PASS
9043 13:15:00.794731 DUTY Scan : NO K
9044 13:15:00.795163 ZQ Calibration : PASS
9045 13:15:00.798290 Jitter Meter : NO K
9046 13:15:00.801710 CBT Training : PASS
9047 13:15:00.802141 Write leveling : PASS
9048 13:15:00.805014 RX DQS gating : PASS
9049 13:15:00.805484 RX DQ/DQS(RDDQC) : PASS
9050 13:15:00.808314 TX DQ/DQS : PASS
9051 13:15:00.811747 RX DATLAT : PASS
9052 13:15:00.812253 RX DQ/DQS(Engine): PASS
9053 13:15:00.815217 TX OE : PASS
9054 13:15:00.815725 All Pass.
9055 13:15:00.816065
9056 13:15:00.818580 CH 1, Rank 0
9057 13:15:00.819004 SW Impedance : PASS
9058 13:15:00.821632 DUTY Scan : NO K
9059 13:15:00.825061 ZQ Calibration : PASS
9060 13:15:00.825632 Jitter Meter : NO K
9061 13:15:00.828362 CBT Training : PASS
9062 13:15:00.831665 Write leveling : PASS
9063 13:15:00.832173 RX DQS gating : PASS
9064 13:15:00.835194 RX DQ/DQS(RDDQC) : PASS
9065 13:15:00.838236 TX DQ/DQS : PASS
9066 13:15:00.838665 RX DATLAT : PASS
9067 13:15:00.841981 RX DQ/DQS(Engine): PASS
9068 13:15:00.844856 TX OE : PASS
9069 13:15:00.845314 All Pass.
9070 13:15:00.845649
9071 13:15:00.845996 CH 1, Rank 1
9072 13:15:00.848400 SW Impedance : PASS
9073 13:15:00.851837 DUTY Scan : NO K
9074 13:15:00.852364 ZQ Calibration : PASS
9075 13:15:00.855037 Jitter Meter : NO K
9076 13:15:00.855545 CBT Training : PASS
9077 13:15:00.858543 Write leveling : PASS
9078 13:15:00.861790 RX DQS gating : PASS
9079 13:15:00.862297 RX DQ/DQS(RDDQC) : PASS
9080 13:15:00.865085 TX DQ/DQS : PASS
9081 13:15:00.868459 RX DATLAT : PASS
9082 13:15:00.868962 RX DQ/DQS(Engine): PASS
9083 13:15:00.871541 TX OE : PASS
9084 13:15:00.871981 All Pass.
9085 13:15:00.872311
9086 13:15:00.874782 DramC Write-DBI on
9087 13:15:00.878079 PER_BANK_REFRESH: Hybrid Mode
9088 13:15:00.878507 TX_TRACKING: ON
9089 13:15:00.888073 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9090 13:15:00.894579 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9091 13:15:00.901673 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 13:15:00.904909 [FAST_K] Save calibration result to emmc
9093 13:15:00.907822 sync common calibartion params.
9094 13:15:00.911739 sync cbt_mode0:1, 1:1
9095 13:15:00.914645 dram_init: ddr_geometry: 2
9096 13:15:00.915145 dram_init: ddr_geometry: 2
9097 13:15:00.918051 dram_init: ddr_geometry: 2
9098 13:15:00.921796 0:dram_rank_size:100000000
9099 13:15:00.924357 1:dram_rank_size:100000000
9100 13:15:00.928109 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9101 13:15:00.930981 DFS_SHUFFLE_HW_MODE: ON
9102 13:15:00.934823 dramc_set_vcore_voltage set vcore to 725000
9103 13:15:00.937766 Read voltage for 1600, 0
9104 13:15:00.938271 Vio18 = 0
9105 13:15:00.938600 Vcore = 725000
9106 13:15:00.941594 Vdram = 0
9107 13:15:00.942110 Vddq = 0
9108 13:15:00.942449 Vmddr = 0
9109 13:15:00.944511 switch to 3200 Mbps bootup
9110 13:15:00.948061 [DramcRunTimeConfig]
9111 13:15:00.948485 PHYPLL
9112 13:15:00.948819 DPM_CONTROL_AFTERK: ON
9113 13:15:00.951026 PER_BANK_REFRESH: ON
9114 13:15:00.954414 REFRESH_OVERHEAD_REDUCTION: ON
9115 13:15:00.954839 CMD_PICG_NEW_MODE: OFF
9116 13:15:00.957868 XRTWTW_NEW_MODE: ON
9117 13:15:00.961163 XRTRTR_NEW_MODE: ON
9118 13:15:00.961590 TX_TRACKING: ON
9119 13:15:00.961924 RDSEL_TRACKING: OFF
9120 13:15:00.964548 DQS Precalculation for DVFS: ON
9121 13:15:00.967605 RX_TRACKING: OFF
9122 13:15:00.968032 HW_GATING DBG: ON
9123 13:15:00.971066 ZQCS_ENABLE_LP4: ON
9124 13:15:00.971492 RX_PICG_NEW_MODE: ON
9125 13:15:00.974311 TX_PICG_NEW_MODE: ON
9126 13:15:00.977852 ENABLE_RX_DCM_DPHY: ON
9127 13:15:00.978355 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9128 13:15:00.981336 DUMMY_READ_FOR_TRACKING: OFF
9129 13:15:00.984452 !!! SPM_CONTROL_AFTERK: OFF
9130 13:15:00.987758 !!! SPM could not control APHY
9131 13:15:00.988227 IMPEDANCE_TRACKING: ON
9132 13:15:00.991086 TEMP_SENSOR: ON
9133 13:15:00.991511 HW_SAVE_FOR_SR: OFF
9134 13:15:00.994383 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9135 13:15:00.998004 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9136 13:15:01.000866 Read ODT Tracking: ON
9137 13:15:01.004411 Refresh Rate DeBounce: ON
9138 13:15:01.004908 DFS_NO_QUEUE_FLUSH: ON
9139 13:15:01.007859 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9140 13:15:01.011015 ENABLE_DFS_RUNTIME_MRW: OFF
9141 13:15:01.014315 DDR_RESERVE_NEW_MODE: ON
9142 13:15:01.014739 MR_CBT_SWITCH_FREQ: ON
9143 13:15:01.017998 =========================
9144 13:15:01.036957 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9145 13:15:01.040367 dram_init: ddr_geometry: 2
9146 13:15:01.059151 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9147 13:15:01.061900 dram_init: dram init end (result: 0)
9148 13:15:01.068605 DRAM-K: Full calibration passed in 24505 msecs
9149 13:15:01.071942 MRC: failed to locate region type 0.
9150 13:15:01.072462 DRAM rank0 size:0x100000000,
9151 13:15:01.075297 DRAM rank1 size=0x100000000
9152 13:15:01.085331 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9153 13:15:01.091733 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9154 13:15:01.098404 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9155 13:15:01.105273 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9156 13:15:01.108194 DRAM rank0 size:0x100000000,
9157 13:15:01.112052 DRAM rank1 size=0x100000000
9158 13:15:01.112472 CBMEM:
9159 13:15:01.115216 IMD: root @ 0xfffff000 254 entries.
9160 13:15:01.118250 IMD: root @ 0xffffec00 62 entries.
9161 13:15:01.121770 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9162 13:15:01.124862 WARNING: RO_VPD is uninitialized or empty.
9163 13:15:01.132043 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9164 13:15:01.138697 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9165 13:15:01.151173 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9166 13:15:01.162713 BS: romstage times (exec / console): total (unknown) / 24004 ms
9167 13:15:01.163236
9168 13:15:01.163572
9169 13:15:01.172670 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9170 13:15:01.176097 ARM64: Exception handlers installed.
9171 13:15:01.179247 ARM64: Testing exception
9172 13:15:01.183098 ARM64: Done test exception
9173 13:15:01.183604 Enumerating buses...
9174 13:15:01.186140 Show all devs... Before device enumeration.
9175 13:15:01.189053 Root Device: enabled 1
9176 13:15:01.193030 CPU_CLUSTER: 0: enabled 1
9177 13:15:01.193491 CPU: 00: enabled 1
9178 13:15:01.195763 Compare with tree...
9179 13:15:01.196209 Root Device: enabled 1
9180 13:15:01.199052 CPU_CLUSTER: 0: enabled 1
9181 13:15:01.202438 CPU: 00: enabled 1
9182 13:15:01.203028 Root Device scanning...
9183 13:15:01.206033 scan_static_bus for Root Device
9184 13:15:01.208865 CPU_CLUSTER: 0 enabled
9185 13:15:01.212507 scan_static_bus for Root Device done
9186 13:15:01.215641 scan_bus: bus Root Device finished in 8 msecs
9187 13:15:01.216065 done
9188 13:15:01.222245 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9189 13:15:01.225648 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9190 13:15:01.232016 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9191 13:15:01.235398 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9192 13:15:01.238790 Allocating resources...
9193 13:15:01.242007 Reading resources...
9194 13:15:01.245521 Root Device read_resources bus 0 link: 0
9195 13:15:01.245952 DRAM rank0 size:0x100000000,
9196 13:15:01.248891 DRAM rank1 size=0x100000000
9197 13:15:01.251924 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9198 13:15:01.255598 CPU: 00 missing read_resources
9199 13:15:01.258855 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9200 13:15:01.265444 Root Device read_resources bus 0 link: 0 done
9201 13:15:01.265835 Done reading resources.
9202 13:15:01.272340 Show resources in subtree (Root Device)...After reading.
9203 13:15:01.275816 Root Device child on link 0 CPU_CLUSTER: 0
9204 13:15:01.278671 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 13:15:01.288736 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 13:15:01.288908 CPU: 00
9207 13:15:01.291694 Root Device assign_resources, bus 0 link: 0
9208 13:15:01.294947 CPU_CLUSTER: 0 missing set_resources
9209 13:15:01.298277 Root Device assign_resources, bus 0 link: 0 done
9210 13:15:01.302030 Done setting resources.
9211 13:15:01.308344 Show resources in subtree (Root Device)...After assigning values.
9212 13:15:01.312539 Root Device child on link 0 CPU_CLUSTER: 0
9213 13:15:01.315212 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 13:15:01.325253 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 13:15:01.325376 CPU: 00
9216 13:15:01.328406 Done allocating resources.
9217 13:15:01.331913 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9218 13:15:01.335409 Enabling resources...
9219 13:15:01.335528 done.
9220 13:15:01.341647 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9221 13:15:01.341808 Initializing devices...
9222 13:15:01.345021 Root Device init
9223 13:15:01.345190 init hardware done!
9224 13:15:01.348183 0x00000018: ctrlr->caps
9225 13:15:01.351835 52.000 MHz: ctrlr->f_max
9226 13:15:01.351959 0.400 MHz: ctrlr->f_min
9227 13:15:01.355026 0x40ff8080: ctrlr->voltages
9228 13:15:01.355150 sclk: 390625
9229 13:15:01.358539 Bus Width = 1
9230 13:15:01.358660 sclk: 390625
9231 13:15:01.358754 Bus Width = 1
9232 13:15:01.362023 Early init status = 3
9233 13:15:01.368600 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9234 13:15:01.371975 in-header: 03 fc 00 00 01 00 00 00
9235 13:15:01.372096 in-data: 00
9236 13:15:01.378595 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9237 13:15:01.381780 in-header: 03 fd 00 00 00 00 00 00
9238 13:15:01.385173 in-data:
9239 13:15:01.388737 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9240 13:15:01.391905 in-header: 03 fc 00 00 01 00 00 00
9241 13:15:01.395936 in-data: 00
9242 13:15:01.398491 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9243 13:15:01.405083 in-header: 03 fd 00 00 00 00 00 00
9244 13:15:01.407560 in-data:
9245 13:15:01.411104 [SSUSB] Setting up USB HOST controller...
9246 13:15:01.414314 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9247 13:15:01.417755 [SSUSB] phy power-on done.
9248 13:15:01.421455 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9249 13:15:01.428085 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9250 13:15:01.431363 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9251 13:15:01.438657 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9252 13:15:01.444734 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9253 13:15:01.451249 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9254 13:15:01.457808 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9255 13:15:01.464385 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9256 13:15:01.467738 SPM: binary array size = 0x9dc
9257 13:15:01.471551 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9258 13:15:01.477816 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9259 13:15:01.484699 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9260 13:15:01.487712 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9261 13:15:01.494163 configure_display: Starting display init
9262 13:15:01.527673 anx7625_power_on_init: Init interface.
9263 13:15:01.531121 anx7625_disable_pd_protocol: Disabled PD feature.
9264 13:15:01.533977 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9265 13:15:01.562414 anx7625_start_dp_work: Secure OCM version=00
9266 13:15:01.566113 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9267 13:15:01.580784 sp_tx_get_edid_block: EDID Block = 1
9268 13:15:01.683567 Extracted contents:
9269 13:15:01.686672 header: 00 ff ff ff ff ff ff 00
9270 13:15:01.690216 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9271 13:15:01.693369 version: 01 04
9272 13:15:01.696587 basic params: 95 1f 11 78 0a
9273 13:15:01.699825 chroma info: 76 90 94 55 54 90 27 21 50 54
9274 13:15:01.703394 established: 00 00 00
9275 13:15:01.710285 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9276 13:15:01.713541 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9277 13:15:01.720156 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9278 13:15:01.726375 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9279 13:15:01.733189 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9280 13:15:01.736663 extensions: 00
9281 13:15:01.737201 checksum: fb
9282 13:15:01.737550
9283 13:15:01.740364 Manufacturer: IVO Model 57d Serial Number 0
9284 13:15:01.743331 Made week 0 of 2020
9285 13:15:01.743856 EDID version: 1.4
9286 13:15:01.746393 Digital display
9287 13:15:01.749663 6 bits per primary color channel
9288 13:15:01.750190 DisplayPort interface
9289 13:15:01.753166 Maximum image size: 31 cm x 17 cm
9290 13:15:01.756821 Gamma: 220%
9291 13:15:01.757461 Check DPMS levels
9292 13:15:01.759610 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9293 13:15:01.762971 First detailed timing is preferred timing
9294 13:15:01.766077 Established timings supported:
9295 13:15:01.769674 Standard timings supported:
9296 13:15:01.770182 Detailed timings
9297 13:15:01.775871 Hex of detail: 383680a07038204018303c0035ae10000019
9298 13:15:01.779475 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9299 13:15:01.786162 0780 0798 07c8 0820 hborder 0
9300 13:15:01.789507 0438 043b 0447 0458 vborder 0
9301 13:15:01.792652 -hsync -vsync
9302 13:15:01.793283 Did detailed timing
9303 13:15:01.796026 Hex of detail: 000000000000000000000000000000000000
9304 13:15:01.799191 Manufacturer-specified data, tag 0
9305 13:15:01.806277 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9306 13:15:01.806871 ASCII string: InfoVision
9307 13:15:01.812993 Hex of detail: 000000fe00523134304e574635205248200a
9308 13:15:01.815755 ASCII string: R140NWF5 RH
9309 13:15:01.816178 Checksum
9310 13:15:01.816514 Checksum: 0xfb (valid)
9311 13:15:01.822728 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9312 13:15:01.825572 DSI data_rate: 832800000 bps
9313 13:15:01.829296 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9314 13:15:01.832932 anx7625_parse_edid: pixelclock(138800).
9315 13:15:01.839553 hactive(1920), hsync(48), hfp(24), hbp(88)
9316 13:15:01.843032 vactive(1080), vsync(12), vfp(3), vbp(17)
9317 13:15:01.846373 anx7625_dsi_config: config dsi.
9318 13:15:01.852492 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9319 13:15:01.865611 anx7625_dsi_config: success to config DSI
9320 13:15:01.868679 anx7625_dp_start: MIPI phy setup OK.
9321 13:15:01.871619 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9322 13:15:01.875026 mtk_ddp_mode_set invalid vrefresh 60
9323 13:15:01.878717 main_disp_path_setup
9324 13:15:01.879254 ovl_layer_smi_id_en
9325 13:15:01.882054 ovl_layer_smi_id_en
9326 13:15:01.882480 ccorr_config
9327 13:15:01.882811 aal_config
9328 13:15:01.885020 gamma_config
9329 13:15:01.885579 postmask_config
9330 13:15:01.888515 dither_config
9331 13:15:01.891832 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9332 13:15:01.898120 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9333 13:15:01.901717 Root Device init finished in 553 msecs
9334 13:15:01.905037 CPU_CLUSTER: 0 init
9335 13:15:01.911601 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9336 13:15:01.915115 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9337 13:15:01.918469 APU_MBOX 0x190000b0 = 0x10001
9338 13:15:01.921755 APU_MBOX 0x190001b0 = 0x10001
9339 13:15:01.925031 APU_MBOX 0x190005b0 = 0x10001
9340 13:15:01.928697 APU_MBOX 0x190006b0 = 0x10001
9341 13:15:01.931732 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9342 13:15:01.944657 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9343 13:15:01.956554 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9344 13:15:01.963807 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9345 13:15:01.974979 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9346 13:15:01.983827 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9347 13:15:01.987503 CPU_CLUSTER: 0 init finished in 81 msecs
9348 13:15:01.990993 Devices initialized
9349 13:15:01.993983 Show all devs... After init.
9350 13:15:01.994407 Root Device: enabled 1
9351 13:15:01.997373 CPU_CLUSTER: 0: enabled 1
9352 13:15:02.000714 CPU: 00: enabled 1
9353 13:15:02.004121 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9354 13:15:02.007377 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9355 13:15:02.010725 ELOG: NV offset 0x57f000 size 0x1000
9356 13:15:02.017353 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9357 13:15:02.024402 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9358 13:15:02.027481 ELOG: Event(17) added with size 13 at 2024-07-18 13:14:51 UTC
9359 13:15:02.030831 out: cmd=0x121: 03 db 21 01 00 00 00 00
9360 13:15:02.035628 in-header: 03 4a 00 00 2c 00 00 00
9361 13:15:02.049257 in-data: f5 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9362 13:15:02.055434 ELOG: Event(A1) added with size 10 at 2024-07-18 13:14:51 UTC
9363 13:15:02.062078 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9364 13:15:02.065426 ELOG: Event(A0) added with size 9 at 2024-07-18 13:14:52 UTC
9365 13:15:02.072531 elog_add_boot_reason: Logged dev mode boot
9366 13:15:02.075522 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9367 13:15:02.079022 Finalize devices...
9368 13:15:02.079446 Devices finalized
9369 13:15:02.085602 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9370 13:15:02.088892 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9371 13:15:02.092367 in-header: 03 07 00 00 08 00 00 00
9372 13:15:02.095286 in-data: aa e4 47 04 13 02 00 00
9373 13:15:02.098743 Chrome EC: UHEPI supported
9374 13:15:02.102061 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9375 13:15:02.106028 in-header: 03 a9 00 00 08 00 00 00
9376 13:15:02.108802 in-data: 84 60 60 08 00 00 00 00
9377 13:15:02.115431 ELOG: Event(91) added with size 10 at 2024-07-18 13:14:52 UTC
9378 13:15:02.119170 Chrome EC: clear events_b mask to 0x0000000020004000
9379 13:15:02.125681 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9380 13:15:02.130342 in-header: 03 fd 00 00 00 00 00 00
9381 13:15:02.133420 in-data:
9382 13:15:02.137022 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9383 13:15:02.140106 Writing coreboot table at 0xffe64000
9384 13:15:02.143428 0. 000000000010a000-0000000000113fff: RAMSTAGE
9385 13:15:02.150224 1. 0000000040000000-00000000400fffff: RAM
9386 13:15:02.153774 2. 0000000040100000-000000004032afff: RAMSTAGE
9387 13:15:02.156973 3. 000000004032b000-00000000545fffff: RAM
9388 13:15:02.160460 4. 0000000054600000-000000005465ffff: BL31
9389 13:15:02.163545 5. 0000000054660000-00000000ffe63fff: RAM
9390 13:15:02.170144 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9391 13:15:02.173250 7. 0000000100000000-000000023fffffff: RAM
9392 13:15:02.176934 Passing 5 GPIOs to payload:
9393 13:15:02.180335 NAME | PORT | POLARITY | VALUE
9394 13:15:02.186973 EC in RW | 0x000000aa | low | undefined
9395 13:15:02.189772 EC interrupt | 0x00000005 | low | undefined
9396 13:15:02.193308 TPM interrupt | 0x000000ab | high | undefined
9397 13:15:02.200098 SD card detect | 0x00000011 | high | undefined
9398 13:15:02.203443 speaker enable | 0x00000093 | high | undefined
9399 13:15:02.207009 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9400 13:15:02.210099 in-header: 03 f9 00 00 02 00 00 00
9401 13:15:02.213572 in-data: 02 00
9402 13:15:02.216767 ADC[4]: Raw value=901032 ID=7
9403 13:15:02.217218 ADC[3]: Raw value=213179 ID=1
9404 13:15:02.220208 RAM Code: 0x71
9405 13:15:02.223690 ADC[6]: Raw value=74502 ID=0
9406 13:15:02.224118 ADC[5]: Raw value=212072 ID=1
9407 13:15:02.226661 SKU Code: 0x1
9408 13:15:02.229993 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4b3c
9409 13:15:02.233031 coreboot table: 964 bytes.
9410 13:15:02.236564 IMD ROOT 0. 0xfffff000 0x00001000
9411 13:15:02.239815 IMD SMALL 1. 0xffffe000 0x00001000
9412 13:15:02.243405 RO MCACHE 2. 0xffffc000 0x00001104
9413 13:15:02.246571 CONSOLE 3. 0xfff7c000 0x00080000
9414 13:15:02.250083 FMAP 4. 0xfff7b000 0x00000452
9415 13:15:02.253018 TIME STAMP 5. 0xfff7a000 0x00000910
9416 13:15:02.256409 VBOOT WORK 6. 0xfff66000 0x00014000
9417 13:15:02.259953 RAMOOPS 7. 0xffe66000 0x00100000
9418 13:15:02.263035 COREBOOT 8. 0xffe64000 0x00002000
9419 13:15:02.266697 IMD small region:
9420 13:15:02.269962 IMD ROOT 0. 0xffffec00 0x00000400
9421 13:15:02.272924 VPD 1. 0xffffeb80 0x0000006c
9422 13:15:02.276464 MMC STATUS 2. 0xffffeb60 0x00000004
9423 13:15:02.280295 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9424 13:15:02.286599 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9425 13:15:02.326974 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9426 13:15:02.330365 Checking segment from ROM address 0x40100000
9427 13:15:02.333478 Checking segment from ROM address 0x4010001c
9428 13:15:02.340413 Loading segment from ROM address 0x40100000
9429 13:15:02.340925 code (compression=0)
9430 13:15:02.350889 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9431 13:15:02.356938 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9432 13:15:02.357427 it's not compressed!
9433 13:15:02.363640 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9434 13:15:02.370196 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9435 13:15:02.388121 Loading segment from ROM address 0x4010001c
9436 13:15:02.388629 Entry Point 0x80000000
9437 13:15:02.390687 Loaded segments
9438 13:15:02.394258 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9439 13:15:02.400966 Jumping to boot code at 0x80000000(0xffe64000)
9440 13:15:02.407588 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9441 13:15:02.414243 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9442 13:15:02.421727 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9443 13:15:02.424958 Checking segment from ROM address 0x40100000
9444 13:15:02.428208 Checking segment from ROM address 0x4010001c
9445 13:15:02.435644 Loading segment from ROM address 0x40100000
9446 13:15:02.436153 code (compression=1)
9447 13:15:02.441966 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9448 13:15:02.452241 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9449 13:15:02.452747 using LZMA
9450 13:15:02.460299 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9451 13:15:02.467284 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9452 13:15:02.470306 Loading segment from ROM address 0x4010001c
9453 13:15:02.470737 Entry Point 0x54601000
9454 13:15:02.473756 Loaded segments
9455 13:15:02.477058 NOTICE: MT8192 bl31_setup
9456 13:15:02.483598 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9457 13:15:02.487563 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9458 13:15:02.490581 WARNING: region 0:
9459 13:15:02.494129 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 13:15:02.494643 WARNING: region 1:
9461 13:15:02.500543 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9462 13:15:02.503508 WARNING: region 2:
9463 13:15:02.507238 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9464 13:15:02.510798 WARNING: region 3:
9465 13:15:02.513919 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 13:15:02.517070 WARNING: region 4:
9467 13:15:02.523521 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 13:15:02.523955 WARNING: region 5:
9469 13:15:02.527246 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 13:15:02.530271 WARNING: region 6:
9471 13:15:02.533482 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 13:15:02.536881 WARNING: region 7:
9473 13:15:02.540573 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 13:15:02.546709 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9475 13:15:02.550441 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9476 13:15:02.553435 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9477 13:15:02.560174 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9478 13:15:02.563690 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9479 13:15:02.570228 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9480 13:15:02.573469 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9481 13:15:02.576910 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9482 13:15:02.583463 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9483 13:15:02.587149 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9484 13:15:02.590140 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9485 13:15:02.596662 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9486 13:15:02.600229 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9487 13:15:02.603176 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9488 13:15:02.609783 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9489 13:15:02.612936 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9490 13:15:02.619817 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9491 13:15:02.623477 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9492 13:15:02.626499 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9493 13:15:02.633339 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9494 13:15:02.636700 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9495 13:15:02.643344 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9496 13:15:02.646352 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9497 13:15:02.649949 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9498 13:15:02.656501 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9499 13:15:02.660156 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9500 13:15:02.667104 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9501 13:15:02.670361 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9502 13:15:02.673365 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9503 13:15:02.679760 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9504 13:15:02.683424 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9505 13:15:02.687070 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9506 13:15:02.693703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9507 13:15:02.697022 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9508 13:15:02.699785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9509 13:15:02.703582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9510 13:15:02.710146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9511 13:15:02.713488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9512 13:15:02.717189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9513 13:15:02.719852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9514 13:15:02.726583 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9515 13:15:02.729612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9516 13:15:02.733469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9517 13:15:02.736725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9518 13:15:02.743278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9519 13:15:02.746168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9520 13:15:02.750004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9521 13:15:02.756244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9522 13:15:02.759657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9523 13:15:02.762962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9524 13:15:02.769171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9525 13:15:02.773268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9526 13:15:02.779493 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9527 13:15:02.782858 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9528 13:15:02.789502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9529 13:15:02.792968 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9530 13:15:02.796347 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9531 13:15:02.802399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9532 13:15:02.806271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9533 13:15:02.812623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9534 13:15:02.815901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9535 13:15:02.822683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9536 13:15:02.825889 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9537 13:15:02.832120 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9538 13:15:02.835387 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9539 13:15:02.838839 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9540 13:15:02.845780 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9541 13:15:02.848915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9542 13:15:02.855865 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9543 13:15:02.858757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9544 13:15:02.865501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9545 13:15:02.869040 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9546 13:15:02.872792 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9547 13:15:02.879196 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9548 13:15:02.882413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9549 13:15:02.889041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9550 13:15:02.892676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9551 13:15:02.899145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9552 13:15:02.902313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9553 13:15:02.908883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9554 13:15:02.912454 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9555 13:15:02.915361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9556 13:15:02.922440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9557 13:15:02.925311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9558 13:15:02.931915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9559 13:15:02.935910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9560 13:15:02.942503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9561 13:15:02.945452 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9562 13:15:02.948670 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9563 13:15:02.955451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9564 13:15:02.958664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9565 13:15:02.965734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9566 13:15:02.969159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9567 13:15:02.975461 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9568 13:15:02.979020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9569 13:15:02.985552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9570 13:15:02.989265 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9571 13:15:02.992471 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9572 13:15:02.995538 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9573 13:15:03.002430 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9574 13:15:03.005314 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9575 13:15:03.008836 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9576 13:15:03.015431 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9577 13:15:03.018589 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9578 13:15:03.022132 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9579 13:15:03.028466 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9580 13:15:03.031904 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9581 13:15:03.038391 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9582 13:15:03.041685 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9583 13:15:03.045276 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9584 13:15:03.052116 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9585 13:15:03.055197 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9586 13:15:03.061561 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9587 13:15:03.064941 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9588 13:15:03.068173 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9589 13:15:03.075398 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9590 13:15:03.078465 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9591 13:15:03.081991 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9592 13:15:03.088742 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9593 13:15:03.092160 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9594 13:15:03.095399 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9595 13:15:03.098345 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9596 13:15:03.105316 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9597 13:15:03.108598 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9598 13:15:03.111904 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9599 13:15:03.118303 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9600 13:15:03.121553 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9601 13:15:03.128228 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9602 13:15:03.131486 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9603 13:15:03.134796 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9604 13:15:03.141816 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9605 13:15:03.145005 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9606 13:15:03.148429 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9607 13:15:03.154880 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9608 13:15:03.158095 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9609 13:15:03.165100 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9610 13:15:03.168648 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9611 13:15:03.171619 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9612 13:15:03.178086 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9613 13:15:03.181865 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9614 13:15:03.188391 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9615 13:15:03.191539 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9616 13:15:03.195022 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9617 13:15:03.201697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9618 13:15:03.205269 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9619 13:15:03.208185 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9620 13:15:03.215016 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9621 13:15:03.218251 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9622 13:15:03.224559 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9623 13:15:03.228408 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9624 13:15:03.231351 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9625 13:15:03.238110 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9626 13:15:03.241591 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9627 13:15:03.248244 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9628 13:15:03.251381 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9629 13:15:03.254971 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9630 13:15:03.261185 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9631 13:15:03.264840 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9632 13:15:03.268302 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9633 13:15:03.274774 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9634 13:15:03.277956 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9635 13:15:03.284432 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9636 13:15:03.288316 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9637 13:15:03.291412 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9638 13:15:03.298317 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9639 13:15:03.301540 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9640 13:15:03.308542 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9641 13:15:03.311496 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9642 13:15:03.314885 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9643 13:15:03.321370 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9644 13:15:03.324534 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9645 13:15:03.331170 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9646 13:15:03.334768 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9647 13:15:03.338004 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9648 13:15:03.344424 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9649 13:15:03.348122 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9650 13:15:03.351736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9651 13:15:03.357910 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9652 13:15:03.361502 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9653 13:15:03.367926 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9654 13:15:03.371056 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9655 13:15:03.374397 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9656 13:15:03.380933 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9657 13:15:03.384485 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9658 13:15:03.391232 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9659 13:15:03.394253 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9660 13:15:03.397751 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9661 13:15:03.404684 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9662 13:15:03.407857 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9663 13:15:03.414307 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9664 13:15:03.417408 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9665 13:15:03.420925 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9666 13:15:03.427442 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9667 13:15:03.430869 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9668 13:15:03.437318 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9669 13:15:03.441027 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9670 13:15:03.447304 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9671 13:15:03.450788 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9672 13:15:03.454058 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9673 13:15:03.460418 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9674 13:15:03.463416 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9675 13:15:03.470041 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9676 13:15:03.473485 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9677 13:15:03.476623 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9678 13:15:03.483242 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9679 13:15:03.487211 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9680 13:15:03.493414 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9681 13:15:03.496700 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9682 13:15:03.503716 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9683 13:15:03.506343 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9684 13:15:03.509869 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9685 13:15:03.516757 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9686 13:15:03.519675 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9687 13:15:03.526263 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9688 13:15:03.529884 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9689 13:15:03.533162 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9690 13:15:03.539875 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9691 13:15:03.543843 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9692 13:15:03.549712 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9693 13:15:03.552983 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9694 13:15:03.560020 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9695 13:15:03.563187 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9696 13:15:03.566812 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9697 13:15:03.573416 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9698 13:15:03.576581 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9699 13:15:03.583369 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9700 13:15:03.586783 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9701 13:15:03.590358 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9702 13:15:03.596674 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9703 13:15:03.600568 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9704 13:15:03.603474 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9705 13:15:03.606690 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9706 13:15:03.613515 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9707 13:15:03.616814 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9708 13:15:03.620165 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9709 13:15:03.626817 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9710 13:15:03.630445 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9711 13:15:03.633280 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9712 13:15:03.640478 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9713 13:15:03.643787 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9714 13:15:03.650038 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9715 13:15:03.653697 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9716 13:15:03.656822 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9717 13:15:03.663218 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9718 13:15:03.666533 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9719 13:15:03.669849 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9720 13:15:03.676845 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9721 13:15:03.679910 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9722 13:15:03.683239 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9723 13:15:03.689743 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9724 13:15:03.693193 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9725 13:15:03.699616 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9726 13:15:03.703122 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9727 13:15:03.706372 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9728 13:15:03.713231 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9729 13:15:03.716432 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9730 13:15:03.719603 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9731 13:15:03.726239 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9732 13:15:03.729559 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9733 13:15:03.733109 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9734 13:15:03.739868 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9735 13:15:03.743178 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9736 13:15:03.749575 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9737 13:15:03.752952 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9738 13:15:03.756462 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9739 13:15:03.762816 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9740 13:15:03.766124 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9741 13:15:03.769747 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9742 13:15:03.776170 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9743 13:15:03.779643 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9744 13:15:03.782763 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9745 13:15:03.786388 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9746 13:15:03.793003 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9747 13:15:03.796096 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9748 13:15:03.799369 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9749 13:15:03.803004 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9750 13:15:03.806319 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9751 13:15:03.812971 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9752 13:15:03.816743 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9753 13:15:03.819628 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9754 13:15:03.826144 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9755 13:15:03.829327 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9756 13:15:03.832599 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9757 13:15:03.839554 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9758 13:15:03.842876 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9759 13:15:03.849621 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9760 13:15:03.852707 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9761 13:15:03.856238 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9762 13:15:03.863081 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9763 13:15:03.866204 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9764 13:15:03.872763 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9765 13:15:03.876197 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9766 13:15:03.879231 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9767 13:15:03.886000 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9768 13:15:03.889236 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9769 13:15:03.896034 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9770 13:15:03.899275 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9771 13:15:03.902844 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9772 13:15:03.909963 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9773 13:15:03.912779 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9774 13:15:03.919308 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9775 13:15:03.923076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9776 13:15:03.926551 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9777 13:15:03.932754 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9778 13:15:03.936061 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9779 13:15:03.942771 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9780 13:15:03.946298 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9781 13:15:03.949295 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9782 13:15:03.955984 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9783 13:15:03.959604 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9784 13:15:03.965806 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9785 13:15:03.969365 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9786 13:15:03.975975 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9787 13:15:03.979195 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9788 13:15:03.982682 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9789 13:15:03.989165 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9790 13:15:03.992340 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9791 13:15:03.998949 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9792 13:15:04.002401 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9793 13:15:04.005656 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9794 13:15:04.012261 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9795 13:15:04.015981 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9796 13:15:04.022215 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9797 13:15:04.025482 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9798 13:15:04.028996 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9799 13:15:04.035413 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9800 13:15:04.038975 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9801 13:15:04.045255 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9802 13:15:04.048863 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9803 13:15:04.051787 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9804 13:15:04.058511 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9805 13:15:04.062195 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9806 13:15:04.068495 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9807 13:15:04.071870 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9808 13:15:04.078777 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9809 13:15:04.082060 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9810 13:15:04.085078 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9811 13:15:04.091754 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9812 13:15:04.095054 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9813 13:15:04.098330 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9814 13:15:04.105033 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9815 13:15:04.108284 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9816 13:15:04.115210 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9817 13:15:04.118629 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9818 13:15:04.125074 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9819 13:15:04.128550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9820 13:15:04.132456 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9821 13:15:04.138287 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9822 13:15:04.141873 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9823 13:15:04.148441 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9824 13:15:04.151675 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9825 13:15:04.154992 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9826 13:15:04.162011 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9827 13:15:04.165066 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9828 13:15:04.171923 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9829 13:15:04.175406 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9830 13:15:04.178480 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9831 13:15:04.185226 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9832 13:15:04.188696 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9833 13:15:04.195707 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9834 13:15:04.198535 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9835 13:15:04.205273 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9836 13:15:04.208465 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9837 13:15:04.211805 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9838 13:15:04.218625 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9839 13:15:04.221871 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9840 13:15:04.228471 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9841 13:15:04.232182 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9842 13:15:04.238674 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9843 13:15:04.242256 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9844 13:15:04.245389 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9845 13:15:04.251837 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9846 13:15:04.254964 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9847 13:15:04.261980 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9848 13:15:04.265208 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9849 13:15:04.271833 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9850 13:15:04.275029 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9851 13:15:04.278704 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9852 13:15:04.285311 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9853 13:15:04.288361 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9854 13:15:04.295201 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9855 13:15:04.298635 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9856 13:15:04.305198 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9857 13:15:04.308924 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9858 13:15:04.315259 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9859 13:15:04.318751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9860 13:15:04.322000 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9861 13:15:04.328434 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9862 13:15:04.331901 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9863 13:15:04.338658 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9864 13:15:04.341876 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9865 13:15:04.345441 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9866 13:15:04.352424 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9867 13:15:04.355119 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9868 13:15:04.361977 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9869 13:15:04.365642 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9870 13:15:04.372110 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9871 13:15:04.375329 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9872 13:15:04.378706 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9873 13:15:04.385353 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9874 13:15:04.388333 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9875 13:15:04.394995 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9876 13:15:04.398605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9877 13:15:04.401640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9878 13:15:04.408806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9879 13:15:04.411765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9880 13:15:04.418674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9881 13:15:04.422330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9882 13:15:04.428768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9883 13:15:04.432063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9884 13:15:04.438447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9885 13:15:04.441906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9886 13:15:04.448404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9887 13:15:04.452117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9888 13:15:04.458403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9889 13:15:04.462281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9890 13:15:04.468594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9891 13:15:04.471941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9892 13:15:04.478005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9893 13:15:04.481435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9894 13:15:04.488487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9895 13:15:04.491707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9896 13:15:04.495024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9897 13:15:04.501783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9898 13:15:04.505288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9899 13:15:04.511596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9900 13:15:04.515047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9901 13:15:04.522039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9902 13:15:04.525237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9903 13:15:04.531951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9904 13:15:04.535053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9905 13:15:04.541676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9906 13:15:04.545625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9907 13:15:04.551734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9908 13:15:04.554949 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9909 13:15:04.558597 INFO: [APUAPC] vio 0
9910 13:15:04.561713 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9911 13:15:04.568167 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9912 13:15:04.571619 INFO: [APUAPC] D0_APC_0: 0x400510
9913 13:15:04.574818 INFO: [APUAPC] D0_APC_1: 0x0
9914 13:15:04.575207 INFO: [APUAPC] D0_APC_2: 0x1540
9915 13:15:04.578824 INFO: [APUAPC] D0_APC_3: 0x0
9916 13:15:04.581751 INFO: [APUAPC] D1_APC_0: 0xffffffff
9917 13:15:04.584994 INFO: [APUAPC] D1_APC_1: 0xffffffff
9918 13:15:04.588202 INFO: [APUAPC] D1_APC_2: 0x3fffff
9919 13:15:04.591586 INFO: [APUAPC] D1_APC_3: 0x0
9920 13:15:04.595395 INFO: [APUAPC] D2_APC_0: 0xffffffff
9921 13:15:04.598563 INFO: [APUAPC] D2_APC_1: 0xffffffff
9922 13:15:04.601699 INFO: [APUAPC] D2_APC_2: 0x3fffff
9923 13:15:04.604921 INFO: [APUAPC] D2_APC_3: 0x0
9924 13:15:04.608711 INFO: [APUAPC] D3_APC_0: 0xffffffff
9925 13:15:04.611646 INFO: [APUAPC] D3_APC_1: 0xffffffff
9926 13:15:04.615186 INFO: [APUAPC] D3_APC_2: 0x3fffff
9927 13:15:04.618397 INFO: [APUAPC] D3_APC_3: 0x0
9928 13:15:04.621799 INFO: [APUAPC] D4_APC_0: 0xffffffff
9929 13:15:04.624779 INFO: [APUAPC] D4_APC_1: 0xffffffff
9930 13:15:04.628350 INFO: [APUAPC] D4_APC_2: 0x3fffff
9931 13:15:04.631697 INFO: [APUAPC] D4_APC_3: 0x0
9932 13:15:04.634810 INFO: [APUAPC] D5_APC_0: 0xffffffff
9933 13:15:04.638327 INFO: [APUAPC] D5_APC_1: 0xffffffff
9934 13:15:04.641622 INFO: [APUAPC] D5_APC_2: 0x3fffff
9935 13:15:04.644959 INFO: [APUAPC] D5_APC_3: 0x0
9936 13:15:04.648471 INFO: [APUAPC] D6_APC_0: 0xffffffff
9937 13:15:04.651563 INFO: [APUAPC] D6_APC_1: 0xffffffff
9938 13:15:04.654943 INFO: [APUAPC] D6_APC_2: 0x3fffff
9939 13:15:04.658799 INFO: [APUAPC] D6_APC_3: 0x0
9940 13:15:04.661916 INFO: [APUAPC] D7_APC_0: 0xffffffff
9941 13:15:04.665320 INFO: [APUAPC] D7_APC_1: 0xffffffff
9942 13:15:04.668587 INFO: [APUAPC] D7_APC_2: 0x3fffff
9943 13:15:04.671802 INFO: [APUAPC] D7_APC_3: 0x0
9944 13:15:04.675419 INFO: [APUAPC] D8_APC_0: 0xffffffff
9945 13:15:04.678447 INFO: [APUAPC] D8_APC_1: 0xffffffff
9946 13:15:04.681988 INFO: [APUAPC] D8_APC_2: 0x3fffff
9947 13:15:04.685199 INFO: [APUAPC] D8_APC_3: 0x0
9948 13:15:04.688391 INFO: [APUAPC] D9_APC_0: 0xffffffff
9949 13:15:04.691496 INFO: [APUAPC] D9_APC_1: 0xffffffff
9950 13:15:04.695045 INFO: [APUAPC] D9_APC_2: 0x3fffff
9951 13:15:04.695427 INFO: [APUAPC] D9_APC_3: 0x0
9952 13:15:04.701686 INFO: [APUAPC] D10_APC_0: 0xffffffff
9953 13:15:04.704940 INFO: [APUAPC] D10_APC_1: 0xffffffff
9954 13:15:04.708480 INFO: [APUAPC] D10_APC_2: 0x3fffff
9955 13:15:04.711477 INFO: [APUAPC] D10_APC_3: 0x0
9956 13:15:04.714906 INFO: [APUAPC] D11_APC_0: 0xffffffff
9957 13:15:04.718224 INFO: [APUAPC] D11_APC_1: 0xffffffff
9958 13:15:04.721758 INFO: [APUAPC] D11_APC_2: 0x3fffff
9959 13:15:04.724851 INFO: [APUAPC] D11_APC_3: 0x0
9960 13:15:04.728198 INFO: [APUAPC] D12_APC_0: 0xffffffff
9961 13:15:04.731574 INFO: [APUAPC] D12_APC_1: 0xffffffff
9962 13:15:04.734708 INFO: [APUAPC] D12_APC_2: 0x3fffff
9963 13:15:04.738383 INFO: [APUAPC] D12_APC_3: 0x0
9964 13:15:04.741592 INFO: [APUAPC] D13_APC_0: 0xffffffff
9965 13:15:04.744787 INFO: [APUAPC] D13_APC_1: 0xffffffff
9966 13:15:04.748225 INFO: [APUAPC] D13_APC_2: 0x3fffff
9967 13:15:04.751244 INFO: [APUAPC] D13_APC_3: 0x0
9968 13:15:04.754822 INFO: [APUAPC] D14_APC_0: 0xffffffff
9969 13:15:04.758252 INFO: [APUAPC] D14_APC_1: 0xffffffff
9970 13:15:04.761644 INFO: [APUAPC] D14_APC_2: 0x3fffff
9971 13:15:04.765019 INFO: [APUAPC] D14_APC_3: 0x0
9972 13:15:04.768151 INFO: [APUAPC] D15_APC_0: 0xffffffff
9973 13:15:04.771352 INFO: [APUAPC] D15_APC_1: 0xffffffff
9974 13:15:04.774811 INFO: [APUAPC] D15_APC_2: 0x3fffff
9975 13:15:04.777920 INFO: [APUAPC] D15_APC_3: 0x0
9976 13:15:04.778341 INFO: [APUAPC] APC_CON: 0x4
9977 13:15:04.781359 INFO: [NOCDAPC] D0_APC_0: 0x0
9978 13:15:04.784628 INFO: [NOCDAPC] D0_APC_1: 0x0
9979 13:15:04.787865 INFO: [NOCDAPC] D1_APC_0: 0x0
9980 13:15:04.791211 INFO: [NOCDAPC] D1_APC_1: 0xfff
9981 13:15:04.794739 INFO: [NOCDAPC] D2_APC_0: 0x0
9982 13:15:04.798119 INFO: [NOCDAPC] D2_APC_1: 0xfff
9983 13:15:04.801531 INFO: [NOCDAPC] D3_APC_0: 0x0
9984 13:15:04.805155 INFO: [NOCDAPC] D3_APC_1: 0xfff
9985 13:15:04.805622 INFO: [NOCDAPC] D4_APC_0: 0x0
9986 13:15:04.808108 INFO: [NOCDAPC] D4_APC_1: 0xfff
9987 13:15:04.811583 INFO: [NOCDAPC] D5_APC_0: 0x0
9988 13:15:04.814818 INFO: [NOCDAPC] D5_APC_1: 0xfff
9989 13:15:04.818354 INFO: [NOCDAPC] D6_APC_0: 0x0
9990 13:15:04.821624 INFO: [NOCDAPC] D6_APC_1: 0xfff
9991 13:15:04.824785 INFO: [NOCDAPC] D7_APC_0: 0x0
9992 13:15:04.827678 INFO: [NOCDAPC] D7_APC_1: 0xfff
9993 13:15:04.831263 INFO: [NOCDAPC] D8_APC_0: 0x0
9994 13:15:04.834775 INFO: [NOCDAPC] D8_APC_1: 0xfff
9995 13:15:04.837865 INFO: [NOCDAPC] D9_APC_0: 0x0
9996 13:15:04.838269 INFO: [NOCDAPC] D9_APC_1: 0xfff
9997 13:15:04.841579 INFO: [NOCDAPC] D10_APC_0: 0x0
9998 13:15:04.844671 INFO: [NOCDAPC] D10_APC_1: 0xfff
9999 13:15:04.848126 INFO: [NOCDAPC] D11_APC_0: 0x0
10000 13:15:04.851224 INFO: [NOCDAPC] D11_APC_1: 0xfff
10001 13:15:04.854203 INFO: [NOCDAPC] D12_APC_0: 0x0
10002 13:15:04.857903 INFO: [NOCDAPC] D12_APC_1: 0xfff
10003 13:15:04.860968 INFO: [NOCDAPC] D13_APC_0: 0x0
10004 13:15:04.864360 INFO: [NOCDAPC] D13_APC_1: 0xfff
10005 13:15:04.867729 INFO: [NOCDAPC] D14_APC_0: 0x0
10006 13:15:04.871024 INFO: [NOCDAPC] D14_APC_1: 0xfff
10007 13:15:04.874307 INFO: [NOCDAPC] D15_APC_0: 0x0
10008 13:15:04.878031 INFO: [NOCDAPC] D15_APC_1: 0xfff
10009 13:15:04.881269 INFO: [NOCDAPC] APC_CON: 0x4
10010 13:15:04.884360 INFO: [APUAPC] set_apusys_apc done
10011 13:15:04.884871 INFO: [DEVAPC] devapc_init done
10012 13:15:04.891446 INFO: GICv3 without legacy support detected.
10013 13:15:04.894591 INFO: ARM GICv3 driver initialized in EL3
10014 13:15:04.897850 INFO: Maximum SPI INTID supported: 639
10015 13:15:04.901109 INFO: BL31: Initializing runtime services
10016 13:15:04.907866 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10017 13:15:04.911340 INFO: SPM: enable CPC mode
10018 13:15:04.914732 INFO: mcdi ready for mcusys-off-idle and system suspend
10019 13:15:04.920907 INFO: BL31: Preparing for EL3 exit to normal world
10020 13:15:04.924455 INFO: Entry point address = 0x80000000
10021 13:15:04.924961 INFO: SPSR = 0x8
10022 13:15:04.931933
10023 13:15:04.932311
10024 13:15:04.932679
10025 13:15:04.935124 Starting depthcharge on Spherion...
10026 13:15:04.935508
10027 13:15:04.935823 Wipe memory regions:
10028 13:15:04.936132
10029 13:15:04.938577 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10030 13:15:04.939042 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10031 13:15:04.939411 Setting prompt string to ['asurada:']
10032 13:15:04.939730 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10033 13:15:04.940310 [0x00000040000000, 0x00000054600000)
10034 13:15:05.060913
10035 13:15:05.061483 [0x00000054660000, 0x00000080000000)
10036 13:15:05.320952
10037 13:15:05.321511 [0x000000821a7280, 0x000000ffe64000)
10038 13:15:06.065337
10039 13:15:06.065868 [0x00000100000000, 0x00000240000000)
10040 13:15:07.953656
10041 13:15:07.956506 Initializing XHCI USB controller at 0x11200000.
10042 13:15:08.995681
10043 13:15:08.998676 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10044 13:15:08.998753
10045 13:15:08.998812
10046 13:15:08.999072 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 13:15:08.999144 Sending line: 'tftpboot 192.168.201.1 14879020/tftp-deploy-9azu58h2/kernel/image.itb 14879020/tftp-deploy-9azu58h2/kernel/cmdline '
10049 13:15:09.099665 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 13:15:09.099770 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10051 13:15:09.103829 asurada: tftpboot 192.168.201.1 14879020/tftp-deploy-9azu58h2/kernel/image.ittp-deploy-9azu58h2/kernel/cmdline
10052 13:15:09.103908
10053 13:15:09.103967 Waiting for link
10054 13:15:09.262102
10055 13:15:09.262219 R8152: Initializing
10056 13:15:09.262283
10057 13:15:09.265290 Version 9 (ocp_data = 6010)
10058 13:15:09.265368
10059 13:15:09.268366 R8152: Done initializing
10060 13:15:09.268442
10061 13:15:09.268502 Adding net device
10062 13:15:11.216640
10063 13:15:11.216763 done.
10064 13:15:11.216851
10065 13:15:11.216933 MAC: 00:e0:4c:72:2d:d6
10066 13:15:11.217013
10067 13:15:11.220223 Sending DHCP discover... done.
10068 13:15:11.220300
10069 13:15:11.223347 Waiting for reply... done.
10070 13:15:11.223423
10071 13:15:11.226647 Sending DHCP request... done.
10072 13:15:11.226726
10073 13:15:11.232027 Waiting for reply... done.
10074 13:15:11.232104
10075 13:15:11.232164 My ip is 192.168.201.21
10076 13:15:11.232219
10077 13:15:11.235745 The DHCP server ip is 192.168.201.1
10078 13:15:11.235823
10079 13:15:11.242330 TFTP server IP predefined by user: 192.168.201.1
10080 13:15:11.242406
10081 13:15:11.248681 Bootfile predefined by user: 14879020/tftp-deploy-9azu58h2/kernel/image.itb
10082 13:15:11.248758
10083 13:15:11.248817 Sending tftp read request... done.
10084 13:15:11.252294
10085 13:15:11.255899 Waiting for the transfer...
10086 13:15:11.255976
10087 13:15:11.520802 00000000 ################################################################
10088 13:15:11.520915
10089 13:15:11.778498 00080000 ################################################################
10090 13:15:11.778614
10091 13:15:12.049632 00100000 ################################################################
10092 13:15:12.049748
10093 13:15:12.311381 00180000 ################################################################
10094 13:15:12.311522
10095 13:15:12.577627 00200000 ################################################################
10096 13:15:12.577747
10097 13:15:12.835476 00280000 ################################################################
10098 13:15:12.835605
10099 13:15:13.107075 00300000 ################################################################
10100 13:15:13.107189
10101 13:15:13.396739 00380000 ################################################################
10102 13:15:13.396854
10103 13:15:13.688895 00400000 ################################################################
10104 13:15:13.689019
10105 13:15:13.966133 00480000 ################################################################
10106 13:15:13.966251
10107 13:15:14.220181 00500000 ################################################################
10108 13:15:14.220310
10109 13:15:14.512482 00580000 ################################################################
10110 13:15:14.512606
10111 13:15:14.800072 00600000 ################################################################
10112 13:15:14.800202
10113 13:15:15.071126 00680000 ################################################################
10114 13:15:15.071256
10115 13:15:15.346762 00700000 ################################################################
10116 13:15:15.346889
10117 13:15:15.640230 00780000 ################################################################
10118 13:15:15.640366
10119 13:15:15.924711 00800000 ################################################################
10120 13:15:15.924827
10121 13:15:16.206615 00880000 ################################################################
10122 13:15:16.206746
10123 13:15:16.491464 00900000 ################################################################
10124 13:15:16.491573
10125 13:15:16.772352 00980000 ################################################################
10126 13:15:16.772466
10127 13:15:17.060287 00a00000 ################################################################
10128 13:15:17.060403
10129 13:15:17.349518 00a80000 ################################################################
10130 13:15:17.349660
10131 13:15:17.631271 00b00000 ################################################################
10132 13:15:17.631405
10133 13:15:17.895916 00b80000 ################################################################
10134 13:15:17.896036
10135 13:15:18.149817 00c00000 ################################################################
10136 13:15:18.149929
10137 13:15:18.431172 00c80000 ################################################################
10138 13:15:18.431296
10139 13:15:18.707078 00d00000 ################################################################
10140 13:15:18.707200
10141 13:15:18.989891 00d80000 ################################################################
10142 13:15:18.990042
10143 13:15:19.267519 00e00000 ################################################################
10144 13:15:19.267639
10145 13:15:19.557386 00e80000 ################################################################
10146 13:15:19.557511
10147 13:15:19.848570 00f00000 ################################################################
10148 13:15:19.848696
10149 13:15:20.141030 00f80000 ################################################################
10150 13:15:20.141193
10151 13:15:20.447398 01000000 ################################################################
10152 13:15:20.447513
10153 13:15:20.699877 01080000 ################################################################
10154 13:15:20.700030
10155 13:15:20.986483 01100000 ################################################################
10156 13:15:20.986601
10157 13:15:21.285175 01180000 ################################################################
10158 13:15:21.285387
10159 13:15:21.550685 01200000 ################################################################
10160 13:15:21.550809
10161 13:15:21.821342 01280000 ################################################################
10162 13:15:21.821518
10163 13:15:22.097365 01300000 ################################################################
10164 13:15:22.097488
10165 13:15:22.377472 01380000 ################################################################
10166 13:15:22.377618
10167 13:15:22.651771 01400000 ################################################################
10168 13:15:22.651896
10169 13:15:22.946910 01480000 ################################################################
10170 13:15:22.947036
10171 13:15:23.231275 01500000 ################################################################
10172 13:15:23.231424
10173 13:15:23.508634 01580000 ################################################################
10174 13:15:23.508762
10175 13:15:23.779360 01600000 ################################################################
10176 13:15:23.779512
10177 13:15:24.044375 01680000 ################################################################
10178 13:15:24.044523
10179 13:15:24.308908 01700000 ################################################################
10180 13:15:24.309042
10181 13:15:24.583352 01780000 ################################################################
10182 13:15:24.583479
10183 13:15:24.861513 01800000 ################################################################
10184 13:15:24.861644
10185 13:15:25.135668 01880000 ################################################################
10186 13:15:25.135837
10187 13:15:25.405289 01900000 ################################################################
10188 13:15:25.405420
10189 13:15:25.687534 01980000 ################################################################
10190 13:15:25.687683
10191 13:15:25.980079 01a00000 ################################################################
10192 13:15:25.980253
10193 13:15:26.272188 01a80000 ################################################################
10194 13:15:26.272306
10195 13:15:26.534575 01b00000 ################################################################
10196 13:15:26.534705
10197 13:15:26.801646 01b80000 ################################################################
10198 13:15:26.801766
10199 13:15:27.062209 01c00000 ################################################################
10200 13:15:27.062369
10201 13:15:27.330816 01c80000 ################################################################
10202 13:15:27.330960
10203 13:15:27.618391 01d00000 ################################################################
10204 13:15:27.618543
10205 13:15:27.905536 01d80000 ################################################################
10206 13:15:27.905657
10207 13:15:28.182277 01e00000 ################################################################
10208 13:15:28.182427
10209 13:15:28.449518 01e80000 ################################################################
10210 13:15:28.449650
10211 13:15:28.725229 01f00000 ################################################################
10212 13:15:28.725392
10213 13:15:28.990802 01f80000 ################################################################
10214 13:15:28.990962
10215 13:15:29.261634 02000000 ################################################################
10216 13:15:29.261747
10217 13:15:29.524388 02080000 ################################################################
10218 13:15:29.524534
10219 13:15:29.775987 02100000 ################################################################
10220 13:15:29.776103
10221 13:15:30.058948 02180000 ################################################################
10222 13:15:30.059088
10223 13:15:30.334400 02200000 ################################################################
10224 13:15:30.334523
10225 13:15:30.620869 02280000 ################################################################
10226 13:15:30.620984
10227 13:15:30.886934 02300000 ################################################################
10228 13:15:30.887077
10229 13:15:31.173742 02380000 ################################################################
10230 13:15:31.173862
10231 13:15:31.433065 02400000 ################################################################
10232 13:15:31.433212
10233 13:15:31.709426 02480000 ################################################################
10234 13:15:31.709546
10235 13:15:31.968656 02500000 ################################################################
10236 13:15:31.968802
10237 13:15:32.229335 02580000 ################################################################
10238 13:15:32.229448
10239 13:15:32.508255 02600000 ################################################################
10240 13:15:32.508409
10241 13:15:32.764038 02680000 ################################################################
10242 13:15:32.764154
10243 13:15:33.020714 02700000 ################################################################
10244 13:15:33.020856
10245 13:15:33.288116 02780000 ################################################################
10246 13:15:33.288231
10247 13:15:33.555990 02800000 ################################################################
10248 13:15:33.556107
10249 13:15:33.825328 02880000 ################################################################
10250 13:15:33.825442
10251 13:15:34.105447 02900000 ################################################################
10252 13:15:34.105589
10253 13:15:34.386172 02980000 ################################################################
10254 13:15:34.386297
10255 13:15:34.648246 02a00000 ################################################################
10256 13:15:34.648365
10257 13:15:34.912745 02a80000 ################################################################
10258 13:15:34.912885
10259 13:15:35.184229 02b00000 ################################################################
10260 13:15:35.184375
10261 13:15:35.457619 02b80000 ################################################################
10262 13:15:35.457736
10263 13:15:35.716180 02c00000 ################################################################
10264 13:15:35.716297
10265 13:15:35.978300 02c80000 ################################################################
10266 13:15:35.978416
10267 13:15:36.249944 02d00000 ################################################################
10268 13:15:36.250056
10269 13:15:36.511739 02d80000 ################################################################
10270 13:15:36.511854
10271 13:15:36.789403 02e00000 ################################################################
10272 13:15:36.789520
10273 13:15:37.074776 02e80000 ################################################################
10274 13:15:37.074891
10275 13:15:37.351775 02f00000 ################################################################
10276 13:15:37.351884
10277 13:15:37.620334 02f80000 ################################################################
10278 13:15:37.620457
10279 13:15:37.900327 03000000 ################################################################
10280 13:15:37.900450
10281 13:15:38.190005 03080000 ################################################################
10282 13:15:38.190139
10283 13:15:38.453522 03100000 ################################################################
10284 13:15:38.453679
10285 13:15:38.733687 03180000 ################################################################
10286 13:15:38.733813
10287 13:15:39.007603 03200000 ################################################################
10288 13:15:39.007730
10289 13:15:39.276967 03280000 ################################################################
10290 13:15:39.277091
10291 13:15:39.558904 03300000 ################################################################
10292 13:15:39.559049
10293 13:15:39.839164 03380000 ################################################################
10294 13:15:39.839286
10295 13:15:40.130177 03400000 ################################################################
10296 13:15:40.130334
10297 13:15:40.404831 03480000 ################################################################
10298 13:15:40.404953
10299 13:15:40.671398 03500000 ################################################################
10300 13:15:40.671560
10301 13:15:40.925003 03580000 ################################################################
10302 13:15:40.925175
10303 13:15:41.174094 03600000 ################################################################
10304 13:15:41.174247
10305 13:15:41.423234 03680000 ################################################################
10306 13:15:41.423391
10307 13:15:41.678715 03700000 ################################################################
10308 13:15:41.678879
10309 13:15:41.931772 03780000 ################################################################
10310 13:15:41.931909
10311 13:15:42.185520 03800000 ################################################################
10312 13:15:42.185642
10313 13:15:42.439779 03880000 ################################################################
10314 13:15:42.439925
10315 13:15:42.692741 03900000 ################################################################
10316 13:15:42.692867
10317 13:15:42.942726 03980000 ################################################################
10318 13:15:42.942896
10319 13:15:43.193023 03a00000 ################################################################
10320 13:15:43.193211
10321 13:15:43.445217 03a80000 ################################################################
10322 13:15:43.445399
10323 13:15:43.696362 03b00000 ################################################################
10324 13:15:43.696488
10325 13:15:43.944657 03b80000 ################################################################
10326 13:15:43.944775
10327 13:15:44.193744 03c00000 ################################################################
10328 13:15:44.193932
10329 13:15:44.448128 03c80000 ################################################################
10330 13:15:44.448253
10331 13:15:44.703317 03d00000 ################################################################
10332 13:15:44.703431
10333 13:15:44.954481 03d80000 ################################################################
10334 13:15:44.954605
10335 13:15:45.089470 03e00000 ################################### done.
10336 13:15:45.089587
10337 13:15:45.092721 The bootfile was 65291398 bytes long.
10338 13:15:45.092818
10339 13:15:45.095867 Sending tftp read request... done.
10340 13:15:45.095947
10341 13:15:45.099253 Waiting for the transfer...
10342 13:15:45.099361
10343 13:15:45.099453 00000000 # done.
10344 13:15:45.099542
10345 13:15:45.109110 Command line loaded dynamically from TFTP file: 14879020/tftp-deploy-9azu58h2/kernel/cmdline
10346 13:15:45.109227
10347 13:15:45.122404 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10348 13:15:45.122537
10349 13:15:45.122630 Loading FIT.
10350 13:15:45.122714
10351 13:15:45.125858 Image ramdisk-1 has 52127641 bytes.
10352 13:15:45.125939
10353 13:15:45.128896 Image fdt-1 has 47258 bytes.
10354 13:15:45.128976
10355 13:15:45.132546 Image kernel-1 has 13114469 bytes.
10356 13:15:45.132649
10357 13:15:45.138816 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10358 13:15:45.138923
10359 13:15:45.158823 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10360 13:15:45.158930
10361 13:15:45.161971 Choosing best match conf-1 for compat google,spherion-rev2.
10362 13:15:45.167256
10363 13:15:45.171699 Connected to device vid:did:rid of 1ae0:0028:00
10364 13:15:45.179817
10365 13:15:45.183401 tpm_get_response: command 0x17b, return code 0x0
10366 13:15:45.183522
10367 13:15:45.186677 ec_init: CrosEC protocol v3 supported (256, 248)
10368 13:15:45.190688
10369 13:15:45.193832 tpm_cleanup: add release locality here.
10370 13:15:45.193933
10371 13:15:45.194024 Shutting down all USB controllers.
10372 13:15:45.197357
10373 13:15:45.197432 Removing current net device
10374 13:15:45.197512
10375 13:15:45.204194 Exiting depthcharge with code 4 at timestamp: 69594358
10376 13:15:45.204310
10377 13:15:45.207388 LZMA decompressing kernel-1 to 0x821a6718
10378 13:15:45.207483
10379 13:15:45.210729 LZMA decompressing kernel-1 to 0x40000000
10380 13:15:46.826399
10381 13:15:46.826517 jumping to kernel
10382 13:15:46.827073 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10383 13:15:46.827170 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10384 13:15:46.827241 Setting prompt string to ['Linux version [0-9]']
10385 13:15:46.827321 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10386 13:15:46.827388 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10387 13:15:46.907026
10388 13:15:46.910202 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10389 13:15:46.913721 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10390 13:15:46.913863 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10391 13:15:46.913978 Setting prompt string to []
10392 13:15:46.914088 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10393 13:15:46.914188 Using line separator: #'\n'#
10394 13:15:46.914276 No login prompt set.
10395 13:15:46.914371 Parsing kernel messages
10396 13:15:46.914455 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10397 13:15:46.914626 [login-action] Waiting for messages, (timeout 00:03:38)
10398 13:15:46.914714 Waiting using forced prompt support (timeout 00:01:49)
10399 13:15:46.933283 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j272990-arm64-gcc-12-defconfig-arm64-chromebook-fgzcq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024
10400 13:15:46.936650 [ 0.000000] random: crng init done
10401 13:15:46.939977 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10402 13:15:46.943348 [ 0.000000] efi: UEFI not found.
10403 13:15:46.953215 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10404 13:15:46.959938 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10405 13:15:46.969525 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10406 13:15:46.979701 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10407 13:15:46.986071 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10408 13:15:46.989211 [ 0.000000] printk: bootconsole [mtk8250] enabled
10409 13:15:46.998065 [ 0.000000] NUMA: No NUMA configuration found
10410 13:15:47.004469 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10411 13:15:47.011430 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10412 13:15:47.011569 [ 0.000000] Zone ranges:
10413 13:15:47.017912 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10414 13:15:47.021350 [ 0.000000] DMA32 empty
10415 13:15:47.027986 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10416 13:15:47.031147 [ 0.000000] Movable zone start for each node
10417 13:15:47.034760 [ 0.000000] Early memory node ranges
10418 13:15:47.040898 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10419 13:15:47.047764 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10420 13:15:47.054310 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10421 13:15:47.060734 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10422 13:15:47.067393 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10423 13:15:47.073762 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10424 13:15:47.131492 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10425 13:15:47.137767 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10426 13:15:47.144353 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10427 13:15:47.147956 [ 0.000000] psci: probing for conduit method from DT.
10428 13:15:47.154459 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10429 13:15:47.157519 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10430 13:15:47.164551 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10431 13:15:47.167787 [ 0.000000] psci: SMC Calling Convention v1.2
10432 13:15:47.174465 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10433 13:15:47.177484 [ 0.000000] Detected VIPT I-cache on CPU0
10434 13:15:47.184264 [ 0.000000] CPU features: detected: GIC system register CPU interface
10435 13:15:47.190966 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10436 13:15:47.197278 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10437 13:15:47.203950 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10438 13:15:47.213789 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10439 13:15:47.220425 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10440 13:15:47.223787 [ 0.000000] alternatives: applying boot alternatives
10441 13:15:47.230268 [ 0.000000] Fallback order for Node 0: 0
10442 13:15:47.236998 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10443 13:15:47.240254 [ 0.000000] Policy zone: Normal
10444 13:15:47.253759 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10445 13:15:47.263814 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10446 13:15:47.276063 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10447 13:15:47.286033 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10448 13:15:47.292626 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10449 13:15:47.295769 <6>[ 0.000000] software IO TLB: area num 8.
10450 13:15:47.352950 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10451 13:15:47.502691 <6>[ 0.000000] Memory: 7913156K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 439612K reserved, 32768K cma-reserved)
10452 13:15:47.509366 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10453 13:15:47.515812 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10454 13:15:47.518840 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10455 13:15:47.525999 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10456 13:15:47.532272 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10457 13:15:47.535583 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10458 13:15:47.545624 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10459 13:15:47.552139 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10460 13:15:47.558822 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10461 13:15:47.565192 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10462 13:15:47.568476 <6>[ 0.000000] GICv3: 608 SPIs implemented
10463 13:15:47.571619 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10464 13:15:47.578512 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10465 13:15:47.582080 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10466 13:15:47.588380 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10467 13:15:47.601953 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10468 13:15:47.614924 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10469 13:15:47.621361 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10470 13:15:47.629049 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10471 13:15:47.642256 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10472 13:15:47.649151 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10473 13:15:47.655626 <6>[ 0.009177] Console: colour dummy device 80x25
10474 13:15:47.665412 <6>[ 0.013926] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10475 13:15:47.672303 <6>[ 0.024367] pid_max: default: 32768 minimum: 301
10476 13:15:47.675192 <6>[ 0.029239] LSM: Security Framework initializing
10477 13:15:47.681897 <6>[ 0.034178] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10478 13:15:47.691723 <6>[ 0.042025] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10479 13:15:47.701964 <6>[ 0.051499] cblist_init_generic: Setting adjustable number of callback queues.
10480 13:15:47.705232 <6>[ 0.058940] cblist_init_generic: Setting shift to 3 and lim to 1.
10481 13:15:47.715471 <6>[ 0.065279] cblist_init_generic: Setting adjustable number of callback queues.
10482 13:15:47.721839 <6>[ 0.072706] cblist_init_generic: Setting shift to 3 and lim to 1.
10483 13:15:47.725326 <6>[ 0.079148] rcu: Hierarchical SRCU implementation.
10484 13:15:47.731927 <6>[ 0.084164] rcu: Max phase no-delay instances is 1000.
10485 13:15:47.738579 <6>[ 0.091180] EFI services will not be available.
10486 13:15:47.741715 <6>[ 0.096138] smp: Bringing up secondary CPUs ...
10487 13:15:47.750044 <6>[ 0.101193] Detected VIPT I-cache on CPU1
10488 13:15:47.756497 <6>[ 0.101264] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10489 13:15:47.763393 <6>[ 0.101295] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10490 13:15:47.766424 <6>[ 0.101638] Detected VIPT I-cache on CPU2
10491 13:15:47.773549 <6>[ 0.101691] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10492 13:15:47.783047 <6>[ 0.101707] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10493 13:15:47.786338 <6>[ 0.101970] Detected VIPT I-cache on CPU3
10494 13:15:47.793105 <6>[ 0.102018] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10495 13:15:47.799893 <6>[ 0.102032] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10496 13:15:47.802831 <6>[ 0.102339] CPU features: detected: Spectre-v4
10497 13:15:47.809672 <6>[ 0.102345] CPU features: detected: Spectre-BHB
10498 13:15:47.812864 <6>[ 0.102351] Detected PIPT I-cache on CPU4
10499 13:15:47.819354 <6>[ 0.102410] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10500 13:15:47.826351 <6>[ 0.102427] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10501 13:15:47.832422 <6>[ 0.102723] Detected PIPT I-cache on CPU5
10502 13:15:47.839557 <6>[ 0.102788] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10503 13:15:47.846153 <6>[ 0.102804] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10504 13:15:47.849335 <6>[ 0.103088] Detected PIPT I-cache on CPU6
10505 13:15:47.855693 <6>[ 0.103154] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10506 13:15:47.862099 <6>[ 0.103170] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10507 13:15:47.869031 <6>[ 0.103471] Detected PIPT I-cache on CPU7
10508 13:15:47.875334 <6>[ 0.103537] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10509 13:15:47.881950 <6>[ 0.103552] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10510 13:15:47.885659 <6>[ 0.103600] smp: Brought up 1 node, 8 CPUs
10511 13:15:47.891578 <6>[ 0.244977] SMP: Total of 8 processors activated.
10512 13:15:47.895219 <6>[ 0.249929] CPU features: detected: 32-bit EL0 Support
10513 13:15:47.904951 <6>[ 0.255291] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10514 13:15:47.911617 <6>[ 0.264091] CPU features: detected: Common not Private translations
10515 13:15:47.918105 <6>[ 0.270568] CPU features: detected: CRC32 instructions
10516 13:15:47.924888 <6>[ 0.275919] CPU features: detected: RCpc load-acquire (LDAPR)
10517 13:15:47.927864 <6>[ 0.281879] CPU features: detected: LSE atomic instructions
10518 13:15:47.934883 <6>[ 0.287661] CPU features: detected: Privileged Access Never
10519 13:15:47.941540 <6>[ 0.293440] CPU features: detected: RAS Extension Support
10520 13:15:47.948178 <6>[ 0.299048] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10521 13:15:47.951346 <6>[ 0.306270] CPU: All CPU(s) started at EL2
10522 13:15:47.957846 <6>[ 0.310587] alternatives: applying system-wide alternatives
10523 13:15:47.967615 <6>[ 0.321467] devtmpfs: initialized
10524 13:15:47.983095 <6>[ 0.330241] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10525 13:15:47.989790 <6>[ 0.340199] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10526 13:15:47.996700 <6>[ 0.348441] pinctrl core: initialized pinctrl subsystem
10527 13:15:47.999707 <6>[ 0.355109] DMI not present or invalid.
10528 13:15:48.006215 <6>[ 0.359516] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10529 13:15:48.016391 <6>[ 0.366303] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10530 13:15:48.023267 <6>[ 0.373886] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10531 13:15:48.032807 <6>[ 0.382120] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10532 13:15:48.036286 <6>[ 0.390360] audit: initializing netlink subsys (disabled)
10533 13:15:48.046002 <5>[ 0.396049] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10534 13:15:48.052866 <6>[ 0.396753] thermal_sys: Registered thermal governor 'step_wise'
10535 13:15:48.059266 <6>[ 0.404014] thermal_sys: Registered thermal governor 'power_allocator'
10536 13:15:48.062913 <6>[ 0.410268] cpuidle: using governor menu
10537 13:15:48.069406 <6>[ 0.421228] NET: Registered PF_QIPCRTR protocol family
10538 13:15:48.076131 <6>[ 0.426715] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10539 13:15:48.082763 <6>[ 0.433815] ASID allocator initialised with 32768 entries
10540 13:15:48.085746 <6>[ 0.440385] Serial: AMBA PL011 UART driver
10541 13:15:48.096035 <4>[ 0.449715] Trying to register duplicate clock ID: 134
10542 13:15:48.154079 <6>[ 0.510853] KASLR enabled
10543 13:15:48.168342 <6>[ 0.518479] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10544 13:15:48.174933 <6>[ 0.525490] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10545 13:15:48.181340 <6>[ 0.531977] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10546 13:15:48.187952 <6>[ 0.538979] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10547 13:15:48.194525 <6>[ 0.545468] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10548 13:15:48.201281 <6>[ 0.552470] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10549 13:15:48.207836 <6>[ 0.558958] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10550 13:15:48.214415 <6>[ 0.565962] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10551 13:15:48.217377 <6>[ 0.573476] ACPI: Interpreter disabled.
10552 13:15:48.226336 <6>[ 0.579914] iommu: Default domain type: Translated
10553 13:15:48.232860 <6>[ 0.585027] iommu: DMA domain TLB invalidation policy: strict mode
10554 13:15:48.236164 <5>[ 0.591677] SCSI subsystem initialized
10555 13:15:48.242638 <6>[ 0.595838] usbcore: registered new interface driver usbfs
10556 13:15:48.249204 <6>[ 0.601572] usbcore: registered new interface driver hub
10557 13:15:48.252836 <6>[ 0.607124] usbcore: registered new device driver usb
10558 13:15:48.259425 <6>[ 0.613228] pps_core: LinuxPPS API ver. 1 registered
10559 13:15:48.269514 <6>[ 0.618421] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10560 13:15:48.272638 <6>[ 0.627764] PTP clock support registered
10561 13:15:48.275739 <6>[ 0.632010] EDAC MC: Ver: 3.0.0
10562 13:15:48.283478 <6>[ 0.637168] FPGA manager framework
10563 13:15:48.289932 <6>[ 0.640853] Advanced Linux Sound Architecture Driver Initialized.
10564 13:15:48.293245 <6>[ 0.647646] vgaarb: loaded
10565 13:15:48.300358 <6>[ 0.650740] clocksource: Switched to clocksource arch_sys_counter
10566 13:15:48.303438 <5>[ 0.657175] VFS: Disk quotas dquot_6.6.0
10567 13:15:48.309923 <6>[ 0.661358] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10568 13:15:48.313142 <6>[ 0.668546] pnp: PnP ACPI: disabled
10569 13:15:48.321817 <6>[ 0.675232] NET: Registered PF_INET protocol family
10570 13:15:48.331285 <6>[ 0.680826] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10571 13:15:48.342816 <6>[ 0.693160] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10572 13:15:48.352912 <6>[ 0.701976] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10573 13:15:48.359622 <6>[ 0.709950] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10574 13:15:48.365827 <6>[ 0.718654] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10575 13:15:48.378253 <6>[ 0.728410] TCP: Hash tables configured (established 65536 bind 65536)
10576 13:15:48.384799 <6>[ 0.735276] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10577 13:15:48.391398 <6>[ 0.742476] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10578 13:15:48.398046 <6>[ 0.750176] NET: Registered PF_UNIX/PF_LOCAL protocol family
10579 13:15:48.404631 <6>[ 0.756333] RPC: Registered named UNIX socket transport module.
10580 13:15:48.408042 <6>[ 0.762488] RPC: Registered udp transport module.
10581 13:15:48.414604 <6>[ 0.767421] RPC: Registered tcp transport module.
10582 13:15:48.420886 <6>[ 0.772352] RPC: Registered tcp NFSv4.1 backchannel transport module.
10583 13:15:48.424543 <6>[ 0.779020] PCI: CLS 0 bytes, default 64
10584 13:15:48.427614 <6>[ 0.783358] Unpacking initramfs...
10585 13:15:48.437802 <6>[ 0.787148] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10586 13:15:48.444096 <6>[ 0.795788] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10587 13:15:48.450945 <6>[ 0.804582] kvm [1]: IPA Size Limit: 40 bits
10588 13:15:48.454558 <6>[ 0.809109] kvm [1]: GICv3: no GICV resource entry
10589 13:15:48.461061 <6>[ 0.814128] kvm [1]: disabling GICv2 emulation
10590 13:15:48.467428 <6>[ 0.818815] kvm [1]: GIC system register CPU interface enabled
10591 13:15:48.471032 <6>[ 0.824975] kvm [1]: vgic interrupt IRQ18
10592 13:15:48.477375 <6>[ 0.831037] kvm [1]: VHE mode initialized successfully
10593 13:15:48.484108 <5>[ 0.837378] Initialise system trusted keyrings
10594 13:15:48.490999 <6>[ 0.842176] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10595 13:15:48.498292 <6>[ 0.852036] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10596 13:15:48.505095 <5>[ 0.858407] NFS: Registering the id_resolver key type
10597 13:15:48.508597 <5>[ 0.863706] Key type id_resolver registered
10598 13:15:48.515164 <5>[ 0.868119] Key type id_legacy registered
10599 13:15:48.521392 <6>[ 0.872414] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10600 13:15:48.528544 <6>[ 0.879335] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10601 13:15:48.534725 <6>[ 0.887063] 9p: Installing v9fs 9p2000 file system support
10602 13:15:48.571431 <5>[ 0.925338] Key type asymmetric registered
10603 13:15:48.574925 <5>[ 0.929670] Asymmetric key parser 'x509' registered
10604 13:15:48.584745 <6>[ 0.934817] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10605 13:15:48.587881 <6>[ 0.942433] io scheduler mq-deadline registered
10606 13:15:48.591433 <6>[ 0.947195] io scheduler kyber registered
10607 13:15:48.610538 <6>[ 0.964330] EINJ: ACPI disabled.
10608 13:15:48.643417 <4>[ 0.990280] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 13:15:48.652957 <4>[ 1.001063] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 13:15:48.668388 <6>[ 1.022120] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10611 13:15:48.676336 <6>[ 1.030050] printk: console [ttyS0] disabled
10612 13:15:48.704559 <6>[ 1.054678] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10613 13:15:48.710964 <6>[ 1.064151] printk: console [ttyS0] enabled
10614 13:15:48.714134 <6>[ 1.064151] printk: console [ttyS0] enabled
10615 13:15:48.720745 <6>[ 1.073050] printk: bootconsole [mtk8250] disabled
10616 13:15:48.724193 <6>[ 1.073050] printk: bootconsole [mtk8250] disabled
10617 13:15:48.730981 <6>[ 1.084259] SuperH (H)SCI(F) driver initialized
10618 13:15:48.734218 <6>[ 1.089541] msm_serial: driver initialized
10619 13:15:48.748038 <6>[ 1.098583] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10620 13:15:48.758345 <6>[ 1.107131] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10621 13:15:48.764733 <6>[ 1.115674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10622 13:15:48.774748 <6>[ 1.124303] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10623 13:15:48.784562 <6>[ 1.133016] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10624 13:15:48.791396 <6>[ 1.141733] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10625 13:15:48.801165 <6>[ 1.150277] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10626 13:15:48.807935 <6>[ 1.159083] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10627 13:15:48.817831 <6>[ 1.167629] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10628 13:15:48.829532 <6>[ 1.183242] loop: module loaded
10629 13:15:48.835887 <6>[ 1.189202] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10630 13:15:48.858560 <4>[ 1.212469] mtk-pmic-keys: Failed to locate of_node [id: -1]
10631 13:15:48.865808 <6>[ 1.219328] megasas: 07.719.03.00-rc1
10632 13:15:48.875346 <6>[ 1.228882] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10633 13:15:48.884625 <6>[ 1.238137] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10634 13:15:48.900811 <6>[ 1.254149] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10635 13:15:48.956600 <6>[ 1.303649] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10636 13:15:50.680326 <6>[ 3.034304] Freeing initrd memory: 50900K
10637 13:15:50.692119 <6>[ 3.046061] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10638 13:15:50.703426 <6>[ 3.057084] tun: Universal TUN/TAP device driver, 1.6
10639 13:15:50.706438 <6>[ 3.063175] thunder_xcv, ver 1.0
10640 13:15:50.709947 <6>[ 3.066671] thunder_bgx, ver 1.0
10641 13:15:50.713194 <6>[ 3.070171] nicpf, ver 1.0
10642 13:15:50.723670 <6>[ 3.074216] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10643 13:15:50.726819 <6>[ 3.081693] hns3: Copyright (c) 2017 Huawei Corporation.
10644 13:15:50.733437 <6>[ 3.087281] hclge is initializing
10645 13:15:50.737075 <6>[ 3.090864] e1000: Intel(R) PRO/1000 Network Driver
10646 13:15:50.743302 <6>[ 3.095993] e1000: Copyright (c) 1999-2006 Intel Corporation.
10647 13:15:50.746824 <6>[ 3.102009] e1000e: Intel(R) PRO/1000 Network Driver
10648 13:15:50.753418 <6>[ 3.107225] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10649 13:15:50.759702 <6>[ 3.113411] igb: Intel(R) Gigabit Ethernet Network Driver
10650 13:15:50.766571 <6>[ 3.119061] igb: Copyright (c) 2007-2014 Intel Corporation.
10651 13:15:50.773217 <6>[ 3.124897] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10652 13:15:50.779594 <6>[ 3.131414] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10653 13:15:50.782991 <6>[ 3.137879] sky2: driver version 1.30
10654 13:15:50.789889 <6>[ 3.142817] usbcore: registered new device driver r8152-cfgselector
10655 13:15:50.796453 <6>[ 3.149353] usbcore: registered new interface driver r8152
10656 13:15:50.802623 <6>[ 3.155173] VFIO - User Level meta-driver version: 0.3
10657 13:15:50.809658 <6>[ 3.163428] usbcore: registered new interface driver usb-storage
10658 13:15:50.815878 <6>[ 3.169877] usbcore: registered new device driver onboard-usb-hub
10659 13:15:50.825317 <6>[ 3.179036] mt6397-rtc mt6359-rtc: registered as rtc0
10660 13:15:50.834893 <6>[ 3.184503] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-18T13:15:40 UTC (1721308540)
10661 13:15:50.838485 <6>[ 3.194072] i2c_dev: i2c /dev entries driver
10662 13:15:50.852562 <4>[ 3.206202] cpu cpu0: supply cpu not found, using dummy regulator
10663 13:15:50.859156 <4>[ 3.212626] cpu cpu1: supply cpu not found, using dummy regulator
10664 13:15:50.865473 <4>[ 3.219033] cpu cpu2: supply cpu not found, using dummy regulator
10665 13:15:50.872086 <4>[ 3.225430] cpu cpu3: supply cpu not found, using dummy regulator
10666 13:15:50.878796 <4>[ 3.231831] cpu cpu4: supply cpu not found, using dummy regulator
10667 13:15:50.885460 <4>[ 3.238226] cpu cpu5: supply cpu not found, using dummy regulator
10668 13:15:50.892064 <4>[ 3.244620] cpu cpu6: supply cpu not found, using dummy regulator
10669 13:15:50.898813 <4>[ 3.251020] cpu cpu7: supply cpu not found, using dummy regulator
10670 13:15:50.918016 <6>[ 3.271661] cpu cpu0: EM: created perf domain
10671 13:15:50.921200 <6>[ 3.276570] cpu cpu4: EM: created perf domain
10672 13:15:50.928130 <6>[ 3.281945] sdhci: Secure Digital Host Controller Interface driver
10673 13:15:50.934911 <6>[ 3.288377] sdhci: Copyright(c) Pierre Ossman
10674 13:15:50.941440 <6>[ 3.293331] Synopsys Designware Multimedia Card Interface Driver
10675 13:15:50.947661 <6>[ 3.299966] sdhci-pltfm: SDHCI platform and OF driver helper
10676 13:15:50.951373 <6>[ 3.300090] mmc0: CQHCI version 5.10
10677 13:15:50.957638 <6>[ 3.309965] ledtrig-cpu: registered to indicate activity on CPUs
10678 13:15:50.964344 <6>[ 3.316867] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10679 13:15:50.971189 <6>[ 3.323926] usbcore: registered new interface driver usbhid
10680 13:15:50.974334 <6>[ 3.329748] usbhid: USB HID core driver
10681 13:15:50.980949 <6>[ 3.333948] spi_master spi0: will run message pump with realtime priority
10682 13:15:51.027871 <6>[ 3.375123] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10683 13:15:51.046562 <6>[ 3.390692] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10684 13:15:51.050025 <6>[ 3.400169] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10685 13:15:51.058707 <6>[ 3.412474] cros-ec-spi spi0.0: Chrome EC device registered
10686 13:15:51.065447 <6>[ 3.418463] mmc0: Command Queue Engine enabled
10687 13:15:51.071832 <6>[ 3.423203] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10688 13:15:51.075421 <6>[ 3.431057] mmcblk0: mmc0:0001 DA4128 116 GiB
10689 13:15:51.088064 <6>[ 3.441948] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10690 13:15:51.095385 <6>[ 3.449412] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10691 13:15:51.105341 <6>[ 3.454140] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10692 13:15:51.108931 <6>[ 3.455383] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10693 13:15:51.115157 <6>[ 3.465273] NET: Registered PF_PACKET protocol family
10694 13:15:51.121975 <6>[ 3.470051] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10695 13:15:51.125096 <6>[ 3.474576] 9pnet: Installing 9P2000 support
10696 13:15:51.131730 <5>[ 3.485586] Key type dns_resolver registered
10697 13:15:51.135298 <6>[ 3.490701] registered taskstats version 1
10698 13:15:51.141817 <5>[ 3.495116] Loading compiled-in X.509 certificates
10699 13:15:51.170964 <4>[ 3.518427] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10700 13:15:51.180830 <4>[ 3.529173] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10701 13:15:51.195815 <6>[ 3.549625] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10702 13:15:51.203117 <6>[ 3.556835] xhci-mtk 11200000.usb: xHCI Host Controller
10703 13:15:51.209337 <6>[ 3.562337] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10704 13:15:51.219700 <6>[ 3.570190] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10705 13:15:51.226624 <6>[ 3.579628] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10706 13:15:51.232936 <6>[ 3.585716] xhci-mtk 11200000.usb: xHCI Host Controller
10707 13:15:51.239375 <6>[ 3.591211] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10708 13:15:51.246342 <6>[ 3.599000] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10709 13:15:51.252837 <6>[ 3.606848] hub 1-0:1.0: USB hub found
10710 13:15:51.256040 <6>[ 3.610874] hub 1-0:1.0: 1 port detected
10711 13:15:51.266084 <6>[ 3.615203] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10712 13:15:51.269140 <6>[ 3.623986] hub 2-0:1.0: USB hub found
10713 13:15:51.272568 <6>[ 3.628012] hub 2-0:1.0: 1 port detected
10714 13:15:51.280817 <6>[ 3.634621] mtk-msdc 11f70000.mmc: Got CD GPIO
10715 13:15:51.294838 <6>[ 3.645415] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10716 13:15:51.304791 <6>[ 3.653849] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10717 13:15:51.311266 <6>[ 3.662193] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10718 13:15:51.321680 <6>[ 3.670545] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10719 13:15:51.328018 <6>[ 3.678885] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10720 13:15:51.337927 <6>[ 3.687224] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10721 13:15:51.344661 <6>[ 3.695563] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10722 13:15:51.354366 <6>[ 3.703902] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10723 13:15:51.361231 <6>[ 3.712241] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10724 13:15:51.371352 <6>[ 3.720580] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10725 13:15:51.377816 <6>[ 3.728917] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10726 13:15:51.387573 <6>[ 3.737264] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10727 13:15:51.394361 <6>[ 3.745603] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10728 13:15:51.404290 <6>[ 3.753942] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10729 13:15:51.410458 <6>[ 3.762281] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10730 13:15:51.417270 <6>[ 3.770990] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10731 13:15:51.423864 <6>[ 3.778145] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10732 13:15:51.430853 <6>[ 3.784896] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10733 13:15:51.441237 <6>[ 3.791657] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10734 13:15:51.447359 <6>[ 3.798592] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10735 13:15:51.453980 <6>[ 3.805447] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10736 13:15:51.464317 <6>[ 3.814581] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10737 13:15:51.474217 <6>[ 3.823702] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10738 13:15:51.483829 <6>[ 3.832996] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10739 13:15:51.493941 <6>[ 3.842465] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10740 13:15:51.500341 <6>[ 3.851934] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10741 13:15:51.510654 <6>[ 3.861056] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10742 13:15:51.520527 <6>[ 3.870524] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10743 13:15:51.530303 <6>[ 3.879644] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10744 13:15:51.540249 <6>[ 3.888962] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10745 13:15:51.550155 <6>[ 3.899124] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10746 13:15:51.560284 <6>[ 3.911002] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10747 13:15:51.676180 <6>[ 4.027047] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10748 13:15:51.830366 <6>[ 4.184267] hub 1-1:1.0: USB hub found
10749 13:15:51.833815 <6>[ 4.188732] hub 1-1:1.0: 4 ports detected
10750 13:15:51.844625 <6>[ 4.198366] hub 1-1:1.0: USB hub found
10751 13:15:51.847721 <6>[ 4.202639] hub 1-1:1.0: 4 ports detected
10752 13:15:51.956889 <6>[ 4.307449] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10753 13:15:51.983706 <6>[ 4.337926] hub 2-1:1.0: USB hub found
10754 13:15:51.986986 <6>[ 4.342478] hub 2-1:1.0: 3 ports detected
10755 13:15:52.000010 <6>[ 4.353878] hub 2-1:1.0: USB hub found
10756 13:15:52.003424 <6>[ 4.358257] hub 2-1:1.0: 3 ports detected
10757 13:15:52.168042 <6>[ 4.519059] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10758 13:15:52.300939 <6>[ 4.654889] hub 1-1.4:1.0: USB hub found
10759 13:15:52.304108 <6>[ 4.659557] hub 1-1.4:1.0: 2 ports detected
10760 13:15:52.319390 <6>[ 4.673231] hub 1-1.4:1.0: USB hub found
10761 13:15:52.322516 <6>[ 4.677823] hub 1-1.4:1.0: 2 ports detected
10762 13:15:52.380653 <6>[ 4.731278] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10763 13:15:52.488833 <6>[ 4.839692] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10764 13:15:52.543928 <6>[ 4.894915] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10765 13:15:52.582748 <6>[ 4.936660] r8152 2-1.3:1.0 eth0: v1.12.13
10766 13:15:52.620056 <6>[ 4.970998] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10767 13:15:52.816196 <6>[ 5.167059] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10768 13:15:54.265301 <6>[ 6.619449] r8152 2-1.3:1.0 eth0: carrier on
10769 13:15:56.560317 <5>[ 6.650873] Sending DHCP requests .., OK
10770 13:15:56.567042 <6>[ 8.919226] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10771 13:15:56.570215 <6>[ 8.927530] IP-Config: Complete:
10772 13:15:56.583608 <6>[ 8.931024] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10773 13:15:56.590489 <6>[ 8.941732] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10774 13:15:56.596880 <6>[ 8.950348] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10775 13:15:56.603561 <6>[ 8.950357] nameserver0=192.168.201.1
10776 13:15:56.606772 <6>[ 8.962532] clk: Disabling unused clocks
10777 13:15:56.610340 <6>[ 8.968072] ALSA device list:
10778 13:15:56.616788 <6>[ 8.971337] No soundcards found.
10779 13:15:56.624529 <6>[ 8.979155] Freeing unused kernel memory: 8512K
10780 13:15:56.628115 <6>[ 8.984146] Run /init as init process
10781 13:15:56.660989 <6>[ 9.015486] NET: Registered PF_INET6 protocol family
10782 13:15:56.667946 <6>[ 9.022239] Segment Routing with IPv6
10783 13:15:56.671035 <6>[ 9.026191] In-situ OAM (IOAM) with IPv6
10784 13:15:56.714422 <30>[ 9.042706] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10785 13:15:56.721162 <30>[ 9.075759] systemd[1]: Detected architecture arm64.
10786 13:15:56.721278
10787 13:15:56.727935 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10788 13:15:56.728038
10789 13:15:56.744406 <30>[ 9.099141] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10790 13:15:56.888204 <30>[ 9.239448] systemd[1]: Queued start job for default target graphical.target.
10791 13:15:56.929077 <30>[ 9.280543] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10792 13:15:56.936083 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10793 13:15:56.956309 <30>[ 9.307686] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10794 13:15:56.966103 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10795 13:15:56.984886 <30>[ 9.336070] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10796 13:15:56.994561 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10797 13:15:57.012532 <30>[ 9.363647] systemd[1]: Created slice user.slice - User and Session Slice.
10798 13:15:57.019121 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10799 13:15:57.043612 <30>[ 9.391334] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10800 13:15:57.050203 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10801 13:15:57.071329 <30>[ 9.419248] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10802 13:15:57.077983 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10803 13:15:57.106356 <30>[ 9.447590] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10804 13:15:57.115930 <30>[ 9.467482] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10805 13:15:57.122484 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10806 13:15:57.140032 <30>[ 9.491452] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10807 13:15:57.149878 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10808 13:15:57.168190 <30>[ 9.519565] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10809 13:15:57.178387 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10810 13:15:57.192838 <30>[ 9.547605] systemd[1]: Reached target paths.target - Path Units.
10811 13:15:57.202910 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10812 13:15:57.220302 <30>[ 9.571557] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10813 13:15:57.226978 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10814 13:15:57.240641 <30>[ 9.595016] systemd[1]: Reached target slices.target - Slice Units.
10815 13:15:57.250514 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10816 13:15:57.264994 <30>[ 9.619534] systemd[1]: Reached target swap.target - Swaps.
10817 13:15:57.271442 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10818 13:15:57.292272 <30>[ 9.643553] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10819 13:15:57.302383 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10820 13:15:57.320537 <30>[ 9.671533] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10821 13:15:57.330137 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10822 13:15:57.349847 <30>[ 9.701318] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10823 13:15:57.359923 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10824 13:15:57.376836 <30>[ 9.727725] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10825 13:15:57.386705 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10826 13:15:57.404643 <30>[ 9.755746] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10827 13:15:57.411043 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10828 13:15:57.432288 <30>[ 9.783828] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10829 13:15:57.442722 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10830 13:15:57.460889 <30>[ 9.812466] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10831 13:15:57.470843 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10832 13:15:57.488789 <30>[ 9.840168] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10833 13:15:57.498542 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10834 13:15:57.548023 <30>[ 9.899269] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10835 13:15:57.554755 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10836 13:15:57.573380 <30>[ 9.924825] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10837 13:15:57.580150 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10838 13:15:57.602453 <30>[ 9.953762] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10839 13:15:57.608888 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10840 13:15:57.634797 <30>[ 9.979197] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10841 13:15:57.647219 <30>[ 9.998667] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10842 13:15:57.657248 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10843 13:15:57.680973 <30>[ 10.032332] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10844 13:15:57.687711 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10845 13:15:57.712764 <30>[ 10.063882] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10846 13:15:57.725723 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 10.077905] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10847 13:15:57.728756 Module dm_mod...
10848 13:15:57.752438 <30>[ 10.103942] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10849 13:15:57.759019 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10850 13:15:57.824539 <30>[ 10.175797] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10851 13:15:57.834482 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10852 13:15:57.857145 <30>[ 10.208172] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10853 13:15:57.863372 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10854 13:15:57.924624 <30>[ 10.275649] systemd[1]: Starting systemd-journald.service - Journal Service...
10855 13:15:57.930792 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10856 13:15:57.951416 <30>[ 10.302497] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10857 13:15:57.957467 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10858 13:15:57.982507 <30>[ 10.330436] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10859 13:15:57.988939 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10860 13:15:58.011953 <30>[ 10.363326] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10861 13:15:58.022039 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10862 13:15:58.042971 <30>[ 10.394223] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10863 13:15:58.049447 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10864 13:15:58.072663 <30>[ 10.424007] systemd[1]: Started systemd-journald.service - Journal Service.
10865 13:15:58.079405 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10866 13:15:58.098138 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10867 13:15:58.116674 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10868 13:15:58.136659 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10869 13:15:58.157212 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10870 13:15:58.178149 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10871 13:15:58.197379 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10872 13:15:58.218408 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10873 13:15:58.238654 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10874 13:15:58.258686 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10875 13:15:58.278738 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10876 13:15:58.297378 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10877 13:15:58.318393 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10878 13:15:58.325122 See 'systemctl status systemd-remount-fs.service' for details.
10879 13:15:58.335022 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10880 13:15:58.354822 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10881 13:15:58.416708 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10882 13:15:58.441071 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10883 13:15:58.459252 <46>[ 10.810722] systemd-journald[194]: Received client request to flush runtime journal.
10884 13:15:58.472484 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10885 13:15:58.497010 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10886 13:15:58.520205 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10887 13:15:58.550615 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10888 13:15:58.569407 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10889 13:15:58.589442 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10890 13:15:58.609451 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10891 13:15:58.629264 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10892 13:15:58.676594 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10893 13:15:58.710929 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10894 13:15:58.728385 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10895 13:15:58.747602 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10896 13:15:58.792030 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10897 13:15:58.813238 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10898 13:15:58.837096 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10899 13:15:58.890737 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10900 13:15:58.917849 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10901 13:15:58.942189 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10902 13:15:59.018421 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10903 13:15:59.041340 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10904 13:15:59.070759 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10905 13:15:59.189723 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10906 13:15:59.208729 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10907 13:15:59.228373 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10908 13:15:59.252845 <6>[ 11.604154] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10909 13:15:59.259137 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10910 13:15:59.269594 <6>[ 11.620789] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10911 13:15:59.275946 <6>[ 11.629017] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10912 13:15:59.282883 <6>[ 11.629750] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10913 13:15:59.292778 <4>[ 11.637025] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10914 13:15:59.302815 [[0;32m OK [<6>[ 11.654047] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10915 13:15:59.312820 0m] Reached targ<6>[ 11.663008] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10916 13:15:59.318981 et [0;1;39mtime<6>[ 11.665504] remoteproc remoteproc0: scp is available
10917 13:15:59.328932 rs.target[0m - <6>[ 11.673106] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10918 13:15:59.329069 Timer Units.
10919 13:15:59.335600 <6>[ 11.679044] remoteproc remoteproc0: powering up scp
10920 13:15:59.342560 <6>[ 11.682011] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10921 13:15:59.352699 <6>[ 11.682070] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10922 13:15:59.359501 <6>[ 11.682084] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10923 13:15:59.369356 <6>[ 11.688264] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10924 13:15:59.375592 <6>[ 11.688267] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10925 13:15:59.385589 <6>[ 11.688274] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10926 13:15:59.392376 <3>[ 11.691087] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10927 13:15:59.402335 <6>[ 11.694879] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10928 13:15:59.408817 <3>[ 11.702307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10929 13:15:59.415507 <6>[ 11.711021] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10930 13:15:59.422008 <3>[ 11.775032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 13:15:59.431950 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10932 13:15:59.438571 <3>[ 11.790275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 13:15:59.448234 <4>[ 11.794003] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10934 13:15:59.455009 <6>[ 11.794335] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10935 13:15:59.461438 <3>[ 11.799710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 13:15:59.471352 <4>[ 11.807671] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10937 13:15:59.478076 <3>[ 11.814785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10938 13:15:59.484540 <6>[ 11.836785] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10939 13:15:59.494593 <6>[ 11.836812] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10940 13:15:59.501225 <6>[ 11.836822] remoteproc remoteproc0: remote processor scp is now up
10941 13:15:59.508004 <3>[ 11.838214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10942 13:15:59.511068 <6>[ 11.842207] mc: Linux media interface: v0.10
10943 13:15:59.521678 <6>[ 11.856486] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10944 13:15:59.528258 <3>[ 11.860131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10945 13:15:59.534520 <6>[ 11.868295] pci_bus 0000:00: root bus resource [bus 00-ff]
10946 13:15:59.541360 <3>[ 11.880912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10947 13:15:59.548031 <6>[ 11.887860] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10948 13:15:59.557776 <3>[ 11.897772] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10949 13:15:59.567718 <6>[ 11.901696] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10950 13:15:59.574530 <3>[ 11.908809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10951 13:15:59.580939 <6>[ 11.917008] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10952 13:15:59.587768 <6>[ 11.918123] videodev: Linux video capture interface: v2.00
10953 13:15:59.594148 <3>[ 11.926851] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10954 13:15:59.603993 <6>[ 11.931662] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10955 13:15:59.610863 <6>[ 11.934814] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10956 13:15:59.620795 <3>[ 11.941164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10957 13:15:59.627445 <6>[ 11.942077] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10958 13:15:59.637081 <6>[ 11.944099] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10959 13:15:59.640354 <6>[ 11.946867] pci 0000:00:00.0: supports D1 D2
10960 13:15:59.650835 <3>[ 11.954891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10961 13:15:59.657071 <6>[ 11.964187] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10962 13:15:59.667033 <6>[ 11.967309] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10963 13:15:59.673994 <6>[ 11.967748] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10964 13:15:59.683901 <3>[ 11.971663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10965 13:15:59.690229 <3>[ 11.971675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10966 13:15:59.700253 <3>[ 11.971680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10967 13:15:59.706982 <3>[ 11.971747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10968 13:15:59.716851 <6>[ 11.984759] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10969 13:15:59.720137 <6>[ 11.997654] Bluetooth: Core ver 2.22
10970 13:15:59.726725 <6>[ 12.001201] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10971 13:15:59.730249 <6>[ 12.009369] NET: Registered PF_BLUETOOTH protocol family
10972 13:15:59.739945 <6>[ 12.016193] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10973 13:15:59.746565 <6>[ 12.026072] Bluetooth: HCI device and connection manager initialized
10974 13:15:59.753404 <6>[ 12.026983] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10975 13:15:59.766422 <6>[ 12.027968] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10976 13:15:59.769921 <6>[ 12.028063] usbcore: registered new interface driver uvcvideo
10977 13:15:59.779343 <6>[ 12.035122] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10978 13:15:59.786247 <4>[ 12.042936] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10979 13:15:59.792889 <4>[ 12.042936] Fallback method does not support PEC.
10980 13:15:59.796004 <6>[ 12.043273] Bluetooth: HCI socket layer initialized
10981 13:15:59.806091 <6>[ 12.051274] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10982 13:15:59.809262 <6>[ 12.059344] Bluetooth: L2CAP socket layer initialized
10983 13:15:59.816025 <6>[ 12.067533] pci 0000:01:00.0: supports D1 D2
10984 13:15:59.819177 <6>[ 12.068159] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10985 13:15:59.825811 <6>[ 12.075672] Bluetooth: SCO socket layer initialized
10986 13:15:59.832505 <6>[ 12.079487] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10987 13:15:59.839119 <6>[ 12.090602] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10988 13:15:59.845796 <6>[ 12.165041] usbcore: registered new interface driver btusb
10989 13:15:59.855718 <4>[ 12.166026] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10990 13:15:59.862144 <3>[ 12.166037] Bluetooth: hci0: Failed to load firmware file (-2)
10991 13:15:59.868926 <3>[ 12.166041] Bluetooth: hci0: Failed to set up firmware (-2)
10992 13:15:59.878686 <4>[ 12.166046] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10993 13:15:59.885402 <6>[ 12.169850] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10994 13:15:59.895279 <6>[ 12.246335] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10995 13:15:59.901765 <6>[ 12.246345] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10996 13:15:59.911772 <6>[ 12.246359] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10997 13:15:59.918413 <6>[ 12.246371] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10998 13:15:59.925228 <6>[ 12.246383] pci 0000:00:00.0: PCI bridge to [bus 01]
10999 13:15:59.932000 [[0;32m OK [<6>[ 12.246388] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11000 13:15:59.941671 0m] Reached targ<6>[ 12.246550] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11001 13:15:59.948396 et [0;1;39msock<6>[ 12.301170] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11002 13:15:59.955107 ets.target[0m -<6>[ 12.308561] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11003 13:15:59.958068 Socket Units.
11004 13:15:59.976245 <5>[ 12.327812] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11005 13:15:59.997766 <5>[ 12.349258] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11006 13:16:00.004351 <5>[ 12.356747] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11007 13:16:00.014113 <4>[ 12.365210] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11008 13:16:00.017843 <6>[ 12.374120] cfg80211: failed to load regulatory.db
11009 13:16:00.028269 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11010 13:16:00.046709 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11011 13:16:00.062533 <6>[ 12.414203] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11012 13:16:00.069203 <6>[ 12.421924] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11013 13:16:00.075904 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11014 13:16:00.093085 <6>[ 12.448167] mt7921e 0000:01:00.0: ASIC revision: 79610010
11015 13:16:00.105952 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11016 13:16:00.127933 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11017 13:16:00.160597 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11018 13:16:00.199100 <6>[ 12.550555] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11019 13:16:00.202205 <6>[ 12.550555]
11020 13:16:00.208466 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11021 13:16:00.228116 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11022 13:16:00.240517 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11023 13:16:00.259176 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11024 13:16:00.313992 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11025 13:16:00.338516 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11026 13:16:00.358741 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11027 13:16:00.377755 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11028 13:16:00.396546 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11029 13:16:00.443453 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11030 13:16:00.468000 [[0;32m OK [0m] Started [0;<6>[ 12.817722] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11031 13:16:00.474319 1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11032 13:16:00.489916 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11033 13:16:00.505289 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11034 13:16:00.524259 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11035 13:16:00.579916 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11036 13:16:00.604685 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11037 13:16:00.626384 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11038 13:16:00.666206 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11039 13:16:00.721849
11040 13:16:00.725339 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11041 13:16:00.725451
11042 13:16:00.728328 debian-bookworm-arm64 login: root (automatic login)
11043 13:16:00.728428
11044 13:16:00.752336 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Thu Jul 18 12:53:03 UTC 2024 aarch64
11045 13:16:00.752465
11046 13:16:00.758669 The programs included with the Debian GNU/Linux system are free software;
11047 13:16:00.765314 the exact distribution terms for each program are described in the
11048 13:16:00.768695 individual files in /usr/share/doc/*/copyright.
11049 13:16:00.768795
11050 13:16:00.775673 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11051 13:16:00.778867 permitted by applicable law.
11052 13:16:00.779340 Matched prompt #10: / #
11054 13:16:00.779623 Setting prompt string to ['/ #']
11055 13:16:00.779750 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11057 13:16:00.780035 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11058 13:16:00.780161 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
11059 13:16:00.780256 Setting prompt string to ['/ #']
11060 13:16:00.780343 Forcing a shell prompt, looking for ['/ #']
11061 13:16:00.780429 Sending line: ''
11063 13:16:00.830787 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11064 13:16:00.830888 Waiting using forced prompt support (timeout 00:02:30)
11065 13:16:00.835386 / #
11066 13:16:00.835697 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11067 13:16:00.835827 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11068 13:16:00.835956 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11069 13:16:00.836074 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
11070 13:16:00.836202 end: 2 depthcharge-action (duration 00:01:36) [common]
11071 13:16:00.836324 start: 3 lava-test-retry (timeout 00:05:00) [common]
11072 13:16:00.836450 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11073 13:16:00.836553 Using namespace: common
11074 13:16:00.836655 Sending line: '#'
11076 13:16:00.937122 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11077 13:16:00.941812 / # #
11078 13:16:00.942106 Using /lava-14879020
11079 13:16:00.942203 Sending line: 'export SHELL=/bin/sh'
11081 13:16:01.047665 / # export SHELL=/bin/sh
11082 13:16:01.047946 Sending line: '. /lava-14879020/environment'
11084 13:16:01.153707 / # . /lava-14879020/environment
11085 13:16:01.154015 Sending line: '/lava-14879020/bin/lava-test-runner /lava-14879020/0'
11087 13:16:01.254492 Test shell timeout: 10s (minimum of the action and connection timeout)
11088 13:16:01.259469 / # /lava-14879020/bin/lava-test-runner /lava-14879020/0
11089 13:16:01.279613 + export TESTRUN_ID=0_cros-ec
11090 13:16:01.286378 +<8>[ 13.640628] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14879020_1.5.2.3.1>
11091 13:16:01.286673 Received signal: <STARTRUN> 0_cros-ec 14879020_1.5.2.3.1
11092 13:16:01.286772 Starting test lava.0_cros-ec (14879020_1.5.2.3.1)
11093 13:16:01.286884 Skipping test definition patterns.
11094 13:16:01.289490 cd /lava-14879020/0/tests/0_cros-ec
11095 13:16:01.293110 + cat uuid
11096 13:16:01.293216 + UUID=14879020_1.5.2.3.1
11097 13:16:01.296249 + set +x
11098 13:16:01.299347 + python3 -m cros.runners.lava_runner -v
11099 13:16:01.334771 <6>[ 13.690095] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11100 13:16:01.748537 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11101 13:16:01.755125 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11102 13:16:01.755247
11103 13:16:01.762177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11104 13:16:01.762463 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11106 13:16:01.771693 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11107 13:16:01.781706 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11108 13:16:01.781825
11109 13:16:01.788468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11110 13:16:01.788745 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11112 13:16:01.798791 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11113 13:16:01.804888 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11114 13:16:01.805001
11115 13:16:01.811502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11116 13:16:01.811803 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11118 13:16:01.818225 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11119 13:16:01.821919 Checks the standard ABI for the main Embedded Controller. ... ok
11120 13:16:01.822081
11121 13:16:01.828094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11122 13:16:01.828423 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11124 13:16:01.835205 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11125 13:16:01.841618 Checks the main Embedded controller character device. ... ok
11126 13:16:01.841775
11127 13:16:01.848251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11128 13:16:01.848580 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11130 13:16:01.854560 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11131 13:16:01.861079 Checks basic comunication with the main Embedded controller. ... ok
11132 13:16:01.861242
11133 13:16:01.864759 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11135 13:16:01.867851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11136 13:16:01.871479 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11137 13:16:01.881160 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11138 13:16:01.881281
11139 13:16:01.885034 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11141 13:16:01.887992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11142 13:16:01.894739 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11143 13:16:01.901086 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11144 13:16:01.901240
11145 13:16:01.907669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11146 13:16:01.907971 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11148 13:16:01.914088 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11149 13:16:01.920921 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11150 13:16:01.921044
11151 13:16:01.927587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11152 13:16:01.927869 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11154 13:16:01.933911 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11155 13:16:01.940611 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11156 13:16:01.940740
11157 13:16:01.947221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11158 13:16:01.947516 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11160 13:16:01.953945 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11161 13:16:01.963952 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11162 13:16:01.964086
11163 13:16:01.967291 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11165 13:16:01.970860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11166 13:16:01.973824 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11167 13:16:01.983773 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11168 13:16:01.983887
11169 13:16:01.987122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11170 13:16:01.987382 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11172 13:16:01.997092 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11173 13:16:02.004081 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11174 13:16:02.004195
11175 13:16:02.010602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11176 13:16:02.010892 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11178 13:16:02.017374 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11179 13:16:02.026847 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11180 13:16:02.026957
11181 13:16:02.033739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11182 13:16:02.034014 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11184 13:16:02.040404 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11185 13:16:02.047174 Check the cros battery ABI. ... skipped 'No BAT found'
11186 13:16:02.047292
11187 13:16:02.053501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11188 13:16:02.053757 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11190 13:16:02.063391 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11191 13:16:02.070049 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11192 13:16:02.070146
11193 13:16:02.076818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11194 13:16:02.077062 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11196 13:16:02.083727 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11197 13:16:02.089895 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11198 13:16:02.089983
11199 13:16:02.096694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11200 13:16:02.096948 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11202 13:16:02.106915 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11203 13:16:02.110045 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11204 13:16:02.113113
11205 13:16:02.120264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11206 13:16:02.120352
11207 13:16:02.120583 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11209 13:16:02.130139 ----------------------------------------------------------<8>[ 14.483432] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14879020_1.5.2.3.1>
11210 13:16:02.130223 ------------
11211 13:16:02.130457 Received signal: <ENDRUN> 0_cros-ec 14879020_1.5.2.3.1
11212 13:16:02.130539 Ending use of test pattern.
11213 13:16:02.130597 Ending test lava.0_cros-ec (14879020_1.5.2.3.1), duration 0.84
11215 13:16:02.133344 Ran 18 tests in 0.346s
11216 13:16:02.133422
11217 13:16:02.133482 OK (skipped=15)
11218 13:16:02.136517 + set +x
11219 13:16:02.136588 <LAVA_TEST_RUNNER EXIT>
11220 13:16:02.136811 ok: lava_test_shell seems to have completed
11221 13:16:02.136973 test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_abi: pass
test_cros_ec_chardev: pass
test_cros_ec_hello: pass
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
test_cros_ec_pwm_backlight: skip
test_cros_ec_battery_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_extcon_usbc_abi: skip
11222 13:16:02.137065 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11223 13:16:02.137161 end: 3 lava-test-retry (duration 00:00:01) [common]
11224 13:16:02.137254 start: 4 finalize (timeout 00:07:59) [common]
11225 13:16:02.137343 start: 4.1 power-off (timeout 00:00:30) [common]
11226 13:16:02.137467 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11227 13:16:04.222949 >> Command sent successfully.
11228 13:16:04.226095 Returned 0 in 2 seconds
11229 13:16:04.226233 end: 4.1 power-off (duration 00:00:02) [common]
11231 13:16:04.226424 start: 4.2 read-feedback (timeout 00:07:57) [common]
11232 13:16:04.226561 Listened to connection for namespace 'common' for up to 1s
11233 13:16:05.227565 Finalising connection for namespace 'common'
11234 13:16:05.227730 Disconnecting from shell: Finalise
11235 13:16:05.227826 / #
11236 13:16:05.328073 end: 4.2 read-feedback (duration 00:00:01) [common]
11237 13:16:05.328244 end: 4 finalize (duration 00:00:03) [common]
11238 13:16:05.328372 Cleaning after the job
11239 13:16:05.328494 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/ramdisk
11240 13:16:05.335124 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/kernel
11241 13:16:05.351340 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/dtb
11242 13:16:05.351600 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14879020/tftp-deploy-9azu58h2/modules
11243 13:16:05.357695 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14879020
11244 13:16:05.457813 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14879020
11245 13:16:05.457995 Job finished correctly