Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:16:38.344889 lava-dispatcher, installed at version: 2024.01
2 01:16:38.345639 start: 0 validate
3 01:16:38.346112 Start time: 2024-11-08 01:16:38.346082+00:00 (UTC)
4 01:16:38.346640 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:16:38.347185 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:16:38.389945 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:16:38.390472 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-144-g118f0dcf6420%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:16:38.419801 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:16:38.420490 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-144-g118f0dcf6420%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:16:38.450124 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:16:38.450932 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:16:38.481827 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:16:38.482316 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-144-g118f0dcf6420%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:16:38.518738 validate duration: 0.17
16 01:16:38.519586 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:16:38.519919 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:16:38.520267 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:16:38.520855 Not decompressing ramdisk as can be used compressed.
20 01:16:38.521298 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:16:38.521582 saving as /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/ramdisk/initrd.cpio.gz
22 01:16:38.521850 total size: 5628169 (5 MB)
23 01:16:38.559138 progress 0 % (0 MB)
24 01:16:38.567332 progress 5 % (0 MB)
25 01:16:38.575816 progress 10 % (0 MB)
26 01:16:38.583201 progress 15 % (0 MB)
27 01:16:38.589734 progress 20 % (1 MB)
28 01:16:38.593442 progress 25 % (1 MB)
29 01:16:38.597679 progress 30 % (1 MB)
30 01:16:38.601919 progress 35 % (1 MB)
31 01:16:38.605755 progress 40 % (2 MB)
32 01:16:38.609920 progress 45 % (2 MB)
33 01:16:38.613678 progress 50 % (2 MB)
34 01:16:38.617924 progress 55 % (2 MB)
35 01:16:38.621913 progress 60 % (3 MB)
36 01:16:38.625587 progress 65 % (3 MB)
37 01:16:38.629752 progress 70 % (3 MB)
38 01:16:38.633376 progress 75 % (4 MB)
39 01:16:38.637556 progress 80 % (4 MB)
40 01:16:38.641274 progress 85 % (4 MB)
41 01:16:38.645271 progress 90 % (4 MB)
42 01:16:38.649104 progress 95 % (5 MB)
43 01:16:38.652392 progress 100 % (5 MB)
44 01:16:38.653034 5 MB downloaded in 0.13 s (40.92 MB/s)
45 01:16:38.653558 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:16:38.654435 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:16:38.654721 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:16:38.654988 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:16:38.655575 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-144-g118f0dcf6420/arm64/defconfig/gcc-12/kernel/Image
51 01:16:38.655849 saving as /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/kernel/Image
52 01:16:38.656087 total size: 45775360 (43 MB)
53 01:16:38.656300 No compression specified
54 01:16:38.690670 progress 0 % (0 MB)
55 01:16:38.718226 progress 5 % (2 MB)
56 01:16:38.746282 progress 10 % (4 MB)
57 01:16:38.774028 progress 15 % (6 MB)
58 01:16:38.801940 progress 20 % (8 MB)
59 01:16:38.829695 progress 25 % (10 MB)
60 01:16:38.857302 progress 30 % (13 MB)
61 01:16:38.884620 progress 35 % (15 MB)
62 01:16:38.912250 progress 40 % (17 MB)
63 01:16:38.940129 progress 45 % (19 MB)
64 01:16:38.967779 progress 50 % (21 MB)
65 01:16:38.995394 progress 55 % (24 MB)
66 01:16:39.023430 progress 60 % (26 MB)
67 01:16:39.051212 progress 65 % (28 MB)
68 01:16:39.078776 progress 70 % (30 MB)
69 01:16:39.106544 progress 75 % (32 MB)
70 01:16:39.134459 progress 80 % (34 MB)
71 01:16:39.162289 progress 85 % (37 MB)
72 01:16:39.189917 progress 90 % (39 MB)
73 01:16:39.217745 progress 95 % (41 MB)
74 01:16:39.244732 progress 100 % (43 MB)
75 01:16:39.245487 43 MB downloaded in 0.59 s (74.07 MB/s)
76 01:16:39.245962 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:16:39.246775 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:16:39.247049 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:16:39.247312 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:16:39.247800 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-144-g118f0dcf6420/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:16:39.248107 saving as /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:16:39.248320 total size: 54703 (0 MB)
84 01:16:39.248528 No compression specified
85 01:16:39.287897 progress 59 % (0 MB)
86 01:16:39.288748 progress 100 % (0 MB)
87 01:16:39.289287 0 MB downloaded in 0.04 s (1.27 MB/s)
88 01:16:39.289736 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:16:39.290545 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:16:39.290804 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:16:39.291065 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:16:39.291508 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:16:39.291742 saving as /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/nfsrootfs/full.rootfs.tar
95 01:16:39.291946 total size: 120894716 (115 MB)
96 01:16:39.292193 Using unxz to decompress xz
97 01:16:39.325944 progress 0 % (0 MB)
98 01:16:40.133979 progress 5 % (5 MB)
99 01:16:40.968534 progress 10 % (11 MB)
100 01:16:41.765436 progress 15 % (17 MB)
101 01:16:42.498113 progress 20 % (23 MB)
102 01:16:43.102460 progress 25 % (28 MB)
103 01:16:43.939917 progress 30 % (34 MB)
104 01:16:44.729076 progress 35 % (40 MB)
105 01:16:45.076570 progress 40 % (46 MB)
106 01:16:45.467817 progress 45 % (51 MB)
107 01:16:46.180031 progress 50 % (57 MB)
108 01:16:47.054182 progress 55 % (63 MB)
109 01:16:47.831260 progress 60 % (69 MB)
110 01:16:48.584422 progress 65 % (74 MB)
111 01:16:49.360045 progress 70 % (80 MB)
112 01:16:50.185180 progress 75 % (86 MB)
113 01:16:50.968490 progress 80 % (92 MB)
114 01:16:51.732718 progress 85 % (98 MB)
115 01:16:52.580821 progress 90 % (103 MB)
116 01:16:53.353345 progress 95 % (109 MB)
117 01:16:54.197692 progress 100 % (115 MB)
118 01:16:54.210115 115 MB downloaded in 14.92 s (7.73 MB/s)
119 01:16:54.210798 end: 1.4.1 http-download (duration 00:00:15) [common]
121 01:16:54.212475 end: 1.4 download-retry (duration 00:00:15) [common]
122 01:16:54.213002 start: 1.5 download-retry (timeout 00:09:44) [common]
123 01:16:54.213525 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 01:16:54.214568 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-144-g118f0dcf6420/arm64/defconfig/gcc-12/modules.tar.xz
125 01:16:54.215049 saving as /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/modules/modules.tar
126 01:16:54.215463 total size: 11605964 (11 MB)
127 01:16:54.215882 Using unxz to decompress xz
128 01:16:54.258105 progress 0 % (0 MB)
129 01:16:54.323861 progress 5 % (0 MB)
130 01:16:54.396945 progress 10 % (1 MB)
131 01:16:54.492042 progress 15 % (1 MB)
132 01:16:54.583928 progress 20 % (2 MB)
133 01:16:54.662652 progress 25 % (2 MB)
134 01:16:54.737753 progress 30 % (3 MB)
135 01:16:54.810707 progress 35 % (3 MB)
136 01:16:54.886660 progress 40 % (4 MB)
137 01:16:54.961687 progress 45 % (5 MB)
138 01:16:55.044834 progress 50 % (5 MB)
139 01:16:55.121258 progress 55 % (6 MB)
140 01:16:55.205980 progress 60 % (6 MB)
141 01:16:55.285739 progress 65 % (7 MB)
142 01:16:55.361836 progress 70 % (7 MB)
143 01:16:55.443622 progress 75 % (8 MB)
144 01:16:55.525954 progress 80 % (8 MB)
145 01:16:55.605764 progress 85 % (9 MB)
146 01:16:55.689240 progress 90 % (9 MB)
147 01:16:55.768177 progress 95 % (10 MB)
148 01:16:55.845276 progress 100 % (11 MB)
149 01:16:55.855938 11 MB downloaded in 1.64 s (6.75 MB/s)
150 01:16:55.877171 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:16:55.887645 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:16:55.888022 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 01:16:55.888324 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 01:17:12.254340 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/956205/extract-nfsrootfs-k1zh1v0n
156 01:17:12.254941 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:17:12.255279 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 01:17:12.255955 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq
159 01:17:12.256525 makedir: /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin
160 01:17:12.256903 makedir: /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/tests
161 01:17:12.257224 makedir: /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/results
162 01:17:12.257563 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-add-keys
163 01:17:12.258175 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-add-sources
164 01:17:12.258762 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-background-process-start
165 01:17:12.260729 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-background-process-stop
166 01:17:12.261381 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-common-functions
167 01:17:12.261902 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-echo-ipv4
168 01:17:12.262424 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-install-packages
169 01:17:12.262941 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-installed-packages
170 01:17:12.263429 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-os-build
171 01:17:12.263919 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-probe-channel
172 01:17:12.264470 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-probe-ip
173 01:17:12.264970 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-target-ip
174 01:17:12.265453 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-target-mac
175 01:17:12.265943 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-target-storage
176 01:17:12.266466 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-test-case
177 01:17:12.266992 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-test-event
178 01:17:12.267497 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-test-feedback
179 01:17:12.268126 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-test-raise
180 01:17:12.268664 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-test-reference
181 01:17:12.269174 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-test-runner
182 01:17:12.269689 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-test-set
183 01:17:12.270191 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-test-shell
184 01:17:12.270728 Updating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-add-keys (debian)
185 01:17:12.271314 Updating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-add-sources (debian)
186 01:17:12.271850 Updating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-install-packages (debian)
187 01:17:12.272456 Updating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-installed-packages (debian)
188 01:17:12.273031 Updating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/bin/lava-os-build (debian)
189 01:17:12.273523 Creating /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/environment
190 01:17:12.273941 LAVA metadata
191 01:17:12.274217 - LAVA_JOB_ID=956205
192 01:17:12.274433 - LAVA_DISPATCHER_IP=192.168.6.2
193 01:17:12.274809 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 01:17:12.275790 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 01:17:12.276167 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 01:17:12.276387 skipped lava-vland-overlay
197 01:17:12.276630 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 01:17:12.276887 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 01:17:12.277106 skipped lava-multinode-overlay
200 01:17:12.277347 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 01:17:12.277598 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 01:17:12.277848 Loading test definitions
203 01:17:12.278127 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 01:17:12.278350 Using /lava-956205 at stage 0
205 01:17:12.279449 uuid=956205_1.6.2.4.1 testdef=None
206 01:17:12.279773 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 01:17:12.280062 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 01:17:12.281695 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 01:17:12.282511 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 01:17:12.284477 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 01:17:12.285324 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 01:17:12.287179 runner path: /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/0/tests/0_timesync-off test_uuid 956205_1.6.2.4.1
215 01:17:12.287771 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 01:17:12.288634 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 01:17:12.288863 Using /lava-956205 at stage 0
219 01:17:12.289230 Fetching tests from https://github.com/kernelci/test-definitions.git
220 01:17:12.289536 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/0/tests/1_kselftest-alsa'
221 01:17:15.681996 Running '/usr/bin/git checkout kernelci.org
222 01:17:16.130094 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 01:17:16.131526 uuid=956205_1.6.2.4.5 testdef=None
224 01:17:16.131863 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 01:17:16.132655 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 01:17:16.135465 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 01:17:16.136304 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 01:17:16.140001 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 01:17:16.140851 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 01:17:16.144421 runner path: /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/0/tests/1_kselftest-alsa test_uuid 956205_1.6.2.4.5
234 01:17:16.144705 BOARD='meson-g12b-a311d-libretech-cc'
235 01:17:16.144911 BRANCH='clk'
236 01:17:16.145109 SKIPFILE='/dev/null'
237 01:17:16.145307 SKIP_INSTALL='True'
238 01:17:16.145503 TESTPROG_URL='http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-144-g118f0dcf6420/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 01:17:16.145703 TST_CASENAME=''
240 01:17:16.145899 TST_CMDFILES='alsa'
241 01:17:16.146433 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 01:17:16.147212 Creating lava-test-runner.conf files
244 01:17:16.147416 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/956205/lava-overlay-xuwtwilq/lava-956205/0 for stage 0
245 01:17:16.147765 - 0_timesync-off
246 01:17:16.148029 - 1_kselftest-alsa
247 01:17:16.148439 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 01:17:16.148760 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 01:17:39.263908 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 01:17:39.264387 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 01:17:39.264654 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 01:17:39.264924 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 01:17:39.265187 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 01:17:39.879399 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 01:17:39.879866 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
256 01:17:39.880160 extracting modules file /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956205/extract-nfsrootfs-k1zh1v0n
257 01:17:41.244969 extracting modules file /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956205/extract-overlay-ramdisk-rfxvzf64/ramdisk
258 01:17:42.649725 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 01:17:42.650225 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 01:17:42.650529 [common] Applying overlay to NFS
261 01:17:42.650763 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956205/compress-overlay-c4gnz1pk/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/956205/extract-nfsrootfs-k1zh1v0n
262 01:17:45.418637 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 01:17:45.419125 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 01:17:45.419402 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 01:17:45.419634 Converting downloaded kernel to a uImage
266 01:17:45.419947 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/kernel/Image /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/kernel/uImage
267 01:17:45.923964 output: Image Name:
268 01:17:45.924424 output: Created: Fri Nov 8 01:17:45 2024
269 01:17:45.924638 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 01:17:45.924845 output: Data Size: 45775360 Bytes = 44702.50 KiB = 43.65 MiB
271 01:17:45.925047 output: Load Address: 01080000
272 01:17:45.925248 output: Entry Point: 01080000
273 01:17:45.925446 output:
274 01:17:45.925783 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 01:17:45.926053 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 01:17:45.926322 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
277 01:17:45.926577 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 01:17:45.926836 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
279 01:17:45.927095 Building ramdisk /var/lib/lava/dispatcher/tmp/956205/extract-overlay-ramdisk-rfxvzf64/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/956205/extract-overlay-ramdisk-rfxvzf64/ramdisk
280 01:17:48.039768 >> 166791 blocks
281 01:17:55.805910 Adding RAMdisk u-boot header.
282 01:17:55.806576 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/956205/extract-overlay-ramdisk-rfxvzf64/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/956205/extract-overlay-ramdisk-rfxvzf64/ramdisk.cpio.gz.uboot
283 01:17:56.073564 output: Image Name:
284 01:17:56.073984 output: Created: Fri Nov 8 01:17:55 2024
285 01:17:56.074195 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 01:17:56.074400 output: Data Size: 23433091 Bytes = 22883.88 KiB = 22.35 MiB
287 01:17:56.074602 output: Load Address: 00000000
288 01:17:56.074799 output: Entry Point: 00000000
289 01:17:56.074998 output:
290 01:17:56.075593 rename /var/lib/lava/dispatcher/tmp/956205/extract-overlay-ramdisk-rfxvzf64/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/ramdisk/ramdisk.cpio.gz.uboot
291 01:17:56.076050 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 01:17:56.076667 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 01:17:56.077251 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 01:17:56.077750 No LXC device requested
295 01:17:56.078298 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 01:17:56.078855 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 01:17:56.079394 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 01:17:56.079842 Checking files for TFTP limit of 4294967296 bytes.
299 01:17:56.082800 end: 1 tftp-deploy (duration 00:01:18) [common]
300 01:17:56.083424 start: 2 uboot-action (timeout 00:05:00) [common]
301 01:17:56.084034 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 01:17:56.084600 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 01:17:56.085156 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 01:17:56.085733 Using kernel file from prepare-kernel: 956205/tftp-deploy-yw8u_zq5/kernel/uImage
305 01:17:56.086419 substitutions:
306 01:17:56.086870 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 01:17:56.087315 - {DTB_ADDR}: 0x01070000
308 01:17:56.087758 - {DTB}: 956205/tftp-deploy-yw8u_zq5/dtb/meson-g12b-a311d-libretech-cc.dtb
309 01:17:56.088245 - {INITRD}: 956205/tftp-deploy-yw8u_zq5/ramdisk/ramdisk.cpio.gz.uboot
310 01:17:56.088693 - {KERNEL_ADDR}: 0x01080000
311 01:17:56.089133 - {KERNEL}: 956205/tftp-deploy-yw8u_zq5/kernel/uImage
312 01:17:56.089569 - {LAVA_MAC}: None
313 01:17:56.090044 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/956205/extract-nfsrootfs-k1zh1v0n
314 01:17:56.090483 - {NFS_SERVER_IP}: 192.168.6.2
315 01:17:56.090913 - {PRESEED_CONFIG}: None
316 01:17:56.091344 - {PRESEED_LOCAL}: None
317 01:17:56.091775 - {RAMDISK_ADDR}: 0x08000000
318 01:17:56.092256 - {RAMDISK}: 956205/tftp-deploy-yw8u_zq5/ramdisk/ramdisk.cpio.gz.uboot
319 01:17:56.092693 - {ROOT_PART}: None
320 01:17:56.093126 - {ROOT}: None
321 01:17:56.093554 - {SERVER_IP}: 192.168.6.2
322 01:17:56.093983 - {TEE_ADDR}: 0x83000000
323 01:17:56.094409 - {TEE}: None
324 01:17:56.094834 Parsed boot commands:
325 01:17:56.095251 - setenv autoload no
326 01:17:56.095677 - setenv initrd_high 0xffffffff
327 01:17:56.096124 - setenv fdt_high 0xffffffff
328 01:17:56.096551 - dhcp
329 01:17:56.096974 - setenv serverip 192.168.6.2
330 01:17:56.097401 - tftpboot 0x01080000 956205/tftp-deploy-yw8u_zq5/kernel/uImage
331 01:17:56.097831 - tftpboot 0x08000000 956205/tftp-deploy-yw8u_zq5/ramdisk/ramdisk.cpio.gz.uboot
332 01:17:56.098257 - tftpboot 0x01070000 956205/tftp-deploy-yw8u_zq5/dtb/meson-g12b-a311d-libretech-cc.dtb
333 01:17:56.098685 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/956205/extract-nfsrootfs-k1zh1v0n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 01:17:56.099129 - bootm 0x01080000 0x08000000 0x01070000
335 01:17:56.099668 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 01:17:56.101374 start: 2.3 connect-device (timeout 00:05:00) [common]
338 01:17:56.101837 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 01:17:56.115974 Setting prompt string to ['lava-test: # ']
340 01:17:56.117611 end: 2.3 connect-device (duration 00:00:00) [common]
341 01:17:56.118269 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 01:17:56.118991 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 01:17:56.119655 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 01:17:56.121009 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 01:17:56.170080 >> OK - accepted request
346 01:17:56.172293 Returned 0 in 0 seconds
347 01:17:56.273443 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 01:17:56.275139 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 01:17:56.275745 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 01:17:56.276357 Setting prompt string to ['Hit any key to stop autoboot']
352 01:17:56.276855 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 01:17:56.278518 Trying 192.168.56.21...
354 01:17:56.279040 Connected to conserv1.
355 01:17:56.279487 Escape character is '^]'.
356 01:17:56.279941
357 01:17:56.280441 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 01:17:56.280908
359 01:18:07.771771 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 01:18:07.772476 bl2_stage_init 0x01
361 01:18:07.772950 bl2_stage_init 0x81
362 01:18:07.777318 hw id: 0x0000 - pwm id 0x01
363 01:18:07.777878 bl2_stage_init 0xc1
364 01:18:07.778335 bl2_stage_init 0x02
365 01:18:07.778771
366 01:18:07.783084 L0:00000000
367 01:18:07.783585 L1:20000703
368 01:18:07.784093 L2:00008067
369 01:18:07.784552 L3:14000000
370 01:18:07.788518 B2:00402000
371 01:18:07.788996 B1:e0f83180
372 01:18:07.789449
373 01:18:07.789883 TE: 58124
374 01:18:07.790312
375 01:18:07.794066 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 01:18:07.794532
377 01:18:07.794967 Board ID = 1
378 01:18:07.799654 Set A53 clk to 24M
379 01:18:07.800156 Set A73 clk to 24M
380 01:18:07.800591 Set clk81 to 24M
381 01:18:07.805247 A53 clk: 1200 MHz
382 01:18:07.805709 A73 clk: 1200 MHz
383 01:18:07.806137 CLK81: 166.6M
384 01:18:07.806561 smccc: 00012a92
385 01:18:07.811067 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 01:18:07.816359 board id: 1
387 01:18:07.822475 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 01:18:07.832909 fw parse done
389 01:18:07.838967 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 01:18:07.881495 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 01:18:07.892364 PIEI prepare done
392 01:18:07.892822 fastboot data load
393 01:18:07.893256 fastboot data verify
394 01:18:07.898070 verify result: 266
395 01:18:07.903693 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 01:18:07.904199 LPDDR4 probe
397 01:18:07.904639 ddr clk to 1584MHz
398 01:18:07.911630 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 01:18:07.948893
400 01:18:07.949367 dmc_version 0001
401 01:18:07.955625 Check phy result
402 01:18:07.961402 INFO : End of CA training
403 01:18:07.961863 INFO : End of initialization
404 01:18:07.967085 INFO : Training has run successfully!
405 01:18:07.967541 Check phy result
406 01:18:07.972598 INFO : End of initialization
407 01:18:07.973051 INFO : End of read enable training
408 01:18:07.976078 INFO : End of fine write leveling
409 01:18:07.981587 INFO : End of Write leveling coarse delay
410 01:18:07.987242 INFO : Training has run successfully!
411 01:18:07.987714 Check phy result
412 01:18:07.988212 INFO : End of initialization
413 01:18:07.992785 INFO : End of read dq deskew training
414 01:18:07.996236 INFO : End of MPR read delay center optimization
415 01:18:08.001795 INFO : End of write delay center optimization
416 01:18:08.007459 INFO : End of read delay center optimization
417 01:18:08.007934 INFO : End of max read latency training
418 01:18:08.013057 INFO : Training has run successfully!
419 01:18:08.013582 1D training succeed
420 01:18:08.021115 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 01:18:08.068629 Check phy result
422 01:18:08.069122 INFO : End of initialization
423 01:18:08.090223 INFO : End of 2D read delay Voltage center optimization
424 01:18:08.110305 INFO : End of 2D read delay Voltage center optimization
425 01:18:08.162244 INFO : End of 2D write delay Voltage center optimization
426 01:18:08.211518 INFO : End of 2D write delay Voltage center optimization
427 01:18:08.217050 INFO : Training has run successfully!
428 01:18:08.217544
429 01:18:08.218004 channel==0
430 01:18:08.222642 RxClkDly_Margin_A0==88 ps 9
431 01:18:08.223114 TxDqDly_Margin_A0==98 ps 10
432 01:18:08.226119 RxClkDly_Margin_A1==88 ps 9
433 01:18:08.226588 TxDqDly_Margin_A1==98 ps 10
434 01:18:08.231745 TrainedVREFDQ_A0==74
435 01:18:08.232253 TrainedVREFDQ_A1==74
436 01:18:08.232707 VrefDac_Margin_A0==25
437 01:18:08.237287 DeviceVref_Margin_A0==40
438 01:18:08.237761 VrefDac_Margin_A1==25
439 01:18:08.242793 DeviceVref_Margin_A1==40
440 01:18:08.243261
441 01:18:08.243711
442 01:18:08.244198 channel==1
443 01:18:08.244648 RxClkDly_Margin_A0==98 ps 10
444 01:18:08.248480 TxDqDly_Margin_A0==88 ps 9
445 01:18:08.248959 RxClkDly_Margin_A1==98 ps 10
446 01:18:08.254096 TxDqDly_Margin_A1==88 ps 9
447 01:18:08.254567 TrainedVREFDQ_A0==76
448 01:18:08.255017 TrainedVREFDQ_A1==77
449 01:18:08.259710 VrefDac_Margin_A0==22
450 01:18:08.260224 DeviceVref_Margin_A0==38
451 01:18:08.265224 VrefDac_Margin_A1==22
452 01:18:08.265693 DeviceVref_Margin_A1==37
453 01:18:08.266139
454 01:18:08.270833 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 01:18:08.271320
456 01:18:08.298863 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 01:18:08.304390 2D training succeed
458 01:18:08.310026 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 01:18:08.310502 auto size-- 65535DDR cs0 size: 2048MB
460 01:18:08.315609 DDR cs1 size: 2048MB
461 01:18:08.316113 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 01:18:08.321243 cs0 DataBus test pass
463 01:18:08.321710 cs1 DataBus test pass
464 01:18:08.322155 cs0 AddrBus test pass
465 01:18:08.326832 cs1 AddrBus test pass
466 01:18:08.327305
467 01:18:08.327752 100bdlr_step_size ps== 420
468 01:18:08.328242 result report
469 01:18:08.332397 boot times 0Enable ddr reg access
470 01:18:08.339971 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 01:18:08.353411 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 01:18:08.925423 0.0;M3 CHK:0;cm4_sp_mode 0
473 01:18:08.926015 MVN_1=0x00000000
474 01:18:08.930823 MVN_2=0x00000000
475 01:18:08.936591 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 01:18:08.937067 OPS=0x10
477 01:18:08.937523 ring efuse init
478 01:18:08.937964 chipver efuse init
479 01:18:08.942196 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 01:18:08.947802 [0.018961 Inits done]
481 01:18:08.948320 secure task start!
482 01:18:08.948770 high task start!
483 01:18:08.952380 low task start!
484 01:18:08.952850 run into bl31
485 01:18:08.959037 NOTICE: BL31: v1.3(release):4fc40b1
486 01:18:08.966865 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 01:18:08.967344 NOTICE: BL31: G12A normal boot!
488 01:18:08.992155 NOTICE: BL31: BL33 decompress pass
489 01:18:08.997863 ERROR: Error initializing runtime service opteed_fast
490 01:18:10.230908
491 01:18:10.231586
492 01:18:10.239281 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 01:18:10.239824
494 01:18:10.240327 Model: Libre Computer AML-A311D-CC Alta
495 01:18:10.447688 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 01:18:10.470944 DRAM: 2 GiB (effective 3.8 GiB)
497 01:18:10.613984 Core: 408 devices, 31 uclasses, devicetree: separate
498 01:18:10.619773 WDT: Not starting watchdog@f0d0
499 01:18:10.652084 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 01:18:10.664546 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 01:18:10.669498 ** Bad device specification mmc 0 **
502 01:18:10.679867 Card did not respond to voltage select! : -110
503 01:18:10.687501 ** Bad device specification mmc 0 **
504 01:18:10.688007 Couldn't find partition mmc 0
505 01:18:10.695846 Card did not respond to voltage select! : -110
506 01:18:10.701363 ** Bad device specification mmc 0 **
507 01:18:10.701842 Couldn't find partition mmc 0
508 01:18:10.706435 Error: could not access storage.
509 01:18:11.971855 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 01:18:11.972578 bl2_stage_init 0x01
511 01:18:11.973063 bl2_stage_init 0x81
512 01:18:11.977425 hw id: 0x0000 - pwm id 0x01
513 01:18:11.977918 bl2_stage_init 0xc1
514 01:18:11.978375 bl2_stage_init 0x02
515 01:18:11.978824
516 01:18:11.982999 L0:00000000
517 01:18:11.983470 L1:20000703
518 01:18:11.983916 L2:00008067
519 01:18:11.984398 L3:14000000
520 01:18:11.988658 B2:00402000
521 01:18:11.989132 B1:e0f83180
522 01:18:11.989581
523 01:18:11.990026 TE: 58124
524 01:18:11.990472
525 01:18:11.994248 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 01:18:11.994729
527 01:18:11.995182 Board ID = 1
528 01:18:11.999818 Set A53 clk to 24M
529 01:18:12.000318 Set A73 clk to 24M
530 01:18:12.000770 Set clk81 to 24M
531 01:18:12.005494 A53 clk: 1200 MHz
532 01:18:12.005966 A73 clk: 1200 MHz
533 01:18:12.006411 CLK81: 166.6M
534 01:18:12.006851 smccc: 00012a92
535 01:18:12.011003 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 01:18:12.016626 board id: 1
537 01:18:12.022551 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 01:18:12.033232 fw parse done
539 01:18:12.039145 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 01:18:12.081869 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 01:18:12.092701 PIEI prepare done
542 01:18:12.093189 fastboot data load
543 01:18:12.093648 fastboot data verify
544 01:18:12.098333 verify result: 266
545 01:18:12.103936 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 01:18:12.104455 LPDDR4 probe
547 01:18:12.104909 ddr clk to 1584MHz
548 01:18:12.111880 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 01:18:12.149188
550 01:18:12.149698 dmc_version 0001
551 01:18:12.155846 Check phy result
552 01:18:12.161693 INFO : End of CA training
553 01:18:12.162168 INFO : End of initialization
554 01:18:12.167325 INFO : Training has run successfully!
555 01:18:12.167796 Check phy result
556 01:18:12.172872 INFO : End of initialization
557 01:18:12.173346 INFO : End of read enable training
558 01:18:12.176286 INFO : End of fine write leveling
559 01:18:12.181829 INFO : End of Write leveling coarse delay
560 01:18:12.187604 INFO : Training has run successfully!
561 01:18:12.188102 Check phy result
562 01:18:12.188550 INFO : End of initialization
563 01:18:12.193071 INFO : End of read dq deskew training
564 01:18:12.198660 INFO : End of MPR read delay center optimization
565 01:18:12.199136 INFO : End of write delay center optimization
566 01:18:12.204308 INFO : End of read delay center optimization
567 01:18:12.209832 INFO : End of max read latency training
568 01:18:12.210306 INFO : Training has run successfully!
569 01:18:12.215528 1D training succeed
570 01:18:12.221362 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 01:18:12.268943 Check phy result
572 01:18:12.269459 INFO : End of initialization
573 01:18:12.290503 INFO : End of 2D read delay Voltage center optimization
574 01:18:12.310685 INFO : End of 2D read delay Voltage center optimization
575 01:18:12.362494 INFO : End of 2D write delay Voltage center optimization
576 01:18:12.411825 INFO : End of 2D write delay Voltage center optimization
577 01:18:12.417440 INFO : Training has run successfully!
578 01:18:12.417933
579 01:18:12.418388 channel==0
580 01:18:12.422925 RxClkDly_Margin_A0==88 ps 9
581 01:18:12.423397 TxDqDly_Margin_A0==98 ps 10
582 01:18:12.428616 RxClkDly_Margin_A1==88 ps 9
583 01:18:12.429084 TxDqDly_Margin_A1==98 ps 10
584 01:18:12.429537 TrainedVREFDQ_A0==74
585 01:18:12.434150 TrainedVREFDQ_A1==74
586 01:18:12.434622 VrefDac_Margin_A0==25
587 01:18:12.435065 DeviceVref_Margin_A0==40
588 01:18:12.439719 VrefDac_Margin_A1==24
589 01:18:12.440228 DeviceVref_Margin_A1==40
590 01:18:12.440681
591 01:18:12.441127
592 01:18:12.445346 channel==1
593 01:18:12.445819 RxClkDly_Margin_A0==98 ps 10
594 01:18:12.446269 TxDqDly_Margin_A0==98 ps 10
595 01:18:12.450948 RxClkDly_Margin_A1==98 ps 10
596 01:18:12.451424 TxDqDly_Margin_A1==88 ps 9
597 01:18:12.456601 TrainedVREFDQ_A0==76
598 01:18:12.457077 TrainedVREFDQ_A1==77
599 01:18:12.457526 VrefDac_Margin_A0==22
600 01:18:12.462110 DeviceVref_Margin_A0==38
601 01:18:12.462577 VrefDac_Margin_A1==22
602 01:18:12.467703 DeviceVref_Margin_A1==37
603 01:18:12.468203
604 01:18:12.468652 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 01:18:12.473380
606 01:18:12.501327 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 01:18:12.501871 2D training succeed
608 01:18:12.506879 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 01:18:12.512542 auto size-- 65535DDR cs0 size: 2048MB
610 01:18:12.513031 DDR cs1 size: 2048MB
611 01:18:12.518054 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 01:18:12.518537 cs0 DataBus test pass
613 01:18:12.523676 cs1 DataBus test pass
614 01:18:12.524221 cs0 AddrBus test pass
615 01:18:12.524675 cs1 AddrBus test pass
616 01:18:12.525115
617 01:18:12.529289 100bdlr_step_size ps== 420
618 01:18:12.529785 result report
619 01:18:12.534869 boot times 0Enable ddr reg access
620 01:18:12.540395 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 01:18:12.553737 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 01:18:13.125892 0.0;M3 CHK:0;cm4_sp_mode 0
623 01:18:13.126564 MVN_1=0x00000000
624 01:18:13.131251 MVN_2=0x00000000
625 01:18:13.137005 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 01:18:13.137535 OPS=0x10
627 01:18:13.137998 ring efuse init
628 01:18:13.138474 chipver efuse init
629 01:18:13.142652 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 01:18:13.148225 [0.018960 Inits done]
631 01:18:13.148699 secure task start!
632 01:18:13.149132 high task start!
633 01:18:13.152798 low task start!
634 01:18:13.153275 run into bl31
635 01:18:13.159444 NOTICE: BL31: v1.3(release):4fc40b1
636 01:18:13.167252 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 01:18:13.167724 NOTICE: BL31: G12A normal boot!
638 01:18:13.192662 NOTICE: BL31: BL33 decompress pass
639 01:18:13.198424 ERROR: Error initializing runtime service opteed_fast
640 01:18:14.431515
641 01:18:14.432196
642 01:18:14.439814 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 01:18:14.440339
644 01:18:14.440799 Model: Libre Computer AML-A311D-CC Alta
645 01:18:14.648173 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 01:18:14.671487 DRAM: 2 GiB (effective 3.8 GiB)
647 01:18:14.814590 Core: 408 devices, 31 uclasses, devicetree: separate
648 01:18:14.820606 WDT: Not starting watchdog@f0d0
649 01:18:14.852879 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 01:18:14.865200 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 01:18:14.870197 ** Bad device specification mmc 0 **
652 01:18:14.880648 Card did not respond to voltage select! : -110
653 01:18:14.888119 ** Bad device specification mmc 0 **
654 01:18:14.888509 Couldn't find partition mmc 0
655 01:18:14.896444 Card did not respond to voltage select! : -110
656 01:18:14.902072 ** Bad device specification mmc 0 **
657 01:18:14.902628 Couldn't find partition mmc 0
658 01:18:14.907212 Error: could not access storage.
659 01:18:15.249635 Net: eth0: ethernet@ff3f0000
660 01:18:15.250312 starting USB...
661 01:18:15.501425 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 01:18:15.502016 Starting the controller
663 01:18:15.508388 USB XHCI 1.10
664 01:18:17.224103 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 01:18:17.224798 bl2_stage_init 0x01
666 01:18:17.225281 bl2_stage_init 0x81
667 01:18:17.229612 hw id: 0x0000 - pwm id 0x01
668 01:18:17.230112 bl2_stage_init 0xc1
669 01:18:17.230571 bl2_stage_init 0x02
670 01:18:17.231026
671 01:18:17.235242 L0:00000000
672 01:18:17.235724 L1:20000703
673 01:18:17.236213 L2:00008067
674 01:18:17.236658 L3:14000000
675 01:18:17.238270 B2:00402000
676 01:18:17.238748 B1:e0f83180
677 01:18:17.239201
678 01:18:17.239646 TE: 58124
679 01:18:17.240127
680 01:18:17.249291 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 01:18:17.249795
682 01:18:17.250253 Board ID = 1
683 01:18:17.250697 Set A53 clk to 24M
684 01:18:17.251137 Set A73 clk to 24M
685 01:18:17.254791 Set clk81 to 24M
686 01:18:17.255267 A53 clk: 1200 MHz
687 01:18:17.255714 A73 clk: 1200 MHz
688 01:18:17.258527 CLK81: 166.6M
689 01:18:17.259005 smccc: 00012a92
690 01:18:17.264027 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 01:18:17.269670 board id: 1
692 01:18:17.274653 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 01:18:17.285270 fw parse done
694 01:18:17.291368 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 01:18:17.333872 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 01:18:17.344835 PIEI prepare done
697 01:18:17.345326 fastboot data load
698 01:18:17.345783 fastboot data verify
699 01:18:17.350382 verify result: 266
700 01:18:17.356030 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 01:18:17.356520 LPDDR4 probe
702 01:18:17.356969 ddr clk to 1584MHz
703 01:18:17.364049 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 01:18:17.401405
705 01:18:17.401915 dmc_version 0001
706 01:18:17.408005 Check phy result
707 01:18:17.415317 INFO : End of CA training
708 01:18:17.415844 INFO : End of initialization
709 01:18:17.419435 INFO : Training has run successfully!
710 01:18:17.419922 Check phy result
711 01:18:17.425011 INFO : End of initialization
712 01:18:17.425496 INFO : End of read enable training
713 01:18:17.430717 INFO : End of fine write leveling
714 01:18:17.436235 INFO : End of Write leveling coarse delay
715 01:18:17.436709 INFO : Training has run successfully!
716 01:18:17.437158 Check phy result
717 01:18:17.441811 INFO : End of initialization
718 01:18:17.442292 INFO : End of read dq deskew training
719 01:18:17.447424 INFO : End of MPR read delay center optimization
720 01:18:17.453041 INFO : End of write delay center optimization
721 01:18:17.458718 INFO : End of read delay center optimization
722 01:18:17.459231 INFO : End of max read latency training
723 01:18:17.464292 INFO : Training has run successfully!
724 01:18:17.464776 1D training succeed
725 01:18:17.473497 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 01:18:17.521104 Check phy result
727 01:18:17.521616 INFO : End of initialization
728 01:18:17.543612 INFO : End of 2D read delay Voltage center optimization
729 01:18:17.563839 INFO : End of 2D read delay Voltage center optimization
730 01:18:17.615974 INFO : End of 2D write delay Voltage center optimization
731 01:18:17.665342 INFO : End of 2D write delay Voltage center optimization
732 01:18:17.670863 INFO : Training has run successfully!
733 01:18:17.671340
734 01:18:17.671800 channel==0
735 01:18:17.676438 RxClkDly_Margin_A0==88 ps 9
736 01:18:17.676916 TxDqDly_Margin_A0==98 ps 10
737 01:18:17.679832 RxClkDly_Margin_A1==88 ps 9
738 01:18:17.680334 TxDqDly_Margin_A1==98 ps 10
739 01:18:17.685314 TrainedVREFDQ_A0==74
740 01:18:17.685791 TrainedVREFDQ_A1==74
741 01:18:17.690894 VrefDac_Margin_A0==24
742 01:18:17.691375 DeviceVref_Margin_A0==40
743 01:18:17.691824 VrefDac_Margin_A1==24
744 01:18:17.696619 DeviceVref_Margin_A1==40
745 01:18:17.697101
746 01:18:17.697548
747 01:18:17.697995 channel==1
748 01:18:17.698436 RxClkDly_Margin_A0==98 ps 10
749 01:18:17.699968 TxDqDly_Margin_A0==98 ps 10
750 01:18:17.705602 RxClkDly_Margin_A1==98 ps 10
751 01:18:17.706078 TxDqDly_Margin_A1==88 ps 9
752 01:18:17.706523 TrainedVREFDQ_A0==77
753 01:18:17.711229 TrainedVREFDQ_A1==77
754 01:18:17.711719 VrefDac_Margin_A0==22
755 01:18:17.716792 DeviceVref_Margin_A0==37
756 01:18:17.717263 VrefDac_Margin_A1==22
757 01:18:17.717709 DeviceVref_Margin_A1==37
758 01:18:17.718144
759 01:18:17.722489 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 01:18:17.722974
761 01:18:17.756050 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
762 01:18:17.756561 2D training succeed
763 01:18:17.761511 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 01:18:17.767005 auto size-- 65535DDR cs0 size: 2048MB
765 01:18:17.767483 DDR cs1 size: 2048MB
766 01:18:17.772607 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 01:18:17.773085 cs0 DataBus test pass
768 01:18:17.773533 cs1 DataBus test pass
769 01:18:17.778280 cs0 AddrBus test pass
770 01:18:17.778755 cs1 AddrBus test pass
771 01:18:17.779200
772 01:18:17.783835 100bdlr_step_size ps== 420
773 01:18:17.784355 result report
774 01:18:17.784801 boot times 0Enable ddr reg access
775 01:18:17.793702 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 01:18:17.807246 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 01:18:18.380454 0.0;M3 CHK:0;cm4_sp_mode 0
778 01:18:18.381002 MVN_1=0x00000000
779 01:18:18.385843 MVN_2=0x00000000
780 01:18:18.391624 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 01:18:18.392252 OPS=0x10
782 01:18:18.392697 ring efuse init
783 01:18:18.393122 chipver efuse init
784 01:18:18.397304 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 01:18:18.402782 [0.018961 Inits done]
786 01:18:18.403243 secure task start!
787 01:18:18.403673 high task start!
788 01:18:18.407360 low task start!
789 01:18:18.407820 run into bl31
790 01:18:18.414226 NOTICE: BL31: v1.3(release):4fc40b1
791 01:18:18.421981 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 01:18:18.422452 NOTICE: BL31: G12A normal boot!
793 01:18:18.447781 NOTICE: BL31: BL33 decompress pass
794 01:18:18.453447 ERROR: Error initializing runtime service opteed_fast
795 01:18:19.686426
796 01:18:19.687083
797 01:18:19.694685 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 01:18:19.695174
799 01:18:19.695626 Model: Libre Computer AML-A311D-CC Alta
800 01:18:19.903074 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 01:18:19.926494 DRAM: 2 GiB (effective 3.8 GiB)
802 01:18:20.069457 Core: 408 devices, 31 uclasses, devicetree: separate
803 01:18:20.075414 WDT: Not starting watchdog@f0d0
804 01:18:20.107853 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 01:18:20.120149 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 01:18:20.124978 ** Bad device specification mmc 0 **
807 01:18:20.135347 Card did not respond to voltage select! : -110
808 01:18:20.143110 ** Bad device specification mmc 0 **
809 01:18:20.143780 Couldn't find partition mmc 0
810 01:18:20.151500 Card did not respond to voltage select! : -110
811 01:18:20.156926 ** Bad device specification mmc 0 **
812 01:18:20.157471 Couldn't find partition mmc 0
813 01:18:20.161975 Error: could not access storage.
814 01:18:20.504410 Net: eth0: ethernet@ff3f0000
815 01:18:20.505071 starting USB...
816 01:18:20.756271 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 01:18:20.756875 Starting the controller
818 01:18:20.763212 USB XHCI 1.10
819 01:18:22.922391 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 01:18:22.923063 bl2_stage_init 0x01
821 01:18:22.923543 bl2_stage_init 0x81
822 01:18:22.927950 hw id: 0x0000 - pwm id 0x01
823 01:18:22.928511 bl2_stage_init 0xc1
824 01:18:22.928979 bl2_stage_init 0x02
825 01:18:22.929432
826 01:18:22.933540 L0:00000000
827 01:18:22.934058 L1:20000703
828 01:18:22.934513 L2:00008067
829 01:18:22.934963 L3:14000000
830 01:18:22.939243 B2:00402000
831 01:18:22.939759 B1:e0f83180
832 01:18:22.940266
833 01:18:22.940724 TE: 58167
834 01:18:22.941177
835 01:18:22.944712 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 01:18:22.945231
837 01:18:22.945690 Board ID = 1
838 01:18:22.950325 Set A53 clk to 24M
839 01:18:22.950844 Set A73 clk to 24M
840 01:18:22.951297 Set clk81 to 24M
841 01:18:22.955898 A53 clk: 1200 MHz
842 01:18:22.956438 A73 clk: 1200 MHz
843 01:18:22.956903 CLK81: 166.6M
844 01:18:22.957352 smccc: 00012abe
845 01:18:22.961593 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 01:18:22.967284 board id: 1
847 01:18:22.973011 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 01:18:22.983725 fw parse done
849 01:18:22.989662 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 01:18:23.032173 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 01:18:23.043080 PIEI prepare done
852 01:18:23.043613 fastboot data load
853 01:18:23.044126 fastboot data verify
854 01:18:23.048722 verify result: 266
855 01:18:23.054381 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 01:18:23.054901 LPDDR4 probe
857 01:18:23.055360 ddr clk to 1584MHz
858 01:18:23.062301 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 01:18:23.099581
860 01:18:23.100146 dmc_version 0001
861 01:18:23.106276 Check phy result
862 01:18:23.112210 INFO : End of CA training
863 01:18:23.112727 INFO : End of initialization
864 01:18:23.117688 INFO : Training has run successfully!
865 01:18:23.118204 Check phy result
866 01:18:23.123296 INFO : End of initialization
867 01:18:23.123810 INFO : End of read enable training
868 01:18:23.126606 INFO : End of fine write leveling
869 01:18:23.132216 INFO : End of Write leveling coarse delay
870 01:18:23.137797 INFO : Training has run successfully!
871 01:18:23.138311 Check phy result
872 01:18:23.138769 INFO : End of initialization
873 01:18:23.143323 INFO : End of read dq deskew training
874 01:18:23.148956 INFO : End of MPR read delay center optimization
875 01:18:23.149468 INFO : End of write delay center optimization
876 01:18:23.154557 INFO : End of read delay center optimization
877 01:18:23.160195 INFO : End of max read latency training
878 01:18:23.160715 INFO : Training has run successfully!
879 01:18:23.165728 1D training succeed
880 01:18:23.171753 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 01:18:23.219299 Check phy result
882 01:18:23.219813 INFO : End of initialization
883 01:18:23.240903 INFO : End of 2D read delay Voltage center optimization
884 01:18:23.261051 INFO : End of 2D read delay Voltage center optimization
885 01:18:23.312878 INFO : End of 2D write delay Voltage center optimization
886 01:18:23.362276 INFO : End of 2D write delay Voltage center optimization
887 01:18:23.367721 INFO : Training has run successfully!
888 01:18:23.368292
889 01:18:23.368758 channel==0
890 01:18:23.373336 RxClkDly_Margin_A0==88 ps 9
891 01:18:23.373860 TxDqDly_Margin_A0==98 ps 10
892 01:18:23.378962 RxClkDly_Margin_A1==88 ps 9
893 01:18:23.379479 TxDqDly_Margin_A1==98 ps 10
894 01:18:23.379940 TrainedVREFDQ_A0==74
895 01:18:23.384536 TrainedVREFDQ_A1==74
896 01:18:23.385080 VrefDac_Margin_A0==25
897 01:18:23.385561 DeviceVref_Margin_A0==40
898 01:18:23.390280 VrefDac_Margin_A1==25
899 01:18:23.390829 DeviceVref_Margin_A1==40
900 01:18:23.391286
901 01:18:23.391737
902 01:18:23.395697 channel==1
903 01:18:23.396254 RxClkDly_Margin_A0==98 ps 10
904 01:18:23.396690 TxDqDly_Margin_A0==88 ps 9
905 01:18:23.401306 RxClkDly_Margin_A1==98 ps 10
906 01:18:23.401820 TxDqDly_Margin_A1==88 ps 9
907 01:18:23.406906 TrainedVREFDQ_A0==76
908 01:18:23.407407 TrainedVREFDQ_A1==77
909 01:18:23.407841 VrefDac_Margin_A0==22
910 01:18:23.412554 DeviceVref_Margin_A0==38
911 01:18:23.413122 VrefDac_Margin_A1==22
912 01:18:23.418363 DeviceVref_Margin_A1==37
913 01:18:23.418947
914 01:18:23.419385 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 01:18:23.419815
916 01:18:23.451602 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 01:18:23.452187 2D training succeed
918 01:18:23.457215 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 01:18:23.462815 auto size-- 65535DDR cs0 size: 2048MB
920 01:18:23.463320 DDR cs1 size: 2048MB
921 01:18:23.468419 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 01:18:23.468926 cs0 DataBus test pass
923 01:18:23.473995 cs1 DataBus test pass
924 01:18:23.474497 cs0 AddrBus test pass
925 01:18:23.474931 cs1 AddrBus test pass
926 01:18:23.475354
927 01:18:23.479594 100bdlr_step_size ps== 420
928 01:18:23.480142 result report
929 01:18:23.485224 boot times 0Enable ddr reg access
930 01:18:23.490572 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 01:18:23.504023 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 01:18:24.076085 0.0;M3 CHK:0;cm4_sp_mode 0
933 01:18:24.076748 MVN_1=0x00000000
934 01:18:24.081481 MVN_2=0x00000000
935 01:18:24.087243 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 01:18:24.087764 OPS=0x10
937 01:18:24.088269 ring efuse init
938 01:18:24.088720 chipver efuse init
939 01:18:24.092903 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 01:18:24.098436 [0.018960 Inits done]
941 01:18:24.098957 secure task start!
942 01:18:24.099414 high task start!
943 01:18:24.103034 low task start!
944 01:18:24.103543 run into bl31
945 01:18:24.109676 NOTICE: BL31: v1.3(release):4fc40b1
946 01:18:24.117488 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 01:18:24.118004 NOTICE: BL31: G12A normal boot!
948 01:18:24.142920 NOTICE: BL31: BL33 decompress pass
949 01:18:24.148537 ERROR: Error initializing runtime service opteed_fast
950 01:18:25.381561
951 01:18:25.382253
952 01:18:25.389921 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 01:18:25.390526
954 01:18:25.390997 Model: Libre Computer AML-A311D-CC Alta
955 01:18:25.598354 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 01:18:25.621731 DRAM: 2 GiB (effective 3.8 GiB)
957 01:18:25.764616 Core: 408 devices, 31 uclasses, devicetree: separate
958 01:18:25.770519 WDT: Not starting watchdog@f0d0
959 01:18:25.802797 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 01:18:25.815216 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 01:18:25.820223 ** Bad device specification mmc 0 **
962 01:18:25.830552 Card did not respond to voltage select! : -110
963 01:18:25.838207 ** Bad device specification mmc 0 **
964 01:18:25.838738 Couldn't find partition mmc 0
965 01:18:25.846537 Card did not respond to voltage select! : -110
966 01:18:25.852075 ** Bad device specification mmc 0 **
967 01:18:25.852593 Couldn't find partition mmc 0
968 01:18:25.857118 Error: could not access storage.
969 01:18:26.199577 Net: eth0: ethernet@ff3f0000
970 01:18:26.200252 starting USB...
971 01:18:26.451475 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 01:18:26.452151 Starting the controller
973 01:18:26.458402 USB XHCI 1.10
974 01:18:28.012636 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 01:18:28.020878 scanning usb for storage devices... 0 Storage Device(s) found
977 01:18:28.072524 Hit any key to stop autoboot: 1
978 01:18:28.073397 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
979 01:18:28.074226 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
980 01:18:28.074768 Setting prompt string to ['=>']
981 01:18:28.075320 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
982 01:18:28.088346 0
983 01:18:28.089298 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 01:18:28.089837 Sending with 10 millisecond of delay
986 01:18:29.224844 => setenv autoload no
987 01:18:29.235719 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
988 01:18:29.241201 setenv autoload no
989 01:18:29.241990 Sending with 10 millisecond of delay
991 01:18:31.040136 => setenv initrd_high 0xffffffff
992 01:18:31.051003 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
993 01:18:31.052050 setenv initrd_high 0xffffffff
994 01:18:31.052836 Sending with 10 millisecond of delay
996 01:18:32.669381 => setenv fdt_high 0xffffffff
997 01:18:32.680238 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
998 01:18:32.681142 setenv fdt_high 0xffffffff
999 01:18:32.681909 Sending with 10 millisecond of delay
1001 01:18:32.973789 => dhcp
1002 01:18:32.984560 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1003 01:18:32.985476 dhcp
1004 01:18:32.985955 Speed: 1000, full duplex
1005 01:18:32.986407 BOOTP broadcast 1
1006 01:18:32.992803 DHCP client bound to address 192.168.6.27 (8 ms)
1007 01:18:32.993593 Sending with 10 millisecond of delay
1009 01:18:34.670645 => setenv serverip 192.168.6.2
1010 01:18:34.681517 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1011 01:18:34.682482 setenv serverip 192.168.6.2
1012 01:18:34.683233 Sending with 10 millisecond of delay
1014 01:18:38.407251 => tftpboot 0x01080000 956205/tftp-deploy-yw8u_zq5/kernel/uImage
1015 01:18:38.418116 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1016 01:18:38.419087 tftpboot 0x01080000 956205/tftp-deploy-yw8u_zq5/kernel/uImage
1017 01:18:38.419578 Speed: 1000, full duplex
1018 01:18:38.420136 Using ethernet@ff3f0000 device
1019 01:18:38.421212 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 01:18:38.426682 Filename '956205/tftp-deploy-yw8u_zq5/kernel/uImage'.
1021 01:18:38.430551 Load address: 0x1080000
1022 01:18:41.238605 Loading: *################################################## 43.7 MiB
1023 01:18:41.239263 15.5 MiB/s
1024 01:18:41.239740 done
1025 01:18:41.243089 Bytes transferred = 45775424 (2ba7a40 hex)
1026 01:18:41.243943 Sending with 10 millisecond of delay
1028 01:18:45.930494 => tftpboot 0x08000000 956205/tftp-deploy-yw8u_zq5/ramdisk/ramdisk.cpio.gz.uboot
1029 01:18:45.941317 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1030 01:18:45.942221 tftpboot 0x08000000 956205/tftp-deploy-yw8u_zq5/ramdisk/ramdisk.cpio.gz.uboot
1031 01:18:45.942710 Speed: 1000, full duplex
1032 01:18:45.943170 Using ethernet@ff3f0000 device
1033 01:18:45.944324 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 01:18:45.956086 Filename '956205/tftp-deploy-yw8u_zq5/ramdisk/ramdisk.cpio.gz.uboot'.
1035 01:18:45.956642 Load address: 0x8000000
1036 01:18:52.835159 Loading: *##########################T ####################### UDP wrong checksum 00000005 00006f72
1037 01:18:57.835485 T UDP wrong checksum 00000005 00006f72
1038 01:19:07.838644 T T UDP wrong checksum 00000005 00006f72
1039 01:19:15.531724 T UDP wrong checksum 000000ff 00001ac3
1040 01:19:15.583190 UDP wrong checksum 000000ff 0000abb5
1041 01:19:22.261985 T UDP wrong checksum 000000ff 00001f84
1042 01:19:22.322967 UDP wrong checksum 000000ff 0000bb76
1043 01:19:27.841995 T T UDP wrong checksum 00000005 00006f72
1044 01:19:42.846778 T T
1045 01:19:42.847489 Retry count exceeded; starting again
1047 01:19:42.849172 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1050 01:19:42.851316 end: 2.4 uboot-commands (duration 00:01:47) [common]
1052 01:19:42.853086 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1054 01:19:42.854242 end: 2 uboot-action (duration 00:01:47) [common]
1056 01:19:42.855921 Cleaning after the job
1057 01:19:42.856599 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/ramdisk
1058 01:19:42.858610 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/kernel
1059 01:19:42.910790 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/dtb
1060 01:19:42.912195 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/nfsrootfs
1061 01:19:43.073309 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956205/tftp-deploy-yw8u_zq5/modules
1062 01:19:43.093251 start: 4.1 power-off (timeout 00:00:30) [common]
1063 01:19:43.093989 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1064 01:19:43.127479 >> OK - accepted request
1065 01:19:43.129535 Returned 0 in 0 seconds
1066 01:19:43.230428 end: 4.1 power-off (duration 00:00:00) [common]
1068 01:19:43.231525 start: 4.2 read-feedback (timeout 00:10:00) [common]
1069 01:19:43.232311 Listened to connection for namespace 'common' for up to 1s
1070 01:19:44.233179 Finalising connection for namespace 'common'
1071 01:19:44.233688 Disconnecting from shell: Finalise
1072 01:19:44.234001 =>
1073 01:19:44.334755 end: 4.2 read-feedback (duration 00:00:01) [common]
1074 01:19:44.335225 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/956205
1075 01:19:47.154967 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/956205
1076 01:19:47.155595 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.