Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:20:18.533680 lava-dispatcher, installed at version: 2024.01
2 01:20:18.534535 start: 0 validate
3 01:20:18.535045 Start time: 2024-11-08 01:20:18.535011+00:00 (UTC)
4 01:20:18.535621 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:20:18.536254 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:20:18.577661 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:20:18.578226 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-144-g118f0dcf6420%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:20:18.610871 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:20:18.611622 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-144-g118f0dcf6420%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:20:18.641659 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:20:18.642270 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:20:18.673993 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:20:18.674498 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-144-g118f0dcf6420%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:20:18.711133 validate duration: 0.18
16 01:20:18.712034 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:20:18.712387 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:20:18.712728 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:20:18.713316 Not decompressing ramdisk as can be used compressed.
20 01:20:18.713780 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 01:20:18.714078 saving as /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/ramdisk/initrd.cpio.gz
22 01:20:18.714354 total size: 5628140 (5 MB)
23 01:20:18.749492 progress 0 % (0 MB)
24 01:20:18.753687 progress 5 % (0 MB)
25 01:20:18.757853 progress 10 % (0 MB)
26 01:20:18.761536 progress 15 % (0 MB)
27 01:20:18.765573 progress 20 % (1 MB)
28 01:20:18.769303 progress 25 % (1 MB)
29 01:20:18.773297 progress 30 % (1 MB)
30 01:20:18.777359 progress 35 % (1 MB)
31 01:20:18.781023 progress 40 % (2 MB)
32 01:20:18.785020 progress 45 % (2 MB)
33 01:20:18.788630 progress 50 % (2 MB)
34 01:20:18.792650 progress 55 % (2 MB)
35 01:20:18.796733 progress 60 % (3 MB)
36 01:20:18.800313 progress 65 % (3 MB)
37 01:20:18.804356 progress 70 % (3 MB)
38 01:20:18.808019 progress 75 % (4 MB)
39 01:20:18.812025 progress 80 % (4 MB)
40 01:20:18.815632 progress 85 % (4 MB)
41 01:20:18.819563 progress 90 % (4 MB)
42 01:20:18.823416 progress 95 % (5 MB)
43 01:20:18.826677 progress 100 % (5 MB)
44 01:20:18.827357 5 MB downloaded in 0.11 s (47.51 MB/s)
45 01:20:18.827944 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:20:18.828909 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:20:18.829234 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:20:18.829528 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:20:18.830018 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-144-g118f0dcf6420/arm64/defconfig/gcc-12/kernel/Image
51 01:20:18.830283 saving as /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/kernel/Image
52 01:20:18.830507 total size: 45775360 (43 MB)
53 01:20:18.830733 No compression specified
54 01:20:18.865977 progress 0 % (0 MB)
55 01:20:18.894541 progress 5 % (2 MB)
56 01:20:18.922698 progress 10 % (4 MB)
57 01:20:18.950831 progress 15 % (6 MB)
58 01:20:18.979008 progress 20 % (8 MB)
59 01:20:19.007109 progress 25 % (10 MB)
60 01:20:19.035097 progress 30 % (13 MB)
61 01:20:19.062630 progress 35 % (15 MB)
62 01:20:19.090771 progress 40 % (17 MB)
63 01:20:19.118889 progress 45 % (19 MB)
64 01:20:19.146864 progress 50 % (21 MB)
65 01:20:19.174822 progress 55 % (24 MB)
66 01:20:19.202947 progress 60 % (26 MB)
67 01:20:19.231182 progress 65 % (28 MB)
68 01:20:19.258886 progress 70 % (30 MB)
69 01:20:19.286925 progress 75 % (32 MB)
70 01:20:19.315144 progress 80 % (34 MB)
71 01:20:19.343297 progress 85 % (37 MB)
72 01:20:19.371420 progress 90 % (39 MB)
73 01:20:19.402489 progress 95 % (41 MB)
74 01:20:19.430691 progress 100 % (43 MB)
75 01:20:19.431513 43 MB downloaded in 0.60 s (72.64 MB/s)
76 01:20:19.432027 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:20:19.432865 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:20:19.433143 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:20:19.433413 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:20:19.434027 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-144-g118f0dcf6420/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:20:19.434331 saving as /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:20:19.434543 total size: 54703 (0 MB)
84 01:20:19.434753 No compression specified
85 01:20:19.472323 progress 59 % (0 MB)
86 01:20:19.473182 progress 100 % (0 MB)
87 01:20:19.473739 0 MB downloaded in 0.04 s (1.33 MB/s)
88 01:20:19.474213 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:20:19.475045 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:20:19.475313 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:20:19.475579 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:20:19.476049 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 01:20:19.476310 saving as /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/nfsrootfs/full.rootfs.tar
95 01:20:19.476515 total size: 474398908 (452 MB)
96 01:20:19.476728 Using unxz to decompress xz
97 01:20:19.512018 progress 0 % (0 MB)
98 01:20:20.611607 progress 5 % (22 MB)
99 01:20:22.062309 progress 10 % (45 MB)
100 01:20:22.514385 progress 15 % (67 MB)
101 01:20:23.295484 progress 20 % (90 MB)
102 01:20:23.834515 progress 25 % (113 MB)
103 01:20:24.198383 progress 30 % (135 MB)
104 01:20:24.817631 progress 35 % (158 MB)
105 01:20:25.743279 progress 40 % (181 MB)
106 01:20:26.593755 progress 45 % (203 MB)
107 01:20:27.145360 progress 50 % (226 MB)
108 01:20:27.803364 progress 55 % (248 MB)
109 01:20:29.032835 progress 60 % (271 MB)
110 01:20:30.545978 progress 65 % (294 MB)
111 01:20:32.208234 progress 70 % (316 MB)
112 01:20:35.303460 progress 75 % (339 MB)
113 01:20:37.776408 progress 80 % (361 MB)
114 01:20:40.698781 progress 85 % (384 MB)
115 01:20:43.860881 progress 90 % (407 MB)
116 01:20:47.042953 progress 95 % (429 MB)
117 01:20:50.212701 progress 100 % (452 MB)
118 01:20:50.225723 452 MB downloaded in 30.75 s (14.71 MB/s)
119 01:20:50.226421 end: 1.4.1 http-download (duration 00:00:31) [common]
121 01:20:50.227420 end: 1.4 download-retry (duration 00:00:31) [common]
122 01:20:50.227764 start: 1.5 download-retry (timeout 00:09:28) [common]
123 01:20:50.228168 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 01:20:50.228872 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-144-g118f0dcf6420/arm64/defconfig/gcc-12/modules.tar.xz
125 01:20:50.229194 saving as /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/modules/modules.tar
126 01:20:50.229446 total size: 11605964 (11 MB)
127 01:20:50.229709 Using unxz to decompress xz
128 01:20:50.275905 progress 0 % (0 MB)
129 01:20:50.348126 progress 5 % (0 MB)
130 01:20:50.429146 progress 10 % (1 MB)
131 01:20:50.527501 progress 15 % (1 MB)
132 01:20:50.622442 progress 20 % (2 MB)
133 01:20:50.703437 progress 25 % (2 MB)
134 01:20:50.781995 progress 30 % (3 MB)
135 01:20:50.858691 progress 35 % (3 MB)
136 01:20:50.937937 progress 40 % (4 MB)
137 01:20:51.020085 progress 45 % (5 MB)
138 01:20:51.106412 progress 50 % (5 MB)
139 01:20:51.185875 progress 55 % (6 MB)
140 01:20:51.274524 progress 60 % (6 MB)
141 01:20:51.355221 progress 65 % (7 MB)
142 01:20:51.431645 progress 70 % (7 MB)
143 01:20:51.513256 progress 75 % (8 MB)
144 01:20:51.598692 progress 80 % (8 MB)
145 01:20:51.678165 progress 85 % (9 MB)
146 01:20:51.756224 progress 90 % (9 MB)
147 01:20:51.835553 progress 95 % (10 MB)
148 01:20:51.911944 progress 100 % (11 MB)
149 01:20:51.922794 11 MB downloaded in 1.69 s (6.54 MB/s)
150 01:20:51.923835 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:20:51.925790 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:20:51.926371 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 01:20:51.926950 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 01:21:07.096551 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/956209/extract-nfsrootfs-6fmuj7ed
156 01:21:07.097145 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 01:21:07.097435 start: 1.6.2 lava-overlay (timeout 00:09:12) [common]
158 01:21:07.098131 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx
159 01:21:07.098582 makedir: /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin
160 01:21:07.098910 makedir: /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/tests
161 01:21:07.099234 makedir: /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/results
162 01:21:07.099575 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-add-keys
163 01:21:07.100131 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-add-sources
164 01:21:07.100639 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-background-process-start
165 01:21:07.101148 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-background-process-stop
166 01:21:07.101701 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-common-functions
167 01:21:07.102223 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-echo-ipv4
168 01:21:07.102728 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-install-packages
169 01:21:07.103345 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-installed-packages
170 01:21:07.103851 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-os-build
171 01:21:07.104393 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-probe-channel
172 01:21:07.104887 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-probe-ip
173 01:21:07.105365 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-target-ip
174 01:21:07.105852 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-target-mac
175 01:21:07.106330 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-target-storage
176 01:21:07.106821 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-test-case
177 01:21:07.107309 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-test-event
178 01:21:07.107796 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-test-feedback
179 01:21:07.108330 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-test-raise
180 01:21:07.108819 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-test-reference
181 01:21:07.109327 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-test-runner
182 01:21:07.109827 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-test-set
183 01:21:07.110315 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-test-shell
184 01:21:07.110810 Updating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-install-packages (oe)
185 01:21:07.111350 Updating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/bin/lava-installed-packages (oe)
186 01:21:07.111814 Creating /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/environment
187 01:21:07.112222 LAVA metadata
188 01:21:07.112489 - LAVA_JOB_ID=956209
189 01:21:07.112706 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:21:07.113085 start: 1.6.2.1 ssh-authorize (timeout 00:09:12) [common]
191 01:21:07.114072 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:21:07.114403 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:12) [common]
193 01:21:07.114617 skipped lava-vland-overlay
194 01:21:07.114863 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:21:07.115121 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:12) [common]
196 01:21:07.115347 skipped lava-multinode-overlay
197 01:21:07.115596 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:21:07.115850 start: 1.6.2.4 test-definition (timeout 00:09:12) [common]
199 01:21:07.116139 Loading test definitions
200 01:21:07.116427 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:12) [common]
201 01:21:07.116651 Using /lava-956209 at stage 0
202 01:21:07.118022 uuid=956209_1.6.2.4.1 testdef=None
203 01:21:07.118341 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:21:07.118608 start: 1.6.2.4.2 test-overlay (timeout 00:09:12) [common]
205 01:21:07.120416 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:21:07.121228 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:12) [common]
208 01:21:07.123469 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:21:07.124382 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:12) [common]
211 01:21:07.126542 runner path: /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 956209_1.6.2.4.1
212 01:21:07.127165 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:21:07.127946 Creating lava-test-runner.conf files
215 01:21:07.128184 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/956209/lava-overlay-pldtecpx/lava-956209/0 for stage 0
216 01:21:07.128547 - 0_v4l2-decoder-conformance-h264
217 01:21:07.128909 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:21:07.129190 start: 1.6.2.5 compress-overlay (timeout 00:09:12) [common]
219 01:21:07.151056 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:21:07.151467 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:12) [common]
221 01:21:07.151730 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:21:07.152025 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:21:07.152297 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:12) [common]
224 01:21:07.790807 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:21:07.791278 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 01:21:07.791531 extracting modules file /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956209/extract-nfsrootfs-6fmuj7ed
227 01:21:09.158511 extracting modules file /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956209/extract-overlay-ramdisk-h25c0tbj/ramdisk
228 01:21:10.574126 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:21:10.574613 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 01:21:10.574894 [common] Applying overlay to NFS
231 01:21:10.575111 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956209/compress-overlay-xv4574di/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/956209/extract-nfsrootfs-6fmuj7ed
232 01:21:10.607171 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:21:10.607612 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 01:21:10.607893 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 01:21:10.608161 Converting downloaded kernel to a uImage
236 01:21:10.608481 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/kernel/Image /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/kernel/uImage
237 01:21:11.126824 output: Image Name:
238 01:21:11.127254 output: Created: Fri Nov 8 01:21:10 2024
239 01:21:11.127471 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:21:11.127682 output: Data Size: 45775360 Bytes = 44702.50 KiB = 43.65 MiB
241 01:21:11.127888 output: Load Address: 01080000
242 01:21:11.128144 output: Entry Point: 01080000
243 01:21:11.128352 output:
244 01:21:11.128694 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 01:21:11.128974 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 01:21:11.129250 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
247 01:21:11.129509 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:21:11.129774 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
249 01:21:11.130037 Building ramdisk /var/lib/lava/dispatcher/tmp/956209/extract-overlay-ramdisk-h25c0tbj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/956209/extract-overlay-ramdisk-h25c0tbj/ramdisk
250 01:21:13.269112 >> 166791 blocks
251 01:21:20.971455 Adding RAMdisk u-boot header.
252 01:21:20.972229 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/956209/extract-overlay-ramdisk-h25c0tbj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/956209/extract-overlay-ramdisk-h25c0tbj/ramdisk.cpio.gz.uboot
253 01:21:21.206659 output: Image Name:
254 01:21:21.207088 output: Created: Fri Nov 8 01:21:20 2024
255 01:21:21.207308 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:21:21.207518 output: Data Size: 23432007 Bytes = 22882.82 KiB = 22.35 MiB
257 01:21:21.207723 output: Load Address: 00000000
258 01:21:21.207927 output: Entry Point: 00000000
259 01:21:21.208361 output:
260 01:21:21.209560 rename /var/lib/lava/dispatcher/tmp/956209/extract-overlay-ramdisk-h25c0tbj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/ramdisk/ramdisk.cpio.gz.uboot
261 01:21:21.210296 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 01:21:21.210846 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 01:21:21.211379 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:58) [common]
264 01:21:21.211841 No LXC device requested
265 01:21:21.212394 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:21:21.212912 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 01:21:21.213411 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:21:21.213828 Checking files for TFTP limit of 4294967296 bytes.
269 01:21:21.216513 end: 1 tftp-deploy (duration 00:01:03) [common]
270 01:21:21.217099 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:21:21.217625 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:21:21.218123 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:21:21.218632 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:21:21.219165 Using kernel file from prepare-kernel: 956209/tftp-deploy-uzqf_ib9/kernel/uImage
275 01:21:21.219789 substitutions:
276 01:21:21.220229 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:21:21.220633 - {DTB_ADDR}: 0x01070000
278 01:21:21.221033 - {DTB}: 956209/tftp-deploy-uzqf_ib9/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:21:21.221432 - {INITRD}: 956209/tftp-deploy-uzqf_ib9/ramdisk/ramdisk.cpio.gz.uboot
280 01:21:21.221828 - {KERNEL_ADDR}: 0x01080000
281 01:21:21.222220 - {KERNEL}: 956209/tftp-deploy-uzqf_ib9/kernel/uImage
282 01:21:21.222613 - {LAVA_MAC}: None
283 01:21:21.223040 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/956209/extract-nfsrootfs-6fmuj7ed
284 01:21:21.223442 - {NFS_SERVER_IP}: 192.168.6.2
285 01:21:21.223832 - {PRESEED_CONFIG}: None
286 01:21:21.224272 - {PRESEED_LOCAL}: None
287 01:21:21.224665 - {RAMDISK_ADDR}: 0x08000000
288 01:21:21.225174 - {RAMDISK}: 956209/tftp-deploy-uzqf_ib9/ramdisk/ramdisk.cpio.gz.uboot
289 01:21:21.225579 - {ROOT_PART}: None
290 01:21:21.225975 - {ROOT}: None
291 01:21:21.226367 - {SERVER_IP}: 192.168.6.2
292 01:21:21.226764 - {TEE_ADDR}: 0x83000000
293 01:21:21.227154 - {TEE}: None
294 01:21:21.227546 Parsed boot commands:
295 01:21:21.227929 - setenv autoload no
296 01:21:21.228351 - setenv initrd_high 0xffffffff
297 01:21:21.228742 - setenv fdt_high 0xffffffff
298 01:21:21.229130 - dhcp
299 01:21:21.229518 - setenv serverip 192.168.6.2
300 01:21:21.229904 - tftpboot 0x01080000 956209/tftp-deploy-uzqf_ib9/kernel/uImage
301 01:21:21.230295 - tftpboot 0x08000000 956209/tftp-deploy-uzqf_ib9/ramdisk/ramdisk.cpio.gz.uboot
302 01:21:21.230681 - tftpboot 0x01070000 956209/tftp-deploy-uzqf_ib9/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:21:21.231066 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/956209/extract-nfsrootfs-6fmuj7ed,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:21:21.231467 - bootm 0x01080000 0x08000000 0x01070000
305 01:21:21.231970 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:21:21.233495 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:21:21.233919 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:21:21.248629 Setting prompt string to ['lava-test: # ']
310 01:21:21.250120 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:21:21.250703 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:21:21.251244 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:21:21.251773 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:21:21.252924 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:21:21.289681 >> OK - accepted request
316 01:21:21.291782 Returned 0 in 0 seconds
317 01:21:21.393008 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:21:21.394672 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:21:21.395259 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:21:21.395775 Setting prompt string to ['Hit any key to stop autoboot']
322 01:21:21.396304 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:21:21.397887 Trying 192.168.56.21...
324 01:21:21.398364 Connected to conserv1.
325 01:21:21.398788 Escape character is '^]'.
326 01:21:21.399207
327 01:21:21.399635 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 01:21:21.400079
329 01:21:32.763530 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:21:32.764215 bl2_stage_init 0x01
331 01:21:32.764651 bl2_stage_init 0x81
332 01:21:32.768979 hw id: 0x0000 - pwm id 0x01
333 01:21:32.769428 bl2_stage_init 0xc1
334 01:21:32.769829 bl2_stage_init 0x02
335 01:21:32.770223
336 01:21:32.774608 L0:00000000
337 01:21:32.775048 L1:20000703
338 01:21:32.775445 L2:00008067
339 01:21:32.775834 L3:14000000
340 01:21:32.777481 B2:00402000
341 01:21:32.777920 B1:e0f83180
342 01:21:32.778323
343 01:21:32.778722 TE: 58167
344 01:21:32.779120
345 01:21:32.788564 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:21:32.789009
347 01:21:32.789412 Board ID = 1
348 01:21:32.789801 Set A53 clk to 24M
349 01:21:32.790190 Set A73 clk to 24M
350 01:21:32.794312 Set clk81 to 24M
351 01:21:32.794740 A53 clk: 1200 MHz
352 01:21:32.795133 A73 clk: 1200 MHz
353 01:21:32.797796 CLK81: 166.6M
354 01:21:32.798218 smccc: 00012abe
355 01:21:32.803370 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:21:32.809161 board id: 1
357 01:21:32.814115 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:21:32.824596 fw parse done
359 01:21:32.830563 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:21:32.873184 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:21:32.884070 PIEI prepare done
362 01:21:32.884498 fastboot data load
363 01:21:32.884897 fastboot data verify
364 01:21:32.889659 verify result: 266
365 01:21:32.895266 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:21:32.895696 LPDDR4 probe
367 01:21:32.896142 ddr clk to 1584MHz
368 01:21:32.903263 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:21:32.940538
370 01:21:32.940977 dmc_version 0001
371 01:21:32.947287 Check phy result
372 01:21:32.953156 INFO : End of CA training
373 01:21:32.953596 INFO : End of initialization
374 01:21:32.958734 INFO : Training has run successfully!
375 01:21:32.959158 Check phy result
376 01:21:32.964334 INFO : End of initialization
377 01:21:32.964759 INFO : End of read enable training
378 01:21:32.967557 INFO : End of fine write leveling
379 01:21:32.973117 INFO : End of Write leveling coarse delay
380 01:21:32.978823 INFO : Training has run successfully!
381 01:21:32.979243 Check phy result
382 01:21:32.979642 INFO : End of initialization
383 01:21:32.984320 INFO : End of read dq deskew training
384 01:21:32.990045 INFO : End of MPR read delay center optimization
385 01:21:32.990496 INFO : End of write delay center optimization
386 01:21:32.995572 INFO : End of read delay center optimization
387 01:21:33.001100 INFO : End of max read latency training
388 01:21:33.001533 INFO : Training has run successfully!
389 01:21:33.006771 1D training succeed
390 01:21:33.012718 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:21:33.060399 Check phy result
392 01:21:33.061012 INFO : End of initialization
393 01:21:33.082114 INFO : End of 2D read delay Voltage center optimization
394 01:21:33.102274 INFO : End of 2D read delay Voltage center optimization
395 01:21:33.154447 INFO : End of 2D write delay Voltage center optimization
396 01:21:33.203766 INFO : End of 2D write delay Voltage center optimization
397 01:21:33.209227 INFO : Training has run successfully!
398 01:21:33.209664
399 01:21:33.210075 channel==0
400 01:21:33.214863 RxClkDly_Margin_A0==88 ps 9
401 01:21:33.215303 TxDqDly_Margin_A0==98 ps 10
402 01:21:33.218219 RxClkDly_Margin_A1==88 ps 9
403 01:21:33.218648 TxDqDly_Margin_A1==88 ps 9
404 01:21:33.223704 TrainedVREFDQ_A0==74
405 01:21:33.224158 TrainedVREFDQ_A1==75
406 01:21:33.224561 VrefDac_Margin_A0==25
407 01:21:33.229318 DeviceVref_Margin_A0==40
408 01:21:33.229742 VrefDac_Margin_A1==25
409 01:21:33.234932 DeviceVref_Margin_A1==39
410 01:21:33.235360
411 01:21:33.235757
412 01:21:33.236185 channel==1
413 01:21:33.236581 RxClkDly_Margin_A0==98 ps 10
414 01:21:33.240591 TxDqDly_Margin_A0==88 ps 9
415 01:21:33.241027 RxClkDly_Margin_A1==98 ps 10
416 01:21:33.246181 TxDqDly_Margin_A1==88 ps 9
417 01:21:33.246626 TrainedVREFDQ_A0==77
418 01:21:33.247024 TrainedVREFDQ_A1==78
419 01:21:33.251676 VrefDac_Margin_A0==22
420 01:21:33.252132 DeviceVref_Margin_A0==37
421 01:21:33.257271 VrefDac_Margin_A1==24
422 01:21:33.257693 DeviceVref_Margin_A1==36
423 01:21:33.258086
424 01:21:33.262898 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:21:33.263322
426 01:21:33.290904 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 01:21:33.296457 2D training succeed
428 01:21:33.302091 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:21:33.302518 auto size-- 65535DDR cs0 size: 2048MB
430 01:21:33.307666 DDR cs1 size: 2048MB
431 01:21:33.308165 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:21:33.313264 cs0 DataBus test pass
433 01:21:33.313689 cs1 DataBus test pass
434 01:21:33.314086 cs0 AddrBus test pass
435 01:21:33.318889 cs1 AddrBus test pass
436 01:21:33.319310
437 01:21:33.319712 100bdlr_step_size ps== 420
438 01:21:33.320144 result report
439 01:21:33.324426 boot times 0Enable ddr reg access
440 01:21:33.332170 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:21:33.345571 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:21:33.919511 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:21:33.920200 MVN_1=0x00000000
444 01:21:33.924786 MVN_2=0x00000000
445 01:21:33.930479 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:21:33.930925 OPS=0x10
447 01:21:33.931335 ring efuse init
448 01:21:33.931738 chipver efuse init
449 01:21:33.936218 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:21:33.941702 [0.018961 Inits done]
451 01:21:33.942140 secure task start!
452 01:21:33.942544 high task start!
453 01:21:33.946334 low task start!
454 01:21:33.946766 run into bl31
455 01:21:33.952940 NOTICE: BL31: v1.3(release):4fc40b1
456 01:21:33.960806 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:21:33.961248 NOTICE: BL31: G12A normal boot!
458 01:21:33.986667 NOTICE: BL31: BL33 decompress pass
459 01:21:33.992293 ERROR: Error initializing runtime service opteed_fast
460 01:21:35.225257
461 01:21:35.225692
462 01:21:35.233624 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:21:35.233901
464 01:21:35.234123 Model: Libre Computer AML-A311D-CC Alta
465 01:21:35.442259 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:21:35.465642 DRAM: 2 GiB (effective 3.8 GiB)
467 01:21:35.608702 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:21:35.614596 WDT: Not starting watchdog@f0d0
469 01:21:35.646792 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:21:35.659078 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:21:35.664183 ** Bad device specification mmc 0 **
472 01:21:35.674520 Card did not respond to voltage select! : -110
473 01:21:35.682125 ** Bad device specification mmc 0 **
474 01:21:35.682637 Couldn't find partition mmc 0
475 01:21:35.690484 Card did not respond to voltage select! : -110
476 01:21:35.695776 ** Bad device specification mmc 0 **
477 01:21:35.696294 Couldn't find partition mmc 0
478 01:21:35.700933 Error: could not access storage.
479 01:21:36.963821 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 01:21:36.964480 bl2_stage_init 0x01
481 01:21:36.964910 bl2_stage_init 0x81
482 01:21:36.969386 hw id: 0x0000 - pwm id 0x01
483 01:21:36.969869 bl2_stage_init 0xc1
484 01:21:36.970293 bl2_stage_init 0x02
485 01:21:36.970704
486 01:21:36.975029 L0:00000000
487 01:21:36.975496 L1:20000703
488 01:21:36.975914 L2:00008067
489 01:21:36.976362 L3:14000000
490 01:21:36.980595 B2:00402000
491 01:21:36.981050 B1:e0f83180
492 01:21:36.981466
493 01:21:36.981872 TE: 58124
494 01:21:36.982279
495 01:21:36.986096 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 01:21:36.986557
497 01:21:36.986974 Board ID = 1
498 01:21:36.991790 Set A53 clk to 24M
499 01:21:36.992272 Set A73 clk to 24M
500 01:21:36.992705 Set clk81 to 24M
501 01:21:36.997410 A53 clk: 1200 MHz
502 01:21:36.997869 A73 clk: 1200 MHz
503 01:21:36.998287 CLK81: 166.6M
504 01:21:36.998694 smccc: 00012a91
505 01:21:37.002982 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 01:21:37.008570 board id: 1
507 01:21:37.014521 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 01:21:37.025148 fw parse done
509 01:21:37.031176 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 01:21:37.073590 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 01:21:37.084519 PIEI prepare done
512 01:21:37.084986 fastboot data load
513 01:21:37.085405 fastboot data verify
514 01:21:37.090179 verify result: 266
515 01:21:37.095766 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 01:21:37.096094 LPDDR4 probe
517 01:21:37.096324 ddr clk to 1584MHz
518 01:21:37.103833 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 01:21:37.140998
520 01:21:37.141555 dmc_version 0001
521 01:21:37.147728 Check phy result
522 01:21:37.156416 INFO : End of CA training
523 01:21:37.156957 INFO : End of initialization
524 01:21:37.159141 INFO : Training has run successfully!
525 01:21:37.159623 Check phy result
526 01:21:37.164714 INFO : End of initialization
527 01:21:37.165213 INFO : End of read enable training
528 01:21:37.170321 INFO : End of fine write leveling
529 01:21:37.175941 INFO : End of Write leveling coarse delay
530 01:21:37.176479 INFO : Training has run successfully!
531 01:21:37.176913 Check phy result
532 01:21:37.181571 INFO : End of initialization
533 01:21:37.182111 INFO : End of read dq deskew training
534 01:21:37.187115 INFO : End of MPR read delay center optimization
535 01:21:37.192714 INFO : End of write delay center optimization
536 01:21:37.198326 INFO : End of read delay center optimization
537 01:21:37.198830 INFO : End of max read latency training
538 01:21:37.203933 INFO : Training has run successfully!
539 01:21:37.204467 1D training succeed
540 01:21:37.213118 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 01:21:37.260752 Check phy result
542 01:21:37.261321 INFO : End of initialization
543 01:21:37.283779 INFO : End of 2D read delay Voltage center optimization
544 01:21:37.303605 INFO : End of 2D read delay Voltage center optimization
545 01:21:37.355654 INFO : End of 2D write delay Voltage center optimization
546 01:21:37.404945 INFO : End of 2D write delay Voltage center optimization
547 01:21:37.410479 INFO : Training has run successfully!
548 01:21:37.411367
549 01:21:37.411642 channel==0
550 01:21:37.416069 RxClkDly_Margin_A0==88 ps 9
551 01:21:37.416663 TxDqDly_Margin_A0==98 ps 10
552 01:21:37.421739 RxClkDly_Margin_A1==88 ps 9
553 01:21:37.422268 TxDqDly_Margin_A1==98 ps 10
554 01:21:37.422862 TrainedVREFDQ_A0==74
555 01:21:37.427236 TrainedVREFDQ_A1==74
556 01:21:37.427745 VrefDac_Margin_A0==24
557 01:21:37.428199 DeviceVref_Margin_A0==40
558 01:21:37.433002 VrefDac_Margin_A1==24
559 01:21:37.433756 DeviceVref_Margin_A1==40
560 01:21:37.434206
561 01:21:37.434512
562 01:21:37.438583 channel==1
563 01:21:37.438872 RxClkDly_Margin_A0==98 ps 10
564 01:21:37.439285 TxDqDly_Margin_A0==88 ps 9
565 01:21:37.444047 RxClkDly_Margin_A1==98 ps 10
566 01:21:37.447730 TxDqDly_Margin_A1==88 ps 9
567 01:21:37.449941 TrainedVREFDQ_A0==77
568 01:21:37.450420 TrainedVREFDQ_A1==77
569 01:21:37.451608 VrefDac_Margin_A0==22
570 01:21:37.455248 DeviceVref_Margin_A0==37
571 01:21:37.455722 VrefDac_Margin_A1==24
572 01:21:37.461302 DeviceVref_Margin_A1==37
573 01:21:37.462045
574 01:21:37.462512 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 01:21:37.463270
576 01:21:37.494452 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 01:21:37.495036 2D training succeed
578 01:21:37.500052 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 01:21:37.505682 auto size-- 65535DDR cs0 size: 2048MB
580 01:21:37.506219 DDR cs1 size: 2048MB
581 01:21:37.511251 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 01:21:37.511731 cs0 DataBus test pass
583 01:21:37.516876 cs1 DataBus test pass
584 01:21:37.517383 cs0 AddrBus test pass
585 01:21:37.517840 cs1 AddrBus test pass
586 01:21:37.518257
587 01:21:37.522481 100bdlr_step_size ps== 420
588 01:21:37.522982 result report
589 01:21:37.528080 boot times 0Enable ddr reg access
590 01:21:37.533443 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 01:21:37.546956 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 01:21:38.120927 0.0;M3 CHK:0;cm4_sp_mode 0
593 01:21:38.121363 MVN_1=0x00000000
594 01:21:38.126165 MVN_2=0x00000000
595 01:21:38.132186 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 01:21:38.132657 OPS=0x10
597 01:21:38.133070 ring efuse init
598 01:21:38.133485 chipver efuse init
599 01:21:38.137301 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 01:21:38.142886 [0.018961 Inits done]
601 01:21:38.143330 secure task start!
602 01:21:38.143733 high task start!
603 01:21:38.147644 low task start!
604 01:21:38.148117 run into bl31
605 01:21:38.154173 NOTICE: BL31: v1.3(release):4fc40b1
606 01:21:38.161944 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 01:21:38.162396 NOTICE: BL31: G12A normal boot!
608 01:21:38.187373 NOTICE: BL31: BL33 decompress pass
609 01:21:38.192979 ERROR: Error initializing runtime service opteed_fast
610 01:21:39.425988
611 01:21:39.426619
612 01:21:39.434287 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 01:21:39.434766
614 01:21:39.435207 Model: Libre Computer AML-A311D-CC Alta
615 01:21:39.642726 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 01:21:39.666036 DRAM: 2 GiB (effective 3.8 GiB)
617 01:21:39.809097 Core: 408 devices, 31 uclasses, devicetree: separate
618 01:21:39.814924 WDT: Not starting watchdog@f0d0
619 01:21:39.847152 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 01:21:39.859666 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 01:21:39.864582 ** Bad device specification mmc 0 **
622 01:21:39.874932 Card did not respond to voltage select! : -110
623 01:21:39.882603 ** Bad device specification mmc 0 **
624 01:21:39.883127 Couldn't find partition mmc 0
625 01:21:39.890932 Card did not respond to voltage select! : -110
626 01:21:39.896435 ** Bad device specification mmc 0 **
627 01:21:39.896911 Couldn't find partition mmc 0
628 01:21:39.901485 Error: could not access storage.
629 01:21:40.243975 Net: eth0: ethernet@ff3f0000
630 01:21:40.244666 starting USB...
631 01:21:40.495843 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 01:21:40.496502 Starting the controller
633 01:21:40.502721 USB XHCI 1.10
634 01:21:42.213540 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 01:21:42.213980 bl2_stage_init 0x01
636 01:21:42.214211 bl2_stage_init 0x81
637 01:21:42.219267 hw id: 0x0000 - pwm id 0x01
638 01:21:42.219560 bl2_stage_init 0xc1
639 01:21:42.219796 bl2_stage_init 0x02
640 01:21:42.220055
641 01:21:42.224699 L0:00000000
642 01:21:42.224982 L1:20000703
643 01:21:42.225215 L2:00008067
644 01:21:42.225429 L3:14000000
645 01:21:42.227648 B2:00402000
646 01:21:42.228102 B1:e0f83180
647 01:21:42.228633
648 01:21:42.229070 TE: 58124
649 01:21:42.229495
650 01:21:42.238750 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 01:21:42.239221
652 01:21:42.239646 Board ID = 1
653 01:21:42.240092 Set A53 clk to 24M
654 01:21:42.240506 Set A73 clk to 24M
655 01:21:42.244374 Set clk81 to 24M
656 01:21:42.244832 A53 clk: 1200 MHz
657 01:21:42.245254 A73 clk: 1200 MHz
658 01:21:42.247921 CLK81: 166.6M
659 01:21:42.248404 smccc: 00012a92
660 01:21:42.253392 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 01:21:42.259184 board id: 1
662 01:21:42.264426 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 01:21:42.274833 fw parse done
664 01:21:42.280916 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 01:21:42.323425 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 01:21:42.335948 PIEI prepare done
667 01:21:42.336480 fastboot data load
668 01:21:42.336919 fastboot data verify
669 01:21:42.339944 verify result: 266
670 01:21:42.345550 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 01:21:42.346028 LPDDR4 probe
672 01:21:42.346458 ddr clk to 1584MHz
673 01:21:42.353536 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 01:21:42.390799
675 01:21:42.391291 dmc_version 0001
676 01:21:42.397442 Check phy result
677 01:21:42.403459 INFO : End of CA training
678 01:21:42.403934 INFO : End of initialization
679 01:21:42.408940 INFO : Training has run successfully!
680 01:21:42.409322 Check phy result
681 01:21:42.414599 INFO : End of initialization
682 01:21:42.414979 INFO : End of read enable training
683 01:21:42.417899 INFO : End of fine write leveling
684 01:21:42.423389 INFO : End of Write leveling coarse delay
685 01:21:42.429050 INFO : Training has run successfully!
686 01:21:42.429398 Check phy result
687 01:21:42.429649 INFO : End of initialization
688 01:21:42.434628 INFO : End of read dq deskew training
689 01:21:42.440266 INFO : End of MPR read delay center optimization
690 01:21:42.440611 INFO : End of write delay center optimization
691 01:21:42.445795 INFO : End of read delay center optimization
692 01:21:42.451467 INFO : End of max read latency training
693 01:21:42.451810 INFO : Training has run successfully!
694 01:21:42.457022 1D training succeed
695 01:21:42.463001 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 01:21:42.510646 Check phy result
697 01:21:42.511045 INFO : End of initialization
698 01:21:42.532228 INFO : End of 2D read delay Voltage center optimization
699 01:21:42.552306 INFO : End of 2D read delay Voltage center optimization
700 01:21:42.604353 INFO : End of 2D write delay Voltage center optimization
701 01:21:42.653664 INFO : End of 2D write delay Voltage center optimization
702 01:21:42.659174 INFO : Training has run successfully!
703 01:21:42.659671
704 01:21:42.660148 channel==0
705 01:21:42.664796 RxClkDly_Margin_A0==88 ps 9
706 01:21:42.665305 TxDqDly_Margin_A0==98 ps 10
707 01:21:42.670332 RxClkDly_Margin_A1==88 ps 9
708 01:21:42.670845 TxDqDly_Margin_A1==88 ps 9
709 01:21:42.671280 TrainedVREFDQ_A0==74
710 01:21:42.676008 TrainedVREFDQ_A1==74
711 01:21:42.676534 VrefDac_Margin_A0==25
712 01:21:42.676965 DeviceVref_Margin_A0==40
713 01:21:42.681476 VrefDac_Margin_A1==25
714 01:21:42.681808 DeviceVref_Margin_A1==40
715 01:21:42.682051
716 01:21:42.682267
717 01:21:42.682484 channel==1
718 01:21:42.687042 RxClkDly_Margin_A0==88 ps 9
719 01:21:42.687344 TxDqDly_Margin_A0==88 ps 9
720 01:21:42.692766 RxClkDly_Margin_A1==88 ps 9
721 01:21:42.693263 TxDqDly_Margin_A1==88 ps 9
722 01:21:42.698293 TrainedVREFDQ_A0==77
723 01:21:42.698793 TrainedVREFDQ_A1==77
724 01:21:42.699220 VrefDac_Margin_A0==22
725 01:21:42.704033 DeviceVref_Margin_A0==37
726 01:21:42.704566 VrefDac_Margin_A1==24
727 01:21:42.704992 DeviceVref_Margin_A1==37
728 01:21:42.709615
729 01:21:42.710136 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 01:21:42.710562
731 01:21:42.743131 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 01:21:42.743711 2D training succeed
733 01:21:42.748838 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 01:21:42.754274 auto size-- 65535DDR cs0 size: 2048MB
735 01:21:42.754777 DDR cs1 size: 2048MB
736 01:21:42.759848 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 01:21:42.760382 cs0 DataBus test pass
738 01:21:42.765429 cs1 DataBus test pass
739 01:21:42.765914 cs0 AddrBus test pass
740 01:21:42.766330 cs1 AddrBus test pass
741 01:21:42.766739
742 01:21:42.771067 100bdlr_step_size ps== 420
743 01:21:42.771602 result report
744 01:21:42.776725 boot times 0Enable ddr reg access
745 01:21:42.781784 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 01:21:42.795149 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 01:21:43.367210 0.0;M3 CHK:0;cm4_sp_mode 0
748 01:21:43.367863 MVN_1=0x00000000
749 01:21:43.372700 MVN_2=0x00000000
750 01:21:43.378490 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 01:21:43.379027 OPS=0x10
752 01:21:43.379438 ring efuse init
753 01:21:43.379836 chipver efuse init
754 01:21:43.383974 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 01:21:43.389591 [0.018961 Inits done]
756 01:21:43.390083 secure task start!
757 01:21:43.390489 high task start!
758 01:21:43.394128 low task start!
759 01:21:43.394597 run into bl31
760 01:21:43.400938 NOTICE: BL31: v1.3(release):4fc40b1
761 01:21:43.408761 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 01:21:43.409295 NOTICE: BL31: G12A normal boot!
763 01:21:43.434115 NOTICE: BL31: BL33 decompress pass
764 01:21:43.439807 ERROR: Error initializing runtime service opteed_fast
765 01:21:44.672829
766 01:21:44.673467
767 01:21:44.681096 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 01:21:44.681592
769 01:21:44.682021 Model: Libre Computer AML-A311D-CC Alta
770 01:21:44.889493 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 01:21:44.912882 DRAM: 2 GiB (effective 3.8 GiB)
772 01:21:45.056132 Core: 408 devices, 31 uclasses, devicetree: separate
773 01:21:45.061880 WDT: Not starting watchdog@f0d0
774 01:21:45.094093 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 01:21:45.106315 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 01:21:45.111335 ** Bad device specification mmc 0 **
777 01:21:45.121639 Card did not respond to voltage select! : -110
778 01:21:45.129354 ** Bad device specification mmc 0 **
779 01:21:45.129863 Couldn't find partition mmc 0
780 01:21:45.137693 Card did not respond to voltage select! : -110
781 01:21:45.143212 ** Bad device specification mmc 0 **
782 01:21:45.143728 Couldn't find partition mmc 0
783 01:21:45.148284 Error: could not access storage.
784 01:21:45.491761 Net: eth0: ethernet@ff3f0000
785 01:21:45.492420 starting USB...
786 01:21:45.743574 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 01:21:45.744165 Starting the controller
788 01:21:45.750546 USB XHCI 1.10
789 01:21:47.913714 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 01:21:47.914341 bl2_stage_init 0x01
791 01:21:47.914776 bl2_stage_init 0x81
792 01:21:47.919250 hw id: 0x0000 - pwm id 0x01
793 01:21:47.919739 bl2_stage_init 0xc1
794 01:21:47.920222 bl2_stage_init 0x02
795 01:21:47.920645
796 01:21:47.924929 L0:00000000
797 01:21:47.925413 L1:20000703
798 01:21:47.925828 L2:00008067
799 01:21:47.926235 L3:14000000
800 01:21:47.930368 B2:00402000
801 01:21:47.930842 B1:e0f83180
802 01:21:47.931257
803 01:21:47.931668 TE: 58159
804 01:21:47.932113
805 01:21:47.936032 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 01:21:47.936512
807 01:21:47.936751 Board ID = 1
808 01:21:47.941558 Set A53 clk to 24M
809 01:21:47.941859 Set A73 clk to 24M
810 01:21:47.942091 Set clk81 to 24M
811 01:21:47.947158 A53 clk: 1200 MHz
812 01:21:47.947563 A73 clk: 1200 MHz
813 01:21:47.947930 CLK81: 166.6M
814 01:21:47.948314 smccc: 00012ab5
815 01:21:47.952755 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 01:21:47.958332 board id: 1
817 01:21:47.964267 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:21:47.974868 fw parse done
819 01:21:47.980907 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 01:21:48.023631 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 01:21:48.034352 PIEI prepare done
822 01:21:48.034719 fastboot data load
823 01:21:48.034960 fastboot data verify
824 01:21:48.040039 verify result: 266
825 01:21:48.045598 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 01:21:48.046040 LPDDR4 probe
827 01:21:48.046363 ddr clk to 1584MHz
828 01:21:48.053555 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 01:21:48.090875
830 01:21:48.091266 dmc_version 0001
831 01:21:48.097617 Check phy result
832 01:21:48.103357 INFO : End of CA training
833 01:21:48.103664 INFO : End of initialization
834 01:21:48.109148 INFO : Training has run successfully!
835 01:21:48.109585 Check phy result
836 01:21:48.114555 INFO : End of initialization
837 01:21:48.114843 INFO : End of read enable training
838 01:21:48.117929 INFO : End of fine write leveling
839 01:21:48.123474 INFO : End of Write leveling coarse delay
840 01:21:48.129107 INFO : Training has run successfully!
841 01:21:48.129408 Check phy result
842 01:21:48.129637 INFO : End of initialization
843 01:21:48.134745 INFO : End of read dq deskew training
844 01:21:48.140407 INFO : End of MPR read delay center optimization
845 01:21:48.140759 INFO : End of write delay center optimization
846 01:21:48.145925 INFO : End of read delay center optimization
847 01:21:48.151510 INFO : End of max read latency training
848 01:21:48.151802 INFO : Training has run successfully!
849 01:21:48.157215 1D training succeed
850 01:21:48.163155 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 01:21:48.210743 Check phy result
852 01:21:48.211291 INFO : End of initialization
853 01:21:48.232475 INFO : End of 2D read delay Voltage center optimization
854 01:21:48.252609 INFO : End of 2D read delay Voltage center optimization
855 01:21:48.304633 INFO : End of 2D write delay Voltage center optimization
856 01:21:48.354184 INFO : End of 2D write delay Voltage center optimization
857 01:21:48.359639 INFO : Training has run successfully!
858 01:21:48.360119
859 01:21:48.360393 channel==0
860 01:21:48.365160 RxClkDly_Margin_A0==88 ps 9
861 01:21:48.365580 TxDqDly_Margin_A0==98 ps 10
862 01:21:48.368832 RxClkDly_Margin_A1==88 ps 9
863 01:21:48.369119 TxDqDly_Margin_A1==98 ps 10
864 01:21:48.374454 TrainedVREFDQ_A0==74
865 01:21:48.374996 TrainedVREFDQ_A1==74
866 01:21:48.375411 VrefDac_Margin_A0==25
867 01:21:48.380090 DeviceVref_Margin_A0==40
868 01:21:48.380543 VrefDac_Margin_A1==25
869 01:21:48.385588 DeviceVref_Margin_A1==40
870 01:21:48.386029
871 01:21:48.386426
872 01:21:48.386821 channel==1
873 01:21:48.387210 RxClkDly_Margin_A0==98 ps 10
874 01:21:48.391214 TxDqDly_Margin_A0==98 ps 10
875 01:21:48.391654 RxClkDly_Margin_A1==88 ps 9
876 01:21:48.396802 TxDqDly_Margin_A1==88 ps 9
877 01:21:48.397243 TrainedVREFDQ_A0==77
878 01:21:48.397645 TrainedVREFDQ_A1==77
879 01:21:48.402514 VrefDac_Margin_A0==22
880 01:21:48.402953 DeviceVref_Margin_A0==37
881 01:21:48.403350 VrefDac_Margin_A1==24
882 01:21:48.408031 DeviceVref_Margin_A1==37
883 01:21:48.408467
884 01:21:48.413643 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 01:21:48.414087
886 01:21:48.441652 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 01:21:48.447247 2D training succeed
888 01:21:48.452689 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 01:21:48.453145 auto size-- 65535DDR cs0 size: 2048MB
890 01:21:48.458262 DDR cs1 size: 2048MB
891 01:21:48.458698 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 01:21:48.463941 cs0 DataBus test pass
893 01:21:48.464413 cs1 DataBus test pass
894 01:21:48.464812 cs0 AddrBus test pass
895 01:21:48.469463 cs1 AddrBus test pass
896 01:21:48.469901
897 01:21:48.470301 100bdlr_step_size ps== 420
898 01:21:48.470701 result report
899 01:21:48.475100 boot times 0Enable ddr reg access
900 01:21:48.482417 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 01:21:48.495903 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 01:21:49.069533 0.0;M3 CHK:0;cm4_sp_mode 0
903 01:21:49.069986 MVN_1=0x00000000
904 01:21:49.075082 MVN_2=0x00000000
905 01:21:49.080792 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 01:21:49.081277 OPS=0x10
907 01:21:49.081574 ring efuse init
908 01:21:49.081825 chipver efuse init
909 01:21:49.086377 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 01:21:49.092103 [0.018960 Inits done]
911 01:21:49.092587 secure task start!
912 01:21:49.092993 high task start!
913 01:21:49.096567 low task start!
914 01:21:49.096980 run into bl31
915 01:21:49.103237 NOTICE: BL31: v1.3(release):4fc40b1
916 01:21:49.111048 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 01:21:49.111536 NOTICE: BL31: G12A normal boot!
918 01:21:49.136439 NOTICE: BL31: BL33 decompress pass
919 01:21:49.142188 ERROR: Error initializing runtime service opteed_fast
920 01:21:50.375030
921 01:21:50.375486
922 01:21:50.391149 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 01:21:50.391747
924 01:21:50.392033 Model: Libre Computer AML-A311D-CC Alta
925 01:21:50.591929 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 01:21:50.615299 DRAM: 2 GiB (effective 3.8 GiB)
927 01:21:50.759817 Core: 408 devices, 31 uclasses, devicetree: separate
928 01:21:50.764185 WDT: Not starting watchdog@f0d0
929 01:21:50.796521 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 01:21:50.808802 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 01:21:50.813775 ** Bad device specification mmc 0 **
932 01:21:50.824230 Card did not respond to voltage select! : -110
933 01:21:50.831943 ** Bad device specification mmc 0 **
934 01:21:50.832477 Couldn't find partition mmc 0
935 01:21:50.840256 Card did not respond to voltage select! : -110
936 01:21:50.845786 ** Bad device specification mmc 0 **
937 01:21:50.846427 Couldn't find partition mmc 0
938 01:21:50.850789 Error: could not access storage.
939 01:21:51.193140 Net: eth0: ethernet@ff3f0000
940 01:21:51.193601 starting USB...
941 01:21:51.444939 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 01:21:51.445552 Starting the controller
943 01:21:51.451877 USB XHCI 1.10
944 01:21:53.313576 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 01:21:53.314030 bl2_stage_init 0x01
946 01:21:53.314267 bl2_stage_init 0x81
947 01:21:53.319135 hw id: 0x0000 - pwm id 0x01
948 01:21:53.319669 bl2_stage_init 0xc1
949 01:21:53.320091 bl2_stage_init 0x02
950 01:21:53.320445
951 01:21:53.324731 L0:00000000
952 01:21:53.325121 L1:20000703
953 01:21:53.325343 L2:00008067
954 01:21:53.325547 L3:14000000
955 01:21:53.327602 B2:00402000
956 01:21:53.328119 B1:e0f83180
957 01:21:53.328475
958 01:21:53.328810 TE: 58124
959 01:21:53.329169
960 01:21:53.338807 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 01:21:53.339234
962 01:21:53.339453 Board ID = 1
963 01:21:53.339666 Set A53 clk to 24M
964 01:21:53.339874 Set A73 clk to 24M
965 01:21:53.344396 Set clk81 to 24M
966 01:21:53.344779 A53 clk: 1200 MHz
967 01:21:53.345005 A73 clk: 1200 MHz
968 01:21:53.349999 CLK81: 166.6M
969 01:21:53.350551 smccc: 00012a92
970 01:21:53.355602 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 01:21:53.356115 board id: 1
972 01:21:53.364187 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 01:21:53.374783 fw parse done
974 01:21:53.380757 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 01:21:53.423352 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 01:21:53.434302 PIEI prepare done
977 01:21:53.434808 fastboot data load
978 01:21:53.435222 fastboot data verify
979 01:21:53.439903 verify result: 266
980 01:21:53.445534 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 01:21:53.446094 LPDDR4 probe
982 01:21:53.446500 ddr clk to 1584MHz
983 01:21:53.453633 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 01:21:53.491194
985 01:21:53.491720 dmc_version 0001
986 01:21:53.497696 Check phy result
987 01:21:53.503434 INFO : End of CA training
988 01:21:53.503917 INFO : End of initialization
989 01:21:53.509098 INFO : Training has run successfully!
990 01:21:53.509690 Check phy result
991 01:21:53.514608 INFO : End of initialization
992 01:21:53.515127 INFO : End of read enable training
993 01:21:53.520221 INFO : End of fine write leveling
994 01:21:53.525879 INFO : End of Write leveling coarse delay
995 01:21:53.526392 INFO : Training has run successfully!
996 01:21:53.526826 Check phy result
997 01:21:53.531346 INFO : End of initialization
998 01:21:53.531853 INFO : End of read dq deskew training
999 01:21:53.536975 INFO : End of MPR read delay center optimization
1000 01:21:53.542678 INFO : End of write delay center optimization
1001 01:21:53.548300 INFO : End of read delay center optimization
1002 01:21:53.548807 INFO : End of max read latency training
1003 01:21:53.553811 INFO : Training has run successfully!
1004 01:21:53.554323 1D training succeed
1005 01:21:53.562909 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 01:21:53.610611 Check phy result
1007 01:21:53.611150 INFO : End of initialization
1008 01:21:53.632337 INFO : End of 2D read delay Voltage center optimization
1009 01:21:53.652634 INFO : End of 2D read delay Voltage center optimization
1010 01:21:53.704651 INFO : End of 2D write delay Voltage center optimization
1011 01:21:53.754002 INFO : End of 2D write delay Voltage center optimization
1012 01:21:53.759550 INFO : Training has run successfully!
1013 01:21:53.760103
1014 01:21:53.760558 channel==0
1015 01:21:53.765109 RxClkDly_Margin_A0==88 ps 9
1016 01:21:53.765717 TxDqDly_Margin_A0==98 ps 10
1017 01:21:53.768493 RxClkDly_Margin_A1==88 ps 9
1018 01:21:53.769002 TxDqDly_Margin_A1==98 ps 10
1019 01:21:53.774084 TrainedVREFDQ_A0==74
1020 01:21:53.774645 TrainedVREFDQ_A1==74
1021 01:21:53.775090 VrefDac_Margin_A0==25
1022 01:21:53.779646 DeviceVref_Margin_A0==40
1023 01:21:53.780231 VrefDac_Margin_A1==25
1024 01:21:53.785337 DeviceVref_Margin_A1==40
1025 01:21:53.785865
1026 01:21:53.786311
1027 01:21:53.786746 channel==1
1028 01:21:53.787175 RxClkDly_Margin_A0==98 ps 10
1029 01:21:53.790836 TxDqDly_Margin_A0==98 ps 10
1030 01:21:53.791355 RxClkDly_Margin_A1==98 ps 10
1031 01:21:53.796501 TxDqDly_Margin_A1==88 ps 9
1032 01:21:53.797022 TrainedVREFDQ_A0==77
1033 01:21:53.797470 TrainedVREFDQ_A1==77
1034 01:21:53.802160 VrefDac_Margin_A0==22
1035 01:21:53.802718 DeviceVref_Margin_A0==37
1036 01:21:53.807632 VrefDac_Margin_A1==22
1037 01:21:53.808179 DeviceVref_Margin_A1==37
1038 01:21:53.808615
1039 01:21:53.813319 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 01:21:53.813818
1041 01:21:53.841172 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
1042 01:21:53.846834 2D training succeed
1043 01:21:53.852402 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 01:21:53.852757 auto size-- 65535DDR cs0 size: 2048MB
1045 01:21:53.858067 DDR cs1 size: 2048MB
1046 01:21:53.858568 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 01:21:53.863661 cs0 DataBus test pass
1048 01:21:53.864196 cs1 DataBus test pass
1049 01:21:53.864633 cs0 AddrBus test pass
1050 01:21:53.869251 cs1 AddrBus test pass
1051 01:21:53.869747
1052 01:21:53.870185 100bdlr_step_size ps== 420
1053 01:21:53.870559 result report
1054 01:21:53.874884 boot times 0Enable ddr reg access
1055 01:21:53.882582 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 01:21:53.896143 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 01:21:54.469615 0.0;M3 CHK:0;cm4_sp_mode 0
1058 01:21:54.470090 MVN_1=0x00000000
1059 01:21:54.475054 MVN_2=0x00000000
1060 01:21:54.480865 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 01:21:54.481380 OPS=0x10
1062 01:21:54.481827 ring efuse init
1063 01:21:54.482249 chipver efuse init
1064 01:21:54.486395 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 01:21:54.491962 [0.018961 Inits done]
1066 01:21:54.492495 secure task start!
1067 01:21:54.492924 high task start!
1068 01:21:54.496594 low task start!
1069 01:21:54.497079 run into bl31
1070 01:21:54.503168 NOTICE: BL31: v1.3(release):4fc40b1
1071 01:21:54.511078 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 01:21:54.511620 NOTICE: BL31: G12A normal boot!
1073 01:21:54.536551 NOTICE: BL31: BL33 decompress pass
1074 01:21:54.542245 ERROR: Error initializing runtime service opteed_fast
1075 01:21:55.774944
1076 01:21:55.775548
1077 01:21:55.783356 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 01:21:55.783887
1079 01:21:55.784296 Model: Libre Computer AML-A311D-CC Alta
1080 01:21:55.991858 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 01:21:56.015436 DRAM: 2 GiB (effective 3.8 GiB)
1082 01:21:56.158387 Core: 408 devices, 31 uclasses, devicetree: separate
1083 01:21:56.164269 WDT: Not starting watchdog@f0d0
1084 01:21:56.196523 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 01:21:56.208952 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 01:21:56.213873 ** Bad device specification mmc 0 **
1087 01:21:56.224302 Card did not respond to voltage select! : -110
1088 01:21:56.231971 ** Bad device specification mmc 0 **
1089 01:21:56.232622 Couldn't find partition mmc 0
1090 01:21:56.240320 Card did not respond to voltage select! : -110
1091 01:21:56.245845 ** Bad device specification mmc 0 **
1092 01:21:56.246473 Couldn't find partition mmc 0
1093 01:21:56.250846 Error: could not access storage.
1094 01:21:56.594168 Net: eth0: ethernet@ff3f0000
1095 01:21:56.594617 starting USB...
1096 01:21:56.846091 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 01:21:56.846739 Starting the controller
1098 01:21:56.852981 USB XHCI 1.10
1099 01:21:58.406909 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 01:21:58.415267 scanning usb for storage devices... 0 Storage Device(s) found
1102 01:21:58.466453 Hit any key to stop autoboot: 1
1103 01:21:58.467053 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 01:21:58.467415 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 01:21:58.467707 Setting prompt string to ['=>']
1106 01:21:58.468010 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 01:21:58.472575 0
1108 01:21:58.473191 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 01:21:58.473488 Sending with 10 millisecond of delay
1111 01:21:59.607784 => setenv autoload no
1112 01:21:59.618573 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 01:21:59.621284 setenv autoload no
1114 01:21:59.621847 Sending with 10 millisecond of delay
1116 01:22:01.418010 => setenv initrd_high 0xffffffff
1117 01:22:01.428774 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 01:22:01.429430 setenv initrd_high 0xffffffff
1119 01:22:01.430017 Sending with 10 millisecond of delay
1121 01:22:03.045500 => setenv fdt_high 0xffffffff
1122 01:22:03.056248 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 01:22:03.056878 setenv fdt_high 0xffffffff
1124 01:22:03.057471 Sending with 10 millisecond of delay
1126 01:22:03.348948 => dhcp
1127 01:22:03.359561 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 01:22:03.360165 dhcp
1129 01:22:03.360525 Speed: 1000, full duplex
1130 01:22:03.360854 BOOTP broadcast 1
1131 01:22:03.371716 DHCP client bound to address 192.168.6.27 (12 ms)
1132 01:22:03.372301 Sending with 10 millisecond of delay
1134 01:22:05.047714 => setenv serverip 192.168.6.2
1135 01:22:05.061594 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 01:22:05.062500 setenv serverip 192.168.6.2
1137 01:22:05.063204 Sending with 10 millisecond of delay
1139 01:22:08.787245 => tftpboot 0x01080000 956209/tftp-deploy-uzqf_ib9/kernel/uImage
1140 01:22:08.798060 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 01:22:08.798890 tftpboot 0x01080000 956209/tftp-deploy-uzqf_ib9/kernel/uImage
1142 01:22:08.799353 Speed: 1000, full duplex
1143 01:22:08.799783 Using ethernet@ff3f0000 device
1144 01:22:08.800749 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 01:22:08.806215 Filename '956209/tftp-deploy-uzqf_ib9/kernel/uImage'.
1146 01:22:08.810224 Load address: 0x1080000
1147 01:22:11.607903 Loading: *################################################## 43.7 MiB
1148 01:22:11.608587 15.6 MiB/s
1149 01:22:11.609033 done
1150 01:22:11.612584 Bytes transferred = 45775424 (2ba7a40 hex)
1151 01:22:11.613392 Sending with 10 millisecond of delay
1153 01:22:16.300520 => tftpboot 0x08000000 956209/tftp-deploy-uzqf_ib9/ramdisk/ramdisk.cpio.gz.uboot
1154 01:22:16.311302 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 01:22:16.312148 tftpboot 0x08000000 956209/tftp-deploy-uzqf_ib9/ramdisk/ramdisk.cpio.gz.uboot
1156 01:22:16.312610 Speed: 1000, full duplex
1157 01:22:16.313035 Using ethernet@ff3f0000 device
1158 01:22:16.314059 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 01:22:16.322586 Filename '956209/tftp-deploy-uzqf_ib9/ramdisk/ramdisk.cpio.gz.uboot'.
1160 01:22:16.323002 Load address: 0x8000000
1161 01:22:22.883594 Loading: *##################T ############################### UDP wrong checksum 00000005 0000775e
1162 01:22:27.884045 T UDP wrong checksum 00000005 0000775e
1163 01:22:37.887073 T T UDP wrong checksum 00000005 0000775e
1164 01:22:42.520807 UDP wrong checksum 000000ff 0000fdba
1165 01:22:42.564946 UDP wrong checksum 000000ff 000099ad
1166 01:22:55.460834 T T T UDP wrong checksum 000000ff 00000fac
1167 01:22:55.493540 UDP wrong checksum 000000ff 0000a09e
1168 01:22:57.889070 UDP wrong checksum 00000005 0000775e
1169 01:23:12.895325 T T T
1170 01:23:12.895963 Retry count exceeded; starting again
1172 01:23:12.897451 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1175 01:23:12.899373 end: 2.4 uboot-commands (duration 00:01:52) [common]
1177 01:23:12.901008 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1179 01:23:12.902027 end: 2 uboot-action (duration 00:01:52) [common]
1181 01:23:12.903532 Cleaning after the job
1182 01:23:12.904098 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/ramdisk
1183 01:23:12.905514 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/kernel
1184 01:23:12.948972 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/dtb
1185 01:23:12.949752 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/nfsrootfs
1186 01:23:13.267281 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956209/tftp-deploy-uzqf_ib9/modules
1187 01:23:13.290593 start: 4.1 power-off (timeout 00:00:30) [common]
1188 01:23:13.291400 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1189 01:23:13.326658 >> OK - accepted request
1190 01:23:13.328849 Returned 0 in 0 seconds
1191 01:23:13.429817 end: 4.1 power-off (duration 00:00:00) [common]
1193 01:23:13.431089 start: 4.2 read-feedback (timeout 00:10:00) [common]
1194 01:23:13.431912 Listened to connection for namespace 'common' for up to 1s
1195 01:23:14.432850 Finalising connection for namespace 'common'
1196 01:23:14.433449 Disconnecting from shell: Finalise
1197 01:23:14.433806 =>
1198 01:23:14.534648 end: 4.2 read-feedback (duration 00:00:01) [common]
1199 01:23:14.535209 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/956209
1200 01:23:17.423203 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/956209
1201 01:23:17.423826 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.