Boot log: beaglebone-black
- Warnings: 3
- Kernel Warnings: 101
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 02:08:08.886445 lava-dispatcher, installed at version: 2024.01
2 02:08:08.887218 start: 0 validate
3 02:08:08.887692 Start time: 2024-11-06 02:08:08.887663+00:00 (UTC)
4 02:08:08.888235 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 02:08:08.888757 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 02:08:08.921227 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 02:08:08.921766 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 02:08:08.945972 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 02:08:08.946555 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 02:08:08.972196 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 02:08:08.972718 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 02:08:08.996041 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 02:08:08.996515 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:08:09.029489 validate duration: 0.14
16 02:08:09.030423 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:08:09.030746 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:08:09.031038 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:08:09.031639 Not decompressing ramdisk as can be used compressed.
20 02:08:09.032055 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 02:08:09.032319 saving as /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/ramdisk/initrd.cpio.gz
22 02:08:09.032606 total size: 4775763 (4 MB)
23 02:08:09.062860 progress 0 % (0 MB)
24 02:08:09.066577 progress 5 % (0 MB)
25 02:08:09.069804 progress 10 % (0 MB)
26 02:08:09.073006 progress 15 % (0 MB)
27 02:08:09.076674 progress 20 % (0 MB)
28 02:08:09.079826 progress 25 % (1 MB)
29 02:08:09.082981 progress 30 % (1 MB)
30 02:08:09.086520 progress 35 % (1 MB)
31 02:08:09.089620 progress 40 % (1 MB)
32 02:08:09.093013 progress 45 % (2 MB)
33 02:08:09.096133 progress 50 % (2 MB)
34 02:08:09.099659 progress 55 % (2 MB)
35 02:08:09.102815 progress 60 % (2 MB)
36 02:08:09.105941 progress 65 % (2 MB)
37 02:08:09.109448 progress 70 % (3 MB)
38 02:08:09.112653 progress 75 % (3 MB)
39 02:08:09.115816 progress 80 % (3 MB)
40 02:08:09.119009 progress 85 % (3 MB)
41 02:08:09.122512 progress 90 % (4 MB)
42 02:08:09.125452 progress 95 % (4 MB)
43 02:08:09.128316 progress 100 % (4 MB)
44 02:08:09.128937 4 MB downloaded in 0.10 s (47.29 MB/s)
45 02:08:09.129458 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:08:09.130350 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:08:09.130644 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:08:09.130914 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:08:09.131385 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 02:08:09.131633 saving as /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/kernel/zImage
52 02:08:09.131861 total size: 11444736 (10 MB)
53 02:08:09.132070 No compression specified
54 02:08:09.167425 progress 0 % (0 MB)
55 02:08:09.174894 progress 5 % (0 MB)
56 02:08:09.182381 progress 10 % (1 MB)
57 02:08:09.190075 progress 15 % (1 MB)
58 02:08:09.197338 progress 20 % (2 MB)
59 02:08:09.205218 progress 25 % (2 MB)
60 02:08:09.212317 progress 30 % (3 MB)
61 02:08:09.219899 progress 35 % (3 MB)
62 02:08:09.227177 progress 40 % (4 MB)
63 02:08:09.234830 progress 45 % (4 MB)
64 02:08:09.242135 progress 50 % (5 MB)
65 02:08:09.249764 progress 55 % (6 MB)
66 02:08:09.257146 progress 60 % (6 MB)
67 02:08:09.265252 progress 65 % (7 MB)
68 02:08:09.272528 progress 70 % (7 MB)
69 02:08:09.279673 progress 75 % (8 MB)
70 02:08:09.287346 progress 80 % (8 MB)
71 02:08:09.294396 progress 85 % (9 MB)
72 02:08:09.301855 progress 90 % (9 MB)
73 02:08:09.308994 progress 95 % (10 MB)
74 02:08:09.316052 progress 100 % (10 MB)
75 02:08:09.316536 10 MB downloaded in 0.18 s (59.11 MB/s)
76 02:08:09.317004 end: 1.2.1 http-download (duration 00:00:00) [common]
78 02:08:09.317837 end: 1.2 download-retry (duration 00:00:00) [common]
79 02:08:09.318122 start: 1.3 download-retry (timeout 00:10:00) [common]
80 02:08:09.318390 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 02:08:09.318845 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 02:08:09.319086 saving as /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/dtb/am335x-boneblack.dtb
83 02:08:09.319292 total size: 70568 (0 MB)
84 02:08:09.319500 No compression specified
85 02:08:09.352017 progress 46 % (0 MB)
86 02:08:09.352804 progress 92 % (0 MB)
87 02:08:09.353469 progress 100 % (0 MB)
88 02:08:09.353878 0 MB downloaded in 0.03 s (1.95 MB/s)
89 02:08:09.354337 end: 1.3.1 http-download (duration 00:00:00) [common]
91 02:08:09.355143 end: 1.3 download-retry (duration 00:00:00) [common]
92 02:08:09.355406 start: 1.4 download-retry (timeout 00:10:00) [common]
93 02:08:09.355668 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 02:08:09.356111 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 02:08:09.356352 saving as /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/nfsrootfs/full.rootfs.tar
96 02:08:09.356556 total size: 117747780 (112 MB)
97 02:08:09.356764 Using unxz to decompress xz
98 02:08:09.387848 progress 0 % (0 MB)
99 02:08:10.119202 progress 5 % (5 MB)
100 02:08:10.875622 progress 10 % (11 MB)
101 02:08:11.646372 progress 15 % (16 MB)
102 02:08:12.362063 progress 20 % (22 MB)
103 02:08:12.937149 progress 25 % (28 MB)
104 02:08:13.736208 progress 30 % (33 MB)
105 02:08:14.532456 progress 35 % (39 MB)
106 02:08:14.860017 progress 40 % (44 MB)
107 02:08:15.218270 progress 45 % (50 MB)
108 02:08:15.873279 progress 50 % (56 MB)
109 02:08:16.675809 progress 55 % (61 MB)
110 02:08:17.403200 progress 60 % (67 MB)
111 02:08:18.113533 progress 65 % (73 MB)
112 02:08:18.868019 progress 70 % (78 MB)
113 02:08:19.622468 progress 75 % (84 MB)
114 02:08:20.340865 progress 80 % (89 MB)
115 02:08:21.040885 progress 85 % (95 MB)
116 02:08:21.815791 progress 90 % (101 MB)
117 02:08:22.563364 progress 95 % (106 MB)
118 02:08:23.369752 progress 100 % (112 MB)
119 02:08:23.382056 112 MB downloaded in 14.03 s (8.01 MB/s)
120 02:08:23.383000 end: 1.4.1 http-download (duration 00:00:14) [common]
122 02:08:23.384603 end: 1.4 download-retry (duration 00:00:14) [common]
123 02:08:23.385119 start: 1.5 download-retry (timeout 00:09:46) [common]
124 02:08:23.385628 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 02:08:23.386480 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 02:08:23.386954 saving as /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/modules/modules.tar
127 02:08:23.387361 total size: 6607148 (6 MB)
128 02:08:23.387773 Using unxz to decompress xz
129 02:08:23.430139 progress 0 % (0 MB)
130 02:08:23.466318 progress 5 % (0 MB)
131 02:08:23.508827 progress 10 % (0 MB)
132 02:08:23.551218 progress 15 % (0 MB)
133 02:08:23.594529 progress 20 % (1 MB)
134 02:08:23.639946 progress 25 % (1 MB)
135 02:08:23.681936 progress 30 % (1 MB)
136 02:08:23.723479 progress 35 % (2 MB)
137 02:08:23.766017 progress 40 % (2 MB)
138 02:08:23.808236 progress 45 % (2 MB)
139 02:08:23.850673 progress 50 % (3 MB)
140 02:08:23.892693 progress 55 % (3 MB)
141 02:08:23.937924 progress 60 % (3 MB)
142 02:08:23.984551 progress 65 % (4 MB)
143 02:08:24.027707 progress 70 % (4 MB)
144 02:08:24.073204 progress 75 % (4 MB)
145 02:08:24.115603 progress 80 % (5 MB)
146 02:08:24.157942 progress 85 % (5 MB)
147 02:08:24.201154 progress 90 % (5 MB)
148 02:08:24.244543 progress 95 % (6 MB)
149 02:08:24.288152 progress 100 % (6 MB)
150 02:08:24.300783 6 MB downloaded in 0.91 s (6.90 MB/s)
151 02:08:24.301362 end: 1.5.1 http-download (duration 00:00:01) [common]
153 02:08:24.302709 end: 1.5 download-retry (duration 00:00:01) [common]
154 02:08:24.303306 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 02:08:24.303879 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 02:08:40.753663 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/943474/extract-nfsrootfs-wx0kno9x
157 02:08:40.754272 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 02:08:40.754558 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 02:08:40.755335 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08
160 02:08:40.755793 makedir: /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin
161 02:08:40.756120 makedir: /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/tests
162 02:08:40.756438 makedir: /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/results
163 02:08:40.756769 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-add-keys
164 02:08:40.757298 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-add-sources
165 02:08:40.757806 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-background-process-start
166 02:08:40.758404 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-background-process-stop
167 02:08:40.759008 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-common-functions
168 02:08:40.759511 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-echo-ipv4
169 02:08:40.759998 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-install-packages
170 02:08:40.760475 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-installed-packages
171 02:08:40.760948 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-os-build
172 02:08:40.761422 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-probe-channel
173 02:08:40.761937 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-probe-ip
174 02:08:40.762466 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-target-ip
175 02:08:40.762969 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-target-mac
176 02:08:40.763450 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-target-storage
177 02:08:40.763937 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-test-case
178 02:08:40.764416 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-test-event
179 02:08:40.764889 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-test-feedback
180 02:08:40.765364 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-test-raise
181 02:08:40.765850 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-test-reference
182 02:08:40.766380 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-test-runner
183 02:08:40.766893 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-test-set
184 02:08:40.767443 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-test-shell
185 02:08:40.767941 Updating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-add-keys (debian)
186 02:08:40.768478 Updating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-add-sources (debian)
187 02:08:40.768984 Updating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-install-packages (debian)
188 02:08:40.769485 Updating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-installed-packages (debian)
189 02:08:40.770006 Updating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/bin/lava-os-build (debian)
190 02:08:40.770454 Creating /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/environment
191 02:08:40.770822 LAVA metadata
192 02:08:40.771082 - LAVA_JOB_ID=943474
193 02:08:40.771293 - LAVA_DISPATCHER_IP=192.168.6.3
194 02:08:40.771652 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 02:08:40.772584 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 02:08:40.772892 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 02:08:40.773096 skipped lava-vland-overlay
198 02:08:40.773335 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 02:08:40.773585 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 02:08:40.773802 skipped lava-multinode-overlay
201 02:08:40.774067 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 02:08:40.774316 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 02:08:40.774565 Loading test definitions
204 02:08:40.774841 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 02:08:40.775073 Using /lava-943474 at stage 0
206 02:08:40.776159 uuid=943474_1.6.2.4.1 testdef=None
207 02:08:40.776464 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 02:08:40.776725 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 02:08:40.778289 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 02:08:40.779100 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 02:08:40.781046 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 02:08:40.781890 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 02:08:40.783717 runner path: /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/0/tests/0_timesync-off test_uuid 943474_1.6.2.4.1
216 02:08:40.784267 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 02:08:40.785075 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 02:08:40.785294 Using /lava-943474 at stage 0
220 02:08:40.785646 Fetching tests from https://github.com/kernelci/test-definitions.git
221 02:08:40.785962 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/0/tests/1_kselftest-dt'
222 02:08:44.147020 Running '/usr/bin/git checkout kernelci.org
223 02:08:44.328208 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 02:08:44.329683 uuid=943474_1.6.2.4.5 testdef=None
225 02:08:44.330110 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 02:08:44.330900 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 02:08:44.333957 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 02:08:44.334855 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 02:08:44.338871 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 02:08:44.339815 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 02:08:44.343724 runner path: /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/0/tests/1_kselftest-dt test_uuid 943474_1.6.2.4.5
235 02:08:44.344070 BOARD='beaglebone-black'
236 02:08:44.344291 BRANCH='clk'
237 02:08:44.344498 SKIPFILE='/dev/null'
238 02:08:44.344701 SKIP_INSTALL='True'
239 02:08:44.344900 TESTPROG_URL='http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 02:08:44.345133 TST_CASENAME=''
241 02:08:44.345338 TST_CMDFILES='dt'
242 02:08:44.346053 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 02:08:44.346922 Creating lava-test-runner.conf files
245 02:08:44.347144 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/943474/lava-overlay-52gy4k08/lava-943474/0 for stage 0
246 02:08:44.347563 - 0_timesync-off
247 02:08:44.347840 - 1_kselftest-dt
248 02:08:44.348225 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 02:08:44.348538 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 02:09:07.698312 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 02:09:07.698740 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 02:09:07.699032 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 02:09:07.699335 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 02:09:07.699624 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 02:09:08.048653 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 02:09:08.049126 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 02:09:08.049396 extracting modules file /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943474/extract-nfsrootfs-wx0kno9x
258 02:09:08.931033 extracting modules file /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943474/extract-overlay-ramdisk-oycq1om1/ramdisk
259 02:09:09.841997 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 02:09:09.842469 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 02:09:09.842720 [common] Applying overlay to NFS
262 02:09:09.842930 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943474/compress-overlay-cis9epvh/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/943474/extract-nfsrootfs-wx0kno9x
263 02:09:12.566089 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 02:09:12.566583 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 02:09:12.566860 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 02:09:12.567167 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 02:09:12.567426 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 02:09:12.567685 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 02:09:12.567934 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 02:09:12.568190 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 02:09:12.568416 Building ramdisk /var/lib/lava/dispatcher/tmp/943474/extract-overlay-ramdisk-oycq1om1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/943474/extract-overlay-ramdisk-oycq1om1/ramdisk
272 02:09:13.526252 >> 74887 blocks
273 02:09:18.066575 Adding RAMdisk u-boot header.
274 02:09:18.067284 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/943474/extract-overlay-ramdisk-oycq1om1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/943474/extract-overlay-ramdisk-oycq1om1/ramdisk.cpio.gz.uboot
275 02:09:18.225258 output: Image Name:
276 02:09:18.225692 output: Created: Wed Nov 6 02:09:18 2024
277 02:09:18.226215 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 02:09:18.226684 output: Data Size: 14791132 Bytes = 14444.46 KiB = 14.11 MiB
279 02:09:18.227140 output: Load Address: 00000000
280 02:09:18.227588 output: Entry Point: 00000000
281 02:09:18.228030 output:
282 02:09:18.229005 rename /var/lib/lava/dispatcher/tmp/943474/extract-overlay-ramdisk-oycq1om1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/ramdisk/ramdisk.cpio.gz.uboot
283 02:09:18.229832 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 02:09:18.230465 end: 1.6 prepare-tftp-overlay (duration 00:00:54) [common]
285 02:09:18.231062 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:51) [common]
286 02:09:18.231593 No LXC device requested
287 02:09:18.232158 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 02:09:18.232733 start: 1.8 deploy-device-env (timeout 00:08:51) [common]
289 02:09:18.233289 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 02:09:18.233753 Checking files for TFTP limit of 4294967296 bytes.
291 02:09:18.236722 end: 1 tftp-deploy (duration 00:01:09) [common]
292 02:09:18.237378 start: 2 uboot-action (timeout 00:05:00) [common]
293 02:09:18.238009 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 02:09:18.238584 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 02:09:18.239149 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 02:09:18.239980 substitutions:
297 02:09:18.240452 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 02:09:18.240902 - {DTB_ADDR}: 0x88000000
299 02:09:18.241349 - {DTB}: 943474/tftp-deploy-q65hl3yh/dtb/am335x-boneblack.dtb
300 02:09:18.241790 - {INITRD}: 943474/tftp-deploy-q65hl3yh/ramdisk/ramdisk.cpio.gz.uboot
301 02:09:18.242265 - {KERNEL_ADDR}: 0x82000000
302 02:09:18.242708 - {KERNEL}: 943474/tftp-deploy-q65hl3yh/kernel/zImage
303 02:09:18.243145 - {LAVA_MAC}: None
304 02:09:18.243632 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/943474/extract-nfsrootfs-wx0kno9x
305 02:09:18.244081 - {NFS_SERVER_IP}: 192.168.6.3
306 02:09:18.244525 - {PRESEED_CONFIG}: None
307 02:09:18.244966 - {PRESEED_LOCAL}: None
308 02:09:18.245403 - {RAMDISK_ADDR}: 0x83000000
309 02:09:18.245863 - {RAMDISK}: 943474/tftp-deploy-q65hl3yh/ramdisk/ramdisk.cpio.gz.uboot
310 02:09:18.246309 - {ROOT_PART}: None
311 02:09:18.246742 - {ROOT}: None
312 02:09:18.247174 - {SERVER_IP}: 192.168.6.3
313 02:09:18.247606 - {TEE_ADDR}: 0x83000000
314 02:09:18.248036 - {TEE}: None
315 02:09:18.248500 Parsed boot commands:
316 02:09:18.248926 - setenv autoload no
317 02:09:18.249357 - setenv initrd_high 0xffffffff
318 02:09:18.249792 - setenv fdt_high 0xffffffff
319 02:09:18.250356 - dhcp
320 02:09:18.250808 - setenv serverip 192.168.6.3
321 02:09:18.251246 - tftp 0x82000000 943474/tftp-deploy-q65hl3yh/kernel/zImage
322 02:09:18.251686 - tftp 0x83000000 943474/tftp-deploy-q65hl3yh/ramdisk/ramdisk.cpio.gz.uboot
323 02:09:18.252120 - setenv initrd_size ${filesize}
324 02:09:18.252552 - tftp 0x88000000 943474/tftp-deploy-q65hl3yh/dtb/am335x-boneblack.dtb
325 02:09:18.252986 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/943474/extract-nfsrootfs-wx0kno9x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 02:09:18.253432 - bootz 0x82000000 0x83000000 0x88000000
327 02:09:18.254029 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 02:09:18.255715 start: 2.3 connect-device (timeout 00:05:00) [common]
330 02:09:18.256187 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 02:09:18.271825 Setting prompt string to ['lava-test: # ']
332 02:09:18.273477 end: 2.3 connect-device (duration 00:00:00) [common]
333 02:09:18.274206 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 02:09:18.274849 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 02:09:18.275488 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 02:09:18.276791 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 02:09:18.311249 >> OK - accepted request
338 02:09:18.313088 Returned 0 in 0 seconds
339 02:09:18.414319 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 02:09:18.416112 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 02:09:18.416750 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 02:09:18.417334 Setting prompt string to ['Hit any key to stop autoboot']
344 02:09:18.417899 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 02:09:18.419640 Trying 192.168.56.22...
346 02:09:18.420175 Connected to conserv3.
347 02:09:18.420654 Escape character is '^]'.
348 02:09:18.421127
349 02:09:18.421596 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 02:09:18.422079
351 02:09:27.128520
352 02:09:27.135347 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 02:09:27.135862 Trying to boot from MMC1
354 02:09:31.188116
355 02:09:31.194769 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 02:09:31.195336 Trying to boot from MMC1
357 02:09:33.873659
358 02:09:33.880572 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 02:09:33.881018 Trying to boot from MMC1
360 02:09:34.464373
361 02:09:34.465022
362 02:09:34.469689 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 02:09:34.470236
364 02:09:34.470686 CPU : AM335X-GP rev 2.0
365 02:09:34.474969 Model: TI AM335x BeagleBone Black
366 02:09:34.475474 DRAM: 512 MiB
367 02:09:34.554623 Core: 160 devices, 18 uclasses, devicetree: separate
368 02:09:34.568596 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 02:09:34.968953 NAND: 0 MiB
370 02:09:34.979536 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 02:09:35.102094 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 02:09:35.123499 <ethaddr> not set. Validating first E-fuse MAC
373 02:09:35.153782 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 02:09:35.212150 Hit any key to stop autoboot: 2
376 02:09:35.212837 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 02:09:35.213189 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 02:09:35.213446 Setting prompt string to ['=>']
379 02:09:35.213712 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 02:09:35.222248 0
381 02:09:35.222893 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 02:09:35.223186 Sending with 10 millisecond of delay
384 02:09:36.357460 => setenv autoload no
385 02:09:36.368811 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 02:09:36.373841 setenv autoload no
387 02:09:36.374603 Sending with 10 millisecond of delay
389 02:09:38.172284 => setenv initrd_high 0xffffffff
390 02:09:38.182787 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 02:09:38.183448 setenv initrd_high 0xffffffff
392 02:09:38.184294 Sending with 10 millisecond of delay
394 02:09:39.803301 => setenv fdt_high 0xffffffff
395 02:09:39.814079 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 02:09:39.814949 setenv fdt_high 0xffffffff
397 02:09:39.815866 Sending with 10 millisecond of delay
399 02:09:40.107829 => dhcp
400 02:09:40.118606 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 02:09:40.119470 dhcp
402 02:09:40.119943 link up on port 0, speed 100, full duplex
403 02:09:40.120391 BOOTP broadcast 1
404 02:09:40.372504 BOOTP broadcast 2
405 02:09:40.875395 BOOTP broadcast 3
406 02:09:41.877402 BOOTP broadcast 4
407 02:09:43.879335 BOOTP broadcast 5
408 02:09:43.963773 DHCP client bound to address 192.168.6.8 (3840 ms)
409 02:09:43.964654 Sending with 10 millisecond of delay
411 02:09:45.641574 => setenv serverip 192.168.6.3
412 02:09:45.652485 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
413 02:09:45.653386 setenv serverip 192.168.6.3
414 02:09:45.654203 Sending with 10 millisecond of delay
416 02:09:49.137708 => tftp 0x82000000 943474/tftp-deploy-q65hl3yh/kernel/zImage
417 02:09:49.148624 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
418 02:09:49.149642 tftp 0x82000000 943474/tftp-deploy-q65hl3yh/kernel/zImage
419 02:09:49.150158 link up on port 0, speed 100, full duplex
420 02:09:49.153256 Using ethernet@4a100000 device
421 02:09:49.158799 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
422 02:09:49.166245 Filename '943474/tftp-deploy-q65hl3yh/kernel/zImage'.
423 02:09:49.166840 Load address: 0x82000000
424 02:09:51.196220 Loading: *################################################## 10.9 MiB
425 02:09:51.196846 5.4 MiB/s
426 02:09:51.197290 done
427 02:09:51.200681 Bytes transferred = 11444736 (aea200 hex)
428 02:09:51.201420 Sending with 10 millisecond of delay
430 02:09:55.657693 => tftp 0x83000000 943474/tftp-deploy-q65hl3yh/ramdisk/ramdisk.cpio.gz.uboot
431 02:09:55.668579 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
432 02:09:55.669523 tftp 0x83000000 943474/tftp-deploy-q65hl3yh/ramdisk/ramdisk.cpio.gz.uboot
433 02:09:55.670040 link up on port 0, speed 100, full duplex
434 02:09:55.673481 Using ethernet@4a100000 device
435 02:09:55.679271 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
436 02:09:55.682509 Filename '943474/tftp-deploy-q65hl3yh/ramdisk/ramdisk.cpio.gz.uboot'.
437 02:09:55.687415 Load address: 0x83000000
438 02:09:58.126117 Loading: *################################################## 14.1 MiB
439 02:09:58.126764 5.8 MiB/s
440 02:09:58.127221 done
441 02:09:58.130215 Bytes transferred = 14791196 (e1b21c hex)
442 02:09:58.131005 Sending with 10 millisecond of delay
444 02:09:59.990338 => setenv initrd_size ${filesize}
445 02:10:00.000929 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
446 02:10:00.001522 setenv initrd_size ${filesize}
447 02:10:00.001984 Sending with 10 millisecond of delay
449 02:10:04.148346 => tftp 0x88000000 943474/tftp-deploy-q65hl3yh/dtb/am335x-boneblack.dtb
450 02:10:04.159131 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
451 02:10:04.159996 tftp 0x88000000 943474/tftp-deploy-q65hl3yh/dtb/am335x-boneblack.dtb
452 02:10:04.160419 link up on port 0, speed 100, full duplex
453 02:10:04.163634 Using ethernet@4a100000 device
454 02:10:04.169263 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
455 02:10:04.179779 Filename '943474/tftp-deploy-q65hl3yh/dtb/am335x-boneblack.dtb'.
456 02:10:04.180308 Load address: 0x88000000
457 02:10:04.189599 Loading: *################################################## 68.9 KiB
458 02:10:04.190110 5.2 MiB/s
459 02:10:04.198152 done
460 02:10:04.198640 Bytes transferred = 70568 (113a8 hex)
461 02:10:04.199308 Sending with 10 millisecond of delay
463 02:10:17.383787 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/943474/extract-nfsrootfs-wx0kno9x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
464 02:10:17.394574 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
465 02:10:17.395432 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/943474/extract-nfsrootfs-wx0kno9x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
466 02:10:17.396136 Sending with 10 millisecond of delay
468 02:10:19.738271 => bootz 0x82000000 0x83000000 0x88000000
469 02:10:19.749064 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
470 02:10:19.749572 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
471 02:10:19.750608 bootz 0x82000000 0x83000000 0x88000000
472 02:10:19.751052 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
473 02:10:19.751539 ## Loading init Ramdisk from Legacy Image at 83000000 ...
474 02:10:19.756628 Image Name:
475 02:10:19.757063 Created: 2024-11-06 2:09:18 UTC
476 02:10:19.762187 Image Type: ARM Linux RAMDisk Image (uncompressed)
477 02:10:19.767772 Data Size: 14791132 Bytes = 14.1 MiB
478 02:10:19.768201 Load Address: 00000000
479 02:10:19.773952 Entry Point: 00000000
480 02:10:19.942303 Verifying Checksum ... OK
481 02:10:19.942875 ## Flattened Device Tree blob at 88000000
482 02:10:19.948783 Booting using the fdt blob at 0x88000000
483 02:10:19.949216 Working FDT set to 88000000
484 02:10:19.954484 Using Device Tree in place at 88000000, end 880143a7
485 02:10:19.957890 Working FDT set to 88000000
486 02:10:19.972303
487 02:10:19.972749 Starting kernel ...
488 02:10:19.973152
489 02:10:19.974036 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
490 02:10:19.974626 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
491 02:10:19.975099 Setting prompt string to ['Linux version [0-9]']
492 02:10:19.975550 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
493 02:10:19.976008 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
494 02:10:20.817782 [ 0.000000] Booting Linux on physical CPU 0x0
495 02:10:20.826118 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
496 02:10:20.826580 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
497 02:10:20.826898 Setting prompt string to []
498 02:10:20.827306 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
499 02:10:20.827721 Using line separator: #'\n'#
500 02:10:20.828061 No login prompt set.
501 02:10:20.828555 Parsing kernel messages
502 02:10:20.829170 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
503 02:10:20.830002 [login-action] Waiting for messages, (timeout 00:03:57)
504 02:10:20.830571 Waiting using forced prompt support (timeout 00:01:59)
505 02:10:20.838250 [ 0.000000] Linux version 6.12.0-rc1 (KernelCI@build-j364117-arm-gcc-12-multi-v7-defconfig-bfk57) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Wed Nov 6 01:41:51 UTC 2024
506 02:10:20.847133 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
507 02:10:20.850250 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
508 02:10:20.855827 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
509 02:10:20.867333 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
510 02:10:20.870413 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
511 02:10:20.877438 [ 0.000000] Memory policy: Data cache writeback
512 02:10:20.877898 [ 0.000000] efi: UEFI not found.
513 02:10:20.885892 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
514 02:10:20.891553 [ 0.000000] Zone ranges:
515 02:10:20.897194 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
516 02:10:20.897532 [ 0.000000] Normal empty
517 02:10:20.902996 [ 0.000000] HighMem empty
518 02:10:20.908618 [ 0.000000] Movable zone start for each node
519 02:10:20.908953 [ 0.000000] Early memory node ranges
520 02:10:20.914747 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
521 02:10:20.924152 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
522 02:10:20.949870 [ 0.000000] CPU: All CPU(s) started in SVC mode.
523 02:10:20.955412 [ 0.000000] AM335X ES2.0 (sgx neon)
524 02:10:20.967104 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
525 02:10:20.984746 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/943474/extract-nfsrootfs-wx0kno9x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
526 02:10:20.996332 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
527 02:10:21.002080 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
528 02:10:21.007890 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
529 02:10:21.017889 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
530 02:10:21.046876 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
531 02:10:21.052815 <6>[ 0.000000] trace event string verifier disabled
532 02:10:21.053196 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
533 02:10:21.060946 <6>[ 0.000000] rcu: RCU event tracing is enabled.
534 02:10:21.066609 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
535 02:10:21.078029 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
536 02:10:21.082993 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
537 02:10:21.098056 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
538 02:10:21.115042 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
539 02:10:21.121750 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
540 02:10:21.213391 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
541 02:10:21.224847 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
542 02:10:21.231710 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
543 02:10:21.244696 <6>[ 0.019143] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
544 02:10:21.251857 <6>[ 0.033920] Console: colour dummy device 80x30
545 02:10:21.257922 Matched prompt #6: WARNING:
546 02:10:21.258280 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
547 02:10:21.263468 <3>[ 0.038814] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
548 02:10:21.269173 <3>[ 0.045886] This ensures that you still see kernel messages. Please
549 02:10:21.272431 <3>[ 0.052613] update your kernel commandline.
550 02:10:21.313121 <6>[ 0.057228] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
551 02:10:21.318863 <6>[ 0.096153] CPU: Testing write buffer coherency: ok
552 02:10:21.324738 <6>[ 0.101519] CPU0: Spectre v2: using BPIALL workaround
553 02:10:21.325071 <6>[ 0.106982] pid_max: default: 32768 minimum: 301
554 02:10:21.336228 <6>[ 0.112174] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 02:10:21.343115 <6>[ 0.119997] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
556 02:10:21.349849 <6>[ 0.129345] CPU0: thread -1, cpu 0, socket -1, mpidr 0
557 02:10:21.411033 <6>[ 0.189533] Setting up static identity map for 0x80300000 - 0x803000ac
558 02:10:21.417232 <6>[ 0.199124] rcu: Hierarchical SRCU implementation.
559 02:10:21.425293 <6>[ 0.204412] rcu: Max phase no-delay instances is 1000.
560 02:10:21.433757 <6>[ 0.215402] EFI services will not be available.
561 02:10:21.439481 <6>[ 0.220756] smp: Bringing up secondary CPUs ...
562 02:10:21.445357 <6>[ 0.225724] smp: Brought up 1 node, 1 CPU
563 02:10:21.451032 <6>[ 0.230209] SMP: Total of 1 processors activated (996.14 BogoMIPS).
564 02:10:21.456966 <6>[ 0.236931] CPU: All CPU(s) started in SVC mode.
565 02:10:21.477418 <6>[ 0.242130] Memory: 405996K/522240K available (16384K kernel code, 2542K rwdata, 6788K rodata, 2048K init, 431K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
566 02:10:21.478083 <6>[ 0.258404] devtmpfs: initialized
567 02:10:21.499805 <6>[ 0.275699] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
568 02:10:21.511311 <6>[ 0.284299] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
569 02:10:21.517327 <6>[ 0.294744] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
570 02:10:21.527098 <6>[ 0.307025] pinctrl core: initialized pinctrl subsystem
571 02:10:21.537256 <6>[ 0.317647] DMI not present or invalid.
572 02:10:21.545589 <6>[ 0.323496] NET: Registered PF_NETLINK/PF_ROUTE protocol family
573 02:10:21.555059 <6>[ 0.332420] DMA: preallocated 256 KiB pool for atomic coherent allocations
574 02:10:21.570227 <6>[ 0.343850] thermal_sys: Registered thermal governor 'step_wise'
575 02:10:21.570783 <6>[ 0.344023] cpuidle: using governor menu
576 02:10:21.597749 <6>[ 0.379733] No ATAGs?
577 02:10:21.603949 <6>[ 0.382376] hw-breakpoint: debug architecture 0x4 unsupported.
578 02:10:21.614215 <6>[ 0.394245] Serial: AMBA PL011 UART driver
579 02:10:21.643666 <6>[ 0.425414] iommu: Default domain type: Translated
580 02:10:21.651654 <6>[ 0.430763] iommu: DMA domain TLB invalidation policy: strict mode
581 02:10:21.680373 <5>[ 0.460818] SCSI subsystem initialized
582 02:10:21.693944 <6>[ 0.470239] usbcore: registered new interface driver usbfs
583 02:10:21.700815 <6>[ 0.476197] usbcore: registered new interface driver hub
584 02:10:21.701310 <6>[ 0.482021] usbcore: registered new device driver usb
585 02:10:21.708418 <6>[ 0.488505] pps_core: LinuxPPS API ver. 1 registered
586 02:10:21.719845 <6>[ 0.493938] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
587 02:10:21.726863 <6>[ 0.503641] PTP clock support registered
588 02:10:21.727378 <6>[ 0.508081] EDAC MC: Ver: 3.0.0
589 02:10:21.773345 <6>[ 0.553527] scmi_core: SCMI protocol bus registered
590 02:10:21.798760 <6>[ 0.579986] vgaarb: loaded
591 02:10:21.804782 <6>[ 0.583752] clocksource: Switched to clocksource dmtimer
592 02:10:21.829012 <6>[ 0.610624] NET: Registered PF_INET protocol family
593 02:10:21.841654 <6>[ 0.616323] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
594 02:10:21.847369 <6>[ 0.625167] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
595 02:10:21.858784 <6>[ 0.634099] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
596 02:10:21.864622 <6>[ 0.642340] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
597 02:10:21.876204 <6>[ 0.650626] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
598 02:10:21.882085 <6>[ 0.658346] TCP: Hash tables configured (established 4096 bind 4096)
599 02:10:21.887798 <6>[ 0.665267] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
600 02:10:21.893849 <6>[ 0.672279] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
601 02:10:21.901270 <6>[ 0.679892] NET: Registered PF_UNIX/PF_LOCAL protocol family
602 02:10:21.987266 <6>[ 0.763450] RPC: Registered named UNIX socket transport module.
603 02:10:21.987887 <6>[ 0.769886] RPC: Registered udp transport module.
604 02:10:21.992995 <6>[ 0.775011] RPC: Registered tcp transport module.
605 02:10:21.998794 <6>[ 0.780117] RPC: Registered tcp-with-tls transport module.
606 02:10:22.011798 <6>[ 0.786045] RPC: Registered tcp NFSv4.1 backchannel transport module.
607 02:10:22.012415 <6>[ 0.792954] PCI: CLS 0 bytes, default 64
608 02:10:22.019097 <5>[ 0.798728] Initialise system trusted keyrings
609 02:10:22.039921 <6>[ 0.818867] Trying to unpack rootfs image as initramfs...
610 02:10:22.119018 <6>[ 0.894730] workingset: timestamp_bits=30 max_order=17 bucket_order=0
611 02:10:22.123804 <6>[ 0.902247] squashfs: version 4.0 (2009/01/31) Phillip Lougher
612 02:10:22.162597 <5>[ 0.944474] NFS: Registering the id_resolver key type
613 02:10:22.168324 <5>[ 0.950076] Key type id_resolver registered
614 02:10:22.174266 <5>[ 0.954764] Key type id_legacy registered
615 02:10:22.182444 <6>[ 0.959203] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
616 02:10:22.188719 <6>[ 0.966404] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
617 02:10:22.258566 <5>[ 1.040564] Key type asymmetric registered
618 02:10:22.264327 <5>[ 1.045153] Asymmetric key parser 'x509' registered
619 02:10:22.275826 <6>[ 1.050581] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
620 02:10:22.276380 <6>[ 1.058501] io scheduler mq-deadline registered
621 02:10:22.281643 <6>[ 1.063433] io scheduler kyber registered
622 02:10:22.287219 <6>[ 1.067924] io scheduler bfq registered
623 02:10:22.391845 <6>[ 1.170269] ledtrig-cpu: registered to indicate activity on CPUs
624 02:10:22.657588 <6>[ 1.435689] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
625 02:10:22.686978 <6>[ 1.468785] msm_serial: driver initialized
626 02:10:22.693072 <6>[ 1.473564] SuperH (H)SCI(F) driver initialized
627 02:10:22.699034 <6>[ 1.478922] STMicroelectronics ASC driver initialized
628 02:10:22.704193 <6>[ 1.484607] STM32 USART driver initialized
629 02:10:22.818949 <6>[ 1.600263] brd: module loaded
630 02:10:22.853549 <6>[ 1.635802] loop: module loaded
631 02:10:22.880015 <6>[ 1.661089] CAN device driver interface
632 02:10:22.886510 <6>[ 1.666388] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
633 02:10:22.892312 <6>[ 1.673284] e1000e: Intel(R) PRO/1000 Network Driver
634 02:10:22.898176 <6>[ 1.678750] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
635 02:10:22.903922 <6>[ 1.685192] igb: Intel(R) Gigabit Ethernet Network Driver
636 02:10:22.911176 <6>[ 1.691015] igb: Copyright (c) 2007-2014 Intel Corporation.
637 02:10:22.923844 <6>[ 1.700145] pegasus: Pegasus/Pegasus II USB Ethernet driver
638 02:10:22.929631 <6>[ 1.706297] usbcore: registered new interface driver pegasus
639 02:10:22.935436 <6>[ 1.712420] usbcore: registered new interface driver asix
640 02:10:22.941233 <6>[ 1.718313] usbcore: registered new interface driver ax88179_178a
641 02:10:22.946981 <6>[ 1.724924] usbcore: registered new interface driver cdc_ether
642 02:10:22.952836 <6>[ 1.731223] usbcore: registered new interface driver smsc75xx
643 02:10:22.958538 <6>[ 1.737456] usbcore: registered new interface driver smsc95xx
644 02:10:22.964345 <6>[ 1.743676] usbcore: registered new interface driver net1080
645 02:10:22.970142 <6>[ 1.749823] usbcore: registered new interface driver cdc_subset
646 02:10:22.975936 <6>[ 1.756234] usbcore: registered new interface driver zaurus
647 02:10:22.983560 <6>[ 1.762279] usbcore: registered new interface driver cdc_ncm
648 02:10:22.993345 <6>[ 1.771647] usbcore: registered new interface driver usb-storage
649 02:10:23.280404 <6>[ 2.060474] i2c_dev: i2c /dev entries driver
650 02:10:23.331619 <5>[ 2.110138] cpuidle: enable-method property 'ti,am3352' found operations
651 02:10:23.345139 <6>[ 2.119748] sdhci: Secure Digital Host Controller Interface driver
652 02:10:23.345752 <6>[ 2.126522] sdhci: Copyright(c) Pierre Ossman
653 02:10:23.352018 <6>[ 2.132877] Synopsys Designware Multimedia Card Interface Driver
654 02:10:23.362035 <6>[ 2.140787] sdhci-pltfm: SDHCI platform and OF driver helper
655 02:10:23.483021 <6>[ 2.257539] usbcore: registered new interface driver usbhid
656 02:10:23.483683 <6>[ 2.263579] usbhid: USB HID core driver
657 02:10:23.530970 <6>[ 2.310318] NET: Registered PF_INET6 protocol family
658 02:10:23.567021 <6>[ 2.349067] Segment Routing with IPv6
659 02:10:23.573008 <6>[ 2.353209] In-situ OAM (IOAM) with IPv6
660 02:10:23.579713 <6>[ 2.357729] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
661 02:10:23.585355 <6>[ 2.365005] NET: Registered PF_PACKET protocol family
662 02:10:23.591193 <6>[ 2.370492] can: controller area network core
663 02:10:23.596986 <6>[ 2.375374] NET: Registered PF_CAN protocol family
664 02:10:23.597511 <6>[ 2.380577] can: raw protocol
665 02:10:23.602867 <6>[ 2.383936] can: broadcast manager protocol
666 02:10:23.609305 <6>[ 2.388518] can: netlink gateway - max_hops=1
667 02:10:23.615320 <5>[ 2.394061] Key type dns_resolver registered
668 02:10:23.621609 <6>[ 2.399053] ThumbEE CPU extension supported.
669 02:10:23.622276 <5>[ 2.403813] Registering SWP/SWPB emulation handler
670 02:10:23.631360 <3>[ 2.409459] omap_voltage_late_init: Voltage driver support not added
671 02:10:23.824644 <5>[ 2.604101] Loading compiled-in X.509 certificates
672 02:10:23.963751 <6>[ 2.732711] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
673 02:10:23.970829 <6>[ 2.749369] pinctrl-single 44e10800.pinmux: 142 pins, size 568
674 02:10:23.997021 <3>[ 2.772960] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
675 02:10:24.190790 <3>[ 2.966724] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
676 02:10:24.393873 <6>[ 3.174051] OMAP GPIO hardware version 0.1
677 02:10:24.414247 <6>[ 3.192572] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
678 02:10:24.506702 <4>[ 3.285720] at24 2-0054: supply vcc not found, using dummy regulator
679 02:10:24.566639 <4>[ 3.344963] at24 2-0055: supply vcc not found, using dummy regulator
680 02:10:24.611551 <4>[ 3.389636] at24 2-0056: supply vcc not found, using dummy regulator
681 02:10:24.658160 <4>[ 3.436283] at24 2-0057: supply vcc not found, using dummy regulator
682 02:10:24.690021 <6>[ 3.468864] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
683 02:10:24.764138 <3>[ 3.539749] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
684 02:10:24.789028 <6>[ 3.560533] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
685 02:10:24.808862 <4>[ 3.586602] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
686 02:10:24.826955 <4>[ 3.604629] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
687 02:10:24.966203 <6>[ 3.744332] omap_rng 48310000.rng: Random Number Generator ver. 20
688 02:10:24.988592 <5>[ 3.770319] random: crng init done
689 02:10:25.049262 <6>[ 3.831085] Freeing initrd memory: 14448K
690 02:10:25.059128 <6>[ 3.835752] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
691 02:10:25.111201 <6>[ 3.886185] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
692 02:10:25.116212 <4>[ 3.896517] ------------[ cut here ]------------
693 02:10:25.128318 <4>[ 3.901555] WARNING: CPU: 0 PID: 38 at drivers/base/regmap/regmap.c:1208 devm_regmap_field_alloc+0xb8/0xc4
694 02:10:25.133551 <4>[ 3.911858] invalid empty mask defined
695 02:10:25.134112 <4>[ 3.916002] Modules linked in:
696 02:10:25.139298 <4>[ 3.919425] CPU: 0 UID: 0 PID: 38 Comm: kworker/u4:4 Not tainted 6.12.0-rc1 #1
697 02:10:25.150671 <4>[ 3.927126] Hardware name: Generic AM33XX (Flattened Device Tree)
698 02:10:25.156491 <4>[ 3.933663] Workqueue: events_unbound deferred_probe_work_func
699 02:10:25.157011 <4>[ 3.939945] Call trace:
700 02:10:25.162280 <4>[ 3.939965] unwind_backtrace from show_stack+0x10/0x14
701 02:10:25.168025 <4>[ 3.948494] show_stack from dump_stack_lvl+0x68/0x74
702 02:10:25.173896 <4>[ 3.953974] dump_stack_lvl from __warn+0x7c/0x12c
703 02:10:25.179601 <4>[ 3.959188] __warn from warn_slowpath_fmt+0x124/0x190
704 02:10:25.185296 <4>[ 3.964751] warn_slowpath_fmt from devm_regmap_field_alloc+0xb8/0xc4
705 02:10:25.190998 <4>[ 3.971659] devm_regmap_field_alloc from cpsw_ale_create+0x124/0x368
706 02:10:25.202479 <4>[ 3.978581] cpsw_ale_create from cpsw_init_common+0x238/0x37c
707 02:10:25.208319 <4>[ 3.984859] cpsw_init_common from cpsw_probe+0x530/0xc60
708 02:10:25.213948 <4>[ 3.990691] cpsw_probe from platform_probe+0x5c/0xb0
709 02:10:25.219659 <4>[ 3.996173] platform_probe from really_probe+0xc8/0x2c8
710 02:10:25.225362 <4>[ 4.001917] really_probe from __driver_probe_device+0x88/0x19c
711 02:10:25.231268 <4>[ 4.008282] __driver_probe_device from driver_probe_device+0x30/0x104
712 02:10:25.236867 <4>[ 4.015272] driver_probe_device from __device_attach_driver+0x94/0x108
713 02:10:25.242617 <4>[ 4.022352] __device_attach_driver from bus_for_each_drv+0x90/0xe4
714 02:10:25.248334 <4>[ 4.029075] bus_for_each_drv from __device_attach+0xa8/0x1a4
715 02:10:25.254084 <4>[ 4.035261] __device_attach from bus_probe_device+0x88/0x8c
716 02:10:25.259909 <4>[ 4.041359] bus_probe_device from device_add+0x5a8/0x77c
717 02:10:25.271325 <4>[ 4.047188] device_add from of_platform_device_create_pdata+0x90/0xbc
718 02:10:25.277098 <4>[ 4.054188] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
719 02:10:25.282802 <4>[ 4.062433] of_platform_bus_create from of_platform_populate+0x70/0xd4
720 02:10:25.288542 <4>[ 4.069514] of_platform_populate from sysc_probe+0x100c/0x1418
721 02:10:25.294244 <4>[ 4.075887] sysc_probe from platform_probe+0x5c/0xb0
722 02:10:25.299992 <4>[ 4.081359] platform_probe from really_probe+0xc8/0x2c8
723 02:10:25.305834 <4>[ 4.087100] really_probe from __driver_probe_device+0x88/0x19c
724 02:10:25.317175 <4>[ 4.093465] __driver_probe_device from driver_probe_device+0x30/0x104
725 02:10:25.322968 <4>[ 4.100455] driver_probe_device from __device_attach_driver+0x94/0x108
726 02:10:25.328690 <4>[ 4.107535] __device_attach_driver from bus_for_each_drv+0x90/0xe4
727 02:10:25.334608 <4>[ 4.114258] bus_for_each_drv from __device_attach+0xa8/0x1a4
728 02:10:25.340259 <4>[ 4.120441] __device_attach from bus_probe_device+0x88/0x8c
729 02:10:25.345882 <4>[ 4.126539] bus_probe_device from device_add+0x5a8/0x77c
730 02:10:25.351588 <4>[ 4.132367] device_add from of_platform_device_create_pdata+0x90/0xbc
731 02:10:25.363072 <4>[ 4.139354] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
732 02:10:25.368902 <4>[ 4.147597] of_platform_bus_create from of_platform_populate+0x70/0xd4
733 02:10:25.374681 <4>[ 4.154680] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
734 02:10:25.380260 <4>[ 4.161491] simple_pm_bus_probe from platform_probe+0x5c/0xb0
735 02:10:25.386099 <4>[ 4.167767] platform_probe from really_probe+0xc8/0x2c8
736 02:10:25.397435 <4>[ 4.173507] really_probe from __driver_probe_device+0x88/0x19c
737 02:10:25.403179 <4>[ 4.179871] __driver_probe_device from driver_probe_device+0x30/0x104
738 02:10:25.408964 <4>[ 4.186862] driver_probe_device from __device_attach_driver+0x94/0x108
739 02:10:25.414671 <4>[ 4.193941] __device_attach_driver from bus_for_each_drv+0x90/0xe4
740 02:10:25.420420 <4>[ 4.200662] bus_for_each_drv from __device_attach+0xa8/0x1a4
741 02:10:25.426177 <4>[ 4.206846] __device_attach from bus_probe_device+0x88/0x8c
742 02:10:25.431853 <4>[ 4.212943] bus_probe_device from device_add+0x5a8/0x77c
743 02:10:25.443282 <4>[ 4.218769] device_add from of_platform_device_create_pdata+0x90/0xbc
744 02:10:25.449195 <4>[ 4.225759] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
745 02:10:25.454832 <4>[ 4.234003] of_platform_bus_create from of_platform_populate+0x70/0xd4
746 02:10:25.460555 <4>[ 4.241087] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
747 02:10:25.466378 <4>[ 4.247898] simple_pm_bus_probe from platform_probe+0x5c/0xb0
748 02:10:25.472044 <4>[ 4.254173] platform_probe from really_probe+0xc8/0x2c8
749 02:10:25.483508 <4>[ 4.259915] really_probe from __driver_probe_device+0x88/0x19c
750 02:10:25.489226 <4>[ 4.266279] __driver_probe_device from driver_probe_device+0x30/0x104
751 02:10:25.495179 <4>[ 4.273270] driver_probe_device from __device_attach_driver+0x94/0x108
752 02:10:25.500809 <4>[ 4.280347] __device_attach_driver from bus_for_each_drv+0x90/0xe4
753 02:10:25.506512 <4>[ 4.287069] bus_for_each_drv from __device_attach+0xa8/0x1a4
754 02:10:25.512229 <4>[ 4.293255] __device_attach from bus_probe_device+0x88/0x8c
755 02:10:25.518005 <4>[ 4.299352] bus_probe_device from device_add+0x5a8/0x77c
756 02:10:25.529381 <4>[ 4.305179] device_add from of_platform_device_create_pdata+0x90/0xbc
757 02:10:25.535213 <4>[ 4.312168] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
758 02:10:25.540861 <4>[ 4.320411] of_platform_bus_create from of_platform_populate+0x70/0xd4
759 02:10:25.546630 <4>[ 4.327491] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
760 02:10:25.558116 <4>[ 4.334302] simple_pm_bus_probe from platform_probe+0x5c/0xb0
761 02:10:25.563860 <4>[ 4.340578] platform_probe from really_probe+0xc8/0x2c8
762 02:10:25.569549 <4>[ 4.346320] really_probe from __driver_probe_device+0x88/0x19c
763 02:10:25.575321 <4>[ 4.352686] __driver_probe_device from driver_probe_device+0x30/0x104
764 02:10:25.581076 <4>[ 4.359677] driver_probe_device from __device_attach_driver+0x94/0x108
765 02:10:25.586772 <4>[ 4.366758] __device_attach_driver from bus_for_each_drv+0x90/0xe4
766 02:10:25.592514 <4>[ 4.373477] bus_for_each_drv from __device_attach+0xa8/0x1a4
767 02:10:25.598249 <4>[ 4.379663] __device_attach from bus_probe_device+0x88/0x8c
768 02:10:25.609705 <4>[ 4.385759] bus_probe_device from deferred_probe_work_func+0x78/0xa4
769 02:10:25.615492 <4>[ 4.392659] deferred_probe_work_func from process_one_work+0x178/0x3c0
770 02:10:25.621232 <4>[ 4.399753] process_one_work from worker_thread+0x264/0x42c
771 02:10:25.626966 <4>[ 4.405858] worker_thread from kthread+0xe0/0xfc
772 02:10:25.632666 <4>[ 4.410986] kthread from ret_from_fork+0x14/0x28
773 02:10:25.638468 <4>[ 4.416101] Exception stack(0xe0131fb0 to 0xe0131ff8)
774 02:10:25.644263 <4>[ 4.421566] 1fa0: 00000000 00000000 00000000 00000000
775 02:10:25.655644 <4>[ 4.430246] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
776 02:10:25.661537 <4>[ 4.438927] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
777 02:10:25.667297 <4>[ 4.446115] ---[ end trace 0000000000000000 ]---
778 02:10:25.668362 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
779 02:10:25.668893 login-action: kernel 'warning'
780 02:10:25.669344 [login-action] Waiting for messages, (timeout 00:03:53)
781 02:10:25.669776 Waiting using forced prompt support (timeout 00:01:56)
782 02:10:25.673128 <6>[ 4.451210] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
783 02:10:25.679276 <6>[ 4.458500] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
784 02:10:25.690743 <6>[ 4.466109] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
785 02:10:25.702297 <6>[ 4.474247] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
786 02:10:25.709841 <6>[ 4.485881] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
787 02:10:25.720672 <5>[ 4.494960] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
788 02:10:25.748138 <3>[ 4.524556] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
789 02:10:25.753045 <6>[ 4.533020] edma 49000000.dma: TI EDMA DMA engine driver
790 02:10:25.824522 <3>[ 4.600193] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
791 02:10:25.839395 <6>[ 4.614637] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
792 02:10:25.852293 <3>[ 4.631711] l3-aon-clkctrl:0000:0: failed to disable
793 02:10:25.905957 <6>[ 4.682195] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
794 02:10:25.911705 <6>[ 4.691702] printk: legacy console [ttyS0] enabled
795 02:10:25.917384 <6>[ 4.691702] printk: legacy console [ttyS0] enabled
796 02:10:25.923002 <6>[ 4.702037] printk: legacy bootconsole [omap8250] disabled
797 02:10:25.929030 <6>[ 4.702037] printk: legacy bootconsole [omap8250] disabled
798 02:10:25.959406 <4>[ 4.734605] tps65217-pmic: Failed to locate of_node [id: -1]
799 02:10:25.963034 <4>[ 4.742003] tps65217-bl: Failed to locate of_node [id: -1]
800 02:10:25.979378 <6>[ 4.761629] tps65217 0-0024: TPS65217 ID 0xe version 1.2
801 02:10:25.999797 <6>[ 4.768590] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
802 02:10:26.011584 <6>[ 4.782280] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
803 02:10:26.014381 <6>[ 4.794162] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
804 02:10:26.037337 <6>[ 4.814060] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
805 02:10:26.043332 <6>[ 4.823114] sdhci-omap 48060000.mmc: Got CD GPIO
806 02:10:26.051458 <4>[ 4.828308] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
807 02:10:26.067849 <4>[ 4.842047] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
808 02:10:26.074468 <4>[ 4.852355] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
809 02:10:26.083598 <4>[ 4.861340] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
810 02:10:26.180440 <6>[ 4.958973] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
811 02:10:26.231141 <6>[ 5.007176] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
812 02:10:26.237695 <6>[ 5.015762] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
813 02:10:26.245933 <6>[ 5.024660] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
814 02:10:26.311975 <6>[ 5.091445] mmc1: new high speed MMC card at address 0001
815 02:10:26.319269 <6>[ 5.100119] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
816 02:10:26.337527 <6>[ 5.112300] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
817 02:10:26.344924 <6>[ 5.125577] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
818 02:10:26.361348 <6>[ 5.140987] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
819 02:10:26.373929 <6>[ 5.149916] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
820 02:10:26.381745 <6>[ 5.157112] mmc0: new high speed SDHC card at address aaaa
821 02:10:26.382935 <6>[ 5.165071] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
822 02:10:26.415329 <6>[ 5.195229] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
823 02:10:28.458461 <6>[ 7.234814] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
824 02:10:28.561695 <5>[ 7.263776] Sending DHCP requests ., OK
825 02:10:28.573109 <6>[ 7.348199] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
826 02:10:28.573710 <6>[ 7.356304] IP-Config: Complete:
827 02:10:28.584446 <6>[ 7.359843] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
828 02:10:28.590065 <6>[ 7.370276] host=192.168.6.8, domain=, nis-domain=(none)
829 02:10:28.595720 <6>[ 7.376404] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
830 02:10:28.602385 <6>[ 7.376438] nameserver0=10.255.253.1
831 02:10:28.608444 <6>[ 7.388990] clk: Disabling unused clocks
832 02:10:28.613910 <6>[ 7.393589] PM: genpd: Disabling unused power domains
833 02:10:28.633491 <6>[ 7.412208] Freeing unused kernel image (initmem) memory: 2048K
834 02:10:28.640929 <6>[ 7.421963] Run /init as init process
835 02:10:28.666027 Loading, please wait...
836 02:10:28.740904 Starting systemd-udevd version 252.22-1~deb12u1
837 02:10:31.734215 <4>[ 10.508975] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
838 02:10:31.910118 <4>[ 10.684791] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
839 02:10:32.090640 <6>[ 10.872993] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
840 02:10:32.101559 <6>[ 10.878810] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
841 02:10:32.395754 <6>[ 11.176393] hub 1-0:1.0: USB hub found
842 02:10:32.429200 <6>[ 11.209854] hub 1-0:1.0: 1 port detected
843 02:10:32.695822 <6>[ 11.477020] tda998x 0-0070: found TDA19988
844 02:10:35.549432 Begin: Loading essential drivers ... done.
845 02:10:35.557782 Begin: Running /scripts/init-premount ... done.
846 02:10:35.569011 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
847 02:10:35.580592 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
848 02:10:35.581088 Device /sys/class/net/eth0 found
849 02:10:35.581491 done.
850 02:10:35.652254 Begin: Waiting up to 180 secs for any network device to become available ... done.
851 02:10:35.724699 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
852 02:10:35.853175 IP-Config: eth0 guessed broadcast address 192.168.6.255
853 02:10:35.858768 IP-Config: eth0 complete (dhcp from 192.168.6.1):
854 02:10:35.864273 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
855 02:10:35.875470 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
856 02:10:35.875951 rootserver: 192.168.6.1 rootpath:
857 02:10:35.879038 filename :
858 02:10:35.932908 done.
859 02:10:35.944121 Begin: Running /scripts/nfs-bottom ... done.
860 02:10:36.025124 Begin: Running /scripts/init-bottom ... done.
861 02:10:37.486925 <30>[ 16.264863] systemd[1]: System time before build time, advancing clock.
862 02:10:37.701169 <30>[ 16.453010] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
863 02:10:37.710257 <30>[ 16.490138] systemd[1]: Detected architecture arm.
864 02:10:37.723059
865 02:10:37.723573 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
866 02:10:37.723988
867 02:10:37.744739 <30>[ 16.523375] systemd[1]: Hostname set to <debian-bookworm-armhf>.
868 02:10:39.908577 <30>[ 18.686122] systemd[1]: Queued start job for default target graphical.target.
869 02:10:39.925095 <30>[ 18.700654] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
870 02:10:39.932725 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
871 02:10:39.962033 <30>[ 18.736581] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
872 02:10:39.969556 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
873 02:10:39.994089 <30>[ 18.769977] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
874 02:10:40.006403 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
875 02:10:40.029282 <30>[ 18.805600] systemd[1]: Created slice user.slice - User and Session Slice.
876 02:10:40.035925 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
877 02:10:40.064778 <30>[ 18.835109] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
878 02:10:40.070029 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
879 02:10:40.088918 <30>[ 18.864877] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
880 02:10:40.096708 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
881 02:10:40.127363 <30>[ 18.894857] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
882 02:10:40.139347 <30>[ 18.915617] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
883 02:10:40.144934 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
884 02:10:40.167803 <30>[ 18.944276] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
885 02:10:40.176145 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
886 02:10:40.198568 <30>[ 18.974631] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
887 02:10:40.207040 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
888 02:10:40.228368 <30>[ 19.004706] systemd[1]: Reached target paths.target - Path Units.
889 02:10:40.233535 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
890 02:10:40.258288 <30>[ 19.034524] systemd[1]: Reached target remote-fs.target - Remote File Systems.
891 02:10:40.264760 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
892 02:10:40.288005 <30>[ 19.064335] systemd[1]: Reached target slices.target - Slice Units.
893 02:10:40.293486 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
894 02:10:40.318288 <30>[ 19.094601] systemd[1]: Reached target swap.target - Swaps.
895 02:10:40.322406 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
896 02:10:40.348457 <30>[ 19.124588] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
897 02:10:40.357345 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
898 02:10:40.381342 <30>[ 19.157420] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
899 02:10:40.394382 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
900 02:10:40.488339 <30>[ 19.259648] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
901 02:10:40.501096 <30>[ 19.277242] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
902 02:10:40.509508 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
903 02:10:40.531325 <30>[ 19.306465] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
904 02:10:40.538647 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
905 02:10:40.560753 <30>[ 19.336895] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
906 02:10:40.569503 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
907 02:10:40.593901 <30>[ 19.368866] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
908 02:10:40.599513 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
909 02:10:40.627791 <30>[ 19.405493] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
910 02:10:40.639138 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
911 02:10:40.664435 <30>[ 19.435546] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
912 02:10:40.683970 <30>[ 19.454079] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
913 02:10:40.728435 <30>[ 19.505337] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
914 02:10:40.750434 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
915 02:10:40.810158 <30>[ 19.587012] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
916 02:10:40.837756 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
917 02:10:40.919033 <30>[ 19.694918] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
918 02:10:40.948537 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
919 02:10:41.000118 <30>[ 19.776436] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
920 02:10:41.025683 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
921 02:10:41.078892 <30>[ 19.855692] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
922 02:10:41.098660 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
923 02:10:41.148830 <30>[ 19.927188] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
924 02:10:41.176762 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
925 02:10:41.230664 <30>[ 20.007742] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
926 02:10:41.256518 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
927 02:10:41.308541 <30>[ 20.086543] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
928 02:10:41.334368 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
929 02:10:41.386892 <30>[ 20.164985] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
930 02:10:41.404062 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
931 02:10:41.436220 <28>[ 20.206068] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
932 02:10:41.443816 <28>[ 20.220899] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
933 02:10:41.489716 <30>[ 20.267121] systemd[1]: Starting systemd-journald.service - Journal Service...
934 02:10:41.507724 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
935 02:10:41.547488 <30>[ 20.325240] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
936 02:10:41.567235 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
937 02:10:41.618091 <30>[ 20.395216] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
938 02:10:41.650717 Starting [0;1;39msystemd-network-g… units from Kernel command line...
939 02:10:41.709605 <30>[ 20.485162] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
940 02:10:41.750299 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
941 02:10:41.802299 <30>[ 20.579702] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
942 02:10:41.861988 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
943 02:10:41.932046 <30>[ 20.710296] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
944 02:10:41.986898 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
945 02:10:41.998640 <30>[ 20.775817] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
946 02:10:42.040973 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
947 02:10:42.071385 <30>[ 20.847461] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
948 02:10:42.112576 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
949 02:10:42.248927 <30>[ 21.026743] systemd[1]: modprobe@configfs.service: Deactivated successfully.
950 02:10:42.287436 <30>[ 21.064446] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
951 02:10:42.316225 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
952 02:10:42.337711 <30>[ 21.116684] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
953 02:10:42.367710 <30>[ 21.144279] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
954 02:10:42.376181 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
955 02:10:42.398275 <30>[ 21.176610] systemd[1]: modprobe@drm.service: Deactivated successfully.
956 02:10:42.428017 <30>[ 21.205560] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
957 02:10:42.456894 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
958 02:10:42.480406 <30>[ 21.256735] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
959 02:10:42.507010 <30>[ 21.284169] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
960 02:10:42.537260 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
961 02:10:42.558859 <30>[ 21.335391] systemd[1]: Started systemd-journald.service - Journal Service.
962 02:10:42.565786 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
963 02:10:42.598240 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
964 02:10:42.630291 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
965 02:10:42.658022 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
966 02:10:42.681738 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
967 02:10:42.700353 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
968 02:10:42.727790 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
969 02:10:42.787504 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
970 02:10:42.830853 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
971 02:10:42.899271 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
972 02:10:42.960735 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
973 02:10:43.029929 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
974 02:10:43.196733 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
975 02:10:43.278536 <46>[ 22.056635] systemd-journald[164]: Received client request to flush runtime journal.
976 02:10:43.335418 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
977 02:10:43.390292 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
978 02:10:44.249044 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
979 02:10:44.299725 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
980 02:10:44.967803 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
981 02:10:45.120623 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
982 02:10:45.138263 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
983 02:10:45.158096 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
984 02:10:45.230965 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
985 02:10:45.296836 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
986 02:10:46.202136 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
987 02:10:46.274108 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
988 02:10:46.850853 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
989 02:10:46.972368 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
990 02:10:47.080488 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
991 02:10:48.995109 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m <5>[ 27.767413] cfg80211: Loading compiled-in X.509 certificates for regulatory database
992 02:10:48.995736 - Coldplug All udev Devices.
993 02:10:49.334464 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
994 02:10:49.953467 <5>[ 28.733206] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
995 02:10:49.966786 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
996 02:10:50.017794 <5>[ 28.795945] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
997 02:10:50.046756 <4>[ 28.824255] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
998 02:10:50.052615 <6>[ 28.833237] cfg80211: failed to load regulatory.db
999 02:10:51.639889 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1000 02:10:51.702590 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1001 02:10:51.868498 <46>[ 30.636775] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1002 02:10:51.904615 <46>[ 30.675071] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
1003 02:11:00.841610 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1004 02:11:00.871266 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1005 02:11:00.898778 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1006 02:11:00.919718 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1007 02:11:00.978359 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1008 02:11:01.021138 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1009 02:11:01.089541 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1010 02:11:01.127567 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1011 02:11:01.191909 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1012 02:11:01.226117 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1013 02:11:01.254203 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1014 02:11:01.283072 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1015 02:11:01.324299 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1016 02:11:01.355043 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1017 02:11:01.387745 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1018 02:11:01.428531 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1019 02:11:01.455334 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1020 02:11:01.483939 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1021 02:11:01.513725 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1022 02:11:01.538041 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1023 02:11:01.565491 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1024 02:11:01.587158 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1025 02:11:01.616469 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1026 02:11:01.688216 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1027 02:11:01.729424 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1028 02:11:01.833169 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1029 02:11:01.901464 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1030 02:11:01.948566 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1031 02:11:01.992873 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1032 02:11:02.011288 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1033 02:11:02.225076 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1034 02:11:02.307605 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1035 02:11:02.368921 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1036 02:11:02.387799 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1037 02:11:02.415578 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1038 02:11:02.610773 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1039 02:11:02.971005 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1040 02:11:03.037466 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1041 02:11:03.061515 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1042 02:11:03.158350 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1043 02:11:03.323928 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1044 02:11:03.465067
1045 02:11:03.467485 Debian GNU/Linux 12 dworm-armhf login: root (automatic login)
1046 02:11:03.467988
1047 02:11:03.784406 Linux debian-bookworm-armhf 6.12.0-rc1 #1 SMP Wed Nov 6 01:41:51 UTC 2024 armv7l
1048 02:11:03.784986
1049 02:11:03.790081 The programs included with the Debian GNU/Linux system are free software;
1050 02:11:03.793365 the exact distribution terms for each program are described in the
1051 02:11:03.798895 individual files in /usr/share/doc/*/copyright.
1052 02:11:03.799403
1053 02:11:03.804449 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1054 02:11:03.808972 permitted by applicable law.
1055 02:11:08.877656 Matched prompt #10: / #
1057 02:11:08.880183 Kernel warnings or errors detected.
1058 02:11:08.880601 Setting prompt string to ['/ #']
1059 02:11:08.881125 end: 2.4.4.1 login-action (duration 00:00:48) [common]
1061 02:11:08.883486 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
1062 02:11:08.884030 start: 2.4.5 expect-shell-connection (timeout 00:03:09) [common]
1063 02:11:08.884445 Setting prompt string to ['/ #']
1064 02:11:08.884846 Forcing a shell prompt, looking for ['/ #']
1066 02:11:08.935772 / #
1067 02:11:08.936373 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1068 02:11:08.936913 Waiting using forced prompt support (timeout 00:02:30)
1069 02:11:08.941095
1070 02:11:08.946586 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1071 02:11:08.947261 start: 2.4.6 export-device-env (timeout 00:03:09) [common]
1072 02:11:08.947806 Sending with 10 millisecond of delay
1074 02:11:13.934825 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/943474/extract-nfsrootfs-wx0kno9x'
1075 02:11:13.945757 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/943474/extract-nfsrootfs-wx0kno9x'
1076 02:11:13.947061 Sending with 10 millisecond of delay
1078 02:11:16.044543 / # export NFS_SERVER_IP='192.168.6.3'
1079 02:11:16.055414 export NFS_SERVER_IP='192.168.6.3'
1080 02:11:16.056422 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1081 02:11:16.057021 end: 2.4 uboot-commands (duration 00:01:58) [common]
1082 02:11:16.057611 end: 2 uboot-action (duration 00:01:58) [common]
1083 02:11:16.058237 start: 3 lava-test-retry (timeout 00:06:53) [common]
1084 02:11:16.058818 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1085 02:11:16.059274 Using namespace: common
1087 02:11:16.160393 / # #
1088 02:11:16.161215 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1089 02:11:16.165520 #
1090 02:11:16.172163 Using /lava-943474
1092 02:11:16.273297 / # export SHELL=/bin/bash
1093 02:11:16.278535 export SHELL=/bin/bash
1095 02:11:16.385273 / # . /lava-943474/environment
1096 02:11:16.390534 . /lava-943474/environment
1098 02:11:16.505882 / # /lava-943474/bin/lava-test-runner /lava-943474/0
1099 02:11:16.506674 Test shell timeout: 10s (minimum of the action and connection timeout)
1100 02:11:16.511032 /lava-943474/bin/lava-test-runner /lava-943474/0
1101 02:11:16.903707 + export TESTRUN_ID=0_timesync-off
1102 02:11:16.910755 + TESTRUN_ID=0_timesync-off
1103 02:11:16.911220 + cd /lava-943474/0/tests/0_timesync-off
1104 02:11:16.911638 ++ cat uuid
1105 02:11:16.927594 + UUID=943474_1.6.2.4.1
1106 02:11:16.928058 + set +x
1107 02:11:16.935201 <LAVA_SIGNAL_STARTRUN 0_timesync-off 943474_1.6.2.4.1>
1108 02:11:16.935659 + systemctl stop systemd-timesyncd
1109 02:11:16.936344 Received signal: <STARTRUN> 0_timesync-off 943474_1.6.2.4.1
1110 02:11:16.936787 Starting test lava.0_timesync-off (943474_1.6.2.4.1)
1111 02:11:16.937309 Skipping test definition patterns.
1112 02:11:17.222995 + set +x
1113 02:11:17.223501 <LAVA_SIGNAL_ENDRUN 0_timesync-off 943474_1.6.2.4.1>
1114 02:11:17.224163 Received signal: <ENDRUN> 0_timesync-off 943474_1.6.2.4.1
1115 02:11:17.224651 Ending use of test pattern.
1116 02:11:17.225056 Ending test lava.0_timesync-off (943474_1.6.2.4.1), duration 0.29
1118 02:11:17.384529 + export TESTRUN_ID=1_kselftest-dt
1119 02:11:17.392457 + TESTRUN_ID=1_kselftest-dt
1120 02:11:17.392927 + cd /lava-943474/0/tests/1_kselftest-dt
1121 02:11:17.393343 ++ cat uuid
1122 02:11:17.420432 + UUID=943474_1.6.2.4.5
1123 02:11:17.420914 + set +x
1124 02:11:17.426017 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 943474_1.6.2.4.5>
1125 02:11:17.426480 + cd ./automated/linux/kselftest/
1126 02:11:17.427144 Received signal: <STARTRUN> 1_kselftest-dt 943474_1.6.2.4.5
1127 02:11:17.427561 Starting test lava.1_kselftest-dt (943474_1.6.2.4.5)
1128 02:11:17.428040 Skipping test definition patterns.
1129 02:11:17.454264 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g clk -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1130 02:11:17.553881 INFO: install_deps skipped
1131 02:11:18.139739 --2024-11-06 02:11:18-- http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1132 02:11:18.166715 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1133 02:11:18.308523 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1134 02:11:18.451751 HTTP request sent, awaiting response... 200 OK
1135 02:11:18.452390 Length: 4097648 (3.9M) [application/octet-stream]
1136 02:11:18.457486 Saving to: 'kselftest_armhf.tar.gz'
1137 02:11:18.458167
1138 02:11:20.046773
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kselftest_armhf.tar 1%[ ] 49.92K 179KB/s
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kselftest_armhf.tar 15%[==> ] 636.76K 844KB/s
kselftest_armhf.tar 28%[====> ] 1.11M 1.09MB/s
kselftest_armhf.tar 61%[===========> ] 2.42M 1.99MB/s
kselftest_armhf.tar 80%[===============> ] 3.13M 2.19MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.46MB/s in 1.6s
1139 02:11:20.047496
1140 02:11:20.629386 2024-11-06 02:11:20 (2.46 MB/s) - 'kselftest_armhf.tar.gz' saved [4097648/4097648]
1141 02:11:20.630215
1142 02:11:35.152037 skiplist:
1143 02:11:35.152691 ========================================
1144 02:11:35.157640 ========================================
1145 02:11:35.256506 dt:test_unprobed_devices.sh
1146 02:11:35.289149 ============== Tests to run ===============
1147 02:11:35.296942 dt:test_unprobed_devices.sh
1148 02:11:35.300884 ===========End Tests to run ===============
1149 02:11:35.311942 shardfile-dt pass
1150 02:11:35.554817 <12>[ 74.337140] kselftest: Running tests in dt
1151 02:11:35.585509 TAP version 13
1152 02:11:35.609834 1..1
1153 02:11:35.664501 # timeout set to 45
1154 02:11:35.665120 # selftests: dt: test_unprobed_devices.sh
1155 02:11:36.485865 # TAP version 13
1156 02:12:01.477497 # 1..257
1157 02:12:01.648227 # ok 1 / # SKIP
1158 02:12:01.671107 # ok 2 /clk_mcasp0
1159 02:12:01.745910 # ok 3 /clk_mcasp0_fixed # SKIP
1160 02:12:01.815931 # ok 4 /cpus/cpu@0 # SKIP
1161 02:12:01.887709 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1162 02:12:01.907811 # ok 6 /fixedregulator0
1163 02:12:01.924148 # ok 7 /leds
1164 02:12:01.946818 # ok 8 /ocp
1165 02:12:01.969447 # ok 9 /ocp/interconnect@44c00000
1166 02:12:01.997921 # ok 10 /ocp/interconnect@44c00000/segment@0
1167 02:12:02.016715 # ok 11 /ocp/interconnect@44c00000/segment@100000
1168 02:12:02.042343 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1169 02:12:02.111534 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1170 02:12:02.136571 # ok 14 /ocp/interconnect@44c00000/segment@200000
1171 02:12:02.160570 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1172 02:12:02.263217 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1173 02:12:02.338370 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1174 02:12:02.411392 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1175 02:12:02.483406 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1176 02:12:02.554249 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1177 02:12:02.622949 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1178 02:12:02.697161 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1179 02:12:02.766303 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1180 02:12:02.843053 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1181 02:12:02.914941 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1182 02:12:02.983309 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1183 02:12:03.055851 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1184 02:12:03.125194 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1185 02:12:03.198834 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1186 02:12:03.269864 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1187 02:12:03.341539 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1188 02:12:03.412228 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1189 02:12:03.484580 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1190 02:12:03.556864 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1191 02:12:03.627779 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1192 02:12:03.698739 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1193 02:12:03.770954 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1194 02:12:03.843329 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1195 02:12:03.915053 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1196 02:12:03.986597 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1197 02:12:04.059318 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1198 02:12:04.132564 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1199 02:12:04.204408 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1200 02:12:04.279362 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1201 02:12:04.347084 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1202 02:12:04.425420 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1203 02:12:04.496079 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1204 02:12:04.564436 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1205 02:12:04.638134 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1206 02:12:04.710297 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1207 02:12:04.782058 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1208 02:12:04.853199 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1209 02:12:04.927088 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1210 02:12:04.999209 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1211 02:12:05.070077 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1212 02:12:05.142261 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1213 02:12:05.214473 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1214 02:12:05.286549 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1215 02:12:05.358469 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1216 02:12:05.430228 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1217 02:12:05.502053 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1218 02:12:05.573412 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1219 02:12:05.646866 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1220 02:12:05.717854 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1221 02:12:05.788732 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1222 02:12:05.861489 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1223 02:12:05.933698 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1224 02:12:06.004797 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1225 02:12:06.076217 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1226 02:12:06.149550 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1227 02:12:06.221733 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1228 02:12:06.295596 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1229 02:12:06.367446 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1230 02:12:06.443176 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1231 02:12:06.511029 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1232 02:12:06.582738 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1233 02:12:06.655099 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1234 02:12:06.728148 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1235 02:12:06.801651 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1236 02:12:06.873975 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1237 02:12:06.947318 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1238 02:12:07.016686 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1239 02:12:07.088669 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1240 02:12:07.160682 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1241 02:12:07.232262 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1242 02:12:07.304663 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1243 02:12:07.376241 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1244 02:12:07.452044 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1245 02:12:07.527878 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1246 02:12:07.595194 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1247 02:12:07.669385 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1248 02:12:07.739852 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1249 02:12:07.811899 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1250 02:12:07.884892 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1251 02:12:07.905748 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1252 02:12:07.929455 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1253 02:12:07.958473 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1254 02:12:07.978006 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1255 02:12:08.001687 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1256 02:12:08.025869 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1257 02:12:08.049430 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1258 02:12:08.072188 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1259 02:12:08.181880 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1260 02:12:08.203157 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1261 02:12:08.227186 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1262 02:12:08.250396 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1263 02:12:08.360727 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1264 02:12:08.435288 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1265 02:12:08.505933 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1266 02:12:08.575422 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1267 02:12:08.646982 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1268 02:12:08.719723 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1269 02:12:08.792111 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1270 02:12:08.864609 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1271 02:12:08.941312 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1272 02:12:09.016153 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1273 02:12:09.084750 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1274 02:12:09.165370 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1275 02:12:09.231591 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1276 02:12:09.307313 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1277 02:12:09.385073 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1278 02:12:09.452592 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1279 02:12:09.474924 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1280 02:12:09.544303 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1281 02:12:09.614070 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1282 02:12:09.686760 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1283 02:12:09.712237 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1284 02:12:09.779813 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1285 02:12:09.807926 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1286 02:12:09.880116 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1287 02:12:09.902272 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1288 02:12:09.926853 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1289 02:12:09.950097 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1290 02:12:09.973015 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1291 02:12:09.997697 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1292 02:12:10.022742 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1293 02:12:10.049557 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1294 02:12:10.122273 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1295 02:12:10.143787 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1296 02:12:10.170055 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1297 02:12:10.237360 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1298 02:12:10.307811 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1299 02:12:10.328490 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1300 02:12:10.429756 # not ok 144 /ocp/interconnect@47c00000
1301 02:12:10.505559 # not ok 145 /ocp/interconnect@47c00000/segment@0
1302 02:12:10.526426 # ok 146 /ocp/interconnect@48000000
1303 02:12:10.544630 # ok 147 /ocp/interconnect@48000000/segment@0
1304 02:12:10.570958 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1305 02:12:10.599099 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1306 02:12:10.621898 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1307 02:12:10.644780 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1308 02:12:10.664541 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1309 02:12:10.688805 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1310 02:12:10.713915 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1311 02:12:10.787772 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1312 02:12:10.860983 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1313 02:12:10.881962 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1314 02:12:10.903401 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1315 02:12:10.926162 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1316 02:12:10.950357 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1317 02:12:10.977927 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1318 02:12:11.002533 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1319 02:12:11.023487 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1320 02:12:11.044319 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1321 02:12:11.071980 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1322 02:12:11.095155 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1323 02:12:11.114545 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1324 02:12:11.139279 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1325 02:12:11.169318 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1326 02:12:11.186565 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1327 02:12:11.210039 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1328 02:12:11.234047 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1329 02:12:11.256868 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1330 02:12:11.282951 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1331 02:12:11.306174 # ok 175 /ocp/interconnect@48000000/segment@100000
1332 02:12:11.331360 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1333 02:12:11.352970 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1334 02:12:11.426279 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1335 02:12:11.503540 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1336 02:12:11.573901 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1337 02:12:11.646027 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1338 02:12:11.713144 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1339 02:12:11.791083 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1340 02:12:11.857121 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1341 02:12:11.930409 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1342 02:12:11.950481 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1343 02:12:11.975610 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1344 02:12:11.999657 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1345 02:12:12.027553 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1346 02:12:12.050973 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1347 02:12:12.072925 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1348 02:12:12.098511 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1349 02:12:12.122987 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1350 02:12:12.141546 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1351 02:12:12.164789 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1352 02:12:12.192291 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1353 02:12:12.212950 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1354 02:12:12.237492 # ok 198 /ocp/interconnect@48000000/segment@200000
1355 02:12:12.260975 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1356 02:12:12.332132 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1357 02:12:12.380830 # ok 201 /ocp/interconnect@48000000/segment@300000
1358 02:12:12.405955 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1359 02:12:12.431801 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1360 02:12:12.456551 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1361 02:12:12.479420 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1362 02:12:12.502078 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1363 02:12:12.531072 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1364 02:12:12.603234 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1365 02:12:12.619236 # ok 209 /ocp/interconnect@4a000000
1366 02:12:12.640961 # ok 210 /ocp/interconnect@4a000000/segment@0
1367 02:12:12.666640 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1368 02:12:12.692742 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1369 02:12:12.717065 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1370 02:12:12.738694 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1371 02:12:12.812945 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1372 02:12:12.916968 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1373 02:12:12.988590 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1374 02:12:13.092895 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1375 02:12:13.163218 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1376 02:12:13.234247 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1377 02:12:13.332447 # not ok 221 /ocp/interconnect@4b140000
1378 02:12:13.404106 # not ok 222 /ocp/interconnect@4b140000/segment@0
1379 02:12:13.478562 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1380 02:12:13.498390 # ok 224 /ocp/target-module@40300000
1381 02:12:13.526734 # ok 225 /ocp/target-module@40300000/sram@0
1382 02:12:13.597959 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1383 02:12:13.664654 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1384 02:12:13.688954 # ok 228 /ocp/target-module@47400000
1385 02:12:13.711138 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1386 02:12:13.736361 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1387 02:12:13.758652 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1388 02:12:13.776546 # ok 232 /ocp/target-module@47400000/usb@1400
1389 02:12:13.799162 # ok 233 /ocp/target-module@47400000/usb@1800
1390 02:12:13.825092 # ok 234 /ocp/target-module@47810000
1391 02:12:13.842226 # ok 235 /ocp/target-module@49000000
1392 02:12:13.865801 # ok 236 /ocp/target-module@49000000/dma@0
1393 02:12:13.889439 # ok 237 /ocp/target-module@49800000
1394 02:12:13.909623 # ok 238 /ocp/target-module@49800000/dma@0
1395 02:12:13.936589 # ok 239 /ocp/target-module@49900000
1396 02:12:13.959383 # ok 240 /ocp/target-module@49900000/dma@0
1397 02:12:13.978528 # ok 241 /ocp/target-module@49a00000
1398 02:12:14.000687 # ok 242 /ocp/target-module@49a00000/dma@0
1399 02:12:14.022221 # ok 243 /ocp/target-module@4c000000
1400 02:12:14.094239 # not ok 244 /ocp/target-module@4c000000/emif@0
1401 02:12:14.119163 # ok 245 /ocp/target-module@50000000
1402 02:12:14.137482 # ok 246 /ocp/target-module@53100000
1403 02:12:14.209189 # not ok 247 /ocp/target-module@53100000/sham@0
1404 02:12:14.231078 # ok 248 /ocp/target-module@53500000
1405 02:12:14.300892 # not ok 249 /ocp/target-module@53500000/aes@0
1406 02:12:14.326813 # ok 250 /ocp/target-module@56000000
1407 02:12:14.430574 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1408 02:12:14.494943 # ok 252 /opp-table # SKIP
1409 02:12:14.564703 # ok 253 /soc # SKIP
1410 02:12:14.585793 # ok 254 /sound
1411 02:12:14.609580 # ok 255 /target-module@4b000000
1412 02:12:14.638308 # ok 256 /target-module@4b000000/target-module@140000
1413 02:12:14.655122 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1414 02:12:14.663414 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1415 02:12:14.671628 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1416 02:12:16.760737 dt_test_unprobed_devices_sh_ skip
1417 02:12:16.766242 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1418 02:12:16.771845 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1419 02:12:16.772415 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1420 02:12:16.777514 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1421 02:12:16.783117 dt_test_unprobed_devices_sh_fixedregulator0 pass
1422 02:12:16.788759 dt_test_unprobed_devices_sh_leds pass
1423 02:12:16.789274 dt_test_unprobed_devices_sh_ocp pass
1424 02:12:16.794338 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1425 02:12:16.799958 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1426 02:12:16.805469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1427 02:12:16.816731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1428 02:12:16.822226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1429 02:12:16.827973 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1430 02:12:16.839321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1431 02:12:16.844702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1432 02:12:16.856019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1433 02:12:16.867116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1434 02:12:16.878340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1435 02:12:16.883888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1436 02:12:16.895126 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1437 02:12:16.906490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1438 02:12:16.917587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1439 02:12:16.928757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1440 02:12:16.934450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1441 02:12:16.945708 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1442 02:12:16.956763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1443 02:12:16.967959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1444 02:12:16.979102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1445 02:12:16.984716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1446 02:12:16.995881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1447 02:12:17.007100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1448 02:12:17.295100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1449 02:12:17.295481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1450 02:12:17.295702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1451 02:12:17.296190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1452 02:12:17.296431 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1453 02:12:17.296656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1454 02:12:17.296865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1455 02:12:17.297067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1456 02:12:17.297271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1457 02:12:17.297476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1458 02:12:17.297677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1459 02:12:17.297905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1460 02:12:17.298107 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1461 02:12:17.298306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1462 02:12:17.298504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1463 02:12:17.298785 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1464 02:12:17.298993 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1465 02:12:17.299194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1466 02:12:17.299392 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1467 02:12:17.299586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1468 02:12:17.299779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1469 02:12:17.299976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1470 02:12:17.300171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1471 02:12:17.300363 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1472 02:12:17.300556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1473 02:12:17.300749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1474 02:12:17.301105 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1475 02:12:17.310949 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1476 02:12:17.317166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1477 02:12:17.328529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1478 02:12:17.342920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1479 02:12:17.354038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1480 02:12:17.363019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1481 02:12:17.374294 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1482 02:12:17.385462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1483 02:12:17.396576 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1484 02:12:17.402249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1485 02:12:17.413403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1486 02:12:17.424734 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1487 02:12:17.435732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1488 02:12:17.446971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1489 02:12:17.458133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1490 02:12:17.469332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1491 02:12:17.480492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1492 02:12:17.491846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1493 02:12:17.502920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1494 02:12:17.514208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1495 02:12:17.525283 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1496 02:12:17.536552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1497 02:12:17.547681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1498 02:12:17.558923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1499 02:12:17.570062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1500 02:12:17.575789 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1501 02:12:17.586839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1502 02:12:17.598059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1503 02:12:17.609286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1504 02:12:17.620422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1505 02:12:17.631636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1506 02:12:17.642807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1507 02:12:17.654140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1508 02:12:17.665228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1509 02:12:17.676420 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1510 02:12:17.687645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1511 02:12:17.698772 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1512 02:12:17.704595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1513 02:12:17.715541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1514 02:12:17.721174 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1515 02:12:17.732299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1516 02:12:17.743522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1517 02:12:17.749151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1518 02:12:17.760299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1519 02:12:17.771498 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1520 02:12:17.777116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1521 02:12:17.788562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1522 02:12:17.799816 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1523 02:12:17.810820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1524 02:12:17.822114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1525 02:12:17.833158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1526 02:12:17.844473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1527 02:12:17.861135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1528 02:12:17.872304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1529 02:12:17.883448 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1530 02:12:17.894723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1531 02:12:17.905842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1532 02:12:17.917016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1533 02:12:17.928288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1534 02:12:17.939405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1535 02:12:17.956215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1536 02:12:17.967369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1537 02:12:17.984144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1538 02:12:17.995452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1539 02:12:18.001121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1540 02:12:18.012206 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1541 02:12:18.017868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1542 02:12:18.029006 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1543 02:12:18.040199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1544 02:12:18.045949 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1545 02:12:18.057054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1546 02:12:18.062612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1547 02:12:18.073793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1548 02:12:18.079396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1549 02:12:18.090601 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1550 02:12:18.096218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1551 02:12:18.107381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1552 02:12:18.118553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1553 02:12:18.129848 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1554 02:12:18.135381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1555 02:12:18.146663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1556 02:12:18.157897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1557 02:12:18.169020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1558 02:12:18.174609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1559 02:12:18.180304 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1560 02:12:18.185695 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1561 02:12:18.191294 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1562 02:12:18.197001 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1563 02:12:18.208165 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1564 02:12:18.213734 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1565 02:12:18.219725 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1566 02:12:18.230556 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1567 02:12:18.236139 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1568 02:12:18.247336 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1569 02:12:18.252968 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1570 02:12:18.264173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1571 02:12:18.269848 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1572 02:12:18.281032 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1573 02:12:18.286635 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1574 02:12:18.297883 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1575 02:12:18.303482 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1576 02:12:18.309021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1577 02:12:18.320287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1578 02:12:18.325937 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1579 02:12:18.337099 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1580 02:12:18.342746 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1581 02:12:18.353924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1582 02:12:18.359584 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1583 02:12:18.370777 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1584 02:12:18.376355 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1585 02:12:18.387603 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1586 02:12:18.393074 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1587 02:12:18.404320 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1588 02:12:18.409942 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1589 02:12:18.421082 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1590 02:12:18.426725 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1591 02:12:18.432308 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1592 02:12:18.443461 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1593 02:12:18.454684 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1594 02:12:18.465883 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1595 02:12:18.477137 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1596 02:12:18.488352 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1597 02:12:18.493972 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1598 02:12:18.505074 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1599 02:12:18.516219 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1600 02:12:18.527426 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1601 02:12:18.538622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1602 02:12:18.544242 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1603 02:12:18.555414 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1604 02:12:18.561026 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1605 02:12:18.572188 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1606 02:12:18.577844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1607 02:12:18.589045 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1608 02:12:18.594673 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1609 02:12:18.605917 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1610 02:12:18.611477 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1611 02:12:18.622678 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1612 02:12:18.628306 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1613 02:12:18.639490 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1614 02:12:18.645099 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1615 02:12:18.656251 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1616 02:12:18.661863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1617 02:12:18.667453 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1618 02:12:18.678589 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1619 02:12:18.684341 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1620 02:12:18.695387 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1621 02:12:18.701135 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1622 02:12:18.712267 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1623 02:12:18.717912 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1624 02:12:18.723384 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1625 02:12:18.728975 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1626 02:12:18.740262 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1627 02:12:18.745783 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1628 02:12:18.756907 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1629 02:12:18.762558 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1630 02:12:18.774115 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1631 02:12:18.784963 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1632 02:12:18.796105 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1633 02:12:18.801724 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1634 02:12:18.812908 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1635 02:12:18.824097 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1636 02:12:18.829758 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1637 02:12:18.835393 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1638 02:12:18.841010 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1639 02:12:18.846614 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1640 02:12:18.852223 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1641 02:12:18.857874 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1642 02:12:18.863480 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1643 02:12:18.869031 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1644 02:12:18.880185 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1645 02:12:18.885764 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1646 02:12:18.891386 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1647 02:12:18.896984 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1648 02:12:18.902624 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1649 02:12:18.908201 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1650 02:12:18.913778 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1651 02:12:18.919413 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1652 02:12:18.925019 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1653 02:12:18.930628 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1654 02:12:18.936299 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1655 02:12:18.941943 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1656 02:12:18.947439 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1657 02:12:18.953124 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1658 02:12:18.958647 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1659 02:12:18.964316 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1660 02:12:18.969857 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1661 02:12:18.975528 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1662 02:12:18.981071 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1663 02:12:18.986709 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1664 02:12:18.992295 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1665 02:12:18.997874 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1666 02:12:19.003422 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1667 02:12:19.009018 dt_test_unprobed_devices_sh_opp-table skip
1668 02:12:19.009571 dt_test_unprobed_devices_sh_soc skip
1669 02:12:19.014683 dt_test_unprobed_devices_sh_sound pass
1670 02:12:19.020275 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1671 02:12:19.025920 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1672 02:12:19.031442 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1673 02:12:19.037035 dt_test_unprobed_devices_sh fail
1674 02:12:19.042778 + ../../utils/send-to-lava.sh ./output/result.txt
1675 02:12:19.048224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1676 02:12:19.049199 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1678 02:12:19.053119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1679 02:12:19.053915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1681 02:12:19.140267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1682 02:12:19.141189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1684 02:12:19.233077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1685 02:12:19.233975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1687 02:12:19.323578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1688 02:12:19.324487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1690 02:12:19.420146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1691 02:12:19.421066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1693 02:12:19.510573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1694 02:12:19.511474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1696 02:12:19.600420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1697 02:12:19.601349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1699 02:12:19.691494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1700 02:12:19.692400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1702 02:12:19.784849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1703 02:12:19.785788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1705 02:12:19.878684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1706 02:12:19.879345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1708 02:12:19.968693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1709 02:12:19.971142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1711 02:12:20.059746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1712 02:12:20.060389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1714 02:12:20.151112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1715 02:12:20.151761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1717 02:12:20.238191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1718 02:12:20.238838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1720 02:12:20.330761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1721 02:12:20.331740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1723 02:12:20.424404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1724 02:12:20.425241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1726 02:12:20.517224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1727 02:12:20.518087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1729 02:12:20.610111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1730 02:12:20.611030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1732 02:12:20.702821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1733 02:12:20.703693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1735 02:12:20.794400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1736 02:12:20.795245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1738 02:12:20.887277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1739 02:12:20.888223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1741 02:12:20.978693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1742 02:12:20.979541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1744 02:12:21.071612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1745 02:12:21.072416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1747 02:12:21.165405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1748 02:12:21.166306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1750 02:12:21.266934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1751 02:12:21.267736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1753 02:12:21.368880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1754 02:12:21.369759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1756 02:12:21.462879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1757 02:12:21.463756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1759 02:12:21.554119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1760 02:12:21.554989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1762 02:12:21.643904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1763 02:12:21.644805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1765 02:12:21.735747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1766 02:12:21.736613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1768 02:12:21.830303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1769 02:12:21.831193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1771 02:12:21.922879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1772 02:12:21.923778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1774 02:12:22.014208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1775 02:12:22.015071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1777 02:12:22.105398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1778 02:12:22.106308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1780 02:12:22.198871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1781 02:12:22.199746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1783 02:12:22.291905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1784 02:12:22.292794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1786 02:12:22.384244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1787 02:12:22.385130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1789 02:12:22.477269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1790 02:12:22.478203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1792 02:12:22.571054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1793 02:12:22.571939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1795 02:12:22.663401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1796 02:12:22.664269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1798 02:12:22.756023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1799 02:12:22.756920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1801 02:12:22.849574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1802 02:12:22.850488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1804 02:12:22.941715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1805 02:12:22.942630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1807 02:12:23.033869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1808 02:12:23.034767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1810 02:12:23.127107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1811 02:12:23.128006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1813 02:12:23.219351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1814 02:12:23.220018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1816 02:12:23.312156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1817 02:12:23.312964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1819 02:12:23.405947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1820 02:12:23.406807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1822 02:12:23.500172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1823 02:12:23.501036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1825 02:12:23.592352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1826 02:12:23.593077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1828 02:12:23.686183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1829 02:12:23.687003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1831 02:12:23.781754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1832 02:12:23.782588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1834 02:12:23.873934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1835 02:12:23.874469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1837 02:12:23.967530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1838 02:12:23.968495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1840 02:12:24.060409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1841 02:12:24.061282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1843 02:12:24.152766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1844 02:12:24.153617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1846 02:12:24.244840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1847 02:12:24.245707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1849 02:12:24.334741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1850 02:12:24.335588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1852 02:12:24.427066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1853 02:12:24.427986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1855 02:12:24.522422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1856 02:12:24.523322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1858 02:12:24.616319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1859 02:12:24.617191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1861 02:12:24.709540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1862 02:12:24.710438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1864 02:12:24.802554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1865 02:12:24.803483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1867 02:12:24.895080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1868 02:12:24.895906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1870 02:12:24.987528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1871 02:12:24.988330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1873 02:12:25.081137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1874 02:12:25.081987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1876 02:12:25.173145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1877 02:12:25.173987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1879 02:12:25.264681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1880 02:12:25.265568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1882 02:12:25.351108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1883 02:12:25.351892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1885 02:12:25.445345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1886 02:12:25.446209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1888 02:12:25.536356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1889 02:12:25.537254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1891 02:12:25.628542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1892 02:12:25.629406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1894 02:12:25.722465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1895 02:12:25.723315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1897 02:12:25.813083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1898 02:12:25.813909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1900 02:12:25.906436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1901 02:12:25.907063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1903 02:12:26.000172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1904 02:12:26.000996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1906 02:12:26.288095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1907 02:12:26.288575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1908 02:12:26.289157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1910 02:12:26.290288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1912 02:12:26.291621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1913 02:12:26.292223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1915 02:12:26.371781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1916 02:12:26.372438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1918 02:12:26.464702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1919 02:12:26.465352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1921 02:12:26.558004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1922 02:12:26.558677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1924 02:12:26.651385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1925 02:12:26.652297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1927 02:12:26.742474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1928 02:12:26.743423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1930 02:12:26.833969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1931 02:12:26.834863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1933 02:12:26.926013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1934 02:12:26.926939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1936 02:12:27.018409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1937 02:12:27.019326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1939 02:12:27.110944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1940 02:12:27.111846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1942 02:12:27.204918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1943 02:12:27.205860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1945 02:12:27.295770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1946 02:12:27.296847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1948 02:12:27.385354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1949 02:12:27.386320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1951 02:12:27.488910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1952 02:12:27.490003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1954 02:12:27.591455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1955 02:12:27.592370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1957 02:12:27.686217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1958 02:12:27.687195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1960 02:12:27.775999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1961 02:12:27.776923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1963 02:12:27.868016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1964 02:12:27.868921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1966 02:12:27.961562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1967 02:12:27.962571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1969 02:12:28.052772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1970 02:12:28.053746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1972 02:12:28.139740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1973 02:12:28.140794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1975 02:12:28.232192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1976 02:12:28.233131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1978 02:12:28.323616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1979 02:12:28.324658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1981 02:12:28.416032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1982 02:12:28.416957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1984 02:12:28.510977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1985 02:12:28.511908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1987 02:12:28.601710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1988 02:12:28.602596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1990 02:12:28.693269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1991 02:12:28.693947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1993 02:12:28.786405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1994 02:12:28.787056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1996 02:12:28.889757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1997 02:12:28.890403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1999 02:12:28.992447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
2000 02:12:28.993089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
2002 02:12:29.093874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
2003 02:12:29.094500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
2005 02:12:29.194082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
2006 02:12:29.194943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
2008 02:12:29.287600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
2009 02:12:29.288425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
2011 02:12:29.378790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
2012 02:12:29.379766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
2014 02:12:29.470910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
2015 02:12:29.471893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
2017 02:12:29.563901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2018 02:12:29.564804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2020 02:12:29.657594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2021 02:12:29.658507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2023 02:12:29.750047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2024 02:12:29.750878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2026 02:12:29.843121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2027 02:12:29.843948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2029 02:12:29.933792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2030 02:12:29.934711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2032 02:12:30.025636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2033 02:12:30.026487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2035 02:12:30.117585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2037 02:12:30.120633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2038 02:12:30.210721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2040 02:12:30.213871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2041 02:12:30.311586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2043 02:12:30.314716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2044 02:12:30.404447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2045 02:12:30.405286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2047 02:12:30.495775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2048 02:12:30.496635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2050 02:12:30.586077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2051 02:12:30.586947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2053 02:12:30.688070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2054 02:12:30.688914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2056 02:12:30.788587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2057 02:12:30.789424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2059 02:12:30.882083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2060 02:12:30.882950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2062 02:12:30.974758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2063 02:12:30.975607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2065 02:12:31.070601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2066 02:12:31.071463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2068 02:12:31.160999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2069 02:12:31.161771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2071 02:12:31.252269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2072 02:12:31.253047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2074 02:12:31.344082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2075 02:12:31.344932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2077 02:12:31.436332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2078 02:12:31.437169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2080 02:12:31.532694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2081 02:12:31.534419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2083 02:12:31.623523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2084 02:12:31.624138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2086 02:12:31.717063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2087 02:12:31.717838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2089 02:12:31.810156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2090 02:12:31.810894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2092 02:12:31.898156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2093 02:12:31.898894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2095 02:12:31.991457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2096 02:12:31.992287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2098 02:12:32.083805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2099 02:12:32.084523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2101 02:12:32.176442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2102 02:12:32.177171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2104 02:12:32.268249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2105 02:12:32.269037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2107 02:12:32.356620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2108 02:12:32.357354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2110 02:12:32.450694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2111 02:12:32.451426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2113 02:12:32.543036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2114 02:12:32.543771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2116 02:12:32.636822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2117 02:12:32.637543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2119 02:12:32.729140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2120 02:12:32.729871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2122 02:12:32.821473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2123 02:12:32.822233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2125 02:12:32.914573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2126 02:12:32.915305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2128 02:12:33.006421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2129 02:12:33.007146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2131 02:12:33.108339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2132 02:12:33.109091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2134 02:12:33.209453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2135 02:12:33.210320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2137 02:12:33.310423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2138 02:12:33.311402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2140 02:12:33.401488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2141 02:12:33.402367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2143 02:12:33.494107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2144 02:12:33.494958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2146 02:12:33.583962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2147 02:12:33.584796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2149 02:12:33.675632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2150 02:12:33.676476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2152 02:12:33.766640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2153 02:12:33.767476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2155 02:12:33.860511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2156 02:12:33.861315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2158 02:12:33.950287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2159 02:12:33.951359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2161 02:12:34.041060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2162 02:12:34.042139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2164 02:12:34.133507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2165 02:12:34.134604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2167 02:12:34.226115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2168 02:12:34.227228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2170 02:12:34.321154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2171 02:12:34.322300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2173 02:12:34.410448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2174 02:12:34.411510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2176 02:12:34.503324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2177 02:12:34.504183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2179 02:12:34.599342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2180 02:12:34.600188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2182 02:12:34.691294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2183 02:12:34.692148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2185 02:12:34.783399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2186 02:12:34.784249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2188 02:12:34.876011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2189 02:12:34.876848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2191 02:12:34.967705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2192 02:12:34.968559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2194 02:12:35.059892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2195 02:12:35.060739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2197 02:12:35.152949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2198 02:12:35.153833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2200 02:12:35.243939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2201 02:12:35.244761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2203 02:12:35.339114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2204 02:12:35.339985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2206 02:12:35.430803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2207 02:12:35.431671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2209 02:12:35.524482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2210 02:12:35.525374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2212 02:12:35.619704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2213 02:12:35.620558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2215 02:12:35.712331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2216 02:12:35.713177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2218 02:12:35.807535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2219 02:12:35.808562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2221 02:12:35.903132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2222 02:12:35.904060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2224 02:12:36.002180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2225 02:12:36.003031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2227 02:12:36.097326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2228 02:12:36.098198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2230 02:12:36.197123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2231 02:12:36.197949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2233 02:12:36.293631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2234 02:12:36.294502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2236 02:12:36.398740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2237 02:12:36.399615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2239 02:12:36.494447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2240 02:12:36.495298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2242 02:12:36.591774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2243 02:12:36.592600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2245 02:12:36.691310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2246 02:12:36.692155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2248 02:12:36.796506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2249 02:12:36.797357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2251 02:12:36.898775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2252 02:12:36.899639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2254 02:12:37.002312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2255 02:12:37.003169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2257 02:12:37.101908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2258 02:12:37.102751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2260 02:12:37.201495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2261 02:12:37.202410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2263 02:12:37.299776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2264 02:12:37.300567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2266 02:12:37.398505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2267 02:12:37.399338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2269 02:12:37.496193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2270 02:12:37.496997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2272 02:12:37.598604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2273 02:12:37.599411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2275 02:12:37.693867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2276 02:12:37.694657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2278 02:12:37.789478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2279 02:12:37.790355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2281 02:12:37.892924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2282 02:12:37.893721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2284 02:12:37.991398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2285 02:12:37.992221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2287 02:12:38.084989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2288 02:12:38.085892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2290 02:12:38.183985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2291 02:12:38.184816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2293 02:12:38.279058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2294 02:12:38.279898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2296 02:12:38.376788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2297 02:12:38.377870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2299 02:12:38.482302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2300 02:12:38.483154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2302 02:12:38.581395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2303 02:12:38.582285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2305 02:12:38.683561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2306 02:12:38.684402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2308 02:12:38.779141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2309 02:12:38.779983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2311 02:12:38.871958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2312 02:12:38.872954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2314 02:12:38.962430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2315 02:12:38.963297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2317 02:12:39.048422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2318 02:12:39.049372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2320 02:12:39.138483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2321 02:12:39.139324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2323 02:12:39.230010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2324 02:12:39.230928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2326 02:12:39.323486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2327 02:12:39.324382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2329 02:12:39.414305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2330 02:12:39.415185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2332 02:12:39.507549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2333 02:12:39.508503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2335 02:12:39.598063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2336 02:12:39.598953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2338 02:12:39.686305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2339 02:12:39.687591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2341 02:12:39.779138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2342 02:12:39.779780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2344 02:12:39.878265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2345 02:12:39.893170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2347 02:12:39.969174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2348 02:12:39.969997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2350 02:12:40.062936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2351 02:12:40.063756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2353 02:12:40.158746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2354 02:12:40.159562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2356 02:12:40.247704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2358 02:12:40.250886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2359 02:12:40.341643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2360 02:12:40.342461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2362 02:12:40.434805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2363 02:12:40.435611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2365 02:12:40.526945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2366 02:12:40.527505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2368 02:12:40.618476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2369 02:12:40.619253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2371 02:12:40.710930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2372 02:12:40.711769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2374 02:12:40.802381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2375 02:12:40.803175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2377 02:12:40.892959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2378 02:12:40.893765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2380 02:12:40.995395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2381 02:12:40.996574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2383 02:12:41.090667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2384 02:12:41.091258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2386 02:12:41.181667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2387 02:12:41.182494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2389 02:12:41.272278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2390 02:12:41.273252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2392 02:12:41.364205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2393 02:12:41.364837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2395 02:12:41.457472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2396 02:12:41.458452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2398 02:12:41.557510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2399 02:12:41.558319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2401 02:12:41.658695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2402 02:12:41.659534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2404 02:12:41.751488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2405 02:12:41.752354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2407 02:12:41.846031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2408 02:12:41.846834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2410 02:12:41.936655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2411 02:12:41.937755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2413 02:12:42.029212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2414 02:12:42.029851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2416 02:12:42.121423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2417 02:12:42.122096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2419 02:12:42.213648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2420 02:12:42.214521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2422 02:12:42.307280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2423 02:12:42.308069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2425 02:12:42.398038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2426 02:12:42.398850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2428 02:12:42.489082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2429 02:12:42.489908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2431 02:12:42.580863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2432 02:12:42.581642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2434 02:12:42.675457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2435 02:12:42.676221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2437 02:12:42.764914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2438 02:12:42.765712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2440 02:12:42.857536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2441 02:12:42.858350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2443 02:12:42.950923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2444 02:12:42.951708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2446 02:12:43.043906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2447 02:12:43.044763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2449 02:12:43.135844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2450 02:12:43.136440 + set +x
2451 02:12:43.137187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2453 02:12:43.139952 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 943474_1.6.2.4.5>
2454 02:12:43.140704 Received signal: <ENDRUN> 1_kselftest-dt 943474_1.6.2.4.5
2455 02:12:43.141168 Ending use of test pattern.
2456 02:12:43.141570 Ending test lava.1_kselftest-dt (943474_1.6.2.4.5), duration 85.71
2458 02:12:43.146170 <LAVA_TEST_RUNNER EXIT>
2459 02:12:43.146897 ok: lava_test_shell seems to have completed
2460 02:12:43.159881 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2461 02:12:43.161888 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2462 02:12:43.162565 end: 3 lava-test-retry (duration 00:01:27) [common]
2463 02:12:43.163391 start: 4 finalize (timeout 00:05:26) [common]
2464 02:12:43.164095 start: 4.1 power-off (timeout 00:00:30) [common]
2465 02:12:43.165345 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2466 02:12:43.200032 >> OK - accepted request
2467 02:12:43.202029 Returned 0 in 0 seconds
2468 02:12:43.303113 end: 4.1 power-off (duration 00:00:00) [common]
2470 02:12:43.304189 start: 4.2 read-feedback (timeout 00:05:26) [common]
2471 02:12:43.305043 Listened to connection for namespace 'common' for up to 1s
2472 02:12:43.305643 Listened to connection for namespace 'common' for up to 1s
2473 02:12:44.305855 Finalising connection for namespace 'common'
2474 02:12:44.306477 Disconnecting from shell: Finalise
2475 02:12:44.306899 / #
2476 02:12:44.407722 end: 4.2 read-feedback (duration 00:00:01) [common]
2477 02:12:44.408227 end: 4 finalize (duration 00:00:01) [common]
2478 02:12:44.408653 Cleaning after the job
2479 02:12:44.409044 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/ramdisk
2480 02:12:44.414311 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/kernel
2481 02:12:44.415651 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/dtb
2482 02:12:44.416569 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/nfsrootfs
2483 02:12:44.553302 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943474/tftp-deploy-q65hl3yh/modules
2484 02:12:44.562167 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/943474
2485 02:12:47.764761 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/943474
2486 02:12:47.765356 Job finished correctly