Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:32:58.940604 lava-dispatcher, installed at version: 2024.01
2 02:32:58.941360 start: 0 validate
3 02:32:58.941831 Start time: 2024-11-06 02:32:58.941802+00:00 (UTC)
4 02:32:58.942353 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:32:58.942882 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 02:32:58.983191 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:32:58.983722 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:32:59.012442 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:32:59.013039 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:33:00.061562 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:33:00.062066 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 02:33:00.099730 validate duration: 1.16
14 02:33:00.101258 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 02:33:00.101885 start: 1.1 download-retry (timeout 00:10:00) [common]
16 02:33:00.102469 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 02:33:00.103419 Not decompressing ramdisk as can be used compressed.
18 02:33:00.104189 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 02:33:00.104659 saving as /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/ramdisk/rootfs.cpio.gz
20 02:33:00.105153 total size: 8181887 (7 MB)
21 02:33:00.144343 progress 0 % (0 MB)
22 02:33:00.155863 progress 5 % (0 MB)
23 02:33:00.167088 progress 10 % (0 MB)
24 02:33:00.178701 progress 15 % (1 MB)
25 02:33:00.184534 progress 20 % (1 MB)
26 02:33:00.190095 progress 25 % (1 MB)
27 02:33:00.195212 progress 30 % (2 MB)
28 02:33:00.200748 progress 35 % (2 MB)
29 02:33:00.205926 progress 40 % (3 MB)
30 02:33:00.211593 progress 45 % (3 MB)
31 02:33:00.216834 progress 50 % (3 MB)
32 02:33:00.222340 progress 55 % (4 MB)
33 02:33:00.227540 progress 60 % (4 MB)
34 02:33:00.233129 progress 65 % (5 MB)
35 02:33:00.238272 progress 70 % (5 MB)
36 02:33:00.243726 progress 75 % (5 MB)
37 02:33:00.248817 progress 80 % (6 MB)
38 02:33:00.254282 progress 85 % (6 MB)
39 02:33:00.259363 progress 90 % (7 MB)
40 02:33:00.264978 progress 95 % (7 MB)
41 02:33:00.269805 progress 100 % (7 MB)
42 02:33:00.270459 7 MB downloaded in 0.17 s (47.20 MB/s)
43 02:33:00.271034 end: 1.1.1 http-download (duration 00:00:00) [common]
45 02:33:00.271959 end: 1.1 download-retry (duration 00:00:00) [common]
46 02:33:00.272314 start: 1.2 download-retry (timeout 00:10:00) [common]
47 02:33:00.272611 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 02:33:00.273104 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kernel/Image
49 02:33:00.273358 saving as /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/kernel/Image
50 02:33:00.273578 total size: 45779456 (43 MB)
51 02:33:00.273799 No compression specified
52 02:33:00.309238 progress 0 % (0 MB)
53 02:33:00.336549 progress 5 % (2 MB)
54 02:33:00.364361 progress 10 % (4 MB)
55 02:33:00.392179 progress 15 % (6 MB)
56 02:33:00.420165 progress 20 % (8 MB)
57 02:33:00.450238 progress 25 % (10 MB)
58 02:33:00.478100 progress 30 % (13 MB)
59 02:33:00.505680 progress 35 % (15 MB)
60 02:33:00.533526 progress 40 % (17 MB)
61 02:33:00.561371 progress 45 % (19 MB)
62 02:33:00.589393 progress 50 % (21 MB)
63 02:33:00.617441 progress 55 % (24 MB)
64 02:33:00.645542 progress 60 % (26 MB)
65 02:33:00.673433 progress 65 % (28 MB)
66 02:33:00.701070 progress 70 % (30 MB)
67 02:33:00.728953 progress 75 % (32 MB)
68 02:33:00.764898 progress 80 % (34 MB)
69 02:33:00.802981 progress 85 % (37 MB)
70 02:33:00.841002 progress 90 % (39 MB)
71 02:33:00.878183 progress 95 % (41 MB)
72 02:33:00.905875 progress 100 % (43 MB)
73 02:33:00.906398 43 MB downloaded in 0.63 s (68.99 MB/s)
74 02:33:00.906894 end: 1.2.1 http-download (duration 00:00:01) [common]
76 02:33:00.907726 end: 1.2 download-retry (duration 00:00:01) [common]
77 02:33:00.908029 start: 1.3 download-retry (timeout 00:09:59) [common]
78 02:33:00.908309 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 02:33:00.908787 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 02:33:00.909074 saving as /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/dtb/meson-g12b-a311d-libretech-cc.dtb
81 02:33:00.909287 total size: 54703 (0 MB)
82 02:33:00.909500 No compression specified
83 02:33:00.949353 progress 59 % (0 MB)
84 02:33:00.950205 progress 100 % (0 MB)
85 02:33:00.950771 0 MB downloaded in 0.04 s (1.26 MB/s)
86 02:33:00.951250 end: 1.3.1 http-download (duration 00:00:00) [common]
88 02:33:00.952103 end: 1.3 download-retry (duration 00:00:00) [common]
89 02:33:00.952374 start: 1.4 download-retry (timeout 00:09:59) [common]
90 02:33:00.952642 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 02:33:00.953107 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/modules.tar.xz
92 02:33:00.953361 saving as /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/modules/modules.tar
93 02:33:00.953568 total size: 11613264 (11 MB)
94 02:33:00.953778 Using unxz to decompress xz
95 02:33:00.989086 progress 0 % (0 MB)
96 02:33:01.056136 progress 5 % (0 MB)
97 02:33:01.131786 progress 10 % (1 MB)
98 02:33:01.229974 progress 15 % (1 MB)
99 02:33:01.321605 progress 20 % (2 MB)
100 02:33:01.400747 progress 25 % (2 MB)
101 02:33:01.476086 progress 30 % (3 MB)
102 02:33:01.555013 progress 35 % (3 MB)
103 02:33:01.627754 progress 40 % (4 MB)
104 02:33:01.704792 progress 45 % (5 MB)
105 02:33:01.790798 progress 50 % (5 MB)
106 02:33:01.869015 progress 55 % (6 MB)
107 02:33:01.957135 progress 60 % (6 MB)
108 02:33:02.037415 progress 65 % (7 MB)
109 02:33:02.117858 progress 70 % (7 MB)
110 02:33:02.197462 progress 75 % (8 MB)
111 02:33:02.281116 progress 80 % (8 MB)
112 02:33:02.361130 progress 85 % (9 MB)
113 02:33:02.439656 progress 90 % (9 MB)
114 02:33:02.517534 progress 95 % (10 MB)
115 02:33:02.594038 progress 100 % (11 MB)
116 02:33:02.606992 11 MB downloaded in 1.65 s (6.70 MB/s)
117 02:33:02.607598 end: 1.4.1 http-download (duration 00:00:02) [common]
119 02:33:02.609082 end: 1.4 download-retry (duration 00:00:02) [common]
120 02:33:02.609683 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 02:33:02.610259 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 02:33:02.610803 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 02:33:02.611357 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 02:33:02.612447 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h
125 02:33:02.613371 makedir: /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin
126 02:33:02.614069 makedir: /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/tests
127 02:33:02.614738 makedir: /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/results
128 02:33:02.615404 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-add-keys
129 02:33:02.616464 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-add-sources
130 02:33:02.617491 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-background-process-start
131 02:33:02.618520 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-background-process-stop
132 02:33:02.619614 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-common-functions
133 02:33:02.620684 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-echo-ipv4
134 02:33:02.621677 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-install-packages
135 02:33:02.622706 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-installed-packages
136 02:33:02.623684 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-os-build
137 02:33:02.624874 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-probe-channel
138 02:33:02.625887 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-probe-ip
139 02:33:02.626864 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-target-ip
140 02:33:02.627878 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-target-mac
141 02:33:02.629002 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-target-storage
142 02:33:02.630004 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-test-case
143 02:33:02.630982 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-test-event
144 02:33:02.631954 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-test-feedback
145 02:33:02.632983 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-test-raise
146 02:33:02.633952 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-test-reference
147 02:33:02.634925 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-test-runner
148 02:33:02.635936 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-test-set
149 02:33:02.637009 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-test-shell
150 02:33:02.638056 Updating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-install-packages (oe)
151 02:33:02.639101 Updating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/bin/lava-installed-packages (oe)
152 02:33:02.640023 Creating /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/environment
153 02:33:02.640817 LAVA metadata
154 02:33:02.641359 - LAVA_JOB_ID=943577
155 02:33:02.641832 - LAVA_DISPATCHER_IP=192.168.6.2
156 02:33:02.642543 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 02:33:02.644529 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 02:33:02.645164 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 02:33:02.645582 skipped lava-vland-overlay
160 02:33:02.646068 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 02:33:02.646574 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 02:33:02.646998 skipped lava-multinode-overlay
163 02:33:02.647478 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 02:33:02.648002 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 02:33:02.648486 Loading test definitions
166 02:33:02.649031 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 02:33:02.649468 Using /lava-943577 at stage 0
168 02:33:02.651638 uuid=943577_1.5.2.4.1 testdef=None
169 02:33:02.652210 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 02:33:02.652501 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 02:33:02.654329 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 02:33:02.655150 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 02:33:02.657419 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 02:33:02.658304 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 02:33:02.660510 runner path: /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/0/tests/0_dmesg test_uuid 943577_1.5.2.4.1
178 02:33:02.661140 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 02:33:02.661948 Creating lava-test-runner.conf files
181 02:33:02.662153 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/943577/lava-overlay-2rp4sr6h/lava-943577/0 for stage 0
182 02:33:02.662484 - 0_dmesg
183 02:33:02.662843 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 02:33:02.663130 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 02:33:02.686726 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 02:33:02.687126 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 02:33:02.687396 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 02:33:02.687662 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 02:33:02.687931 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 02:33:03.711972 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 02:33:03.712461 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 02:33:03.712716 extracting modules file /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943577/extract-overlay-ramdisk-lw5i4jfz/ramdisk
193 02:33:05.048029 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 02:33:05.048533 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 02:33:05.048859 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943577/compress-overlay-325wbjmj/overlay-1.5.2.5.tar.gz to ramdisk
196 02:33:05.049117 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943577/compress-overlay-325wbjmj/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/943577/extract-overlay-ramdisk-lw5i4jfz/ramdisk
197 02:33:05.081730 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 02:33:05.082163 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 02:33:05.082492 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 02:33:05.082766 Converting downloaded kernel to a uImage
201 02:33:05.083116 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/kernel/Image /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/kernel/uImage
202 02:33:05.559877 output: Image Name:
203 02:33:05.560334 output: Created: Wed Nov 6 02:33:05 2024
204 02:33:05.560549 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 02:33:05.560756 output: Data Size: 45779456 Bytes = 44706.50 KiB = 43.66 MiB
206 02:33:05.560957 output: Load Address: 01080000
207 02:33:05.561157 output: Entry Point: 01080000
208 02:33:05.561355 output:
209 02:33:05.561689 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 02:33:05.561963 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 02:33:05.562235 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 02:33:05.562490 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 02:33:05.562749 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 02:33:05.563005 Building ramdisk /var/lib/lava/dispatcher/tmp/943577/extract-overlay-ramdisk-lw5i4jfz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/943577/extract-overlay-ramdisk-lw5i4jfz/ramdisk
215 02:33:07.892780 >> 181555 blocks
216 02:33:16.293835 Adding RAMdisk u-boot header.
217 02:33:16.294482 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/943577/extract-overlay-ramdisk-lw5i4jfz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/943577/extract-overlay-ramdisk-lw5i4jfz/ramdisk.cpio.gz.uboot
218 02:33:16.566625 output: Image Name:
219 02:33:16.567041 output: Created: Wed Nov 6 02:33:16 2024
220 02:33:16.567252 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 02:33:16.567457 output: Data Size: 26057353 Bytes = 25446.63 KiB = 24.85 MiB
222 02:33:16.567658 output: Load Address: 00000000
223 02:33:16.567858 output: Entry Point: 00000000
224 02:33:16.568246 output:
225 02:33:16.569342 rename /var/lib/lava/dispatcher/tmp/943577/extract-overlay-ramdisk-lw5i4jfz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/ramdisk/ramdisk.cpio.gz.uboot
226 02:33:16.570116 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 02:33:16.570706 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 02:33:16.571278 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 02:33:16.571795 No LXC device requested
230 02:33:16.572384 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 02:33:16.572941 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 02:33:16.573479 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 02:33:16.573928 Checking files for TFTP limit of 4294967296 bytes.
234 02:33:16.576885 end: 1 tftp-deploy (duration 00:00:16) [common]
235 02:33:16.577516 start: 2 uboot-action (timeout 00:05:00) [common]
236 02:33:16.578090 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 02:33:16.578636 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 02:33:16.579186 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 02:33:16.579759 Using kernel file from prepare-kernel: 943577/tftp-deploy-7mmgm9ic/kernel/uImage
240 02:33:16.580473 substitutions:
241 02:33:16.580923 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 02:33:16.581361 - {DTB_ADDR}: 0x01070000
243 02:33:16.581798 - {DTB}: 943577/tftp-deploy-7mmgm9ic/dtb/meson-g12b-a311d-libretech-cc.dtb
244 02:33:16.582236 - {INITRD}: 943577/tftp-deploy-7mmgm9ic/ramdisk/ramdisk.cpio.gz.uboot
245 02:33:16.582671 - {KERNEL_ADDR}: 0x01080000
246 02:33:16.583102 - {KERNEL}: 943577/tftp-deploy-7mmgm9ic/kernel/uImage
247 02:33:16.583536 - {LAVA_MAC}: None
248 02:33:16.584029 - {PRESEED_CONFIG}: None
249 02:33:16.584465 - {PRESEED_LOCAL}: None
250 02:33:16.584898 - {RAMDISK_ADDR}: 0x08000000
251 02:33:16.585322 - {RAMDISK}: 943577/tftp-deploy-7mmgm9ic/ramdisk/ramdisk.cpio.gz.uboot
252 02:33:16.585752 - {ROOT_PART}: None
253 02:33:16.586179 - {ROOT}: None
254 02:33:16.586608 - {SERVER_IP}: 192.168.6.2
255 02:33:16.587040 - {TEE_ADDR}: 0x83000000
256 02:33:16.587466 - {TEE}: None
257 02:33:16.587894 Parsed boot commands:
258 02:33:16.588371 - setenv autoload no
259 02:33:16.588799 - setenv initrd_high 0xffffffff
260 02:33:16.589224 - setenv fdt_high 0xffffffff
261 02:33:16.589649 - dhcp
262 02:33:16.590074 - setenv serverip 192.168.6.2
263 02:33:16.590502 - tftpboot 0x01080000 943577/tftp-deploy-7mmgm9ic/kernel/uImage
264 02:33:16.590928 - tftpboot 0x08000000 943577/tftp-deploy-7mmgm9ic/ramdisk/ramdisk.cpio.gz.uboot
265 02:33:16.591353 - tftpboot 0x01070000 943577/tftp-deploy-7mmgm9ic/dtb/meson-g12b-a311d-libretech-cc.dtb
266 02:33:16.591779 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 02:33:16.592248 - bootm 0x01080000 0x08000000 0x01070000
268 02:33:16.592792 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 02:33:16.594409 start: 2.3 connect-device (timeout 00:05:00) [common]
271 02:33:16.594891 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 02:33:16.611019 Setting prompt string to ['lava-test: # ']
273 02:33:16.612627 end: 2.3 connect-device (duration 00:00:00) [common]
274 02:33:16.613292 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 02:33:16.613882 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 02:33:16.614541 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 02:33:16.616038 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 02:33:16.653504 >> OK - accepted request
279 02:33:16.655877 Returned 0 in 0 seconds
280 02:33:16.757095 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 02:33:16.758785 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 02:33:16.759394 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 02:33:16.759943 Setting prompt string to ['Hit any key to stop autoboot']
285 02:33:16.760486 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 02:33:16.762189 Trying 192.168.56.21...
287 02:33:16.762703 Connected to conserv1.
288 02:33:16.763145 Escape character is '^]'.
289 02:33:16.763606
290 02:33:16.764103 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 02:33:16.764573
292 02:33:28.013443 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 02:33:28.013997 bl2_stage_init 0x01
294 02:33:28.014269 bl2_stage_init 0x81
295 02:33:28.018998 hw id: 0x0000 - pwm id 0x01
296 02:33:28.019489 bl2_stage_init 0xc1
297 02:33:28.019788 bl2_stage_init 0x02
298 02:33:28.020123
299 02:33:28.024544 L0:00000000
300 02:33:28.024982 L1:20000703
301 02:33:28.025230 L2:00008067
302 02:33:28.025473 L3:14000000
303 02:33:28.030213 B2:00402000
304 02:33:28.030943 B1:e0f83180
305 02:33:28.031471
306 02:33:28.032006 TE: 58124
307 02:33:28.032281
308 02:33:28.035718 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 02:33:28.036483
310 02:33:28.037036 Board ID = 1
311 02:33:28.041390 Set A53 clk to 24M
312 02:33:28.042074 Set A73 clk to 24M
313 02:33:28.042581 Set clk81 to 24M
314 02:33:28.046947 A53 clk: 1200 MHz
315 02:33:28.047632 A73 clk: 1200 MHz
316 02:33:28.048437 CLK81: 166.6M
317 02:33:28.048988 smccc: 00012a92
318 02:33:28.052495 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 02:33:28.058270 board id: 1
320 02:33:28.064214 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 02:33:28.074584 fw parse done
322 02:33:28.080523 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 02:33:28.123225 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 02:33:28.134116 PIEI prepare done
325 02:33:28.134766 fastboot data load
326 02:33:28.135319 fastboot data verify
327 02:33:28.139680 verify result: 266
328 02:33:28.145307 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 02:33:28.145677 LPDDR4 probe
330 02:33:28.145947 ddr clk to 1584MHz
331 02:33:28.153307 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 02:33:28.190830
333 02:33:28.191542 dmc_version 0001
334 02:33:28.197469 Check phy result
335 02:33:28.203236 INFO : End of CA training
336 02:33:28.203890 INFO : End of initialization
337 02:33:28.208874 INFO : Training has run successfully!
338 02:33:28.209510 Check phy result
339 02:33:28.214450 INFO : End of initialization
340 02:33:28.215069 INFO : End of read enable training
341 02:33:28.217733 INFO : End of fine write leveling
342 02:33:28.223347 INFO : End of Write leveling coarse delay
343 02:33:28.228969 INFO : Training has run successfully!
344 02:33:28.229593 Check phy result
345 02:33:28.230125 INFO : End of initialization
346 02:33:28.234477 INFO : End of read dq deskew training
347 02:33:28.240111 INFO : End of MPR read delay center optimization
348 02:33:28.240731 INFO : End of write delay center optimization
349 02:33:28.245705 INFO : End of read delay center optimization
350 02:33:28.251263 INFO : End of max read latency training
351 02:33:28.251886 INFO : Training has run successfully!
352 02:33:28.256778 1D training succeed
353 02:33:28.262961 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 02:33:28.310443 Check phy result
355 02:33:28.311170 INFO : End of initialization
356 02:33:28.332113 INFO : End of 2D read delay Voltage center optimization
357 02:33:28.352317 INFO : End of 2D read delay Voltage center optimization
358 02:33:28.404417 INFO : End of 2D write delay Voltage center optimization
359 02:33:28.453673 INFO : End of 2D write delay Voltage center optimization
360 02:33:28.459148 INFO : Training has run successfully!
361 02:33:28.459749
362 02:33:28.460341 channel==0
363 02:33:28.464742 RxClkDly_Margin_A0==88 ps 9
364 02:33:28.465330 TxDqDly_Margin_A0==98 ps 10
365 02:33:28.468099 RxClkDly_Margin_A1==88 ps 9
366 02:33:28.468669 TxDqDly_Margin_A1==98 ps 10
367 02:33:28.473745 TrainedVREFDQ_A0==74
368 02:33:28.474359 TrainedVREFDQ_A1==74
369 02:33:28.474872 VrefDac_Margin_A0==25
370 02:33:28.479268 DeviceVref_Margin_A0==40
371 02:33:28.479859 VrefDac_Margin_A1==25
372 02:33:28.484938 DeviceVref_Margin_A1==40
373 02:33:28.485509
374 02:33:28.486057
375 02:33:28.486588 channel==1
376 02:33:28.487093 RxClkDly_Margin_A0==98 ps 10
377 02:33:28.490460 TxDqDly_Margin_A0==98 ps 10
378 02:33:28.491033 RxClkDly_Margin_A1==88 ps 9
379 02:33:28.496083 TxDqDly_Margin_A1==88 ps 9
380 02:33:28.496667 TrainedVREFDQ_A0==76
381 02:33:28.497177 TrainedVREFDQ_A1==77
382 02:33:28.501731 VrefDac_Margin_A0==22
383 02:33:28.502308 DeviceVref_Margin_A0==38
384 02:33:28.507306 VrefDac_Margin_A1==24
385 02:33:28.507884 DeviceVref_Margin_A1==37
386 02:33:28.508442
387 02:33:28.512929 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 02:33:28.513531
389 02:33:28.540866 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 02:33:28.546477 2D training succeed
391 02:33:28.552086 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 02:33:28.552723 auto size-- 65535DDR cs0 size: 2048MB
393 02:33:28.557684 DDR cs1 size: 2048MB
394 02:33:28.558276 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 02:33:28.563295 cs0 DataBus test pass
396 02:33:28.563895 cs1 DataBus test pass
397 02:33:28.564489 cs0 AddrBus test pass
398 02:33:28.568928 cs1 AddrBus test pass
399 02:33:28.569511
400 02:33:28.570046 100bdlr_step_size ps== 420
401 02:33:28.570590 result report
402 02:33:28.574467 boot times 0Enable ddr reg access
403 02:33:28.582127 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 02:33:28.595587 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 02:33:29.169385 0.0;M3 CHK:0;cm4_sp_mode 0
406 02:33:29.170178 MVN_1=0x00000000
407 02:33:29.174797 MVN_2=0x00000000
408 02:33:29.180501 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 02:33:29.181048 OPS=0x10
410 02:33:29.181559 ring efuse init
411 02:33:29.182059 chipver efuse init
412 02:33:29.186084 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 02:33:29.191688 [0.018961 Inits done]
414 02:33:29.192269 secure task start!
415 02:33:29.192777 high task start!
416 02:33:29.196305 low task start!
417 02:33:29.196828 run into bl31
418 02:33:29.202945 NOTICE: BL31: v1.3(release):4fc40b1
419 02:33:29.210738 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 02:33:29.211281 NOTICE: BL31: G12A normal boot!
421 02:33:29.236190 NOTICE: BL31: BL33 decompress pass
422 02:33:29.241865 ERROR: Error initializing runtime service opteed_fast
423 02:33:30.474821
424 02:33:30.475612
425 02:33:30.483182 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 02:33:30.483770
427 02:33:30.484346 Model: Libre Computer AML-A311D-CC Alta
428 02:33:30.691552 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 02:33:30.714931 DRAM: 2 GiB (effective 3.8 GiB)
430 02:33:30.857975 Core: 408 devices, 31 uclasses, devicetree: separate
431 02:33:30.863756 WDT: Not starting watchdog@f0d0
432 02:33:30.896111 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 02:33:30.908469 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 02:33:30.913448 ** Bad device specification mmc 0 **
435 02:33:30.923786 Card did not respond to voltage select! : -110
436 02:33:30.931427 ** Bad device specification mmc 0 **
437 02:33:30.932011 Couldn't find partition mmc 0
438 02:33:30.939769 Card did not respond to voltage select! : -110
439 02:33:30.945287 ** Bad device specification mmc 0 **
440 02:33:30.945839 Couldn't find partition mmc 0
441 02:33:30.950351 Error: could not access storage.
442 02:33:32.213835 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 02:33:32.214644 bl2_stage_init 0x81
444 02:33:32.219342 hw id: 0x0000 - pwm id 0x01
445 02:33:32.219935 bl2_stage_init 0xc1
446 02:33:32.220672 bl2_stage_init 0x02
447 02:33:32.221160
448 02:33:32.224930 L0:00000000
449 02:33:32.225438 L1:20000703
450 02:33:32.225893 L2:00008067
451 02:33:32.226337 L3:14000000
452 02:33:32.226778 B2:00402000
453 02:33:32.227727 B1:e0f83180
454 02:33:32.228366
455 02:33:32.228832 TE: 58141
456 02:33:32.229285
457 02:33:32.238957 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 02:33:32.239453
459 02:33:32.239908 Board ID = 1
460 02:33:32.240395 Set A53 clk to 24M
461 02:33:32.240839 Set A73 clk to 24M
462 02:33:32.244532 Set clk81 to 24M
463 02:33:32.245021 A53 clk: 1200 MHz
464 02:33:32.245468 A73 clk: 1200 MHz
465 02:33:32.250087 CLK81: 166.6M
466 02:33:32.250586 smccc: 00012aa3
467 02:33:32.255680 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 02:33:32.256207 board id: 1
469 02:33:32.264361 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 02:33:32.274917 fw parse done
471 02:33:32.280859 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 02:33:32.323494 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 02:33:32.334446 PIEI prepare done
474 02:33:32.334970 fastboot data load
475 02:33:32.335436 fastboot data verify
476 02:33:32.340346 verify result: 266
477 02:33:32.345664 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 02:33:32.346161 LPDDR4 probe
479 02:33:32.346613 ddr clk to 1584MHz
480 02:33:32.353648 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 02:33:32.390908
482 02:33:32.391413 dmc_version 0001
483 02:33:32.397562 Check phy result
484 02:33:32.403426 INFO : End of CA training
485 02:33:32.403926 INFO : End of initialization
486 02:33:32.409070 INFO : Training has run successfully!
487 02:33:32.409620 Check phy result
488 02:33:32.414650 INFO : End of initialization
489 02:33:32.415135 INFO : End of read enable training
490 02:33:32.420346 INFO : End of fine write leveling
491 02:33:32.425836 INFO : End of Write leveling coarse delay
492 02:33:32.426297 INFO : Training has run successfully!
493 02:33:32.426720 Check phy result
494 02:33:32.431439 INFO : End of initialization
495 02:33:32.431904 INFO : End of read dq deskew training
496 02:33:32.437027 INFO : End of MPR read delay center optimization
497 02:33:32.442599 INFO : End of write delay center optimization
498 02:33:32.448527 INFO : End of read delay center optimization
499 02:33:32.449087 INFO : End of max read latency training
500 02:33:32.453943 INFO : Training has run successfully!
501 02:33:32.454488 1D training succeed
502 02:33:32.463043 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 02:33:32.510652 Check phy result
504 02:33:32.511205 INFO : End of initialization
505 02:33:32.532451 INFO : End of 2D read delay Voltage center optimization
506 02:33:32.552596 INFO : End of 2D read delay Voltage center optimization
507 02:33:32.604596 INFO : End of 2D write delay Voltage center optimization
508 02:33:32.654309 INFO : End of 2D write delay Voltage center optimization
509 02:33:32.659551 INFO : Training has run successfully!
510 02:33:32.660059
511 02:33:32.660503 channel==0
512 02:33:32.665140 RxClkDly_Margin_A0==88 ps 9
513 02:33:32.665602 TxDqDly_Margin_A0==98 ps 10
514 02:33:32.670748 RxClkDly_Margin_A1==88 ps 9
515 02:33:32.671200 TxDqDly_Margin_A1==88 ps 9
516 02:33:32.671625 TrainedVREFDQ_A0==74
517 02:33:32.676403 TrainedVREFDQ_A1==74
518 02:33:32.676867 VrefDac_Margin_A0==25
519 02:33:32.677277 DeviceVref_Margin_A0==40
520 02:33:32.681938 VrefDac_Margin_A1==25
521 02:33:32.682388 DeviceVref_Margin_A1==40
522 02:33:32.682801
523 02:33:32.683203
524 02:33:32.683605 channel==1
525 02:33:32.687542 RxClkDly_Margin_A0==98 ps 10
526 02:33:32.688025 TxDqDly_Margin_A0==98 ps 10
527 02:33:32.693124 RxClkDly_Margin_A1==88 ps 9
528 02:33:32.693577 TxDqDly_Margin_A1==88 ps 9
529 02:33:32.698727 TrainedVREFDQ_A0==77
530 02:33:32.699194 TrainedVREFDQ_A1==77
531 02:33:32.699612 VrefDac_Margin_A0==22
532 02:33:32.704368 DeviceVref_Margin_A0==37
533 02:33:32.704818 VrefDac_Margin_A1==24
534 02:33:32.709979 DeviceVref_Margin_A1==37
535 02:33:32.710503
536 02:33:32.710928 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 02:33:32.711336
538 02:33:32.743498 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 02:33:32.744046 2D training succeed
540 02:33:32.749099 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 02:33:32.754747 auto size-- 65535DDR cs0 size: 2048MB
542 02:33:32.755237 DDR cs1 size: 2048MB
543 02:33:32.760428 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 02:33:32.760903 cs0 DataBus test pass
545 02:33:32.765936 cs1 DataBus test pass
546 02:33:32.766399 cs0 AddrBus test pass
547 02:33:32.766815 cs1 AddrBus test pass
548 02:33:32.767218
549 02:33:32.771533 100bdlr_step_size ps== 420
550 02:33:32.772042 result report
551 02:33:32.777158 boot times 0Enable ddr reg access
552 02:33:32.782461 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 02:33:32.795873 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 02:33:33.369648 0.0;M3 CHK:0;cm4_sp_mode 0
555 02:33:33.370272 MVN_1=0x00000000
556 02:33:33.375068 MVN_2=0x00000000
557 02:33:33.380858 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 02:33:33.381399 OPS=0x10
559 02:33:33.381867 ring efuse init
560 02:33:33.382277 chipver efuse init
561 02:33:33.386465 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 02:33:33.392054 [0.018961 Inits done]
563 02:33:33.392520 secure task start!
564 02:33:33.392912 high task start!
565 02:33:33.396567 low task start!
566 02:33:33.397004 run into bl31
567 02:33:33.403263 NOTICE: BL31: v1.3(release):4fc40b1
568 02:33:33.411119 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 02:33:33.411655 NOTICE: BL31: G12A normal boot!
570 02:33:33.436439 NOTICE: BL31: BL33 decompress pass
571 02:33:33.442073 ERROR: Error initializing runtime service opteed_fast
572 02:33:34.675216
573 02:33:34.675842
574 02:33:34.683528 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 02:33:34.684034
576 02:33:34.684462 Model: Libre Computer AML-A311D-CC Alta
577 02:33:34.892159 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 02:33:34.915295 DRAM: 2 GiB (effective 3.8 GiB)
579 02:33:35.058430 Core: 408 devices, 31 uclasses, devicetree: separate
580 02:33:35.064261 WDT: Not starting watchdog@f0d0
581 02:33:35.096584 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 02:33:35.109004 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 02:33:35.113965 ** Bad device specification mmc 0 **
584 02:33:35.124238 Card did not respond to voltage select! : -110
585 02:33:35.131928 ** Bad device specification mmc 0 **
586 02:33:35.132433 Couldn't find partition mmc 0
587 02:33:35.140241 Card did not respond to voltage select! : -110
588 02:33:35.145790 ** Bad device specification mmc 0 **
589 02:33:35.146240 Couldn't find partition mmc 0
590 02:33:35.150911 Error: could not access storage.
591 02:33:35.581547 Net: eth0: ethernet@ff3f0000
592 02:33:35.582175 starting USB...
593 02:33:35.745163 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 02:33:35.745745 Starting the controller
595 02:33:35.751971 USB XHCI 1.10
596 02:33:37.465660 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 02:33:37.466291 bl2_stage_init 0x01
598 02:33:37.466716 bl2_stage_init 0x81
599 02:33:37.471142 hw id: 0x0000 - pwm id 0x01
600 02:33:37.471589 bl2_stage_init 0xc1
601 02:33:37.472034 bl2_stage_init 0x02
602 02:33:37.472447
603 02:33:37.476737 L0:00000000
604 02:33:37.477172 L1:20000703
605 02:33:37.477577 L2:00008067
606 02:33:37.477976 L3:14000000
607 02:33:37.479726 B2:00402000
608 02:33:37.480187 B1:e0f83180
609 02:33:37.480591
610 02:33:37.480991 TE: 58159
611 02:33:37.481393
612 02:33:37.490975 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 02:33:37.491445
614 02:33:37.491858 Board ID = 1
615 02:33:37.492292 Set A53 clk to 24M
616 02:33:37.492689 Set A73 clk to 24M
617 02:33:37.496495 Set clk81 to 24M
618 02:33:37.496935 A53 clk: 1200 MHz
619 02:33:37.497339 A73 clk: 1200 MHz
620 02:33:37.502110 CLK81: 166.6M
621 02:33:37.502542 smccc: 00012ab5
622 02:33:37.507711 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 02:33:37.508173 board id: 1
624 02:33:37.516252 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 02:33:37.526870 fw parse done
626 02:33:37.532898 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 02:33:37.575523 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 02:33:37.586366 PIEI prepare done
629 02:33:37.586811 fastboot data load
630 02:33:37.587218 fastboot data verify
631 02:33:37.591976 verify result: 266
632 02:33:37.597560 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 02:33:37.597996 LPDDR4 probe
634 02:33:37.598396 ddr clk to 1584MHz
635 02:33:37.605601 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 02:33:37.642868
637 02:33:37.643393 dmc_version 0001
638 02:33:37.649541 Check phy result
639 02:33:37.655372 INFO : End of CA training
640 02:33:37.655803 INFO : End of initialization
641 02:33:37.660985 INFO : Training has run successfully!
642 02:33:37.661418 Check phy result
643 02:33:37.666512 INFO : End of initialization
644 02:33:37.666941 INFO : End of read enable training
645 02:33:37.672144 INFO : End of fine write leveling
646 02:33:37.677740 INFO : End of Write leveling coarse delay
647 02:33:37.678165 INFO : Training has run successfully!
648 02:33:37.678564 Check phy result
649 02:33:37.683331 INFO : End of initialization
650 02:33:37.683759 INFO : End of read dq deskew training
651 02:33:37.688960 INFO : End of MPR read delay center optimization
652 02:33:37.694513 INFO : End of write delay center optimization
653 02:33:37.700141 INFO : End of read delay center optimization
654 02:33:37.700579 INFO : End of max read latency training
655 02:33:37.705788 INFO : Training has run successfully!
656 02:33:37.706223 1D training succeed
657 02:33:37.714997 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 02:33:37.762591 Check phy result
659 02:33:37.763098 INFO : End of initialization
660 02:33:37.785153 INFO : End of 2D read delay Voltage center optimization
661 02:33:37.805072 INFO : End of 2D read delay Voltage center optimization
662 02:33:37.856593 INFO : End of 2D write delay Voltage center optimization
663 02:33:37.906042 INFO : End of 2D write delay Voltage center optimization
664 02:33:37.911544 INFO : Training has run successfully!
665 02:33:37.912227
666 02:33:37.912694 channel==0
667 02:33:37.917106 RxClkDly_Margin_A0==88 ps 9
668 02:33:37.917550 TxDqDly_Margin_A0==98 ps 10
669 02:33:37.922702 RxClkDly_Margin_A1==88 ps 9
670 02:33:37.923140 TxDqDly_Margin_A1==88 ps 9
671 02:33:37.923543 TrainedVREFDQ_A0==74
672 02:33:37.928285 TrainedVREFDQ_A1==74
673 02:33:37.928720 VrefDac_Margin_A0==25
674 02:33:37.929117 DeviceVref_Margin_A0==40
675 02:33:37.933963 VrefDac_Margin_A1==24
676 02:33:37.934436 DeviceVref_Margin_A1==40
677 02:33:37.934842
678 02:33:37.935242
679 02:33:37.935639 channel==1
680 02:33:37.939508 RxClkDly_Margin_A0==88 ps 9
681 02:33:37.939947 TxDqDly_Margin_A0==88 ps 9
682 02:33:37.945085 RxClkDly_Margin_A1==88 ps 9
683 02:33:37.945535 TxDqDly_Margin_A1==88 ps 9
684 02:33:37.950681 TrainedVREFDQ_A0==76
685 02:33:37.951122 TrainedVREFDQ_A1==77
686 02:33:37.951526 VrefDac_Margin_A0==23
687 02:33:37.956283 DeviceVref_Margin_A0==38
688 02:33:37.956716 VrefDac_Margin_A1==24
689 02:33:37.957118 DeviceVref_Margin_A1==37
690 02:33:37.961903
691 02:33:37.962436 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 02:33:37.962907
693 02:33:37.995500 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000019 00000019 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 02:33:37.996080 2D training succeed
695 02:33:38.001098 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 02:33:38.006679 auto size-- 65535DDR cs0 size: 2048MB
697 02:33:38.007125 DDR cs1 size: 2048MB
698 02:33:38.012338 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 02:33:38.012776 cs0 DataBus test pass
700 02:33:38.017897 cs1 DataBus test pass
701 02:33:38.018330 cs0 AddrBus test pass
702 02:33:38.018734 cs1 AddrBus test pass
703 02:33:38.019133
704 02:33:38.023467 100bdlr_step_size ps== 420
705 02:33:38.023906 result report
706 02:33:38.029072 boot times 0Enable ddr reg access
707 02:33:38.034458 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 02:33:38.047756 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 02:33:38.621394 0.0;M3 CHK:0;cm4_sp_mode 0
710 02:33:38.622060 MVN_1=0x00000000
711 02:33:38.626912 MVN_2=0x00000000
712 02:33:38.632652 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 02:33:38.633213 OPS=0x10
714 02:33:38.633656 ring efuse init
715 02:33:38.634087 chipver efuse init
716 02:33:38.640874 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 02:33:38.641405 [0.018961 Inits done]
718 02:33:38.641838 secure task start!
719 02:33:38.648383 high task start!
720 02:33:38.648879 low task start!
721 02:33:38.649310 run into bl31
722 02:33:38.655032 NOTICE: BL31: v1.3(release):4fc40b1
723 02:33:38.662842 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 02:33:38.663345 NOTICE: BL31: G12A normal boot!
725 02:33:38.688828 NOTICE: BL31: BL33 decompress pass
726 02:33:38.694540 ERROR: Error initializing runtime service opteed_fast
727 02:33:39.927361
728 02:33:39.928104
729 02:33:39.935796 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 02:33:39.936488
731 02:33:39.936941 Model: Libre Computer AML-A311D-CC Alta
732 02:33:40.144230 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 02:33:40.167532 DRAM: 2 GiB (effective 3.8 GiB)
734 02:33:40.310485 Core: 408 devices, 31 uclasses, devicetree: separate
735 02:33:40.316322 WDT: Not starting watchdog@f0d0
736 02:33:40.348581 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 02:33:40.361021 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 02:33:40.366022 ** Bad device specification mmc 0 **
739 02:33:40.376376 Card did not respond to voltage select! : -110
740 02:33:40.384078 ** Bad device specification mmc 0 **
741 02:33:40.384626 Couldn't find partition mmc 0
742 02:33:40.392332 Card did not respond to voltage select! : -110
743 02:33:40.397879 ** Bad device specification mmc 0 **
744 02:33:40.398408 Couldn't find partition mmc 0
745 02:33:40.402929 Error: could not access storage.
746 02:33:40.745548 Net: eth0: ethernet@ff3f0000
747 02:33:40.746221 starting USB...
748 02:33:40.997320 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 02:33:40.998240 Starting the controller
750 02:33:41.004265 USB XHCI 1.10
751 02:33:43.145577 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 02:33:43.146006 bl2_stage_init 0x01
753 02:33:43.146257 bl2_stage_init 0x81
754 02:33:43.151108 hw id: 0x0000 - pwm id 0x01
755 02:33:43.151529 bl2_stage_init 0xc1
756 02:33:43.151871 bl2_stage_init 0x02
757 02:33:43.152246
758 02:33:43.156581 L0:00000000
759 02:33:43.156875 L1:20000703
760 02:33:43.157108 L2:00008067
761 02:33:43.157330 L3:14000000
762 02:33:43.159589 B2:00402000
763 02:33:43.160014 B1:e0f83180
764 02:33:43.160374
765 02:33:43.160726 TE: 58159
766 02:33:43.161069
767 02:33:43.170737 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 02:33:43.171191
769 02:33:43.171445 Board ID = 1
770 02:33:43.171663 Set A53 clk to 24M
771 02:33:43.171883 Set A73 clk to 24M
772 02:33:43.176325 Set clk81 to 24M
773 02:33:43.176860 A53 clk: 1200 MHz
774 02:33:43.177324 A73 clk: 1200 MHz
775 02:33:43.179930 CLK81: 166.6M
776 02:33:43.180492 smccc: 00012ab5
777 02:33:43.185514 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 02:33:43.191090 board id: 1
779 02:33:43.196002 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 02:33:43.206658 fw parse done
781 02:33:43.212632 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 02:33:43.255269 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 02:33:43.266305 PIEI prepare done
784 02:33:43.266819 fastboot data load
785 02:33:43.267292 fastboot data verify
786 02:33:43.271892 verify result: 266
787 02:33:43.277425 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 02:33:43.277934 LPDDR4 probe
789 02:33:43.278387 ddr clk to 1584MHz
790 02:33:43.285327 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 02:33:43.322577
792 02:33:43.323089 dmc_version 0001
793 02:33:43.329381 Check phy result
794 02:33:43.335190 INFO : End of CA training
795 02:33:43.335688 INFO : End of initialization
796 02:33:43.340950 INFO : Training has run successfully!
797 02:33:43.341564 Check phy result
798 02:33:43.346517 INFO : End of initialization
799 02:33:43.347080 INFO : End of read enable training
800 02:33:43.352113 INFO : End of fine write leveling
801 02:33:43.357752 INFO : End of Write leveling coarse delay
802 02:33:43.358340 INFO : Training has run successfully!
803 02:33:43.358811 Check phy result
804 02:33:43.363370 INFO : End of initialization
805 02:33:43.363932 INFO : End of read dq deskew training
806 02:33:43.368965 INFO : End of MPR read delay center optimization
807 02:33:43.374400 INFO : End of write delay center optimization
808 02:33:43.380045 INFO : End of read delay center optimization
809 02:33:43.380613 INFO : End of max read latency training
810 02:33:43.385616 INFO : Training has run successfully!
811 02:33:43.386182 1D training succeed
812 02:33:43.394763 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 02:33:43.442396 Check phy result
814 02:33:43.443001 INFO : End of initialization
815 02:33:43.463976 INFO : End of 2D read delay Voltage center optimization
816 02:33:43.484068 INFO : End of 2D read delay Voltage center optimization
817 02:33:43.536008 INFO : End of 2D write delay Voltage center optimization
818 02:33:43.585175 INFO : End of 2D write delay Voltage center optimization
819 02:33:43.590761 INFO : Training has run successfully!
820 02:33:43.591327
821 02:33:43.591803 channel==0
822 02:33:43.596352 RxClkDly_Margin_A0==88 ps 9
823 02:33:43.596907 TxDqDly_Margin_A0==98 ps 10
824 02:33:43.601949 RxClkDly_Margin_A1==88 ps 9
825 02:33:43.602503 TxDqDly_Margin_A1==88 ps 9
826 02:33:43.602970 TrainedVREFDQ_A0==74
827 02:33:43.607557 TrainedVREFDQ_A1==74
828 02:33:43.608152 VrefDac_Margin_A0==25
829 02:33:43.608624 DeviceVref_Margin_A0==40
830 02:33:43.613144 VrefDac_Margin_A1==25
831 02:33:43.613697 DeviceVref_Margin_A1==40
832 02:33:43.614158
833 02:33:43.614611
834 02:33:43.615059 channel==1
835 02:33:43.618762 RxClkDly_Margin_A0==98 ps 10
836 02:33:43.619318 TxDqDly_Margin_A0==98 ps 10
837 02:33:43.624371 RxClkDly_Margin_A1==98 ps 10
838 02:33:43.624929 TxDqDly_Margin_A1==88 ps 9
839 02:33:43.629988 TrainedVREFDQ_A0==77
840 02:33:43.630595 TrainedVREFDQ_A1==77
841 02:33:43.631069 VrefDac_Margin_A0==22
842 02:33:43.635542 DeviceVref_Margin_A0==37
843 02:33:43.636146 VrefDac_Margin_A1==22
844 02:33:43.641144 DeviceVref_Margin_A1==37
845 02:33:43.641679
846 02:33:43.642114 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 02:33:43.642543
848 02:33:43.674750 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000018 dram_vref_reg_value 0x 00000060
849 02:33:43.675376 2D training succeed
850 02:33:43.680394 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 02:33:43.685923 auto size-- 65535DDR cs0 size: 2048MB
852 02:33:43.686464 DDR cs1 size: 2048MB
853 02:33:43.691513 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 02:33:43.692094 cs0 DataBus test pass
855 02:33:43.697131 cs1 DataBus test pass
856 02:33:43.697691 cs0 AddrBus test pass
857 02:33:43.698140 cs1 AddrBus test pass
858 02:33:43.698578
859 02:33:43.702714 100bdlr_step_size ps== 420
860 02:33:43.703261 result report
861 02:33:43.708367 boot times 0Enable ddr reg access
862 02:33:43.713685 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 02:33:43.727114 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 02:33:44.299169 0.0;M3 CHK:0;cm4_sp_mode 0
865 02:33:44.299834 MVN_1=0x00000000
866 02:33:44.304664 MVN_2=0x00000000
867 02:33:44.310427 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 02:33:44.310964 OPS=0x10
869 02:33:44.311433 ring efuse init
870 02:33:44.311881 chipver efuse init
871 02:33:44.316062 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 02:33:44.321626 [0.018960 Inits done]
873 02:33:44.322161 secure task start!
874 02:33:44.322617 high task start!
875 02:33:44.326211 low task start!
876 02:33:44.326747 run into bl31
877 02:33:44.332884 NOTICE: BL31: v1.3(release):4fc40b1
878 02:33:44.340684 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 02:33:44.341231 NOTICE: BL31: G12A normal boot!
880 02:33:44.366042 NOTICE: BL31: BL33 decompress pass
881 02:33:44.371722 ERROR: Error initializing runtime service opteed_fast
882 02:33:45.604596
883 02:33:45.605247
884 02:33:45.613051 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 02:33:45.613597
886 02:33:45.614061 Model: Libre Computer AML-A311D-CC Alta
887 02:33:45.821485 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 02:33:45.844890 DRAM: 2 GiB (effective 3.8 GiB)
889 02:33:45.987895 Core: 408 devices, 31 uclasses, devicetree: separate
890 02:33:45.993708 WDT: Not starting watchdog@f0d0
891 02:33:46.025994 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 02:33:46.038380 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 02:33:46.043396 ** Bad device specification mmc 0 **
894 02:33:46.053744 Card did not respond to voltage select! : -110
895 02:33:46.061383 ** Bad device specification mmc 0 **
896 02:33:46.061911 Couldn't find partition mmc 0
897 02:33:46.069738 Card did not respond to voltage select! : -110
898 02:33:46.075250 ** Bad device specification mmc 0 **
899 02:33:46.075774 Couldn't find partition mmc 0
900 02:33:46.080328 Error: could not access storage.
901 02:33:46.423805 Net: eth0: ethernet@ff3f0000
902 02:33:46.424484 starting USB...
903 02:33:46.675662 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 02:33:46.676389 Starting the controller
905 02:33:46.682607 USB XHCI 1.10
906 02:33:48.545576 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 02:33:48.546223 bl2_stage_init 0x01
908 02:33:48.546676 bl2_stage_init 0x81
909 02:33:48.551149 hw id: 0x0000 - pwm id 0x01
910 02:33:48.551654 bl2_stage_init 0xc1
911 02:33:48.552145 bl2_stage_init 0x02
912 02:33:48.552593
913 02:33:48.556718 L0:00000000
914 02:33:48.557219 L1:20000703
915 02:33:48.557663 L2:00008067
916 02:33:48.558102 L3:14000000
917 02:33:48.562409 B2:00402000
918 02:33:48.562911 B1:e0f83180
919 02:33:48.563357
920 02:33:48.563799 TE: 58167
921 02:33:48.564278
922 02:33:48.568046 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 02:33:48.568570
924 02:33:48.569026 Board ID = 1
925 02:33:48.573583 Set A53 clk to 24M
926 02:33:48.574084 Set A73 clk to 24M
927 02:33:48.574528 Set clk81 to 24M
928 02:33:48.579138 A53 clk: 1200 MHz
929 02:33:48.579641 A73 clk: 1200 MHz
930 02:33:48.580117 CLK81: 166.6M
931 02:33:48.580560 smccc: 00012abe
932 02:33:48.584722 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 02:33:48.590429 board id: 1
934 02:33:48.596329 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 02:33:48.606794 fw parse done
936 02:33:48.612753 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 02:33:48.655345 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 02:33:48.666276 PIEI prepare done
939 02:33:48.666819 fastboot data load
940 02:33:48.667253 fastboot data verify
941 02:33:48.671861 verify result: 266
942 02:33:48.677495 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 02:33:48.678000 LPDDR4 probe
944 02:33:48.678423 ddr clk to 1584MHz
945 02:33:48.685421 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 02:33:48.722768
947 02:33:48.723288 dmc_version 0001
948 02:33:48.729445 Check phy result
949 02:33:48.735316 INFO : End of CA training
950 02:33:48.735801 INFO : End of initialization
951 02:33:48.740901 INFO : Training has run successfully!
952 02:33:48.741394 Check phy result
953 02:33:48.746489 INFO : End of initialization
954 02:33:48.746978 INFO : End of read enable training
955 02:33:48.749767 INFO : End of fine write leveling
956 02:33:48.755334 INFO : End of Write leveling coarse delay
957 02:33:48.760978 INFO : Training has run successfully!
958 02:33:48.761472 Check phy result
959 02:33:48.761900 INFO : End of initialization
960 02:33:48.766630 INFO : End of read dq deskew training
961 02:33:48.772194 INFO : End of MPR read delay center optimization
962 02:33:48.772686 INFO : End of write delay center optimization
963 02:33:48.777699 INFO : End of read delay center optimization
964 02:33:48.783332 INFO : End of max read latency training
965 02:33:48.783825 INFO : Training has run successfully!
966 02:33:48.788944 1D training succeed
967 02:33:48.794966 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 02:33:48.842478 Check phy result
969 02:33:48.843014 INFO : End of initialization
970 02:33:48.864998 INFO : End of 2D read delay Voltage center optimization
971 02:33:48.884823 INFO : End of 2D read delay Voltage center optimization
972 02:33:48.937274 INFO : End of 2D write delay Voltage center optimization
973 02:33:48.986670 INFO : End of 2D write delay Voltage center optimization
974 02:33:48.992289 INFO : Training has run successfully!
975 02:33:48.992803
976 02:33:48.993254 channel==0
977 02:33:48.997863 RxClkDly_Margin_A0==88 ps 9
978 02:33:48.998369 TxDqDly_Margin_A0==98 ps 10
979 02:33:49.001111 RxClkDly_Margin_A1==88 ps 9
980 02:33:49.001614 TxDqDly_Margin_A1==98 ps 10
981 02:33:49.006768 TrainedVREFDQ_A0==74
982 02:33:49.007275 TrainedVREFDQ_A1==76
983 02:33:49.012288 VrefDac_Margin_A0==24
984 02:33:49.012791 DeviceVref_Margin_A0==40
985 02:33:49.013240 VrefDac_Margin_A1==24
986 02:33:49.017896 DeviceVref_Margin_A1==38
987 02:33:49.018398
988 02:33:49.018844
989 02:33:49.019282 channel==1
990 02:33:49.019711 RxClkDly_Margin_A0==98 ps 10
991 02:33:49.023524 TxDqDly_Margin_A0==98 ps 10
992 02:33:49.024078 RxClkDly_Margin_A1==98 ps 10
993 02:33:49.029116 TxDqDly_Margin_A1==88 ps 9
994 02:33:49.029625 TrainedVREFDQ_A0==77
995 02:33:49.030074 TrainedVREFDQ_A1==77
996 02:33:49.034716 VrefDac_Margin_A0==22
997 02:33:49.035223 DeviceVref_Margin_A0==37
998 02:33:49.040234 VrefDac_Margin_A1==22
999 02:33:49.040754 DeviceVref_Margin_A1==37
1000 02:33:49.041200
1001 02:33:49.045824 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 02:33:49.046326
1003 02:33:49.073748 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1004 02:33:49.079422 2D training succeed
1005 02:33:49.084974 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 02:33:49.085482 auto size-- 65535DDR cs0 size: 2048MB
1007 02:33:49.090631 DDR cs1 size: 2048MB
1008 02:33:49.091143 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 02:33:49.096229 cs0 DataBus test pass
1010 02:33:49.096764 cs1 DataBus test pass
1011 02:33:49.097230 cs0 AddrBus test pass
1012 02:33:49.101815 cs1 AddrBus test pass
1013 02:33:49.102326
1014 02:33:49.102780 100bdlr_step_size ps== 420
1015 02:33:49.103231 result report
1016 02:33:49.107395 boot times 0Enable ddr reg access
1017 02:33:49.115199 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 02:33:49.128710 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 02:33:49.702443 0.0;M3 CHK:0;cm4_sp_mode 0
1020 02:33:49.703064 MVN_1=0x00000000
1021 02:33:49.708058 MVN_2=0x00000000
1022 02:33:49.713839 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 02:33:49.714344 OPS=0x10
1024 02:33:49.714796 ring efuse init
1025 02:33:49.715233 chipver efuse init
1026 02:33:49.721979 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 02:33:49.722513 [0.018961 Inits done]
1028 02:33:49.729588 secure task start!
1029 02:33:49.730088 high task start!
1030 02:33:49.730533 low task start!
1031 02:33:49.730972 run into bl31
1032 02:33:49.736201 NOTICE: BL31: v1.3(release):4fc40b1
1033 02:33:49.744079 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 02:33:49.744596 NOTICE: BL31: G12A normal boot!
1035 02:33:49.769415 NOTICE: BL31: BL33 decompress pass
1036 02:33:49.775104 ERROR: Error initializing runtime service opteed_fast
1037 02:33:51.008027
1038 02:33:51.008684
1039 02:33:51.016408 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 02:33:51.016993
1041 02:33:51.017452 Model: Libre Computer AML-A311D-CC Alta
1042 02:33:51.224867 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 02:33:51.248870 DRAM: 2 GiB (effective 3.8 GiB)
1044 02:33:51.391167 Core: 408 devices, 31 uclasses, devicetree: separate
1045 02:33:51.397635 WDT: Not starting watchdog@f0d0
1046 02:33:51.429249 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 02:33:51.441764 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 02:33:51.446765 ** Bad device specification mmc 0 **
1049 02:33:51.458995 Card did not respond to voltage select! : -110
1050 02:33:51.464665 ** Bad device specification mmc 0 **
1051 02:33:51.465204 Couldn't find partition mmc 0
1052 02:33:51.473195 Card did not respond to voltage select! : -110
1053 02:33:51.478563 ** Bad device specification mmc 0 **
1054 02:33:51.479184 Couldn't find partition mmc 0
1055 02:33:51.483563 Error: could not access storage.
1056 02:33:51.827176 Net: eth0: ethernet@ff3f0000
1057 02:33:51.827775 starting USB...
1058 02:33:52.078732 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 02:33:52.079333 Starting the controller
1060 02:33:52.085794 USB XHCI 1.10
1061 02:33:53.639841 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 02:33:53.648067 scanning usb for storage devices... 0 Storage Device(s) found
1064 02:33:53.699595 Hit any key to stop autoboot: 1
1065 02:33:53.700401 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 02:33:53.701028 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 02:33:53.701518 Setting prompt string to ['=>']
1068 02:33:53.701991 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 02:33:53.715528 0
1070 02:33:53.716459 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 02:33:53.716935 Sending with 10 millisecond of delay
1073 02:33:54.851574 => setenv autoload no
1074 02:33:54.862389 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 02:33:54.867177 setenv autoload no
1076 02:33:54.867896 Sending with 10 millisecond of delay
1078 02:33:56.664828 => setenv initrd_high 0xffffffff
1079 02:33:56.675618 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 02:33:56.676946 setenv initrd_high 0xffffffff
1081 02:33:56.677652 Sending with 10 millisecond of delay
1083 02:33:58.293674 => setenv fdt_high 0xffffffff
1084 02:33:58.304435 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 02:33:58.305214 setenv fdt_high 0xffffffff
1086 02:33:58.305916 Sending with 10 millisecond of delay
1088 02:33:58.597682 => dhcp
1089 02:33:58.608323 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 02:33:58.609054 dhcp
1091 02:33:58.609476 Speed: 1000, full duplex
1092 02:33:58.609886 BOOTP broadcast 1
1093 02:33:58.619229 DHCP client bound to address 192.168.6.27 (10 ms)
1094 02:33:58.619906 Sending with 10 millisecond of delay
1096 02:34:00.296200 => setenv serverip 192.168.6.2
1097 02:34:00.306995 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 02:34:00.307882 setenv serverip 192.168.6.2
1099 02:34:00.308624 Sending with 10 millisecond of delay
1101 02:34:04.032303 => tftpboot 0x01080000 943577/tftp-deploy-7mmgm9ic/kernel/uImage
1102 02:34:04.043104 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1103 02:34:04.043894 tftpboot 0x01080000 943577/tftp-deploy-7mmgm9ic/kernel/uImage
1104 02:34:04.044423 Speed: 1000, full duplex
1105 02:34:04.044882 Using ethernet@ff3f0000 device
1106 02:34:04.045762 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 02:34:04.051405 Filename '943577/tftp-deploy-7mmgm9ic/kernel/uImage'.
1108 02:34:04.055324 Load address: 0x1080000
1109 02:34:06.833281 Loading: *################################################## 43.7 MiB
1110 02:34:06.833897 15.7 MiB/s
1111 02:34:06.834325 done
1112 02:34:06.837788 Bytes transferred = 45779520 (2ba8a40 hex)
1113 02:34:06.838586 Sending with 10 millisecond of delay
1115 02:34:11.525361 => tftpboot 0x08000000 943577/tftp-deploy-7mmgm9ic/ramdisk/ramdisk.cpio.gz.uboot
1116 02:34:11.536160 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1117 02:34:11.536974 tftpboot 0x08000000 943577/tftp-deploy-7mmgm9ic/ramdisk/ramdisk.cpio.gz.uboot
1118 02:34:11.537418 Speed: 1000, full duplex
1119 02:34:11.537828 Using ethernet@ff3f0000 device
1120 02:34:11.538833 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1121 02:34:11.550758 Filename '943577/tftp-deploy-7mmgm9ic/ramdisk/ramdisk.cpio.gz.uboot'.
1122 02:34:11.551258 Load address: 0x8000000
1123 02:34:18.624310 Loading: *######################T ########################### UDP wrong checksum 00000005 00006d52
1124 02:34:23.624816 T UDP wrong checksum 00000005 00006d52
1125 02:34:33.627938 T T UDP wrong checksum 00000005 00006d52
1126 02:34:53.631889 T T T T UDP wrong checksum 00000005 00006d52
1127 02:35:08.635897 T T
1128 02:35:08.636717 Retry count exceeded; starting again
1130 02:35:08.638479 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1133 02:35:08.640933 end: 2.4 uboot-commands (duration 00:01:52) [common]
1135 02:35:08.642383 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1137 02:35:08.643444 end: 2 uboot-action (duration 00:01:52) [common]
1139 02:35:08.645141 Cleaning after the job
1140 02:35:08.645705 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/ramdisk
1141 02:35:08.647089 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/kernel
1142 02:35:08.695039 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/dtb
1143 02:35:08.695796 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943577/tftp-deploy-7mmgm9ic/modules
1144 02:35:08.714711 start: 4.1 power-off (timeout 00:00:30) [common]
1145 02:35:08.715354 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1146 02:35:08.748586 >> OK - accepted request
1147 02:35:08.750280 Returned 0 in 0 seconds
1148 02:35:08.851046 end: 4.1 power-off (duration 00:00:00) [common]
1150 02:35:08.852069 start: 4.2 read-feedback (timeout 00:10:00) [common]
1151 02:35:08.852805 Listened to connection for namespace 'common' for up to 1s
1152 02:35:09.853348 Finalising connection for namespace 'common'
1153 02:35:09.854075 Disconnecting from shell: Finalise
1154 02:35:09.854632 =>
1155 02:35:09.955697 end: 4.2 read-feedback (duration 00:00:01) [common]
1156 02:35:09.956454 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/943577
1157 02:35:10.257200 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/943577
1158 02:35:10.257825 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.