Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:55:00.047706 lava-dispatcher, installed at version: 2024.01
2 02:55:00.048515 start: 0 validate
3 02:55:00.048998 Start time: 2024-11-06 02:55:00.048967+00:00 (UTC)
4 02:55:00.049544 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:55:00.050075 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 02:55:00.086889 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:55:00.087604 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:55:00.123296 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:55:00.124141 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:55:00.159017 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:55:00.159541 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 02:55:00.201468 validate duration: 0.15
14 02:55:00.202487 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 02:55:00.202902 start: 1.1 download-retry (timeout 00:10:00) [common]
16 02:55:00.203269 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 02:55:00.204027 Not decompressing ramdisk as can be used compressed.
18 02:55:00.204606 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 02:55:00.204895 saving as /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/ramdisk/rootfs.cpio.gz
20 02:55:00.205198 total size: 47897469 (45 MB)
21 02:55:00.240799 progress 0 % (0 MB)
22 02:55:00.273710 progress 5 % (2 MB)
23 02:55:00.306391 progress 10 % (4 MB)
24 02:55:00.341994 progress 15 % (6 MB)
25 02:55:00.380273 progress 20 % (9 MB)
26 02:55:00.418392 progress 25 % (11 MB)
27 02:55:00.456040 progress 30 % (13 MB)
28 02:55:00.493872 progress 35 % (16 MB)
29 02:55:00.531543 progress 40 % (18 MB)
30 02:55:00.569438 progress 45 % (20 MB)
31 02:55:00.607245 progress 50 % (22 MB)
32 02:55:00.644851 progress 55 % (25 MB)
33 02:55:00.682890 progress 60 % (27 MB)
34 02:55:00.720800 progress 65 % (29 MB)
35 02:55:00.758311 progress 70 % (32 MB)
36 02:55:00.795670 progress 75 % (34 MB)
37 02:55:00.833503 progress 80 % (36 MB)
38 02:55:00.871608 progress 85 % (38 MB)
39 02:55:00.909481 progress 90 % (41 MB)
40 02:55:00.947046 progress 95 % (43 MB)
41 02:55:00.983813 progress 100 % (45 MB)
42 02:55:00.984752 45 MB downloaded in 0.78 s (58.60 MB/s)
43 02:55:00.985421 end: 1.1.1 http-download (duration 00:00:01) [common]
45 02:55:00.986494 end: 1.1 download-retry (duration 00:00:01) [common]
46 02:55:00.986899 start: 1.2 download-retry (timeout 00:09:59) [common]
47 02:55:00.987292 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 02:55:00.987885 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kernel/Image
49 02:55:00.988220 saving as /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/kernel/Image
50 02:55:00.988478 total size: 45779456 (43 MB)
51 02:55:00.988735 No compression specified
52 02:55:01.029559 progress 0 % (0 MB)
53 02:55:01.063659 progress 5 % (2 MB)
54 02:55:01.097880 progress 10 % (4 MB)
55 02:55:01.132087 progress 15 % (6 MB)
56 02:55:01.166551 progress 20 % (8 MB)
57 02:55:01.200618 progress 25 % (10 MB)
58 02:55:01.234923 progress 30 % (13 MB)
59 02:55:01.268619 progress 35 % (15 MB)
60 02:55:01.303041 progress 40 % (17 MB)
61 02:55:01.337313 progress 45 % (19 MB)
62 02:55:01.371103 progress 50 % (21 MB)
63 02:55:01.405379 progress 55 % (24 MB)
64 02:55:01.439881 progress 60 % (26 MB)
65 02:55:01.474055 progress 65 % (28 MB)
66 02:55:01.507352 progress 70 % (30 MB)
67 02:55:01.541333 progress 75 % (32 MB)
68 02:55:01.575242 progress 80 % (34 MB)
69 02:55:01.608942 progress 85 % (37 MB)
70 02:55:01.642677 progress 90 % (39 MB)
71 02:55:01.676641 progress 95 % (41 MB)
72 02:55:01.710099 progress 100 % (43 MB)
73 02:55:01.710750 43 MB downloaded in 0.72 s (60.45 MB/s)
74 02:55:01.711334 end: 1.2.1 http-download (duration 00:00:01) [common]
76 02:55:01.712399 end: 1.2 download-retry (duration 00:00:01) [common]
77 02:55:01.712744 start: 1.3 download-retry (timeout 00:09:58) [common]
78 02:55:01.713072 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 02:55:01.713629 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 02:55:01.713928 saving as /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/dtb/meson-g12b-a311d-libretech-cc.dtb
81 02:55:01.714190 total size: 54703 (0 MB)
82 02:55:01.714447 No compression specified
83 02:55:01.754482 progress 59 % (0 MB)
84 02:55:01.755486 progress 100 % (0 MB)
85 02:55:01.756198 0 MB downloaded in 0.04 s (1.24 MB/s)
86 02:55:01.756784 end: 1.3.1 http-download (duration 00:00:00) [common]
88 02:55:01.757815 end: 1.3 download-retry (duration 00:00:00) [common]
89 02:55:01.758142 start: 1.4 download-retry (timeout 00:09:58) [common]
90 02:55:01.758469 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 02:55:01.759029 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/modules.tar.xz
92 02:55:01.759332 saving as /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/modules/modules.tar
93 02:55:01.759584 total size: 11613264 (11 MB)
94 02:55:01.759841 Using unxz to decompress xz
95 02:55:01.801628 progress 0 % (0 MB)
96 02:55:01.867659 progress 5 % (0 MB)
97 02:55:01.941843 progress 10 % (1 MB)
98 02:55:02.037591 progress 15 % (1 MB)
99 02:55:02.129726 progress 20 % (2 MB)
100 02:55:02.213475 progress 25 % (2 MB)
101 02:55:02.289470 progress 30 % (3 MB)
102 02:55:02.368670 progress 35 % (3 MB)
103 02:55:02.441548 progress 40 % (4 MB)
104 02:55:02.517953 progress 45 % (5 MB)
105 02:55:02.603196 progress 50 % (5 MB)
106 02:55:02.682095 progress 55 % (6 MB)
107 02:55:02.768021 progress 60 % (6 MB)
108 02:55:02.848706 progress 65 % (7 MB)
109 02:55:02.930983 progress 70 % (7 MB)
110 02:55:03.009866 progress 75 % (8 MB)
111 02:55:03.096224 progress 80 % (8 MB)
112 02:55:03.176062 progress 85 % (9 MB)
113 02:55:03.255054 progress 90 % (9 MB)
114 02:55:03.334602 progress 95 % (10 MB)
115 02:55:03.414321 progress 100 % (11 MB)
116 02:55:03.426652 11 MB downloaded in 1.67 s (6.64 MB/s)
117 02:55:03.427386 end: 1.4.1 http-download (duration 00:00:02) [common]
119 02:55:03.428792 end: 1.4 download-retry (duration 00:00:02) [common]
120 02:55:03.429438 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 02:55:03.430029 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 02:55:03.430586 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 02:55:03.431152 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 02:55:03.432818 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7
125 02:55:03.433845 makedir: /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin
126 02:55:03.434651 makedir: /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/tests
127 02:55:03.436056 makedir: /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/results
128 02:55:03.436837 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-add-keys
129 02:55:03.437789 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-add-sources
130 02:55:03.439783 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-background-process-start
131 02:55:03.441111 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-background-process-stop
132 02:55:03.441917 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-common-functions
133 02:55:03.442746 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-echo-ipv4
134 02:55:03.444128 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-install-packages
135 02:55:03.446135 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-installed-packages
136 02:55:03.448486 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-os-build
137 02:55:03.449383 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-probe-channel
138 02:55:03.450268 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-probe-ip
139 02:55:03.456780 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-target-ip
140 02:55:03.458276 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-target-mac
141 02:55:03.459617 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-target-storage
142 02:55:03.460481 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-test-case
143 02:55:03.462041 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-test-event
144 02:55:03.463342 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-test-feedback
145 02:55:03.465613 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-test-raise
146 02:55:03.466836 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-test-reference
147 02:55:03.475115 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-test-runner
148 02:55:03.477869 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-test-set
149 02:55:03.478666 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-test-shell
150 02:55:03.479308 Updating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-install-packages (oe)
151 02:55:03.480179 Updating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/bin/lava-installed-packages (oe)
152 02:55:03.481176 Creating /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/environment
153 02:55:03.481808 LAVA metadata
154 02:55:03.482122 - LAVA_JOB_ID=943552
155 02:55:03.482360 - LAVA_DISPATCHER_IP=192.168.6.2
156 02:55:03.482805 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 02:55:03.484678 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 02:55:03.485186 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 02:55:03.485506 skipped lava-vland-overlay
160 02:55:03.485838 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 02:55:03.486175 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 02:55:03.486467 skipped lava-multinode-overlay
163 02:55:03.486797 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 02:55:03.487134 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 02:55:03.487468 Loading test definitions
166 02:55:03.487852 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 02:55:03.488190 Using /lava-943552 at stage 0
168 02:55:03.489701 uuid=943552_1.5.2.4.1 testdef=None
169 02:55:03.490131 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 02:55:03.490484 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 02:55:03.492841 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 02:55:03.493968 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 02:55:03.497529 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 02:55:03.498543 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 02:55:03.501253 runner path: /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/0/tests/0_igt-gpu-panfrost test_uuid 943552_1.5.2.4.1
178 02:55:03.502000 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 02:55:03.502925 Creating lava-test-runner.conf files
181 02:55:03.503152 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/943552/lava-overlay-15y3_gx7/lava-943552/0 for stage 0
182 02:55:03.503572 - 0_igt-gpu-panfrost
183 02:55:03.504059 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 02:55:03.504415 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 02:55:03.538316 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 02:55:03.538834 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 02:55:03.539149 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 02:55:03.539459 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 02:55:03.539763 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 02:55:10.704170 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 02:55:10.704629 start: 1.5.4 extract-modules (timeout 00:09:49) [common]
192 02:55:10.704878 extracting modules file /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943552/extract-overlay-ramdisk-pq9n4ywe/ramdisk
193 02:55:12.098473 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 02:55:12.098966 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 02:55:12.099247 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943552/compress-overlay-f_4r1uyg/overlay-1.5.2.5.tar.gz to ramdisk
196 02:55:12.099462 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943552/compress-overlay-f_4r1uyg/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/943552/extract-overlay-ramdisk-pq9n4ywe/ramdisk
197 02:55:12.129644 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 02:55:12.130059 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 02:55:12.130333 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 02:55:12.130567 Converting downloaded kernel to a uImage
201 02:55:12.130878 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/kernel/Image /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/kernel/uImage
202 02:55:12.589309 output: Image Name:
203 02:55:12.589745 output: Created: Wed Nov 6 02:55:12 2024
204 02:55:12.589962 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 02:55:12.590170 output: Data Size: 45779456 Bytes = 44706.50 KiB = 43.66 MiB
206 02:55:12.590374 output: Load Address: 01080000
207 02:55:12.590574 output: Entry Point: 01080000
208 02:55:12.590777 output:
209 02:55:12.591119 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 02:55:12.591390 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 02:55:12.591666 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 02:55:12.591925 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 02:55:12.592248 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 02:55:12.592518 Building ramdisk /var/lib/lava/dispatcher/tmp/943552/extract-overlay-ramdisk-pq9n4ywe/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/943552/extract-overlay-ramdisk-pq9n4ywe/ramdisk
215 02:55:19.491975 >> 502360 blocks
216 02:55:39.990766 Adding RAMdisk u-boot header.
217 02:55:39.991628 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/943552/extract-overlay-ramdisk-pq9n4ywe/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/943552/extract-overlay-ramdisk-pq9n4ywe/ramdisk.cpio.gz.uboot
218 02:55:40.655958 output: Image Name:
219 02:55:40.656628 output: Created: Wed Nov 6 02:55:39 2024
220 02:55:40.657044 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 02:55:40.657450 output: Data Size: 65709985 Bytes = 64169.91 KiB = 62.67 MiB
222 02:55:40.657850 output: Load Address: 00000000
223 02:55:40.658245 output: Entry Point: 00000000
224 02:55:40.658635 output:
225 02:55:40.659670 rename /var/lib/lava/dispatcher/tmp/943552/extract-overlay-ramdisk-pq9n4ywe/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/ramdisk/ramdisk.cpio.gz.uboot
226 02:55:40.660434 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 02:55:40.660977 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 02:55:40.661502 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 02:55:40.661953 No LXC device requested
230 02:55:40.662452 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 02:55:40.662954 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 02:55:40.663441 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 02:55:40.663847 Checking files for TFTP limit of 4294967296 bytes.
234 02:55:40.666529 end: 1 tftp-deploy (duration 00:00:40) [common]
235 02:55:40.667088 start: 2 uboot-action (timeout 00:05:00) [common]
236 02:55:40.667603 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 02:55:40.668121 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 02:55:40.668640 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 02:55:40.669156 Using kernel file from prepare-kernel: 943552/tftp-deploy-gjta2qb4/kernel/uImage
240 02:55:40.669754 substitutions:
241 02:55:40.670158 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 02:55:40.670558 - {DTB_ADDR}: 0x01070000
243 02:55:40.670954 - {DTB}: 943552/tftp-deploy-gjta2qb4/dtb/meson-g12b-a311d-libretech-cc.dtb
244 02:55:40.671349 - {INITRD}: 943552/tftp-deploy-gjta2qb4/ramdisk/ramdisk.cpio.gz.uboot
245 02:55:40.671742 - {KERNEL_ADDR}: 0x01080000
246 02:55:40.672168 - {KERNEL}: 943552/tftp-deploy-gjta2qb4/kernel/uImage
247 02:55:40.672562 - {LAVA_MAC}: None
248 02:55:40.672991 - {PRESEED_CONFIG}: None
249 02:55:40.673385 - {PRESEED_LOCAL}: None
250 02:55:40.673769 - {RAMDISK_ADDR}: 0x08000000
251 02:55:40.674154 - {RAMDISK}: 943552/tftp-deploy-gjta2qb4/ramdisk/ramdisk.cpio.gz.uboot
252 02:55:40.674547 - {ROOT_PART}: None
253 02:55:40.674933 - {ROOT}: None
254 02:55:40.675321 - {SERVER_IP}: 192.168.6.2
255 02:55:40.675712 - {TEE_ADDR}: 0x83000000
256 02:55:40.676124 - {TEE}: None
257 02:55:40.676513 Parsed boot commands:
258 02:55:40.676888 - setenv autoload no
259 02:55:40.677274 - setenv initrd_high 0xffffffff
260 02:55:40.677659 - setenv fdt_high 0xffffffff
261 02:55:40.678041 - dhcp
262 02:55:40.678422 - setenv serverip 192.168.6.2
263 02:55:40.678803 - tftpboot 0x01080000 943552/tftp-deploy-gjta2qb4/kernel/uImage
264 02:55:40.679187 - tftpboot 0x08000000 943552/tftp-deploy-gjta2qb4/ramdisk/ramdisk.cpio.gz.uboot
265 02:55:40.679573 - tftpboot 0x01070000 943552/tftp-deploy-gjta2qb4/dtb/meson-g12b-a311d-libretech-cc.dtb
266 02:55:40.679958 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 02:55:40.680372 - bootm 0x01080000 0x08000000 0x01070000
268 02:55:40.680871 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 02:55:40.682339 start: 2.3 connect-device (timeout 00:05:00) [common]
271 02:55:40.682778 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 02:55:40.696552 Setting prompt string to ['lava-test: # ']
273 02:55:40.698042 end: 2.3 connect-device (duration 00:00:00) [common]
274 02:55:40.698641 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 02:55:40.699171 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 02:55:40.699678 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 02:55:40.700848 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 02:55:40.737483 >> OK - accepted request
279 02:55:40.739631 Returned 0 in 0 seconds
280 02:55:40.840784 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 02:55:40.842331 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 02:55:40.842880 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 02:55:40.843385 Setting prompt string to ['Hit any key to stop autoboot']
285 02:55:40.843836 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 02:55:40.845444 Trying 192.168.56.21...
287 02:55:40.845915 Connected to conserv1.
288 02:55:40.846319 Escape character is '^]'.
289 02:55:40.846728
290 02:55:40.847144 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 02:55:40.847557
292 02:55:51.552905 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 02:55:51.553555 bl2_stage_init 0x01
294 02:55:51.553982 bl2_stage_init 0x81
295 02:55:51.558288 hw id: 0x0000 - pwm id 0x01
296 02:55:51.558756 bl2_stage_init 0xc1
297 02:55:51.559175 bl2_stage_init 0x02
298 02:55:51.559589
299 02:55:51.563975 L0:00000000
300 02:55:51.564438 L1:20000703
301 02:55:51.564842 L2:00008067
302 02:55:51.565239 L3:14000000
303 02:55:51.569467 B2:00402000
304 02:55:51.569886 B1:e0f83180
305 02:55:51.570274
306 02:55:51.570662 TE: 58159
307 02:55:51.571046
308 02:55:51.575140 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 02:55:51.575557
310 02:55:51.575948 Board ID = 1
311 02:55:51.580683 Set A53 clk to 24M
312 02:55:51.581127 Set A73 clk to 24M
313 02:55:51.581514 Set clk81 to 24M
314 02:55:51.586233 A53 clk: 1200 MHz
315 02:55:51.586644 A73 clk: 1200 MHz
316 02:55:51.587030 CLK81: 166.6M
317 02:55:51.587413 smccc: 00012ab5
318 02:55:51.591837 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 02:55:51.597449 board id: 1
320 02:55:51.603351 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 02:55:51.614002 fw parse done
322 02:55:51.619977 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 02:55:51.662637 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 02:55:51.673535 PIEI prepare done
325 02:55:51.673958 fastboot data load
326 02:55:51.674355 fastboot data verify
327 02:55:51.679083 verify result: 266
328 02:55:51.684669 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 02:55:51.685094 LPDDR4 probe
330 02:55:51.685487 ddr clk to 1584MHz
331 02:55:51.692685 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 02:55:51.729896
333 02:55:51.730335 dmc_version 0001
334 02:55:51.739231 Check phy result
335 02:55:51.742470 INFO : End of CA training
336 02:55:51.742892 INFO : End of initialization
337 02:55:51.748070 INFO : Training has run successfully!
338 02:55:51.748503 Check phy result
339 02:55:51.753701 INFO : End of initialization
340 02:55:51.754117 INFO : End of read enable training
341 02:55:51.759270 INFO : End of fine write leveling
342 02:55:51.764854 INFO : End of Write leveling coarse delay
343 02:55:51.765271 INFO : Training has run successfully!
344 02:55:51.765665 Check phy result
345 02:55:51.770444 INFO : End of initialization
346 02:55:51.770861 INFO : End of read dq deskew training
347 02:55:51.776059 INFO : End of MPR read delay center optimization
348 02:55:51.781620 INFO : End of write delay center optimization
349 02:55:51.787307 INFO : End of read delay center optimization
350 02:55:51.787726 INFO : End of max read latency training
351 02:55:51.792839 INFO : Training has run successfully!
352 02:55:51.793271 1D training succeed
353 02:55:51.802061 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 02:55:51.849780 Check phy result
355 02:55:51.850294 INFO : End of initialization
356 02:55:51.872216 INFO : End of 2D read delay Voltage center optimization
357 02:55:51.892521 INFO : End of 2D read delay Voltage center optimization
358 02:55:51.944529 INFO : End of 2D write delay Voltage center optimization
359 02:55:51.993984 INFO : End of 2D write delay Voltage center optimization
360 02:55:51.999592 INFO : Training has run successfully!
361 02:55:52.000065
362 02:55:52.000471 channel==0
363 02:55:52.005024 RxClkDly_Margin_A0==88 ps 9
364 02:55:52.005436 TxDqDly_Margin_A0==98 ps 10
365 02:55:52.008480 RxClkDly_Margin_A1==88 ps 9
366 02:55:52.008905 TxDqDly_Margin_A1==98 ps 10
367 02:55:52.014011 TrainedVREFDQ_A0==74
368 02:55:52.014430 TrainedVREFDQ_A1==74
369 02:55:52.014824 VrefDac_Margin_A0==24
370 02:55:52.019652 DeviceVref_Margin_A0==40
371 02:55:52.020082 VrefDac_Margin_A1==24
372 02:55:52.025214 DeviceVref_Margin_A1==40
373 02:55:52.025622
374 02:55:52.026014
375 02:55:52.026403 channel==1
376 02:55:52.026787 RxClkDly_Margin_A0==98 ps 10
377 02:55:52.030863 TxDqDly_Margin_A0==88 ps 9
378 02:55:52.031277 RxClkDly_Margin_A1==88 ps 9
379 02:55:52.036432 TxDqDly_Margin_A1==108 ps 11
380 02:55:52.036850 TrainedVREFDQ_A0==74
381 02:55:52.037241 TrainedVREFDQ_A1==78
382 02:55:52.042035 VrefDac_Margin_A0==22
383 02:55:52.042442 DeviceVref_Margin_A0==40
384 02:55:52.047647 VrefDac_Margin_A1==24
385 02:55:52.048075 DeviceVref_Margin_A1==36
386 02:55:52.048463
387 02:55:52.053248 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 02:55:52.053683
389 02:55:52.081264 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 02:55:52.086830 2D training succeed
391 02:55:52.092461 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 02:55:52.092882 auto size-- 65535DDR cs0 size: 2048MB
393 02:55:52.097918 DDR cs1 size: 2048MB
394 02:55:52.098330 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 02:55:52.103552 cs0 DataBus test pass
396 02:55:52.103966 cs1 DataBus test pass
397 02:55:52.104401 cs0 AddrBus test pass
398 02:55:52.109104 cs1 AddrBus test pass
399 02:55:52.109522
400 02:55:52.109912 100bdlr_step_size ps== 420
401 02:55:52.110308 result report
402 02:55:52.114705 boot times 0Enable ddr reg access
403 02:55:52.122437 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 02:55:52.135919 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 02:55:52.709578 0.0;M3 CHK:0;cm4_sp_mode 0
406 02:55:52.710076 MVN_1=0x00000000
407 02:55:52.715040 MVN_2=0x00000000
408 02:55:52.720798 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 02:55:52.721247 OPS=0x10
410 02:55:52.721657 ring efuse init
411 02:55:52.722059 chipver efuse init
412 02:55:52.726388 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 02:55:52.732047 [0.018960 Inits done]
414 02:55:52.732483 secure task start!
415 02:55:52.732891 high task start!
416 02:55:52.736600 low task start!
417 02:55:52.737033 run into bl31
418 02:55:52.743242 NOTICE: BL31: v1.3(release):4fc40b1
419 02:55:52.751038 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 02:55:52.751496 NOTICE: BL31: G12A normal boot!
421 02:55:52.776416 NOTICE: BL31: BL33 decompress pass
422 02:55:52.782103 ERROR: Error initializing runtime service opteed_fast
423 02:55:54.015099
424 02:55:54.015671
425 02:55:54.023363 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 02:55:54.023807
427 02:55:54.024257 Model: Libre Computer AML-A311D-CC Alta
428 02:55:54.231855 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 02:55:54.255152 DRAM: 2 GiB (effective 3.8 GiB)
430 02:55:54.398208 Core: 408 devices, 31 uclasses, devicetree: separate
431 02:55:54.404047 WDT: Not starting watchdog@f0d0
432 02:55:54.436242 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 02:55:54.448701 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 02:55:54.453690 ** Bad device specification mmc 0 **
435 02:55:54.464038 Card did not respond to voltage select! : -110
436 02:55:54.471686 ** Bad device specification mmc 0 **
437 02:55:54.472146 Couldn't find partition mmc 0
438 02:55:54.480039 Card did not respond to voltage select! : -110
439 02:55:54.485527 ** Bad device specification mmc 0 **
440 02:55:54.485970 Couldn't find partition mmc 0
441 02:55:54.490582 Error: could not access storage.
442 02:55:55.753076 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 02:55:55.753636 bl2_stage_init 0x01
444 02:55:55.754064 bl2_stage_init 0x81
445 02:55:55.758634 hw id: 0x0000 - pwm id 0x01
446 02:55:55.759066 bl2_stage_init 0xc1
447 02:55:55.759472 bl2_stage_init 0x02
448 02:55:55.759873
449 02:55:55.764246 L0:00000000
450 02:55:55.764686 L1:20000703
451 02:55:55.765093 L2:00008067
452 02:55:55.765492 L3:14000000
453 02:55:55.769820 B2:00402000
454 02:55:55.770245 B1:e0f83180
455 02:55:55.770645
456 02:55:55.771046 TE: 58159
457 02:55:55.771443
458 02:55:55.775429 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 02:55:55.775862
460 02:55:55.776302 Board ID = 1
461 02:55:55.781052 Set A53 clk to 24M
462 02:55:55.781476 Set A73 clk to 24M
463 02:55:55.781880 Set clk81 to 24M
464 02:55:55.786623 A53 clk: 1200 MHz
465 02:55:55.787046 A73 clk: 1200 MHz
466 02:55:55.787448 CLK81: 166.6M
467 02:55:55.787845 smccc: 00012ab5
468 02:55:55.792205 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 02:55:55.797808 board id: 1
470 02:55:55.803692 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 02:55:55.814357 fw parse done
472 02:55:55.820314 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 02:55:55.862974 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 02:55:55.873857 PIEI prepare done
475 02:55:55.874285 fastboot data load
476 02:55:55.874693 fastboot data verify
477 02:55:55.879475 verify result: 266
478 02:55:55.885079 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 02:55:55.885510 LPDDR4 probe
480 02:55:55.885913 ddr clk to 1584MHz
481 02:55:55.893043 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 02:55:55.930277
483 02:55:55.930702 dmc_version 0001
484 02:55:55.936980 Check phy result
485 02:55:55.942843 INFO : End of CA training
486 02:55:55.943262 INFO : End of initialization
487 02:55:55.948449 INFO : Training has run successfully!
488 02:55:55.948867 Check phy result
489 02:55:55.954069 INFO : End of initialization
490 02:55:55.954491 INFO : End of read enable training
491 02:55:55.959634 INFO : End of fine write leveling
492 02:55:55.965258 INFO : End of Write leveling coarse delay
493 02:55:55.965702 INFO : Training has run successfully!
494 02:55:55.966105 Check phy result
495 02:55:55.970827 INFO : End of initialization
496 02:55:55.971245 INFO : End of read dq deskew training
497 02:55:55.976446 INFO : End of MPR read delay center optimization
498 02:55:55.982088 INFO : End of write delay center optimization
499 02:55:55.987615 INFO : End of read delay center optimization
500 02:55:55.988066 INFO : End of max read latency training
501 02:55:55.993255 INFO : Training has run successfully!
502 02:55:55.993677 1D training succeed
503 02:55:56.002439 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 02:55:56.050010 Check phy result
505 02:55:56.050432 INFO : End of initialization
506 02:55:56.071746 INFO : End of 2D read delay Voltage center optimization
507 02:55:56.091975 INFO : End of 2D read delay Voltage center optimization
508 02:55:56.143975 INFO : End of 2D write delay Voltage center optimization
509 02:55:56.193342 INFO : End of 2D write delay Voltage center optimization
510 02:55:56.198952 INFO : Training has run successfully!
511 02:55:56.199378
512 02:55:56.199780 channel==0
513 02:55:56.204540 RxClkDly_Margin_A0==88 ps 9
514 02:55:56.204964 TxDqDly_Margin_A0==98 ps 10
515 02:55:56.210160 RxClkDly_Margin_A1==88 ps 9
516 02:55:56.210579 TxDqDly_Margin_A1==98 ps 10
517 02:55:56.210983 TrainedVREFDQ_A0==74
518 02:55:56.215750 TrainedVREFDQ_A1==74
519 02:55:56.216221 VrefDac_Margin_A0==25
520 02:55:56.216624 DeviceVref_Margin_A0==40
521 02:55:56.221354 VrefDac_Margin_A1==25
522 02:55:56.221775 DeviceVref_Margin_A1==40
523 02:55:56.222177
524 02:55:56.222576
525 02:55:56.226940 channel==1
526 02:55:56.227358 RxClkDly_Margin_A0==98 ps 10
527 02:55:56.227758 TxDqDly_Margin_A0==98 ps 10
528 02:55:56.232524 RxClkDly_Margin_A1==98 ps 10
529 02:55:56.232946 TxDqDly_Margin_A1==88 ps 9
530 02:55:56.238164 TrainedVREFDQ_A0==77
531 02:55:56.238589 TrainedVREFDQ_A1==77
532 02:55:56.238992 VrefDac_Margin_A0==22
533 02:55:56.243751 DeviceVref_Margin_A0==37
534 02:55:56.244195 VrefDac_Margin_A1==22
535 02:55:56.249339 DeviceVref_Margin_A1==37
536 02:55:56.249761
537 02:55:56.250166 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 02:55:56.254926
539 02:55:56.282960 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 02:55:56.283412 2D training succeed
541 02:55:56.288558 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 02:55:56.294163 auto size-- 65535DDR cs0 size: 2048MB
543 02:55:56.294591 DDR cs1 size: 2048MB
544 02:55:56.299749 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 02:55:56.300216 cs0 DataBus test pass
546 02:55:56.305353 cs1 DataBus test pass
547 02:55:56.305777 cs0 AddrBus test pass
548 02:55:56.306176 cs1 AddrBus test pass
549 02:55:56.306569
550 02:55:56.310956 100bdlr_step_size ps== 420
551 02:55:56.311391 result report
552 02:55:56.316545 boot times 0Enable ddr reg access
553 02:55:56.321982 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 02:55:56.335465 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 02:55:56.909114 0.0;M3 CHK:0;cm4_sp_mode 0
556 02:55:56.909592 MVN_1=0x00000000
557 02:55:56.914668 MVN_2=0x00000000
558 02:55:56.920432 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 02:55:56.920914 OPS=0x10
560 02:55:56.921327 ring efuse init
561 02:55:56.921709 chipver efuse init
562 02:55:56.926018 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 02:55:56.931591 [0.018960 Inits done]
564 02:55:56.932043 secure task start!
565 02:55:56.932435 high task start!
566 02:55:56.936250 low task start!
567 02:55:56.936661 run into bl31
568 02:55:56.942851 NOTICE: BL31: v1.3(release):4fc40b1
569 02:55:56.950649 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 02:55:56.951068 NOTICE: BL31: G12A normal boot!
571 02:55:56.976029 NOTICE: BL31: BL33 decompress pass
572 02:55:56.981680 ERROR: Error initializing runtime service opteed_fast
573 02:55:58.214745
574 02:55:58.215340
575 02:55:58.223150 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 02:55:58.223596
577 02:55:58.224033 Model: Libre Computer AML-A311D-CC Alta
578 02:55:58.431489 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 02:55:58.454972 DRAM: 2 GiB (effective 3.8 GiB)
580 02:55:58.597828 Core: 408 devices, 31 uclasses, devicetree: separate
581 02:55:58.603759 WDT: Not starting watchdog@f0d0
582 02:55:58.636062 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 02:55:58.648529 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 02:55:58.653573 ** Bad device specification mmc 0 **
585 02:55:58.663833 Card did not respond to voltage select! : -110
586 02:55:58.671511 ** Bad device specification mmc 0 **
587 02:55:58.671942 Couldn't find partition mmc 0
588 02:55:58.679844 Card did not respond to voltage select! : -110
589 02:55:58.685327 ** Bad device specification mmc 0 **
590 02:55:58.685777 Couldn't find partition mmc 0
591 02:55:58.690443 Error: could not access storage.
592 02:55:59.033546 Net: eth0: ethernet@ff3f0000
593 02:55:59.034078 starting USB...
594 02:55:59.284755 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 02:55:59.285265 Starting the controller
596 02:55:59.291716 USB XHCI 1.10
597 02:56:01.001928 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 02:56:01.002466 bl2_stage_init 0x01
599 02:56:01.002896 bl2_stage_init 0x81
600 02:56:01.007597 hw id: 0x0000 - pwm id 0x01
601 02:56:01.008104 bl2_stage_init 0xc1
602 02:56:01.008530 bl2_stage_init 0x02
603 02:56:01.008939
604 02:56:01.013052 L0:00000000
605 02:56:01.013520 L1:20000703
606 02:56:01.013937 L2:00008067
607 02:56:01.014343 L3:14000000
608 02:56:01.015964 B2:00402000
609 02:56:01.016447 B1:e0f83180
610 02:56:01.016857
611 02:56:01.017261 TE: 58159
612 02:56:01.017664
613 02:56:01.027024 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 02:56:01.027484
615 02:56:01.027901 Board ID = 1
616 02:56:01.028341 Set A53 clk to 24M
617 02:56:01.028749 Set A73 clk to 24M
618 02:56:01.032717 Set clk81 to 24M
619 02:56:01.033174 A53 clk: 1200 MHz
620 02:56:01.033592 A73 clk: 1200 MHz
621 02:56:01.036251 CLK81: 166.6M
622 02:56:01.036701 smccc: 00012ab5
623 02:56:01.041771 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 02:56:01.047327 board id: 1
625 02:56:01.052720 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 02:56:01.063109 fw parse done
627 02:56:01.069066 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 02:56:01.111685 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 02:56:01.122664 PIEI prepare done
630 02:56:01.123129 fastboot data load
631 02:56:01.123550 fastboot data verify
632 02:56:01.128238 verify result: 266
633 02:56:01.133864 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 02:56:01.134322 LPDDR4 probe
635 02:56:01.134739 ddr clk to 1584MHz
636 02:56:01.141881 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 02:56:01.179087
638 02:56:01.179539 dmc_version 0001
639 02:56:01.185789 Check phy result
640 02:56:01.191632 INFO : End of CA training
641 02:56:01.192115 INFO : End of initialization
642 02:56:01.197229 INFO : Training has run successfully!
643 02:56:01.197677 Check phy result
644 02:56:01.202816 INFO : End of initialization
645 02:56:01.203264 INFO : End of read enable training
646 02:56:01.208431 INFO : End of fine write leveling
647 02:56:01.214031 INFO : End of Write leveling coarse delay
648 02:56:01.214477 INFO : Training has run successfully!
649 02:56:01.214889 Check phy result
650 02:56:01.219628 INFO : End of initialization
651 02:56:01.220109 INFO : End of read dq deskew training
652 02:56:01.225219 INFO : End of MPR read delay center optimization
653 02:56:01.230816 INFO : End of write delay center optimization
654 02:56:01.236436 INFO : End of read delay center optimization
655 02:56:01.236881 INFO : End of max read latency training
656 02:56:01.242051 INFO : Training has run successfully!
657 02:56:01.242527 1D training succeed
658 02:56:01.251204 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 02:56:01.298763 Check phy result
660 02:56:01.299215 INFO : End of initialization
661 02:56:01.320403 INFO : End of 2D read delay Voltage center optimization
662 02:56:01.340509 INFO : End of 2D read delay Voltage center optimization
663 02:56:01.392433 INFO : End of 2D write delay Voltage center optimization
664 02:56:01.441657 INFO : End of 2D write delay Voltage center optimization
665 02:56:01.447242 INFO : Training has run successfully!
666 02:56:01.447690
667 02:56:01.448147 channel==0
668 02:56:01.452865 RxClkDly_Margin_A0==88 ps 9
669 02:56:01.453316 TxDqDly_Margin_A0==98 ps 10
670 02:56:01.458428 RxClkDly_Margin_A1==88 ps 9
671 02:56:01.458870 TxDqDly_Margin_A1==98 ps 10
672 02:56:01.459289 TrainedVREFDQ_A0==74
673 02:56:01.464045 TrainedVREFDQ_A1==75
674 02:56:01.464510 VrefDac_Margin_A0==25
675 02:56:01.464924 DeviceVref_Margin_A0==40
676 02:56:01.469621 VrefDac_Margin_A1==25
677 02:56:01.470067 DeviceVref_Margin_A1==39
678 02:56:01.470478
679 02:56:01.470881
680 02:56:01.475228 channel==1
681 02:56:01.475674 RxClkDly_Margin_A0==98 ps 10
682 02:56:01.476119 TxDqDly_Margin_A0==88 ps 9
683 02:56:01.480844 RxClkDly_Margin_A1==88 ps 9
684 02:56:01.481290 TxDqDly_Margin_A1==88 ps 9
685 02:56:01.486432 TrainedVREFDQ_A0==77
686 02:56:01.486882 TrainedVREFDQ_A1==77
687 02:56:01.487296 VrefDac_Margin_A0==22
688 02:56:01.492047 DeviceVref_Margin_A0==37
689 02:56:01.492497 VrefDac_Margin_A1==24
690 02:56:01.497614 DeviceVref_Margin_A1==37
691 02:56:01.498061
692 02:56:01.498470 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 02:56:01.498871
694 02:56:01.531238 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000018 dram_vref_reg_value 0x 00000060
695 02:56:01.531718 2D training succeed
696 02:56:01.536901 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 02:56:01.542414 auto size-- 65535DDR cs0 size: 2048MB
698 02:56:01.542862 DDR cs1 size: 2048MB
699 02:56:01.548058 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 02:56:01.548514 cs0 DataBus test pass
701 02:56:01.553621 cs1 DataBus test pass
702 02:56:01.554066 cs0 AddrBus test pass
703 02:56:01.554471 cs1 AddrBus test pass
704 02:56:01.554876
705 02:56:01.559256 100bdlr_step_size ps== 420
706 02:56:01.559714 result report
707 02:56:01.564896 boot times 0Enable ddr reg access
708 02:56:01.570080 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 02:56:01.583558 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 02:56:02.155519 0.0;M3 CHK:0;cm4_sp_mode 0
711 02:56:02.156067 MVN_1=0x00000000
712 02:56:02.161047 MVN_2=0x00000000
713 02:56:02.166851 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 02:56:02.167381 OPS=0x10
715 02:56:02.167779 ring efuse init
716 02:56:02.168211 chipver efuse init
717 02:56:02.172394 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 02:56:02.177977 [0.018961 Inits done]
719 02:56:02.178411 secure task start!
720 02:56:02.178798 high task start!
721 02:56:02.182544 low task start!
722 02:56:02.182974 run into bl31
723 02:56:02.189174 NOTICE: BL31: v1.3(release):4fc40b1
724 02:56:02.196982 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 02:56:02.197417 NOTICE: BL31: G12A normal boot!
726 02:56:02.222375 NOTICE: BL31: BL33 decompress pass
727 02:56:02.228041 ERROR: Error initializing runtime service opteed_fast
728 02:56:03.460993
729 02:56:03.461599
730 02:56:03.469378 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 02:56:03.469846
732 02:56:03.470266 Model: Libre Computer AML-A311D-CC Alta
733 02:56:03.677749 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 02:56:03.701197 DRAM: 2 GiB (effective 3.8 GiB)
735 02:56:03.844181 Core: 408 devices, 31 uclasses, devicetree: separate
736 02:56:03.850011 WDT: Not starting watchdog@f0d0
737 02:56:03.882282 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 02:56:03.894753 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 02:56:03.899727 ** Bad device specification mmc 0 **
740 02:56:03.910059 Card did not respond to voltage select! : -110
741 02:56:03.917717 ** Bad device specification mmc 0 **
742 02:56:03.918170 Couldn't find partition mmc 0
743 02:56:03.926033 Card did not respond to voltage select! : -110
744 02:56:03.931574 ** Bad device specification mmc 0 **
745 02:56:03.932075 Couldn't find partition mmc 0
746 02:56:03.936620 Error: could not access storage.
747 02:56:04.280110 Net: eth0: ethernet@ff3f0000
748 02:56:04.280647 starting USB...
749 02:56:04.531918 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 02:56:04.532472 Starting the controller
751 02:56:04.538899 USB XHCI 1.10
752 02:56:06.701769 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 02:56:06.702362 bl2_stage_init 0x01
754 02:56:06.702796 bl2_stage_init 0x81
755 02:56:06.707448 hw id: 0x0000 - pwm id 0x01
756 02:56:06.707914 bl2_stage_init 0xc1
757 02:56:06.708373 bl2_stage_init 0x02
758 02:56:06.708788
759 02:56:06.713009 L0:00000000
760 02:56:06.713507 L1:20000703
761 02:56:06.713931 L2:00008067
762 02:56:06.714342 L3:14000000
763 02:56:06.718738 B2:00402000
764 02:56:06.719196 B1:e0f83180
765 02:56:06.719609
766 02:56:06.720045 TE: 58124
767 02:56:06.720461
768 02:56:06.724223 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 02:56:06.724683
770 02:56:06.725096 Board ID = 1
771 02:56:06.729750 Set A53 clk to 24M
772 02:56:06.730200 Set A73 clk to 24M
773 02:56:06.730609 Set clk81 to 24M
774 02:56:06.735393 A53 clk: 1200 MHz
775 02:56:06.735839 A73 clk: 1200 MHz
776 02:56:06.736279 CLK81: 166.6M
777 02:56:06.736686 smccc: 00012a92
778 02:56:06.741005 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 02:56:06.746553 board id: 1
780 02:56:06.752401 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 02:56:06.763014 fw parse done
782 02:56:06.769023 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 02:56:06.811653 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 02:56:06.822567 PIEI prepare done
785 02:56:06.823014 fastboot data load
786 02:56:06.823429 fastboot data verify
787 02:56:06.828237 verify result: 266
788 02:56:06.833820 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 02:56:06.834263 LPDDR4 probe
790 02:56:06.834672 ddr clk to 1584MHz
791 02:56:06.841813 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 02:56:06.879088
793 02:56:06.879586 dmc_version 0001
794 02:56:06.885780 Check phy result
795 02:56:06.891663 INFO : End of CA training
796 02:56:06.892133 INFO : End of initialization
797 02:56:06.897177 INFO : Training has run successfully!
798 02:56:06.897620 Check phy result
799 02:56:06.902790 INFO : End of initialization
800 02:56:06.903232 INFO : End of read enable training
801 02:56:06.908434 INFO : End of fine write leveling
802 02:56:06.914011 INFO : End of Write leveling coarse delay
803 02:56:06.914454 INFO : Training has run successfully!
804 02:56:06.914865 Check phy result
805 02:56:06.919648 INFO : End of initialization
806 02:56:06.920130 INFO : End of read dq deskew training
807 02:56:06.925246 INFO : End of MPR read delay center optimization
808 02:56:06.930792 INFO : End of write delay center optimization
809 02:56:06.936435 INFO : End of read delay center optimization
810 02:56:06.936886 INFO : End of max read latency training
811 02:56:06.942029 INFO : Training has run successfully!
812 02:56:06.942472 1D training succeed
813 02:56:06.951210 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 02:56:06.998777 Check phy result
815 02:56:06.999232 INFO : End of initialization
816 02:56:07.020360 INFO : End of 2D read delay Voltage center optimization
817 02:56:07.040469 INFO : End of 2D read delay Voltage center optimization
818 02:56:07.092412 INFO : End of 2D write delay Voltage center optimization
819 02:56:07.141634 INFO : End of 2D write delay Voltage center optimization
820 02:56:07.147256 INFO : Training has run successfully!
821 02:56:07.147704
822 02:56:07.148178 channel==0
823 02:56:07.152837 RxClkDly_Margin_A0==88 ps 9
824 02:56:07.153287 TxDqDly_Margin_A0==98 ps 10
825 02:56:07.158452 RxClkDly_Margin_A1==88 ps 9
826 02:56:07.158911 TxDqDly_Margin_A1==88 ps 9
827 02:56:07.159352 TrainedVREFDQ_A0==74
828 02:56:07.164106 TrainedVREFDQ_A1==74
829 02:56:07.164635 VrefDac_Margin_A0==25
830 02:56:07.165067 DeviceVref_Margin_A0==40
831 02:56:07.169679 VrefDac_Margin_A1==25
832 02:56:07.170167 DeviceVref_Margin_A1==40
833 02:56:07.170556
834 02:56:07.170941
835 02:56:07.171326 channel==1
836 02:56:07.175246 RxClkDly_Margin_A0==98 ps 10
837 02:56:07.175680 TxDqDly_Margin_A0==88 ps 9
838 02:56:07.180800 RxClkDly_Margin_A1==98 ps 10
839 02:56:07.181229 TxDqDly_Margin_A1==88 ps 9
840 02:56:07.186419 TrainedVREFDQ_A0==77
841 02:56:07.186847 TrainedVREFDQ_A1==77
842 02:56:07.187238 VrefDac_Margin_A0==22
843 02:56:07.192029 DeviceVref_Margin_A0==37
844 02:56:07.192460 VrefDac_Margin_A1==22
845 02:56:07.197565 DeviceVref_Margin_A1==37
846 02:56:07.197985
847 02:56:07.198374 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 02:56:07.198760
849 02:56:07.231181 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 02:56:07.231701 2D training succeed
851 02:56:07.236750 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 02:56:07.242375 auto size-- 65535DDR cs0 size: 2048MB
853 02:56:07.242812 DDR cs1 size: 2048MB
854 02:56:07.247951 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 02:56:07.248416 cs0 DataBus test pass
856 02:56:07.253572 cs1 DataBus test pass
857 02:56:07.253997 cs0 AddrBus test pass
858 02:56:07.254385 cs1 AddrBus test pass
859 02:56:07.254769
860 02:56:07.259153 100bdlr_step_size ps== 420
861 02:56:07.259622 result report
862 02:56:07.264741 boot times 0Enable ddr reg access
863 02:56:07.270022 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 02:56:07.283505 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 02:56:07.855595 0.0;M3 CHK:0;cm4_sp_mode 0
866 02:56:07.856230 MVN_1=0x00000000
867 02:56:07.861115 MVN_2=0x00000000
868 02:56:07.866825 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 02:56:07.867280 OPS=0x10
870 02:56:07.867698 ring efuse init
871 02:56:07.868138 chipver efuse init
872 02:56:07.875112 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 02:56:07.875577 [0.018961 Inits done]
874 02:56:07.876011 secure task start!
875 02:56:07.882640 high task start!
876 02:56:07.883088 low task start!
877 02:56:07.883497 run into bl31
878 02:56:07.889184 NOTICE: BL31: v1.3(release):4fc40b1
879 02:56:07.897027 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 02:56:07.897483 NOTICE: BL31: G12A normal boot!
881 02:56:07.922450 NOTICE: BL31: BL33 decompress pass
882 02:56:07.928185 ERROR: Error initializing runtime service opteed_fast
883 02:56:09.161105
884 02:56:09.161628
885 02:56:09.169496 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 02:56:09.169955
887 02:56:09.170375 Model: Libre Computer AML-A311D-CC Alta
888 02:56:09.377797 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 02:56:09.401257 DRAM: 2 GiB (effective 3.8 GiB)
890 02:56:09.544309 Core: 408 devices, 31 uclasses, devicetree: separate
891 02:56:09.550201 WDT: Not starting watchdog@f0d0
892 02:56:09.582391 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 02:56:09.594819 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 02:56:09.599853 ** Bad device specification mmc 0 **
895 02:56:09.610075 Card did not respond to voltage select! : -110
896 02:56:09.617888 ** Bad device specification mmc 0 **
897 02:56:09.618334 Couldn't find partition mmc 0
898 02:56:09.626135 Card did not respond to voltage select! : -110
899 02:56:09.631640 ** Bad device specification mmc 0 **
900 02:56:09.632114 Couldn't find partition mmc 0
901 02:56:09.636774 Error: could not access storage.
902 02:56:09.979242 Net: eth0: ethernet@ff3f0000
903 02:56:09.979746 starting USB...
904 02:56:10.230956 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 02:56:10.231476 Starting the controller
906 02:56:10.237918 USB XHCI 1.10
907 02:56:11.792286 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 02:56:11.800503 scanning usb for storage devices... 0 Storage Device(s) found
910 02:56:11.851975 Hit any key to stop autoboot: 1
911 02:56:11.852786 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
912 02:56:11.853381 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
913 02:56:11.853863 Setting prompt string to ['=>']
914 02:56:11.854349 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
915 02:56:11.868007 0
916 02:56:11.868867 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 02:56:11.869369 Sending with 10 millisecond of delay
919 02:56:13.003844 => setenv autoload no
920 02:56:13.014601 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
921 02:56:13.019449 setenv autoload no
922 02:56:13.020172 Sending with 10 millisecond of delay
924 02:56:14.816651 => setenv initrd_high 0xffffffff
925 02:56:14.827416 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
926 02:56:14.828282 setenv initrd_high 0xffffffff
927 02:56:14.829015 Sending with 10 millisecond of delay
929 02:56:16.445027 => setenv fdt_high 0xffffffff
930 02:56:16.455793 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
931 02:56:16.456688 setenv fdt_high 0xffffffff
932 02:56:16.457411 Sending with 10 millisecond of delay
934 02:56:16.749155 => dhcp
935 02:56:16.759840 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
936 02:56:16.760682 dhcp
937 02:56:16.761126 Speed: 1000, full duplex
938 02:56:16.761543 BOOTP broadcast 1
939 02:56:16.768622 DHCP client bound to address 192.168.6.27 (9 ms)
940 02:56:16.769359 Sending with 10 millisecond of delay
942 02:56:18.445461 => setenv serverip 192.168.6.2
943 02:56:18.456240 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
944 02:56:18.457117 setenv serverip 192.168.6.2
945 02:56:18.457799 Sending with 10 millisecond of delay
947 02:56:22.183152 => tftpboot 0x01080000 943552/tftp-deploy-gjta2qb4/kernel/uImage
948 02:56:22.193953 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 02:56:22.194748 tftpboot 0x01080000 943552/tftp-deploy-gjta2qb4/kernel/uImage
950 02:56:22.195205 Speed: 1000, full duplex
951 02:56:22.195620 Using ethernet@ff3f0000 device
952 02:56:22.196611 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 02:56:22.202133 Filename '943552/tftp-deploy-gjta2qb4/kernel/uImage'.
954 02:56:22.206061 Load address: 0x1080000
955 02:56:25.007812 Loading: *################################################## 43.7 MiB
956 02:56:25.008497 15.6 MiB/s
957 02:56:25.008946 done
958 02:56:25.012202 Bytes transferred = 45779520 (2ba8a40 hex)
959 02:56:25.013052 Sending with 10 millisecond of delay
961 02:56:29.704782 => tftpboot 0x08000000 943552/tftp-deploy-gjta2qb4/ramdisk/ramdisk.cpio.gz.uboot
962 02:56:29.715587 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
963 02:56:29.716532 tftpboot 0x08000000 943552/tftp-deploy-gjta2qb4/ramdisk/ramdisk.cpio.gz.uboot
964 02:56:29.716989 Speed: 1000, full duplex
965 02:56:29.717403 Using ethernet@ff3f0000 device
966 02:56:29.718731 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 02:56:29.730257 Filename '943552/tftp-deploy-gjta2qb4/ramdisk/ramdisk.cpio.gz.uboot'.
968 02:56:29.730824 Load address: 0x8000000
969 02:56:39.185364 Loading: *######T ########################################### UDP wrong checksum 0000000f 0000b5ee
970 02:56:44.186092 T UDP wrong checksum 0000000f 0000b5ee
971 02:56:54.188459 T T UDP wrong checksum 0000000f 0000b5ee
972 02:57:14.193197 T T T T UDP wrong checksum 0000000f 0000b5ee
973 02:57:29.197389 T T
974 02:57:29.198072 Retry count exceeded; starting again
976 02:57:29.199607 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
979 02:57:29.201731 end: 2.4 uboot-commands (duration 00:01:49) [common]
981 02:57:29.203239 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
983 02:57:29.204391 end: 2 uboot-action (duration 00:01:49) [common]
985 02:57:29.206024 Cleaning after the job
986 02:57:29.206599 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/ramdisk
987 02:57:29.208847 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/kernel
988 02:57:29.263916 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/dtb
989 02:57:29.266301 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943552/tftp-deploy-gjta2qb4/modules
990 02:57:29.294167 start: 4.1 power-off (timeout 00:00:30) [common]
991 02:57:29.294818 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
992 02:57:29.328458 >> OK - accepted request
993 02:57:29.330265 Returned 0 in 0 seconds
994 02:57:29.431285 end: 4.1 power-off (duration 00:00:00) [common]
996 02:57:29.432162 start: 4.2 read-feedback (timeout 00:10:00) [common]
997 02:57:29.432792 Listened to connection for namespace 'common' for up to 1s
998 02:57:30.433671 Finalising connection for namespace 'common'
999 02:57:30.434324 Disconnecting from shell: Finalise
1000 02:57:30.434889 =>
1001 02:57:30.535830 end: 4.2 read-feedback (duration 00:00:01) [common]
1002 02:57:30.536509 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/943552
1003 02:57:31.162227 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/943552
1004 02:57:31.162837 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.