Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 8
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 02:46:19.540204 lava-dispatcher, installed at version: 2024.01
2 02:46:19.540966 start: 0 validate
3 02:46:19.541446 Start time: 2024-11-06 02:46:19.541417+00:00 (UTC)
4 02:46:19.541983 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:46:19.542517 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:46:19.587033 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:46:19.587681 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:46:19.617851 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:46:19.618468 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:46:19.648970 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:46:19.649447 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:46:19.680103 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:46:19.680587 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:46:19.717482 validate duration: 0.18
16 02:46:19.718337 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:46:19.718659 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:46:19.718971 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:46:19.719532 Not decompressing ramdisk as can be used compressed.
20 02:46:19.719974 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 02:46:19.720296 saving as /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/ramdisk/initrd.cpio.gz
22 02:46:19.720570 total size: 5628169 (5 MB)
23 02:46:19.758051 progress 0 % (0 MB)
24 02:46:19.765343 progress 5 % (0 MB)
25 02:46:19.773595 progress 10 % (0 MB)
26 02:46:19.780811 progress 15 % (0 MB)
27 02:46:19.786585 progress 20 % (1 MB)
28 02:46:19.790339 progress 25 % (1 MB)
29 02:46:19.794450 progress 30 % (1 MB)
30 02:46:19.798700 progress 35 % (1 MB)
31 02:46:19.802488 progress 40 % (2 MB)
32 02:46:19.806673 progress 45 % (2 MB)
33 02:46:19.810361 progress 50 % (2 MB)
34 02:46:19.814487 progress 55 % (2 MB)
35 02:46:19.818567 progress 60 % (3 MB)
36 02:46:19.822195 progress 65 % (3 MB)
37 02:46:19.826370 progress 70 % (3 MB)
38 02:46:19.829977 progress 75 % (4 MB)
39 02:46:19.834119 progress 80 % (4 MB)
40 02:46:19.837709 progress 85 % (4 MB)
41 02:46:19.841778 progress 90 % (4 MB)
42 02:46:19.845606 progress 95 % (5 MB)
43 02:46:19.848891 progress 100 % (5 MB)
44 02:46:19.849618 5 MB downloaded in 0.13 s (41.63 MB/s)
45 02:46:19.850173 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:46:19.851070 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:46:19.851371 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:46:19.851640 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:46:19.852241 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kernel/Image
51 02:46:19.852522 saving as /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/kernel/Image
52 02:46:19.852735 total size: 45779456 (43 MB)
53 02:46:19.852947 No compression specified
54 02:46:19.888204 progress 0 % (0 MB)
55 02:46:19.916055 progress 5 % (2 MB)
56 02:46:19.944477 progress 10 % (4 MB)
57 02:46:19.972342 progress 15 % (6 MB)
58 02:46:20.000407 progress 20 % (8 MB)
59 02:46:20.028583 progress 25 % (10 MB)
60 02:46:20.056592 progress 30 % (13 MB)
61 02:46:20.084163 progress 35 % (15 MB)
62 02:46:20.112103 progress 40 % (17 MB)
63 02:46:20.140003 progress 45 % (19 MB)
64 02:46:20.168080 progress 50 % (21 MB)
65 02:46:20.196272 progress 55 % (24 MB)
66 02:46:20.224116 progress 60 % (26 MB)
67 02:46:20.252072 progress 65 % (28 MB)
68 02:46:20.279727 progress 70 % (30 MB)
69 02:46:20.307770 progress 75 % (32 MB)
70 02:46:20.335973 progress 80 % (34 MB)
71 02:46:20.363903 progress 85 % (37 MB)
72 02:46:20.391828 progress 90 % (39 MB)
73 02:46:20.419745 progress 95 % (41 MB)
74 02:46:20.447221 progress 100 % (43 MB)
75 02:46:20.447742 43 MB downloaded in 0.59 s (73.38 MB/s)
76 02:46:20.448243 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:46:20.449079 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:46:20.449356 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:46:20.449622 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:46:20.450091 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:46:20.450364 saving as /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:46:20.450573 total size: 54703 (0 MB)
84 02:46:20.450899 No compression specified
85 02:46:20.490299 progress 59 % (0 MB)
86 02:46:20.491138 progress 100 % (0 MB)
87 02:46:20.491696 0 MB downloaded in 0.04 s (1.27 MB/s)
88 02:46:20.492192 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:46:20.493021 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:46:20.493284 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:46:20.493546 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:46:20.493993 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 02:46:20.494233 saving as /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/nfsrootfs/full.rootfs.tar
95 02:46:20.494437 total size: 120894716 (115 MB)
96 02:46:20.494646 Using unxz to decompress xz
97 02:46:20.528072 progress 0 % (0 MB)
98 02:46:21.416204 progress 5 % (5 MB)
99 02:46:22.302687 progress 10 % (11 MB)
100 02:46:23.092527 progress 15 % (17 MB)
101 02:46:23.824964 progress 20 % (23 MB)
102 02:46:24.423845 progress 25 % (28 MB)
103 02:46:25.261013 progress 30 % (34 MB)
104 02:46:26.051515 progress 35 % (40 MB)
105 02:46:26.397553 progress 40 % (46 MB)
106 02:46:26.766684 progress 45 % (51 MB)
107 02:46:27.481265 progress 50 % (57 MB)
108 02:46:28.359574 progress 55 % (63 MB)
109 02:46:29.133576 progress 60 % (69 MB)
110 02:46:29.892113 progress 65 % (74 MB)
111 02:46:30.674346 progress 70 % (80 MB)
112 02:46:31.490696 progress 75 % (86 MB)
113 02:46:32.274824 progress 80 % (92 MB)
114 02:46:33.033895 progress 85 % (98 MB)
115 02:46:33.885683 progress 90 % (103 MB)
116 02:46:34.663107 progress 95 % (109 MB)
117 02:46:35.491962 progress 100 % (115 MB)
118 02:46:35.504994 115 MB downloaded in 15.01 s (7.68 MB/s)
119 02:46:35.505860 end: 1.4.1 http-download (duration 00:00:15) [common]
121 02:46:35.507475 end: 1.4 download-retry (duration 00:00:15) [common]
122 02:46:35.508044 start: 1.5 download-retry (timeout 00:09:44) [common]
123 02:46:35.508584 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 02:46:35.509406 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/modules.tar.xz
125 02:46:35.509876 saving as /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/modules/modules.tar
126 02:46:35.510292 total size: 11613264 (11 MB)
127 02:46:35.510715 Using unxz to decompress xz
128 02:46:35.549877 progress 0 % (0 MB)
129 02:46:35.615668 progress 5 % (0 MB)
130 02:46:35.689121 progress 10 % (1 MB)
131 02:46:35.783918 progress 15 % (1 MB)
132 02:46:35.875155 progress 20 % (2 MB)
133 02:46:35.954209 progress 25 % (2 MB)
134 02:46:36.029372 progress 30 % (3 MB)
135 02:46:36.107132 progress 35 % (3 MB)
136 02:46:36.178995 progress 40 % (4 MB)
137 02:46:36.254270 progress 45 % (5 MB)
138 02:46:36.337703 progress 50 % (5 MB)
139 02:46:36.414825 progress 55 % (6 MB)
140 02:46:36.499439 progress 60 % (6 MB)
141 02:46:36.579242 progress 65 % (7 MB)
142 02:46:36.661338 progress 70 % (7 MB)
143 02:46:36.739601 progress 75 % (8 MB)
144 02:46:36.822369 progress 80 % (8 MB)
145 02:46:36.902781 progress 85 % (9 MB)
146 02:46:36.980762 progress 90 % (9 MB)
147 02:46:37.057938 progress 95 % (10 MB)
148 02:46:37.134049 progress 100 % (11 MB)
149 02:46:37.145733 11 MB downloaded in 1.64 s (6.77 MB/s)
150 02:46:37.146317 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:46:37.147149 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:46:37.147424 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 02:46:37.147695 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 02:46:53.552732 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/943521/extract-nfsrootfs-7e1yg237
156 02:46:53.553372 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 02:46:53.553669 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 02:46:53.554405 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3
159 02:46:53.554886 makedir: /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin
160 02:46:53.555290 makedir: /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/tests
161 02:46:53.555644 makedir: /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/results
162 02:46:53.556020 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-add-keys
163 02:46:53.556598 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-add-sources
164 02:46:53.557143 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-background-process-start
165 02:46:53.557677 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-background-process-stop
166 02:46:53.558240 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-common-functions
167 02:46:53.558771 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-echo-ipv4
168 02:46:53.559283 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-install-packages
169 02:46:53.559795 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-installed-packages
170 02:46:53.560344 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-os-build
171 02:46:53.560856 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-probe-channel
172 02:46:53.561365 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-probe-ip
173 02:46:53.561879 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-target-ip
174 02:46:53.562393 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-target-mac
175 02:46:53.562911 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-target-storage
176 02:46:53.563436 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-test-case
177 02:46:53.563952 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-test-event
178 02:46:53.564512 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-test-feedback
179 02:46:53.565078 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-test-raise
180 02:46:53.565633 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-test-reference
181 02:46:53.566155 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-test-runner
182 02:46:53.566683 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-test-set
183 02:46:53.567197 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-test-shell
184 02:46:53.567721 Updating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-add-keys (debian)
185 02:46:53.568346 Updating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-add-sources (debian)
186 02:46:53.568952 Updating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-install-packages (debian)
187 02:46:53.569514 Updating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-installed-packages (debian)
188 02:46:53.570062 Updating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/bin/lava-os-build (debian)
189 02:46:53.570546 Creating /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/environment
190 02:46:53.570972 LAVA metadata
191 02:46:53.571251 - LAVA_JOB_ID=943521
192 02:46:53.571471 - LAVA_DISPATCHER_IP=192.168.6.2
193 02:46:53.571867 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 02:46:53.572952 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 02:46:53.573309 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 02:46:53.573524 skipped lava-vland-overlay
197 02:46:53.573770 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 02:46:53.574030 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 02:46:53.574255 skipped lava-multinode-overlay
200 02:46:53.574501 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 02:46:53.574756 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 02:46:53.575015 Loading test definitions
203 02:46:53.575307 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 02:46:53.575532 Using /lava-943521 at stage 0
205 02:46:53.576788 uuid=943521_1.6.2.4.1 testdef=None
206 02:46:53.577158 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 02:46:53.577435 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 02:46:53.579152 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 02:46:53.580071 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 02:46:53.582244 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 02:46:53.583123 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 02:46:53.585111 runner path: /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/0/tests/0_timesync-off test_uuid 943521_1.6.2.4.1
215 02:46:53.585721 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 02:46:53.586556 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 02:46:53.586805 Using /lava-943521 at stage 0
219 02:46:53.587181 Fetching tests from https://github.com/kernelci/test-definitions.git
220 02:46:53.587485 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/0/tests/1_kselftest-alsa'
221 02:46:57.119256 Running '/usr/bin/git checkout kernelci.org
222 02:46:57.283796 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 02:46:57.285254 uuid=943521_1.6.2.4.5 testdef=None
224 02:46:57.285600 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 02:46:57.286350 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 02:46:57.289252 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 02:46:57.290071 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 02:46:57.293816 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 02:46:57.294667 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 02:46:57.298280 runner path: /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/0/tests/1_kselftest-alsa test_uuid 943521_1.6.2.4.5
234 02:46:57.298566 BOARD='meson-g12b-a311d-libretech-cc'
235 02:46:57.298771 BRANCH='clk'
236 02:46:57.298968 SKIPFILE='/dev/null'
237 02:46:57.299164 SKIP_INSTALL='True'
238 02:46:57.299359 TESTPROG_URL='http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 02:46:57.299557 TST_CASENAME=''
240 02:46:57.299752 TST_CMDFILES='alsa'
241 02:46:57.300352 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 02:46:57.301157 Creating lava-test-runner.conf files
244 02:46:57.301362 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/943521/lava-overlay-v124eec3/lava-943521/0 for stage 0
245 02:46:57.301713 - 0_timesync-off
246 02:46:57.301953 - 1_kselftest-alsa
247 02:46:57.302281 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 02:46:57.302561 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 02:47:20.576596 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 02:47:20.577043 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 02:47:20.577312 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 02:47:20.577588 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 02:47:20.577858 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 02:47:21.187289 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 02:47:21.187766 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
256 02:47:21.188055 extracting modules file /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943521/extract-nfsrootfs-7e1yg237
257 02:47:22.545369 extracting modules file /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943521/extract-overlay-ramdisk-suraox69/ramdisk
258 02:47:23.960557 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 02:47:23.961189 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 02:47:23.961558 [common] Applying overlay to NFS
261 02:47:23.961789 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943521/compress-overlay-eaf3effz/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/943521/extract-nfsrootfs-7e1yg237
262 02:47:26.698758 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 02:47:26.699245 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 02:47:26.699518 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 02:47:26.699750 Converting downloaded kernel to a uImage
266 02:47:26.700081 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/kernel/Image /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/kernel/uImage
267 02:47:27.184909 output: Image Name:
268 02:47:27.185321 output: Created: Wed Nov 6 02:47:26 2024
269 02:47:27.185532 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 02:47:27.185737 output: Data Size: 45779456 Bytes = 44706.50 KiB = 43.66 MiB
271 02:47:27.185938 output: Load Address: 01080000
272 02:47:27.186139 output: Entry Point: 01080000
273 02:47:27.186339 output:
274 02:47:27.186669 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 02:47:27.186937 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 02:47:27.187208 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
277 02:47:27.187464 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 02:47:27.187724 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
279 02:47:27.188014 Building ramdisk /var/lib/lava/dispatcher/tmp/943521/extract-overlay-ramdisk-suraox69/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/943521/extract-overlay-ramdisk-suraox69/ramdisk
280 02:47:29.401344 >> 166772 blocks
281 02:47:37.276382 Adding RAMdisk u-boot header.
282 02:47:37.277046 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/943521/extract-overlay-ramdisk-suraox69/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/943521/extract-overlay-ramdisk-suraox69/ramdisk.cpio.gz.uboot
283 02:47:37.518994 output: Image Name:
284 02:47:37.519400 output: Created: Wed Nov 6 02:47:37 2024
285 02:47:37.519610 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 02:47:37.519815 output: Data Size: 23427478 Bytes = 22878.40 KiB = 22.34 MiB
287 02:47:37.520146 output: Load Address: 00000000
288 02:47:37.520597 output: Entry Point: 00000000
289 02:47:37.521052 output:
290 02:47:37.522229 rename /var/lib/lava/dispatcher/tmp/943521/extract-overlay-ramdisk-suraox69/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/ramdisk/ramdisk.cpio.gz.uboot
291 02:47:37.523011 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 02:47:37.523605 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 02:47:37.524231 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 02:47:37.524735 No LXC device requested
295 02:47:37.525280 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 02:47:37.525844 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 02:47:37.526388 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 02:47:37.526840 Checking files for TFTP limit of 4294967296 bytes.
299 02:47:37.529782 end: 1 tftp-deploy (duration 00:01:18) [common]
300 02:47:37.530418 start: 2 uboot-action (timeout 00:05:00) [common]
301 02:47:37.530993 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 02:47:37.531545 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 02:47:37.532130 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 02:47:37.532718 Using kernel file from prepare-kernel: 943521/tftp-deploy-ss4p34vt/kernel/uImage
305 02:47:37.533405 substitutions:
306 02:47:37.533858 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 02:47:37.534307 - {DTB_ADDR}: 0x01070000
308 02:47:37.534749 - {DTB}: 943521/tftp-deploy-ss4p34vt/dtb/meson-g12b-a311d-libretech-cc.dtb
309 02:47:37.535195 - {INITRD}: 943521/tftp-deploy-ss4p34vt/ramdisk/ramdisk.cpio.gz.uboot
310 02:47:37.535636 - {KERNEL_ADDR}: 0x01080000
311 02:47:37.536107 - {KERNEL}: 943521/tftp-deploy-ss4p34vt/kernel/uImage
312 02:47:37.536546 - {LAVA_MAC}: None
313 02:47:37.537019 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/943521/extract-nfsrootfs-7e1yg237
314 02:47:37.537460 - {NFS_SERVER_IP}: 192.168.6.2
315 02:47:37.537893 - {PRESEED_CONFIG}: None
316 02:47:37.538327 - {PRESEED_LOCAL}: None
317 02:47:37.538760 - {RAMDISK_ADDR}: 0x08000000
318 02:47:37.539187 - {RAMDISK}: 943521/tftp-deploy-ss4p34vt/ramdisk/ramdisk.cpio.gz.uboot
319 02:47:37.539618 - {ROOT_PART}: None
320 02:47:37.540102 - {ROOT}: None
321 02:47:37.540540 - {SERVER_IP}: 192.168.6.2
322 02:47:37.540970 - {TEE_ADDR}: 0x83000000
323 02:47:37.541395 - {TEE}: None
324 02:47:37.541822 Parsed boot commands:
325 02:47:37.542239 - setenv autoload no
326 02:47:37.542665 - setenv initrd_high 0xffffffff
327 02:47:37.543091 - setenv fdt_high 0xffffffff
328 02:47:37.543516 - dhcp
329 02:47:37.543941 - setenv serverip 192.168.6.2
330 02:47:37.544407 - tftpboot 0x01080000 943521/tftp-deploy-ss4p34vt/kernel/uImage
331 02:47:37.544845 - tftpboot 0x08000000 943521/tftp-deploy-ss4p34vt/ramdisk/ramdisk.cpio.gz.uboot
332 02:47:37.545278 - tftpboot 0x01070000 943521/tftp-deploy-ss4p34vt/dtb/meson-g12b-a311d-libretech-cc.dtb
333 02:47:37.545709 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943521/extract-nfsrootfs-7e1yg237,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 02:47:37.546151 - bootm 0x01080000 0x08000000 0x01070000
335 02:47:37.546703 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 02:47:37.548369 start: 2.3 connect-device (timeout 00:05:00) [common]
338 02:47:37.548831 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 02:47:37.564369 Setting prompt string to ['lava-test: # ']
340 02:47:37.565981 end: 2.3 connect-device (duration 00:00:00) [common]
341 02:47:37.566653 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 02:47:37.567256 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 02:47:37.567832 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 02:47:37.569105 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 02:47:37.608674 >> OK - accepted request
346 02:47:37.610516 Returned 0 in 0 seconds
347 02:47:37.711659 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 02:47:37.713441 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 02:47:37.714029 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 02:47:37.714575 Setting prompt string to ['Hit any key to stop autoboot']
352 02:47:37.715057 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 02:47:37.716751 Trying 192.168.56.21...
354 02:47:37.717277 Connected to conserv1.
355 02:47:37.717719 Escape character is '^]'.
356 02:47:37.718173
357 02:47:37.718633 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 02:47:37.719089
359 02:47:49.408182 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 02:47:49.408848 bl2_stage_init 0x01
361 02:47:49.409311 bl2_stage_init 0x81
362 02:47:49.413781 hw id: 0x0000 - pwm id 0x01
363 02:47:49.414326 bl2_stage_init 0xc1
364 02:47:49.414789 bl2_stage_init 0x02
365 02:47:49.415224
366 02:47:49.419385 L0:00000000
367 02:47:49.419904 L1:20000703
368 02:47:49.420390 L2:00008067
369 02:47:49.420821 L3:14000000
370 02:47:49.422357 B2:00402000
371 02:47:49.422849 B1:e0f83180
372 02:47:49.423287
373 02:47:49.423702 TE: 58124
374 02:47:49.424296
375 02:47:49.433502 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 02:47:49.433992
377 02:47:49.434432 Board ID = 1
378 02:47:49.434867 Set A53 clk to 24M
379 02:47:49.435300 Set A73 clk to 24M
380 02:47:49.439309 Set clk81 to 24M
381 02:47:49.439790 A53 clk: 1200 MHz
382 02:47:49.440261 A73 clk: 1200 MHz
383 02:47:49.444773 CLK81: 166.6M
384 02:47:49.445237 smccc: 00012a91
385 02:47:49.450252 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 02:47:49.450715 board id: 1
387 02:47:49.458822 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 02:47:49.469367 fw parse done
389 02:47:49.475327 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 02:47:49.517963 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 02:47:49.528796 PIEI prepare done
392 02:47:49.529264 fastboot data load
393 02:47:49.529701 fastboot data verify
394 02:47:49.534530 verify result: 266
395 02:47:49.540089 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 02:47:49.540553 LPDDR4 probe
397 02:47:49.540983 ddr clk to 1584MHz
398 02:47:49.548082 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 02:47:49.584367
400 02:47:49.584878 dmc_version 0001
401 02:47:49.592085 Check phy result
402 02:47:49.597881 INFO : End of CA training
403 02:47:49.598371 INFO : End of initialization
404 02:47:49.603505 INFO : Training has run successfully!
405 02:47:49.604013 Check phy result
406 02:47:49.609131 INFO : End of initialization
407 02:47:49.609620 INFO : End of read enable training
408 02:47:49.612581 INFO : End of fine write leveling
409 02:47:49.618257 INFO : End of Write leveling coarse delay
410 02:47:49.623755 INFO : Training has run successfully!
411 02:47:49.624270 Check phy result
412 02:47:49.624740 INFO : End of initialization
413 02:47:49.629314 INFO : End of read dq deskew training
414 02:47:49.634918 INFO : End of MPR read delay center optimization
415 02:47:49.635404 INFO : End of write delay center optimization
416 02:47:49.640552 INFO : End of read delay center optimization
417 02:47:49.646140 INFO : End of max read latency training
418 02:47:49.646623 INFO : Training has run successfully!
419 02:47:49.651722 1D training succeed
420 02:47:49.657610 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 02:47:49.705053 Check phy result
422 02:47:49.705536 INFO : End of initialization
423 02:47:49.726849 INFO : End of 2D read delay Voltage center optimization
424 02:47:49.747102 INFO : End of 2D read delay Voltage center optimization
425 02:47:49.799164 INFO : End of 2D write delay Voltage center optimization
426 02:47:49.848582 INFO : End of 2D write delay Voltage center optimization
427 02:47:49.854045 INFO : Training has run successfully!
428 02:47:49.854537
429 02:47:49.854994 channel==0
430 02:47:49.859702 RxClkDly_Margin_A0==78 ps 8
431 02:47:49.860238 TxDqDly_Margin_A0==98 ps 10
432 02:47:49.862964 RxClkDly_Margin_A1==88 ps 9
433 02:47:49.863449 TxDqDly_Margin_A1==98 ps 10
434 02:47:49.868564 TrainedVREFDQ_A0==74
435 02:47:49.869062 TrainedVREFDQ_A1==74
436 02:47:49.874132 VrefDac_Margin_A0==25
437 02:47:49.874621 DeviceVref_Margin_A0==40
438 02:47:49.875079 VrefDac_Margin_A1==25
439 02:47:49.879775 DeviceVref_Margin_A1==40
440 02:47:49.880288
441 02:47:49.880749
442 02:47:49.881200 channel==1
443 02:47:49.881641 RxClkDly_Margin_A0==98 ps 10
444 02:47:49.885342 TxDqDly_Margin_A0==88 ps 9
445 02:47:49.885834 RxClkDly_Margin_A1==98 ps 10
446 02:47:49.890945 TxDqDly_Margin_A1==88 ps 9
447 02:47:49.891437 TrainedVREFDQ_A0==77
448 02:47:49.891893 TrainedVREFDQ_A1==77
449 02:47:49.896595 VrefDac_Margin_A0==22
450 02:47:49.897084 DeviceVref_Margin_A0==37
451 02:47:49.902164 VrefDac_Margin_A1==22
452 02:47:49.902660 DeviceVref_Margin_A1==37
453 02:47:49.903117
454 02:47:49.907697 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 02:47:49.908221
456 02:47:49.935680 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 02:47:49.941270 2D training succeed
458 02:47:49.946931 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 02:47:49.947430 auto size-- 65535DDR cs0 size: 2048MB
460 02:47:49.952542 DDR cs1 size: 2048MB
461 02:47:49.953037 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 02:47:49.958070 cs0 DataBus test pass
463 02:47:49.958560 cs1 DataBus test pass
464 02:47:49.959013 cs0 AddrBus test pass
465 02:47:49.963690 cs1 AddrBus test pass
466 02:47:49.964220
467 02:47:49.964680 100bdlr_step_size ps== 420
468 02:47:49.965139 result report
469 02:47:49.969274 boot times 0Enable ddr reg access
470 02:47:49.977030 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 02:47:49.990619 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 02:47:50.564291 0.0;M3 CHK:0;cm4_sp_mode 0
473 02:47:50.564931 MVN_1=0x00000000
474 02:47:50.569716 MVN_2=0x00000000
475 02:47:50.575457 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 02:47:50.575959 OPS=0x10
477 02:47:50.576483 ring efuse init
478 02:47:50.576939 chipver efuse init
479 02:47:50.580966 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 02:47:50.586691 [0.018961 Inits done]
481 02:47:50.587208 secure task start!
482 02:47:50.587668 high task start!
483 02:47:50.591356 low task start!
484 02:47:50.591858 run into bl31
485 02:47:50.597837 NOTICE: BL31: v1.3(release):4fc40b1
486 02:47:50.605739 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 02:47:50.606249 NOTICE: BL31: G12A normal boot!
488 02:47:50.631026 NOTICE: BL31: BL33 decompress pass
489 02:47:50.636739 ERROR: Error initializing runtime service opteed_fast
490 02:47:51.869788
491 02:47:51.870420
492 02:47:51.878035 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 02:47:51.878541
494 02:47:51.879007 Model: Libre Computer AML-A311D-CC Alta
495 02:47:52.086539 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 02:47:52.109880 DRAM: 2 GiB (effective 3.8 GiB)
497 02:47:52.252798 Core: 408 devices, 31 uclasses, devicetree: separate
498 02:47:52.258816 WDT: Not starting watchdog@f0d0
499 02:47:52.290920 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 02:47:52.303321 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 02:47:52.308418 ** Bad device specification mmc 0 **
502 02:47:52.318757 Card did not respond to voltage select! : -110
503 02:47:52.326428 ** Bad device specification mmc 0 **
504 02:47:52.326927 Couldn't find partition mmc 0
505 02:47:52.334732 Card did not respond to voltage select! : -110
506 02:47:52.340261 ** Bad device specification mmc 0 **
507 02:47:52.340743 Couldn't find partition mmc 0
508 02:47:52.345287 Error: could not access storage.
509 02:47:53.608706 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 02:47:53.609348 bl2_stage_init 0x01
511 02:47:53.609836 bl2_stage_init 0x81
512 02:47:53.614390 hw id: 0x0000 - pwm id 0x01
513 02:47:53.614878 bl2_stage_init 0xc1
514 02:47:53.615338 bl2_stage_init 0x02
515 02:47:53.615787
516 02:47:53.619893 L0:00000000
517 02:47:53.620408 L1:20000703
518 02:47:53.620863 L2:00008067
519 02:47:53.621312 L3:14000000
520 02:47:53.625552 B2:00402000
521 02:47:53.626032 B1:e0f83180
522 02:47:53.626482
523 02:47:53.626926 TE: 58159
524 02:47:53.627372
525 02:47:53.631068 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 02:47:53.631556
527 02:47:53.632038 Board ID = 1
528 02:47:53.636544 Set A53 clk to 24M
529 02:47:53.637027 Set A73 clk to 24M
530 02:47:53.637483 Set clk81 to 24M
531 02:47:53.642165 A53 clk: 1200 MHz
532 02:47:53.642636 A73 clk: 1200 MHz
533 02:47:53.643081 CLK81: 166.6M
534 02:47:53.643519 smccc: 00012ab5
535 02:47:53.647823 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 02:47:53.653390 board id: 1
537 02:47:53.659230 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 02:47:53.669873 fw parse done
539 02:47:53.675942 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 02:47:53.718530 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 02:47:53.729411 PIEI prepare done
542 02:47:53.729885 fastboot data load
543 02:47:53.730341 fastboot data verify
544 02:47:53.735029 verify result: 266
545 02:47:53.740555 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 02:47:53.741027 LPDDR4 probe
547 02:47:53.741472 ddr clk to 1584MHz
548 02:47:53.748587 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 02:47:53.785813
550 02:47:53.786316 dmc_version 0001
551 02:47:53.792485 Check phy result
552 02:47:53.798322 INFO : End of CA training
553 02:47:53.798793 INFO : End of initialization
554 02:47:53.804082 INFO : Training has run successfully!
555 02:47:53.804557 Check phy result
556 02:47:53.809552 INFO : End of initialization
557 02:47:53.810022 INFO : End of read enable training
558 02:47:53.812861 INFO : End of fine write leveling
559 02:47:53.818373 INFO : End of Write leveling coarse delay
560 02:47:53.824070 INFO : Training has run successfully!
561 02:47:53.824548 Check phy result
562 02:47:53.825003 INFO : End of initialization
563 02:47:53.829570 INFO : End of read dq deskew training
564 02:47:53.835158 INFO : End of MPR read delay center optimization
565 02:47:53.835629 INFO : End of write delay center optimization
566 02:47:53.840799 INFO : End of read delay center optimization
567 02:47:53.846394 INFO : End of max read latency training
568 02:47:53.846865 INFO : Training has run successfully!
569 02:47:53.852076 1D training succeed
570 02:47:53.857961 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 02:47:53.905511 Check phy result
572 02:47:53.905982 INFO : End of initialization
573 02:47:53.927180 INFO : End of 2D read delay Voltage center optimization
574 02:47:53.947328 INFO : End of 2D read delay Voltage center optimization
575 02:47:53.999246 INFO : End of 2D write delay Voltage center optimization
576 02:47:54.048359 INFO : End of 2D write delay Voltage center optimization
577 02:47:54.054142 INFO : Training has run successfully!
578 02:47:54.054615
579 02:47:54.055073 channel==0
580 02:47:54.059624 RxClkDly_Margin_A0==88 ps 9
581 02:47:54.060130 TxDqDly_Margin_A0==98 ps 10
582 02:47:54.065220 RxClkDly_Margin_A1==88 ps 9
583 02:47:54.065686 TxDqDly_Margin_A1==98 ps 10
584 02:47:54.066138 TrainedVREFDQ_A0==74
585 02:47:54.070833 TrainedVREFDQ_A1==75
586 02:47:54.071307 VrefDac_Margin_A0==25
587 02:47:54.071751 DeviceVref_Margin_A0==40
588 02:47:54.076345 VrefDac_Margin_A1==25
589 02:47:54.076820 DeviceVref_Margin_A1==39
590 02:47:54.077265
591 02:47:54.077711
592 02:47:54.082136 channel==1
593 02:47:54.082607 RxClkDly_Margin_A0==98 ps 10
594 02:47:54.083051 TxDqDly_Margin_A0==98 ps 10
595 02:47:54.087560 RxClkDly_Margin_A1==88 ps 9
596 02:47:54.088063 TxDqDly_Margin_A1==88 ps 9
597 02:47:54.093157 TrainedVREFDQ_A0==77
598 02:47:54.093634 TrainedVREFDQ_A1==77
599 02:47:54.094083 VrefDac_Margin_A0==22
600 02:47:54.098857 DeviceVref_Margin_A0==37
601 02:47:54.099326 VrefDac_Margin_A1==24
602 02:47:54.104451 DeviceVref_Margin_A1==37
603 02:47:54.104934
604 02:47:54.105388 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 02:47:54.105833
606 02:47:54.138141 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 02:47:54.138657 2D training succeed
608 02:47:54.143563 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 02:47:54.149105 auto size-- 65535DDR cs0 size: 2048MB
610 02:47:54.149588 DDR cs1 size: 2048MB
611 02:47:54.154705 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 02:47:54.155223 cs0 DataBus test pass
613 02:47:54.160299 cs1 DataBus test pass
614 02:47:54.160812 cs0 AddrBus test pass
615 02:47:54.161276 cs1 AddrBus test pass
616 02:47:54.161728
617 02:47:54.165894 100bdlr_step_size ps== 420
618 02:47:54.166392 result report
619 02:47:54.171497 boot times 0Enable ddr reg access
620 02:47:54.176890 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 02:47:54.190415 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 02:47:54.762460 0.0;M3 CHK:0;cm4_sp_mode 0
623 02:47:54.763143 MVN_1=0x00000000
624 02:47:54.767910 MVN_2=0x00000000
625 02:47:54.773622 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 02:47:54.774148 OPS=0x10
627 02:47:54.774616 ring efuse init
628 02:47:54.775095 chipver efuse init
629 02:47:54.779224 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 02:47:54.784800 [0.018960 Inits done]
631 02:47:54.785273 secure task start!
632 02:47:54.785707 high task start!
633 02:47:54.789386 low task start!
634 02:47:54.789852 run into bl31
635 02:47:54.796139 NOTICE: BL31: v1.3(release):4fc40b1
636 02:47:54.803825 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 02:47:54.804325 NOTICE: BL31: G12A normal boot!
638 02:47:54.829188 NOTICE: BL31: BL33 decompress pass
639 02:47:54.834862 ERROR: Error initializing runtime service opteed_fast
640 02:47:56.067780
641 02:47:56.068453
642 02:47:56.076187 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 02:47:56.076678
644 02:47:56.077132 Model: Libre Computer AML-A311D-CC Alta
645 02:47:56.284595 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 02:47:56.307948 DRAM: 2 GiB (effective 3.8 GiB)
647 02:47:56.451188 Core: 408 devices, 31 uclasses, devicetree: separate
648 02:47:56.456920 WDT: Not starting watchdog@f0d0
649 02:47:56.489282 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 02:47:56.501618 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 02:47:56.506536 ** Bad device specification mmc 0 **
652 02:47:56.516917 Card did not respond to voltage select! : -110
653 02:47:56.524551 ** Bad device specification mmc 0 **
654 02:47:56.525158 Couldn't find partition mmc 0
655 02:47:56.533001 Card did not respond to voltage select! : -110
656 02:47:56.538391 ** Bad device specification mmc 0 **
657 02:47:56.538931 Couldn't find partition mmc 0
658 02:47:56.543437 Error: could not access storage.
659 02:47:56.885883 Net: eth0: ethernet@ff3f0000
660 02:47:56.886552 starting USB...
661 02:47:57.137733 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 02:47:57.138350 Starting the controller
663 02:47:57.144653 USB XHCI 1.10
664 02:47:58.859493 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 02:47:58.860169 bl2_stage_init 0x01
666 02:47:58.860609 bl2_stage_init 0x81
667 02:47:58.865000 hw id: 0x0000 - pwm id 0x01
668 02:47:58.865482 bl2_stage_init 0xc1
669 02:47:58.865902 bl2_stage_init 0x02
670 02:47:58.866313
671 02:47:58.870758 L0:00000000
672 02:47:58.871231 L1:20000703
673 02:47:58.871649 L2:00008067
674 02:47:58.872090 L3:14000000
675 02:47:58.876229 B2:00402000
676 02:47:58.876708 B1:e0f83180
677 02:47:58.877119
678 02:47:58.877527 TE: 58167
679 02:47:58.877929
680 02:47:58.881820 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 02:47:58.882296
682 02:47:58.882706 Board ID = 1
683 02:47:58.887496 Set A53 clk to 24M
684 02:47:58.887963 Set A73 clk to 24M
685 02:47:58.888416 Set clk81 to 24M
686 02:47:58.892999 A53 clk: 1200 MHz
687 02:47:58.893464 A73 clk: 1200 MHz
688 02:47:58.893875 CLK81: 166.6M
689 02:47:58.894280 smccc: 00012abd
690 02:47:58.898755 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 02:47:58.904192 board id: 1
692 02:47:58.910053 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 02:47:58.920725 fw parse done
694 02:47:58.926786 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 02:47:58.969286 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 02:47:58.980282 PIEI prepare done
697 02:47:58.980785 fastboot data load
698 02:47:58.981211 fastboot data verify
699 02:47:58.985961 verify result: 266
700 02:47:58.991589 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 02:47:58.992090 LPDDR4 probe
702 02:47:58.992507 ddr clk to 1584MHz
703 02:47:58.999535 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 02:47:59.036758
705 02:47:59.037256 dmc_version 0001
706 02:47:59.043457 Check phy result
707 02:47:59.049363 INFO : End of CA training
708 02:47:59.049847 INFO : End of initialization
709 02:47:59.054905 INFO : Training has run successfully!
710 02:47:59.055383 Check phy result
711 02:47:59.060606 INFO : End of initialization
712 02:47:59.061075 INFO : End of read enable training
713 02:47:59.066115 INFO : End of fine write leveling
714 02:47:59.071859 INFO : End of Write leveling coarse delay
715 02:47:59.072360 INFO : Training has run successfully!
716 02:47:59.072774 Check phy result
717 02:47:59.077319 INFO : End of initialization
718 02:47:59.077790 INFO : End of read dq deskew training
719 02:47:59.082892 INFO : End of MPR read delay center optimization
720 02:47:59.088508 INFO : End of write delay center optimization
721 02:47:59.094110 INFO : End of read delay center optimization
722 02:47:59.094587 INFO : End of max read latency training
723 02:47:59.099875 INFO : Training has run successfully!
724 02:47:59.100390 1D training succeed
725 02:47:59.108861 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 02:47:59.156714 Check phy result
727 02:47:59.157229 INFO : End of initialization
728 02:47:59.179320 INFO : End of 2D read delay Voltage center optimization
729 02:47:59.199435 INFO : End of 2D read delay Voltage center optimization
730 02:47:59.251529 INFO : End of 2D write delay Voltage center optimization
731 02:47:59.300867 INFO : End of 2D write delay Voltage center optimization
732 02:47:59.306504 INFO : Training has run successfully!
733 02:47:59.306981
734 02:47:59.307395 channel==0
735 02:47:59.311957 RxClkDly_Margin_A0==88 ps 9
736 02:47:59.312462 TxDqDly_Margin_A0==98 ps 10
737 02:47:59.317695 RxClkDly_Margin_A1==88 ps 9
738 02:47:59.318165 TxDqDly_Margin_A1==98 ps 10
739 02:47:59.318579 TrainedVREFDQ_A0==74
740 02:47:59.323180 TrainedVREFDQ_A1==75
741 02:47:59.323650 VrefDac_Margin_A0==24
742 02:47:59.324120 DeviceVref_Margin_A0==40
743 02:47:59.328770 VrefDac_Margin_A1==24
744 02:47:59.329253 DeviceVref_Margin_A1==39
745 02:47:59.329663
746 02:47:59.330064
747 02:47:59.334291 channel==1
748 02:47:59.334765 RxClkDly_Margin_A0==98 ps 10
749 02:47:59.335175 TxDqDly_Margin_A0==98 ps 10
750 02:47:59.339942 RxClkDly_Margin_A1==88 ps 9
751 02:47:59.340427 TxDqDly_Margin_A1==88 ps 9
752 02:47:59.345655 TrainedVREFDQ_A0==77
753 02:47:59.346112 TrainedVREFDQ_A1==77
754 02:47:59.346519 VrefDac_Margin_A0==22
755 02:47:59.351114 DeviceVref_Margin_A0==37
756 02:47:59.351568 VrefDac_Margin_A1==24
757 02:47:59.356746 DeviceVref_Margin_A1==37
758 02:47:59.357205
759 02:47:59.357618 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 02:47:59.358021
761 02:47:59.390320 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000018 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 02:47:59.390918 2D training succeed
763 02:47:59.396077 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 02:47:59.401558 auto size-- 65535DDR cs0 size: 2048MB
765 02:47:59.402022 DDR cs1 size: 2048MB
766 02:47:59.407132 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 02:47:59.407589 cs0 DataBus test pass
768 02:47:59.412749 cs1 DataBus test pass
769 02:47:59.413209 cs0 AddrBus test pass
770 02:47:59.413617 cs1 AddrBus test pass
771 02:47:59.414018
772 02:47:59.418339 100bdlr_step_size ps== 420
773 02:47:59.418805 result report
774 02:47:59.424013 boot times 0Enable ddr reg access
775 02:47:59.429294 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 02:47:59.442726 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 02:48:00.015956 0.0;M3 CHK:0;cm4_sp_mode 0
778 02:48:00.016607 MVN_1=0x00000000
779 02:48:00.021461 MVN_2=0x00000000
780 02:48:00.027077 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 02:48:00.027581 OPS=0x10
782 02:48:00.028015 ring efuse init
783 02:48:00.028417 chipver efuse init
784 02:48:00.035510 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 02:48:00.036014 [0.018960 Inits done]
786 02:48:00.036416 secure task start!
787 02:48:00.042933 high task start!
788 02:48:00.043387 low task start!
789 02:48:00.043777 run into bl31
790 02:48:00.049614 NOTICE: BL31: v1.3(release):4fc40b1
791 02:48:00.057299 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 02:48:00.057761 NOTICE: BL31: G12A normal boot!
793 02:48:00.082641 NOTICE: BL31: BL33 decompress pass
794 02:48:00.088348 ERROR: Error initializing runtime service opteed_fast
795 02:48:01.321469
796 02:48:01.322101
797 02:48:01.329732 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 02:48:01.330222
799 02:48:01.330643 Model: Libre Computer AML-A311D-CC Alta
800 02:48:01.538112 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 02:48:01.561732 DRAM: 2 GiB (effective 3.8 GiB)
802 02:48:01.704577 Core: 408 devices, 31 uclasses, devicetree: separate
803 02:48:01.710445 WDT: Not starting watchdog@f0d0
804 02:48:01.742752 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 02:48:01.755066 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 02:48:01.760233 ** Bad device specification mmc 0 **
807 02:48:01.770524 Card did not respond to voltage select! : -110
808 02:48:01.778250 ** Bad device specification mmc 0 **
809 02:48:01.778806 Couldn't find partition mmc 0
810 02:48:01.786513 Card did not respond to voltage select! : -110
811 02:48:01.792127 ** Bad device specification mmc 0 **
812 02:48:01.792702 Couldn't find partition mmc 0
813 02:48:01.797172 Error: could not access storage.
814 02:48:02.139527 Net: eth0: ethernet@ff3f0000
815 02:48:02.140177 starting USB...
816 02:48:02.391283 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 02:48:02.391902 Starting the controller
818 02:48:02.398394 USB XHCI 1.10
819 02:48:04.559082 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 02:48:04.560023 bl2_stage_init 0x01
821 02:48:04.560721 bl2_stage_init 0x81
822 02:48:04.564767 hw id: 0x0000 - pwm id 0x01
823 02:48:04.565483 bl2_stage_init 0xc1
824 02:48:04.566124 bl2_stage_init 0x02
825 02:48:04.566711
826 02:48:04.570249 L0:00000000
827 02:48:04.570752 L1:20000703
828 02:48:04.571203 L2:00008067
829 02:48:04.571654 L3:14000000
830 02:48:04.575806 B2:00402000
831 02:48:04.576344 B1:e0f83180
832 02:48:04.576793
833 02:48:04.577248 TE: 58159
834 02:48:04.577689
835 02:48:04.581368 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 02:48:04.581885
837 02:48:04.582334 Board ID = 1
838 02:48:04.586960 Set A53 clk to 24M
839 02:48:04.587482 Set A73 clk to 24M
840 02:48:04.587925 Set clk81 to 24M
841 02:48:04.592601 A53 clk: 1200 MHz
842 02:48:04.593333 A73 clk: 1200 MHz
843 02:48:04.593993 CLK81: 166.6M
844 02:48:04.594573 smccc: 00012ab5
845 02:48:04.598271 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 02:48:04.603964 board id: 1
847 02:48:04.609888 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 02:48:04.620204 fw parse done
849 02:48:04.626226 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 02:48:04.668930 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 02:48:04.679811 PIEI prepare done
852 02:48:04.680592 fastboot data load
853 02:48:04.681244 fastboot data verify
854 02:48:04.685406 verify result: 266
855 02:48:04.691008 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 02:48:04.691723 LPDDR4 probe
857 02:48:04.692341 ddr clk to 1584MHz
858 02:48:04.698986 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 02:48:04.736369
860 02:48:04.736975 dmc_version 0001
861 02:48:04.742949 Check phy result
862 02:48:04.748743 INFO : End of CA training
863 02:48:04.749229 INFO : End of initialization
864 02:48:04.754382 INFO : Training has run successfully!
865 02:48:04.754872 Check phy result
866 02:48:04.759920 INFO : End of initialization
867 02:48:04.760485 INFO : End of read enable training
868 02:48:04.763236 INFO : End of fine write leveling
869 02:48:04.768786 INFO : End of Write leveling coarse delay
870 02:48:04.774391 INFO : Training has run successfully!
871 02:48:04.774870 Check phy result
872 02:48:04.775315 INFO : End of initialization
873 02:48:04.779964 INFO : End of read dq deskew training
874 02:48:04.785626 INFO : End of MPR read delay center optimization
875 02:48:04.786108 INFO : End of write delay center optimization
876 02:48:04.791218 INFO : End of read delay center optimization
877 02:48:04.796796 INFO : End of max read latency training
878 02:48:04.797285 INFO : Training has run successfully!
879 02:48:04.802412 1D training succeed
880 02:48:04.808361 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 02:48:04.855915 Check phy result
882 02:48:04.856434 INFO : End of initialization
883 02:48:04.878366 INFO : End of 2D read delay Voltage center optimization
884 02:48:04.898495 INFO : End of 2D read delay Voltage center optimization
885 02:48:04.950424 INFO : End of 2D write delay Voltage center optimization
886 02:48:04.999715 INFO : End of 2D write delay Voltage center optimization
887 02:48:05.005206 INFO : Training has run successfully!
888 02:48:05.005689
889 02:48:05.006131 channel==0
890 02:48:05.010798 RxClkDly_Margin_A0==88 ps 9
891 02:48:05.011278 TxDqDly_Margin_A0==98 ps 10
892 02:48:05.016451 RxClkDly_Margin_A1==88 ps 9
893 02:48:05.016925 TxDqDly_Margin_A1==88 ps 9
894 02:48:05.017363 TrainedVREFDQ_A0==74
895 02:48:05.022704 TrainedVREFDQ_A1==74
896 02:48:05.023176 VrefDac_Margin_A0==24
897 02:48:05.023604 DeviceVref_Margin_A0==40
898 02:48:05.027702 VrefDac_Margin_A1==24
899 02:48:05.028194 DeviceVref_Margin_A1==40
900 02:48:05.028629
901 02:48:05.029060
902 02:48:05.029485 channel==1
903 02:48:05.033188 RxClkDly_Margin_A0==98 ps 10
904 02:48:05.033670 TxDqDly_Margin_A0==98 ps 10
905 02:48:05.038722 RxClkDly_Margin_A1==88 ps 9
906 02:48:05.039193 TxDqDly_Margin_A1==88 ps 9
907 02:48:05.044376 TrainedVREFDQ_A0==77
908 02:48:05.044861 TrainedVREFDQ_A1==77
909 02:48:05.045292 VrefDac_Margin_A0==22
910 02:48:05.049962 DeviceVref_Margin_A0==37
911 02:48:05.050426 VrefDac_Margin_A1==24
912 02:48:05.055622 DeviceVref_Margin_A1==37
913 02:48:05.056134
914 02:48:05.056574 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 02:48:05.057003
916 02:48:05.089056 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 02:48:05.089578 2D training succeed
918 02:48:05.094666 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 02:48:05.100270 auto size-- 65535DDR cs0 size: 2048MB
920 02:48:05.100741 DDR cs1 size: 2048MB
921 02:48:05.105878 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 02:48:05.106347 cs0 DataBus test pass
923 02:48:05.111617 cs1 DataBus test pass
924 02:48:05.112127 cs0 AddrBus test pass
925 02:48:05.112562 cs1 AddrBus test pass
926 02:48:05.112984
927 02:48:05.117060 100bdlr_step_size ps== 420
928 02:48:05.117541 result report
929 02:48:05.122681 boot times 0Enable ddr reg access
930 02:48:05.127939 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 02:48:05.141447 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 02:48:05.713409 0.0;M3 CHK:0;cm4_sp_mode 0
933 02:48:05.714031 MVN_1=0x00000000
934 02:48:05.718853 MVN_2=0x00000000
935 02:48:05.724599 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 02:48:05.725078 OPS=0x10
937 02:48:05.725518 ring efuse init
938 02:48:05.725950 chipver efuse init
939 02:48:05.730190 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 02:48:05.735788 [0.018961 Inits done]
941 02:48:05.736332 secure task start!
942 02:48:05.736772 high task start!
943 02:48:05.740417 low task start!
944 02:48:05.740894 run into bl31
945 02:48:05.747015 NOTICE: BL31: v1.3(release):4fc40b1
946 02:48:05.754841 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 02:48:05.755325 NOTICE: BL31: G12A normal boot!
948 02:48:05.780182 NOTICE: BL31: BL33 decompress pass
949 02:48:05.785838 ERROR: Error initializing runtime service opteed_fast
950 02:48:07.018957
951 02:48:07.019578
952 02:48:07.027144 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 02:48:07.027646
954 02:48:07.028132 Model: Libre Computer AML-A311D-CC Alta
955 02:48:07.235641 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 02:48:07.258988 DRAM: 2 GiB (effective 3.8 GiB)
957 02:48:07.401952 Core: 408 devices, 31 uclasses, devicetree: separate
958 02:48:07.407878 WDT: Not starting watchdog@f0d0
959 02:48:07.440122 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 02:48:07.452565 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 02:48:07.457507 ** Bad device specification mmc 0 **
962 02:48:07.467904 Card did not respond to voltage select! : -110
963 02:48:07.475502 ** Bad device specification mmc 0 **
964 02:48:07.476044 Couldn't find partition mmc 0
965 02:48:07.483874 Card did not respond to voltage select! : -110
966 02:48:07.489333 ** Bad device specification mmc 0 **
967 02:48:07.489819 Couldn't find partition mmc 0
968 02:48:07.494401 Error: could not access storage.
969 02:48:07.836991 Net: eth0: ethernet@ff3f0000
970 02:48:07.837536 starting USB...
971 02:48:08.088816 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 02:48:08.089442 Starting the controller
973 02:48:08.095583 USB XHCI 1.10
974 02:48:09.958380 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 02:48:09.959009 bl2_stage_init 0x01
976 02:48:09.959440 bl2_stage_init 0x81
977 02:48:09.964043 hw id: 0x0000 - pwm id 0x01
978 02:48:09.964532 bl2_stage_init 0xc1
979 02:48:09.964955 bl2_stage_init 0x02
980 02:48:09.965367
981 02:48:09.969605 L0:00000000
982 02:48:09.970080 L1:20000703
983 02:48:09.970496 L2:00008067
984 02:48:09.970902 L3:14000000
985 02:48:09.975238 B2:00402000
986 02:48:09.975712 B1:e0f83180
987 02:48:09.976155
988 02:48:09.976572 TE: 58159
989 02:48:09.976980
990 02:48:09.980780 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 02:48:09.981251
992 02:48:09.981664 Board ID = 1
993 02:48:09.986372 Set A53 clk to 24M
994 02:48:09.986834 Set A73 clk to 24M
995 02:48:09.987243 Set clk81 to 24M
996 02:48:09.991976 A53 clk: 1200 MHz
997 02:48:09.992464 A73 clk: 1200 MHz
998 02:48:09.992877 CLK81: 166.6M
999 02:48:09.993279 smccc: 00012ab5
1000 02:48:09.997613 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 02:48:10.003231 board id: 1
1002 02:48:10.009058 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 02:48:10.019739 fw parse done
1004 02:48:10.025745 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 02:48:10.068343 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 02:48:10.079238 PIEI prepare done
1007 02:48:10.079699 fastboot data load
1008 02:48:10.080126 fastboot data verify
1009 02:48:10.084933 verify result: 266
1010 02:48:10.090507 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 02:48:10.090974 LPDDR4 probe
1012 02:48:10.091366 ddr clk to 1584MHz
1013 02:48:10.098476 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 02:48:10.135736
1015 02:48:10.136246 dmc_version 0001
1016 02:48:10.142415 Check phy result
1017 02:48:10.148350 INFO : End of CA training
1018 02:48:10.148803 INFO : End of initialization
1019 02:48:10.153933 INFO : Training has run successfully!
1020 02:48:10.154430 Check phy result
1021 02:48:10.159684 INFO : End of initialization
1022 02:48:10.160189 INFO : End of read enable training
1023 02:48:10.165247 INFO : End of fine write leveling
1024 02:48:10.170824 INFO : End of Write leveling coarse delay
1025 02:48:10.171292 INFO : Training has run successfully!
1026 02:48:10.171703 Check phy result
1027 02:48:10.176496 INFO : End of initialization
1028 02:48:10.176968 INFO : End of read dq deskew training
1029 02:48:10.182039 INFO : End of MPR read delay center optimization
1030 02:48:10.187637 INFO : End of write delay center optimization
1031 02:48:10.193234 INFO : End of read delay center optimization
1032 02:48:10.193699 INFO : End of max read latency training
1033 02:48:10.198858 INFO : Training has run successfully!
1034 02:48:10.199325 1D training succeed
1035 02:48:10.208002 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 02:48:10.255748 Check phy result
1037 02:48:10.256279 INFO : End of initialization
1038 02:48:10.277142 INFO : End of 2D read delay Voltage center optimization
1039 02:48:10.297249 INFO : End of 2D read delay Voltage center optimization
1040 02:48:10.349172 INFO : End of 2D write delay Voltage center optimization
1041 02:48:10.398505 INFO : End of 2D write delay Voltage center optimization
1042 02:48:10.403947 INFO : Training has run successfully!
1043 02:48:10.404467
1044 02:48:10.404928 channel==0
1045 02:48:10.409661 RxClkDly_Margin_A0==88 ps 9
1046 02:48:10.410147 TxDqDly_Margin_A0==98 ps 10
1047 02:48:10.415162 RxClkDly_Margin_A1==88 ps 9
1048 02:48:10.415644 TxDqDly_Margin_A1==98 ps 10
1049 02:48:10.416096 TrainedVREFDQ_A0==74
1050 02:48:10.420769 TrainedVREFDQ_A1==74
1051 02:48:10.421275 VrefDac_Margin_A0==25
1052 02:48:10.421695 DeviceVref_Margin_A0==40
1053 02:48:10.426474 VrefDac_Margin_A1==25
1054 02:48:10.426949 DeviceVref_Margin_A1==40
1055 02:48:10.427363
1056 02:48:10.427769
1057 02:48:10.431959 channel==1
1058 02:48:10.432463 RxClkDly_Margin_A0==98 ps 10
1059 02:48:10.432878 TxDqDly_Margin_A0==98 ps 10
1060 02:48:10.437610 RxClkDly_Margin_A1==88 ps 9
1061 02:48:10.438090 TxDqDly_Margin_A1==88 ps 9
1062 02:48:10.443251 TrainedVREFDQ_A0==77
1063 02:48:10.443759 TrainedVREFDQ_A1==77
1064 02:48:10.444214 VrefDac_Margin_A0==22
1065 02:48:10.448778 DeviceVref_Margin_A0==37
1066 02:48:10.449257 VrefDac_Margin_A1==24
1067 02:48:10.454485 DeviceVref_Margin_A1==37
1068 02:48:10.454954
1069 02:48:10.455367 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 02:48:10.455770
1071 02:48:10.487817 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000018 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
1072 02:48:10.488374 2D training succeed
1073 02:48:10.493512 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 02:48:10.499148 auto size-- 65535DDR cs0 size: 2048MB
1075 02:48:10.499622 DDR cs1 size: 2048MB
1076 02:48:10.504712 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 02:48:10.505182 cs0 DataBus test pass
1078 02:48:10.510408 cs1 DataBus test pass
1079 02:48:10.510876 cs0 AddrBus test pass
1080 02:48:10.511282 cs1 AddrBus test pass
1081 02:48:10.511682
1082 02:48:10.515914 100bdlr_step_size ps== 420
1083 02:48:10.516421 result report
1084 02:48:10.521509 boot times 0Enable ddr reg access
1085 02:48:10.526859 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 02:48:10.540275 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 02:48:11.112343 0.0;M3 CHK:0;cm4_sp_mode 0
1088 02:48:11.112983 MVN_1=0x00000000
1089 02:48:11.117783 MVN_2=0x00000000
1090 02:48:11.123530 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 02:48:11.124042 OPS=0x10
1092 02:48:11.124470 ring efuse init
1093 02:48:11.124882 chipver efuse init
1094 02:48:11.129145 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 02:48:11.134720 [0.018961 Inits done]
1096 02:48:11.135186 secure task start!
1097 02:48:11.135600 high task start!
1098 02:48:11.139316 low task start!
1099 02:48:11.139835 run into bl31
1100 02:48:11.145912 NOTICE: BL31: v1.3(release):4fc40b1
1101 02:48:11.153706 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 02:48:11.154172 NOTICE: BL31: G12A normal boot!
1103 02:48:11.179074 NOTICE: BL31: BL33 decompress pass
1104 02:48:11.184730 ERROR: Error initializing runtime service opteed_fast
1105 02:48:12.417719
1106 02:48:12.418340
1107 02:48:12.426084 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 02:48:12.426606
1109 02:48:12.427044 Model: Libre Computer AML-A311D-CC Alta
1110 02:48:12.634996 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 02:48:12.657844 DRAM: 2 GiB (effective 3.8 GiB)
1112 02:48:12.800820 Core: 408 devices, 31 uclasses, devicetree: separate
1113 02:48:12.806714 WDT: Not starting watchdog@f0d0
1114 02:48:12.838968 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 02:48:12.851393 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 02:48:12.856459 ** Bad device specification mmc 0 **
1117 02:48:12.866721 Card did not respond to voltage select! : -110
1118 02:48:12.874380 ** Bad device specification mmc 0 **
1119 02:48:12.874886 Couldn't find partition mmc 0
1120 02:48:12.882690 Card did not respond to voltage select! : -110
1121 02:48:12.888221 ** Bad device specification mmc 0 **
1122 02:48:12.888728 Couldn't find partition mmc 0
1123 02:48:12.893300 Error: could not access storage.
1124 02:48:13.236790 Net: eth0: ethernet@ff3f0000
1125 02:48:13.237208 starting USB...
1126 02:48:13.488573 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 02:48:13.489141 Starting the controller
1128 02:48:13.495581 USB XHCI 1.10
1129 02:48:15.052193 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 02:48:15.060369 scanning usb for storage devices... 0 Storage Device(s) found
1132 02:48:15.111945 Hit any key to stop autoboot: 1
1133 02:48:15.112767 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 02:48:15.113412 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1135 02:48:15.113875 Setting prompt string to ['=>']
1136 02:48:15.114344 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1137 02:48:15.127768 0
1138 02:48:15.128721 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 02:48:15.129213 Sending with 10 millisecond of delay
1141 02:48:16.263915 => setenv autoload no
1142 02:48:16.274722 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 02:48:16.279607 setenv autoload no
1144 02:48:16.280381 Sending with 10 millisecond of delay
1146 02:48:18.076790 => setenv initrd_high 0xffffffff
1147 02:48:18.087565 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1148 02:48:18.088471 setenv initrd_high 0xffffffff
1149 02:48:18.089194 Sending with 10 millisecond of delay
1151 02:48:19.705123 => setenv fdt_high 0xffffffff
1152 02:48:19.715914 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 02:48:19.716783 setenv fdt_high 0xffffffff
1154 02:48:19.717499 Sending with 10 millisecond of delay
1156 02:48:20.009291 => dhcp
1157 02:48:20.020068 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 02:48:20.020894 dhcp
1159 02:48:20.021337 Speed: 1000, full duplex
1160 02:48:20.021755 BOOTP broadcast 1
1161 02:48:20.218541 DHCP client bound to address 192.168.6.27 (198 ms)
1162 02:48:20.219321 Sending with 10 millisecond of delay
1164 02:48:21.895469 => setenv serverip 192.168.6.2
1165 02:48:21.906257 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 02:48:21.907091 setenv serverip 192.168.6.2
1167 02:48:21.907803 Sending with 10 millisecond of delay
1169 02:48:25.630693 => tftpboot 0x01080000 943521/tftp-deploy-ss4p34vt/kernel/uImage
1170 02:48:25.642251 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 02:48:25.643207 tftpboot 0x01080000 943521/tftp-deploy-ss4p34vt/kernel/uImage
1172 02:48:25.643646 Speed: 1000, full duplex
1173 02:48:25.644101 Using ethernet@ff3f0000 device
1174 02:48:25.644896 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 02:48:25.650580 Filename '943521/tftp-deploy-ss4p34vt/kernel/uImage'.
1176 02:48:25.654356 Load address: 0x1080000
1177 02:48:28.442168 Loading: *################################################## 43.7 MiB
1178 02:48:28.442760 15.6 MiB/s
1179 02:48:28.443200 done
1180 02:48:28.446611 Bytes transferred = 45779520 (2ba8a40 hex)
1181 02:48:28.447345 Sending with 10 millisecond of delay
1183 02:48:33.134481 => tftpboot 0x08000000 943521/tftp-deploy-ss4p34vt/ramdisk/ramdisk.cpio.gz.uboot
1184 02:48:33.145342 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 02:48:33.146377 tftpboot 0x08000000 943521/tftp-deploy-ss4p34vt/ramdisk/ramdisk.cpio.gz.uboot
1186 02:48:33.146829 Speed: 1000, full duplex
1187 02:48:33.147237 Using ethernet@ff3f0000 device
1188 02:48:33.148224 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 02:48:33.156906 Filename '943521/tftp-deploy-ss4p34vt/ramdisk/ramdisk.cpio.gz.uboot'.
1190 02:48:33.157399 Load address: 0x8000000
1191 02:48:35.403841 Loading: *######################## UDP wrong checksum 000000ff 0000ba4e
1192 02:48:35.445401 UDP wrong checksum 000000ff 00005641
1193 02:48:40.218646 T ########################## 22.3 MiB
1194 02:48:40.219284 3.2 MiB/s
1195 02:48:40.219719 done
1196 02:48:40.223007 Bytes transferred = 23427542 (16579d6 hex)
1197 02:48:40.223820 Sending with 10 millisecond of delay
1199 02:48:45.391107 => tftpboot 0x01070000 943521/tftp-deploy-ss4p34vt/dtb/meson-g12b-a311d-libretech-cc.dtb
1200 02:48:45.401851 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:52)
1201 02:48:45.402594 tftpboot 0x01070000 943521/tftp-deploy-ss4p34vt/dtb/meson-g12b-a311d-libretech-cc.dtb
1202 02:48:45.403032 Speed: 1000, full duplex
1203 02:48:45.403427 Using ethernet@ff3f0000 device
1204 02:48:45.406822 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1205 02:48:45.418878 Filename '943521/tftp-deploy-ss4p34vt/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1206 02:48:45.419358 Load address: 0x1070000
1207 02:48:45.434900 Loading: *################################################## 53.4 KiB
1208 02:48:45.435328 3.1 MiB/s
1209 02:48:45.435721 done
1210 02:48:45.441269 Bytes transferred = 54703 (d5af hex)
1211 02:48:45.441953 Sending with 10 millisecond of delay
1213 02:48:58.735670 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943521/extract-nfsrootfs-7e1yg237,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1214 02:48:58.747493 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:39)
1215 02:48:58.748239 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943521/extract-nfsrootfs-7e1yg237,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1216 02:48:58.748807 Sending with 10 millisecond of delay
1218 02:49:01.088879 => bootm 0x01080000 0x08000000 0x01070000
1219 02:49:01.099842 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1220 02:49:01.100270 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:36)
1221 02:49:01.100867 bootm 0x01080000 0x08000000 0x01070000
1222 02:49:01.101134 ## Booting kernel from Legacy Image at 01080000 ...
1223 02:49:01.104519 Image Name:
1224 02:49:01.110000 Image Type: AArch64 Linux Kernel Image (uncompressed)
1225 02:49:01.110430 Data Size: 45779456 Bytes = 43.7 MiB
1226 02:49:01.112184 Load Address: 01080000
1227 02:49:01.118899 Entry Point: 01080000
1228 02:49:01.311093 Verifying Checksum ... OK
1229 02:49:01.311516 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1230 02:49:01.316517 Image Name:
1231 02:49:01.322046 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1232 02:49:01.322496 Data Size: 23427478 Bytes = 22.3 MiB
1233 02:49:01.324397 Load Address: 00000000
1234 02:49:01.331580 Entry Point: 00000000
1235 02:49:01.429747 Verifying Checksum ... OK
1236 02:49:01.430318 ## Flattened Device Tree blob at 01070000
1237 02:49:01.435157 Booting using the fdt blob at 0x1070000
1238 02:49:01.435462 Working FDT set to 1070000
1239 02:49:01.439674 Loading Kernel Image
1240 02:49:01.591244 Loading Ramdisk to 7e9a8000, end 7ffff996 ... OK
1241 02:49:01.599434 Loading Device Tree to 000000007e997000, end 000000007e9a75ae ... OK
1242 02:49:01.599760 Working FDT set to 7e997000
1243 02:49:01.600029
1244 02:49:01.600995 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1245 02:49:01.601660 start: 2.4.4 auto-login-action (timeout 00:03:36) [common]
1246 02:49:01.602155 Setting prompt string to ['Linux version [0-9]']
1247 02:49:01.602639 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1248 02:49:01.603215 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1249 02:49:01.604360 Starting kernel ...
1250 02:49:01.604853
1251 02:49:01.639958 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1252 02:49:01.641069 start: 2.4.4.1 login-action (timeout 00:03:36) [common]
1253 02:49:01.641637 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1254 02:49:01.642141 Setting prompt string to []
1255 02:49:01.642659 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1256 02:49:01.643144 Using line separator: #'\n'#
1257 02:49:01.643585 No login prompt set.
1258 02:49:01.644087 Parsing kernel messages
1259 02:49:01.644521 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1260 02:49:01.645389 [login-action] Waiting for messages, (timeout 00:03:36)
1261 02:49:01.645917 Waiting using forced prompt support (timeout 00:01:48)
1262 02:49:01.656510 [ 0.000000] Linux version 6.12.0-rc1 (KernelCI@build-j364116-arm64-gcc-12-defconfig-xfvrw) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Nov 6 01:46:21 UTC 2024
1263 02:49:01.662063 [ 0.000000] KASLR disabled due to lack of seed
1264 02:49:01.667580 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1265 02:49:01.673007 [ 0.000000] efi: UEFI not found.
1266 02:49:01.678560 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1267 02:49:01.684065 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1268 02:49:01.695029 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1269 02:49:01.706079 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1270 02:49:01.711628 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1271 02:49:01.722618 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1272 02:49:01.733651 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1273 02:49:01.739258 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1274 02:49:01.744750 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1275 02:49:01.750410 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1276 02:49:01.750921 [ 0.000000] Zone ranges:
1277 02:49:01.755814 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1278 02:49:01.761353 [ 0.000000] DMA32 empty
1279 02:49:01.761866 [ 0.000000] Normal empty
1280 02:49:01.766846 [ 0.000000] Movable zone start for each node
1281 02:49:01.772334 [ 0.000000] Early memory node ranges
1282 02:49:01.777817 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1283 02:49:01.783355 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1284 02:49:01.788858 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1285 02:49:01.794371 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1286 02:49:01.821695 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1287 02:49:01.827341 [ 0.000000] psci: probing for conduit method from DT.
1288 02:49:01.827852 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1289 02:49:01.836290 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1290 02:49:01.836816 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1291 02:49:01.841847 [ 0.000000] psci: SMC Calling Convention v1.1
1292 02:49:01.847414 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1293 02:49:01.852857 [ 0.000000] Detected VIPT I-cache on CPU0
1294 02:49:01.858385 [ 0.000000] CPU features: detected: ARM erratum 845719
1295 02:49:01.863916 [ 0.000000] alternatives: applying boot alternatives
1296 02:49:01.885921 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943521/extract-nfsrootfs-7e1yg237,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1297 02:49:01.891516 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1298 02:49:01.902496 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1299 02:49:01.903028 <6>[ 0.000000] Fallback order for Node 0: 0
1300 02:49:01.913554 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1301 02:49:01.914112 <6>[ 0.000000] Policy zone: DMA
1302 02:49:01.919103 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1303 02:49:01.930196 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1304 02:49:01.930756 <6>[ 0.000000] software IO TLB: area num 8.
1305 02:49:01.941129 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1306 02:49:01.987617 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1307 02:49:01.993229 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1308 02:49:01.998676 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1309 02:49:02.004261 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1310 02:49:02.009749 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1311 02:49:02.015385 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1312 02:49:02.020757 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1313 02:49:02.026373 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1314 02:49:02.037339 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1315 02:49:02.048330 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1316 02:49:02.053904 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1317 02:49:02.059427 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1318 02:49:02.059953 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1319 02:49:02.069245 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1320 02:49:02.082040 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1321 02:49:02.093030 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1322 02:49:02.098560 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1323 02:49:02.104114 <6>[ 0.008795] Console: colour dummy device 80x25
1324 02:49:02.115149 <6>[ 0.012939] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1325 02:49:02.120680 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1326 02:49:02.126158 <6>[ 0.028190] LSM: initializing lsm=capability
1327 02:49:02.131686 <6>[ 0.032732] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1328 02:49:02.137308 <6>[ 0.040212] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1329 02:49:02.142743 <6>[ 0.050751] rcu: Hierarchical SRCU implementation.
1330 02:49:02.148318 <6>[ 0.053267] rcu: Max phase no-delay instances is 1000.
1331 02:49:02.159285 <6>[ 0.058871] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1332 02:49:02.167748 <6>[ 0.071594] EFI services will not be available.
1333 02:49:02.168278 <6>[ 0.075239] smp: Bringing up secondary CPUs ...
1334 02:49:02.184029 <6>[ 0.077136] Detected VIPT I-cache on CPU1
1335 02:49:02.189529 <6>[ 0.077255] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1336 02:49:02.195068 <6>[ 0.078594] CPU features: detected: Spectre-v2
1337 02:49:02.204110 <6>[ 0.078609] CPU features: detected: Spectre-v4
1338 02:49:02.204621 <6>[ 0.078614] CPU features: detected: Spectre-BHB
1339 02:49:02.209631 <6>[ 0.078619] CPU features: detected: ARM erratum 858921
1340 02:49:02.215172 <6>[ 0.078627] Detected VIPT I-cache on CPU2
1341 02:49:02.220714 <6>[ 0.078701] arch_timer: Enabling local workaround for ARM erratum 858921
1342 02:49:02.226164 <6>[ 0.078719] arch_timer: CPU2: Trapping CNTVCT access
1343 02:49:02.237311 <6>[ 0.078729] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1344 02:49:02.237827 <6>[ 0.079669] Detected VIPT I-cache on CPU3
1345 02:49:02.248302 <6>[ 0.079715] arch_timer: Enabling local workaround for ARM erratum 858921
1346 02:49:02.248806 <6>[ 0.079725] arch_timer: CPU3: Trapping CNTVCT access
1347 02:49:02.259292 <6>[ 0.079732] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1348 02:49:02.259787 <6>[ 0.087699] Detected VIPT I-cache on CPU4
1349 02:49:02.270360 <6>[ 0.087746] arch_timer: Enabling local workaround for ARM erratum 858921
1350 02:49:02.275845 <6>[ 0.087755] arch_timer: CPU4: Trapping CNTVCT access
1351 02:49:02.281371 <6>[ 0.087762] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1352 02:49:02.286893 <6>[ 0.095655] Detected VIPT I-cache on CPU5
1353 02:49:02.292425 <6>[ 0.095702] arch_timer: Enabling local workaround for ARM erratum 858921
1354 02:49:02.297940 <6>[ 0.095712] arch_timer: CPU5: Trapping CNTVCT access
1355 02:49:02.303467 <6>[ 0.095719] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1356 02:49:02.308989 <6>[ 0.095839] smp: Brought up 1 node, 6 CPUs
1357 02:49:02.314502 <6>[ 0.217069] SMP: Total of 6 processors activated.
1358 02:49:02.314980 <6>[ 0.221973] CPU: All CPU(s) started at EL2
1359 02:49:02.320035 <6>[ 0.226316] CPU features: detected: 32-bit EL0 Support
1360 02:49:02.325542 <6>[ 0.231633] CPU features: detected: 32-bit EL1 Support
1361 02:49:02.331070 <6>[ 0.236979] CPU features: detected: CRC32 instructions
1362 02:49:02.336560 <6>[ 0.242380] alternatives: applying system-wide alternatives
1363 02:49:02.353320 <6>[ 0.249567] Memory: 3557376K/4012396K available (17280K kernel code, 4898K rwdata, 11896K rodata, 10496K init, 742K bss, 187856K reserved, 262144K cma-reserved)
1364 02:49:02.360104 <6>[ 0.263908] devtmpfs: initialized
1365 02:49:02.371041 <6>[ 0.273076] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1366 02:49:02.376545 <6>[ 0.277430] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1367 02:49:02.382142 <6>[ 0.288222] 21376 pages in range for non-PLT usage
1368 02:49:02.387579 <6>[ 0.288232] 512896 pages in range for PLT usage
1369 02:49:02.393207 <6>[ 0.289785] pinctrl core: initialized pinctrl subsystem
1370 02:49:02.393694 <6>[ 0.301869] DMI not present or invalid.
1371 02:49:02.398655 <6>[ 0.306152] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1372 02:49:02.409684 <6>[ 0.310895] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1373 02:49:02.415306 <6>[ 0.317666] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1374 02:49:02.426276 <6>[ 0.325767] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1375 02:49:02.431741 <6>[ 0.333262] audit: initializing netlink subsys (disabled)
1376 02:49:02.437312 <5>[ 0.338993] audit: type=2000 audit(0.260:1): state=initialized audit_enabled=0 res=1
1377 02:49:02.442802 <6>[ 0.340408] thermal_sys: Registered thermal governor 'step_wise'
1378 02:49:02.448361 <6>[ 0.346768] thermal_sys: Registered thermal governor 'power_allocator'
1379 02:49:02.453825 <6>[ 0.353029] cpuidle: using governor menu
1380 02:49:02.459348 <6>[ 0.364070] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1381 02:49:02.464871 <6>[ 0.370944] ASID allocator initialised with 65536 entries
1382 02:49:02.473115 <6>[ 0.378421] Serial: AMBA PL011 UART driver
1383 02:49:02.482908 <6>[ 0.389039] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1384 02:49:02.498179 <6>[ 0.404529] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1385 02:49:02.507339 <6>[ 0.407191] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1386 02:49:02.512856 <6>[ 0.420348] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1387 02:49:02.523894 <6>[ 0.423573] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1388 02:49:02.532960 <6>[ 0.431993] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1389 02:49:02.538475 <6>[ 0.439619] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1390 02:49:02.544005 <6>[ 0.453216] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1391 02:49:02.555011 <6>[ 0.455441] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1392 02:49:02.560524 <6>[ 0.461921] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1393 02:49:02.566061 <6>[ 0.468900] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1394 02:49:02.571584 <6>[ 0.475368] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1395 02:49:02.577096 <6>[ 0.482353] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1396 02:49:02.588217 <6>[ 0.488823] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1397 02:49:02.593642 <6>[ 0.495808] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1398 02:49:02.599185 <6>[ 0.503833] ACPI: Interpreter disabled.
1399 02:49:02.604717 <6>[ 0.509313] iommu: Default domain type: Translated
1400 02:49:02.610325 <6>[ 0.511341] iommu: DMA domain TLB invalidation policy: strict mode
1401 02:49:02.610834 <5>[ 0.518086] SCSI subsystem initialized
1402 02:49:02.615746 <6>[ 0.521966] usbcore: registered new interface driver usbfs
1403 02:49:02.621337 <6>[ 0.527402] usbcore: registered new interface driver hub
1404 02:49:02.626775 <6>[ 0.532915] usbcore: registered new device driver usb
1405 02:49:02.632319 <6>[ 0.539181] pps_core: LinuxPPS API ver. 1 registered
1406 02:49:02.643327 <6>[ 0.543336] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1407 02:49:02.648861 <6>[ 0.552655] PTP clock support registered
1408 02:49:02.649357 <6>[ 0.556898] EDAC MC: Ver: 3.0.0
1409 02:49:02.654380 <6>[ 0.560558] scmi_core: SCMI protocol bus registered
1410 02:49:02.659904 <6>[ 0.566156] FPGA manager framework
1411 02:49:02.665427 <6>[ 0.568917] Advanced Linux Sound Architecture Driver Initialized.
1412 02:49:02.670936 <6>[ 0.575873] vgaarb: loaded
1413 02:49:02.676461 <6>[ 0.578407] clocksource: Switched to clocksource arch_sys_counter
1414 02:49:02.682056 <5>[ 0.584560] VFS: Disk quotas dquot_6.6.0
1415 02:49:02.687523 <6>[ 0.588550] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1416 02:49:02.688069 <6>[ 0.595757] pnp: PnP ACPI: disabled
1417 02:49:02.693039 <6>[ 0.604187] NET: Registered PF_INET protocol family
1418 02:49:02.704090 <6>[ 0.604578] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1419 02:49:02.709612 <6>[ 0.614737] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1420 02:49:02.720617 <6>[ 0.620751] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1421 02:49:02.726231 <6>[ 0.628648] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1422 02:49:02.737230 <6>[ 0.636886] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1423 02:49:02.742691 <6>[ 0.644679] TCP: Hash tables configured (established 32768 bind 32768)
1424 02:49:02.748211 <6>[ 0.651156] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1425 02:49:02.753752 <6>[ 0.658004] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1426 02:49:02.764777 <6>[ 0.665429] NET: Registered PF_UNIX/PF_LOCAL protocol family
1427 02:49:02.770338 <6>[ 0.671518] RPC: Registered named UNIX socket transport module.
1428 02:49:02.775820 <6>[ 0.677293] RPC: Registered udp transport module.
1429 02:49:02.776354 <6>[ 0.682198] RPC: Registered tcp transport module.
1430 02:49:02.781407 <6>[ 0.687112] RPC: Registered tcp-with-tls transport module.
1431 02:49:02.792416 <6>[ 0.692805] RPC: Registered tcp NFSv4.1 backchannel transport module.
1432 02:49:02.792937 <6>[ 0.699454] PCI: CLS 0 bytes, default 64
1433 02:49:02.797923 <6>[ 0.703774] Unpacking initramfs...
1434 02:49:02.803434 <6>[ 0.709944] kvm [1]: nv: 554 coarse grained trap handlers
1435 02:49:02.808953 <6>[ 0.713131] kvm [1]: IPA Size Limit: 40 bits
1436 02:49:02.814480 <6>[ 0.718746] kvm [1]: vgic interrupt IRQ9
1437 02:49:02.820042 <6>[ 0.721465] kvm [1]: Hyp nVHE mode initialized successfully
1438 02:49:02.825495 <5>[ 0.728670] Initialise system trusted keyrings
1439 02:49:02.831022 <6>[ 0.732120] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1440 02:49:02.836545 <6>[ 0.738762] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1441 02:49:02.842063 <5>[ 0.744853] NFS: Registering the id_resolver key type
1442 02:49:02.847562 <5>[ 0.749850] Key type id_resolver registered
1443 02:49:02.848106 <5>[ 0.754218] Key type id_legacy registered
1444 02:49:02.858617 <6>[ 0.758455] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1445 02:49:02.864199 <6>[ 0.765344] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1446 02:49:02.869869 <6>[ 0.773150] 9p: Installing v9fs 9p2000 file system support
1447 02:49:02.908202 <5>[ 0.819915] Key type asymmetric registered
1448 02:49:02.913586 <5>[ 0.819958] Asymmetric key parser 'x509' registered
1449 02:49:02.924627 <6>[ 0.823833] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1450 02:49:02.925142 <6>[ 0.831346] io scheduler mq-deadline registered
1451 02:49:02.930162 <6>[ 0.836093] io scheduler kyber registered
1452 02:49:02.935657 <6>[ 0.840347] io scheduler bfq registered
1453 02:49:02.942092 <6>[ 0.848141] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1454 02:49:02.958515 <6>[ 0.866608] ledtrig-cpu: registered to indicate activity on CPUs
1455 02:49:02.991176 <6>[ 0.898062] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1456 02:49:03.010584 <6>[ 0.911234] Serial: 8250/16550 driver, 4 ports<6>[ 0.915802] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1457 02:49:03.016187 <6>[ 0.925446] printk: legacy console [ttyAML0] enabled
1458 02:49:03.021673 <6>[ 0.925446] printk: legacy console [ttyAML0] enabled
1459 02:49:03.027261 <6>[ 0.930243] printk: legacy bootconsole [meson0] disabled
1460 02:49:03.032766 <6>[ 0.930243] printk: legacy bootconsole [meson0] disabled
1461 02:49:03.038411 <6>[ 0.943166] msm_serial: driver initialized
1462 02:49:03.043865 <6>[ 0.946211] SuperH (H)SCI(F) driver initialized
1463 02:49:03.044417 <6>[ 0.950722] STM32 USART driver initialized
1464 02:49:03.049386 <5>[ 0.956885] random: crng init done
1465 02:49:03.056370 <6>[ 0.962390] loop: module loaded
1466 02:49:03.056895 <6>[ 0.963690] megasas: 07.727.03.00-rc1
1467 02:49:03.061918 <6>[ 0.972721] tun: Universal TUN/TAP device driver, 1.6
1468 02:49:03.067534 <6>[ 0.973927] thunder_xcv, ver 1.0
1469 02:49:03.073019 <6>[ 0.975923] thunder_bgx, ver 1.0
1470 02:49:03.073528 <6>[ 0.979360] nicpf, ver 1.0
1471 02:49:03.078542 <6>[ 0.983976] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1472 02:49:03.084205 <6>[ 0.989742] hns3: Copyright (c) 2017 Huawei Corporation.
1473 02:49:03.089654 <6>[ 0.995330] hclge is initializing
1474 02:49:03.095189 <6>[ 0.998869] e1000: Intel(R) PRO/1000 Network Driver
1475 02:49:03.100831 <6>[ 1.003949] e1000: Copyright (c) 1999-2006 Intel Corporation.
1476 02:49:03.106493 <6>[ 1.009972] e1000e: Intel(R) PRO/1000 Network Driver
1477 02:49:03.111859 <6>[ 1.015131] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1478 02:49:03.117426 <6>[ 1.021309] igb: Intel(R) Gigabit Ethernet Network Driver
1479 02:49:03.122944 <6>[ 1.026917] igb: Copyright (c) 2007-2014 Intel Corporation.
1480 02:49:03.128457 <6>[ 1.032750] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1481 02:49:03.134043 <6>[ 1.039223] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1482 02:49:03.139576 <6>[ 1.045988] sky2: driver version 1.30
1483 02:49:03.145134 <6>[ 1.051076] VFIO - User Level meta-driver version: 0.3
1484 02:49:03.150682 <6>[ 1.058603] usbcore: registered new interface driver usb-storage
1485 02:49:03.156695 <6>[ 1.064849] i2c_dev: i2c /dev entries driver
1486 02:49:03.169530 <6>[ 1.075817] sdhci: Secure Digital Host Controller Interface driver
1487 02:49:03.170072 <6>[ 1.076622] sdhci: Copyright(c) Pierre Ossman
1488 02:49:03.180609 <6>[ 1.082396] Synopsys Designware Multimedia Card Interface Driver
1489 02:49:03.186327 <6>[ 1.088884] sdhci-pltfm: SDHCI platform and OF driver helper
1490 02:49:03.186852 <6>[ 1.096534] meson-sm: secure-monitor enabled
1491 02:49:03.199061 <6>[ 1.099103] usbcore: registered new interface driver usbhid
1492 02:49:03.199613 <6>[ 1.103681] usbhid: USB HID core driver
1493 02:49:03.206650 <6>[ 1.118463] NET: Registered PF_PACKET protocol family
1494 02:49:03.212221 <6>[ 1.118554] 9pnet: Installing 9P2000 support
1495 02:49:03.219201 <5>[ 1.122712] Key type dns_resolver registered
1496 02:49:03.224761 <6>[ 1.134226] registered taskstats version 1
1497 02:49:03.230300 <5>[ 1.134373] Loading compiled-in X.509 certificates
1498 02:49:03.233895 <6>[ 1.143045] Demotion targets for Node 0: null
1499 02:49:03.273966 <6>[ 1.185769] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1500 02:49:03.279492 <6>[ 1.185813] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1501 02:49:03.290589 <4>[ 1.196040] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1502 02:49:03.296155 <4>[ 1.198589] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1503 02:49:03.301708 <6>[ 1.206149] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1504 02:49:03.307247 <6>[ 1.215397] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1505 02:49:03.318315 <6>[ 1.218847] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1506 02:49:03.329416 <6>[ 1.226833] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1507 02:49:03.334971 <6>[ 1.236365] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1508 02:49:03.340500 <6>[ 1.242588] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1509 02:49:03.346046 <6>[ 1.248218] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1510 02:49:03.351579 <6>[ 1.256098] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1511 02:49:03.357150 <6>[ 1.263325] hub 1-0:1.0: USB hub found
1512 02:49:03.362705 <6>[ 1.266874] hub 1-0:1.0: 2 ports detected
1513 02:49:03.368222 <6>[ 1.272922] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1514 02:49:03.373768 <6>[ 1.279811] hub 2-0:1.0: USB hub found
1515 02:49:03.378845 <6>[ 1.283422] hub 2-0:1.0: 1 port detected
1516 02:49:03.398938 <6>[ 1.308081] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1517 02:49:03.414394 <6>[ 1.322847] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1518 02:49:03.450033 <6>[ 1.358181] Trying to probe devices needed for running init ...
1519 02:49:03.614946 <6>[ 1.522439] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1520 02:49:03.751540 <6>[ 1.657721] mmc0: new ultra high speed SDR104 SDXC card at address e624
1521 02:49:03.757698 <6>[ 1.659874] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1522 02:49:03.758327 <6>[ 1.665767] mmcblk0: p1
1523 02:49:03.771421 <6>[ 1.681385] Freeing initrd memory: 22876K
1524 02:49:03.799480 <6>[ 1.711213] hub 1-1:1.0: USB hub found
1525 02:49:03.805154 <6>[ 1.711518] hub 1-1:1.0: 4 ports detected
1526 02:49:03.874992 <6>[ 1.782548] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1527 02:49:03.912127 <6>[ 1.823856] hub 2-1:1.0: USB hub found
1528 02:49:03.917796 <6>[ 1.824677] hub 2-1:1.0: 4 ports detected
1529 02:49:15.735064 <6>[ 13.646473] clk: Disabling unused clocks
1530 02:49:15.740371 <6>[ 13.646643] PM: genpd: Disabling unused power domains
1531 02:49:15.748655 <6>[ 13.650333] ALSA device list:
1532 02:49:15.749163 <6>[ 13.653538] No soundcards found.
1533 02:49:15.754248 <6>[ 13.665601] Freeing unused kernel memory: 10496K
1534 02:49:15.760189 <6>[ 13.665699] Run /init as init process
1535 02:49:15.765712 Loading, please wait...
1536 02:49:15.797834 Starting systemd-udevd version 252.22-1~deb12u1
1537 02:49:16.222862 <6>[ 14.132187] mc: Linux media interface: v0.10
1538 02:49:16.236137 <6>[ 14.142257] videodev: Linux video capture interface: v2.00
1539 02:49:16.241647 <6>[ 14.147957] panfrost ffe40000.gpu: clock rate = 24000000
1540 02:49:16.247538 <3>[ 14.148052] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1541 02:49:16.304517 <4>[ 14.210818] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1542 02:49:16.315664 <6>[ 14.215716] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1543 02:49:16.321326 <6>[ 14.218366] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1544 02:49:16.326771 <6>[ 14.223446] meson-vrtc ff8000a8.rtc: registered as rtc0
1545 02:49:16.332338 <6>[ 14.230861] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1546 02:49:16.343455 <6>[ 14.242468] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1547 02:49:16.354505 <6>[ 14.244193] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1548 02:49:16.360063 <6>[ 14.263570] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1549 02:49:16.365590 <6>[ 14.272870] Registered IR keymap rc-empty
1550 02:49:16.372543 <6>[ 14.274236] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1551 02:49:16.383785 <6>[ 14.289254] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1552 02:49:16.391538 <3>[ 14.289562] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1553 02:49:16.402565 <6>[ 14.308911] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1554 02:49:16.408236 <6>[ 14.309862] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1555 02:49:16.419237 <4>[ 14.311112] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1556 02:49:16.419725 <6>[ 14.311756] rc rc0: sw decoder init
1557 02:49:16.424748 <6>[ 14.311798] meson-ir ff808000.ir: receiver initialized
1558 02:49:16.430292 <6>[ 14.317658] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1559 02:49:16.441436 <6>[ 14.334762] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1560 02:49:16.446941 <6>[ 14.341841] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1561 02:49:16.454794 <6>[ 14.359870] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1562 02:49:16.466553 <6>[ 14.372923] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1563 02:49:16.472199 <6>[ 14.378587] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1564 02:49:16.477667 <6>[ 14.379149] usbcore: registered new device driver onboard-usb-dev
1565 02:49:16.483241 <6>[ 14.383103] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1566 02:49:16.494322 <6>[ 14.394587] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1567 02:49:16.499871 <6>[ 14.399938] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1568 02:49:16.510953 <6>[ 14.402267] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1569 02:49:16.516489 <3>[ 14.411992] meson-drm ff900000.vpu: DSI transceiver device is disabled
1570 02:49:16.522053 <6>[ 14.419162] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1571 02:49:16.527575 <6>[ 14.419169] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1572 02:49:16.538673 <6>[ 14.426412] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1573 02:49:16.549790 <6>[ 14.428152] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1574 02:49:16.555325 <6>[ 14.431377] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1575 02:49:16.560314 <6>[ 14.462996] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1576 02:49:16.735413 <6>[ 14.469079] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1577 02:49:16.740949 <6>[ 14.469083] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1578 02:49:16.746554 <6>[ 14.472500] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1579 02:49:16.752099 <6>[ 14.623196] Console: switching to colour frame buffer device 128x48
1580 02:49:16.762057 <6>[ 14.663478] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1581 02:49:16.983369 <6>[ 14.895202] hub 1-1:1.0: USB hub found
1582 02:49:16.989049 <6>[ 14.895529] hub 1-1:1.0: 4 ports detected
1583 02:49:17.132087 <4>[ 15.038430] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1584 02:49:17.137614 <3>[ 15.040789] onboard-usb-dev 1-1: Failed to suspend device, error -32
1585 02:49:17.144642 <3>[ 15.047223] onboard-usb-dev 1-1: can't set config #1, error -71
1586 02:49:17.164088 <4>[ 15.070421] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1587 02:49:17.169608 <3>[ 15.072813] onboard-usb-dev 1-1: Failed to suspend device, error -32
1588 02:49:17.175131 <6>[ 15.072820] onboard-usb-dev 1-1: USB disconnect, device number 2
1589 02:49:17.180685 Begin: Loading essential drivers ... done.
1590 02:49:17.186260 Begin: Running /scripts/init-premount ... done.
1591 02:49:17.191773 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1592 02:49:17.197306 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1593 02:49:17.203971 Device /sys/class/net/end0 found
1594 02:49:17.204463 done.
1595 02:49:17.217736 Begin: Waiting up to 180 secs for any network device to become available ... done.
1596 02:49:17.281653 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.184060] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1597 02:49:17.282139
1598 02:49:17.338779 <6>[ 15.242530] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=35)
1599 02:49:17.353310 <6>[ 15.259576] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1600 02:49:17.358763 <6>[ 15.261766] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1601 02:49:17.368068 <6>[ 15.269116] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1602 02:49:17.429313 <6>[ 15.334446] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1603 02:49:17.433571 <4>[ 15.342427] rc rc0: two consecutive events of type space
1604 02:49:17.623478 <6>[ 15.535310] hub 1-1:1.0: USB hub found
1605 02:49:17.629178 <6>[ 15.535788] hub 1-1:1.0: 4 ports detected
1606 02:49:17.755733 <6>[ 15.663159] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1607 02:49:18.011926 <6>[ 15.919350] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1608 02:49:18.832527 IP-Config: no response after 2 secs - giving up
1609 02:49:18.885779 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1610 02:49:20.318929 <6>[ 18.224515] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1611 02:49:21.101877 IP-Config: end0 guessed broadcast address 192.168.6.255
1612 02:49:21.107282 IP-Config: end0 complete (dhcp from 192.168.6.1):
1613 02:49:21.112922 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1614 02:49:21.121843 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1615 02:49:21.127348 rootserver: 192.168.6.1 rootpath:
1616 02:49:21.127861 filename :
1617 02:49:21.227370 done.
1618 02:49:21.237772 Begin: Running /scripts/nfs-bottom ... done.
1619 02:49:21.254269 Begin: Running /scripts/init-bottom ... done.
1620 02:49:21.589211 <30>[ 19.496423] systemd[1]: System time before build time, advancing clock.
1621 02:49:21.643573 <6>[ 19.555097] NET: Registered PF_INET6 protocol family
1622 02:49:21.648990 <6>[ 19.556204] Segment Routing with IPv6
1623 02:49:21.654228 <6>[ 19.558622] In-situ OAM (IOAM) with IPv6
1624 02:49:21.731255 <30>[ 19.611768] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1625 02:49:21.736813 <30>[ 19.639130] systemd[1]: Detected architecture arm64.
1626 02:49:21.737292
1627 02:49:21.740689 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1628 02:49:21.741153
1629 02:49:21.756188 <30>[ 19.664087] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1630 02:49:22.423433 <30>[ 20.330114] systemd[1]: Queued start job for default target graphical.target.
1631 02:49:22.466555 <30>[ 20.372792] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1632 02:49:22.475200 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1633 02:49:22.486698 <30>[ 20.391402] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1634 02:49:22.493603 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1635 02:49:22.505230 <30>[ 20.411440] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1636 02:49:22.514313 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1637 02:49:22.525293 <30>[ 20.431206] systemd[1]: Created slice user.slice - User and Session Slice.
1638 02:49:22.531651 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1639 02:49:22.542661 <30>[ 20.446679] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1640 02:49:22.554171 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1641 02:49:22.565155 <30>[ 20.466622] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1642 02:49:22.571706 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1643 02:49:22.593868 <30>[ 20.486578] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1644 02:49:22.599435 <30>[ 20.500634] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1645 02:49:22.607075 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1646 02:49:22.618186 <30>[ 20.522504] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1647 02:49:22.624381 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1648 02:49:22.640218 <30>[ 20.546527] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1649 02:49:22.649244 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1650 02:49:22.660324 <30>[ 20.566549] systemd[1]: Reached target paths.target - Path Units.
1651 02:49:22.668758 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1652 02:49:22.674300 <30>[ 20.582518] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1653 02:49:22.686081 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1654 02:49:22.691544 <30>[ 20.598500] systemd[1]: Reached target slices.target - Slice Units.
1655 02:49:22.699708 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1656 02:49:22.705245 <30>[ 20.614517] systemd[1]: Reached target swap.target - Swaps.
1657 02:49:22.712215 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1658 02:49:22.724204 <30>[ 20.630546] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1659 02:49:22.733178 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1660 02:49:22.748358 <30>[ 20.654704] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1661 02:49:22.757607 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1662 02:49:22.769457 <30>[ 20.675791] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1663 02:49:22.783403 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1664 02:49:22.788981 <30>[ 20.695411] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1665 02:49:22.802112 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1666 02:49:22.807594 <30>[ 20.714874] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1667 02:49:22.814413 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1668 02:49:22.825496 <30>[ 20.731490] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1669 02:49:22.834301 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1670 02:49:22.846106 <30>[ 20.752427] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1671 02:49:22.851649 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1672 02:49:22.864418 <30>[ 20.770758] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1673 02:49:22.872879 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1674 02:49:22.912335 <30>[ 20.818628] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1675 02:49:22.919076 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1676 02:49:22.930829 <30>[ 20.837148] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1677 02:49:22.938366 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1678 02:49:22.950511 <30>[ 20.856851] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1679 02:49:22.958996 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1680 02:49:22.976021 <30>[ 20.875155] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1681 02:49:23.000827 <30>[ 20.907120] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1682 02:49:23.009387 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1683 02:49:23.025212 <30>[ 20.931524] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1684 02:49:23.033225 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1685 02:49:23.049275 <30>[ 20.955588] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1686 02:49:23.056868 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1687 02:49:23.073922 <30>[ 20.980138] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1688 02:49:23.089896 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Mo<6>[ 20.988834] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1689 02:49:23.090430 dule drm...
1690 02:49:23.104770 <30>[ 21.011105] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1691 02:49:23.113091 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1692 02:49:23.132541 <30>[ 21.038891] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1693 02:49:23.139869 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1694 02:49:23.146897 <6>[ 21.058749] fuse: init (API version 7.41)
1695 02:49:23.158018 <30>[ 21.061014] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1696 02:49:23.161908 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1697 02:49:23.179166 <30>[ 21.085371] systemd[1]: Starting systemd-journald.service - Journal Service...
1698 02:49:23.185440 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1699 02:49:23.237034 <30>[ 21.143212] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1700 02:49:23.244503 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1701 02:49:23.265112 <30>[ 21.171344] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1702 02:49:23.274431 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1703 02:49:23.290246 <30>[ 21.196458] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1704 02:49:23.298971 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1705 02:49:23.314921 <30>[ 21.221123] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1706 02:49:23.324006 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1707 02:49:23.334876 <30>[ 21.241156] systemd[1]: Started systemd-journald.service - Journal Service.
1708 02:49:23.341751 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1709 02:49:23.354615 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1710 02:49:23.368461 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1711 02:49:23.376051 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1712 02:49:23.389163 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1713 02:49:23.409483 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1714 02:49:23.421457 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1715 02:49:23.433234 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1716 02:49:23.453512 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1717 02:49:23.469359 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1718 02:49:23.481369 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1719 02:49:23.493254 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1720 02:49:23.509352 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1721 02:49:23.521362 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1722 02:49:23.537468 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1723 02:49:23.587046 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1724 02:49:23.598383 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1725 02:49:23.614584 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1726 02:49:23.626124 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1727 02:49:23.641369 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1728 02:49:23.653658 <46>[ 21.559914] systemd-journald[229]: Received client request to flush runtime journal.
1729 02:49:23.661056 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1730 02:49:23.688735 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1731 02:49:23.695338 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1732 02:49:23.717163 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1733 02:49:23.737390 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1734 02:49:23.753362 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1735 02:49:23.786859 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1736 02:49:23.844165 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1737 02:49:23.967401 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1738 02:49:23.979893 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1739 02:49:23.992907 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1740 02:49:24.011957 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1741 02:49:24.064002 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1742 02:49:24.078690 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1743 02:49:24.280614 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1744 02:49:24.339167 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1745 02:49:24.346723 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1746 02:49:24.431732 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1747 02:49:24.494695 <5>[ 22.400996] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1748 02:49:24.508131 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1749 02:49:24.518982 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1750 02:49:24.535455 <5>[ 22.441699] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1751 02:49:24.541073 <5>[ 22.442356] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1752 02:49:24.549888 <4>[ 22.451268] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1753 02:49:24.554706 <6>[ 22.460455] cfg80211: failed to load regulatory.db
1754 02:49:24.599394 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1755 02:49:24.620955 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1756 02:49:24.635179 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1757 02:49:24.652399 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1758 02:49:24.679573 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1759 02:49:24.692873 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1760 02:49:24.704516 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1761 02:49:24.716664 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1762 02:49:24.727659 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1763 02:49:24.757720 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily <46>[ 22.647673] systemd-journald[229]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1764 02:49:24.768819 <46>[ 22.665412] systemd-journald[229]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1765 02:49:24.774004 apt download activities.
1766 02:49:24.792197 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1767 02:49:24.800643 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1768 02:49:24.818991 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1769 02:49:24.908374 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1770 02:49:24.916859 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1771 02:49:24.930074 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1772 02:49:24.935667 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1773 02:49:24.947562 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1774 02:49:24.995254 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1775 02:49:25.048103 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1776 02:49:25.069983 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1777 02:49:25.082081 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1778 02:49:25.117465 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1779 02:49:25.129475 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1780 02:49:25.145853 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1781 02:49:25.165448 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1782 02:49:25.181575 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1783 02:49:25.193837 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1784 02:49:25.209460 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1785 02:49:25.221575 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1786 02:49:25.237976 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1787 02:49:25.244635 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1788 02:49:25.257191 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1789 02:49:25.268748 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1790 02:49:25.300619 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1791 02:49:25.361534 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1792 02:49:25.419656
1793 02:49:25.420359 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1794 02:49:25.420837
1795 02:49:25.426728 debian-bookworm-arm64 login: root (automatic login)
1796 02:49:25.427260
1797 02:49:25.566108 Linux debian-bookworm-arm64 6.12.0-rc1 #1 SMP PREEMPT Wed Nov 6 01:46:21 UTC 2024 aarch64
1798 02:49:25.566514
1799 02:49:25.571678 The programs included with the Debian GNU/Linux system are free software;
1800 02:49:25.577180 the exact distribution terms for each program are described in the
1801 02:49:25.582816 individual files in /usr/share/doc/*/copyright.
1802 02:49:25.583310
1803 02:49:25.588274 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1804 02:49:25.591387 permitted by applicable law.
1805 02:49:26.180133 Matched prompt #10: / #
1807 02:49:26.181714 Setting prompt string to ['/ #']
1808 02:49:26.182297 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1810 02:49:26.183684 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1811 02:49:26.184256 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
1812 02:49:26.184680 Setting prompt string to ['/ #']
1813 02:49:26.185079 Forcing a shell prompt, looking for ['/ #']
1815 02:49:26.236050 / #
1816 02:49:26.236771 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1817 02:49:26.237210 Waiting using forced prompt support (timeout 00:02:30)
1818 02:49:26.242193
1819 02:49:26.242980 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1820 02:49:26.243515 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
1821 02:49:26.243964 Sending with 10 millisecond of delay
1823 02:49:31.232471 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/943521/extract-nfsrootfs-7e1yg237'
1824 02:49:31.243488 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/943521/extract-nfsrootfs-7e1yg237'
1825 02:49:31.244368 Sending with 10 millisecond of delay
1827 02:49:33.346488 / # export NFS_SERVER_IP='192.168.6.2'
1828 02:49:33.357509 export NFS_SERVER_IP='192.168.6.2'
1829 02:49:33.358525 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1830 02:49:33.359197 end: 2.4 uboot-commands (duration 00:01:56) [common]
1831 02:49:33.359847 end: 2 uboot-action (duration 00:01:56) [common]
1832 02:49:33.360577 start: 3 lava-test-retry (timeout 00:06:46) [common]
1833 02:49:33.361233 start: 3.1 lava-test-shell (timeout 00:06:46) [common]
1834 02:49:33.361746 Using namespace: common
1836 02:49:33.463026 / # #
1837 02:49:33.463864 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1838 02:49:33.469455 #
1839 02:49:33.470322 Using /lava-943521
1841 02:49:33.571583 / # export SHELL=/bin/bash
1842 02:49:33.577565 export SHELL=/bin/bash
1844 02:49:33.678687 / # . /lava-943521/environment
1845 02:49:33.683754 . /lava-943521/environment
1847 02:49:33.788639 / # /lava-943521/bin/lava-test-runner /lava-943521/0
1848 02:49:33.789388 Test shell timeout: 10s (minimum of the action and connection timeout)
1849 02:49:33.793738 /lava-943521/bin/lava-test-runner /lava-943521/0
1850 02:49:33.986390 + export TESTRUN_ID=0_timesync-off
1851 02:49:33.994124 + TESTRUN_ID=0_timesync-off
1852 02:49:33.994690 + cd /lava-943521/0/tests/0_timesync-off
1853 02:49:33.995110 ++ cat uuid
1854 02:49:34.001742 + UUID=943521_1.6.2.4.1
1855 02:49:34.002241 + set +x
1856 02:49:34.010333 <LAVA_SIGNAL_STARTRUN 0_timesync-off 943521_1.6.2.4.1>
1857 02:49:34.010817 + systemctl stop systemd-timesyncd
1858 02:49:34.011520 Received signal: <STARTRUN> 0_timesync-off 943521_1.6.2.4.1
1859 02:49:34.011961 Starting test lava.0_timesync-off (943521_1.6.2.4.1)
1860 02:49:34.012515 Skipping test definition patterns.
1861 02:49:34.048642 + set +x
1862 02:49:34.049236 <LAVA_SIGNAL_ENDRUN 0_timesync-off 943521_1.6.2.4.1>
1863 02:49:34.049911 Received signal: <ENDRUN> 0_timesync-off 943521_1.6.2.4.1
1864 02:49:34.050422 Ending use of test pattern.
1865 02:49:34.050828 Ending test lava.0_timesync-off (943521_1.6.2.4.1), duration 0.04
1867 02:49:34.133008 + export TESTRUN_ID=1_kselftest-alsa
1868 02:49:34.139606 + TESTRUN_ID=1_kselftest-alsa
1869 02:49:34.140148 + cd /lava-943521/0/tests/1_kselftest-alsa
1870 02:49:34.140576 ++ cat uuid
1871 02:49:34.145111 + UUID=943521_1.6.2.4.5
1872 02:49:34.145604 + set +x
1873 02:49:34.150667 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 943521_1.6.2.4.5>
1874 02:49:34.151177 + cd ./automated/linux/kselftest/
1875 02:49:34.151903 Received signal: <STARTRUN> 1_kselftest-alsa 943521_1.6.2.4.5
1876 02:49:34.152416 Starting test lava.1_kselftest-alsa (943521_1.6.2.4.5)
1877 02:49:34.152964 Skipping test definition patterns.
1878 02:49:34.179394 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g clk -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1879 02:49:34.228639 INFO: install_deps skipped
1880 02:49:34.351857 --2024-11-06 02:49:34-- http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kselftest.tar.xz
1881 02:49:34.609209 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1882 02:49:34.750449 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1883 02:49:34.891835 HTTP request sent, awaiting response... 200 OK
1884 02:49:34.892402 Length: 5042576 (4.8M) [application/octet-stream]
1885 02:49:34.897287 Saving to: 'kselftest_armhf.tar.gz'
1886 02:49:34.897764
1887 02:49:36.029356
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 179KB/s
kselftest_armhf.tar 4%[ ] 218.67K 393KB/s
kselftest_armhf.tar 18%[==> ] 893.67K 1.05MB/s
kselftest_armhf.tar 72%[=============> ] 3.51M 3.15MB/s
kselftest_armhf.tar 100%[===================>] 4.81M 4.25MB/s in 1.1s
1888 02:49:36.030053
1889 02:49:36.106819 2024-11-06 02:49:36 (4.25 MB/s) - 'kselftest_armhf.tar.gz' saved [5042576/5042576]
1890 02:49:36.107478
1891 02:49:44.382170 skiplist:
1892 02:49:44.382876 ========================================
1893 02:49:44.387742 ========================================
1894 02:49:44.429830 alsa:mixer-test
1895 02:49:44.430411 alsa:pcm-test
1896 02:49:44.430871 alsa:test-pcmtest-driver
1897 02:49:44.433915 alsa:utimer-test
1898 02:49:44.447207 ============== Tests to run ===============
1899 02:49:44.447788 alsa:mixer-test
1900 02:49:44.452599 alsa:pcm-test
1901 02:49:44.453103 alsa:test-pcmtest-driver
1902 02:49:44.453561 alsa:utimer-test
1903 02:49:44.460830 ===========End Tests to run ===============
1904 02:49:44.461331 shardfile-alsa pass
1905 02:49:44.562087 <12>[ 42.471617] kselftest: Running tests in alsa
1906 02:49:44.568500 TAP version 13
1907 02:49:44.576274 1..4
1908 02:49:44.608494 # timeout set to 45
1909 02:49:44.609054 # selftests: alsa: mixer-test
1910 02:49:44.762347 # TAP version 13
1911 02:49:44.762991 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1912 02:49:44.767722 # 1..427
1913 02:49:44.768258 # ok 1 get_value.LCALTA.60
1914 02:49:44.768712 # # LCALTA.60 TDMOUT_A SRC SEL
1915 02:49:44.773172 # ok 2 name.LCALTA.60
1916 02:49:44.773654 # ok 3 write_default.LCALTA.60
1917 02:49:44.778708 # ok 4 write_valid.LCALTA.60
1918 02:49:44.779189 # ok 5 write_invalid.LCALTA.60
1919 02:49:44.784341 # ok 6 event_missing.LCALTA.60
1920 02:49:44.784827 # ok 7 event_spurious.LCALTA.60
1921 02:49:44.790039 # ok 8 get_value.LCALTA.59
1922 02:49:44.790538 # # LCALTA.59 TDMOUT_B SRC SEL
1923 02:49:44.795569 # ok 9 name.LCALTA.59
1924 02:49:44.796118 # ok 10 write_default.LCALTA.59
1925 02:49:44.801017 # ok 11 write_valid.LCALTA.59
1926 02:49:44.801543 # ok 12 write_invalid.LCALTA.59
1927 02:49:44.806661 # ok 13 event_missing.LCALTA.59
1928 02:49:44.807173 # ok 14 event_spurious.LCALTA.59
1929 02:49:44.812243 # ok 15 get_value.LCALTA.58
1930 02:49:44.812755 # # LCALTA.58 TDMOUT_C SRC SEL
1931 02:49:44.817666 # ok 16 name.LCALTA.58
1932 02:49:44.818179 # ok 17 write_default.LCALTA.58
1933 02:49:44.823321 # ok 18 write_valid.LCALTA.58
1934 02:49:44.823843 # ok 19 write_invalid.LCALTA.58
1935 02:49:44.828846 # ok 20 event_missing.LCALTA.58
1936 02:49:44.829362 # ok 21 event_spurious.LCALTA.58
1937 02:49:44.834333 # ok 22 get_value.LCALTA.57
1938 02:49:44.834848 # # LCALTA.57 TDMIN_A SRC SEL
1939 02:49:44.835302 # ok 23 name.LCALTA.57
1940 02:49:44.839926 # ok 24 write_default.LCALTA.57
1941 02:49:44.840462 # ok 25 write_valid.LCALTA.57
1942 02:49:44.845476 # ok 26 write_invalid.LCALTA.57
1943 02:49:44.845978 # ok 27 event_missing.LCALTA.57
1944 02:49:44.851040 # ok 28 event_spurious.LCALTA.57
1945 02:49:44.851548 # ok 29 get_value.LCALTA.56
1946 02:49:44.856557 # # LCALTA.56 TDMIN_B SRC SEL
1947 02:49:44.857079 # ok 30 name.LCALTA.56
1948 02:49:44.862027 # ok 31 write_default.LCALTA.56
1949 02:49:44.862531 # ok 32 write_valid.LCALTA.56
1950 02:49:44.867532 # ok 33 write_invalid.LCALTA.56
1951 02:49:44.878610 #<3>[ 42.776207] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1952 02:49:44.879168 ok 34 event_missing.LCALTA.56
1953 02:49:44.884278 # ok 35 event_spurious.LCALTA.56
1954 02:49:44.884793 # ok 36 get_value.LCALTA.55
1955 02:49:44.889734 # # LCALTA.55 TDMIN_C SRC SEL
1956 02:49:44.890234 # ok 37 name.LCALTA.55
1957 02:49:44.895284 # ok 38 write_default.LCALTA.55
1958 02:49:44.895785 # ok 39 write_valid.LCALTA.55
1959 02:49:44.900831 # ok 40 write_invalid.LCALTA.55
1960 02:49:44.901337 # ok 41 event_missing.LCALTA.55
1961 02:49:44.906374 # ok 42 event_spurious.LCALTA.55
1962 02:49:44.906875 # ok 43 get_value.LCALTA.54
1963 02:49:44.911909 # # LCALTA.54 ACODEC Left DAC Sel
1964 02:49:44.912444 # ok 44 name.LCALTA.54
1965 02:49:44.917483 # ok 45 write_default.LCALTA.54
1966 02:49:44.917983 # ok 46 write_valid.LCALTA.54
1967 02:49:44.923018 # ok 47 write_invalid.LCALTA.54
1968 02:49:44.923520 # ok 48 event_missing.LCALTA.54
1969 02:49:44.928565 # ok 49 event_spurious.LCALTA.54
1970 02:49:44.929070 # ok 50 get_value.LCALTA.53
1971 02:49:44.934114 # # LCALTA.53 ACODEC Right DAC Sel
1972 02:49:44.934621 # ok 51 name.LCALTA.53
1973 02:49:44.939657 # ok 52 write_default.LCALTA.53
1974 02:49:44.940191 # ok 53 write_valid.LCALTA.53
1975 02:49:44.945240 # ok 54 write_invalid.LCALTA.53
1976 02:49:44.945765 # ok 55 event_missing.LCALTA.53
1977 02:49:44.950768 # ok 56 event_spurious.LCALTA.53
1978 02:49:44.951273 # ok 57 get_value.LCALTA.52
1979 02:49:44.956327 # # LCALTA.52 TOACODEC OUT EN Switch
1980 02:49:44.956832 # ok 58 name.LCALTA.52
1981 02:49:44.961866 # ok 59 write_default.LCALTA.52
1982 02:49:44.962361 # ok 60 write_valid.LCALTA.52
1983 02:49:44.967416 # ok 61 write_invalid.LCALTA.52
1984 02:49:44.967922 # ok 62 event_missing.LCALTA.52
1985 02:49:44.972950 # ok 63 event_spurious.LCALTA.52
1986 02:49:44.973451 # ok 64 get_value.LCALTA.51
1987 02:49:44.978510 # # LCALTA.51 TOACODEC SRC
1988 02:49:44.979007 # ok 65 name.LCALTA.51
1989 02:49:44.984085 # ok 66 write_default.LCALTA.51
1990 02:49:44.984587 # ok 67 write_valid.LCALTA.51
1991 02:49:44.989600 # ok 68 write_invalid.LCALTA.51
1992 02:49:44.990097 # ok 69 event_missing.LCALTA.51
1993 02:49:44.995142 # ok 70 event_spurious.LCALTA.51
1994 02:49:44.995648 # ok 71 get_value.LCALTA.50
1995 02:49:45.000692 # # LCALTA.50 TOHDMITX SPDIF SRC
1996 02:49:45.001194 # ok 72 name.LCALTA.50
1997 02:49:45.001642 # ok 73 write_default.LCALTA.50
1998 02:49:45.006262 # ok 74 write_valid.LCALTA.50
1999 02:49:45.006763 # ok 75 write_invalid.LCALTA.50
2000 02:49:45.011785 # ok 76 event_missing.LCALTA.50
2001 02:49:45.017339 # ok 77 event_spurious.LCALTA.50
2002 02:49:45.017842 # ok 78 get_value.LCALTA.49
2003 02:49:45.018291 # # LCALTA.49 TOHDMITX Switch
2004 02:49:45.022837 # ok 79 name.LCALTA.49
2005 02:49:45.023334 # ok 80 write_default.LCALTA.49
2006 02:49:45.028397 # ok 81 write_valid.LCALTA.49
2007 02:49:45.028895 # ok 82 write_invalid.LCALTA.49
2008 02:49:45.033969 # ok 83 event_missing.LCALTA.49
2009 02:49:45.034472 # ok 84 event_spurious.LCALTA.49
2010 02:49:45.039521 # ok 85 get_value.LCALTA.48
2011 02:49:45.040052 # # LCALTA.48 TOHDMITX I2S SRC
2012 02:49:45.045057 # ok 86 name.LCALTA.48
2013 02:49:45.045553 # ok 87 write_default.LCALTA.48
2014 02:49:45.050604 # ok 88 write_valid.LCALTA.48
2015 02:49:45.051105 # ok 89 write_invalid.LCALTA.48
2016 02:49:45.056179 # ok 90 event_missing.LCALTA.48
2017 02:49:45.056680 # ok 91 event_spurious.LCALTA.48
2018 02:49:45.061707 # ok 92 get_value.LCALTA.47
2019 02:49:45.062211 # # LCALTA.47 TODDR_C SRC SEL
2020 02:49:45.067289 # ok 93 name.LCALTA.47
2021 02:49:45.067788 # ok 94 write_default.LCALTA.47
2022 02:49:45.072808 # ok 95 write_valid.LCALTA.47
2023 02:49:45.073309 # ok 96 write_invalid.LCALTA.47
2024 02:49:45.078354 # ok 97 event_missing.LCALTA.47
2025 02:49:45.078859 # ok 98 event_spurious.LCALTA.47
2026 02:49:45.083887 # ok 99 get_value.LCALTA.46
2027 02:49:45.084424 # # LCALTA.46 TODDR_B SRC SEL
2028 02:49:45.084881 # ok 100 name.LCALTA.46
2029 02:49:45.089439 # ok 101 write_default.LCALTA.46
2030 02:49:45.094984 # ok 102 write_valid.LCALTA.46
2031 02:49:45.095486 # ok 103 write_invalid.LCALTA.46
2032 02:49:45.100557 # ok 104 event_missing.LCALTA.46
2033 02:49:45.101061 # ok 105 event_spurious.LCALTA.46
2034 02:49:45.106081 # ok 106 get_value.LCALTA.45
2035 02:49:45.106576 # # LCALTA.45 TODDR_A SRC SEL
2036 02:49:45.107027 # ok 107 name.LCALTA.45
2037 02:49:45.111600 # ok 108 write_default.LCALTA.45
2038 02:49:45.117213 # ok 109 write_valid.LCALTA.45
2039 02:49:45.117722 # ok 110 write_invalid.LCALTA.45
2040 02:49:45.122752 # ok 111 event_missing.LCALTA.45
2041 02:49:45.123256 # ok 112 event_spurious.LCALTA.45
2042 02:49:45.128349 # ok 113 get_value.LCALTA.44
2043 02:49:45.128872 # # LCALTA.44 FRDDR_C SINK 3 SEL
2044 02:49:45.133782 # ok 114 name.LCALTA.44
2045 02:49:45.134290 # ok 115 write_default.LCALTA.44
2046 02:49:45.139313 # ok 116 write_valid.LCALTA.44
2047 02:49:45.139817 # ok 117 write_invalid.LCALTA.44
2048 02:49:45.144901 # ok 118 event_missing.LCALTA.44
2049 02:49:45.145413 # ok 119 event_spurious.LCALTA.44
2050 02:49:45.150443 # ok 120 get_value.LCALTA.43
2051 02:49:45.150948 # # LCALTA.43 FRDDR_C SINK 2 SEL
2052 02:49:45.156006 # ok 121 name.LCALTA.43
2053 02:49:45.156507 # ok 122 write_default.LCALTA.43
2054 02:49:45.161516 # ok 123 write_valid.LCALTA.43
2055 02:49:45.162014 # ok 124 write_invalid.LCALTA.43
2056 02:49:45.167087 # ok 125 event_missing.LCALTA.43
2057 02:49:45.167590 # ok 126 event_spurious.LCALTA.43
2058 02:49:45.172634 # ok 127 get_value.LCALTA.42
2059 02:49:45.173140 # # LCALTA.42 FRDDR_C SINK 1 SEL
2060 02:49:45.178182 # ok 128 name.LCALTA.42
2061 02:49:45.178688 # ok 129 write_default.LCALTA.42
2062 02:49:45.183731 # ok 130 write_valid.LCALTA.42
2063 02:49:45.184262 # ok 131 write_invalid.LCALTA.42
2064 02:49:45.189282 # ok 132 event_missing.LCALTA.42
2065 02:49:45.189785 # ok 133 event_spurious.LCALTA.42
2066 02:49:45.194816 # ok 134 get_value.LCALTA.41
2067 02:49:45.195318 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2068 02:49:45.200371 # ok 135 name.LCALTA.41
2069 02:49:45.200873 # ok 136 write_default.LCALTA.41
2070 02:49:45.205934 # ok 137 write_valid.LCALTA.41
2071 02:49:45.206436 # ok 138 write_invalid.LCALTA.41
2072 02:49:45.211456 # ok 139 event_missing.LCALTA.41
2073 02:49:45.211956 # ok 140 event_spurious.LCALTA.41
2074 02:49:45.217000 # ok 141 get_value.LCALTA.40
2075 02:49:45.217497 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2076 02:49:45.222549 # ok 142 name.LCALTA.40
2077 02:49:45.223043 # ok 143 write_default.LCALTA.40
2078 02:49:45.228095 # ok 144 write_valid.LCALTA.40
2079 02:49:45.228591 # ok 145 write_invalid.LCALTA.40
2080 02:49:45.233611 # ok 146 event_missing.LCALTA.40
2081 02:49:45.234107 # ok 147 event_spurious.LCALTA.40
2082 02:49:45.239277 # ok 148 get_value.LCALTA.39
2083 02:49:45.244709 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2084 02:49:45.245204 # ok 149 name.LCALTA.39
2085 02:49:45.245656 # ok 150 write_default.LCALTA.39
2086 02:49:45.250306 # ok 151 write_valid.LCALTA.39
2087 02:49:45.250809 # ok 152 write_invalid.LCALTA.39
2088 02:49:45.255866 # ok 153 event_missing.LCALTA.39
2089 02:49:45.261375 # ok 154 event_spurious.LCALTA.39
2090 02:49:45.261883 # ok 155 get_value.LCALTA.38
2091 02:49:45.266903 # # LCALTA.38 FRDDR_B SINK 3 SEL
2092 02:49:45.267401 # ok 156 name.LCALTA.38
2093 02:49:45.267855 # ok 157 write_default.LCALTA.38
2094 02:49:45.272472 # ok 158 write_valid.LCALTA.38
2095 02:49:45.272974 # ok 159 write_invalid.LCALTA.38
2096 02:49:45.278025 # ok 160 event_missing.LCALTA.38
2097 02:49:45.283563 # ok 161 event_spurious.LCALTA.38
2098 02:49:45.284090 # ok 162 get_value.LCALTA.37
2099 02:49:45.289103 # # LCALTA.37 FRDDR_B SINK 2 SEL
2100 02:49:45.289601 # ok 163 name.LCALTA.37
2101 02:49:45.290051 # ok 164 write_default.LCALTA.37
2102 02:49:45.294655 # ok 165 write_valid.LCALTA.37
2103 02:49:45.300316 # ok 166 write_invalid.LCALTA.37
2104 02:49:45.300816 # ok 167 event_missing.LCALTA.37
2105 02:49:45.305749 # ok 168 event_spurious.LCALTA.37
2106 02:49:45.306250 # ok 169 get_value.LCALTA.36
2107 02:49:45.311317 # # LCALTA.36 FRDDR_B SINK 1 SEL
2108 02:49:45.311820 # ok 170 name.LCALTA.36
2109 02:49:45.316845 # ok 171 write_default.LCALTA.36
2110 02:49:45.317346 # ok 172 write_valid.LCALTA.36
2111 02:49:45.322379 # ok 173 write_invalid.LCALTA.36
2112 02:49:45.322875 # ok 174 event_missing.LCALTA.36
2113 02:49:45.327955 # ok 175 event_spurious.LCALTA.36
2114 02:49:45.328485 # ok 176 get_value.LCALTA.35
2115 02:49:45.333491 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2116 02:49:45.333991 # ok 177 name.LCALTA.35
2117 02:49:45.339031 # ok 178 write_default.LCALTA.35
2118 02:49:45.339540 # ok 179 write_valid.LCALTA.35
2119 02:49:45.344578 # ok 180 write_invalid.LCALTA.35
2120 02:49:45.345084 # ok 181 event_missing.LCALTA.35
2121 02:49:45.350128 # ok 182 event_spurious.LCALTA.35
2122 02:49:45.350632 # ok 183 get_value.LCALTA.34
2123 02:49:45.355692 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2124 02:49:45.356229 # ok 184 name.LCALTA.34
2125 02:49:45.361323 # ok 185 write_default.LCALTA.34
2126 02:49:45.361828 # ok 186 write_valid.LCALTA.34
2127 02:49:45.366748 # ok 187 write_invalid.LCALTA.34
2128 02:49:45.367250 # ok 188 event_missing.LCALTA.34
2129 02:49:45.372298 # ok 189 event_spurious.LCALTA.34
2130 02:49:45.372802 # ok 190 get_value.LCALTA.33
2131 02:49:45.377851 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2132 02:49:45.378352 # ok 191 name.LCALTA.33
2133 02:49:45.383384 # ok 192 write_default.LCALTA.33
2134 02:49:45.383882 # ok 193 write_valid.LCALTA.33
2135 02:49:45.388937 # ok 194 write_invalid.LCALTA.33
2136 02:49:45.389440 # ok 195 event_missing.LCALTA.33
2137 02:49:45.394472 # ok 196 event_spurious.LCALTA.33
2138 02:49:45.394975 # ok 197 get_value.LCALTA.32
2139 02:49:45.400060 # # LCALTA.32 FRDDR_A SINK 3 SEL
2140 02:49:45.400561 # ok 198 name.LCALTA.32
2141 02:49:45.405570 # ok 199 write_default.LCALTA.32
2142 02:49:45.406069 # ok 200 write_valid.LCALTA.32
2143 02:49:45.411200 # ok 201 write_invalid.LCALTA.32
2144 02:49:45.411702 # ok 202 event_missing.LCALTA.32
2145 02:49:45.416672 # ok 203 event_spurious.LCALTA.32
2146 02:49:45.417172 # ok 204 get_value.LCALTA.31
2147 02:49:45.422296 # # LCALTA.31 FRDDR_A SINK 2 SEL
2148 02:49:45.422804 # ok 205 name.LCALTA.31
2149 02:49:45.427743 # ok 206 write_default.LCALTA.31
2150 02:49:45.428387 # ok 207 write_valid.LCALTA.31
2151 02:49:45.433307 # ok 208 write_invalid.LCALTA.31
2152 02:49:45.433816 # ok 209 event_missing.LCALTA.31
2153 02:49:45.438844 # ok 210 event_spurious.LCALTA.31
2154 02:49:45.439347 # ok 211 get_value.LCALTA.30
2155 02:49:45.444413 # # LCALTA.30 FRDDR_A SINK 1 SEL
2156 02:49:45.444917 # ok 212 name.LCALTA.30
2157 02:49:45.449952 # ok 213 write_default.LCALTA.30
2158 02:49:45.450463 # ok 214 write_valid.LCALTA.30
2159 02:49:45.455488 # ok 215 write_invalid.LCALTA.30
2160 02:49:45.461056 # ok 216 event_missing.LCALTA.30
2161 02:49:45.461555 # ok 217 event_spurious.LCALTA.30
2162 02:49:45.466584 # ok 218 get_value.LCALTA.29
2163 02:49:45.467081 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2164 02:49:45.472235 # ok 219 name.LCALTA.29
2165 02:49:45.472746 # ok 220 write_default.LCALTA.29
2166 02:49:45.477678 # ok 221 write_valid.LCALTA.29
2167 02:49:45.478178 # ok 222 write_invalid.LCALTA.29
2168 02:49:45.483323 # ok 223 event_missing.LCALTA.29
2169 02:49:45.483823 # ok 224 event_spurious.LCALTA.29
2170 02:49:45.488768 # ok 225 get_value.LCALTA.28
2171 02:49:45.489266 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2172 02:49:45.494328 # ok 226 name.LCALTA.28
2173 02:49:45.494827 # ok 227 write_default.LCALTA.28
2174 02:49:45.499858 # ok 228 write_valid.LCALTA.28
2175 02:49:45.500395 # ok 229 write_invalid.LCALTA.28
2176 02:49:45.505420 # ok 230 event_missing.LCALTA.28
2177 02:49:45.505931 # ok 231 event_spurious.LCALTA.28
2178 02:49:45.510945 # ok 232 get_value.LCALTA.27
2179 02:49:45.511452 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2180 02:49:45.516518 # ok 233 name.LCALTA.27
2181 02:49:45.517034 # ok 234 write_default.LCALTA.27
2182 02:49:45.522054 # ok 235 write_valid.LCALTA.27
2183 02:49:45.522564 # ok 236 write_invalid.LCALTA.27
2184 02:49:45.527606 # ok 237 event_missing.LCALTA.27
2185 02:49:45.528152 # ok 238 event_spurious.LCALTA.27
2186 02:49:45.533193 # ok 239 get_value.LCALTA.26
2187 02:49:45.533700 # # LCALTA.26 ELD
2188 02:49:45.538704 # ok 240 name.LCALTA.26
2189 02:49:45.539216 # # ELD is not writeable
2190 02:49:45.544323 # ok 241 # SKIP write_default.LCALTA.26
2191 02:49:45.544836 # # ELD is not writeable
2192 02:49:45.549868 # ok 242 # SKIP write_valid.LCALTA.26
2193 02:49:45.550388 # # ELD is not writeable
2194 02:49:45.555380 # ok 243 # SKIP write_invalid.LCALTA.26
2195 02:49:45.555895 # ok 244 event_missing.LCALTA.26
2196 02:49:45.560918 # ok 245 event_spurious.LCALTA.26
2197 02:49:45.561429 # ok 246 get_value.LCALTA.25
2198 02:49:45.566454 # # LCALTA.25 IEC958 Playback Default
2199 02:49:45.566970 # ok 247 name.LCALTA.25
2200 02:49:45.572027 # ok 248 write_default.LCALTA.25
2201 02:49:45.572535 # ok 249 # SKIP write_valid.LCALTA.25
2202 02:49:45.577561 # ok 250 # SKIP write_invalid.LCALTA.25
2203 02:49:45.583083 # ok 251 event_missing.LCALTA.25
2204 02:49:45.583592 # ok 252 event_spurious.LCALTA.25
2205 02:49:45.588637 # ok 253 get_value.LCALTA.24
2206 02:49:45.589141 # # LCALTA.24 IEC958 Playback Mask
2207 02:49:45.589593 # ok 254 name.LCALTA.24
2208 02:49:45.594239 # # IEC958 Playback Mask is not writeable
2209 02:49:45.599769 # ok 255 # SKIP write_default.LCALTA.24
2210 02:49:45.600331 # # IEC958 Playback Mask is not writeable
2211 02:49:45.605391 # ok 256 # SKIP write_valid.LCALTA.24
2212 02:49:45.610836 # # IEC958 Playback Mask is not writeable
2213 02:49:45.611375 # ok 257 # SKIP write_invalid.LCALTA.24
2214 02:49:45.616405 # ok 258 event_missing.LCALTA.24
2215 02:49:45.616945 # ok 259 event_spurious.LCALTA.24
2216 02:49:45.621963 # ok 260 get_value.LCALTA.23
2217 02:49:45.622503 # # LCALTA.23 Playback Channel Map
2218 02:49:45.627551 # ok 261 name.LCALTA.23
2219 02:49:45.633031 # # Playback Channel Map is not writeable
2220 02:49:45.633552 # ok 262 # SKIP write_default.LCALTA.23
2221 02:49:45.638558 # # Playback Channel Map is not writeable
2222 02:49:45.639079 # ok 263 # SKIP write_valid.LCALTA.23
2223 02:49:45.644131 # # Playback Channel Map is not writeable
2224 02:49:45.649654 # ok 264 # SKIP write_invalid.LCALTA.23
2225 02:49:45.650183 # ok 265 event_missing.LCALTA.23
2226 02:49:45.655234 # ok 266 event_spurious.LCALTA.23
2227 02:49:45.655759 # ok 267 get_value.LCALTA.22
2228 02:49:45.660763 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2229 02:49:45.661283 # ok 268 name.LCALTA.22
2230 02:49:45.666396 # ok 269 write_default.LCALTA.22
2231 02:49:45.666914 # ok 270 write_valid.LCALTA.22
2232 02:49:45.671874 # ok 271 write_invalid.LCALTA.22
2233 02:49:45.672448 # ok 272 event_missing.LCALTA.22
2234 02:49:45.677455 # ok 273 event_spurious.LCALTA.22
2235 02:49:45.682953 # ok 274 get_value.LCALTA.21
2236 02:49:45.683485 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2237 02:49:45.683933 # ok 275 name.LCALTA.21
2238 02:49:45.688496 # ok 276 write_default.LCALTA.21
2239 02:49:45.694048 # ok 277 write_valid.LCALTA.21
2240 02:49:45.694575 # ok 278 write_invalid.LCALTA.21
2241 02:49:45.699594 # ok 279 event_missing.LCALTA.21
2242 02:49:45.700150 # ok 280 event_spurious.LCALTA.21
2243 02:49:45.705154 # ok 281 get_value.LCALTA.20
2244 02:49:45.705673 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2245 02:49:45.710671 # ok 282 name.LCALTA.20
2246 02:49:45.711190 # ok 283 write_default.LCALTA.20
2247 02:49:45.716292 # ok 284 write_valid.LCALTA.20
2248 02:49:45.716816 # ok 285 write_invalid.LCALTA.20
2249 02:49:45.721759 # ok 286 event_missing.LCALTA.20
2250 02:49:45.722277 # ok 287 event_spurious.LCALTA.20
2251 02:49:45.727403 # ok 288 get_value.LCALTA.19
2252 02:49:45.727926 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2253 02:49:45.732838 # ok 289 name.LCALTA.19
2254 02:49:45.733352 # ok 290 write_default.LCALTA.19
2255 02:49:45.738418 # ok 291 write_valid.LCALTA.19
2256 02:49:45.738927 # ok 292 write_invalid.LCALTA.19
2257 02:49:45.743918 # ok 293 event_missing.LCALTA.19
2258 02:49:45.744460 # ok 294 event_spurious.LCALTA.19
2259 02:49:45.749504 # ok 295 get_value.LCALTA.18
2260 02:49:45.750020 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2261 02:49:45.755017 # ok 296 name.LCALTA.18
2262 02:49:45.755530 # ok 297 write_default.LCALTA.18
2263 02:49:45.760583 # ok 298 write_valid.LCALTA.18
2264 02:49:45.761100 # ok 299 write_invalid.LCALTA.18
2265 02:49:45.766124 # ok 300 event_missing.LCALTA.18
2266 02:49:45.766634 # ok 301 event_spurious.LCALTA.18
2267 02:49:45.771676 # ok 302 get_value.LCALTA.17
2268 02:49:45.777236 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2269 02:49:45.777760 # ok 303 name.LCALTA.17
2270 02:49:45.778199 # ok 304 write_default.LCALTA.17
2271 02:49:45.782767 # ok 305 write_valid.LCALTA.17
2272 02:49:45.788347 # ok 306 write_invalid.LCALTA.17
2273 02:49:45.788852 # ok 307 event_missing.LCALTA.17
2274 02:49:45.793891 # ok 308 event_spurious.LCALTA.17
2275 02:49:45.794446 # ok 309 get_value.LCALTA.16
2276 02:49:45.799400 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2277 02:49:45.799917 # ok 310 name.LCALTA.16
2278 02:49:45.804927 # ok 311 write_default.LCALTA.16
2279 02:49:45.805445 # ok 312 write_valid.LCALTA.16
2280 02:49:45.810488 # ok 313 write_invalid.LCALTA.16
2281 02:49:45.810998 # ok 314 event_missing.LCALTA.16
2282 02:49:45.816044 # ok 315 event_spurious.LCALTA.16
2283 02:49:45.816554 # ok 316 get_value.LCALTA.15
2284 02:49:45.821563 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2285 02:49:45.822070 # ok 317 name.LCALTA.15
2286 02:49:45.827115 # ok 318 write_default.LCALTA.15
2287 02:49:45.827621 # ok 319 write_valid.LCALTA.15
2288 02:49:45.832643 # ok 320 write_invalid.LCALTA.15
2289 02:49:45.833151 # ok 321 event_missing.LCALTA.15
2290 02:49:45.838222 # ok 322 event_spurious.LCALTA.15
2291 02:49:45.838733 # ok 323 get_value.LCALTA.14
2292 02:49:45.843740 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2293 02:49:45.844317 # ok 324 name.LCALTA.14
2294 02:49:45.849372 # ok 325 write_default.LCALTA.14
2295 02:49:45.849880 # ok 326 write_valid.LCALTA.14
2296 02:49:45.854848 # ok 327 write_invalid.LCALTA.14
2297 02:49:45.855356 # ok 328 event_missing.LCALTA.14
2298 02:49:45.860414 # ok 329 event_spurious.LCALTA.14
2299 02:49:45.860921 # ok 330 get_value.LCALTA.13
2300 02:49:45.865950 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2301 02:49:45.866460 # ok 331 name.LCALTA.13
2302 02:49:45.871515 # ok 332 write_default.LCALTA.13
2303 02:49:45.872058 # ok 333 write_valid.LCALTA.13
2304 02:49:45.877040 # ok 334 write_invalid.LCALTA.13
2305 02:49:45.877542 # ok 335 event_missing.LCALTA.13
2306 02:49:45.882596 # ok 336 event_spurious.LCALTA.13
2307 02:49:45.883118 # ok 337 get_value.LCALTA.12
2308 02:49:45.888173 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2309 02:49:45.888704 # ok 338 name.LCALTA.12
2310 02:49:45.893732 # ok 339 write_default.LCALTA.12
2311 02:49:45.899284 # ok 340 write_valid.LCALTA.12
2312 02:49:45.899799 # ok 341 write_invalid.LCALTA.12
2313 02:49:45.904807 # ok 342 event_missing.LCALTA.12
2314 02:49:45.905317 # ok 343 event_spurious.LCALTA.12
2315 02:49:45.910402 # ok 344 get_value.LCALTA.11
2316 02:49:45.910908 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2317 02:49:45.915899 # ok 345 name.LCALTA.11
2318 02:49:45.916439 # ok 346 write_default.LCALTA.11
2319 02:49:45.921444 # ok 347 write_valid.LCALTA.11
2320 02:49:45.921956 # ok 348 write_invalid.LCALTA.11
2321 02:49:45.926966 # ok 349 event_missing.LCALTA.11
2322 02:49:45.927471 # ok 350 event_spurious.LCALTA.11
2323 02:49:45.932499 # ok 351 get_value.LCALTA.10
2324 02:49:45.933009 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2325 02:49:45.938019 # ok 352 name.LCALTA.10
2326 02:49:45.938529 # ok 353 write_default.LCALTA.10
2327 02:49:45.943637 # ok 354 write_valid.LCALTA.10
2328 02:49:45.944186 # ok 355 write_invalid.LCALTA.10
2329 02:49:45.949174 # ok 356 event_missing.LCALTA.10
2330 02:49:45.949680 # ok 357 event_spurious.LCALTA.10
2331 02:49:45.954717 # ok 358 get_value.LCALTA.9
2332 02:49:45.955225 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2333 02:49:45.960305 # ok 359 name.LCALTA.9
2334 02:49:45.960811 # ok 360 write_default.LCALTA.9
2335 02:49:45.965805 # ok 361 write_valid.LCALTA.9
2336 02:49:45.966303 # ok 362 write_invalid.LCALTA.9
2337 02:49:45.971391 # ok 363 event_missing.LCALTA.9
2338 02:49:45.971888 # ok 364 event_spurious.LCALTA.9
2339 02:49:45.976873 # ok 365 get_value.LCALTA.8
2340 02:49:45.977366 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2341 02:49:45.982438 # ok 366 name.LCALTA.8
2342 02:49:45.982938 # ok 367 write_default.LCALTA.8
2343 02:49:45.988018 # ok 368 write_valid.LCALTA.8
2344 02:49:45.988527 # ok 369 write_invalid.LCALTA.8
2345 02:49:45.993530 # ok 370 event_missing.LCALTA.8
2346 02:49:45.994032 # ok 371 event_spurious.LCALTA.8
2347 02:49:45.999056 # ok 372 get_value.LCALTA.7
2348 02:49:45.999549 # # LCALTA.7 ACODEC Unmute Ramp Switch
2349 02:49:46.004621 # ok 373 name.LCALTA.7
2350 02:49:46.005120 # ok 374 write_default.LCALTA.7
2351 02:49:46.010154 # ok 375 write_valid.LCALTA.7
2352 02:49:46.010648 # ok 376 write_invalid.LCALTA.7
2353 02:49:46.015724 # ok 377 event_missing.LCALTA.7
2354 02:49:46.016254 # ok 378 event_spurious.LCALTA.7
2355 02:49:46.021279 # ok 379 get_value.LCALTA.6
2356 02:49:46.021777 # # LCALTA.6 ACODEC Mute Ramp Switch
2357 02:49:46.026789 # ok 380 name.LCALTA.6
2358 02:49:46.027293 # ok 381 write_default.LCALTA.6
2359 02:49:46.032397 # ok 382 write_valid.LCALTA.6
2360 02:49:46.032898 # ok 383 write_invalid.LCALTA.6
2361 02:49:46.037973 # ok 384 event_missing.LCALTA.6
2362 02:49:46.038486 # ok 385 event_spurious.LCALTA.6
2363 02:49:46.043470 # ok 386 get_value.LCALTA.5
2364 02:49:46.043961 # # LCALTA.5 ACODEC Volume Ramp Switch
2365 02:49:46.049002 # ok 387 name.LCALTA.5
2366 02:49:46.049507 # ok 388 write_default.LCALTA.5
2367 02:49:46.054534 # ok 389 write_valid.LCALTA.5
2368 02:49:46.055032 # ok 390 write_invalid.LCALTA.5
2369 02:49:46.060094 # ok 391 event_missing.LCALTA.5
2370 02:49:46.060592 # ok 392 event_spurious.LCALTA.5
2371 02:49:46.065651 # ok 393 get_value.LCALTA.4
2372 02:49:46.066148 # # LCALTA.4 ACODEC Ramp Rate
2373 02:49:46.071168 # ok 394 name.LCALTA.4
2374 02:49:46.071659 # ok 395 write_default.LCALTA.4
2375 02:49:46.076692 # ok 396 write_valid.LCALTA.4
2376 02:49:46.077184 # ok 397 write_invalid.LCALTA.4
2377 02:49:46.082263 # ok 398 event_missing.LCALTA.4
2378 02:49:46.082766 # ok 399 event_spurious.LCALTA.4
2379 02:49:46.087816 # ok 400 get_value.LCALTA.3
2380 02:49:46.088343 # # LCALTA.3 ACODEC Playback Volume
2381 02:49:46.093417 # ok 401 name.LCALTA.3
2382 02:49:46.093908 # ok 402 write_default.LCALTA.3
2383 02:49:46.098911 # ok 403 write_valid.LCALTA.3
2384 02:49:46.099402 # ok 404 write_invalid.LCALTA.3
2385 02:49:46.104460 # ok 405 event_missing.LCALTA.3
2386 02:49:46.104960 # ok 406 event_spurious.LCALTA.3
2387 02:49:46.109992 # ok 407 get_value.LCALTA.2
2388 02:49:46.110488 # # LCALTA.2 ACODEC Playback Switch
2389 02:49:46.115546 # ok 408 name.LCALTA.2
2390 02:49:46.116080 # ok 409 write_default.LCALTA.2
2391 02:49:46.121132 # ok 410 write_valid.LCALTA.2
2392 02:49:46.121638 # ok 411 write_invalid.LCALTA.2
2393 02:49:46.126687 # ok 412 event_missing.LCALTA.2
2394 02:49:46.127199 # ok 413 event_spurious.LCALTA.2
2395 02:49:46.132253 # ok 414 get_value.LCALTA.1
2396 02:49:46.132764 # # LCALTA.1 ACODEC Playback Channel Mode
2397 02:49:46.137745 # ok 415 name.LCALTA.1
2398 02:49:46.138246 # ok 416 write_default.LCALTA.1
2399 02:49:46.143300 # ok 417 write_valid.LCALTA.1
2400 02:49:46.143794 # ok 418 write_invalid.LCALTA.1
2401 02:49:46.148852 # ok 419 event_missing.LCALTA.1
2402 02:49:46.149348 # ok 420 event_spurious.LCALTA.1
2403 02:49:46.154425 # ok 421 get_value.LCALTA.0
2404 02:49:46.154916 # # LCALTA.0 TOACODEC Lane Select
2405 02:49:46.159908 # ok 422 name.LCALTA.0
2406 02:49:46.160434 # ok 423 write_default.LCALTA.0
2407 02:49:46.165487 # ok 424 write_valid.LCALTA.0
2408 02:49:46.165982 # ok 425 write_invalid.LCALTA.0
2409 02:49:46.171014 # ok 426 event_missing.LCALTA.0
2410 02:49:46.171502 # ok 427 event_spurious.LCALTA.0
2411 02:49:46.176566 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2412 02:49:46.182104 ok 1 selftests: alsa: mixer-test
2413 02:49:46.182604 # timeout set to 45
2414 02:49:46.183063 # selftests: alsa: pcm-test
2415 02:49:46.187651 # TAP version 13
2416 02:49:46.188199 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2417 02:49:46.193214 # # LCALTA.0 - fe.dai-link-0 (*)
2418 02:49:46.193706 # # LCALTA.0 - fe.dai-link-1 (*)
2419 02:49:46.198743 # # LCALTA.0 - fe.dai-link-2 (*)
2420 02:49:46.199242 # # LCALTA.0 - fe.dai-link-3 (*)
2421 02:49:46.204292 # # LCALTA.0 - fe.dai-link-4 (*)
2422 02:49:46.204781 # # LCALTA.0 - fe.dai-link-5 (*)
2423 02:49:46.209845 # 1..42
2424 02:49:46.215430 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2425 02:49:46.215920 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2426 02:49:46.220930 # # snd_pcm_hw_params: Invalid argument
2427 02:49:46.226474 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2428 02:49:46.232057 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2429 02:49:46.232570 # # snd_pcm_hw_params: Invalid argument
2430 02:49:46.237550 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2431 02:49:46.243138 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2432 02:49:46.248666 # # snd_pcm_hw_params: Invalid argument
2433 02:49:46.254224 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2434 02:49:46.259756 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2435 02:49:46.260285 # # snd_pcm_hw_params: Invalid argument
2436 02:49:46.265294 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2437 02:49:46.270833 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2438 02:49:46.276432 # # snd_pcm_hw_params: Invalid argument
2439 02:49:46.281949 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2440 02:49:46.287489 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2441 02:49:46.288020 # # snd_pcm_hw_params: Invalid argument
2442 02:49:46.293043 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2443 02:49:46.298547 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2444 02:49:46.304146 # # snd_pcm_hw_params: Invalid argument
2445 02:49:46.309690 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2446 02:49:46.310182 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2447 02:49:46.315208 # # snd_pcm_hw_params: Invalid argument
2448 02:49:46.320772 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2449 02:49:46.326456 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2450 02:49:46.326956 # # snd_pcm_hw_params: Invalid argument
2451 02:49:46.337408 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2452 02:49:46.337920 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2453 02:49:46.342960 # # snd_pcm_hw_params: Invalid argument
2454 02:49:46.348471 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2455 02:49:46.354071 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2456 02:49:46.354571 # # snd_pcm_hw_params: Invalid argument
2457 02:49:46.359612 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2458 02:49:46.365153 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2459 02:49:46.370724 # # snd_pcm_hw_params: Invalid argument
2460 02:49:46.376329 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2461 02:49:46.381775 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2462 02:49:46.382272 # # snd_pcm_hw_params: Invalid argument
2463 02:49:46.387465 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2464 02:49:46.392886 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2465 02:49:46.398474 # # snd_pcm_hw_params: Invalid argument
2466 02:49:46.404007 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2467 02:49:46.409530 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2468 02:49:46.410042 # # snd_pcm_hw_params: Invalid argument
2469 02:49:46.415078 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2470 02:49:46.420608 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2471 02:49:46.426147 # # snd_pcm_hw_params: Invalid argument
2472 02:49:46.431695 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2473 02:49:46.432244 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2474 02:49:46.437306 # # snd_pcm_hw_params: Invalid argument
2475 02:49:46.442777 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2476 02:49:46.448482 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2477 02:49:46.453928 # # snd_pcm_hw_params: Invalid argument
2478 02:49:46.459473 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2479 02:49:46.460016 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2480 02:49:46.465012 # # snd_pcm_hw_params: Invalid argument
2481 02:49:46.470530 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2482 02:49:46.476105 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2483 02:49:46.481620 # # snd_pcm_hw_params: Invalid argument
2484 02:49:46.487141 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2485 02:49:46.487649 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2486 02:49:46.492702 # # snd_pcm_hw_params: Invalid argument
2487 02:49:46.498334 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2488 02:49:46.503841 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2489 02:49:46.504385 # # snd_pcm_hw_params: Invalid argument
2490 02:49:46.509487 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2491 02:49:46.514906 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2492 02:49:46.520489 # # snd_pcm_hw_params: Invalid argument
2493 02:49:46.526010 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2494 02:49:46.531563 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2495 02:49:46.532108 # # snd_pcm_hw_params: Invalid argument
2496 02:49:46.537119 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2497 02:49:46.542655 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2498 02:49:46.548246 # # snd_pcm_hw_params: Invalid argument
2499 02:49:46.553762 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2500 02:49:46.559360 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2501 02:49:46.559868 # # snd_pcm_hw_params: Invalid argument
2502 02:49:46.564853 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2503 02:49:46.570513 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2504 02:49:46.575959 # # snd_pcm_hw_params: Invalid argument
2505 02:49:46.581485 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2506 02:49:46.587037 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2507 02:49:46.587563 # # snd_pcm_hw_params: Invalid argument
2508 02:49:46.592607 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2509 02:49:46.598149 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2510 02:49:46.603688 # # snd_pcm_hw_params: Invalid argument
2511 02:49:46.609247 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2512 02:49:46.614754 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2513 02:49:46.615269 # # snd_pcm_hw_params: Invalid argument
2514 02:49:46.620365 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2515 02:49:46.625768 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2516 02:49:46.631370 # # snd_pcm_hw_params: Invalid argument
2517 02:49:46.636848 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2518 02:49:46.642376 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2519 02:49:46.642855 # # snd_pcm_hw_params: Invalid argument
2520 02:49:46.647944 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2521 02:49:46.653476 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2522 02:49:46.659012 # # snd_pcm_hw_params: Invalid argument
2523 02:49:46.664581 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2524 02:49:46.670150 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2525 02:49:46.670638 # # snd_pcm_hw_params: Invalid argument
2526 02:49:46.675665 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2527 02:49:46.681276 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2528 02:49:46.686783 # # snd_pcm_hw_params: Invalid argument
2529 02:49:46.692401 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2530 02:49:46.697860 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2531 02:49:46.698336 # # snd_pcm_hw_params: Invalid argument
2532 02:49:46.703404 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2533 02:49:46.708965 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2534 02:49:46.714504 # # snd_pcm_hw_params: Invalid argument
2535 02:49:46.720070 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2536 02:49:46.725593 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2537 02:49:46.726074 # # snd_pcm_hw_params: Invalid argument
2538 02:49:46.731163 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2539 02:49:46.736692 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2540 02:49:46.742270 # # snd_pcm_hw_params: Invalid argument
2541 02:49:46.747786 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2542 02:49:46.753413 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2543 02:49:46.753899 # # snd_pcm_hw_params: Invalid argument
2544 02:49:46.758863 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2545 02:49:46.764414 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2546 02:49:46.769961 # # snd_pcm_hw_params: Invalid argument
2547 02:49:46.775525 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2548 02:49:46.781055 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2549 02:49:46.781530 # # snd_pcm_hw_params: Invalid argument
2550 02:49:46.786587 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2551 02:49:46.792213 ok 2 selftests: alsa: pcm-test
2552 02:49:46.792694 # timeout set to 45
2553 02:49:46.797692 # selftests: alsa: test-pcmtest-driver
2554 02:49:46.798170 # TAP version 13
2555 02:49:46.798621 # 1..5
2556 02:49:46.803271 # # Starting 5 tests from 1 test cases.
2557 02:49:46.803748 # # RUN pcmtest.playback ...
2558 02:49:46.808804 # # SKIP Can't read patterns. Probably, module isn't loaded
2559 02:49:46.814403 # # OK pcmtest.playback
2560 02:49:46.819891 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2561 02:49:46.825454 # # RUN pcmtest.capture ...
2562 02:49:46.830986 # # SKIP Can't read patterns. Probably, module isn't loaded
2563 02:49:46.836547 # # OK pcmtest.capture
2564 02:49:46.842068 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2565 02:49:46.847617 # # RUN pcmtest.ni_capture ...
2566 02:49:46.853184 # # SKIP Can't read patterns. Probably, module isn't loaded
2567 02:49:46.853673 # # OK pcmtest.ni_capture
2568 02:49:46.864300 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2569 02:49:46.864798 # # RUN pcmtest.ni_playback ...
2570 02:49:46.869815 # # SKIP Can't read patterns. Probably, module isn't loaded
2571 02:49:46.875424 # # OK pcmtest.ni_playback
2572 02:49:46.880914 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2573 02:49:46.886476 # # RUN pcmtest.reset_ioctl ...
2574 02:49:46.891976 # # SKIP Can't read patterns. Probably, module isn't loaded
2575 02:49:46.897546 # # OK pcmtest.reset_ioctl
2576 02:49:46.903064 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2577 02:49:46.908632 # # PASSED: 5 / 5 tests passed.
2578 02:49:46.914173 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2579 02:49:46.914654 ok 3 selftests: alsa: test-pcmtest-driver
2580 02:49:46.919715 # timeout set to 45
2581 02:49:46.920217 # selftests: alsa: utimer-test
2582 02:49:46.920668 # TAP version 13
2583 02:49:46.921116 # 1..2
2584 02:49:46.925286 # # Starting 2 tests from 2 test cases.
2585 02:49:46.930779 # # RUN global.wrong_timers_test ...
2586 02:49:46.936425 # # OK global.wrong_timers_test
2587 02:49:46.936911 # ok 1 global.wrong_timers_test
2588 02:49:46.941885 # # RUN timer_f.utimer ...
2589 02:49:46.947474 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2590 02:49:46.952992 # # utimer: Test terminated by assertion
2591 02:49:46.958575 # # FAIL timer_f.utimer
2592 02:49:46.959056 # not ok 2 timer_f.utimer
2593 02:49:46.964103 # # FAILED: 1 / 2 tests passed.
2594 02:49:46.971524 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2595 02:49:46.972043 not ok 4 selftests: alsa: utimer-test # exit=1
2596 02:49:47.478296 alsa_mixer-test_get_value_LCALTA_60 pass
2597 02:49:47.483741 alsa_mixer-test_name_LCALTA_60 pass
2598 02:49:47.484323 alsa_mixer-test_write_default_LCALTA_60 pass
2599 02:49:47.489323 alsa_mixer-test_write_valid_LCALTA_60 pass
2600 02:49:47.492764 alsa_mixer-test_write_invalid_LCALTA_60 pass
2601 02:49:47.498330 alsa_mixer-test_event_missing_LCALTA_60 pass
2602 02:49:47.503859 alsa_mixer-test_event_spurious_LCALTA_60 pass
2603 02:49:47.504369 alsa_mixer-test_get_value_LCALTA_59 pass
2604 02:49:47.509446 alsa_mixer-test_name_LCALTA_59 pass
2605 02:49:47.514951 alsa_mixer-test_write_default_LCALTA_59 pass
2606 02:49:47.515423 alsa_mixer-test_write_valid_LCALTA_59 pass
2607 02:49:47.520506 alsa_mixer-test_write_invalid_LCALTA_59 pass
2608 02:49:47.526049 alsa_mixer-test_event_missing_LCALTA_59 pass
2609 02:49:47.526521 alsa_mixer-test_event_spurious_LCALTA_59 pass
2610 02:49:47.531590 alsa_mixer-test_get_value_LCALTA_58 pass
2611 02:49:47.537127 alsa_mixer-test_name_LCALTA_58 pass
2612 02:49:47.537597 alsa_mixer-test_write_default_LCALTA_58 pass
2613 02:49:47.542680 alsa_mixer-test_write_valid_LCALTA_58 pass
2614 02:49:47.548219 alsa_mixer-test_write_invalid_LCALTA_58 pass
2615 02:49:47.553766 alsa_mixer-test_event_missing_LCALTA_58 pass
2616 02:49:47.554302 alsa_mixer-test_event_spurious_LCALTA_58 pass
2617 02:49:47.559342 alsa_mixer-test_get_value_LCALTA_57 pass
2618 02:49:47.564940 alsa_mixer-test_name_LCALTA_57 pass
2619 02:49:47.565430 alsa_mixer-test_write_default_LCALTA_57 pass
2620 02:49:47.570519 alsa_mixer-test_write_valid_LCALTA_57 pass
2621 02:49:47.576050 alsa_mixer-test_write_invalid_LCALTA_57 pass
2622 02:49:47.576540 alsa_mixer-test_event_missing_LCALTA_57 pass
2623 02:49:47.581581 alsa_mixer-test_event_spurious_LCALTA_57 pass
2624 02:49:47.587110 alsa_mixer-test_get_value_LCALTA_56 pass
2625 02:49:47.587596 alsa_mixer-test_name_LCALTA_56 pass
2626 02:49:47.592652 alsa_mixer-test_write_default_LCALTA_56 pass
2627 02:49:47.598212 alsa_mixer-test_write_valid_LCALTA_56 pass
2628 02:49:47.598693 alsa_mixer-test_write_invalid_LCALTA_56 pass
2629 02:49:47.603766 alsa_mixer-test_event_missing_LCALTA_56 pass
2630 02:49:47.609299 alsa_mixer-test_event_spurious_LCALTA_56 pass
2631 02:49:47.614830 alsa_mixer-test_get_value_LCALTA_55 pass
2632 02:49:47.615312 alsa_mixer-test_name_LCALTA_55 pass
2633 02:49:47.620381 alsa_mixer-test_write_default_LCALTA_55 pass
2634 02:49:47.625936 alsa_mixer-test_write_valid_LCALTA_55 pass
2635 02:49:47.626414 alsa_mixer-test_write_invalid_LCALTA_55 pass
2636 02:49:47.631508 alsa_mixer-test_event_missing_LCALTA_55 pass
2637 02:49:47.637037 alsa_mixer-test_event_spurious_LCALTA_55 pass
2638 02:49:47.637528 alsa_mixer-test_get_value_LCALTA_54 pass
2639 02:49:47.642587 alsa_mixer-test_name_LCALTA_54 pass
2640 02:49:47.648148 alsa_mixer-test_write_default_LCALTA_54 pass
2641 02:49:47.648632 alsa_mixer-test_write_valid_LCALTA_54 pass
2642 02:49:47.653656 alsa_mixer-test_write_invalid_LCALTA_54 pass
2643 02:49:47.659212 alsa_mixer-test_event_missing_LCALTA_54 pass
2644 02:49:47.664778 alsa_mixer-test_event_spurious_LCALTA_54 pass
2645 02:49:47.665259 alsa_mixer-test_get_value_LCALTA_53 pass
2646 02:49:47.670299 alsa_mixer-test_name_LCALTA_53 pass
2647 02:49:47.675863 alsa_mixer-test_write_default_LCALTA_53 pass
2648 02:49:47.676374 alsa_mixer-test_write_valid_LCALTA_53 pass
2649 02:49:47.681411 alsa_mixer-test_write_invalid_LCALTA_53 pass
2650 02:49:47.686935 alsa_mixer-test_event_missing_LCALTA_53 pass
2651 02:49:47.687414 alsa_mixer-test_event_spurious_LCALTA_53 pass
2652 02:49:47.692520 alsa_mixer-test_get_value_LCALTA_52 pass
2653 02:49:47.698044 alsa_mixer-test_name_LCALTA_52 pass
2654 02:49:47.698518 alsa_mixer-test_write_default_LCALTA_52 pass
2655 02:49:47.703590 alsa_mixer-test_write_valid_LCALTA_52 pass
2656 02:49:47.709130 alsa_mixer-test_write_invalid_LCALTA_52 pass
2657 02:49:47.709623 alsa_mixer-test_event_missing_LCALTA_52 pass
2658 02:49:47.714663 alsa_mixer-test_event_spurious_LCALTA_52 pass
2659 02:49:47.720233 alsa_mixer-test_get_value_LCALTA_51 pass
2660 02:49:47.720715 alsa_mixer-test_name_LCALTA_51 pass
2661 02:49:47.725781 alsa_mixer-test_write_default_LCALTA_51 pass
2662 02:49:47.731325 alsa_mixer-test_write_valid_LCALTA_51 pass
2663 02:49:47.736835 alsa_mixer-test_write_invalid_LCALTA_51 pass
2664 02:49:47.737309 alsa_mixer-test_event_missing_LCALTA_51 pass
2665 02:49:47.742384 alsa_mixer-test_event_spurious_LCALTA_51 pass
2666 02:49:47.747925 alsa_mixer-test_get_value_LCALTA_50 pass
2667 02:49:47.748429 alsa_mixer-test_name_LCALTA_50 pass
2668 02:49:47.753551 alsa_mixer-test_write_default_LCALTA_50 pass
2669 02:49:47.759061 alsa_mixer-test_write_valid_LCALTA_50 pass
2670 02:49:47.759537 alsa_mixer-test_write_invalid_LCALTA_50 pass
2671 02:49:47.764604 alsa_mixer-test_event_missing_LCALTA_50 pass
2672 02:49:47.770158 alsa_mixer-test_event_spurious_LCALTA_50 pass
2673 02:49:47.770636 alsa_mixer-test_get_value_LCALTA_49 pass
2674 02:49:47.775689 alsa_mixer-test_name_LCALTA_49 pass
2675 02:49:47.781225 alsa_mixer-test_write_default_LCALTA_49 pass
2676 02:49:47.781700 alsa_mixer-test_write_valid_LCALTA_49 pass
2677 02:49:47.786788 alsa_mixer-test_write_invalid_LCALTA_49 pass
2678 02:49:47.792340 alsa_mixer-test_event_missing_LCALTA_49 pass
2679 02:49:47.797876 alsa_mixer-test_event_spurious_LCALTA_49 pass
2680 02:49:47.798389 alsa_mixer-test_get_value_LCALTA_48 pass
2681 02:49:47.803409 alsa_mixer-test_name_LCALTA_48 pass
2682 02:49:47.808962 alsa_mixer-test_write_default_LCALTA_48 pass
2683 02:49:47.809447 alsa_mixer-test_write_valid_LCALTA_48 pass
2684 02:49:47.814524 alsa_mixer-test_write_invalid_LCALTA_48 pass
2685 02:49:47.820068 alsa_mixer-test_event_missing_LCALTA_48 pass
2686 02:49:47.820547 alsa_mixer-test_event_spurious_LCALTA_48 pass
2687 02:49:47.825594 alsa_mixer-test_get_value_LCALTA_47 pass
2688 02:49:47.831127 alsa_mixer-test_name_LCALTA_47 pass
2689 02:49:47.831598 alsa_mixer-test_write_default_LCALTA_47 pass
2690 02:49:47.836674 alsa_mixer-test_write_valid_LCALTA_47 pass
2691 02:49:47.842232 alsa_mixer-test_write_invalid_LCALTA_47 pass
2692 02:49:47.847797 alsa_mixer-test_event_missing_LCALTA_47 pass
2693 02:49:47.848483 alsa_mixer-test_event_spurious_LCALTA_47 pass
2694 02:49:47.853339 alsa_mixer-test_get_value_LCALTA_46 pass
2695 02:49:47.853821 alsa_mixer-test_name_LCALTA_46 pass
2696 02:49:47.859034 alsa_mixer-test_write_default_LCALTA_46 pass
2697 02:49:47.864438 alsa_mixer-test_write_valid_LCALTA_46 pass
2698 02:49:47.869995 alsa_mixer-test_write_invalid_LCALTA_46 pass
2699 02:49:47.870474 alsa_mixer-test_event_missing_LCALTA_46 pass
2700 02:49:47.875560 alsa_mixer-test_event_spurious_LCALTA_46 pass
2701 02:49:47.881062 alsa_mixer-test_get_value_LCALTA_45 pass
2702 02:49:47.881554 alsa_mixer-test_name_LCALTA_45 pass
2703 02:49:47.886621 alsa_mixer-test_write_default_LCALTA_45 pass
2704 02:49:47.892186 alsa_mixer-test_write_valid_LCALTA_45 pass
2705 02:49:47.892667 alsa_mixer-test_write_invalid_LCALTA_45 pass
2706 02:49:47.897703 alsa_mixer-test_event_missing_LCALTA_45 pass
2707 02:49:47.903264 alsa_mixer-test_event_spurious_LCALTA_45 pass
2708 02:49:47.908815 alsa_mixer-test_get_value_LCALTA_44 pass
2709 02:49:47.909300 alsa_mixer-test_name_LCALTA_44 pass
2710 02:49:47.914348 alsa_mixer-test_write_default_LCALTA_44 pass
2711 02:49:47.919925 alsa_mixer-test_write_valid_LCALTA_44 pass
2712 02:49:47.920448 alsa_mixer-test_write_invalid_LCALTA_44 pass
2713 02:49:47.925539 alsa_mixer-test_event_missing_LCALTA_44 pass
2714 02:49:47.931104 alsa_mixer-test_event_spurious_LCALTA_44 pass
2715 02:49:47.931591 alsa_mixer-test_get_value_LCALTA_43 pass
2716 02:49:47.936602 alsa_mixer-test_name_LCALTA_43 pass
2717 02:49:47.942088 alsa_mixer-test_write_default_LCALTA_43 pass
2718 02:49:47.942569 alsa_mixer-test_write_valid_LCALTA_43 pass
2719 02:49:47.947627 alsa_mixer-test_write_invalid_LCALTA_43 pass
2720 02:49:47.953207 alsa_mixer-test_event_missing_LCALTA_43 pass
2721 02:49:47.953689 alsa_mixer-test_event_spurious_LCALTA_43 pass
2722 02:49:47.958735 alsa_mixer-test_get_value_LCALTA_42 pass
2723 02:49:47.964275 alsa_mixer-test_name_LCALTA_42 pass
2724 02:49:47.964753 alsa_mixer-test_write_default_LCALTA_42 pass
2725 02:49:47.969834 alsa_mixer-test_write_valid_LCALTA_42 pass
2726 02:49:47.975376 alsa_mixer-test_write_invalid_LCALTA_42 pass
2727 02:49:47.980935 alsa_mixer-test_event_missing_LCALTA_42 pass
2728 02:49:47.981421 alsa_mixer-test_event_spurious_LCALTA_42 pass
2729 02:49:47.986562 alsa_mixer-test_get_value_LCALTA_41 pass
2730 02:49:47.992050 alsa_mixer-test_name_LCALTA_41 pass
2731 02:49:47.992534 alsa_mixer-test_write_default_LCALTA_41 pass
2732 02:49:47.997578 alsa_mixer-test_write_valid_LCALTA_41 pass
2733 02:49:48.003096 alsa_mixer-test_write_invalid_LCALTA_41 pass
2734 02:49:48.003571 alsa_mixer-test_event_missing_LCALTA_41 pass
2735 02:49:48.008652 alsa_mixer-test_event_spurious_LCALTA_41 pass
2736 02:49:48.014186 alsa_mixer-test_get_value_LCALTA_40 pass
2737 02:49:48.014670 alsa_mixer-test_name_LCALTA_40 pass
2738 02:49:48.019750 alsa_mixer-test_write_default_LCALTA_40 pass
2739 02:49:48.025286 alsa_mixer-test_write_valid_LCALTA_40 pass
2740 02:49:48.025766 alsa_mixer-test_write_invalid_LCALTA_40 pass
2741 02:49:48.030840 alsa_mixer-test_event_missing_LCALTA_40 pass
2742 02:49:48.036457 alsa_mixer-test_event_spurious_LCALTA_40 pass
2743 02:49:48.041935 alsa_mixer-test_get_value_LCALTA_39 pass
2744 02:49:48.042414 alsa_mixer-test_name_LCALTA_39 pass
2745 02:49:48.047585 alsa_mixer-test_write_default_LCALTA_39 pass
2746 02:49:48.053038 alsa_mixer-test_write_valid_LCALTA_39 pass
2747 02:49:48.053526 alsa_mixer-test_write_invalid_LCALTA_39 pass
2748 02:49:48.058578 alsa_mixer-test_event_missing_LCALTA_39 pass
2749 02:49:48.064106 alsa_mixer-test_event_spurious_LCALTA_39 pass
2750 02:49:48.064585 alsa_mixer-test_get_value_LCALTA_38 pass
2751 02:49:48.069645 alsa_mixer-test_name_LCALTA_38 pass
2752 02:49:48.075214 alsa_mixer-test_write_default_LCALTA_38 pass
2753 02:49:48.075691 alsa_mixer-test_write_valid_LCALTA_38 pass
2754 02:49:48.080736 alsa_mixer-test_write_invalid_LCALTA_38 pass
2755 02:49:48.086297 alsa_mixer-test_event_missing_LCALTA_38 pass
2756 02:49:48.091861 alsa_mixer-test_event_spurious_LCALTA_38 pass
2757 02:49:48.092377 alsa_mixer-test_get_value_LCALTA_37 pass
2758 02:49:48.097473 alsa_mixer-test_name_LCALTA_37 pass
2759 02:49:48.102945 alsa_mixer-test_write_default_LCALTA_37 pass
2760 02:49:48.103424 alsa_mixer-test_write_valid_LCALTA_37 pass
2761 02:49:48.108602 alsa_mixer-test_write_invalid_LCALTA_37 pass
2762 02:49:48.114024 alsa_mixer-test_event_missing_LCALTA_37 pass
2763 02:49:48.114500 alsa_mixer-test_event_spurious_LCALTA_37 pass
2764 02:49:48.119590 alsa_mixer-test_get_value_LCALTA_36 pass
2765 02:49:48.125137 alsa_mixer-test_name_LCALTA_36 pass
2766 02:49:48.125616 alsa_mixer-test_write_default_LCALTA_36 pass
2767 02:49:48.130668 alsa_mixer-test_write_valid_LCALTA_36 pass
2768 02:49:48.136232 alsa_mixer-test_write_invalid_LCALTA_36 pass
2769 02:49:48.136712 alsa_mixer-test_event_missing_LCALTA_36 pass
2770 02:49:48.141775 alsa_mixer-test_event_spurious_LCALTA_36 pass
2771 02:49:48.147328 alsa_mixer-test_get_value_LCALTA_35 pass
2772 02:49:48.147803 alsa_mixer-test_name_LCALTA_35 pass
2773 02:49:48.152870 alsa_mixer-test_write_default_LCALTA_35 pass
2774 02:49:48.158474 alsa_mixer-test_write_valid_LCALTA_35 pass
2775 02:49:48.163968 alsa_mixer-test_write_invalid_LCALTA_35 pass
2776 02:49:48.164475 alsa_mixer-test_event_missing_LCALTA_35 pass
2777 02:49:48.169607 alsa_mixer-test_event_spurious_LCALTA_35 pass
2778 02:49:48.175063 alsa_mixer-test_get_value_LCALTA_34 pass
2779 02:49:48.175543 alsa_mixer-test_name_LCALTA_34 pass
2780 02:49:48.180613 alsa_mixer-test_write_default_LCALTA_34 pass
2781 02:49:48.186134 alsa_mixer-test_write_valid_LCALTA_34 pass
2782 02:49:48.186628 alsa_mixer-test_write_invalid_LCALTA_34 pass
2783 02:49:48.191677 alsa_mixer-test_event_missing_LCALTA_34 pass
2784 02:49:48.197253 alsa_mixer-test_event_spurious_LCALTA_34 pass
2785 02:49:48.197739 alsa_mixer-test_get_value_LCALTA_33 pass
2786 02:49:48.202793 alsa_mixer-test_name_LCALTA_33 pass
2787 02:49:48.208333 alsa_mixer-test_write_default_LCALTA_33 pass
2788 02:49:48.208807 alsa_mixer-test_write_valid_LCALTA_33 pass
2789 02:49:48.213881 alsa_mixer-test_write_invalid_LCALTA_33 pass
2790 02:49:48.219487 alsa_mixer-test_event_missing_LCALTA_33 pass
2791 02:49:48.224997 alsa_mixer-test_event_spurious_LCALTA_33 pass
2792 02:49:48.225513 alsa_mixer-test_get_value_LCALTA_32 pass
2793 02:49:48.230610 alsa_mixer-test_name_LCALTA_32 pass
2794 02:49:48.236088 alsa_mixer-test_write_default_LCALTA_32 pass
2795 02:49:48.236579 alsa_mixer-test_write_valid_LCALTA_32 pass
2796 02:49:48.241605 alsa_mixer-test_write_invalid_LCALTA_32 pass
2797 02:49:48.247174 alsa_mixer-test_event_missing_LCALTA_32 pass
2798 02:49:48.247653 alsa_mixer-test_event_spurious_LCALTA_32 pass
2799 02:49:48.252714 alsa_mixer-test_get_value_LCALTA_31 pass
2800 02:49:48.258273 alsa_mixer-test_name_LCALTA_31 pass
2801 02:49:48.258753 alsa_mixer-test_write_default_LCALTA_31 pass
2802 02:49:48.263817 alsa_mixer-test_write_valid_LCALTA_31 pass
2803 02:49:48.269356 alsa_mixer-test_write_invalid_LCALTA_31 pass
2804 02:49:48.274878 alsa_mixer-test_event_missing_LCALTA_31 pass
2805 02:49:48.275355 alsa_mixer-test_event_spurious_LCALTA_31 pass
2806 02:49:48.280495 alsa_mixer-test_get_value_LCALTA_30 pass
2807 02:49:48.280979 alsa_mixer-test_name_LCALTA_30 pass
2808 02:49:48.286004 alsa_mixer-test_write_default_LCALTA_30 pass
2809 02:49:48.291629 alsa_mixer-test_write_valid_LCALTA_30 pass
2810 02:49:48.297085 alsa_mixer-test_write_invalid_LCALTA_30 pass
2811 02:49:48.297569 alsa_mixer-test_event_missing_LCALTA_30 pass
2812 02:49:48.302627 alsa_mixer-test_event_spurious_LCALTA_30 pass
2813 02:49:48.308218 alsa_mixer-test_get_value_LCALTA_29 pass
2814 02:49:48.308708 alsa_mixer-test_name_LCALTA_29 pass
2815 02:49:48.313722 alsa_mixer-test_write_default_LCALTA_29 pass
2816 02:49:48.319271 alsa_mixer-test_write_valid_LCALTA_29 pass
2817 02:49:48.319750 alsa_mixer-test_write_invalid_LCALTA_29 pass
2818 02:49:48.324816 alsa_mixer-test_event_missing_LCALTA_29 pass
2819 02:49:48.330369 alsa_mixer-test_event_spurious_LCALTA_29 pass
2820 02:49:48.335889 alsa_mixer-test_get_value_LCALTA_28 pass
2821 02:49:48.336423 alsa_mixer-test_name_LCALTA_28 pass
2822 02:49:48.341503 alsa_mixer-test_write_default_LCALTA_28 pass
2823 02:49:48.347003 alsa_mixer-test_write_valid_LCALTA_28 pass
2824 02:49:48.347482 alsa_mixer-test_write_invalid_LCALTA_28 pass
2825 02:49:48.352634 alsa_mixer-test_event_missing_LCALTA_28 pass
2826 02:49:48.358097 alsa_mixer-test_event_spurious_LCALTA_28 pass
2827 02:49:48.358576 alsa_mixer-test_get_value_LCALTA_27 pass
2828 02:49:48.363683 alsa_mixer-test_name_LCALTA_27 pass
2829 02:49:48.369192 alsa_mixer-test_write_default_LCALTA_27 pass
2830 02:49:48.369674 alsa_mixer-test_write_valid_LCALTA_27 pass
2831 02:49:48.374730 alsa_mixer-test_write_invalid_LCALTA_27 pass
2832 02:49:48.380290 alsa_mixer-test_event_missing_LCALTA_27 pass
2833 02:49:48.380761 alsa_mixer-test_event_spurious_LCALTA_27 pass
2834 02:49:48.385830 alsa_mixer-test_get_value_LCALTA_26 pass
2835 02:49:48.391389 alsa_mixer-test_name_LCALTA_26 pass
2836 02:49:48.391863 alsa_mixer-test_write_default_LCALTA_26 skip
2837 02:49:48.396926 alsa_mixer-test_write_valid_LCALTA_26 skip
2838 02:49:48.402506 alsa_mixer-test_write_invalid_LCALTA_26 skip
2839 02:49:48.408047 alsa_mixer-test_event_missing_LCALTA_26 pass
2840 02:49:48.408522 alsa_mixer-test_event_spurious_LCALTA_26 pass
2841 02:49:48.413641 alsa_mixer-test_get_value_LCALTA_25 pass
2842 02:49:48.419126 alsa_mixer-test_name_LCALTA_25 pass
2843 02:49:48.419598 alsa_mixer-test_write_default_LCALTA_25 pass
2844 02:49:48.424685 alsa_mixer-test_write_valid_LCALTA_25 skip
2845 02:49:48.430184 alsa_mixer-test_write_invalid_LCALTA_25 skip
2846 02:49:48.430659 alsa_mixer-test_event_missing_LCALTA_25 pass
2847 02:49:48.435731 alsa_mixer-test_event_spurious_LCALTA_25 pass
2848 02:49:48.441281 alsa_mixer-test_get_value_LCALTA_24 pass
2849 02:49:48.441758 alsa_mixer-test_name_LCALTA_24 pass
2850 02:49:48.446846 alsa_mixer-test_write_default_LCALTA_24 skip
2851 02:49:48.452399 alsa_mixer-test_write_valid_LCALTA_24 skip
2852 02:49:48.452885 alsa_mixer-test_write_invalid_LCALTA_24 skip
2853 02:49:48.457941 alsa_mixer-test_event_missing_LCALTA_24 pass
2854 02:49:48.463523 alsa_mixer-test_event_spurious_LCALTA_24 pass
2855 02:49:48.469031 alsa_mixer-test_get_value_LCALTA_23 pass
2856 02:49:48.469509 alsa_mixer-test_name_LCALTA_23 pass
2857 02:49:48.474625 alsa_mixer-test_write_default_LCALTA_23 skip
2858 02:49:48.480110 alsa_mixer-test_write_valid_LCALTA_23 skip
2859 02:49:48.480579 alsa_mixer-test_write_invalid_LCALTA_23 skip
2860 02:49:48.485694 alsa_mixer-test_event_missing_LCALTA_23 pass
2861 02:49:48.491193 alsa_mixer-test_event_spurious_LCALTA_23 pass
2862 02:49:48.491669 alsa_mixer-test_get_value_LCALTA_22 pass
2863 02:49:48.496775 alsa_mixer-test_name_LCALTA_22 pass
2864 02:49:48.502318 alsa_mixer-test_write_default_LCALTA_22 pass
2865 02:49:48.502797 alsa_mixer-test_write_valid_LCALTA_22 pass
2866 02:49:48.507860 alsa_mixer-test_write_invalid_LCALTA_22 pass
2867 02:49:48.513387 alsa_mixer-test_event_missing_LCALTA_22 pass
2868 02:49:48.518949 alsa_mixer-test_event_spurious_LCALTA_22 pass
2869 02:49:48.519423 alsa_mixer-test_get_value_LCALTA_21 pass
2870 02:49:48.524526 alsa_mixer-test_name_LCALTA_21 pass
2871 02:49:48.530049 alsa_mixer-test_write_default_LCALTA_21 pass
2872 02:49:48.530525 alsa_mixer-test_write_valid_LCALTA_21 pass
2873 02:49:48.535650 alsa_mixer-test_write_invalid_LCALTA_21 pass
2874 02:49:48.541147 alsa_mixer-test_event_missing_LCALTA_21 pass
2875 02:49:48.541629 alsa_mixer-test_event_spurious_LCALTA_21 pass
2876 02:49:48.546702 alsa_mixer-test_get_value_LCALTA_20 pass
2877 02:49:48.552236 alsa_mixer-test_name_LCALTA_20 pass
2878 02:49:48.552713 alsa_mixer-test_write_default_LCALTA_20 pass
2879 02:49:48.557780 alsa_mixer-test_write_valid_LCALTA_20 pass
2880 02:49:48.563307 alsa_mixer-test_write_invalid_LCALTA_20 pass
2881 02:49:48.563780 alsa_mixer-test_event_missing_LCALTA_20 pass
2882 02:49:48.568866 alsa_mixer-test_event_spurious_LCALTA_20 pass
2883 02:49:48.574429 alsa_mixer-test_get_value_LCALTA_19 pass
2884 02:49:48.574905 alsa_mixer-test_name_LCALTA_19 pass
2885 02:49:48.579964 alsa_mixer-test_write_default_LCALTA_19 pass
2886 02:49:48.585535 alsa_mixer-test_write_valid_LCALTA_19 pass
2887 02:49:48.591053 alsa_mixer-test_write_invalid_LCALTA_19 pass
2888 02:49:48.591535 alsa_mixer-test_event_missing_LCALTA_19 pass
2889 02:49:48.596668 alsa_mixer-test_event_spurious_LCALTA_19 pass
2890 02:49:48.602154 alsa_mixer-test_get_value_LCALTA_18 pass
2891 02:49:48.602632 alsa_mixer-test_name_LCALTA_18 pass
2892 02:49:48.607707 alsa_mixer-test_write_default_LCALTA_18 pass
2893 02:49:48.613240 alsa_mixer-test_write_valid_LCALTA_18 pass
2894 02:49:48.613741 alsa_mixer-test_write_invalid_LCALTA_18 pass
2895 02:49:48.618800 alsa_mixer-test_event_missing_LCALTA_18 pass
2896 02:49:48.624333 alsa_mixer-test_event_spurious_LCALTA_18 pass
2897 02:49:48.624806 alsa_mixer-test_get_value_LCALTA_17 pass
2898 02:49:48.629858 alsa_mixer-test_name_LCALTA_17 pass
2899 02:49:48.635441 alsa_mixer-test_write_default_LCALTA_17 pass
2900 02:49:48.635916 alsa_mixer-test_write_valid_LCALTA_17 pass
2901 02:49:48.640987 alsa_mixer-test_write_invalid_LCALTA_17 pass
2902 02:49:48.646544 alsa_mixer-test_event_missing_LCALTA_17 pass
2903 02:49:48.652084 alsa_mixer-test_event_spurious_LCALTA_17 pass
2904 02:49:48.652566 alsa_mixer-test_get_value_LCALTA_16 pass
2905 02:49:48.657666 alsa_mixer-test_name_LCALTA_16 pass
2906 02:49:48.663176 alsa_mixer-test_write_default_LCALTA_16 pass
2907 02:49:48.663651 alsa_mixer-test_write_valid_LCALTA_16 pass
2908 02:49:48.668716 alsa_mixer-test_write_invalid_LCALTA_16 pass
2909 02:49:48.674268 alsa_mixer-test_event_missing_LCALTA_16 pass
2910 02:49:48.674741 alsa_mixer-test_event_spurious_LCALTA_16 pass
2911 02:49:48.679804 alsa_mixer-test_get_value_LCALTA_15 pass
2912 02:49:48.685361 alsa_mixer-test_name_LCALTA_15 pass
2913 02:49:48.685836 alsa_mixer-test_write_default_LCALTA_15 pass
2914 02:49:48.690878 alsa_mixer-test_write_valid_LCALTA_15 pass
2915 02:49:48.696426 alsa_mixer-test_write_invalid_LCALTA_15 pass
2916 02:49:48.701997 alsa_mixer-test_event_missing_LCALTA_15 pass
2917 02:49:48.702471 alsa_mixer-test_event_spurious_LCALTA_15 pass
2918 02:49:48.707553 alsa_mixer-test_get_value_LCALTA_14 pass
2919 02:49:48.708069 alsa_mixer-test_name_LCALTA_14 pass
2920 02:49:48.713080 alsa_mixer-test_write_default_LCALTA_14 pass
2921 02:49:48.718678 alsa_mixer-test_write_valid_LCALTA_14 pass
2922 02:49:48.724204 alsa_mixer-test_write_invalid_LCALTA_14 pass
2923 02:49:48.724679 alsa_mixer-test_event_missing_LCALTA_14 pass
2924 02:49:48.729737 alsa_mixer-test_event_spurious_LCALTA_14 pass
2925 02:49:48.735272 alsa_mixer-test_get_value_LCALTA_13 pass
2926 02:49:48.735749 alsa_mixer-test_name_LCALTA_13 pass
2927 02:49:48.740801 alsa_mixer-test_write_default_LCALTA_13 pass
2928 02:49:48.746343 alsa_mixer-test_write_valid_LCALTA_13 pass
2929 02:49:48.746821 alsa_mixer-test_write_invalid_LCALTA_13 pass
2930 02:49:48.751869 alsa_mixer-test_event_missing_LCALTA_13 pass
2931 02:49:48.757457 alsa_mixer-test_event_spurious_LCALTA_13 pass
2932 02:49:48.763008 alsa_mixer-test_get_value_LCALTA_12 pass
2933 02:49:48.763481 alsa_mixer-test_name_LCALTA_12 pass
2934 02:49:48.768558 alsa_mixer-test_write_default_LCALTA_12 pass
2935 02:49:48.774096 alsa_mixer-test_write_valid_LCALTA_12 pass
2936 02:49:48.774572 alsa_mixer-test_write_invalid_LCALTA_12 pass
2937 02:49:48.779694 alsa_mixer-test_event_missing_LCALTA_12 pass
2938 02:49:48.785191 alsa_mixer-test_event_spurious_LCALTA_12 pass
2939 02:49:48.785687 alsa_mixer-test_get_value_LCALTA_11 pass
2940 02:49:48.790734 alsa_mixer-test_name_LCALTA_11 pass
2941 02:49:48.796293 alsa_mixer-test_write_default_LCALTA_11 pass
2942 02:49:48.796767 alsa_mixer-test_write_valid_LCALTA_11 pass
2943 02:49:48.801834 alsa_mixer-test_write_invalid_LCALTA_11 pass
2944 02:49:48.807371 alsa_mixer-test_event_missing_LCALTA_11 pass
2945 02:49:48.807844 alsa_mixer-test_event_spurious_LCALTA_11 pass
2946 02:49:48.812930 alsa_mixer-test_get_value_LCALTA_10 pass
2947 02:49:48.818470 alsa_mixer-test_name_LCALTA_10 pass
2948 02:49:48.818943 alsa_mixer-test_write_default_LCALTA_10 pass
2949 02:49:48.824054 alsa_mixer-test_write_valid_LCALTA_10 pass
2950 02:49:48.829567 alsa_mixer-test_write_invalid_LCALTA_10 pass
2951 02:49:48.835095 alsa_mixer-test_event_missing_LCALTA_10 pass
2952 02:49:48.835567 alsa_mixer-test_event_spurious_LCALTA_10 pass
2953 02:49:48.840695 alsa_mixer-test_get_value_LCALTA_9 pass
2954 02:49:48.846211 alsa_mixer-test_name_LCALTA_9 pass
2955 02:49:48.846687 alsa_mixer-test_write_default_LCALTA_9 pass
2956 02:49:48.851749 alsa_mixer-test_write_valid_LCALTA_9 pass
2957 02:49:48.857299 alsa_mixer-test_write_invalid_LCALTA_9 pass
2958 02:49:48.857778 alsa_mixer-test_event_missing_LCALTA_9 pass
2959 02:49:48.862856 alsa_mixer-test_event_spurious_LCALTA_9 pass
2960 02:49:48.868383 alsa_mixer-test_get_value_LCALTA_8 pass
2961 02:49:48.868860 alsa_mixer-test_name_LCALTA_8 pass
2962 02:49:48.873939 alsa_mixer-test_write_default_LCALTA_8 pass
2963 02:49:48.879487 alsa_mixer-test_write_valid_LCALTA_8 pass
2964 02:49:48.879959 alsa_mixer-test_write_invalid_LCALTA_8 pass
2965 02:49:48.885032 alsa_mixer-test_event_missing_LCALTA_8 pass
2966 02:49:48.890558 alsa_mixer-test_event_spurious_LCALTA_8 pass
2967 02:49:48.891028 alsa_mixer-test_get_value_LCALTA_7 pass
2968 02:49:48.896104 alsa_mixer-test_name_LCALTA_7 pass
2969 02:49:48.901711 alsa_mixer-test_write_default_LCALTA_7 pass
2970 02:49:48.902186 alsa_mixer-test_write_valid_LCALTA_7 pass
2971 02:49:48.907216 alsa_mixer-test_write_invalid_LCALTA_7 pass
2972 02:49:48.912770 alsa_mixer-test_event_missing_LCALTA_7 pass
2973 02:49:48.913255 alsa_mixer-test_event_spurious_LCALTA_7 pass
2974 02:49:48.918320 alsa_mixer-test_get_value_LCALTA_6 pass
2975 02:49:48.923854 alsa_mixer-test_name_LCALTA_6 pass
2976 02:49:48.924363 alsa_mixer-test_write_default_LCALTA_6 pass
2977 02:49:48.929392 alsa_mixer-test_write_valid_LCALTA_6 pass
2978 02:49:48.934948 alsa_mixer-test_write_invalid_LCALTA_6 pass
2979 02:49:48.935424 alsa_mixer-test_event_missing_LCALTA_6 pass
2980 02:49:48.940475 alsa_mixer-test_event_spurious_LCALTA_6 pass
2981 02:49:48.946018 alsa_mixer-test_get_value_LCALTA_5 pass
2982 02:49:48.946492 alsa_mixer-test_name_LCALTA_5 pass
2983 02:49:48.951587 alsa_mixer-test_write_default_LCALTA_5 pass
2984 02:49:48.957130 alsa_mixer-test_write_valid_LCALTA_5 pass
2985 02:49:48.957609 alsa_mixer-test_write_invalid_LCALTA_5 pass
2986 02:49:48.962727 alsa_mixer-test_event_missing_LCALTA_5 pass
2987 02:49:48.968235 alsa_mixer-test_event_spurious_LCALTA_5 pass
2988 02:49:48.968708 alsa_mixer-test_get_value_LCALTA_4 pass
2989 02:49:48.973754 alsa_mixer-test_name_LCALTA_4 pass
2990 02:49:48.979323 alsa_mixer-test_write_default_LCALTA_4 pass
2991 02:49:48.979793 alsa_mixer-test_write_valid_LCALTA_4 pass
2992 02:49:48.984932 alsa_mixer-test_write_invalid_LCALTA_4 pass
2993 02:49:48.990554 alsa_mixer-test_event_missing_LCALTA_4 pass
2994 02:49:48.996095 alsa_mixer-test_event_spurious_LCALTA_4 pass
2995 02:49:48.996591 alsa_mixer-test_get_value_LCALTA_3 pass
2996 02:49:49.001614 alsa_mixer-test_name_LCALTA_3 pass
2997 02:49:49.002106 alsa_mixer-test_write_default_LCALTA_3 pass
2998 02:49:49.007168 alsa_mixer-test_write_valid_LCALTA_3 pass
2999 02:49:49.012801 alsa_mixer-test_write_invalid_LCALTA_3 pass
3000 02:49:49.018258 alsa_mixer-test_event_missing_LCALTA_3 pass
3001 02:49:49.018754 alsa_mixer-test_event_spurious_LCALTA_3 pass
3002 02:49:49.023825 alsa_mixer-test_get_value_LCALTA_2 pass
3003 02:49:49.024345 alsa_mixer-test_name_LCALTA_2 pass
3004 02:49:49.029355 alsa_mixer-test_write_default_LCALTA_2 pass
3005 02:49:49.034878 alsa_mixer-test_write_valid_LCALTA_2 pass
3006 02:49:49.040439 alsa_mixer-test_write_invalid_LCALTA_2 pass
3007 02:49:49.040940 alsa_mixer-test_event_missing_LCALTA_2 pass
3008 02:49:49.045996 alsa_mixer-test_event_spurious_LCALTA_2 pass
3009 02:49:49.051525 alsa_mixer-test_get_value_LCALTA_1 pass
3010 02:49:49.052064 alsa_mixer-test_name_LCALTA_1 pass
3011 02:49:49.057090 alsa_mixer-test_write_default_LCALTA_1 pass
3012 02:49:49.062636 alsa_mixer-test_write_valid_LCALTA_1 pass
3013 02:49:49.063142 alsa_mixer-test_write_invalid_LCALTA_1 pass
3014 02:49:49.068218 alsa_mixer-test_event_missing_LCALTA_1 pass
3015 02:49:49.073836 alsa_mixer-test_event_spurious_LCALTA_1 pass
3016 02:49:49.074350 alsa_mixer-test_get_value_LCALTA_0 pass
3017 02:49:49.079272 alsa_mixer-test_name_LCALTA_0 pass
3018 02:49:49.084843 alsa_mixer-test_write_default_LCALTA_0 pass
3019 02:49:49.085350 alsa_mixer-test_write_valid_LCALTA_0 pass
3020 02:49:49.090383 alsa_mixer-test_write_invalid_LCALTA_0 pass
3021 02:49:49.095893 alsa_mixer-test_event_missing_LCALTA_0 pass
3022 02:49:49.096436 alsa_mixer-test_event_spurious_LCALTA_0 pass
3023 02:49:49.101472 alsa_mixer-test pass
3024 02:49:49.106995 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3025 02:49:49.107509 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3026 02:49:49.112530 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3027 02:49:49.118074 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3028 02:49:49.123610 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3029 02:49:49.129185 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3030 02:49:49.129703 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3031 02:49:49.134826 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3032 02:49:49.140303 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3033 02:49:49.145846 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3034 02:49:49.151383 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3035 02:49:49.156936 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3036 02:49:49.157460 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3037 02:49:49.162486 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3038 02:49:49.168052 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3039 02:49:49.173572 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3040 02:49:49.179106 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3041 02:49:49.184728 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3042 02:49:49.185246 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3043 02:49:49.190199 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3044 02:49:49.195860 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3045 02:49:49.201299 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3046 02:49:49.206834 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3047 02:49:49.212385 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3048 02:49:49.212900 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3049 02:49:49.217942 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3050 02:49:49.223461 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3051 02:49:49.229024 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3052 02:49:49.234577 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3053 02:49:49.240130 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3054 02:49:49.245735 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3055 02:49:49.246247 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3056 02:49:49.251221 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3057 02:49:49.256862 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3058 02:49:49.262315 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3059 02:49:49.267848 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3060 02:49:49.273415 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3061 02:49:49.273929 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3062 02:49:49.278953 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3063 02:49:49.284503 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3064 02:49:49.290044 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3065 02:49:49.295570 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3066 02:49:49.296107 alsa_pcm-test pass
3067 02:49:49.306694 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3068 02:49:49.312270 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3069 02:49:49.323272 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3070 02:49:49.328861 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3071 02:49:49.339904 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3072 02:49:49.340471 alsa_test-pcmtest-driver pass
3073 02:49:49.345504 alsa_utimer-test_global_wrong_timers_test pass
3074 02:49:49.351071 alsa_utimer-test_timer_f_utimer fail
3075 02:49:49.351585 alsa_utimer-test fail
3076 02:49:49.356621 + ../../utils/send-to-lava.sh ./output/result.txt
3077 02:49:49.362144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3078 02:49:49.363112 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3080 02:49:49.367778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3081 02:49:49.368592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3083 02:49:49.375550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3084 02:49:49.376358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3086 02:49:49.409784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3087 02:49:49.410597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3089 02:49:49.474781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3090 02:49:49.475586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3092 02:49:49.532249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3093 02:49:49.533121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3095 02:49:49.582184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3096 02:49:49.583021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3098 02:49:49.636498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3099 02:49:49.637323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3101 02:49:49.695383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3102 02:49:49.696211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3104 02:49:49.757529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3105 02:49:49.758367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3107 02:49:49.812113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3108 02:49:49.812936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3110 02:49:49.866452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3111 02:49:49.867272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3113 02:49:49.926911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3114 02:49:49.927738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3116 02:49:49.981548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3117 02:49:49.982372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3119 02:49:50.035272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3120 02:49:50.036110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3122 02:49:50.085995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3123 02:49:50.086803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3125 02:49:50.135552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3126 02:49:50.136395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3128 02:49:50.188559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3129 02:49:50.189365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3131 02:49:50.245687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3132 02:49:50.246491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3134 02:49:50.300447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3135 02:49:50.301227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3137 02:49:50.354722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3138 02:49:50.355519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3140 02:49:50.403818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3141 02:49:50.404642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3143 02:49:50.456891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3144 02:49:50.457683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3146 02:49:50.504592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3147 02:49:50.505379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3149 02:49:50.551787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3150 02:49:50.552616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3152 02:49:50.605425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3153 02:49:50.606205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3155 02:49:50.654061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3156 02:49:50.654847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3158 02:49:50.711539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3159 02:49:50.712351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3161 02:49:50.770208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3162 02:49:50.771013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3164 02:49:50.821547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3165 02:49:50.822333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3167 02:49:50.881541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3168 02:49:50.882324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3170 02:49:50.930997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3171 02:49:50.931794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3173 02:49:50.976693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3174 02:49:50.977487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3176 02:49:51.023223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3177 02:49:51.024049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3179 02:49:51.078028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3180 02:49:51.078833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3182 02:49:51.127256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3183 02:49:51.128097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3185 02:49:51.172295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3186 02:49:51.173152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3188 02:49:51.225111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3189 02:49:51.225930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3191 02:49:51.277433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3192 02:49:51.278242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3194 02:49:51.335494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3195 02:49:51.336351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3197 02:49:51.394346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3198 02:49:51.395128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3200 02:49:51.452490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3201 02:49:51.453305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3203 02:49:51.510586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3204 02:49:51.511455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3206 02:49:51.559648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3207 02:49:51.560504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3209 02:49:51.605751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3210 02:49:51.606593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3212 02:49:51.659580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3213 02:49:51.660443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3215 02:49:51.719466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3216 02:49:51.720307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3218 02:49:51.774676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3219 02:49:51.775490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3221 02:49:51.833040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3222 02:49:51.833851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3224 02:49:51.881013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3225 02:49:51.881858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3227 02:49:51.938773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3228 02:49:51.939590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3230 02:49:51.989978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3231 02:49:51.990792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3233 02:49:52.047869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3234 02:49:52.048706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3236 02:49:52.104982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3237 02:49:52.105781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3239 02:49:52.150896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3240 02:49:52.151691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3242 02:49:52.198459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3243 02:49:52.199286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3245 02:49:52.255332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3246 02:49:52.256194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3248 02:49:52.302502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3249 02:49:52.303376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3251 02:49:52.356376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3252 02:49:52.357232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3254 02:49:52.413086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3255 02:49:52.413940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3257 02:49:52.459685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3258 02:49:52.460575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3260 02:49:52.512291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3261 02:49:52.513132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3263 02:49:52.558081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3264 02:49:52.558914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3266 02:49:52.616980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3267 02:49:52.617823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3269 02:49:52.668531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3270 02:49:52.669392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3272 02:49:52.725052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3273 02:49:52.725904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3275 02:49:52.780583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3276 02:49:52.781471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3278 02:49:52.832623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3279 02:49:52.833523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3281 02:49:52.930262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3282 02:49:52.931209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3284 02:49:52.984656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3285 02:49:52.985558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3287 02:49:53.043232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3288 02:49:53.044100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3290 02:49:53.093948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3291 02:49:53.094797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3293 02:49:53.144959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3294 02:49:53.145788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3296 02:49:53.198826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3297 02:49:53.199615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3299 02:49:53.256218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3300 02:49:53.257054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3302 02:49:53.312611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3303 02:49:53.313451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3305 02:49:53.367597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3306 02:49:53.368588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3308 02:49:53.415463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3309 02:49:53.416344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3311 02:49:53.467236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3312 02:49:53.467867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3314 02:49:53.514048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3315 02:49:53.514872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3317 02:49:53.559798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3318 02:49:53.560655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3320 02:49:53.608182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3321 02:49:53.609008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3323 02:49:53.653926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3324 02:49:53.654750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3326 02:49:53.702294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3327 02:49:53.703149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3329 02:49:53.751289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3330 02:49:53.752235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3332 02:49:53.801535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3333 02:49:53.802364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3335 02:49:53.846246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3336 02:49:53.847091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3338 02:49:53.897859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3339 02:49:53.898664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3341 02:49:53.950881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3342 02:49:53.951825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3344 02:49:53.996292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3345 02:49:53.997219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3347 02:49:54.045696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3348 02:49:54.046389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3350 02:49:54.097347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3351 02:49:54.098248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3353 02:49:54.146848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3354 02:49:54.147810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3356 02:49:54.197040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3357 02:49:54.197890 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3359 02:49:54.254582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3360 02:49:54.255468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3362 02:49:54.306252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3363 02:49:54.307139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3365 02:49:54.353446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3366 02:49:54.354308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3368 02:49:54.407178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3369 02:49:54.408114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3371 02:49:54.463157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3372 02:49:54.464101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3374 02:49:54.518128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3375 02:49:54.519047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3377 02:49:54.564126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3378 02:49:54.565071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3380 02:49:54.611390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3381 02:49:54.612341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3383 02:49:54.663162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3384 02:49:54.664101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3386 02:49:54.721228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3387 02:49:54.722178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3389 02:49:54.775881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3390 02:49:54.776867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3392 02:49:54.827641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3393 02:49:54.828321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3395 02:49:54.879035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3396 02:49:54.879952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3398 02:49:54.938881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3399 02:49:54.939742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3401 02:49:54.993855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3402 02:49:54.994710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3404 02:49:55.048338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3405 02:49:55.049199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3407 02:49:55.100868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3408 02:49:55.101725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3410 02:49:55.157301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3411 02:49:55.158157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3413 02:49:55.215385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3414 02:49:55.216263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3416 02:49:55.274335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3417 02:49:55.275218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3419 02:49:55.332840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3420 02:49:55.333663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3422 02:49:55.384175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3423 02:49:55.384972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3425 02:49:55.437610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3426 02:49:55.438473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3428 02:49:55.487170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3429 02:49:55.488042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3431 02:49:55.538209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3432 02:49:55.539102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3434 02:49:55.592324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3435 02:49:55.593139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3437 02:49:55.653448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3438 02:49:55.654325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3440 02:49:55.705695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3441 02:49:55.706390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3443 02:49:55.763647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3444 02:49:55.764300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3446 02:49:55.820030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3447 02:49:55.820646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3449 02:49:55.868225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3450 02:49:55.868840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3452 02:49:55.924315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3453 02:49:55.925195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3455 02:49:55.983572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3456 02:49:55.984691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3458 02:49:56.029194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3459 02:49:56.030119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3461 02:49:56.083741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3462 02:49:56.084634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3464 02:49:56.136594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3465 02:49:56.137463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3467 02:49:56.195186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3468 02:49:56.196082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3470 02:49:56.252427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3471 02:49:56.253240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3473 02:49:56.314648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3474 02:49:56.315453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3476 02:49:56.358710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3477 02:49:56.359535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3479 02:49:56.410674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3480 02:49:56.411517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3482 02:49:56.465519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3483 02:49:56.466411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3485 02:49:56.517058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3486 02:49:56.517934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3488 02:49:56.575229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3489 02:49:56.576134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3491 02:49:56.633728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3492 02:49:56.634631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3494 02:49:56.688011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3495 02:49:56.688850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3497 02:49:56.740548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3498 02:49:56.741414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3500 02:49:56.786294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3501 02:49:56.787125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3503 02:49:56.834064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3504 02:49:56.834895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3506 02:49:56.891157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3507 02:49:56.892023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3509 02:49:56.939300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3510 02:49:56.940138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3512 02:49:56.993109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3513 02:49:56.993933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3515 02:49:57.048338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3516 02:49:57.049227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3518 02:49:57.099148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3519 02:49:57.100033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3521 02:49:57.146700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3522 02:49:57.147552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3524 02:49:57.193061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3525 02:49:57.193914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3527 02:49:57.238588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3528 02:49:57.239560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3530 02:49:57.296813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3531 02:49:57.297630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3533 02:49:57.343416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3534 02:49:57.344218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3536 02:49:57.389282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3537 02:49:57.390079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3539 02:49:57.450462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3540 02:49:57.451290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3542 02:49:57.508099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3543 02:49:57.508920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3545 02:49:57.558099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3546 02:49:57.558919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3548 02:49:57.885875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3549 02:49:57.886606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3550 02:49:57.887089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3551 02:49:57.887557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3552 02:49:57.888153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3553 02:49:57.888907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3555 02:49:57.890324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3557 02:49:57.891696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3559 02:49:57.893079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3561 02:49:57.894398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3563 02:49:57.896014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3564 02:49:57.896825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3566 02:49:57.929679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3567 02:49:57.930504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3569 02:49:57.988991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3570 02:49:57.989825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3572 02:49:58.055916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3573 02:49:58.057831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3575 02:49:58.127649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3576 02:49:58.128662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3578 02:49:58.230509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3579 02:49:58.231242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3581 02:49:58.374248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3582 02:49:58.375213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3584 02:49:58.434445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3585 02:49:58.435091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3587 02:49:58.487220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3588 02:49:58.488115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3590 02:49:58.542277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3591 02:49:58.543135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3593 02:49:58.598228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3594 02:49:58.599132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3596 02:49:58.660995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3597 02:49:58.661914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3599 02:49:58.716438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3600 02:49:58.717407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3602 02:49:58.764013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3603 02:49:58.764716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3605 02:49:58.817700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3606 02:49:58.818392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3608 02:49:58.870945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3609 02:49:58.871846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3611 02:49:58.931626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3612 02:49:58.932335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3614 02:49:58.979416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3615 02:49:58.980234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3617 02:49:59.040765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3618 02:49:59.041456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3620 02:49:59.119390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3621 02:49:59.120063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3623 02:49:59.181189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3624 02:49:59.181824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3626 02:49:59.236499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3627 02:49:59.237140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3629 02:49:59.316787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3630 02:49:59.317476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3632 02:49:59.405406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3633 02:49:59.406151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3635 02:49:59.481623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3636 02:49:59.482269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3638 02:49:59.535524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3639 02:49:59.536169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3641 02:49:59.589081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3642 02:49:59.589740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3644 02:49:59.643532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3645 02:49:59.644184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3647 02:49:59.700504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3648 02:49:59.701116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3650 02:49:59.754787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3651 02:49:59.755431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3653 02:49:59.805772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3654 02:49:59.806413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3656 02:49:59.862504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3657 02:49:59.863123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3659 02:49:59.909707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3660 02:49:59.910297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3662 02:49:59.958686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3663 02:49:59.959320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3665 02:50:00.005991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3666 02:50:00.006590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3668 02:50:00.059891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3669 02:50:00.060523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3671 02:50:00.112613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3672 02:50:00.113223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3674 02:50:00.170039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3675 02:50:00.170640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3677 02:50:00.216946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3678 02:50:00.217562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3680 02:50:00.270840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3681 02:50:00.271464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3683 02:50:00.321686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3684 02:50:00.322293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3686 02:50:00.377687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3687 02:50:00.378295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3689 02:50:00.437233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3690 02:50:00.437864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3692 02:50:00.486487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3693 02:50:00.487102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3695 02:50:00.541646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3696 02:50:00.542246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3698 02:50:00.598842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3699 02:50:00.599462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3701 02:50:00.645111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3702 02:50:00.645929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3704 02:50:00.700227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3705 02:50:00.700892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3707 02:50:00.753618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3708 02:50:00.754279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3710 02:50:00.804696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3711 02:50:00.805364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3713 02:50:00.849938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3714 02:50:00.850577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3716 02:50:00.898182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3717 02:50:00.898846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3719 02:50:00.946711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3720 02:50:00.947343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3722 02:50:01.004300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3723 02:50:01.005183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3725 02:50:01.054681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3726 02:50:01.055545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3728 02:50:01.112233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3729 02:50:01.113070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3731 02:50:01.171752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3732 02:50:01.172670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3734 02:50:01.230604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3735 02:50:01.231428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3737 02:50:01.292701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3738 02:50:01.293824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3740 02:50:01.344252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3741 02:50:01.345275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3743 02:50:01.391832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3744 02:50:01.392935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3746 02:50:01.440263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3747 02:50:01.441266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3749 02:50:01.491933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3750 02:50:01.492932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3752 02:50:01.541396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3753 02:50:01.542434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3755 02:50:01.589335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3756 02:50:01.590271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3758 02:50:01.636201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3759 02:50:01.637101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3761 02:50:01.685719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3762 02:50:01.686575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3764 02:50:01.730975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3765 02:50:01.731855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3767 02:50:01.778486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3768 02:50:01.779318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3770 02:50:01.832253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3771 02:50:01.833086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3773 02:50:01.875409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3774 02:50:01.876167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3776 02:50:01.921547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3777 02:50:01.922444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3779 02:50:01.975629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3780 02:50:01.976336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3782 02:50:02.020618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3783 02:50:02.021205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3785 02:50:02.078952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3786 02:50:02.079559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3788 02:50:02.124181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3789 02:50:02.125062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3791 02:50:02.170836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3792 02:50:02.171646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3794 02:50:02.219367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3795 02:50:02.220196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3797 02:50:02.270361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3798 02:50:02.271181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3800 02:50:02.320488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3801 02:50:02.321346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3803 02:50:02.374433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3804 02:50:02.375265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3806 02:50:02.421174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3807 02:50:02.422034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3809 02:50:02.472037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3810 02:50:02.472897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3812 02:50:02.516636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3813 02:50:02.517490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3815 02:50:02.572277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3816 02:50:02.573159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3818 02:50:02.616256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3819 02:50:02.617122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3821 02:50:02.670064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3822 02:50:02.670939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3824 02:50:02.715232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3825 02:50:02.716104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3827 02:50:02.761858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3828 02:50:02.762720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3830 02:50:02.823369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3831 02:50:02.824276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3833 02:50:02.878085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3834 02:50:02.878937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3836 02:50:02.923668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3837 02:50:02.924300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3839 02:50:02.972334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3840 02:50:02.973157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3842 02:50:03.028047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3843 02:50:03.028941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3845 02:50:03.080098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3846 02:50:03.080940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3848 02:50:03.128269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3849 02:50:03.129127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3851 02:50:03.177172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3852 02:50:03.177943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3854 02:50:03.229292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3855 02:50:03.230043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3857 02:50:03.284361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3858 02:50:03.285148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3860 02:50:03.330988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3861 02:50:03.331734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3863 02:50:03.385563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3864 02:50:03.386293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3866 02:50:03.432704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3867 02:50:03.433485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3869 02:50:03.487159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3870 02:50:03.487919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3872 02:50:03.545986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3873 02:50:03.546586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3875 02:50:03.589204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3876 02:50:03.589786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3878 02:50:03.633305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3879 02:50:03.634123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3881 02:50:03.692921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3882 02:50:03.693803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3884 02:50:03.748464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3885 02:50:03.749217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3887 02:50:03.807429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3888 02:50:03.808279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3890 02:50:03.857242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3891 02:50:03.857842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3893 02:50:03.915448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3894 02:50:03.916057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3896 02:50:03.962189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3897 02:50:03.962812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3899 02:50:04.014442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3900 02:50:04.015030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3902 02:50:04.062052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3903 02:50:04.062663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3905 02:50:04.116999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3906 02:50:04.117985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3908 02:50:04.177997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3909 02:50:04.178998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3911 02:50:04.225499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3912 02:50:04.226435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3914 02:50:04.294511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3915 02:50:04.295436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3917 02:50:04.347623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3918 02:50:04.348578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3920 02:50:04.408188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3921 02:50:04.409122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3923 02:50:04.462803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3924 02:50:04.463716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3926 02:50:04.517638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3927 02:50:04.518532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3929 02:50:04.572841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3930 02:50:04.573725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3932 02:50:04.626913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3933 02:50:04.627827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3935 02:50:04.830248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3936 02:50:04.831155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3938 02:50:04.886347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3939 02:50:04.887197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3941 02:50:04.934232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3942 02:50:04.935071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3944 02:50:04.989798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3945 02:50:04.990378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3947 02:50:05.036067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3948 02:50:05.036631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3950 02:50:05.090722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3951 02:50:05.091650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3953 02:50:05.138586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3954 02:50:05.139689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3956 02:50:05.185132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3957 02:50:05.186136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3959 02:50:05.232012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3960 02:50:05.233034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3962 02:50:05.287616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3963 02:50:05.288617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3965 02:50:05.345658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3966 02:50:05.346648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3968 02:50:05.400377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3969 02:50:05.401395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3971 02:50:05.447724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3972 02:50:05.448701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3974 02:50:05.506802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3975 02:50:05.507727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3977 02:50:05.570724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3978 02:50:05.571662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3980 02:50:05.632804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3981 02:50:05.633696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3983 02:50:05.679967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3984 02:50:05.680909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3986 02:50:05.734063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3987 02:50:05.734998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3989 02:50:05.791026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3990 02:50:05.792012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3992 02:50:05.841314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3993 02:50:05.842181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3995 02:50:05.890579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3996 02:50:05.891519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3998 02:50:05.948026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3999 02:50:05.948920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
4001 02:50:05.996346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
4002 02:50:05.997183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
4004 02:50:06.051214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
4005 02:50:06.052138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
4007 02:50:06.101124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4008 02:50:06.102054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4010 02:50:06.156203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4011 02:50:06.157150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4013 02:50:06.201598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4014 02:50:06.202420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4016 02:50:06.261226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4017 02:50:06.262056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4019 02:50:06.313383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4020 02:50:06.314251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4022 02:50:06.359145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4023 02:50:06.360084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4025 02:50:06.408560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4026 02:50:06.409479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4028 02:50:06.459814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4029 02:50:06.460767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4031 02:50:06.512189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4032 02:50:06.513014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4034 02:50:06.557311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4035 02:50:06.558202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4037 02:50:06.601837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4038 02:50:06.602763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4040 02:50:06.652413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4041 02:50:06.653219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4043 02:50:06.704299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4044 02:50:06.705103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4046 02:50:06.758898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4047 02:50:06.759783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4049 02:50:06.813427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4050 02:50:06.814292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4052 02:50:06.859635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4053 02:50:06.860541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4055 02:50:06.905452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4056 02:50:06.906322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4058 02:50:06.959247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4059 02:50:06.960115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4061 02:50:07.015174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4062 02:50:07.016086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4064 02:50:07.071157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4065 02:50:07.071955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4067 02:50:07.120920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4068 02:50:07.121722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4070 02:50:07.170460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4071 02:50:07.171310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4073 02:50:07.225828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4074 02:50:07.226740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4076 02:50:07.274000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4077 02:50:07.274900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4079 02:50:07.329010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4080 02:50:07.329808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4082 02:50:07.382526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4083 02:50:07.383425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4085 02:50:07.436890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4086 02:50:07.437685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4088 02:50:07.487125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4089 02:50:07.487975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4091 02:50:07.531593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4092 02:50:07.532482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4094 02:50:07.585315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4095 02:50:07.586188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4097 02:50:07.631923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4098 02:50:07.632861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4100 02:50:07.684565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4101 02:50:07.685356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4103 02:50:07.731006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4104 02:50:07.731908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4106 02:50:07.779945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4107 02:50:07.780812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4109 02:50:07.828341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4110 02:50:07.829251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4112 02:50:07.881685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4113 02:50:07.882525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4115 02:50:07.935313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4116 02:50:07.936202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4118 02:50:07.992142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4119 02:50:07.993003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4121 02:50:08.048872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4122 02:50:08.049780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4124 02:50:08.104424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4125 02:50:08.105386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4127 02:50:08.151625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4128 02:50:08.152561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4130 02:50:08.220641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4131 02:50:08.221594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4133 02:50:08.270675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4134 02:50:08.271572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4136 02:50:08.334134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4137 02:50:08.334973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4139 02:50:08.385604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4140 02:50:08.386543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4142 02:50:08.437147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4143 02:50:08.438054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4145 02:50:08.492755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4146 02:50:08.493632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4148 02:50:08.548850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4149 02:50:08.549779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4151 02:50:08.609153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4152 02:50:08.610077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4154 02:50:08.665711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4155 02:50:08.666665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4157 02:50:08.723454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4158 02:50:08.724508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4160 02:50:08.775752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4161 02:50:08.776745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4163 02:50:08.826142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4164 02:50:08.827093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4166 02:50:08.879816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4167 02:50:08.880702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4169 02:50:08.936429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4170 02:50:08.937399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4172 02:50:09.001155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4173 02:50:09.002093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4175 02:50:09.058428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4176 02:50:09.059291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4178 02:50:09.108243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4179 02:50:09.109136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4181 02:50:09.157396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4182 02:50:09.158286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4184 02:50:09.203465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4185 02:50:09.204570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4187 02:50:09.258930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4188 02:50:09.259849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4190 02:50:09.312642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4191 02:50:09.313536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4193 02:50:09.359895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4194 02:50:09.360842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4196 02:50:09.416220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4197 02:50:09.417153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4199 02:50:09.466178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4200 02:50:09.467131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4202 02:50:09.521000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4203 02:50:09.521957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4205 02:50:09.569991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4206 02:50:09.570885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4208 02:50:09.624327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4209 02:50:09.625262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4211 02:50:09.680584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4212 02:50:09.681414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4214 02:50:09.727785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4215 02:50:09.728761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4217 02:50:09.773355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4218 02:50:09.774312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4220 02:50:09.822334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4221 02:50:09.823266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4223 02:50:09.879268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4224 02:50:09.880216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4226 02:50:09.925251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4227 02:50:09.926155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4229 02:50:09.977523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4230 02:50:09.978397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4232 02:50:10.024850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4233 02:50:10.025777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4235 02:50:10.081035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4236 02:50:10.081950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4238 02:50:10.126066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4239 02:50:10.127001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4241 02:50:10.182977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4242 02:50:10.183957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4244 02:50:10.235630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4245 02:50:10.236624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4247 02:50:10.284418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4248 02:50:10.285379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4250 02:50:10.340720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4251 02:50:10.341584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4253 02:50:10.392528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4254 02:50:10.393417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4256 02:50:10.443913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4257 02:50:10.444875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4259 02:50:10.501765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4260 02:50:10.502577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4262 02:50:10.555375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4263 02:50:10.556317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4265 02:50:10.609932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4266 02:50:10.610859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4268 02:50:10.664881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4269 02:50:10.665775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4271 02:50:10.719048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4272 02:50:10.719969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4274 02:50:10.779436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4275 02:50:10.780620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4277 02:50:10.829834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4278 02:50:10.830873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4280 02:50:10.884078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4281 02:50:10.885026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4283 02:50:10.942246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4284 02:50:10.943185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4286 02:50:11.003751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4287 02:50:11.004750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4289 02:50:11.054762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4290 02:50:11.055713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4292 02:50:11.103257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4293 02:50:11.104143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4295 02:50:11.162756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4296 02:50:11.163693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4298 02:50:11.216755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4299 02:50:11.217782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4301 02:50:11.274258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4302 02:50:11.275233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4304 02:50:11.342012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4305 02:50:11.342988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4307 02:50:11.399106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4308 02:50:11.400070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4310 02:50:11.443426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4311 02:50:11.444386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4313 02:50:11.499733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4314 02:50:11.500760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4316 02:50:11.556408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4317 02:50:11.557433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4319 02:50:11.611198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4320 02:50:11.612205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4322 02:50:11.659195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4323 02:50:11.660185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4325 02:50:11.715082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4326 02:50:11.716063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4328 02:50:11.769753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4329 02:50:11.770699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4331 02:50:11.834852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4332 02:50:11.835867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4334 02:50:11.890692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4335 02:50:11.891647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4337 02:50:11.957632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4338 02:50:11.958584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4340 02:50:12.010721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4341 02:50:12.011740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4343 02:50:12.063178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4344 02:50:12.064201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4346 02:50:12.116929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4347 02:50:12.117947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4349 02:50:12.169529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4350 02:50:12.170480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4352 02:50:12.226532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4353 02:50:12.227518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4355 02:50:12.282601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4356 02:50:12.283522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4358 02:50:12.338346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4359 02:50:12.339259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4361 02:50:12.385703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4363 02:50:12.388561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4364 02:50:12.439837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4365 02:50:12.440786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4367 02:50:12.494563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4368 02:50:12.495439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4370 02:50:12.547411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4371 02:50:12.548333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4373 02:50:12.594306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4374 02:50:12.595179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4376 02:50:12.642504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4377 02:50:12.643366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4379 02:50:12.698051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4380 02:50:12.698898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4382 02:50:12.748877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4383 02:50:12.749715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4385 02:50:12.798315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4386 02:50:12.799114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4388 02:50:12.845295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4389 02:50:12.846104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4391 02:50:12.897708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4392 02:50:12.898534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4394 02:50:12.956800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4395 02:50:12.957728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4397 02:50:13.012348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4398 02:50:13.013210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4400 02:50:13.069004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4401 02:50:13.069891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4403 02:50:13.121255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4404 02:50:13.122151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4406 02:50:13.179864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4407 02:50:13.180778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4409 02:50:13.231373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4410 02:50:13.232325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4412 02:50:13.288787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4413 02:50:13.289618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4415 02:50:13.344429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4416 02:50:13.345258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4418 02:50:13.406584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4419 02:50:13.407514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4421 02:50:13.467460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4422 02:50:13.468430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4424 02:50:13.530678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4425 02:50:13.531554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4427 02:50:13.583436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4428 02:50:13.584259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4430 02:50:13.629084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4431 02:50:13.629927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4433 02:50:13.689150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4434 02:50:13.690078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4436 02:50:13.744271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4437 02:50:13.745174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4439 02:50:13.797744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4440 02:50:13.798655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4442 02:50:13.845246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4443 02:50:13.846151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4445 02:50:13.890250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4446 02:50:13.891151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4448 02:50:13.943488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4449 02:50:13.944427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4451 02:50:13.999370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4452 02:50:14.000331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4454 02:50:14.061409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4455 02:50:14.062299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4457 02:50:14.110550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4458 02:50:14.111379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4460 02:50:14.169390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4461 02:50:14.170181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4463 02:50:14.228676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4464 02:50:14.229454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4466 02:50:14.285734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4467 02:50:14.286541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4469 02:50:14.336717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4470 02:50:14.337534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4472 02:50:14.395470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4473 02:50:14.396302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4475 02:50:14.452993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4476 02:50:14.453818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4478 02:50:14.511760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4479 02:50:14.512603 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4481 02:50:14.569498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4482 02:50:14.570302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4484 02:50:14.624913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4485 02:50:14.625732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4487 02:50:14.685863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4488 02:50:14.686648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4490 02:50:14.735375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4491 02:50:14.736161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4493 02:50:14.799347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4494 02:50:14.800132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4496 02:50:14.857356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4497 02:50:14.858166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4499 02:50:14.917369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4500 02:50:14.918176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4502 02:50:14.985407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4503 02:50:14.986225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4505 02:50:15.036201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4506 02:50:15.037023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4508 02:50:15.082380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4509 02:50:15.083180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4511 02:50:15.130700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4512 02:50:15.131331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4514 02:50:15.180869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4515 02:50:15.181478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4517 02:50:15.221733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4519 02:50:15.227033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4520 02:50:15.227334 + set +x
4521 02:50:15.233027 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 943521_1.6.2.4.5>
4522 02:50:15.233599 <LAVA_TEST_RUNNER EXIT>
4523 02:50:15.234304 Received signal: <ENDRUN> 1_kselftest-alsa 943521_1.6.2.4.5
4524 02:50:15.234790 Ending use of test pattern.
4525 02:50:15.235227 Ending test lava.1_kselftest-alsa (943521_1.6.2.4.5), duration 41.08
4527 02:50:15.236910 ok: lava_test_shell seems to have completed
4528 02:50:15.261383 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4529 02:50:15.263269 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4530 02:50:15.263858 end: 3 lava-test-retry (duration 00:00:42) [common]
4531 02:50:15.264526 start: 4 finalize (timeout 00:06:04) [common]
4532 02:50:15.265125 start: 4.1 power-off (timeout 00:00:30) [common]
4533 02:50:15.266118 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4534 02:50:15.301744 >> OK - accepted request
4535 02:50:15.303840 Returned 0 in 0 seconds
4536 02:50:15.404992 end: 4.1 power-off (duration 00:00:00) [common]
4538 02:50:15.406011 start: 4.2 read-feedback (timeout 00:06:04) [common]
4539 02:50:15.406753 Listened to connection for namespace 'common' for up to 1s
4540 02:50:16.407620 Finalising connection for namespace 'common'
4541 02:50:16.408205 Disconnecting from shell: Finalise
4542 02:50:16.408499 / #
4543 02:50:16.509184 end: 4.2 read-feedback (duration 00:00:01) [common]
4544 02:50:16.509733 end: 4 finalize (duration 00:00:01) [common]
4545 02:50:16.510137 Cleaning after the job
4546 02:50:16.510501 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/ramdisk
4547 02:50:16.518510 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/kernel
4548 02:50:16.544687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/dtb
4549 02:50:16.545693 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/nfsrootfs
4550 02:50:16.719157 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943521/tftp-deploy-ss4p34vt/modules
4551 02:50:16.740563 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/943521
4552 02:50:20.321818 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/943521
4553 02:50:20.322397 Job finished correctly