Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:58:00.450875 lava-dispatcher, installed at version: 2024.01
2 02:58:00.451680 start: 0 validate
3 02:58:00.452179 Start time: 2024-11-06 02:58:00.452148+00:00 (UTC)
4 02:58:00.452746 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:58:00.453295 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:58:00.493326 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:58:00.493875 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:58:00.526075 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:58:00.527023 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:58:00.559876 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:58:00.560413 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:58:00.591821 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:58:00.592370 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:58:00.634112 validate duration: 0.18
16 02:58:00.635595 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:58:00.636249 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:58:00.636855 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:58:00.637775 Not decompressing ramdisk as can be used compressed.
20 02:58:00.638536 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 02:58:00.639086 saving as /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/ramdisk/initrd.cpio.gz
22 02:58:00.639613 total size: 5628169 (5 MB)
23 02:58:00.678378 progress 0 % (0 MB)
24 02:58:00.686022 progress 5 % (0 MB)
25 02:58:00.693933 progress 10 % (0 MB)
26 02:58:00.700863 progress 15 % (0 MB)
27 02:58:00.708619 progress 20 % (1 MB)
28 02:58:00.713936 progress 25 % (1 MB)
29 02:58:00.717948 progress 30 % (1 MB)
30 02:58:00.722082 progress 35 % (1 MB)
31 02:58:00.725938 progress 40 % (2 MB)
32 02:58:00.729966 progress 45 % (2 MB)
33 02:58:00.733579 progress 50 % (2 MB)
34 02:58:00.737585 progress 55 % (2 MB)
35 02:58:00.741588 progress 60 % (3 MB)
36 02:58:00.745156 progress 65 % (3 MB)
37 02:58:00.749107 progress 70 % (3 MB)
38 02:58:00.752678 progress 75 % (4 MB)
39 02:58:00.756642 progress 80 % (4 MB)
40 02:58:00.760214 progress 85 % (4 MB)
41 02:58:00.764227 progress 90 % (4 MB)
42 02:58:00.768088 progress 95 % (5 MB)
43 02:58:00.771343 progress 100 % (5 MB)
44 02:58:00.772025 5 MB downloaded in 0.13 s (40.55 MB/s)
45 02:58:00.772582 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:58:00.773487 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:58:00.773779 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:58:00.774048 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:58:00.774529 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kernel/Image
51 02:58:00.774777 saving as /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/kernel/Image
52 02:58:00.774986 total size: 45779456 (43 MB)
53 02:58:00.775199 No compression specified
54 02:58:00.815413 progress 0 % (0 MB)
55 02:58:00.843903 progress 5 % (2 MB)
56 02:58:00.872273 progress 10 % (4 MB)
57 02:58:00.900621 progress 15 % (6 MB)
58 02:58:00.928788 progress 20 % (8 MB)
59 02:58:00.957310 progress 25 % (10 MB)
60 02:58:00.985285 progress 30 % (13 MB)
61 02:58:01.012864 progress 35 % (15 MB)
62 02:58:01.040984 progress 40 % (17 MB)
63 02:58:01.069336 progress 45 % (19 MB)
64 02:58:01.102698 progress 50 % (21 MB)
65 02:58:01.134154 progress 55 % (24 MB)
66 02:58:01.163099 progress 60 % (26 MB)
67 02:58:01.192589 progress 65 % (28 MB)
68 02:58:01.221400 progress 70 % (30 MB)
69 02:58:01.250949 progress 75 % (32 MB)
70 02:58:01.280004 progress 80 % (34 MB)
71 02:58:01.309230 progress 85 % (37 MB)
72 02:58:01.340925 progress 90 % (39 MB)
73 02:58:01.370609 progress 95 % (41 MB)
74 02:58:01.399865 progress 100 % (43 MB)
75 02:58:01.400462 43 MB downloaded in 0.63 s (69.80 MB/s)
76 02:58:01.400943 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:58:01.401772 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:58:01.402052 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:58:01.402322 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:58:01.402796 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:58:01.403075 saving as /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:58:01.403283 total size: 54703 (0 MB)
84 02:58:01.403495 No compression specified
85 02:58:01.442397 progress 59 % (0 MB)
86 02:58:01.443267 progress 100 % (0 MB)
87 02:58:01.443825 0 MB downloaded in 0.04 s (1.29 MB/s)
88 02:58:01.444400 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:58:01.445233 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:58:01.445498 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:58:01.445763 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:58:01.446232 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 02:58:01.446485 saving as /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/nfsrootfs/full.rootfs.tar
95 02:58:01.446689 total size: 120894716 (115 MB)
96 02:58:01.446900 Using unxz to decompress xz
97 02:58:01.485002 progress 0 % (0 MB)
98 02:58:02.316078 progress 5 % (5 MB)
99 02:58:03.164504 progress 10 % (11 MB)
100 02:58:03.966710 progress 15 % (17 MB)
101 02:58:04.721752 progress 20 % (23 MB)
102 02:58:05.320222 progress 25 % (28 MB)
103 02:58:06.150674 progress 30 % (34 MB)
104 02:58:06.943940 progress 35 % (40 MB)
105 02:58:07.292319 progress 40 % (46 MB)
106 02:58:07.662851 progress 45 % (51 MB)
107 02:58:08.387526 progress 50 % (57 MB)
108 02:58:09.275613 progress 55 % (63 MB)
109 02:58:10.063239 progress 60 % (69 MB)
110 02:58:10.818200 progress 65 % (74 MB)
111 02:58:11.595196 progress 70 % (80 MB)
112 02:58:12.420634 progress 75 % (86 MB)
113 02:58:13.208595 progress 80 % (92 MB)
114 02:58:13.972556 progress 85 % (98 MB)
115 02:58:14.825376 progress 90 % (103 MB)
116 02:58:15.607944 progress 95 % (109 MB)
117 02:58:16.455136 progress 100 % (115 MB)
118 02:58:16.467627 115 MB downloaded in 15.02 s (7.68 MB/s)
119 02:58:16.468557 end: 1.4.1 http-download (duration 00:00:15) [common]
121 02:58:16.470165 end: 1.4 download-retry (duration 00:00:15) [common]
122 02:58:16.470699 start: 1.5 download-retry (timeout 00:09:44) [common]
123 02:58:16.471225 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 02:58:16.472253 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/modules.tar.xz
125 02:58:16.472551 saving as /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/modules/modules.tar
126 02:58:16.472769 total size: 11613264 (11 MB)
127 02:58:16.472994 Using unxz to decompress xz
128 02:58:16.513226 progress 0 % (0 MB)
129 02:58:16.592096 progress 5 % (0 MB)
130 02:58:16.681207 progress 10 % (1 MB)
131 02:58:16.778778 progress 15 % (1 MB)
132 02:58:16.870709 progress 20 % (2 MB)
133 02:58:16.951570 progress 25 % (2 MB)
134 02:58:17.027496 progress 30 % (3 MB)
135 02:58:17.106162 progress 35 % (3 MB)
136 02:58:17.180017 progress 40 % (4 MB)
137 02:58:17.256194 progress 45 % (5 MB)
138 02:58:17.340320 progress 50 % (5 MB)
139 02:58:17.417555 progress 55 % (6 MB)
140 02:58:17.502605 progress 60 % (6 MB)
141 02:58:17.583894 progress 65 % (7 MB)
142 02:58:17.664406 progress 70 % (7 MB)
143 02:58:17.742894 progress 75 % (8 MB)
144 02:58:17.827885 progress 80 % (8 MB)
145 02:58:17.907617 progress 85 % (9 MB)
146 02:58:17.985775 progress 90 % (9 MB)
147 02:58:18.062860 progress 95 % (10 MB)
148 02:58:18.139266 progress 100 % (11 MB)
149 02:58:18.151152 11 MB downloaded in 1.68 s (6.60 MB/s)
150 02:58:18.151816 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:58:18.153458 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:58:18.154033 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 02:58:18.154603 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 02:58:35.246310 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/943561/extract-nfsrootfs-eqspemy7
156 02:58:35.246912 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 02:58:35.247201 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 02:58:35.247897 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca
159 02:58:35.248373 makedir: /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin
160 02:58:35.248699 makedir: /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/tests
161 02:58:35.249016 makedir: /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/results
162 02:58:35.249349 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-add-keys
163 02:58:35.249863 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-add-sources
164 02:58:35.250372 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-background-process-start
165 02:58:35.250862 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-background-process-stop
166 02:58:35.251384 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-common-functions
167 02:58:35.251876 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-echo-ipv4
168 02:58:35.252392 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-install-packages
169 02:58:35.252892 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-installed-packages
170 02:58:35.253375 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-os-build
171 02:58:35.253844 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-probe-channel
172 02:58:35.254311 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-probe-ip
173 02:58:35.254782 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-target-ip
174 02:58:35.255250 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-target-mac
175 02:58:35.255721 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-target-storage
176 02:58:35.256236 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-test-case
177 02:58:35.256742 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-test-event
178 02:58:35.257222 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-test-feedback
179 02:58:35.257688 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-test-raise
180 02:58:35.258146 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-test-reference
181 02:58:35.258608 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-test-runner
182 02:58:35.259098 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-test-set
183 02:58:35.259597 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-test-shell
184 02:58:35.260105 Updating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-add-keys (debian)
185 02:58:35.260632 Updating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-add-sources (debian)
186 02:58:35.261125 Updating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-install-packages (debian)
187 02:58:35.261608 Updating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-installed-packages (debian)
188 02:58:35.262090 Updating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/bin/lava-os-build (debian)
189 02:58:35.262515 Creating /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/environment
190 02:58:35.262890 LAVA metadata
191 02:58:35.263163 - LAVA_JOB_ID=943561
192 02:58:35.263378 - LAVA_DISPATCHER_IP=192.168.6.2
193 02:58:35.263745 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 02:58:35.264726 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 02:58:35.265042 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 02:58:35.265252 skipped lava-vland-overlay
197 02:58:35.265493 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 02:58:35.265746 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 02:58:35.265964 skipped lava-multinode-overlay
200 02:58:35.266204 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 02:58:35.266454 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 02:58:35.266700 Loading test definitions
203 02:58:35.266974 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 02:58:35.267193 Using /lava-943561 at stage 0
205 02:58:35.268307 uuid=943561_1.6.2.4.1 testdef=None
206 02:58:35.268612 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 02:58:35.268875 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 02:58:35.270415 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 02:58:35.271196 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 02:58:35.273175 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 02:58:35.273996 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 02:58:35.275786 runner path: /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/0/tests/0_timesync-off test_uuid 943561_1.6.2.4.1
215 02:58:35.276346 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 02:58:35.277151 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 02:58:35.277373 Using /lava-943561 at stage 0
219 02:58:35.277721 Fetching tests from https://github.com/kernelci/test-definitions.git
220 02:58:35.278005 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/0/tests/1_kselftest-rtc'
221 02:58:38.756674 Running '/usr/bin/git checkout kernelci.org
222 02:58:39.295709 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 02:58:39.297167 uuid=943561_1.6.2.4.5 testdef=None
224 02:58:39.297507 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 02:58:39.298251 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 02:58:39.301141 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 02:58:39.301966 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 02:58:39.305631 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 02:58:39.306477 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 02:58:39.310022 runner path: /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/0/tests/1_kselftest-rtc test_uuid 943561_1.6.2.4.5
234 02:58:39.310307 BOARD='meson-g12b-a311d-libretech-cc'
235 02:58:39.310511 BRANCH='clk'
236 02:58:39.310710 SKIPFILE='/dev/null'
237 02:58:39.310906 SKIP_INSTALL='True'
238 02:58:39.311101 TESTPROG_URL='http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 02:58:39.311300 TST_CASENAME=''
240 02:58:39.311495 TST_CMDFILES='rtc'
241 02:58:39.312058 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 02:58:39.312844 Creating lava-test-runner.conf files
244 02:58:39.313046 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/943561/lava-overlay-wa24skca/lava-943561/0 for stage 0
245 02:58:39.313390 - 0_timesync-off
246 02:58:39.313626 - 1_kselftest-rtc
247 02:58:39.313951 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 02:58:39.314231 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 02:59:03.069164 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 02:59:03.069607 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 02:59:03.069871 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 02:59:03.070142 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 02:59:03.070408 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 02:59:03.719821 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 02:59:03.720572 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 02:59:03.720880 extracting modules file /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943561/extract-nfsrootfs-eqspemy7
257 02:59:05.056497 extracting modules file /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943561/extract-overlay-ramdisk-qco2haiu/ramdisk
258 02:59:06.425079 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 02:59:06.425562 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 02:59:06.425856 [common] Applying overlay to NFS
261 02:59:06.426087 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943561/compress-overlay-td2quc5l/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/943561/extract-nfsrootfs-eqspemy7
262 02:59:09.118373 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 02:59:09.118841 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 02:59:09.119144 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 02:59:09.119405 Converting downloaded kernel to a uImage
266 02:59:09.119734 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/kernel/Image /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/kernel/uImage
267 02:59:09.618777 output: Image Name:
268 02:59:09.619206 output: Created: Wed Nov 6 02:59:09 2024
269 02:59:09.619433 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 02:59:09.619650 output: Data Size: 45779456 Bytes = 44706.50 KiB = 43.66 MiB
271 02:59:09.619861 output: Load Address: 01080000
272 02:59:09.620108 output: Entry Point: 01080000
273 02:59:09.620321 output:
274 02:59:09.620667 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 02:59:09.620947 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 02:59:09.621229 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 02:59:09.621497 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 02:59:09.621767 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 02:59:09.622036 Building ramdisk /var/lib/lava/dispatcher/tmp/943561/extract-overlay-ramdisk-qco2haiu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/943561/extract-overlay-ramdisk-qco2haiu/ramdisk
280 02:59:11.722907 >> 166772 blocks
281 02:59:19.454288 Adding RAMdisk u-boot header.
282 02:59:19.454930 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/943561/extract-overlay-ramdisk-qco2haiu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/943561/extract-overlay-ramdisk-qco2haiu/ramdisk.cpio.gz.uboot
283 02:59:19.762256 output: Image Name:
284 02:59:19.762645 output: Created: Wed Nov 6 02:59:19 2024
285 02:59:19.762865 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 02:59:19.763068 output: Data Size: 23427355 Bytes = 22878.28 KiB = 22.34 MiB
287 02:59:19.763269 output: Load Address: 00000000
288 02:59:19.763469 output: Entry Point: 00000000
289 02:59:19.763670 output:
290 02:59:19.764528 rename /var/lib/lava/dispatcher/tmp/943561/extract-overlay-ramdisk-qco2haiu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/ramdisk/ramdisk.cpio.gz.uboot
291 02:59:19.765263 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 02:59:19.765812 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 02:59:19.766338 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 02:59:19.766784 No LXC device requested
295 02:59:19.767279 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 02:59:19.767785 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 02:59:19.768328 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 02:59:19.768748 Checking files for TFTP limit of 4294967296 bytes.
299 02:59:19.771380 end: 1 tftp-deploy (duration 00:01:19) [common]
300 02:59:19.771964 start: 2 uboot-action (timeout 00:05:00) [common]
301 02:59:19.772529 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 02:59:19.773024 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 02:59:19.773527 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 02:59:19.774053 Using kernel file from prepare-kernel: 943561/tftp-deploy-emh637zb/kernel/uImage
305 02:59:19.774680 substitutions:
306 02:59:19.775087 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 02:59:19.775491 - {DTB_ADDR}: 0x01070000
308 02:59:19.775887 - {DTB}: 943561/tftp-deploy-emh637zb/dtb/meson-g12b-a311d-libretech-cc.dtb
309 02:59:19.776323 - {INITRD}: 943561/tftp-deploy-emh637zb/ramdisk/ramdisk.cpio.gz.uboot
310 02:59:19.776719 - {KERNEL_ADDR}: 0x01080000
311 02:59:19.777111 - {KERNEL}: 943561/tftp-deploy-emh637zb/kernel/uImage
312 02:59:19.777506 - {LAVA_MAC}: None
313 02:59:19.777935 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/943561/extract-nfsrootfs-eqspemy7
314 02:59:19.778331 - {NFS_SERVER_IP}: 192.168.6.2
315 02:59:19.778721 - {PRESEED_CONFIG}: None
316 02:59:19.779110 - {PRESEED_LOCAL}: None
317 02:59:19.779500 - {RAMDISK_ADDR}: 0x08000000
318 02:59:19.779886 - {RAMDISK}: 943561/tftp-deploy-emh637zb/ramdisk/ramdisk.cpio.gz.uboot
319 02:59:19.780307 - {ROOT_PART}: None
320 02:59:19.780697 - {ROOT}: None
321 02:59:19.781085 - {SERVER_IP}: 192.168.6.2
322 02:59:19.781469 - {TEE_ADDR}: 0x83000000
323 02:59:19.781849 - {TEE}: None
324 02:59:19.782234 Parsed boot commands:
325 02:59:19.782608 - setenv autoload no
326 02:59:19.782989 - setenv initrd_high 0xffffffff
327 02:59:19.783370 - setenv fdt_high 0xffffffff
328 02:59:19.783749 - dhcp
329 02:59:19.784158 - setenv serverip 192.168.6.2
330 02:59:19.784545 - tftpboot 0x01080000 943561/tftp-deploy-emh637zb/kernel/uImage
331 02:59:19.784936 - tftpboot 0x08000000 943561/tftp-deploy-emh637zb/ramdisk/ramdisk.cpio.gz.uboot
332 02:59:19.785321 - tftpboot 0x01070000 943561/tftp-deploy-emh637zb/dtb/meson-g12b-a311d-libretech-cc.dtb
333 02:59:19.785707 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943561/extract-nfsrootfs-eqspemy7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 02:59:19.786102 - bootm 0x01080000 0x08000000 0x01070000
335 02:59:19.786601 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 02:59:19.788104 start: 2.3 connect-device (timeout 00:05:00) [common]
338 02:59:19.788528 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 02:59:19.803337 Setting prompt string to ['lava-test: # ']
340 02:59:19.804877 end: 2.3 connect-device (duration 00:00:00) [common]
341 02:59:19.805492 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 02:59:19.806075 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 02:59:19.806733 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 02:59:19.807899 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 02:59:19.844565 >> OK - accepted request
346 02:59:19.846740 Returned 0 in 0 seconds
347 02:59:19.947889 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 02:59:19.949578 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 02:59:19.950126 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 02:59:19.950627 Setting prompt string to ['Hit any key to stop autoboot']
352 02:59:19.951075 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 02:59:19.952674 Trying 192.168.56.21...
354 02:59:19.953163 Connected to conserv1.
355 02:59:19.953569 Escape character is '^]'.
356 02:59:19.953983
357 02:59:19.954404 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 02:59:19.954830
359 02:59:30.902511 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 02:59:30.903102 bl2_stage_init 0x01
361 02:59:30.903710 bl2_stage_init 0x81
362 02:59:30.908208 hw id: 0x0000 - pwm id 0x01
363 02:59:30.908710 bl2_stage_init 0xc1
364 02:59:30.909122 bl2_stage_init 0x02
365 02:59:30.909513
366 02:59:30.913676 L0:00000000
367 02:59:30.914135 L1:20000703
368 02:59:30.914545 L2:00008067
369 02:59:30.914951 L3:14000000
370 02:59:30.916702 B2:00402000
371 02:59:30.917131 B1:e0f83180
372 02:59:30.917539
373 02:59:30.917927 TE: 58159
374 02:59:30.918315
375 02:59:30.927902 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 02:59:30.928360
377 02:59:30.928751 Board ID = 1
378 02:59:30.929133 Set A53 clk to 24M
379 02:59:30.929512 Set A73 clk to 24M
380 02:59:30.933311 Set clk81 to 24M
381 02:59:30.933733 A53 clk: 1200 MHz
382 02:59:30.934123 A73 clk: 1200 MHz
383 02:59:30.936966 CLK81: 166.6M
384 02:59:30.937380 smccc: 00012ab5
385 02:59:30.942385 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 02:59:30.948005 board id: 1
387 02:59:30.953126 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 02:59:30.963802 fw parse done
389 02:59:30.969744 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 02:59:31.012396 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 02:59:31.023359 PIEI prepare done
392 02:59:31.023779 fastboot data load
393 02:59:31.024206 fastboot data verify
394 02:59:31.029002 verify result: 266
395 02:59:31.034600 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 02:59:31.035024 LPDDR4 probe
397 02:59:31.035414 ddr clk to 1584MHz
398 02:59:31.042529 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 02:59:31.079801
400 02:59:31.080309 dmc_version 0001
401 02:59:31.086463 Check phy result
402 02:59:31.092354 INFO : End of CA training
403 02:59:31.092810 INFO : End of initialization
404 02:59:31.097914 INFO : Training has run successfully!
405 02:59:31.098342 Check phy result
406 02:59:31.103482 INFO : End of initialization
407 02:59:31.103900 INFO : End of read enable training
408 02:59:31.106896 INFO : End of fine write leveling
409 02:59:31.112459 INFO : End of Write leveling coarse delay
410 02:59:31.118000 INFO : Training has run successfully!
411 02:59:31.118419 Check phy result
412 02:59:31.118810 INFO : End of initialization
413 02:59:31.123634 INFO : End of read dq deskew training
414 02:59:31.129312 INFO : End of MPR read delay center optimization
415 02:59:31.129681 INFO : End of write delay center optimization
416 02:59:31.134928 INFO : End of read delay center optimization
417 02:59:31.140461 INFO : End of max read latency training
418 02:59:31.141059 INFO : Training has run successfully!
419 02:59:31.146074 1D training succeed
420 02:59:31.152028 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 02:59:31.199687 Check phy result
422 02:59:31.200142 INFO : End of initialization
423 02:59:31.221288 INFO : End of 2D read delay Voltage center optimization
424 02:59:31.241822 INFO : End of 2D read delay Voltage center optimization
425 02:59:31.293469 INFO : End of 2D write delay Voltage center optimization
426 02:59:31.342621 INFO : End of 2D write delay Voltage center optimization
427 02:59:31.348114 INFO : Training has run successfully!
428 02:59:31.348547
429 02:59:31.348774 channel==0
430 02:59:31.353695 RxClkDly_Margin_A0==78 ps 8
431 02:59:31.354115 TxDqDly_Margin_A0==98 ps 10
432 02:59:31.357077 RxClkDly_Margin_A1==88 ps 9
433 02:59:31.357431 TxDqDly_Margin_A1==98 ps 10
434 02:59:31.362851 TrainedVREFDQ_A0==74
435 02:59:31.363224 TrainedVREFDQ_A1==74
436 02:59:31.363444 VrefDac_Margin_A0==25
437 02:59:31.368619 DeviceVref_Margin_A0==40
438 02:59:31.368994 VrefDac_Margin_A1==25
439 02:59:31.374015 DeviceVref_Margin_A1==40
440 02:59:31.374487
441 02:59:31.374856
442 02:59:31.375212 channel==1
443 02:59:31.375560 RxClkDly_Margin_A0==98 ps 10
444 02:59:31.377376 TxDqDly_Margin_A0==98 ps 10
445 02:59:31.382708 RxClkDly_Margin_A1==88 ps 9
446 02:59:31.383061 TxDqDly_Margin_A1==88 ps 9
447 02:59:31.383327 TrainedVREFDQ_A0==77
448 02:59:31.388306 TrainedVREFDQ_A1==77
449 02:59:31.388669 VrefDac_Margin_A0==22
450 02:59:31.394129 DeviceVref_Margin_A0==37
451 02:59:31.394520 VrefDac_Margin_A1==24
452 02:59:31.394747 DeviceVref_Margin_A1==37
453 02:59:31.394961
454 02:59:31.403665 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 02:59:31.404376
456 02:59:31.429453 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 02:59:31.435054 2D training succeed
458 02:59:31.438532 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 02:59:31.443926 auto size-- 65535DDR cs0 size: 2048MB
460 02:59:31.444491 DDR cs1 size: 2048MB
461 02:59:31.449538 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 02:59:31.450075 cs0 DataBus test pass
463 02:59:31.450523 cs1 DataBus test pass
464 02:59:31.455170 cs0 AddrBus test pass
465 02:59:31.455706 cs1 AddrBus test pass
466 02:59:31.456198
467 02:59:31.460730 100bdlr_step_size ps== 420
468 02:59:31.461268 result report
469 02:59:31.461708 boot times 0Enable ddr reg access
470 02:59:31.470971 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 02:59:31.484337 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 02:59:32.056317 0.0;M3 CHK:0;cm4_sp_mode 0
473 02:59:32.056904 MVN_1=0x00000000
474 02:59:32.061852 MVN_2=0x00000000
475 02:59:32.067487 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 02:59:32.067970 OPS=0x10
477 02:59:32.068469 ring efuse init
478 02:59:32.068901 chipver efuse init
479 02:59:32.073111 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 02:59:32.078699 [0.018961 Inits done]
481 02:59:32.079175 secure task start!
482 02:59:32.079613 high task start!
483 02:59:32.083275 low task start!
484 02:59:32.083755 run into bl31
485 02:59:32.089936 NOTICE: BL31: v1.3(release):4fc40b1
486 02:59:32.097792 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 02:59:32.098276 NOTICE: BL31: G12A normal boot!
488 02:59:32.123093 NOTICE: BL31: BL33 decompress pass
489 02:59:32.128799 ERROR: Error initializing runtime service opteed_fast
490 02:59:33.361710
491 02:59:33.362354
492 02:59:33.370075 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 02:59:33.370572
494 02:59:33.371018 Model: Libre Computer AML-A311D-CC Alta
495 02:59:33.578497 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 02:59:33.601896 DRAM: 2 GiB (effective 3.8 GiB)
497 02:59:33.744870 Core: 408 devices, 31 uclasses, devicetree: separate
498 02:59:33.750729 WDT: Not starting watchdog@f0d0
499 02:59:33.782999 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 02:59:33.795446 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 02:59:33.800441 ** Bad device specification mmc 0 **
502 02:59:33.810758 Card did not respond to voltage select! : -110
503 02:59:33.818430 ** Bad device specification mmc 0 **
504 02:59:33.818901 Couldn't find partition mmc 0
505 02:59:33.826762 Card did not respond to voltage select! : -110
506 02:59:33.832272 ** Bad device specification mmc 0 **
507 02:59:33.832745 Couldn't find partition mmc 0
508 02:59:33.837356 Error: could not access storage.
509 02:59:35.102781 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 02:59:35.103373 bl2_stage_init 0x01
511 02:59:35.103817 bl2_stage_init 0x81
512 02:59:35.108433 hw id: 0x0000 - pwm id 0x01
513 02:59:35.108920 bl2_stage_init 0xc1
514 02:59:35.109340 bl2_stage_init 0x02
515 02:59:35.109748
516 02:59:35.113992 L0:00000000
517 02:59:35.114466 L1:20000703
518 02:59:35.114877 L2:00008067
519 02:59:35.115275 L3:14000000
520 02:59:35.116879 B2:00402000
521 02:59:35.117352 B1:e0f83180
522 02:59:35.117765
523 02:59:35.118167 TE: 58124
524 02:59:35.118565
525 02:59:35.128049 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 02:59:35.128535
527 02:59:35.128958 Board ID = 1
528 02:59:35.129360 Set A53 clk to 24M
529 02:59:35.129758 Set A73 clk to 24M
530 02:59:35.133697 Set clk81 to 24M
531 02:59:35.134174 A53 clk: 1200 MHz
532 02:59:35.134588 A73 clk: 1200 MHz
533 02:59:35.139366 CLK81: 166.6M
534 02:59:35.139839 smccc: 00012a92
535 02:59:35.144848 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 02:59:35.145330 board id: 1
537 02:59:35.153483 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 02:59:35.164130 fw parse done
539 02:59:35.170086 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 02:59:35.212749 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 02:59:35.223646 PIEI prepare done
542 02:59:35.224167 fastboot data load
543 02:59:35.224599 fastboot data verify
544 02:59:35.229341 verify result: 266
545 02:59:35.234878 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 02:59:35.235352 LPDDR4 probe
547 02:59:35.235765 ddr clk to 1584MHz
548 02:59:35.242869 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 02:59:35.280092
550 02:59:35.280578 dmc_version 0001
551 02:59:35.286831 Check phy result
552 02:59:35.292700 INFO : End of CA training
553 02:59:35.293170 INFO : End of initialization
554 02:59:35.298378 INFO : Training has run successfully!
555 02:59:35.298859 Check phy result
556 02:59:35.303892 INFO : End of initialization
557 02:59:35.304396 INFO : End of read enable training
558 02:59:35.309564 INFO : End of fine write leveling
559 02:59:35.315096 INFO : End of Write leveling coarse delay
560 02:59:35.315567 INFO : Training has run successfully!
561 02:59:35.315977 Check phy result
562 02:59:35.320667 INFO : End of initialization
563 02:59:35.321140 INFO : End of read dq deskew training
564 02:59:35.326346 INFO : End of MPR read delay center optimization
565 02:59:35.331862 INFO : End of write delay center optimization
566 02:59:35.337460 INFO : End of read delay center optimization
567 02:59:35.337932 INFO : End of max read latency training
568 02:59:35.343109 INFO : Training has run successfully!
569 02:59:35.343583 1D training succeed
570 02:59:35.352255 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 02:59:35.399872 Check phy result
572 02:59:35.400383 INFO : End of initialization
573 02:59:35.422328 INFO : End of 2D read delay Voltage center optimization
574 02:59:35.442455 INFO : End of 2D read delay Voltage center optimization
575 02:59:35.494338 INFO : End of 2D write delay Voltage center optimization
576 02:59:35.543582 INFO : End of 2D write delay Voltage center optimization
577 02:59:35.549166 INFO : Training has run successfully!
578 02:59:35.549644
579 02:59:35.550065 channel==0
580 02:59:35.554751 RxClkDly_Margin_A0==88 ps 9
581 02:59:35.555221 TxDqDly_Margin_A0==98 ps 10
582 02:59:35.560363 RxClkDly_Margin_A1==88 ps 9
583 02:59:35.560838 TxDqDly_Margin_A1==98 ps 10
584 02:59:35.561251 TrainedVREFDQ_A0==74
585 02:59:35.565945 TrainedVREFDQ_A1==74
586 02:59:35.566420 VrefDac_Margin_A0==25
587 02:59:35.566829 DeviceVref_Margin_A0==40
588 02:59:35.571438 VrefDac_Margin_A1==24
589 02:59:35.571713 DeviceVref_Margin_A1==40
590 02:59:35.571930
591 02:59:35.572170
592 02:59:35.577162 channel==1
593 02:59:35.577639 RxClkDly_Margin_A0==98 ps 10
594 02:59:35.578052 TxDqDly_Margin_A0==98 ps 10
595 02:59:35.582774 RxClkDly_Margin_A1==98 ps 10
596 02:59:35.583250 TxDqDly_Margin_A1==88 ps 9
597 02:59:35.588397 TrainedVREFDQ_A0==77
598 02:59:35.588873 TrainedVREFDQ_A1==77
599 02:59:35.589290 VrefDac_Margin_A0==22
600 02:59:35.593927 DeviceVref_Margin_A0==37
601 02:59:35.594397 VrefDac_Margin_A1==22
602 02:59:35.599575 DeviceVref_Margin_A1==37
603 02:59:35.600071
604 02:59:35.600495 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 02:59:35.605158
606 02:59:35.633088 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000018 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 02:59:35.633593 2D training succeed
608 02:59:35.638732 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 02:59:35.644381 auto size-- 65535DDR cs0 size: 2048MB
610 02:59:35.644852 DDR cs1 size: 2048MB
611 02:59:35.650008 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 02:59:35.650525 cs0 DataBus test pass
613 02:59:35.655558 cs1 DataBus test pass
614 02:59:35.656103 cs0 AddrBus test pass
615 02:59:35.656512 cs1 AddrBus test pass
616 02:59:35.656903
617 02:59:35.661122 100bdlr_step_size ps== 420
618 02:59:35.661603 result report
619 02:59:35.666705 boot times 0Enable ddr reg access
620 02:59:35.672184 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 02:59:35.685582 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 02:59:36.257600 0.0;M3 CHK:0;cm4_sp_mode 0
623 02:59:36.258108 MVN_1=0x00000000
624 02:59:36.263069 MVN_2=0x00000000
625 02:59:36.268829 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 02:59:36.269296 OPS=0x10
627 02:59:36.269692 ring efuse init
628 02:59:36.270075 chipver efuse init
629 02:59:36.274519 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 02:59:36.280074 [0.018961 Inits done]
631 02:59:36.280535 secure task start!
632 02:59:36.280919 high task start!
633 02:59:36.284654 low task start!
634 02:59:36.285111 run into bl31
635 02:59:36.291276 NOTICE: BL31: v1.3(release):4fc40b1
636 02:59:36.299082 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 02:59:36.299543 NOTICE: BL31: G12A normal boot!
638 02:59:36.324519 NOTICE: BL31: BL33 decompress pass
639 02:59:36.330108 ERROR: Error initializing runtime service opteed_fast
640 02:59:37.563115
641 02:59:37.563701
642 02:59:37.571552 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 02:59:37.572070
644 02:59:37.572498 Model: Libre Computer AML-A311D-CC Alta
645 02:59:37.780118 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 02:59:37.803331 DRAM: 2 GiB (effective 3.8 GiB)
647 02:59:37.946235 Core: 408 devices, 31 uclasses, devicetree: separate
648 02:59:37.952242 WDT: Not starting watchdog@f0d0
649 02:59:37.984466 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 02:59:37.996900 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 02:59:38.001995 ** Bad device specification mmc 0 **
652 02:59:38.012170 Card did not respond to voltage select! : -110
653 02:59:38.020011 ** Bad device specification mmc 0 **
654 02:59:38.020481 Couldn't find partition mmc 0
655 02:59:38.028113 Card did not respond to voltage select! : -110
656 02:59:38.033759 ** Bad device specification mmc 0 **
657 02:59:38.034221 Couldn't find partition mmc 0
658 02:59:38.038912 Error: could not access storage.
659 02:59:38.381246 Net: eth0: ethernet@ff3f0000
660 02:59:38.381739 starting USB...
661 02:59:38.633121 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 02:59:38.633622 Starting the controller
663 02:59:38.640180 USB XHCI 1.10
664 02:59:40.354959 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 02:59:40.355407 bl2_stage_init 0x01
666 02:59:40.355639 bl2_stage_init 0x81
667 02:59:40.360523 hw id: 0x0000 - pwm id 0x01
668 02:59:40.360939 bl2_stage_init 0xc1
669 02:59:40.361274 bl2_stage_init 0x02
670 02:59:40.361598
671 02:59:40.366202 L0:00000000
672 02:59:40.366485 L1:20000703
673 02:59:40.366698 L2:00008067
674 02:59:40.366902 L3:14000000
675 02:59:40.368986 B2:00402000
676 02:59:40.369373 B1:e0f83180
677 02:59:40.369701
678 02:59:40.370024 TE: 58124
679 02:59:40.370339
680 02:59:40.380160 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 02:59:40.380570
682 02:59:40.380900 Board ID = 1
683 02:59:40.381135 Set A53 clk to 24M
684 02:59:40.381344 Set A73 clk to 24M
685 02:59:40.385691 Set clk81 to 24M
686 02:59:40.386086 A53 clk: 1200 MHz
687 02:59:40.386412 A73 clk: 1200 MHz
688 02:59:40.389323 CLK81: 166.6M
689 02:59:40.389757 smccc: 00012a92
690 02:59:40.394747 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 02:59:40.400397 board id: 1
692 02:59:40.405686 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 02:59:40.416030 fw parse done
694 02:59:40.422056 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 02:59:40.464691 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 02:59:40.475717 PIEI prepare done
697 02:59:40.476225 fastboot data load
698 02:59:40.476653 fastboot data verify
699 02:59:40.481315 verify result: 266
700 02:59:40.486875 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 02:59:40.487373 LPDDR4 probe
702 02:59:40.487799 ddr clk to 1584MHz
703 02:59:40.494920 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 02:59:40.532223
705 02:59:40.532722 dmc_version 0001
706 02:59:40.538832 Check phy result
707 02:59:40.544670 INFO : End of CA training
708 02:59:40.545132 INFO : End of initialization
709 02:59:40.550431 INFO : Training has run successfully!
710 02:59:40.550894 Check phy result
711 02:59:40.555872 INFO : End of initialization
712 02:59:40.556381 INFO : End of read enable training
713 02:59:40.561494 INFO : End of fine write leveling
714 02:59:40.567060 INFO : End of Write leveling coarse delay
715 02:59:40.567521 INFO : Training has run successfully!
716 02:59:40.567934 Check phy result
717 02:59:40.572712 INFO : End of initialization
718 02:59:40.573174 INFO : End of read dq deskew training
719 02:59:40.578280 INFO : End of MPR read delay center optimization
720 02:59:40.583871 INFO : End of write delay center optimization
721 02:59:40.589481 INFO : End of read delay center optimization
722 02:59:40.589937 INFO : End of max read latency training
723 02:59:40.595079 INFO : Training has run successfully!
724 02:59:40.595534 1D training succeed
725 02:59:40.603324 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 02:59:40.651846 Check phy result
727 02:59:40.652342 INFO : End of initialization
728 02:59:40.673589 INFO : End of 2D read delay Voltage center optimization
729 02:59:40.693823 INFO : End of 2D read delay Voltage center optimization
730 02:59:40.745876 INFO : End of 2D write delay Voltage center optimization
731 02:59:40.795237 INFO : End of 2D write delay Voltage center optimization
732 02:59:40.800849 INFO : Training has run successfully!
733 02:59:40.801308
734 02:59:40.801721 channel==0
735 02:59:40.806446 RxClkDly_Margin_A0==88 ps 9
736 02:59:40.806906 TxDqDly_Margin_A0==98 ps 10
737 02:59:40.812154 RxClkDly_Margin_A1==88 ps 9
738 02:59:40.812613 TxDqDly_Margin_A1==98 ps 10
739 02:59:40.813026 TrainedVREFDQ_A0==74
740 02:59:40.817633 TrainedVREFDQ_A1==74
741 02:59:40.818092 VrefDac_Margin_A0==25
742 02:59:40.818498 DeviceVref_Margin_A0==40
743 02:59:40.823228 VrefDac_Margin_A1==25
744 02:59:40.823686 DeviceVref_Margin_A1==40
745 02:59:40.824133
746 02:59:40.824542
747 02:59:40.828853 channel==1
748 02:59:40.829315 RxClkDly_Margin_A0==98 ps 10
749 02:59:40.829724 TxDqDly_Margin_A0==98 ps 10
750 02:59:40.834429 RxClkDly_Margin_A1==98 ps 10
751 02:59:40.834886 TxDqDly_Margin_A1==88 ps 9
752 02:59:40.840052 TrainedVREFDQ_A0==77
753 02:59:40.840515 TrainedVREFDQ_A1==77
754 02:59:40.840930 VrefDac_Margin_A0==22
755 02:59:40.845630 DeviceVref_Margin_A0==37
756 02:59:40.846089 VrefDac_Margin_A1==22
757 02:59:40.851229 DeviceVref_Margin_A1==37
758 02:59:40.851695
759 02:59:40.852150 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 02:59:40.856823
761 02:59:40.884789 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 02:59:40.885300 2D training succeed
763 02:59:40.890453 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 02:59:40.896065 auto size-- 65535DDR cs0 size: 2048MB
765 02:59:40.896530 DDR cs1 size: 2048MB
766 02:59:40.901628 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 02:59:40.902089 cs0 DataBus test pass
768 02:59:40.907255 cs1 DataBus test pass
769 02:59:40.907712 cs0 AddrBus test pass
770 02:59:40.908158 cs1 AddrBus test pass
771 02:59:40.908562
772 02:59:40.912866 100bdlr_step_size ps== 420
773 02:59:40.913339 result report
774 02:59:40.918455 boot times 0Enable ddr reg access
775 02:59:40.923867 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 02:59:40.937330 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 02:59:41.510328 0.0;M3 CHK:0;cm4_sp_mode 0
778 02:59:41.510829 MVN_1=0x00000000
779 02:59:41.515873 MVN_2=0x00000000
780 02:59:41.521627 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 02:59:41.522118 OPS=0x10
782 02:59:41.522513 ring efuse init
783 02:59:41.522898 chipver efuse init
784 02:59:41.527248 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 02:59:41.532758 [0.018961 Inits done]
786 02:59:41.533203 secure task start!
787 02:59:41.533590 high task start!
788 02:59:41.537336 low task start!
789 02:59:41.537779 run into bl31
790 02:59:41.544005 NOTICE: BL31: v1.3(release):4fc40b1
791 02:59:41.553169 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 02:59:41.553614 NOTICE: BL31: G12A normal boot!
793 02:59:41.577242 NOTICE: BL31: BL33 decompress pass
794 02:59:41.582873 ERROR: Error initializing runtime service opteed_fast
795 02:59:42.815728
796 02:59:42.816354
797 02:59:42.823961 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 02:59:42.824464
799 02:59:42.824879 Model: Libre Computer AML-A311D-CC Alta
800 02:59:43.032543 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 02:59:43.055962 DRAM: 2 GiB (effective 3.8 GiB)
802 02:59:43.198910 Core: 408 devices, 31 uclasses, devicetree: separate
803 02:59:43.204835 WDT: Not starting watchdog@f0d0
804 02:59:43.237074 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 02:59:43.249500 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 02:59:43.254564 ** Bad device specification mmc 0 **
807 02:59:43.264837 Card did not respond to voltage select! : -110
808 02:59:43.272563 ** Bad device specification mmc 0 **
809 02:59:43.273020 Couldn't find partition mmc 0
810 02:59:43.280815 Card did not respond to voltage select! : -110
811 02:59:43.286374 ** Bad device specification mmc 0 **
812 02:59:43.286840 Couldn't find partition mmc 0
813 02:59:43.291436 Error: could not access storage.
814 02:59:43.634865 Net: eth0: ethernet@ff3f0000
815 02:59:43.635363 starting USB...
816 02:59:43.886657 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 02:59:43.887163 Starting the controller
818 02:59:43.892995 USB XHCI 1.10
819 02:59:46.053343 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 02:59:46.054159 bl2_stage_init 0x01
821 02:59:46.054769 bl2_stage_init 0x81
822 02:59:46.058910 hw id: 0x0000 - pwm id 0x01
823 02:59:46.059593 bl2_stage_init 0xc1
824 02:59:46.060294 bl2_stage_init 0x02
825 02:59:46.060940
826 02:59:46.064494 L0:00000000
827 02:59:46.065151 L1:20000703
828 02:59:46.065729 L2:00008067
829 02:59:46.066375 L3:14000000
830 02:59:46.067456 B2:00402000
831 02:59:46.068150 B1:e0f83180
832 02:59:46.068804
833 02:59:46.069443 TE: 58159
834 02:59:46.070017
835 02:59:46.078522 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 02:59:46.079240
837 02:59:46.079825 Board ID = 1
838 02:59:46.080491 Set A53 clk to 24M
839 02:59:46.081122 Set A73 clk to 24M
840 02:59:46.084119 Set clk81 to 24M
841 02:59:46.084767 A53 clk: 1200 MHz
842 02:59:46.085397 A73 clk: 1200 MHz
843 02:59:46.087634 CLK81: 166.6M
844 02:59:46.088335 smccc: 00012ab5
845 02:59:46.092982 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 02:59:46.098624 board id: 1
847 02:59:46.103228 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 02:59:46.114598 fw parse done
849 02:59:46.120145 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 02:59:46.162146 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 02:59:46.173951 PIEI prepare done
852 02:59:46.174390 fastboot data load
853 02:59:46.174798 fastboot data verify
854 02:59:46.179491 verify result: 266
855 02:59:46.185099 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 02:59:46.185531 LPDDR4 probe
857 02:59:46.185930 ddr clk to 1584MHz
858 02:59:46.192498 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 02:59:46.229455
860 02:59:46.229949 dmc_version 0001
861 02:59:46.236672 Check phy result
862 02:59:46.242868 INFO : End of CA training
863 02:59:46.243303 INFO : End of initialization
864 02:59:46.248483 INFO : Training has run successfully!
865 02:59:46.248920 Check phy result
866 02:59:46.254096 INFO : End of initialization
867 02:59:46.254531 INFO : End of read enable training
868 02:59:46.259699 INFO : End of fine write leveling
869 02:59:46.265277 INFO : End of Write leveling coarse delay
870 02:59:46.265725 INFO : Training has run successfully!
871 02:59:46.266132 Check phy result
872 02:59:46.270880 INFO : End of initialization
873 02:59:46.271326 INFO : End of read dq deskew training
874 02:59:46.276471 INFO : End of MPR read delay center optimization
875 02:59:46.282075 INFO : End of write delay center optimization
876 02:59:46.287802 INFO : End of read delay center optimization
877 02:59:46.288266 INFO : End of max read latency training
878 02:59:46.293278 INFO : Training has run successfully!
879 02:59:46.293707 1D training succeed
880 02:59:46.301537 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 02:59:46.350067 Check phy result
882 02:59:46.350534 INFO : End of initialization
883 02:59:46.370941 INFO : End of 2D read delay Voltage center optimization
884 02:59:46.391068 INFO : End of 2D read delay Voltage center optimization
885 02:59:46.443294 INFO : End of 2D write delay Voltage center optimization
886 02:59:46.492941 INFO : End of 2D write delay Voltage center optimization
887 02:59:46.498499 INFO : Training has run successfully!
888 02:59:46.498939
889 02:59:46.499337 channel==0
890 02:59:46.504075 RxClkDly_Margin_A0==88 ps 9
891 02:59:46.504535 TxDqDly_Margin_A0==98 ps 10
892 02:59:46.509683 RxClkDly_Margin_A1==88 ps 9
893 02:59:46.510112 TxDqDly_Margin_A1==98 ps 10
894 02:59:46.510525 TrainedVREFDQ_A0==74
895 02:59:46.515322 TrainedVREFDQ_A1==74
896 02:59:46.515755 VrefDac_Margin_A0==25
897 02:59:46.516179 DeviceVref_Margin_A0==40
898 02:59:46.520946 VrefDac_Margin_A1==25
899 02:59:46.521388 DeviceVref_Margin_A1==40
900 02:59:46.521777
901 02:59:46.522162
902 02:59:46.526476 channel==1
903 02:59:46.526907 RxClkDly_Margin_A0==98 ps 10
904 02:59:46.527296 TxDqDly_Margin_A0==98 ps 10
905 02:59:46.532097 RxClkDly_Margin_A1==88 ps 9
906 02:59:46.532527 TxDqDly_Margin_A1==88 ps 9
907 02:59:46.537686 TrainedVREFDQ_A0==77
908 02:59:46.538113 TrainedVREFDQ_A1==77
909 02:59:46.538499 VrefDac_Margin_A0==22
910 02:59:46.543298 DeviceVref_Margin_A0==37
911 02:59:46.543720 VrefDac_Margin_A1==24
912 02:59:46.548937 DeviceVref_Margin_A1==37
913 02:59:46.549370
914 02:59:46.549759 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 02:59:46.550144
916 02:59:46.582495 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 02:59:46.582979 2D training succeed
918 02:59:46.588096 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 02:59:46.593701 auto size-- 65535DDR cs0 size: 2048MB
920 02:59:46.594129 DDR cs1 size: 2048MB
921 02:59:46.599306 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 02:59:46.599734 cs0 DataBus test pass
923 02:59:46.604935 cs1 DataBus test pass
924 02:59:46.605361 cs0 AddrBus test pass
925 02:59:46.605745 cs1 AddrBus test pass
926 02:59:46.606128
927 02:59:46.610494 100bdlr_step_size ps== 420
928 02:59:46.610929 result report
929 02:59:46.616066 boot times 0Enable ddr reg access
930 02:59:46.620680 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 02:59:46.634492 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 02:59:47.206915 0.0;M3 CHK:0;cm4_sp_mode 0
933 02:59:47.207438 MVN_1=0x00000000
934 02:59:47.212364 MVN_2=0x00000000
935 02:59:47.218157 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 02:59:47.218609 OPS=0x10
937 02:59:47.219010 ring efuse init
938 02:59:47.219395 chipver efuse init
939 02:59:47.223744 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 02:59:47.229360 [0.018961 Inits done]
941 02:59:47.229806 secure task start!
942 02:59:47.230199 high task start!
943 02:59:47.233810 low task start!
944 02:59:47.234246 run into bl31
945 02:59:47.240576 NOTICE: BL31: v1.3(release):4fc40b1
946 02:59:47.248470 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 02:59:47.248909 NOTICE: BL31: G12A normal boot!
948 02:59:47.273732 NOTICE: BL31: BL33 decompress pass
949 02:59:47.278534 ERROR: Error initializing runtime service opteed_fast
950 02:59:48.512342
951 02:59:48.512905
952 02:59:48.520169 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 02:59:48.520617
954 02:59:48.521014 Model: Libre Computer AML-A311D-CC Alta
955 02:59:48.728406 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 02:59:48.751778 DRAM: 2 GiB (effective 3.8 GiB)
957 02:59:48.895541 Core: 408 devices, 31 uclasses, devicetree: separate
958 02:59:48.900755 WDT: Not starting watchdog@f0d0
959 02:59:48.933656 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 02:59:48.946200 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 02:59:48.951146 ** Bad device specification mmc 0 **
962 02:59:48.961424 Card did not respond to voltage select! : -110
963 02:59:48.969148 ** Bad device specification mmc 0 **
964 02:59:48.969590 Couldn't find partition mmc 0
965 02:59:48.977403 Card did not respond to voltage select! : -110
966 02:59:48.982960 ** Bad device specification mmc 0 **
967 02:59:48.983404 Couldn't find partition mmc 0
968 02:59:48.988022 Error: could not access storage.
969 02:59:49.330484 Net: eth0: ethernet@ff3f0000
970 02:59:49.330963 starting USB...
971 02:59:49.582390 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 02:59:49.582860 Starting the controller
973 02:59:49.589242 USB XHCI 1.10
974 02:59:51.453349 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 02:59:51.453890 bl2_stage_init 0x01
976 02:59:51.454419 bl2_stage_init 0x81
977 02:59:51.458682 hw id: 0x0000 - pwm id 0x01
978 02:59:51.459004 bl2_stage_init 0xc1
979 02:59:51.459270 bl2_stage_init 0x02
980 02:59:51.459534
981 02:59:51.464287 L0:00000000
982 02:59:51.464596 L1:20000703
983 02:59:51.464855 L2:00008067
984 02:59:51.465114 L3:14000000
985 02:59:51.467226 B2:00402000
986 02:59:51.467532 B1:e0f83180
987 02:59:51.467800
988 02:59:51.468088 TE: 58167
989 02:59:51.468362
990 02:59:51.478500 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 02:59:51.478814
992 02:59:51.479081 Board ID = 1
993 02:59:51.479351 Set A53 clk to 24M
994 02:59:51.479611 Set A73 clk to 24M
995 02:59:51.483934 Set clk81 to 24M
996 02:59:51.484261 A53 clk: 1200 MHz
997 02:59:51.484519 A73 clk: 1200 MHz
998 02:59:51.487471 CLK81: 166.6M
999 02:59:51.487773 smccc: 00012abd
1000 02:59:51.492920 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 02:59:51.498599 board id: 1
1002 02:59:51.503746 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 02:59:51.514583 fw parse done
1004 02:59:51.520465 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 02:59:51.562995 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 02:59:51.574016 PIEI prepare done
1007 02:59:51.574464 fastboot data load
1008 02:59:51.574837 fastboot data verify
1009 02:59:51.579557 verify result: 266
1010 02:59:51.585186 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 02:59:51.585592 LPDDR4 probe
1012 02:59:51.585961 ddr clk to 1584MHz
1013 02:59:51.593168 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 02:59:51.630458
1015 02:59:51.630912 dmc_version 0001
1016 02:59:51.637030 Check phy result
1017 02:59:51.642979 INFO : End of CA training
1018 02:59:51.643415 INFO : End of initialization
1019 02:59:51.648599 INFO : Training has run successfully!
1020 02:59:51.649063 Check phy result
1021 02:59:51.654199 INFO : End of initialization
1022 02:59:51.654736 INFO : End of read enable training
1023 02:59:51.659840 INFO : End of fine write leveling
1024 02:59:51.665393 INFO : End of Write leveling coarse delay
1025 02:59:51.665883 INFO : Training has run successfully!
1026 02:59:51.666288 Check phy result
1027 02:59:51.671028 INFO : End of initialization
1028 02:59:51.671526 INFO : End of read dq deskew training
1029 02:59:51.676645 INFO : End of MPR read delay center optimization
1030 02:59:51.682197 INFO : End of write delay center optimization
1031 02:59:51.687825 INFO : End of read delay center optimization
1032 02:59:51.688352 INFO : End of max read latency training
1033 02:59:51.693413 INFO : Training has run successfully!
1034 02:59:51.693914 1D training succeed
1035 02:59:51.701779 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 02:59:51.750177 Check phy result
1037 02:59:51.750681 INFO : End of initialization
1038 02:59:51.771927 INFO : End of 2D read delay Voltage center optimization
1039 02:59:51.791799 INFO : End of 2D read delay Voltage center optimization
1040 02:59:51.843935 INFO : End of 2D write delay Voltage center optimization
1041 02:59:51.893083 INFO : End of 2D write delay Voltage center optimization
1042 02:59:51.898726 INFO : Training has run successfully!
1043 02:59:51.899231
1044 02:59:51.899633 channel==0
1045 02:59:51.904226 RxClkDly_Margin_A0==88 ps 9
1046 02:59:51.904727 TxDqDly_Margin_A0==98 ps 10
1047 02:59:51.907567 RxClkDly_Margin_A1==88 ps 9
1048 02:59:51.908095 TxDqDly_Margin_A1==98 ps 10
1049 02:59:51.913216 TrainedVREFDQ_A0==74
1050 02:59:51.913707 TrainedVREFDQ_A1==74
1051 02:59:51.914104 VrefDac_Margin_A0==25
1052 02:59:51.918852 DeviceVref_Margin_A0==40
1053 02:59:51.919341 VrefDac_Margin_A1==25
1054 02:59:51.924417 DeviceVref_Margin_A1==40
1055 02:59:51.924923
1056 02:59:51.925321
1057 02:59:51.925710 channel==1
1058 02:59:51.926097 RxClkDly_Margin_A0==98 ps 10
1059 02:59:51.927714 TxDqDly_Margin_A0==88 ps 9
1060 02:59:51.933267 RxClkDly_Margin_A1==98 ps 10
1061 02:59:51.933771 TxDqDly_Margin_A1==88 ps 9
1062 02:59:51.934170 TrainedVREFDQ_A0==77
1063 02:59:51.938854 TrainedVREFDQ_A1==77
1064 02:59:51.939354 VrefDac_Margin_A0==22
1065 02:59:51.944505 DeviceVref_Margin_A0==37
1066 02:59:51.944999 VrefDac_Margin_A1==22
1067 02:59:51.945396 DeviceVref_Margin_A1==37
1068 02:59:51.945784
1069 02:59:51.950156 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 02:59:51.950661
1071 02:59:51.983615 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 02:59:51.984195 2D training succeed
1073 02:59:51.989321 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 02:59:51.994800 auto size-- 65535DDR cs0 size: 2048MB
1075 02:59:51.995345 DDR cs1 size: 2048MB
1076 02:59:52.000336 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 02:59:52.000835 cs0 DataBus test pass
1078 02:59:52.001313 cs1 DataBus test pass
1079 02:59:52.005986 cs0 AddrBus test pass
1080 02:59:52.006530 cs1 AddrBus test pass
1081 02:59:52.006999
1082 02:59:52.011597 100bdlr_step_size ps== 420
1083 02:59:52.012191 result report
1084 02:59:52.012635 boot times 0Enable ddr reg access
1085 02:59:52.021458 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 02:59:52.034201 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 02:59:52.606970 0.0;M3 CHK:0;cm4_sp_mode 0
1088 02:59:52.607614 MVN_1=0x00000000
1089 02:59:52.612353 MVN_2=0x00000000
1090 02:59:52.618133 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 02:59:52.618641 OPS=0x10
1092 02:59:52.619107 ring efuse init
1093 02:59:52.619560 chipver efuse init
1094 02:59:52.623731 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 02:59:52.629305 [0.018961 Inits done]
1096 02:59:52.629803 secure task start!
1097 02:59:52.630263 high task start!
1098 02:59:52.633884 low task start!
1099 02:59:52.634382 run into bl31
1100 02:59:52.640585 NOTICE: BL31: v1.3(release):4fc40b1
1101 02:59:52.648404 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 02:59:52.648975 NOTICE: BL31: G12A normal boot!
1103 02:59:52.673760 NOTICE: BL31: BL33 decompress pass
1104 02:59:52.678467 ERROR: Error initializing runtime service opteed_fast
1105 02:59:53.912288
1106 02:59:53.912897
1107 02:59:53.920726 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 02:59:53.921239
1109 02:59:53.921674 Model: Libre Computer AML-A311D-CC Alta
1110 02:59:54.129111 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 02:59:54.152511 DRAM: 2 GiB (effective 3.8 GiB)
1112 02:59:54.295505 Core: 408 devices, 31 uclasses, devicetree: separate
1113 02:59:54.301422 WDT: Not starting watchdog@f0d0
1114 02:59:54.333670 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 02:59:54.346081 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 02:59:54.351096 ** Bad device specification mmc 0 **
1117 02:59:54.361436 Card did not respond to voltage select! : -110
1118 02:59:54.369093 ** Bad device specification mmc 0 **
1119 02:59:54.369597 Couldn't find partition mmc 0
1120 02:59:54.377407 Card did not respond to voltage select! : -110
1121 02:59:54.383022 ** Bad device specification mmc 0 **
1122 02:59:54.383538 Couldn't find partition mmc 0
1123 02:59:54.388100 Error: could not access storage.
1124 02:59:54.730434 Net: eth0: ethernet@ff3f0000
1125 02:59:54.730980 starting USB...
1126 02:59:54.982212 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 02:59:54.982716 Starting the controller
1128 02:59:54.989227 USB XHCI 1.10
1129 02:59:56.543286 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 02:59:56.550725 scanning usb for storage devices... 0 Storage Device(s) found
1132 02:59:56.602419 Hit any key to stop autoboot: 1
1133 02:59:56.603287 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 02:59:56.603935 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 02:59:56.604465 Setting prompt string to ['=>']
1136 02:59:56.604938 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 02:59:56.609020 0
1138 02:59:56.609906 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 02:59:56.610390 Sending with 10 millisecond of delay
1141 02:59:57.745234 => setenv autoload no
1142 02:59:57.756033 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 02:59:57.760875 setenv autoload no
1144 02:59:57.761619 Sending with 10 millisecond of delay
1146 02:59:59.558634 => setenv initrd_high 0xffffffff
1147 02:59:59.569431 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 02:59:59.570329 setenv initrd_high 0xfffff fff
1149 02:59:59.571045 Sending with 10 millisecond of delay
1151 03:00:01.187860 => setenv fdt_high 0xffffffff
1152 03:00:01.198739 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1153 03:00:01.199691 setenv fdt_high 0xffffffff
1154 03:00:01.200475 Sending with 10 millisecond of delay
1156 03:00:01.492488 => dhcp
1157 03:00:01.503273 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 03:00:01.504234 dhcp
1159 03:00:01.504692 Speed: 1000, full duplex
1160 03:00:01.505109 BOOTP broadcast 1
1161 03:00:01.517830 DHCP client bound to address 192.168.6.27 (14 ms)
1162 03:00:01.518603 Sending with 10 millisecond of delay
1164 03:00:03.195642 => setenv serverip 192.168.6.2
1165 03:00:03.206548 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1166 03:00:03.207470 setenv serverip 192.168.6.2
1167 03:00:03.208178 Sending with 10 millisecond of delay
1169 03:00:06.932057 => tftpboot 0x01080000 943561/tftp-deploy-emh637zb/kernel/uImage
1170 03:00:06.942852 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 03:00:06.943670 tftpboot 0x01080000 943561/tftp-deploy-emh637zb/kernel/uImage
1172 03:00:06.944145 Speed: 1000, full duplex
1173 03:00:06.944565 Using ethernet@ff3f0000 device
1174 03:00:06.945293 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 03:00:06.950866 Filename '943561/tftp-deploy-emh637zb/kernel/uImage'.
1176 03:00:06.954765 Load address: 0x1080000
1177 03:00:10.014801 Loading: *################################################## 43.7 MiB
1178 03:00:10.015389 14.3 MiB/s
1179 03:00:10.015826 done
1180 03:00:10.019328 Bytes transferred = 45779520 (2ba8a40 hex)
1181 03:00:10.020140 Sending with 10 millisecond of delay
1183 03:00:14.708516 => tftpboot 0x08000000 943561/tftp-deploy-emh637zb/ramdisk/ramdisk.cpio.gz.uboot
1184 03:00:14.719288 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 03:00:14.720114 tftpboot 0x08000000 943561/tftp-deploy-emh637zb/ramdisk/ramdisk.cpio.gz.uboot
1186 03:00:14.720567 Speed: 1000, full duplex
1187 03:00:14.720984 Using ethernet@ff3f0000 device
1188 03:00:14.722143 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 03:00:14.730783 Filename '943561/tftp-deploy-emh637zb/ramdisk/ramdisk.cpio.gz.uboot'.
1190 03:00:14.731250 Load address: 0x8000000
1191 03:00:15.917500 Loading: *############## UDP wrong checksum 000000ff 00004b54
1192 03:00:15.957728 UDP wrong checksum 000000ff 0000e646
1193 03:00:20.866514 T ################ UDP wrong checksum 000000ff 00002d3d
1194 03:00:20.885118 # UDP wrong checksum 000000ff 0000b62f
1195 03:00:21.534905 ################## UDP wrong checksum 00000005 0000f3eb
1196 03:00:22.799146 UDP wrong checksum 000000ff 000040ca
1197 03:00:22.849368 UDP wrong checksum 000000ff 0000c6bc
1198 03:00:26.533373 T UDP wrong checksum 00000005 0000f3eb
1199 03:00:36.535350 T T UDP wrong checksum 00000005 0000f3eb
1200 03:00:48.340427 T T UDP wrong checksum 000000ff 000029dd
1201 03:00:48.501132 UDP wrong checksum 000000ff 0000b5cf
1202 03:00:50.771390 UDP wrong checksum 000000ff 00002a93
1203 03:00:50.842572 UDP wrong checksum 000000ff 0000bd85
1204 03:00:56.095809 T UDP wrong checksum 000000ff 0000bedd
1205 03:00:56.098282 UDP wrong checksum 000000ff 000049d0
1206 03:00:56.539424 T UDP wrong checksum 00000005 0000f3eb
1207 03:01:11.432274 T T UDP wrong checksum 000000ff 0000ca04
1208 03:01:11.481713 UDP wrong checksum 000000ff 00005af7
1209 03:01:11.542649
1210 03:01:11.543234 Retry count exceeded; starting again
1212 03:01:11.544683 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1215 03:01:11.546528 end: 2.4 uboot-commands (duration 00:01:52) [common]
1217 03:01:11.547845 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1219 03:01:11.550072 end: 2 uboot-action (duration 00:01:52) [common]
1221 03:01:11.552412 Cleaning after the job
1222 03:01:11.553242 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/ramdisk
1223 03:01:11.554741 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/kernel
1224 03:01:11.598799 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/dtb
1225 03:01:11.600248 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/nfsrootfs
1226 03:01:11.804947 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943561/tftp-deploy-emh637zb/modules
1227 03:01:11.825748 start: 4.1 power-off (timeout 00:00:30) [common]
1228 03:01:11.826442 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1229 03:01:11.857915 >> OK - accepted request
1230 03:01:11.860139 Returned 0 in 0 seconds
1231 03:01:11.960943 end: 4.1 power-off (duration 00:00:00) [common]
1233 03:01:11.961956 start: 4.2 read-feedback (timeout 00:10:00) [common]
1234 03:01:11.962609 Listened to connection for namespace 'common' for up to 1s
1235 03:01:12.963559 Finalising connection for namespace 'common'
1236 03:01:12.964098 Disconnecting from shell: Finalise
1237 03:01:12.964405 =>
1238 03:01:13.065079 end: 4.2 read-feedback (duration 00:00:01) [common]
1239 03:01:13.065528 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/943561
1240 03:01:16.483288 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/943561
1241 03:01:16.483891 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.