Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:43:59.545915 lava-dispatcher, installed at version: 2024.01
2 02:43:59.546701 start: 0 validate
3 02:43:59.547177 Start time: 2024-11-06 02:43:59.547147+00:00 (UTC)
4 02:43:59.547743 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:43:59.548331 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:43:59.587743 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:43:59.588379 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:43:59.617490 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:43:59.618170 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 02:43:59.653156 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:43:59.653645 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:43:59.688433 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:43:59.688943 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:43:59.726693 validate duration: 0.18
16 02:43:59.727543 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:43:59.727882 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:43:59.728255 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:43:59.728876 Not decompressing ramdisk as can be used compressed.
20 02:43:59.729415 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 02:43:59.729710 saving as /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/ramdisk/initrd.cpio.gz
22 02:43:59.729988 total size: 5628169 (5 MB)
23 02:43:59.769826 progress 0 % (0 MB)
24 02:43:59.774214 progress 5 % (0 MB)
25 02:43:59.778523 progress 10 % (0 MB)
26 02:43:59.782353 progress 15 % (0 MB)
27 02:43:59.786602 progress 20 % (1 MB)
28 02:43:59.790435 progress 25 % (1 MB)
29 02:43:59.794673 progress 30 % (1 MB)
30 02:43:59.798992 progress 35 % (1 MB)
31 02:43:59.802773 progress 40 % (2 MB)
32 02:43:59.806983 progress 45 % (2 MB)
33 02:43:59.810678 progress 50 % (2 MB)
34 02:43:59.814823 progress 55 % (2 MB)
35 02:43:59.819009 progress 60 % (3 MB)
36 02:43:59.822679 progress 65 % (3 MB)
37 02:43:59.826819 progress 70 % (3 MB)
38 02:43:59.830582 progress 75 % (4 MB)
39 02:43:59.834730 progress 80 % (4 MB)
40 02:43:59.838376 progress 85 % (4 MB)
41 02:43:59.842431 progress 90 % (4 MB)
42 02:43:59.846193 progress 95 % (5 MB)
43 02:43:59.849496 progress 100 % (5 MB)
44 02:43:59.850150 5 MB downloaded in 0.12 s (44.68 MB/s)
45 02:43:59.850676 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:43:59.851566 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:43:59.851856 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:43:59.852153 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:43:59.852636 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kernel/Image
51 02:43:59.852885 saving as /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/kernel/Image
52 02:43:59.853093 total size: 45779456 (43 MB)
53 02:43:59.853300 No compression specified
54 02:43:59.891861 progress 0 % (0 MB)
55 02:43:59.921220 progress 5 % (2 MB)
56 02:43:59.953124 progress 10 % (4 MB)
57 02:43:59.981913 progress 15 % (6 MB)
58 02:44:00.010825 progress 20 % (8 MB)
59 02:44:00.039713 progress 25 % (10 MB)
60 02:44:00.068821 progress 30 % (13 MB)
61 02:44:00.097470 progress 35 % (15 MB)
62 02:44:00.126458 progress 40 % (17 MB)
63 02:44:00.155494 progress 45 % (19 MB)
64 02:44:00.189580 progress 50 % (21 MB)
65 02:44:00.221237 progress 55 % (24 MB)
66 02:44:00.252685 progress 60 % (26 MB)
67 02:44:00.283502 progress 65 % (28 MB)
68 02:44:00.313887 progress 70 % (30 MB)
69 02:44:00.344067 progress 75 % (32 MB)
70 02:44:00.374895 progress 80 % (34 MB)
71 02:44:00.408189 progress 85 % (37 MB)
72 02:44:00.437913 progress 90 % (39 MB)
73 02:44:00.467178 progress 95 % (41 MB)
74 02:44:00.496463 progress 100 % (43 MB)
75 02:44:00.497056 43 MB downloaded in 0.64 s (67.80 MB/s)
76 02:44:00.497557 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:44:00.498391 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:44:00.498670 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:44:00.498937 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:44:00.501277 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 02:44:00.501682 saving as /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 02:44:00.501914 total size: 53209 (0 MB)
84 02:44:00.502142 No compression specified
85 02:44:00.544044 progress 61 % (0 MB)
86 02:44:00.544982 progress 100 % (0 MB)
87 02:44:00.545637 0 MB downloaded in 0.04 s (1.16 MB/s)
88 02:44:00.546195 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:44:00.547086 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:44:00.547397 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:44:00.547706 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:44:00.549486 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 02:44:00.549860 saving as /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/nfsrootfs/full.rootfs.tar
95 02:44:00.550107 total size: 120894716 (115 MB)
96 02:44:00.550342 Using unxz to decompress xz
97 02:44:00.594240 progress 0 % (0 MB)
98 02:44:01.589021 progress 5 % (5 MB)
99 02:44:02.434804 progress 10 % (11 MB)
100 02:44:03.232747 progress 15 % (17 MB)
101 02:44:03.971544 progress 20 % (23 MB)
102 02:44:04.562650 progress 25 % (28 MB)
103 02:44:05.389873 progress 30 % (34 MB)
104 02:44:06.179951 progress 35 % (40 MB)
105 02:44:06.528850 progress 40 % (46 MB)
106 02:44:06.900555 progress 45 % (51 MB)
107 02:44:07.620160 progress 50 % (57 MB)
108 02:44:08.506078 progress 55 % (63 MB)
109 02:44:09.288966 progress 60 % (69 MB)
110 02:44:10.046239 progress 65 % (74 MB)
111 02:44:10.830019 progress 70 % (80 MB)
112 02:44:11.659401 progress 75 % (86 MB)
113 02:44:12.457123 progress 80 % (92 MB)
114 02:44:13.222654 progress 85 % (98 MB)
115 02:44:14.080206 progress 90 % (103 MB)
116 02:44:14.876095 progress 95 % (109 MB)
117 02:44:15.806537 progress 100 % (115 MB)
118 02:44:15.819231 115 MB downloaded in 15.27 s (7.55 MB/s)
119 02:44:15.819917 end: 1.4.1 http-download (duration 00:00:15) [common]
121 02:44:15.821739 end: 1.4 download-retry (duration 00:00:15) [common]
122 02:44:15.822300 start: 1.5 download-retry (timeout 00:09:44) [common]
123 02:44:15.822843 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 02:44:15.824183 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/modules.tar.xz
125 02:44:15.824751 saving as /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/modules/modules.tar
126 02:44:15.825203 total size: 11613264 (11 MB)
127 02:44:15.825655 Using unxz to decompress xz
128 02:44:15.865330 progress 0 % (0 MB)
129 02:44:15.936011 progress 5 % (0 MB)
130 02:44:16.009722 progress 10 % (1 MB)
131 02:44:16.106055 progress 15 % (1 MB)
132 02:44:16.202299 progress 20 % (2 MB)
133 02:44:16.287337 progress 25 % (2 MB)
134 02:44:16.376394 progress 30 % (3 MB)
135 02:44:16.463812 progress 35 % (3 MB)
136 02:44:16.538417 progress 40 % (4 MB)
137 02:44:16.646573 progress 45 % (5 MB)
138 02:44:16.739656 progress 50 % (5 MB)
139 02:44:16.818704 progress 55 % (6 MB)
140 02:44:16.905484 progress 60 % (6 MB)
141 02:44:16.985870 progress 65 % (7 MB)
142 02:44:17.066039 progress 70 % (7 MB)
143 02:44:17.144586 progress 75 % (8 MB)
144 02:44:17.228059 progress 80 % (8 MB)
145 02:44:17.308007 progress 85 % (9 MB)
146 02:44:17.385948 progress 90 % (9 MB)
147 02:44:17.463087 progress 95 % (10 MB)
148 02:44:17.539199 progress 100 % (11 MB)
149 02:44:17.550947 11 MB downloaded in 1.73 s (6.42 MB/s)
150 02:44:17.551801 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:44:17.553435 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:44:17.553951 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 02:44:17.554470 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 02:44:33.960775 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/943587/extract-nfsrootfs-sug9f5e4
156 02:44:33.961394 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 02:44:33.961685 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 02:44:33.962301 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg
159 02:44:33.962735 makedir: /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin
160 02:44:33.963064 makedir: /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/tests
161 02:44:33.963374 makedir: /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/results
162 02:44:33.963710 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-add-keys
163 02:44:33.964300 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-add-sources
164 02:44:33.964819 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-background-process-start
165 02:44:33.965326 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-background-process-stop
166 02:44:33.965854 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-common-functions
167 02:44:33.966397 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-echo-ipv4
168 02:44:33.966939 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-install-packages
169 02:44:33.967474 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-installed-packages
170 02:44:33.968018 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-os-build
171 02:44:33.968537 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-probe-channel
172 02:44:33.969024 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-probe-ip
173 02:44:33.969506 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-target-ip
174 02:44:33.969989 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-target-mac
175 02:44:33.970471 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-target-storage
176 02:44:33.970961 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-test-case
177 02:44:33.971474 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-test-event
178 02:44:33.972110 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-test-feedback
179 02:44:33.972621 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-test-raise
180 02:44:33.973102 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-test-reference
181 02:44:33.973583 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-test-runner
182 02:44:33.974071 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-test-set
183 02:44:33.974552 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-test-shell
184 02:44:33.975042 Updating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-add-keys (debian)
185 02:44:33.975571 Updating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-add-sources (debian)
186 02:44:33.976124 Updating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-install-packages (debian)
187 02:44:33.976642 Updating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-installed-packages (debian)
188 02:44:33.977138 Updating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/bin/lava-os-build (debian)
189 02:44:33.977579 Creating /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/environment
190 02:44:33.977959 LAVA metadata
191 02:44:33.978234 - LAVA_JOB_ID=943587
192 02:44:33.978452 - LAVA_DISPATCHER_IP=192.168.6.2
193 02:44:33.978820 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 02:44:33.979790 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 02:44:33.980131 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 02:44:33.980341 skipped lava-vland-overlay
197 02:44:33.980581 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 02:44:33.980834 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 02:44:33.981050 skipped lava-multinode-overlay
200 02:44:33.981291 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 02:44:33.981540 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 02:44:33.981789 Loading test definitions
203 02:44:33.982063 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 02:44:33.982283 Using /lava-943587 at stage 0
205 02:44:33.983346 uuid=943587_1.6.2.4.1 testdef=None
206 02:44:33.983647 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 02:44:33.983911 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 02:44:33.985494 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 02:44:33.986276 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 02:44:33.988274 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 02:44:33.989107 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 02:44:33.990926 runner path: /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/0/tests/0_timesync-off test_uuid 943587_1.6.2.4.1
215 02:44:33.991463 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 02:44:33.992305 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 02:44:33.992548 Using /lava-943587 at stage 0
219 02:44:33.992904 Fetching tests from https://github.com/kernelci/test-definitions.git
220 02:44:33.993194 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/0/tests/1_kselftest-rtc'
221 02:44:37.444531 Running '/usr/bin/git checkout kernelci.org
222 02:44:37.806549 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 02:44:37.807970 uuid=943587_1.6.2.4.5 testdef=None
224 02:44:37.808346 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 02:44:37.809117 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 02:44:37.811961 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 02:44:37.812807 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 02:44:37.816498 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 02:44:37.817353 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 02:44:37.820917 runner path: /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/0/tests/1_kselftest-rtc test_uuid 943587_1.6.2.4.5
234 02:44:37.821200 BOARD='meson-sm1-s905d3-libretech-cc'
235 02:44:37.821404 BRANCH='clk'
236 02:44:37.821600 SKIPFILE='/dev/null'
237 02:44:37.821797 SKIP_INSTALL='True'
238 02:44:37.821991 TESTPROG_URL='http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 02:44:37.822191 TST_CASENAME=''
240 02:44:37.822387 TST_CMDFILES='rtc'
241 02:44:37.822927 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 02:44:37.823716 Creating lava-test-runner.conf files
244 02:44:37.823920 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/943587/lava-overlay-s6o_7ghg/lava-943587/0 for stage 0
245 02:44:37.824293 - 0_timesync-off
246 02:44:37.824532 - 1_kselftest-rtc
247 02:44:37.824858 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 02:44:37.825139 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 02:45:01.042108 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 02:45:01.042566 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 02:45:01.042862 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 02:45:01.043176 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 02:45:01.043472 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 02:45:01.651899 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 02:45:01.652423 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 02:45:01.652682 extracting modules file /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943587/extract-nfsrootfs-sug9f5e4
257 02:45:02.984769 extracting modules file /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943587/extract-overlay-ramdisk-iuwxtlv4/ramdisk
258 02:45:04.359523 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 02:45:04.360031 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 02:45:04.360314 [common] Applying overlay to NFS
261 02:45:04.360532 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943587/compress-overlay-ecgqxq_m/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/943587/extract-nfsrootfs-sug9f5e4
262 02:45:07.076765 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 02:45:07.077228 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 02:45:07.077503 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 02:45:07.077734 Converting downloaded kernel to a uImage
266 02:45:07.078046 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/kernel/Image /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/kernel/uImage
267 02:45:07.543201 output: Image Name:
268 02:45:07.543587 output: Created: Wed Nov 6 02:45:07 2024
269 02:45:07.543816 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 02:45:07.544070 output: Data Size: 45779456 Bytes = 44706.50 KiB = 43.66 MiB
271 02:45:07.544287 output: Load Address: 01080000
272 02:45:07.544495 output: Entry Point: 01080000
273 02:45:07.544699 output:
274 02:45:07.545034 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 02:45:07.545313 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 02:45:07.545596 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 02:45:07.545860 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 02:45:07.546132 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 02:45:07.546398 Building ramdisk /var/lib/lava/dispatcher/tmp/943587/extract-overlay-ramdisk-iuwxtlv4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/943587/extract-overlay-ramdisk-iuwxtlv4/ramdisk
280 02:45:09.652385 >> 166772 blocks
281 02:45:17.321076 Adding RAMdisk u-boot header.
282 02:45:17.321533 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/943587/extract-overlay-ramdisk-iuwxtlv4/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/943587/extract-overlay-ramdisk-iuwxtlv4/ramdisk.cpio.gz.uboot
283 02:45:17.565685 output: Image Name:
284 02:45:17.566111 output: Created: Wed Nov 6 02:45:17 2024
285 02:45:17.566546 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 02:45:17.566967 output: Data Size: 23427647 Bytes = 22878.56 KiB = 22.34 MiB
287 02:45:17.567380 output: Load Address: 00000000
288 02:45:17.567785 output: Entry Point: 00000000
289 02:45:17.568250 output:
290 02:45:17.569331 rename /var/lib/lava/dispatcher/tmp/943587/extract-overlay-ramdisk-iuwxtlv4/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/ramdisk/ramdisk.cpio.gz.uboot
291 02:45:17.570062 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 02:45:17.570625 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 02:45:17.571166 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 02:45:17.571630 No LXC device requested
295 02:45:17.572179 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 02:45:17.572711 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 02:45:17.573220 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 02:45:17.573641 Checking files for TFTP limit of 4294967296 bytes.
299 02:45:17.576336 end: 1 tftp-deploy (duration 00:01:18) [common]
300 02:45:17.576923 start: 2 uboot-action (timeout 00:05:00) [common]
301 02:45:17.577461 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 02:45:17.577968 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 02:45:17.578482 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 02:45:17.579017 Using kernel file from prepare-kernel: 943587/tftp-deploy-tenhd3r5/kernel/uImage
305 02:45:17.579650 substitutions:
306 02:45:17.580097 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 02:45:17.580512 - {DTB_ADDR}: 0x01070000
308 02:45:17.580916 - {DTB}: 943587/tftp-deploy-tenhd3r5/dtb/meson-sm1-s905d3-libretech-cc.dtb
309 02:45:17.581325 - {INITRD}: 943587/tftp-deploy-tenhd3r5/ramdisk/ramdisk.cpio.gz.uboot
310 02:45:17.581731 - {KERNEL_ADDR}: 0x01080000
311 02:45:17.582130 - {KERNEL}: 943587/tftp-deploy-tenhd3r5/kernel/uImage
312 02:45:17.582527 - {LAVA_MAC}: None
313 02:45:17.582964 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/943587/extract-nfsrootfs-sug9f5e4
314 02:45:17.583369 - {NFS_SERVER_IP}: 192.168.6.2
315 02:45:17.583766 - {PRESEED_CONFIG}: None
316 02:45:17.584233 - {PRESEED_LOCAL}: None
317 02:45:17.584642 - {RAMDISK_ADDR}: 0x08000000
318 02:45:17.585036 - {RAMDISK}: 943587/tftp-deploy-tenhd3r5/ramdisk/ramdisk.cpio.gz.uboot
319 02:45:17.585428 - {ROOT_PART}: None
320 02:45:17.585819 - {ROOT}: None
321 02:45:17.586207 - {SERVER_IP}: 192.168.6.2
322 02:45:17.586594 - {TEE_ADDR}: 0x83000000
323 02:45:17.586980 - {TEE}: None
324 02:45:17.587370 Parsed boot commands:
325 02:45:17.587749 - setenv autoload no
326 02:45:17.588169 - setenv initrd_high 0xffffffff
327 02:45:17.588561 - setenv fdt_high 0xffffffff
328 02:45:17.588951 - dhcp
329 02:45:17.589336 - setenv serverip 192.168.6.2
330 02:45:17.589728 - tftpboot 0x01080000 943587/tftp-deploy-tenhd3r5/kernel/uImage
331 02:45:17.590120 - tftpboot 0x08000000 943587/tftp-deploy-tenhd3r5/ramdisk/ramdisk.cpio.gz.uboot
332 02:45:17.590510 - tftpboot 0x01070000 943587/tftp-deploy-tenhd3r5/dtb/meson-sm1-s905d3-libretech-cc.dtb
333 02:45:17.590902 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943587/extract-nfsrootfs-sug9f5e4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 02:45:17.591305 - bootm 0x01080000 0x08000000 0x01070000
335 02:45:17.591805 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 02:45:17.593335 start: 2.3 connect-device (timeout 00:05:00) [common]
338 02:45:17.593759 [common] connect-device Connecting to device using 'telnet conserv1 3008'
339 02:45:17.607220 Setting prompt string to ['lava-test: # ']
340 02:45:17.608719 end: 2.3 connect-device (duration 00:00:00) [common]
341 02:45:17.609362 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 02:45:17.610017 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 02:45:17.610588 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 02:45:17.611717 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
345 02:45:17.647407 >> OK - accepted request
346 02:45:17.649258 Returned 0 in 0 seconds
347 02:45:17.750345 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 02:45:17.751880 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 02:45:17.752494 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 02:45:17.753019 Setting prompt string to ['Hit any key to stop autoboot']
352 02:45:17.753473 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 02:45:17.755002 Trying 192.168.56.21...
354 02:45:17.755477 Connected to conserv1.
355 02:45:17.755899 Escape character is '^]'.
356 02:45:17.756358
357 02:45:17.756792 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 02:45:17.757220
359 02:45:24.725193 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
360 02:45:24.725637 bl2_stage_init 0x01
361 02:45:24.725887 bl2_stage_init 0x81
362 02:45:24.730689 hw id: 0x0000 - pwm id 0x01
363 02:45:24.731091 bl2_stage_init 0xc1
364 02:45:24.736298 bl2_stage_init 0x02
365 02:45:24.736691
366 02:45:24.737018 L0:00000000
367 02:45:24.737331 L1:00000703
368 02:45:24.737638 L2:00008067
369 02:45:24.737871 L3:15000000
370 02:45:24.741792 S1:00000000
371 02:45:24.742103 B2:20282000
372 02:45:24.742323 B1:a0f83180
373 02:45:24.742529
374 02:45:24.742733 TE: 70520
375 02:45:24.742941
376 02:45:24.747562 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
377 02:45:24.747853
378 02:45:24.753087 Board ID = 1
379 02:45:24.753377 Set cpu clk to 24M
380 02:45:24.753587 Set clk81 to 24M
381 02:45:24.758682 Use GP1_pll as DSU clk.
382 02:45:24.759094 DSU clk: 1200 Mhz
383 02:45:24.759417 CPU clk: 1200 MHz
384 02:45:24.764361 Set clk81 to 166.6M
385 02:45:24.769859 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
386 02:45:24.770158 board id: 1
387 02:45:24.777042 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 02:45:24.788000 fw parse done
389 02:45:24.793973 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 02:45:24.836990 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 02:45:24.848189 PIEI prepare done
392 02:45:24.848509 fastboot data load
393 02:45:24.848733 fastboot data verify
394 02:45:24.853715 verify result: 266
395 02:45:24.859340 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
396 02:45:24.859634 LPDDR4 probe
397 02:45:24.859837 ddr clk to 1584MHz
398 02:45:24.867363 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 02:45:24.905064
400 02:45:24.905444 dmc_version 0001
401 02:45:24.912066 Check phy result
402 02:45:24.918050 INFO : End of CA training
403 02:45:24.918480 INFO : End of initialization
404 02:45:24.923665 INFO : Training has run successfully!
405 02:45:24.923953 Check phy result
406 02:45:24.929330 INFO : End of initialization
407 02:45:24.929623 INFO : End of read enable training
408 02:45:24.934875 INFO : End of fine write leveling
409 02:45:24.940560 INFO : End of Write leveling coarse delay
410 02:45:24.940856 INFO : Training has run successfully!
411 02:45:24.941068 Check phy result
412 02:45:24.946080 INFO : End of initialization
413 02:45:24.946382 INFO : End of read dq deskew training
414 02:45:24.951702 INFO : End of MPR read delay center optimization
415 02:45:24.957315 INFO : End of write delay center optimization
416 02:45:24.962921 INFO : End of read delay center optimization
417 02:45:24.963225 INFO : End of max read latency training
418 02:45:24.968569 INFO : Training has run successfully!
419 02:45:24.969000 1D training succeed
420 02:45:24.977647 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 02:45:25.026037 Check phy result
422 02:45:25.026618 INFO : End of initialization
423 02:45:25.053413 INFO : End of 2D read delay Voltage center optimization
424 02:45:25.077537 INFO : End of 2D read delay Voltage center optimization
425 02:45:25.134212 INFO : End of 2D write delay Voltage center optimization
426 02:45:25.188227 INFO : End of 2D write delay Voltage center optimization
427 02:45:25.193833 INFO : Training has run successfully!
428 02:45:25.194266
429 02:45:25.194674 channel==0
430 02:45:25.199389 RxClkDly_Margin_A0==88 ps 9
431 02:45:25.199817 TxDqDly_Margin_A0==98 ps 10
432 02:45:25.205049 RxClkDly_Margin_A1==88 ps 9
433 02:45:25.205484 TxDqDly_Margin_A1==88 ps 9
434 02:45:25.205890 TrainedVREFDQ_A0==76
435 02:45:25.210636 TrainedVREFDQ_A1==74
436 02:45:25.211061 VrefDac_Margin_A0==24
437 02:45:25.211464 DeviceVref_Margin_A0==38
438 02:45:25.216195 VrefDac_Margin_A1==23
439 02:45:25.216620 DeviceVref_Margin_A1==40
440 02:45:25.217020
441 02:45:25.217414
442 02:45:25.217807 channel==1
443 02:45:25.221847 RxClkDly_Margin_A0==78 ps 8
444 02:45:25.222278 TxDqDly_Margin_A0==88 ps 9
445 02:45:25.227498 RxClkDly_Margin_A1==78 ps 8
446 02:45:25.227924 TxDqDly_Margin_A1==78 ps 8
447 02:45:25.233101 TrainedVREFDQ_A0==77
448 02:45:25.233569 TrainedVREFDQ_A1==75
449 02:45:25.233989 VrefDac_Margin_A0==22
450 02:45:25.238678 DeviceVref_Margin_A0==37
451 02:45:25.239112 VrefDac_Margin_A1==22
452 02:45:25.239514 DeviceVref_Margin_A1==38
453 02:45:25.244258
454 02:45:25.244701 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 02:45:25.245104
456 02:45:25.277747 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
457 02:45:25.278276 2D training succeed
458 02:45:25.283341 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 02:45:25.288956 auto size-- 65535DDR cs0 size: 2048MB
460 02:45:25.289392 DDR cs1 size: 2048MB
461 02:45:25.294576 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 02:45:25.294999 cs0 DataBus test pass
463 02:45:25.300162 cs1 DataBus test pass
464 02:45:25.300589 cs0 AddrBus test pass
465 02:45:25.300998 cs1 AddrBus test pass
466 02:45:25.301395
467 02:45:25.305742 100bdlr_step_size ps== 471
468 02:45:25.306205 result report
469 02:45:25.311398 boot times 0Enable ddr reg access
470 02:45:25.316465 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 02:45:25.330336 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
472 02:45:25.989748 bl2z: ptr: 05129330, size: 00001e40
473 02:45:25.997406 0.0;M3 CHK:0;cm4_sp_mode 0
474 02:45:25.997860 MVN_1=0x00000000
475 02:45:25.998259 MVN_2=0x00000000
476 02:45:26.008857 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
477 02:45:26.009307 OPS=0x04
478 02:45:26.009712 ring efuse init
479 02:45:26.014467 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
480 02:45:26.014919 [0.017354 Inits done]
481 02:45:26.015321 secure task start!
482 02:45:26.021907 high task start!
483 02:45:26.022391 low task start!
484 02:45:26.022823 run into bl31
485 02:45:26.030663 NOTICE: BL31: v1.3(release):4fc40b1
486 02:45:26.038322 NOTICE: BL31: Built : 15:57:33, May 22 2019
487 02:45:26.038823 NOTICE: BL31: G12A normal boot!
488 02:45:26.053906 NOTICE: BL31: BL33 decompress pass
489 02:45:26.059733 ERROR: Error initializing runtime service opteed_fast
490 02:45:28.774684 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
491 02:45:28.775321 bl2_stage_init 0x01
492 02:45:28.775754 bl2_stage_init 0x81
493 02:45:28.780261 hw id: 0x0000 - pwm id 0x01
494 02:45:28.780734 bl2_stage_init 0xc1
495 02:45:28.785878 bl2_stage_init 0x02
496 02:45:28.786386
497 02:45:28.786783 L0:00000000
498 02:45:28.787175 L1:00000703
499 02:45:28.787559 L2:00008067
500 02:45:28.787940 L3:15000000
501 02:45:28.791439 S1:00000000
502 02:45:28.791855 B2:20282000
503 02:45:28.792273 B1:a0f83180
504 02:45:28.792654
505 02:45:28.793038 TE: 71686
506 02:45:28.793418
507 02:45:28.797046 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
508 02:45:28.797468
509 02:45:28.802647 Board ID = 1
510 02:45:28.803077 Set cpu clk to 24M
511 02:45:28.803464 Set clk81 to 24M
512 02:45:28.808248 Use GP1_pll as DSU clk.
513 02:45:28.808667 DSU clk: 1200 Mhz
514 02:45:28.809054 CPU clk: 1200 MHz
515 02:45:28.813825 Set clk81 to 166.6M
516 02:45:28.819429 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
517 02:45:28.819852 board id: 1
518 02:45:28.826618 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
519 02:45:28.837574 fw parse done
520 02:45:28.843496 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
521 02:45:28.886636 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
522 02:45:28.897735 PIEI prepare done
523 02:45:28.898157 fastboot data load
524 02:45:28.898547 fastboot data verify
525 02:45:28.903313 verify result: 266
526 02:45:28.909111 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
527 02:45:28.909528 LPDDR4 probe
528 02:45:28.909914 ddr clk to 1584MHz
529 02:45:28.916947 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
530 02:45:28.954613
531 02:45:28.955036 dmc_version 0001
532 02:45:28.961647 Check phy result
533 02:45:28.967679 INFO : End of CA training
534 02:45:28.968199 INFO : End of initialization
535 02:45:28.973249 INFO : Training has run successfully!
536 02:45:28.973690 Check phy result
537 02:45:28.978856 INFO : End of initialization
538 02:45:28.979284 INFO : End of read enable training
539 02:45:28.984441 INFO : End of fine write leveling
540 02:45:28.990082 INFO : End of Write leveling coarse delay
541 02:45:28.990510 INFO : Training has run successfully!
542 02:45:28.990915 Check phy result
543 02:45:28.995613 INFO : End of initialization
544 02:45:28.996066 INFO : End of read dq deskew training
545 02:45:29.001250 INFO : End of MPR read delay center optimization
546 02:45:29.006875 INFO : End of write delay center optimization
547 02:45:29.012464 INFO : End of read delay center optimization
548 02:45:29.012885 INFO : End of max read latency training
549 02:45:29.018076 INFO : Training has run successfully!
550 02:45:29.018500 1D training succeed
551 02:45:29.027265 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
552 02:45:29.075536 Check phy result
553 02:45:29.076077 INFO : End of initialization
554 02:45:29.102922 INFO : End of 2D read delay Voltage center optimization
555 02:45:29.127041 INFO : End of 2D read delay Voltage center optimization
556 02:45:29.183694 INFO : End of 2D write delay Voltage center optimization
557 02:45:29.237809 INFO : End of 2D write delay Voltage center optimization
558 02:45:29.243163 INFO : Training has run successfully!
559 02:45:29.243631
560 02:45:29.244077 channel==0
561 02:45:29.248763 RxClkDly_Margin_A0==88 ps 9
562 02:45:29.249229 TxDqDly_Margin_A0==98 ps 10
563 02:45:29.252141 RxClkDly_Margin_A1==88 ps 9
564 02:45:29.252894 TxDqDly_Margin_A1==98 ps 10
565 02:45:29.257723 TrainedVREFDQ_A0==74
566 02:45:29.258197 TrainedVREFDQ_A1==74
567 02:45:29.258618 VrefDac_Margin_A0==23
568 02:45:29.263296 DeviceVref_Margin_A0==40
569 02:45:29.263733 VrefDac_Margin_A1==23
570 02:45:29.268912 DeviceVref_Margin_A1==40
571 02:45:29.269342
572 02:45:29.269753
573 02:45:29.270155 channel==1
574 02:45:29.270550 RxClkDly_Margin_A0==78 ps 8
575 02:45:29.274501 TxDqDly_Margin_A0==98 ps 10
576 02:45:29.274940 RxClkDly_Margin_A1==78 ps 8
577 02:45:29.280123 TxDqDly_Margin_A1==88 ps 9
578 02:45:29.280556 TrainedVREFDQ_A0==78
579 02:45:29.280961 TrainedVREFDQ_A1==75
580 02:45:29.285685 VrefDac_Margin_A0==22
581 02:45:29.286132 DeviceVref_Margin_A0==36
582 02:45:29.291293 VrefDac_Margin_A1==22
583 02:45:29.291718 DeviceVref_Margin_A1==38
584 02:45:29.292161
585 02:45:29.296915 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
586 02:45:29.297350
587 02:45:29.324940 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000016 00000018 00000016 00000017 00000018 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
588 02:45:29.330492 2D training succeed
589 02:45:29.336141 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
590 02:45:29.336577 auto size-- 65535DDR cs0 size: 2048MB
591 02:45:29.341695 DDR cs1 size: 2048MB
592 02:45:29.342135 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
593 02:45:29.347290 cs0 DataBus test pass
594 02:45:29.347724 cs1 DataBus test pass
595 02:45:29.348163 cs0 AddrBus test pass
596 02:45:29.352928 cs1 AddrBus test pass
597 02:45:29.353360
598 02:45:29.353766 100bdlr_step_size ps== 471
599 02:45:29.354174 result report
600 02:45:29.358499 boot times 0Enable ddr reg access
601 02:45:29.366006 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
602 02:45:29.379955 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
603 02:45:30.038764 bl2z: ptr: 05129330, size: 00001e40
604 02:45:30.047349 0.0;M3 CHK:0;cm4_sp_mode 0
605 02:45:30.047840 MVN_1=0x00000000
606 02:45:30.048297 MVN_2=0x00000000
607 02:45:30.058848 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
608 02:45:30.059360 OPS=0x04
609 02:45:30.059802 ring efuse init
610 02:45:30.061746 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
611 02:45:30.067648 [0.017354 Inits done]
612 02:45:30.068114 secure task start!
613 02:45:30.068524 high task start!
614 02:45:30.068932 low task start!
615 02:45:30.071939 run into bl31
616 02:45:30.080544 NOTICE: BL31: v1.3(release):4fc40b1
617 02:45:30.088350 NOTICE: BL31: Built : 15:57:33, May 22 2019
618 02:45:30.088787 NOTICE: BL31: G12A normal boot!
619 02:45:30.103858 NOTICE: BL31: BL33 decompress pass
620 02:45:30.109548 ERROR: Error initializing runtime service opteed_fast
621 02:45:31.471413 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
622 02:45:31.472083 bl2_stage_init 0x01
623 02:45:31.472514 bl2_stage_init 0x81
624 02:45:31.476895 hw id: 0x0000 - pwm id 0x01
625 02:45:31.477342 bl2_stage_init 0xc1
626 02:45:31.482548 bl2_stage_init 0x02
627 02:45:31.482992
628 02:45:31.483402 L0:00000000
629 02:45:31.483801 L1:00000703
630 02:45:31.484235 L2:00008067
631 02:45:31.484632 L3:15000000
632 02:45:31.488172 S1:00000000
633 02:45:31.488610 B2:20282000
634 02:45:31.489009 B1:a0f83180
635 02:45:31.489402
636 02:45:31.489795 TE: 67736
637 02:45:31.490189
638 02:45:31.493588 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
639 02:45:31.494024
640 02:45:31.499208 Board ID = 1
641 02:45:31.499640 Set cpu clk to 24M
642 02:45:31.500070 Set clk81 to 24M
643 02:45:31.504805 Use GP1_pll as DSU clk.
644 02:45:31.505234 DSU clk: 1200 Mhz
645 02:45:31.505631 CPU clk: 1200 MHz
646 02:45:31.510478 Set clk81 to 166.6M
647 02:45:31.516041 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
648 02:45:31.516481 board id: 1
649 02:45:31.523196 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
650 02:45:31.533876 fw parse done
651 02:45:31.539968 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
652 02:45:31.582683 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
653 02:45:31.593510 PIEI prepare done
654 02:45:31.594115 fastboot data load
655 02:45:31.594601 fastboot data verify
656 02:45:31.599087 verify result: 266
657 02:45:31.604698 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
658 02:45:31.605306 LPDDR4 probe
659 02:45:31.605779 ddr clk to 1584MHz
660 02:45:31.612773 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
661 02:45:31.649969
662 02:45:31.650588 dmc_version 0001
663 02:45:31.656651 Check phy result
664 02:45:31.662527 INFO : End of CA training
665 02:45:31.663115 INFO : End of initialization
666 02:45:31.668135 INFO : Training has run successfully!
667 02:45:31.668734 Check phy result
668 02:45:31.673720 INFO : End of initialization
669 02:45:31.674300 INFO : End of read enable training
670 02:45:31.679352 INFO : End of fine write leveling
671 02:45:31.684918 INFO : End of Write leveling coarse delay
672 02:45:31.685521 INFO : Training has run successfully!
673 02:45:31.685996 Check phy result
674 02:45:31.690541 INFO : End of initialization
675 02:45:31.691132 INFO : End of read dq deskew training
676 02:45:31.696222 INFO : End of MPR read delay center optimization
677 02:45:31.701744 INFO : End of write delay center optimization
678 02:45:31.707276 INFO : End of read delay center optimization
679 02:45:31.707834 INFO : End of max read latency training
680 02:45:31.712919 INFO : Training has run successfully!
681 02:45:31.713474 1D training succeed
682 02:45:31.722026 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
683 02:45:31.769752 Check phy result
684 02:45:31.770340 INFO : End of initialization
685 02:45:31.792045 INFO : End of 2D read delay Voltage center optimization
686 02:45:31.811222 INFO : End of 2D read delay Voltage center optimization
687 02:45:31.863100 INFO : End of 2D write delay Voltage center optimization
688 02:45:31.912295 INFO : End of 2D write delay Voltage center optimization
689 02:45:31.917857 INFO : Training has run successfully!
690 02:45:31.918398
691 02:45:31.918865 channel==0
692 02:45:31.923569 RxClkDly_Margin_A0==78 ps 8
693 02:45:31.924155 TxDqDly_Margin_A0==98 ps 10
694 02:45:31.926791 RxClkDly_Margin_A1==88 ps 9
695 02:45:31.927327 TxDqDly_Margin_A1==98 ps 10
696 02:45:31.932376 TrainedVREFDQ_A0==75
697 02:45:31.932927 TrainedVREFDQ_A1==74
698 02:45:31.933394 VrefDac_Margin_A0==25
699 02:45:31.937979 DeviceVref_Margin_A0==39
700 02:45:31.938520 VrefDac_Margin_A1==23
701 02:45:31.943453 DeviceVref_Margin_A1==40
702 02:45:31.944020
703 02:45:31.944499
704 02:45:31.944952 channel==1
705 02:45:31.945395 RxClkDly_Margin_A0==78 ps 8
706 02:45:31.946980 TxDqDly_Margin_A0==98 ps 10
707 02:45:31.952493 RxClkDly_Margin_A1==88 ps 9
708 02:45:31.953030 TxDqDly_Margin_A1==88 ps 9
709 02:45:31.953495 TrainedVREFDQ_A0==78
710 02:45:31.958188 TrainedVREFDQ_A1==75
711 02:45:31.958730 VrefDac_Margin_A0==22
712 02:45:31.963811 DeviceVref_Margin_A0==36
713 02:45:31.964380 VrefDac_Margin_A1==20
714 02:45:31.964841 DeviceVref_Margin_A1==39
715 02:45:31.965284
716 02:45:31.969371 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
717 02:45:31.969923
718 02:45:32.002838 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
719 02:45:32.003450 2D training succeed
720 02:45:32.008524 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
721 02:45:32.014040 auto size-- 65535DDR cs0 size: 2048MB
722 02:45:32.014585 DDR cs1 size: 2048MB
723 02:45:32.019636 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
724 02:45:32.020202 cs0 DataBus test pass
725 02:45:32.020669 cs1 DataBus test pass
726 02:45:32.025228 cs0 AddrBus test pass
727 02:45:32.025761 cs1 AddrBus test pass
728 02:45:32.026217
729 02:45:32.030850 100bdlr_step_size ps== 478
730 02:45:32.031405 result report
731 02:45:32.031866 boot times 0Enable ddr reg access
732 02:45:32.040649 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
733 02:45:32.054381 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
734 02:45:32.709364 bl2z: ptr: 05129330, size: 00001e40
735 02:45:32.717532 0.0;M3 CHK:0;cm4_sp_mode 0
736 02:45:32.718097 MVN_1=0x00000000
737 02:45:32.718562 MVN_2=0x00000000
738 02:45:32.728925 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
739 02:45:32.729484 OPS=0x04
740 02:45:32.729944 ring efuse init
741 02:45:32.734725 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
742 02:45:32.735272 [0.017319 Inits done]
743 02:45:32.735733 secure task start!
744 02:45:32.742598 high task start!
745 02:45:32.743141 low task start!
746 02:45:32.743599 run into bl31
747 02:45:32.751196 NOTICE: BL31: v1.3(release):4fc40b1
748 02:45:32.759008 NOTICE: BL31: Built : 15:57:33, May 22 2019
749 02:45:32.759566 NOTICE: BL31: G12A normal boot!
750 02:45:32.774750 NOTICE: BL31: BL33 decompress pass
751 02:45:32.780304 ERROR: Error initializing runtime service opteed_fast
752 02:45:33.575737
753 02:45:33.576428
754 02:45:33.581148 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
755 02:45:33.581692
756 02:45:33.584644 Model: Libre Computer AML-S905D3-CC Solitude
757 02:45:33.731750 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
758 02:45:33.747039 DRAM: 2 GiB (effective 3.8 GiB)
759 02:45:33.848017 Core: 406 devices, 33 uclasses, devicetree: separate
760 02:45:33.854015 WDT: Not starting watchdog@f0d0
761 02:45:33.878970 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
762 02:45:33.891173 Loading Environment from FAT... Card did not respond to voltage select! : -110
763 02:45:33.896243 ** Bad device specification mmc 0 **
764 02:45:33.906264 Card did not respond to voltage select! : -110
765 02:45:33.913982 ** Bad device specification mmc 0 **
766 02:45:33.914543 Couldn't find partition mmc 0
767 02:45:33.922225 Card did not respond to voltage select! : -110
768 02:45:33.927905 ** Bad device specification mmc 0 **
769 02:45:33.928496 Couldn't find partition mmc 0
770 02:45:33.932812 Error: could not access storage.
771 02:45:34.231839 Net: eth0: ethernet@ff3f0000
772 02:45:34.234166 starting USB...
773 02:45:34.473995 Bus usb@ff500000: Register 3000140 NbrPorts 3
774 02:45:34.474666 Starting the controller
775 02:45:34.480869 USB XHCI 1.10
776 02:45:36.035088 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
777 02:45:36.043448 scanning usb for storage devices... 0 Storage Device(s) found
779 02:45:36.095210 Hit any key to stop autoboot: 1
780 02:45:36.096131 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
781 02:45:36.096856 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
782 02:45:36.097404 Setting prompt string to ['=>']
783 02:45:36.097937 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
784 02:45:36.385104 0
785 02:45:36.386205 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
787 02:45:36.487572 => setenv autoload no
788 02:45:36.488739 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
789 02:45:36.494344 setenv autoload no
791 02:45:36.595940 => setenv initrd_high 0xffffffff
792 02:45:36.596975 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
793 02:45:36.601257 setenv initrd_high 0xffffffff
795 02:45:36.702812 => setenv fdt_high 0xffffffff
796 02:45:36.703616 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
797 02:45:36.708549 setenv fdt_high 0xffffffff
799 02:45:36.810204 => dhcp
800 02:45:36.811160 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
801 02:45:36.815165 dhcp
802 02:45:37.570816 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
803 02:45:37.571458 Speed: 1000, full duplex
804 02:45:37.571921 BOOTP broadcast 1
805 02:45:37.585232 DHCP client bound to address 192.168.6.21 (14 ms)
807 02:45:37.686811 => setenv serverip 192.168.6.2
808 02:45:37.687604 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
809 02:45:37.692822 setenv serverip 192.168.6.2
811 02:45:37.794356 => tftpboot 0x01080000 943587/tftp-deploy-tenhd3r5/kernel/uImage
812 02:45:37.795072 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
813 02:45:37.801765 tftpboot 0x01080000 943587/tftp-deploy-tenhd3r5/kernel/uImage
814 02:45:37.802293 Speed: 1000, full duplex
815 02:45:37.802752 Using ethernet@ff3f0000 device
816 02:45:37.807329 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
817 02:45:37.812844 Filename '943587/tftp-deploy-tenhd3r5/kernel/uImage'.
818 02:45:37.816694 Load address: 0x1080000
819 02:45:40.794971 Loading: *################################################## 43.7 MiB
820 02:45:40.795633 14.7 MiB/s
821 02:45:40.796168 done
822 02:45:40.799221 Bytes transferred = 45779520 (2ba8a40 hex)
824 02:45:40.900907 => tftpboot 0x08000000 943587/tftp-deploy-tenhd3r5/ramdisk/ramdisk.cpio.gz.uboot
825 02:45:40.901726 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
826 02:45:40.908925 tftpboot 0x08000000 943587/tftp-deploy-tenhd3r5/ramdisk/ramdisk.cpio.gz.uboot
827 02:45:40.909453 Speed: 1000, full duplex
828 02:45:40.909890 Using ethernet@ff3f0000 device
829 02:45:40.914394 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
830 02:45:40.924067 Filename '943587/tftp-deploy-tenhd3r5/ramdisk/ramdisk.cpio.gz.uboot'.
831 02:45:40.924527 Load address: 0x8000000
832 02:45:42.330972 Loading: *################################################# UDP wrong checksum 00000005 00003eb6
833 02:45:47.332658 T UDP wrong checksum 00000005 00003eb6
834 02:45:57.334837 T T UDP wrong checksum 00000005 00003eb6
835 02:46:17.338890 T T T T UDP wrong checksum 00000005 00003eb6
836 02:46:22.122085 UDP wrong checksum 000000ff 0000e96d
837 02:46:22.161857 UDP wrong checksum 000000ff 00007360
838 02:46:37.343645 T T T
839 02:46:37.344383 Retry count exceeded; starting again
841 02:46:37.345948 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
844 02:46:37.348125 end: 2.4 uboot-commands (duration 00:01:20) [common]
846 02:46:37.349712 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
848 02:46:37.350816 end: 2 uboot-action (duration 00:01:20) [common]
850 02:46:37.352547 Cleaning after the job
851 02:46:37.353140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/ramdisk
852 02:46:37.354459 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/kernel
853 02:46:37.401871 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/dtb
854 02:46:37.402636 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/nfsrootfs
855 02:46:37.554929 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943587/tftp-deploy-tenhd3r5/modules
856 02:46:37.573214 start: 4.1 power-off (timeout 00:00:30) [common]
857 02:46:37.573830 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
858 02:46:37.606389 >> OK - accepted request
859 02:46:37.609021 Returned 0 in 0 seconds
860 02:46:37.709800 end: 4.1 power-off (duration 00:00:00) [common]
862 02:46:37.710718 start: 4.2 read-feedback (timeout 00:10:00) [common]
863 02:46:37.711358 Listened to connection for namespace 'common' for up to 1s
864 02:46:38.712277 Finalising connection for namespace 'common'
865 02:46:38.712747 Disconnecting from shell: Finalise
866 02:46:38.713034 =>
867 02:46:38.813794 end: 4.2 read-feedback (duration 00:00:01) [common]
868 02:46:38.814503 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/943587
869 02:46:41.726565 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/943587
870 02:46:41.727241 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.