Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:42:39.236602 lava-dispatcher, installed at version: 2024.01
2 02:42:39.237466 start: 0 validate
3 02:42:39.237953 Start time: 2024-11-06 02:42:39.237923+00:00 (UTC)
4 02:42:39.238491 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:42:39.239041 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:42:39.280754 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:42:39.281309 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:42:39.311370 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:42:39.311975 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:42:39.342222 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:42:39.342934 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:42:39.373816 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:42:39.374309 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fclk%2Fclk-next%2Fclk-fixes-for-linus-88-g768e1bffbc355%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:42:39.409922 validate duration: 0.17
16 02:42:39.410770 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:42:39.411100 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:42:39.411422 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:42:39.412017 Not decompressing ramdisk as can be used compressed.
20 02:42:39.412479 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 02:42:39.412768 saving as /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/ramdisk/initrd.cpio.gz
22 02:42:39.413049 total size: 5628140 (5 MB)
23 02:42:39.451548 progress 0 % (0 MB)
24 02:42:39.459324 progress 5 % (0 MB)
25 02:42:39.467130 progress 10 % (0 MB)
26 02:42:39.474055 progress 15 % (0 MB)
27 02:42:39.481092 progress 20 % (1 MB)
28 02:42:39.484796 progress 25 % (1 MB)
29 02:42:39.488780 progress 30 % (1 MB)
30 02:42:39.492868 progress 35 % (1 MB)
31 02:42:39.496540 progress 40 % (2 MB)
32 02:42:39.500485 progress 45 % (2 MB)
33 02:42:39.504071 progress 50 % (2 MB)
34 02:42:39.508061 progress 55 % (2 MB)
35 02:42:39.512061 progress 60 % (3 MB)
36 02:42:39.515544 progress 65 % (3 MB)
37 02:42:39.519362 progress 70 % (3 MB)
38 02:42:39.522872 progress 75 % (4 MB)
39 02:42:39.526823 progress 80 % (4 MB)
40 02:42:39.530386 progress 85 % (4 MB)
41 02:42:39.534281 progress 90 % (4 MB)
42 02:42:39.537993 progress 95 % (5 MB)
43 02:42:39.541190 progress 100 % (5 MB)
44 02:42:39.541827 5 MB downloaded in 0.13 s (41.68 MB/s)
45 02:42:39.542363 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:42:39.543229 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:42:39.543514 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:42:39.543781 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:42:39.544257 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/kernel/Image
51 02:42:39.544607 saving as /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/kernel/Image
52 02:42:39.544826 total size: 45779456 (43 MB)
53 02:42:39.545036 No compression specified
54 02:42:39.580294 progress 0 % (0 MB)
55 02:42:39.608470 progress 5 % (2 MB)
56 02:42:39.636771 progress 10 % (4 MB)
57 02:42:39.664976 progress 15 % (6 MB)
58 02:42:39.693355 progress 20 % (8 MB)
59 02:42:39.722052 progress 25 % (10 MB)
60 02:42:39.750554 progress 30 % (13 MB)
61 02:42:39.778633 progress 35 % (15 MB)
62 02:42:39.806873 progress 40 % (17 MB)
63 02:42:39.835071 progress 45 % (19 MB)
64 02:42:39.863088 progress 50 % (21 MB)
65 02:42:39.891106 progress 55 % (24 MB)
66 02:42:39.919483 progress 60 % (26 MB)
67 02:42:39.948213 progress 65 % (28 MB)
68 02:42:39.975911 progress 70 % (30 MB)
69 02:42:40.004441 progress 75 % (32 MB)
70 02:42:40.032656 progress 80 % (34 MB)
71 02:42:40.061010 progress 85 % (37 MB)
72 02:42:40.089112 progress 90 % (39 MB)
73 02:42:40.117259 progress 95 % (41 MB)
74 02:42:40.144945 progress 100 % (43 MB)
75 02:42:40.145511 43 MB downloaded in 0.60 s (72.68 MB/s)
76 02:42:40.145988 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:42:40.146812 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:42:40.147085 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:42:40.147350 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:42:40.147913 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:42:40.148255 saving as /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:42:40.148468 total size: 54703 (0 MB)
84 02:42:40.148681 No compression specified
85 02:42:40.186311 progress 59 % (0 MB)
86 02:42:40.187158 progress 100 % (0 MB)
87 02:42:40.187698 0 MB downloaded in 0.04 s (1.33 MB/s)
88 02:42:40.188190 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:42:40.189010 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:42:40.189271 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:42:40.189533 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:42:40.189993 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 02:42:40.190255 saving as /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/nfsrootfs/full.rootfs.tar
95 02:42:40.190460 total size: 474398908 (452 MB)
96 02:42:40.190671 Using unxz to decompress xz
97 02:42:40.228875 progress 0 % (0 MB)
98 02:42:41.324326 progress 5 % (22 MB)
99 02:42:42.764570 progress 10 % (45 MB)
100 02:42:43.196496 progress 15 % (67 MB)
101 02:42:43.960602 progress 20 % (90 MB)
102 02:42:44.492869 progress 25 % (113 MB)
103 02:42:44.859468 progress 30 % (135 MB)
104 02:42:45.461680 progress 35 % (158 MB)
105 02:42:46.304704 progress 40 % (181 MB)
106 02:42:47.034069 progress 45 % (203 MB)
107 02:42:47.601075 progress 50 % (226 MB)
108 02:42:48.270550 progress 55 % (248 MB)
109 02:42:49.459722 progress 60 % (271 MB)
110 02:42:50.932347 progress 65 % (294 MB)
111 02:42:52.557134 progress 70 % (316 MB)
112 02:42:55.646936 progress 75 % (339 MB)
113 02:42:58.072455 progress 80 % (361 MB)
114 02:43:00.996386 progress 85 % (384 MB)
115 02:43:04.103731 progress 90 % (407 MB)
116 02:43:07.272898 progress 95 % (429 MB)
117 02:43:10.450403 progress 100 % (452 MB)
118 02:43:10.463518 452 MB downloaded in 30.27 s (14.94 MB/s)
119 02:43:10.464552 end: 1.4.1 http-download (duration 00:00:30) [common]
121 02:43:10.466288 end: 1.4 download-retry (duration 00:00:30) [common]
122 02:43:10.466846 start: 1.5 download-retry (timeout 00:09:29) [common]
123 02:43:10.467405 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 02:43:10.468379 downloading http://storage.kernelci.org/clk/clk-next/clk-fixes-for-linus-88-g768e1bffbc355/arm64/defconfig/gcc-12/modules.tar.xz
125 02:43:10.468888 saving as /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/modules/modules.tar
126 02:43:10.469333 total size: 11613264 (11 MB)
127 02:43:10.469785 Using unxz to decompress xz
128 02:43:10.517187 progress 0 % (0 MB)
129 02:43:10.583365 progress 5 % (0 MB)
130 02:43:10.657609 progress 10 % (1 MB)
131 02:43:10.757037 progress 15 % (1 MB)
132 02:43:10.849217 progress 20 % (2 MB)
133 02:43:10.928908 progress 25 % (2 MB)
134 02:43:11.005072 progress 30 % (3 MB)
135 02:43:11.083898 progress 35 % (3 MB)
136 02:43:11.156359 progress 40 % (4 MB)
137 02:43:11.231684 progress 45 % (5 MB)
138 02:43:11.315072 progress 50 % (5 MB)
139 02:43:11.391271 progress 55 % (6 MB)
140 02:43:11.475456 progress 60 % (6 MB)
141 02:43:11.554902 progress 65 % (7 MB)
142 02:43:11.634287 progress 70 % (7 MB)
143 02:43:11.712109 progress 75 % (8 MB)
144 02:43:11.795538 progress 80 % (8 MB)
145 02:43:11.874852 progress 85 % (9 MB)
146 02:43:11.952602 progress 90 % (9 MB)
147 02:43:12.029306 progress 95 % (10 MB)
148 02:43:12.105294 progress 100 % (11 MB)
149 02:43:12.116922 11 MB downloaded in 1.65 s (6.72 MB/s)
150 02:43:12.117859 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:43:12.119694 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:43:12.120336 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 02:43:12.120925 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 02:43:27.955309 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/943514/extract-nfsrootfs-49wthbi7
156 02:43:27.955925 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 02:43:27.956251 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 02:43:27.957083 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2
159 02:43:27.957563 makedir: /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin
160 02:43:27.957895 makedir: /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/tests
161 02:43:27.958206 makedir: /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/results
162 02:43:27.958535 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-add-keys
163 02:43:27.959060 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-add-sources
164 02:43:27.959562 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-background-process-start
165 02:43:27.960087 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-background-process-stop
166 02:43:27.960637 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-common-functions
167 02:43:27.961311 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-echo-ipv4
168 02:43:27.961825 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-install-packages
169 02:43:27.962376 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-installed-packages
170 02:43:27.962857 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-os-build
171 02:43:27.963334 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-probe-channel
172 02:43:27.963807 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-probe-ip
173 02:43:27.964337 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-target-ip
174 02:43:27.964813 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-target-mac
175 02:43:27.965284 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-target-storage
176 02:43:27.965787 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-test-case
177 02:43:27.966323 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-test-event
178 02:43:27.966799 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-test-feedback
179 02:43:27.967269 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-test-raise
180 02:43:27.967731 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-test-reference
181 02:43:27.968230 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-test-runner
182 02:43:27.968716 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-test-set
183 02:43:27.969178 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-test-shell
184 02:43:27.969678 Updating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-install-packages (oe)
185 02:43:27.970242 Updating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/bin/lava-installed-packages (oe)
186 02:43:27.970677 Creating /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/environment
187 02:43:27.971035 LAVA metadata
188 02:43:27.971293 - LAVA_JOB_ID=943514
189 02:43:27.971505 - LAVA_DISPATCHER_IP=192.168.6.2
190 02:43:27.971862 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 02:43:27.972900 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 02:43:27.973212 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 02:43:27.973421 skipped lava-vland-overlay
194 02:43:27.973662 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 02:43:27.973915 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 02:43:27.974134 skipped lava-multinode-overlay
197 02:43:27.974373 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 02:43:27.974622 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 02:43:27.974866 Loading test definitions
200 02:43:27.975141 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 02:43:27.975362 Using /lava-943514 at stage 0
202 02:43:27.976531 uuid=943514_1.6.2.4.1 testdef=None
203 02:43:27.976833 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 02:43:27.977095 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 02:43:27.978768 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 02:43:27.979551 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 02:43:27.981749 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 02:43:27.982581 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 02:43:27.984660 runner path: /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 943514_1.6.2.4.1
212 02:43:27.985224 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 02:43:27.985979 Creating lava-test-runner.conf files
215 02:43:27.986179 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/943514/lava-overlay-ys8h4wc2/lava-943514/0 for stage 0
216 02:43:27.986506 - 0_v4l2-decoder-conformance-h265
217 02:43:27.986838 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 02:43:27.987105 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 02:43:28.008452 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 02:43:28.008824 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 02:43:28.009080 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 02:43:28.009345 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 02:43:28.009604 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 02:43:28.639639 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 02:43:28.640167 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 02:43:28.640441 extracting modules file /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943514/extract-nfsrootfs-49wthbi7
227 02:43:29.979507 extracting modules file /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943514/extract-overlay-ramdisk-1u41h80n/ramdisk
228 02:43:31.357578 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 02:43:31.358071 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 02:43:31.358371 [common] Applying overlay to NFS
231 02:43:31.358601 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943514/compress-overlay-53_6xuxj/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/943514/extract-nfsrootfs-49wthbi7
232 02:43:31.387837 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 02:43:31.388286 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 02:43:31.388585 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 02:43:31.388828 Converting downloaded kernel to a uImage
236 02:43:31.389152 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/kernel/Image /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/kernel/uImage
237 02:43:31.860452 output: Image Name:
238 02:43:31.860888 output: Created: Wed Nov 6 02:43:31 2024
239 02:43:31.861118 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 02:43:31.861332 output: Data Size: 45779456 Bytes = 44706.50 KiB = 43.66 MiB
241 02:43:31.861541 output: Load Address: 01080000
242 02:43:31.861746 output: Entry Point: 01080000
243 02:43:31.861949 output:
244 02:43:31.862292 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 02:43:31.862571 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 02:43:31.862848 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
247 02:43:31.863112 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 02:43:31.863380 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
249 02:43:31.863652 Building ramdisk /var/lib/lava/dispatcher/tmp/943514/extract-overlay-ramdisk-1u41h80n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/943514/extract-overlay-ramdisk-1u41h80n/ramdisk
250 02:43:34.005213 >> 166772 blocks
251 02:43:41.705702 Adding RAMdisk u-boot header.
252 02:43:41.706152 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/943514/extract-overlay-ramdisk-1u41h80n/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/943514/extract-overlay-ramdisk-1u41h80n/ramdisk.cpio.gz.uboot
253 02:43:41.970687 output: Image Name:
254 02:43:41.971119 output: Created: Wed Nov 6 02:43:41 2024
255 02:43:41.971611 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 02:43:41.972080 output: Data Size: 23426475 Bytes = 22877.42 KiB = 22.34 MiB
257 02:43:41.972518 output: Load Address: 00000000
258 02:43:41.972924 output: Entry Point: 00000000
259 02:43:41.973326 output:
260 02:43:41.974333 rename /var/lib/lava/dispatcher/tmp/943514/extract-overlay-ramdisk-1u41h80n/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/ramdisk/ramdisk.cpio.gz.uboot
261 02:43:41.975063 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 02:43:41.975623 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 02:43:41.976202 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 02:43:41.976680 No LXC device requested
265 02:43:41.977202 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 02:43:41.977725 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 02:43:41.978229 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 02:43:41.978654 Checking files for TFTP limit of 4294967296 bytes.
269 02:43:41.981387 end: 1 tftp-deploy (duration 00:01:03) [common]
270 02:43:41.981990 start: 2 uboot-action (timeout 00:05:00) [common]
271 02:43:41.982526 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 02:43:41.983036 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 02:43:41.983551 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 02:43:41.984144 Using kernel file from prepare-kernel: 943514/tftp-deploy-vsu1svf4/kernel/uImage
275 02:43:41.984796 substitutions:
276 02:43:41.985215 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 02:43:41.985622 - {DTB_ADDR}: 0x01070000
278 02:43:41.986025 - {DTB}: 943514/tftp-deploy-vsu1svf4/dtb/meson-g12b-a311d-libretech-cc.dtb
279 02:43:41.986426 - {INITRD}: 943514/tftp-deploy-vsu1svf4/ramdisk/ramdisk.cpio.gz.uboot
280 02:43:41.986828 - {KERNEL_ADDR}: 0x01080000
281 02:43:41.987222 - {KERNEL}: 943514/tftp-deploy-vsu1svf4/kernel/uImage
282 02:43:41.987619 - {LAVA_MAC}: None
283 02:43:41.988079 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/943514/extract-nfsrootfs-49wthbi7
284 02:43:41.988492 - {NFS_SERVER_IP}: 192.168.6.2
285 02:43:41.988840 - {PRESEED_CONFIG}: None
286 02:43:41.989067 - {PRESEED_LOCAL}: None
287 02:43:41.989290 - {RAMDISK_ADDR}: 0x08000000
288 02:43:41.989504 - {RAMDISK}: 943514/tftp-deploy-vsu1svf4/ramdisk/ramdisk.cpio.gz.uboot
289 02:43:41.989725 - {ROOT_PART}: None
290 02:43:41.989939 - {ROOT}: None
291 02:43:41.990150 - {SERVER_IP}: 192.168.6.2
292 02:43:41.990362 - {TEE_ADDR}: 0x83000000
293 02:43:41.990578 - {TEE}: None
294 02:43:41.990786 Parsed boot commands:
295 02:43:41.990997 - setenv autoload no
296 02:43:41.991209 - setenv initrd_high 0xffffffff
297 02:43:41.991541 - setenv fdt_high 0xffffffff
298 02:43:41.991810 - dhcp
299 02:43:41.992069 - setenv serverip 192.168.6.2
300 02:43:41.992301 - tftpboot 0x01080000 943514/tftp-deploy-vsu1svf4/kernel/uImage
301 02:43:41.992531 - tftpboot 0x08000000 943514/tftp-deploy-vsu1svf4/ramdisk/ramdisk.cpio.gz.uboot
302 02:43:41.992746 - tftpboot 0x01070000 943514/tftp-deploy-vsu1svf4/dtb/meson-g12b-a311d-libretech-cc.dtb
303 02:43:41.992961 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943514/extract-nfsrootfs-49wthbi7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 02:43:41.993183 - bootm 0x01080000 0x08000000 0x01070000
305 02:43:41.993474 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 02:43:41.994298 start: 2.3 connect-device (timeout 00:05:00) [common]
308 02:43:41.994672 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 02:43:42.007178 Setting prompt string to ['lava-test: # ']
310 02:43:42.008748 end: 2.3 connect-device (duration 00:00:00) [common]
311 02:43:42.009378 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 02:43:42.009940 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 02:43:42.010485 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 02:43:42.011633 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 02:43:42.048741 >> OK - accepted request
316 02:43:42.050777 Returned 0 in 0 seconds
317 02:43:42.151903 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 02:43:42.153692 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 02:43:42.154300 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 02:43:42.154829 Setting prompt string to ['Hit any key to stop autoboot']
322 02:43:42.155319 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 02:43:42.156948 Trying 192.168.56.21...
324 02:43:42.157438 Connected to conserv1.
325 02:43:42.157874 Escape character is '^]'.
326 02:43:42.158234
327 02:43:42.158473 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 02:43:42.158698
329 02:43:54.148224 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 02:43:54.148852 bl2_stage_init 0x01
331 02:43:54.149305 bl2_stage_init 0x81
332 02:43:54.153938 hw id: 0x0000 - pwm id 0x01
333 02:43:54.154489 bl2_stage_init 0xc1
334 02:43:54.154900 bl2_stage_init 0x02
335 02:43:54.155293
336 02:43:54.159336 L0:00000000
337 02:43:54.159825 L1:20000703
338 02:43:54.160261 L2:00008067
339 02:43:54.160651 L3:14000000
340 02:43:54.164981 B2:00402000
341 02:43:54.165458 B1:e0f83180
342 02:43:54.165862
343 02:43:54.166253 TE: 58124
344 02:43:54.166643
345 02:43:54.170617 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 02:43:54.171080
347 02:43:54.171480 Board ID = 1
348 02:43:54.176116 Set A53 clk to 24M
349 02:43:54.176580 Set A73 clk to 24M
350 02:43:54.176973 Set clk81 to 24M
351 02:43:54.181798 A53 clk: 1200 MHz
352 02:43:54.182251 A73 clk: 1200 MHz
353 02:43:54.182643 CLK81: 166.6M
354 02:43:54.183027 smccc: 00012a92
355 02:43:54.187395 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 02:43:54.192985 board id: 1
357 02:43:54.198852 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 02:43:54.209557 fw parse done
359 02:43:54.215514 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 02:43:54.257970 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 02:43:54.268879 PIEI prepare done
362 02:43:54.269347 fastboot data load
363 02:43:54.269748 fastboot data verify
364 02:43:54.274661 verify result: 266
365 02:43:54.280217 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 02:43:54.280723 LPDDR4 probe
367 02:43:54.281138 ddr clk to 1584MHz
368 02:43:54.288181 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 02:43:54.325391
370 02:43:54.325895 dmc_version 0001
371 02:43:54.332128 Check phy result
372 02:43:54.337964 INFO : End of CA training
373 02:43:54.338428 INFO : End of initialization
374 02:43:54.343547 INFO : Training has run successfully!
375 02:43:54.344033 Check phy result
376 02:43:54.349143 INFO : End of initialization
377 02:43:54.349600 INFO : End of read enable training
378 02:43:54.354743 INFO : End of fine write leveling
379 02:43:54.360339 INFO : End of Write leveling coarse delay
380 02:43:54.360797 INFO : Training has run successfully!
381 02:43:54.361206 Check phy result
382 02:43:54.365958 INFO : End of initialization
383 02:43:54.366417 INFO : End of read dq deskew training
384 02:43:54.371538 INFO : End of MPR read delay center optimization
385 02:43:54.377117 INFO : End of write delay center optimization
386 02:43:54.382743 INFO : End of read delay center optimization
387 02:43:54.383202 INFO : End of max read latency training
388 02:43:54.388326 INFO : Training has run successfully!
389 02:43:54.388788 1D training succeed
390 02:43:54.397519 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 02:43:54.445136 Check phy result
392 02:43:54.445647 INFO : End of initialization
393 02:43:54.466953 INFO : End of 2D read delay Voltage center optimization
394 02:43:54.487146 INFO : End of 2D read delay Voltage center optimization
395 02:43:54.539240 INFO : End of 2D write delay Voltage center optimization
396 02:43:54.588593 INFO : End of 2D write delay Voltage center optimization
397 02:43:54.594129 INFO : Training has run successfully!
398 02:43:54.594590
399 02:43:54.595018 channel==0
400 02:43:54.599720 RxClkDly_Margin_A0==88 ps 9
401 02:43:54.600207 TxDqDly_Margin_A0==98 ps 10
402 02:43:54.605314 RxClkDly_Margin_A1==88 ps 9
403 02:43:54.605789 TxDqDly_Margin_A1==98 ps 10
404 02:43:54.606201 TrainedVREFDQ_A0==74
405 02:43:54.610937 TrainedVREFDQ_A1==74
406 02:43:54.611404 VrefDac_Margin_A0==25
407 02:43:54.611816 DeviceVref_Margin_A0==40
408 02:43:54.616510 VrefDac_Margin_A1==25
409 02:43:54.616969 DeviceVref_Margin_A1==40
410 02:43:54.617375
411 02:43:54.617776
412 02:43:54.622123 channel==1
413 02:43:54.622582 RxClkDly_Margin_A0==98 ps 10
414 02:43:54.622992 TxDqDly_Margin_A0==88 ps 9
415 02:43:54.627715 RxClkDly_Margin_A1==88 ps 9
416 02:43:54.628199 TxDqDly_Margin_A1==88 ps 9
417 02:43:54.633318 TrainedVREFDQ_A0==77
418 02:43:54.633776 TrainedVREFDQ_A1==77
419 02:43:54.634184 VrefDac_Margin_A0==22
420 02:43:54.638905 DeviceVref_Margin_A0==37
421 02:43:54.639364 VrefDac_Margin_A1==24
422 02:43:54.644528 DeviceVref_Margin_A1==37
423 02:43:54.644991
424 02:43:54.645405 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 02:43:54.645803
426 02:43:54.678095 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 02:43:54.678694 2D training succeed
428 02:43:54.683704 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 02:43:54.689337 auto size-- 65535DDR cs0 size: 2048MB
430 02:43:54.689800 DDR cs1 size: 2048MB
431 02:43:54.694932 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 02:43:54.695387 cs0 DataBus test pass
433 02:43:54.700932 cs1 DataBus test pass
434 02:43:54.701392 cs0 AddrBus test pass
435 02:43:54.701806 cs1 AddrBus test pass
436 02:43:54.702205
437 02:43:54.706132 100bdlr_step_size ps== 420
438 02:43:54.706609 result report
439 02:43:54.711711 boot times 0Enable ddr reg access
440 02:43:54.717020 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 02:43:54.730795 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 02:43:55.303464 0.0;M3 CHK:0;cm4_sp_mode 0
443 02:43:55.304179 MVN_1=0x00000000
444 02:43:55.309012 MVN_2=0x00000000
445 02:43:55.314701 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 02:43:55.315176 OPS=0x10
447 02:43:55.315598 ring efuse init
448 02:43:55.316036 chipver efuse init
449 02:43:55.320305 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 02:43:55.325913 [0.018961 Inits done]
451 02:43:55.326382 secure task start!
452 02:43:55.326793 high task start!
453 02:43:55.330486 low task start!
454 02:43:55.330949 run into bl31
455 02:43:55.337151 NOTICE: BL31: v1.3(release):4fc40b1
456 02:43:55.345014 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 02:43:55.345488 NOTICE: BL31: G12A normal boot!
458 02:43:55.370347 NOTICE: BL31: BL33 decompress pass
459 02:43:55.376066 ERROR: Error initializing runtime service opteed_fast
460 02:43:56.609262
461 02:43:56.609704
462 02:43:56.617348 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 02:43:56.617775
464 02:43:56.618030 Model: Libre Computer AML-A311D-CC Alta
465 02:43:56.825785 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 02:43:56.849202 DRAM: 2 GiB (effective 3.8 GiB)
467 02:43:56.992214 Core: 408 devices, 31 uclasses, devicetree: separate
468 02:43:56.997971 WDT: Not starting watchdog@f0d0
469 02:43:57.030281 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 02:43:57.042681 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 02:43:57.047659 ** Bad device specification mmc 0 **
472 02:43:57.057998 Card did not respond to voltage select! : -110
473 02:43:57.065648 ** Bad device specification mmc 0 **
474 02:43:57.065968 Couldn't find partition mmc 0
475 02:43:57.073993 Card did not respond to voltage select! : -110
476 02:43:57.079498 ** Bad device specification mmc 0 **
477 02:43:57.079926 Couldn't find partition mmc 0
478 02:43:57.084571 Error: could not access storage.
479 02:43:58.348791 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
480 02:43:58.349437 bl2_stage_init 0x81
481 02:43:58.354344 hw id: 0x0000 - pwm id 0x01
482 02:43:58.354846 bl2_stage_init 0xc1
483 02:43:58.355269 bl2_stage_init 0x02
484 02:43:58.355676
485 02:43:58.359885 L0:00000000
486 02:43:58.360404 L1:20000703
487 02:43:58.360820 L2:00008067
488 02:43:58.361224 L3:14000000
489 02:43:58.361621 B2:00402000
490 02:43:58.362704 B1:e0f83180
491 02:43:58.363173
492 02:43:58.363584 TE: 58150
493 02:43:58.364014
494 02:43:58.373860 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 02:43:58.374380
496 02:43:58.374798 Board ID = 1
497 02:43:58.375205 Set A53 clk to 24M
498 02:43:58.375603 Set A73 clk to 24M
499 02:43:58.379488 Set clk81 to 24M
500 02:43:58.379960 A53 clk: 1200 MHz
501 02:43:58.380409 A73 clk: 1200 MHz
502 02:43:58.385069 CLK81: 166.6M
503 02:43:58.385537 smccc: 00012aac
504 02:43:58.390669 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 02:43:58.391159 board id: 1
506 02:43:58.399258 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 02:43:58.409911 fw parse done
508 02:43:58.415926 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 02:43:58.458507 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 02:43:58.469415 PIEI prepare done
511 02:43:58.469903 fastboot data load
512 02:43:58.470321 fastboot data verify
513 02:43:58.475101 verify result: 266
514 02:43:58.480647 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 02:43:58.481115 LPDDR4 probe
516 02:43:58.481526 ddr clk to 1584MHz
517 02:43:58.488636 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 02:43:58.525924
519 02:43:58.526426 dmc_version 0001
520 02:43:58.532613 Check phy result
521 02:43:58.538488 INFO : End of CA training
522 02:43:58.538942 INFO : End of initialization
523 02:43:58.544072 INFO : Training has run successfully!
524 02:43:58.544533 Check phy result
525 02:43:58.549670 INFO : End of initialization
526 02:43:58.550122 INFO : End of read enable training
527 02:43:58.555246 INFO : End of fine write leveling
528 02:43:58.560871 INFO : End of Write leveling coarse delay
529 02:43:58.561331 INFO : Training has run successfully!
530 02:43:58.561744 Check phy result
531 02:43:58.566451 INFO : End of initialization
532 02:43:58.566901 INFO : End of read dq deskew training
533 02:43:58.572079 INFO : End of MPR read delay center optimization
534 02:43:58.577665 INFO : End of write delay center optimization
535 02:43:58.583270 INFO : End of read delay center optimization
536 02:43:58.583726 INFO : End of max read latency training
537 02:43:58.588932 INFO : Training has run successfully!
538 02:43:58.589390 1D training succeed
539 02:43:58.598105 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 02:43:58.645751 Check phy result
541 02:43:58.646319 INFO : End of initialization
542 02:43:58.667463 INFO : End of 2D read delay Voltage center optimization
543 02:43:58.687764 INFO : End of 2D read delay Voltage center optimization
544 02:43:58.739809 INFO : End of 2D write delay Voltage center optimization
545 02:43:58.789208 INFO : End of 2D write delay Voltage center optimization
546 02:43:58.794757 INFO : Training has run successfully!
547 02:43:58.795259
548 02:43:58.795697 channel==0
549 02:43:58.800285 RxClkDly_Margin_A0==88 ps 9
550 02:43:58.800786 TxDqDly_Margin_A0==98 ps 10
551 02:43:58.806013 RxClkDly_Margin_A1==88 ps 9
552 02:43:58.806568 TxDqDly_Margin_A1==98 ps 10
553 02:43:58.807000 TrainedVREFDQ_A0==74
554 02:43:58.811539 TrainedVREFDQ_A1==74
555 02:43:58.812048 VrefDac_Margin_A0==25
556 02:43:58.812471 DeviceVref_Margin_A0==40
557 02:43:58.817065 VrefDac_Margin_A1==25
558 02:43:58.817545 DeviceVref_Margin_A1==40
559 02:43:58.817961
560 02:43:58.818369
561 02:43:58.822652 channel==1
562 02:43:58.823115 RxClkDly_Margin_A0==98 ps 10
563 02:43:58.823523 TxDqDly_Margin_A0==98 ps 10
564 02:43:58.828234 RxClkDly_Margin_A1==98 ps 10
565 02:43:58.828711 TxDqDly_Margin_A1==88 ps 9
566 02:43:58.833824 TrainedVREFDQ_A0==77
567 02:43:58.834312 TrainedVREFDQ_A1==77
568 02:43:58.834725 VrefDac_Margin_A0==22
569 02:43:58.839442 DeviceVref_Margin_A0==37
570 02:43:58.839912 VrefDac_Margin_A1==22
571 02:43:58.845045 DeviceVref_Margin_A1==37
572 02:43:58.845507
573 02:43:58.845921 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 02:43:58.850603
575 02:43:58.878581 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
576 02:43:58.879130 2D training succeed
577 02:43:58.884236 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 02:43:58.889825 auto size-- 65535DDR cs0 size: 2048MB
579 02:43:58.890295 DDR cs1 size: 2048MB
580 02:43:58.895543 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 02:43:58.896050 cs0 DataBus test pass
582 02:43:58.901104 cs1 DataBus test pass
583 02:43:58.901571 cs0 AddrBus test pass
584 02:43:58.901981 cs1 AddrBus test pass
585 02:43:58.902375
586 02:43:58.906632 100bdlr_step_size ps== 420
587 02:43:58.907104 result report
588 02:43:58.912247 boot times 0Enable ddr reg access
589 02:43:58.917661 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 02:43:58.931124 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 02:43:59.504905 0.0;M3 CHK:0;cm4_sp_mode 0
592 02:43:59.505539 MVN_1=0x00000000
593 02:43:59.510384 MVN_2=0x00000000
594 02:43:59.516246 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 02:43:59.516778 OPS=0x10
596 02:43:59.517245 ring efuse init
597 02:43:59.517695 chipver efuse init
598 02:43:59.524361 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 02:43:59.524891 [0.018961 Inits done]
600 02:43:59.532028 secure task start!
601 02:43:59.532503 high task start!
602 02:43:59.532899 low task start!
603 02:43:59.533291 run into bl31
604 02:43:59.538622 NOTICE: BL31: v1.3(release):4fc40b1
605 02:43:59.546372 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 02:43:59.546861 NOTICE: BL31: G12A normal boot!
607 02:43:59.571773 NOTICE: BL31: BL33 decompress pass
608 02:43:59.577491 ERROR: Error initializing runtime service opteed_fast
609 02:44:00.810389
610 02:44:00.810836
611 02:44:00.818774 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 02:44:00.819178
613 02:44:00.819423 Model: Libre Computer AML-A311D-CC Alta
614 02:44:01.027764 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 02:44:01.063594 DRAM: 2 GiB (effective 3.8 GiB)
616 02:44:01.193591 Core: 408 devices, 31 uclasses, devicetree: separate
617 02:44:01.199455 WDT: Not starting watchdog@f0d0
618 02:44:01.231776 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 02:44:01.244084 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 02:44:01.249195 ** Bad device specification mmc 0 **
621 02:44:01.259858 Card did not respond to voltage select! : -110
622 02:44:01.267203 ** Bad device specification mmc 0 **
623 02:44:01.267716 Couldn't find partition mmc 0
624 02:44:01.275431 Card did not respond to voltage select! : -110
625 02:44:01.281044 ** Bad device specification mmc 0 **
626 02:44:01.281456 Couldn't find partition mmc 0
627 02:44:01.285996 Error: could not access storage.
628 02:44:01.628579 Net: eth0: ethernet@ff3f0000
629 02:44:01.629273 starting USB...
630 02:44:01.880238 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 02:44:01.880675 Starting the controller
632 02:44:01.887185 USB XHCI 1.10
633 02:44:03.597214 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 02:44:03.597906 bl2_stage_init 0x01
635 02:44:03.598378 bl2_stage_init 0x81
636 02:44:03.602771 hw id: 0x0000 - pwm id 0x01
637 02:44:03.603294 bl2_stage_init 0xc1
638 02:44:03.603751 bl2_stage_init 0x02
639 02:44:03.604255
640 02:44:03.608391 L0:00000000
641 02:44:03.608896 L1:20000703
642 02:44:03.609346 L2:00008067
643 02:44:03.609790 L3:14000000
644 02:44:03.613950 B2:00402000
645 02:44:03.614450 B1:e0f83180
646 02:44:03.614895
647 02:44:03.615340 TE: 58167
648 02:44:03.615782
649 02:44:03.619582 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 02:44:03.620132
651 02:44:03.620593 Board ID = 1
652 02:44:03.625160 Set A53 clk to 24M
653 02:44:03.625652 Set A73 clk to 24M
654 02:44:03.626104 Set clk81 to 24M
655 02:44:03.630725 A53 clk: 1200 MHz
656 02:44:03.631225 A73 clk: 1200 MHz
657 02:44:03.631672 CLK81: 166.6M
658 02:44:03.632146 smccc: 00012abd
659 02:44:03.636260 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 02:44:03.641981 board id: 1
661 02:44:03.648060 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 02:44:03.658368 fw parse done
663 02:44:03.664317 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 02:44:03.706956 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 02:44:03.717837 PIEI prepare done
666 02:44:03.718346 fastboot data load
667 02:44:03.718800 fastboot data verify
668 02:44:03.723548 verify result: 266
669 02:44:03.729136 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 02:44:03.729651 LPDDR4 probe
671 02:44:03.730105 ddr clk to 1584MHz
672 02:44:03.737089 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 02:44:03.774458
674 02:44:03.775114 dmc_version 0001
675 02:44:03.781012 Check phy result
676 02:44:03.786874 INFO : End of CA training
677 02:44:03.787377 INFO : End of initialization
678 02:44:03.792464 INFO : Training has run successfully!
679 02:44:03.792963 Check phy result
680 02:44:03.798068 INFO : End of initialization
681 02:44:03.798561 INFO : End of read enable training
682 02:44:03.803670 INFO : End of fine write leveling
683 02:44:03.809302 INFO : End of Write leveling coarse delay
684 02:44:03.809798 INFO : Training has run successfully!
685 02:44:03.810249 Check phy result
686 02:44:03.814903 INFO : End of initialization
687 02:44:03.815401 INFO : End of read dq deskew training
688 02:44:03.820465 INFO : End of MPR read delay center optimization
689 02:44:03.826058 INFO : End of write delay center optimization
690 02:44:03.831807 INFO : End of read delay center optimization
691 02:44:03.832332 INFO : End of max read latency training
692 02:44:03.837284 INFO : Training has run successfully!
693 02:44:03.837778 1D training succeed
694 02:44:03.846499 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 02:44:03.894118 Check phy result
696 02:44:03.894667 INFO : End of initialization
697 02:44:03.915833 INFO : End of 2D read delay Voltage center optimization
698 02:44:03.936101 INFO : End of 2D read delay Voltage center optimization
699 02:44:03.988181 INFO : End of 2D write delay Voltage center optimization
700 02:44:04.037519 INFO : End of 2D write delay Voltage center optimization
701 02:44:04.043051 INFO : Training has run successfully!
702 02:44:04.043594
703 02:44:04.044120 channel==0
704 02:44:04.048623 RxClkDly_Margin_A0==88 ps 9
705 02:44:04.049115 TxDqDly_Margin_A0==98 ps 10
706 02:44:04.054228 RxClkDly_Margin_A1==88 ps 9
707 02:44:04.054717 TxDqDly_Margin_A1==98 ps 10
708 02:44:04.055175 TrainedVREFDQ_A0==74
709 02:44:04.059821 TrainedVREFDQ_A1==74
710 02:44:04.060354 VrefDac_Margin_A0==25
711 02:44:04.060803 DeviceVref_Margin_A0==40
712 02:44:04.065417 VrefDac_Margin_A1==25
713 02:44:04.065906 DeviceVref_Margin_A1==40
714 02:44:04.066353
715 02:44:04.066796
716 02:44:04.071003 channel==1
717 02:44:04.071494 RxClkDly_Margin_A0==98 ps 10
718 02:44:04.071942 TxDqDly_Margin_A0==88 ps 9
719 02:44:04.076584 RxClkDly_Margin_A1==98 ps 10
720 02:44:04.077074 TxDqDly_Margin_A1==88 ps 9
721 02:44:04.082207 TrainedVREFDQ_A0==77
722 02:44:04.082703 TrainedVREFDQ_A1==77
723 02:44:04.083150 VrefDac_Margin_A0==22
724 02:44:04.087789 DeviceVref_Margin_A0==37
725 02:44:04.088309 VrefDac_Margin_A1==22
726 02:44:04.093388 DeviceVref_Margin_A1==37
727 02:44:04.093877
728 02:44:04.094330 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 02:44:04.094775
730 02:44:04.127008 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
731 02:44:04.127556 2D training succeed
732 02:44:04.132579 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 02:44:04.138189 auto size-- 65535DDR cs0 size: 2048MB
734 02:44:04.138699 DDR cs1 size: 2048MB
735 02:44:04.143919 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 02:44:04.144537 cs0 DataBus test pass
737 02:44:04.149385 cs1 DataBus test pass
738 02:44:04.149877 cs0 AddrBus test pass
739 02:44:04.150326 cs1 AddrBus test pass
740 02:44:04.150764
741 02:44:04.155004 100bdlr_step_size ps== 420
742 02:44:04.155511 result report
743 02:44:04.160605 boot times 0Enable ddr reg access
744 02:44:04.165963 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 02:44:04.179623 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 02:44:04.753290 0.0;M3 CHK:0;cm4_sp_mode 0
747 02:44:04.753733 MVN_1=0x00000000
748 02:44:04.758720 MVN_2=0x00000000
749 02:44:04.764510 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 02:44:04.765033 OPS=0x10
751 02:44:04.765442 ring efuse init
752 02:44:04.765839 chipver efuse init
753 02:44:04.770080 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 02:44:04.775689 [0.018961 Inits done]
755 02:44:04.776214 secure task start!
756 02:44:04.776619 high task start!
757 02:44:04.780297 low task start!
758 02:44:04.780782 run into bl31
759 02:44:04.786947 NOTICE: BL31: v1.3(release):4fc40b1
760 02:44:04.794774 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 02:44:04.795282 NOTICE: BL31: G12A normal boot!
762 02:44:04.820685 NOTICE: BL31: BL33 decompress pass
763 02:44:04.826396 ERROR: Error initializing runtime service opteed_fast
764 02:44:06.059120
765 02:44:06.059545
766 02:44:06.067501 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 02:44:06.067881
768 02:44:06.068137 Model: Libre Computer AML-A311D-CC Alta
769 02:44:06.275950 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 02:44:06.299298 DRAM: 2 GiB (effective 3.8 GiB)
771 02:44:06.442306 Core: 408 devices, 31 uclasses, devicetree: separate
772 02:44:06.448141 WDT: Not starting watchdog@f0d0
773 02:44:06.480400 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 02:44:06.492844 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 02:44:06.497773 ** Bad device specification mmc 0 **
776 02:44:06.508169 Card did not respond to voltage select! : -110
777 02:44:06.515811 ** Bad device specification mmc 0 **
778 02:44:06.516174 Couldn't find partition mmc 0
779 02:44:06.524177 Card did not respond to voltage select! : -110
780 02:44:06.529635 ** Bad device specification mmc 0 **
781 02:44:06.529961 Couldn't find partition mmc 0
782 02:44:06.534791 Error: could not access storage.
783 02:44:06.877201 Net: eth0: ethernet@ff3f0000
784 02:44:06.877635 starting USB...
785 02:44:07.129019 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 02:44:07.129445 Starting the controller
787 02:44:07.135968 USB XHCI 1.10
788 02:44:09.297216 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 02:44:09.297777 bl2_stage_init 0x01
790 02:44:09.298035 bl2_stage_init 0x81
791 02:44:09.302840 hw id: 0x0000 - pwm id 0x01
792 02:44:09.303148 bl2_stage_init 0xc1
793 02:44:09.303369 bl2_stage_init 0x02
794 02:44:09.303574
795 02:44:09.308372 L0:00000000
796 02:44:09.308906 L1:20000703
797 02:44:09.309339 L2:00008067
798 02:44:09.309752 L3:14000000
799 02:44:09.313966 B2:00402000
800 02:44:09.314433 B1:e0f83180
801 02:44:09.314850
802 02:44:09.315255 TE: 58124
803 02:44:09.315660
804 02:44:09.319568 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 02:44:09.320073
806 02:44:09.320499 Board ID = 1
807 02:44:09.325194 Set A53 clk to 24M
808 02:44:09.325665 Set A73 clk to 24M
809 02:44:09.326086 Set clk81 to 24M
810 02:44:09.330748 A53 clk: 1200 MHz
811 02:44:09.331211 A73 clk: 1200 MHz
812 02:44:09.331624 CLK81: 166.6M
813 02:44:09.332063 smccc: 00012a92
814 02:44:09.336312 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 02:44:09.341963 board id: 1
816 02:44:09.348010 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 02:44:09.358366 fw parse done
818 02:44:09.364341 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 02:44:09.406966 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 02:44:09.417870 PIEI prepare done
821 02:44:09.418339 fastboot data load
822 02:44:09.418766 fastboot data verify
823 02:44:09.423507 verify result: 266
824 02:44:09.429080 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 02:44:09.429553 LPDDR4 probe
826 02:44:09.429974 ddr clk to 1584MHz
827 02:44:09.437060 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 02:44:09.474340
829 02:44:09.474810 dmc_version 0001
830 02:44:09.481054 Check phy result
831 02:44:09.486869 INFO : End of CA training
832 02:44:09.487327 INFO : End of initialization
833 02:44:09.492478 INFO : Training has run successfully!
834 02:44:09.492947 Check phy result
835 02:44:09.498056 INFO : End of initialization
836 02:44:09.498511 INFO : End of read enable training
837 02:44:09.503663 INFO : End of fine write leveling
838 02:44:09.509269 INFO : End of Write leveling coarse delay
839 02:44:09.509727 INFO : Training has run successfully!
840 02:44:09.510153 Check phy result
841 02:44:09.514847 INFO : End of initialization
842 02:44:09.515316 INFO : End of read dq deskew training
843 02:44:09.520470 INFO : End of MPR read delay center optimization
844 02:44:09.526052 INFO : End of write delay center optimization
845 02:44:09.531698 INFO : End of read delay center optimization
846 02:44:09.532189 INFO : End of max read latency training
847 02:44:09.537297 INFO : Training has run successfully!
848 02:44:09.537759 1D training succeed
849 02:44:09.546439 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 02:44:09.594134 Check phy result
851 02:44:09.594631 INFO : End of initialization
852 02:44:09.616630 INFO : End of 2D read delay Voltage center optimization
853 02:44:09.636975 INFO : End of 2D read delay Voltage center optimization
854 02:44:09.689016 INFO : End of 2D write delay Voltage center optimization
855 02:44:09.738317 INFO : End of 2D write delay Voltage center optimization
856 02:44:09.743847 INFO : Training has run successfully!
857 02:44:09.744364
858 02:44:09.744811 channel==0
859 02:44:09.749394 RxClkDly_Margin_A0==88 ps 9
860 02:44:09.749856 TxDqDly_Margin_A0==98 ps 10
861 02:44:09.754981 RxClkDly_Margin_A1==88 ps 9
862 02:44:09.755431 TxDqDly_Margin_A1==98 ps 10
863 02:44:09.755878 TrainedVREFDQ_A0==74
864 02:44:09.760623 TrainedVREFDQ_A1==75
865 02:44:09.761154 VrefDac_Margin_A0==25
866 02:44:09.761582 DeviceVref_Margin_A0==40
867 02:44:09.766246 VrefDac_Margin_A1==24
868 02:44:09.766751 DeviceVref_Margin_A1==39
869 02:44:09.767140
870 02:44:09.767528
871 02:44:09.771843 channel==1
872 02:44:09.772314 RxClkDly_Margin_A0==98 ps 10
873 02:44:09.772700 TxDqDly_Margin_A0==98 ps 10
874 02:44:09.777439 RxClkDly_Margin_A1==88 ps 9
875 02:44:09.777874 TxDqDly_Margin_A1==88 ps 9
876 02:44:09.782969 TrainedVREFDQ_A0==77
877 02:44:09.783402 TrainedVREFDQ_A1==77
878 02:44:09.783796 VrefDac_Margin_A0==22
879 02:44:09.788595 DeviceVref_Margin_A0==37
880 02:44:09.789029 VrefDac_Margin_A1==24
881 02:44:09.794237 DeviceVref_Margin_A1==37
882 02:44:09.794676
883 02:44:09.795069 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 02:44:09.795453
885 02:44:09.827828 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
886 02:44:09.828351 2D training succeed
887 02:44:09.833359 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 02:44:09.839067 auto size-- 65535DDR cs0 size: 2048MB
889 02:44:09.839522 DDR cs1 size: 2048MB
890 02:44:09.844598 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 02:44:09.845035 cs0 DataBus test pass
892 02:44:09.850180 cs1 DataBus test pass
893 02:44:09.850609 cs0 AddrBus test pass
894 02:44:09.851000 cs1 AddrBus test pass
895 02:44:09.851384
896 02:44:09.855840 100bdlr_step_size ps== 420
897 02:44:09.856321 result report
898 02:44:09.861382 boot times 0Enable ddr reg access
899 02:44:09.866732 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 02:44:09.880227 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 02:44:10.454082 0.0;M3 CHK:0;cm4_sp_mode 0
902 02:44:10.454530 MVN_1=0x00000000
903 02:44:10.459463 MVN_2=0x00000000
904 02:44:10.465207 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 02:44:10.465690 OPS=0x10
906 02:44:10.465962 ring efuse init
907 02:44:10.466181 chipver efuse init
908 02:44:10.470813 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 02:44:10.476435 [0.018960 Inits done]
910 02:44:10.476775 secure task start!
911 02:44:10.476990 high task start!
912 02:44:10.481001 low task start!
913 02:44:10.481333 run into bl31
914 02:44:10.487622 NOTICE: BL31: v1.3(release):4fc40b1
915 02:44:10.495492 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 02:44:10.496037 NOTICE: BL31: G12A normal boot!
917 02:44:10.520807 NOTICE: BL31: BL33 decompress pass
918 02:44:10.526460 ERROR: Error initializing runtime service opteed_fast
919 02:44:11.759348
920 02:44:11.759788
921 02:44:11.767800 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 02:44:11.768442
923 02:44:11.768933 Model: Libre Computer AML-A311D-CC Alta
924 02:44:11.976263 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 02:44:11.999619 DRAM: 2 GiB (effective 3.8 GiB)
926 02:44:12.142570 Core: 408 devices, 31 uclasses, devicetree: separate
927 02:44:12.148393 WDT: Not starting watchdog@f0d0
928 02:44:12.180729 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 02:44:12.193151 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 02:44:12.198057 ** Bad device specification mmc 0 **
931 02:44:12.208394 Card did not respond to voltage select! : -110
932 02:44:12.216061 ** Bad device specification mmc 0 **
933 02:44:12.216585 Couldn't find partition mmc 0
934 02:44:12.224384 Card did not respond to voltage select! : -110
935 02:44:12.229888 ** Bad device specification mmc 0 **
936 02:44:12.230405 Couldn't find partition mmc 0
937 02:44:12.234945 Error: could not access storage.
938 02:44:12.577476 Net: eth0: ethernet@ff3f0000
939 02:44:12.577902 starting USB...
940 02:44:12.829294 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 02:44:12.829885 Starting the controller
942 02:44:12.836222 USB XHCI 1.10
943 02:44:14.697221 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
944 02:44:14.697648 bl2_stage_init 0x01
945 02:44:14.697869 bl2_stage_init 0x81
946 02:44:14.702771 hw id: 0x0000 - pwm id 0x01
947 02:44:14.703089 bl2_stage_init 0xc1
948 02:44:14.703306 bl2_stage_init 0x02
949 02:44:14.703513
950 02:44:14.708393 L0:00000000
951 02:44:14.708705 L1:20000703
952 02:44:14.708925 L2:00008067
953 02:44:14.709131 L3:14000000
954 02:44:14.711441 B2:00402000
955 02:44:14.711733 B1:e0f83180
956 02:44:14.711947
957 02:44:14.712183 TE: 58167
958 02:44:14.712387
959 02:44:14.722713 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 02:44:14.723060
961 02:44:14.723292 Board ID = 1
962 02:44:14.723498 Set A53 clk to 24M
963 02:44:14.723700 Set A73 clk to 24M
964 02:44:14.728214 Set clk81 to 24M
965 02:44:14.728657 A53 clk: 1200 MHz
966 02:44:14.728913 A73 clk: 1200 MHz
967 02:44:14.731674 CLK81: 166.6M
968 02:44:14.731976 smccc: 00012abe
969 02:44:14.737230 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 02:44:14.742685 board id: 1
971 02:44:14.747959 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 02:44:14.758554 fw parse done
973 02:44:14.764603 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 02:44:14.807018 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 02:44:14.817990 PIEI prepare done
976 02:44:14.818370 fastboot data load
977 02:44:14.818648 fastboot data verify
978 02:44:14.823543 verify result: 266
979 02:44:14.829130 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 02:44:14.829481 LPDDR4 probe
981 02:44:14.829751 ddr clk to 1584MHz
982 02:44:14.837109 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 02:44:14.874445
984 02:44:14.874862 dmc_version 0001
985 02:44:14.881046 Check phy result
986 02:44:14.886907 INFO : End of CA training
987 02:44:14.887248 INFO : End of initialization
988 02:44:14.892645 INFO : Training has run successfully!
989 02:44:14.893017 Check phy result
990 02:44:14.898202 INFO : End of initialization
991 02:44:14.898551 INFO : End of read enable training
992 02:44:14.903778 INFO : End of fine write leveling
993 02:44:14.909366 INFO : End of Write leveling coarse delay
994 02:44:14.909719 INFO : Training has run successfully!
995 02:44:14.909965 Check phy result
996 02:44:14.914988 INFO : End of initialization
997 02:44:14.915485 INFO : End of read dq deskew training
998 02:44:14.920604 INFO : End of MPR read delay center optimization
999 02:44:14.926205 INFO : End of write delay center optimization
1000 02:44:14.931771 INFO : End of read delay center optimization
1001 02:44:14.932147 INFO : End of max read latency training
1002 02:44:14.937378 INFO : Training has run successfully!
1003 02:44:14.937882 1D training succeed
1004 02:44:14.946613 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 02:44:14.994433 Check phy result
1006 02:44:14.994874 INFO : End of initialization
1007 02:44:15.015958 INFO : End of 2D read delay Voltage center optimization
1008 02:44:15.036264 INFO : End of 2D read delay Voltage center optimization
1009 02:44:15.088297 INFO : End of 2D write delay Voltage center optimization
1010 02:44:15.137693 INFO : End of 2D write delay Voltage center optimization
1011 02:44:15.143223 INFO : Training has run successfully!
1012 02:44:15.143636
1013 02:44:15.143891 channel==0
1014 02:44:15.148843 RxClkDly_Margin_A0==88 ps 9
1015 02:44:15.149411 TxDqDly_Margin_A0==98 ps 10
1016 02:44:15.154442 RxClkDly_Margin_A1==88 ps 9
1017 02:44:15.155001 TxDqDly_Margin_A1==88 ps 9
1018 02:44:15.155297 TrainedVREFDQ_A0==74
1019 02:44:15.160026 TrainedVREFDQ_A1==74
1020 02:44:15.160404 VrefDac_Margin_A0==25
1021 02:44:15.160633 DeviceVref_Margin_A0==40
1022 02:44:15.165593 VrefDac_Margin_A1==25
1023 02:44:15.166124 DeviceVref_Margin_A1==40
1024 02:44:15.166481
1025 02:44:15.166819
1026 02:44:15.167151 channel==1
1027 02:44:15.171266 RxClkDly_Margin_A0==98 ps 10
1028 02:44:15.171792 TxDqDly_Margin_A0==88 ps 9
1029 02:44:15.176864 RxClkDly_Margin_A1==98 ps 10
1030 02:44:15.177435 TxDqDly_Margin_A1==98 ps 10
1031 02:44:15.182434 TrainedVREFDQ_A0==75
1032 02:44:15.182840 TrainedVREFDQ_A1==77
1033 02:44:15.183075 VrefDac_Margin_A0==22
1034 02:44:15.188062 DeviceVref_Margin_A0==39
1035 02:44:15.188629 VrefDac_Margin_A1==22
1036 02:44:15.193638 DeviceVref_Margin_A1==37
1037 02:44:15.194193
1038 02:44:15.194467 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 02:44:15.194682
1040 02:44:15.227300 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1041 02:44:15.227743 2D training succeed
1042 02:44:15.232933 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 02:44:15.238803 auto size-- 65535DDR cs0 size: 2048MB
1044 02:44:15.239237 DDR cs1 size: 2048MB
1045 02:44:15.244078 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 02:44:15.244505 cs0 DataBus test pass
1047 02:44:15.249940 cs1 DataBus test pass
1048 02:44:15.250382 cs0 AddrBus test pass
1049 02:44:15.250653 cs1 AddrBus test pass
1050 02:44:15.250903
1051 02:44:15.260332 100bdlr_step_size ps== 420
1052 02:44:15.261251 result report
1053 02:44:15.262131 boot times 0Enable ddr reg access
1054 02:44:15.266785 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 02:44:15.279799 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 02:44:15.853310 0.0;M3 CHK:0;cm4_sp_mode 0
1057 02:44:15.853905 MVN_1=0x00000000
1058 02:44:15.859162 MVN_2=0x00000000
1059 02:44:15.864523 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 02:44:15.864936 OPS=0x10
1061 02:44:15.865156 ring efuse init
1062 02:44:15.865379 chipver efuse init
1063 02:44:15.870467 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 02:44:15.875854 [0.018960 Inits done]
1065 02:44:15.876266 secure task start!
1066 02:44:15.876477 high task start!
1067 02:44:15.880278 low task start!
1068 02:44:15.880692 run into bl31
1069 02:44:15.886872 NOTICE: BL31: v1.3(release):4fc40b1
1070 02:44:15.894723 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 02:44:15.895259 NOTICE: BL31: G12A normal boot!
1072 02:44:15.920107 NOTICE: BL31: BL33 decompress pass
1073 02:44:15.925722 ERROR: Error initializing runtime service opteed_fast
1074 02:44:17.158628
1075 02:44:17.159301
1076 02:44:17.166950 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 02:44:17.167462
1078 02:44:17.167924 Model: Libre Computer AML-A311D-CC Alta
1079 02:44:17.375438 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 02:44:17.398805 DRAM: 2 GiB (effective 3.8 GiB)
1081 02:44:17.541796 Core: 408 devices, 31 uclasses, devicetree: separate
1082 02:44:17.547637 WDT: Not starting watchdog@f0d0
1083 02:44:17.579969 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 02:44:17.592358 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 02:44:17.597345 ** Bad device specification mmc 0 **
1086 02:44:17.607681 Card did not respond to voltage select! : -110
1087 02:44:17.615347 ** Bad device specification mmc 0 **
1088 02:44:17.615673 Couldn't find partition mmc 0
1089 02:44:17.623664 Card did not respond to voltage select! : -110
1090 02:44:17.629169 ** Bad device specification mmc 0 **
1091 02:44:17.629571 Couldn't find partition mmc 0
1092 02:44:17.634229 Error: could not access storage.
1093 02:44:17.976753 Net: eth0: ethernet@ff3f0000
1094 02:44:17.977180 starting USB...
1095 02:44:18.228592 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 02:44:18.229181 Starting the controller
1097 02:44:18.235507 USB XHCI 1.10
1098 02:44:19.789551 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 02:44:19.797866 scanning usb for storage devices... 0 Storage Device(s) found
1101 02:44:19.849115 Hit any key to stop autoboot: 1
1102 02:44:19.850071 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1103 02:44:19.850656 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1104 02:44:19.851116 Setting prompt string to ['=>']
1105 02:44:19.851586 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1106 02:44:19.865531 0
1107 02:44:19.866421 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 02:44:19.866905 Sending with 10 millisecond of delay
1110 02:44:21.001443 => setenv autoload no
1111 02:44:21.012247 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1112 02:44:21.017158 setenv autoload no
1113 02:44:21.017946 Sending with 10 millisecond of delay
1115 02:44:22.815620 => setenv initrd_high 0xffffffff
1116 02:44:22.826542 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1117 02:44:22.827222 setenv initrd_high 0xffffffff
1118 02:44:22.827790 Sending with 10 millisecond of delay
1120 02:44:24.447750 => setenv fdt_high 0xffffffff
1121 02:44:24.458676 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 02:44:24.459314 setenv fdt_high 0xffffffff
1123 02:44:24.459890 Sending with 10 millisecond of delay
1125 02:44:24.751654 => dhcp
1126 02:44:24.762547 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1127 02:44:24.763290 dhcp
1128 02:44:24.763604 Speed: 1000, full duplex
1129 02:44:24.763860 BOOTP broadcast 1
1130 02:44:24.951779 DHCP client bound to address 192.168.6.27 (189 ms)
1131 02:44:24.956171 Sending with 10 millisecond of delay
1133 02:44:26.632434 => setenv serverip 192.168.6.2
1134 02:44:26.643543 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1135 02:44:26.644238 setenv serverip 192.168.6.2
1136 02:44:26.644789 Sending with 10 millisecond of delay
1138 02:44:30.367833 => tftpboot 0x01080000 943514/tftp-deploy-vsu1svf4/kernel/uImage
1139 02:44:30.381550 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1140 02:44:30.382228 tftpboot 0x01080000 943514/tftp-deploy-vsu1svf4/kernel/uImage
1141 02:44:30.382522 Speed: 1000, full duplex
1142 02:44:30.382773 Using ethernet@ff3f0000 device
1143 02:44:30.383018 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1144 02:44:30.386796 Filename '943514/tftp-deploy-vsu1svf4/kernel/uImage'.
1145 02:44:30.390810 Load address: 0x1080000
1146 02:44:33.274528 Loading: *################################################## 43.7 MiB
1147 02:44:33.275137 15.1 MiB/s
1148 02:44:33.275577 done
1149 02:44:33.278856 Bytes transferred = 45779520 (2ba8a40 hex)
1150 02:44:33.279602 Sending with 10 millisecond of delay
1152 02:44:37.966735 => tftpboot 0x08000000 943514/tftp-deploy-vsu1svf4/ramdisk/ramdisk.cpio.gz.uboot
1153 02:44:37.977592 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1154 02:44:37.978535 tftpboot 0x08000000 943514/tftp-deploy-vsu1svf4/ramdisk/ramdisk.cpio.gz.uboot
1155 02:44:37.979010 Speed: 1000, full duplex
1156 02:44:37.979451 Using ethernet@ff3f0000 device
1157 02:44:37.980250 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1158 02:44:37.992089 Filename '943514/tftp-deploy-vsu1svf4/ramdisk/ramdisk.cpio.gz.uboot'.
1159 02:44:37.992377 Load address: 0x8000000
1160 02:44:44.618532 Loading: *#########################T ######################## UDP wrong checksum 00000005 000034c8
1161 02:44:49.619648 T UDP wrong checksum 00000005 000034c8
1162 02:44:59.622793 T T UDP wrong checksum 00000005 000034c8
1163 02:45:19.625025 T T T UDP wrong checksum 00000005 000034c8
1164 02:45:34.630617 T T T
1165 02:45:34.631289 Retry count exceeded; starting again
1167 02:45:34.632896 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1170 02:45:34.634995 end: 2.4 uboot-commands (duration 00:01:53) [common]
1172 02:45:34.636764 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1174 02:45:34.637917 end: 2 uboot-action (duration 00:01:53) [common]
1176 02:45:34.639572 Cleaning after the job
1177 02:45:34.640200 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/ramdisk
1178 02:45:34.642803 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/kernel
1179 02:45:34.673843 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/dtb
1180 02:45:34.675271 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/nfsrootfs
1181 02:45:34.936249 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943514/tftp-deploy-vsu1svf4/modules
1182 02:45:34.955143 start: 4.1 power-off (timeout 00:00:30) [common]
1183 02:45:34.955789 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1184 02:45:34.986493 >> OK - accepted request
1185 02:45:34.988391 Returned 0 in 0 seconds
1186 02:45:35.089178 end: 4.1 power-off (duration 00:00:00) [common]
1188 02:45:35.090225 start: 4.2 read-feedback (timeout 00:10:00) [common]
1189 02:45:35.090882 Listened to connection for namespace 'common' for up to 1s
1190 02:45:36.091828 Finalising connection for namespace 'common'
1191 02:45:36.092340 Disconnecting from shell: Finalise
1192 02:45:36.092624 =>
1193 02:45:36.193292 end: 4.2 read-feedback (duration 00:00:01) [common]
1194 02:45:36.193708 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/943514
1195 02:45:38.876425 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/943514
1196 02:45:38.877268 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.