Boot log: beaglebone-black
- Warnings: 3
- Kernel Warnings: 101
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 22:48:39.465794 lava-dispatcher, installed at version: 2024.01
2 22:48:39.466550 start: 0 validate
3 22:48:39.467027 Start time: 2024-10-16 22:48:39.466998+00:00 (UTC)
4 22:48:39.467545 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 22:48:39.468075 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 22:48:39.499644 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 22:48:39.500189 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 22:48:39.519833 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 22:48:39.520421 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 22:48:39.543053 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 22:48:39.543556 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 22:48:39.571157 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 22:48:39.571605 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 22:48:39.601654 validate duration: 0.13
16 22:48:39.602566 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:48:39.602884 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:48:39.603171 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:48:39.603757 Not decompressing ramdisk as can be used compressed.
20 22:48:39.604176 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 22:48:39.604510 saving as /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/ramdisk/initrd.cpio.gz
22 22:48:39.604780 total size: 4775763 (4 MB)
23 22:48:39.635335 progress 0 % (0 MB)
24 22:48:39.639338 progress 5 % (0 MB)
25 22:48:39.642479 progress 10 % (0 MB)
26 22:48:39.645490 progress 15 % (0 MB)
27 22:48:39.648879 progress 20 % (0 MB)
28 22:48:39.651865 progress 25 % (1 MB)
29 22:48:39.654885 progress 30 % (1 MB)
30 22:48:39.658242 progress 35 % (1 MB)
31 22:48:39.661169 progress 40 % (1 MB)
32 22:48:39.664106 progress 45 % (2 MB)
33 22:48:39.667014 progress 50 % (2 MB)
34 22:48:39.670196 progress 55 % (2 MB)
35 22:48:39.673012 progress 60 % (2 MB)
36 22:48:39.675882 progress 65 % (2 MB)
37 22:48:39.679093 progress 70 % (3 MB)
38 22:48:39.681924 progress 75 % (3 MB)
39 22:48:39.684752 progress 80 % (3 MB)
40 22:48:39.687665 progress 85 % (3 MB)
41 22:48:39.690864 progress 90 % (4 MB)
42 22:48:39.693668 progress 95 % (4 MB)
43 22:48:39.696544 progress 100 % (4 MB)
44 22:48:39.697174 4 MB downloaded in 0.09 s (49.31 MB/s)
45 22:48:39.697734 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:48:39.698698 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:48:39.698997 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:48:39.699280 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:48:39.699771 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 22:48:39.700039 saving as /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/kernel/zImage
52 22:48:39.700283 total size: 11440640 (10 MB)
53 22:48:39.700501 No compression specified
54 22:48:39.729953 progress 0 % (0 MB)
55 22:48:39.737105 progress 5 % (0 MB)
56 22:48:39.743971 progress 10 % (1 MB)
57 22:48:39.751096 progress 15 % (1 MB)
58 22:48:39.757795 progress 20 % (2 MB)
59 22:48:39.764890 progress 25 % (2 MB)
60 22:48:39.771558 progress 30 % (3 MB)
61 22:48:39.778671 progress 35 % (3 MB)
62 22:48:39.785360 progress 40 % (4 MB)
63 22:48:39.792382 progress 45 % (4 MB)
64 22:48:39.799083 progress 50 % (5 MB)
65 22:48:39.806083 progress 55 % (6 MB)
66 22:48:39.812736 progress 60 % (6 MB)
67 22:48:39.819323 progress 65 % (7 MB)
68 22:48:39.826404 progress 70 % (7 MB)
69 22:48:39.832913 progress 75 % (8 MB)
70 22:48:39.839573 progress 80 % (8 MB)
71 22:48:39.845873 progress 85 % (9 MB)
72 22:48:39.852459 progress 90 % (9 MB)
73 22:48:39.858796 progress 95 % (10 MB)
74 22:48:39.865396 progress 100 % (10 MB)
75 22:48:39.865876 10 MB downloaded in 0.17 s (65.89 MB/s)
76 22:48:39.866389 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:48:39.867243 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:48:39.867546 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:48:39.867826 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:48:39.868331 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 22:48:39.868625 saving as /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/dtb/am335x-boneblack.dtb
83 22:48:39.868844 total size: 70568 (0 MB)
84 22:48:39.869059 No compression specified
85 22:48:39.906207 progress 46 % (0 MB)
86 22:48:39.907002 progress 92 % (0 MB)
87 22:48:39.907712 progress 100 % (0 MB)
88 22:48:39.908116 0 MB downloaded in 0.04 s (1.71 MB/s)
89 22:48:39.908579 end: 1.3.1 http-download (duration 00:00:00) [common]
91 22:48:39.909407 end: 1.3 download-retry (duration 00:00:00) [common]
92 22:48:39.909695 start: 1.4 download-retry (timeout 00:10:00) [common]
93 22:48:39.910011 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 22:48:39.910490 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 22:48:39.910752 saving as /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/nfsrootfs/full.rootfs.tar
96 22:48:39.910966 total size: 117747780 (112 MB)
97 22:48:39.911183 Using unxz to decompress xz
98 22:48:39.940926 progress 0 % (0 MB)
99 22:48:40.664343 progress 5 % (5 MB)
100 22:48:41.394608 progress 10 % (11 MB)
101 22:48:42.151870 progress 15 % (16 MB)
102 22:48:42.857404 progress 20 % (22 MB)
103 22:48:43.431049 progress 25 % (28 MB)
104 22:48:44.220806 progress 30 % (33 MB)
105 22:48:45.011394 progress 35 % (39 MB)
106 22:48:45.350243 progress 40 % (44 MB)
107 22:48:45.722948 progress 45 % (50 MB)
108 22:48:46.381165 progress 50 % (56 MB)
109 22:48:47.178275 progress 55 % (61 MB)
110 22:48:47.894657 progress 60 % (67 MB)
111 22:48:48.598918 progress 65 % (73 MB)
112 22:48:49.349333 progress 70 % (78 MB)
113 22:48:50.093741 progress 75 % (84 MB)
114 22:48:50.816403 progress 80 % (89 MB)
115 22:48:51.518113 progress 85 % (95 MB)
116 22:48:52.303028 progress 90 % (101 MB)
117 22:48:53.060425 progress 95 % (106 MB)
118 22:48:53.874763 progress 100 % (112 MB)
119 22:48:53.886864 112 MB downloaded in 13.98 s (8.03 MB/s)
120 22:48:53.887787 end: 1.4.1 http-download (duration 00:00:14) [common]
122 22:48:53.889567 end: 1.4 download-retry (duration 00:00:14) [common]
123 22:48:53.890198 start: 1.5 download-retry (timeout 00:09:46) [common]
124 22:48:53.890775 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 22:48:53.891837 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 22:48:53.892359 saving as /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/modules/modules.tar
127 22:48:53.892814 total size: 6611188 (6 MB)
128 22:48:53.893280 Using unxz to decompress xz
129 22:48:53.932833 progress 0 % (0 MB)
130 22:48:53.966409 progress 5 % (0 MB)
131 22:48:54.009180 progress 10 % (0 MB)
132 22:48:54.052448 progress 15 % (0 MB)
133 22:48:54.094949 progress 20 % (1 MB)
134 22:48:54.142270 progress 25 % (1 MB)
135 22:48:54.185242 progress 30 % (1 MB)
136 22:48:54.229501 progress 35 % (2 MB)
137 22:48:54.272626 progress 40 % (2 MB)
138 22:48:54.316681 progress 45 % (2 MB)
139 22:48:54.358711 progress 50 % (3 MB)
140 22:48:54.401355 progress 55 % (3 MB)
141 22:48:54.448984 progress 60 % (3 MB)
142 22:48:54.492668 progress 65 % (4 MB)
143 22:48:54.535598 progress 70 % (4 MB)
144 22:48:54.581741 progress 75 % (4 MB)
145 22:48:54.624900 progress 80 % (5 MB)
146 22:48:54.666831 progress 85 % (5 MB)
147 22:48:54.709963 progress 90 % (5 MB)
148 22:48:54.753164 progress 95 % (6 MB)
149 22:48:54.796121 progress 100 % (6 MB)
150 22:48:54.809744 6 MB downloaded in 0.92 s (6.88 MB/s)
151 22:48:54.811171 end: 1.5.1 http-download (duration 00:00:01) [common]
153 22:48:54.813395 end: 1.5 download-retry (duration 00:00:01) [common]
154 22:48:54.813768 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 22:48:54.814166 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 22:49:10.846604 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/851213/extract-nfsrootfs-r5r98lox
157 22:49:10.847216 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 22:49:10.847542 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
159 22:49:10.848207 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_
160 22:49:10.848680 makedir: /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin
161 22:49:10.849072 makedir: /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/tests
162 22:49:10.849441 makedir: /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/results
163 22:49:10.849836 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-add-keys
164 22:49:10.850382 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-add-sources
165 22:49:10.850896 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-background-process-start
166 22:49:10.851392 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-background-process-stop
167 22:49:10.851887 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-common-functions
168 22:49:10.852360 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-echo-ipv4
169 22:49:10.852830 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-install-packages
170 22:49:10.853293 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-installed-packages
171 22:49:10.853750 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-os-build
172 22:49:10.854248 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-probe-channel
173 22:49:10.854732 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-probe-ip
174 22:49:10.855279 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-target-ip
175 22:49:10.855756 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-target-mac
176 22:49:10.856216 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-target-storage
177 22:49:10.856686 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-test-case
178 22:49:10.857151 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-test-event
179 22:49:10.857613 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-test-feedback
180 22:49:10.858115 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-test-raise
181 22:49:10.858601 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-test-reference
182 22:49:10.859109 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-test-runner
183 22:49:10.859584 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-test-set
184 22:49:10.860048 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-test-shell
185 22:49:10.860540 Updating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-add-keys (debian)
186 22:49:10.861063 Updating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-add-sources (debian)
187 22:49:10.861558 Updating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-install-packages (debian)
188 22:49:10.862071 Updating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-installed-packages (debian)
189 22:49:10.862562 Updating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/bin/lava-os-build (debian)
190 22:49:10.862983 Creating /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/environment
191 22:49:10.863341 LAVA metadata
192 22:49:10.863595 - LAVA_JOB_ID=851213
193 22:49:10.863805 - LAVA_DISPATCHER_IP=192.168.6.3
194 22:49:10.864147 start: 1.6.2.1 ssh-authorize (timeout 00:09:29) [common]
195 22:49:10.865054 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 22:49:10.865350 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:29) [common]
197 22:49:10.865554 skipped lava-vland-overlay
198 22:49:10.865791 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 22:49:10.866100 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:29) [common]
200 22:49:10.866301 skipped lava-multinode-overlay
201 22:49:10.866536 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 22:49:10.866781 start: 1.6.2.4 test-definition (timeout 00:09:29) [common]
203 22:49:10.867025 Loading test definitions
204 22:49:10.867294 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:29) [common]
205 22:49:10.867529 Using /lava-851213 at stage 0
206 22:49:10.868616 uuid=851213_1.6.2.4.1 testdef=None
207 22:49:10.868912 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 22:49:10.869171 start: 1.6.2.4.2 test-overlay (timeout 00:09:29) [common]
209 22:49:10.870703 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 22:49:10.871478 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:29) [common]
212 22:49:10.873353 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 22:49:10.874186 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:29) [common]
215 22:49:10.875943 runner path: /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/0/tests/0_timesync-off test_uuid 851213_1.6.2.4.1
216 22:49:10.876468 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 22:49:10.877258 start: 1.6.2.4.5 git-repo-action (timeout 00:09:29) [common]
219 22:49:10.877475 Using /lava-851213 at stage 0
220 22:49:10.877838 Fetching tests from https://github.com/kernelci/test-definitions.git
221 22:49:10.878130 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/0/tests/1_kselftest-dt'
222 22:49:14.384240 Running '/usr/bin/git checkout kernelci.org
223 22:49:14.713614 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 22:49:14.715043 uuid=851213_1.6.2.4.5 testdef=None
225 22:49:14.715384 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 22:49:14.716125 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 22:49:14.718911 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 22:49:14.719716 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 22:49:14.723354 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 22:49:14.724191 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 22:49:14.727707 runner path: /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/0/tests/1_kselftest-dt test_uuid 851213_1.6.2.4.5
235 22:49:14.727981 BOARD='beaglebone-black'
236 22:49:14.728185 BRANCH='lee-mfd'
237 22:49:14.728381 SKIPFILE='/dev/null'
238 22:49:14.728573 SKIP_INSTALL='True'
239 22:49:14.728763 TESTPROG_URL='http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 22:49:14.728958 TST_CASENAME=''
241 22:49:14.729150 TST_CMDFILES='dt'
242 22:49:14.729681 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 22:49:14.730481 Creating lava-test-runner.conf files
245 22:49:14.730685 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/851213/lava-overlay-tfrhu8z_/lava-851213/0 for stage 0
246 22:49:14.731045 - 0_timesync-off
247 22:49:14.731282 - 1_kselftest-dt
248 22:49:14.731611 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 22:49:14.731888 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 22:49:37.689448 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 22:49:37.689881 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:02) [common]
252 22:49:37.690173 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 22:49:37.690472 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 22:49:37.690759 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:02) [common]
255 22:49:38.041623 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 22:49:38.042110 start: 1.6.4 extract-modules (timeout 00:09:02) [common]
257 22:49:38.042375 extracting modules file /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/851213/extract-nfsrootfs-r5r98lox
258 22:49:38.915049 extracting modules file /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/851213/extract-overlay-ramdisk-ac2f47d3/ramdisk
259 22:49:39.823706 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 22:49:39.824155 start: 1.6.5 apply-overlay-tftp (timeout 00:09:00) [common]
261 22:49:39.824421 [common] Applying overlay to NFS
262 22:49:39.824639 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851213/compress-overlay-w006dk12/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/851213/extract-nfsrootfs-r5r98lox
263 22:49:42.549067 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 22:49:42.549541 start: 1.6.6 prepare-kernel (timeout 00:08:57) [common]
265 22:49:42.549860 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:57) [common]
266 22:49:42.550160 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 22:49:42.550425 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 22:49:42.550696 start: 1.6.7 configure-preseed-file (timeout 00:08:57) [common]
269 22:49:42.550953 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 22:49:42.551219 start: 1.6.8 compress-ramdisk (timeout 00:08:57) [common]
271 22:49:42.551449 Building ramdisk /var/lib/lava/dispatcher/tmp/851213/extract-overlay-ramdisk-ac2f47d3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/851213/extract-overlay-ramdisk-ac2f47d3/ramdisk
272 22:49:43.530326 >> 74888 blocks
273 22:49:48.075724 Adding RAMdisk u-boot header.
274 22:49:48.076404 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/851213/extract-overlay-ramdisk-ac2f47d3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/851213/extract-overlay-ramdisk-ac2f47d3/ramdisk.cpio.gz.uboot
275 22:49:48.263094 output: Image Name:
276 22:49:48.263500 output: Created: Wed Oct 16 22:49:48 2024
277 22:49:48.263894 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 22:49:48.264305 output: Data Size: 14791180 Bytes = 14444.51 KiB = 14.11 MiB
279 22:49:48.264710 output: Load Address: 00000000
280 22:49:48.265102 output: Entry Point: 00000000
281 22:49:48.265489 output:
282 22:49:48.266512 rename /var/lib/lava/dispatcher/tmp/851213/extract-overlay-ramdisk-ac2f47d3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/ramdisk/ramdisk.cpio.gz.uboot
283 22:49:48.267213 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 22:49:48.267761 end: 1.6 prepare-tftp-overlay (duration 00:00:53) [common]
285 22:49:48.268281 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:51) [common]
286 22:49:48.268733 No LXC device requested
287 22:49:48.269229 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 22:49:48.269733 start: 1.8 deploy-device-env (timeout 00:08:51) [common]
289 22:49:48.270260 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 22:49:48.270672 Checking files for TFTP limit of 4294967296 bytes.
291 22:49:48.273308 end: 1 tftp-deploy (duration 00:01:09) [common]
292 22:49:48.273897 start: 2 uboot-action (timeout 00:05:00) [common]
293 22:49:48.274430 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 22:49:48.274927 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 22:49:48.275422 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 22:49:48.276161 substitutions:
297 22:49:48.276575 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 22:49:48.276972 - {DTB_ADDR}: 0x88000000
299 22:49:48.277366 - {DTB}: 851213/tftp-deploy-ctcwvbpz/dtb/am335x-boneblack.dtb
300 22:49:48.277754 - {INITRD}: 851213/tftp-deploy-ctcwvbpz/ramdisk/ramdisk.cpio.gz.uboot
301 22:49:48.278177 - {KERNEL_ADDR}: 0x82000000
302 22:49:48.278565 - {KERNEL}: 851213/tftp-deploy-ctcwvbpz/kernel/zImage
303 22:49:48.278951 - {LAVA_MAC}: None
304 22:49:48.279378 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/851213/extract-nfsrootfs-r5r98lox
305 22:49:48.279770 - {NFS_SERVER_IP}: 192.168.6.3
306 22:49:48.280155 - {PRESEED_CONFIG}: None
307 22:49:48.280537 - {PRESEED_LOCAL}: None
308 22:49:48.280917 - {RAMDISK_ADDR}: 0x83000000
309 22:49:48.281295 - {RAMDISK}: 851213/tftp-deploy-ctcwvbpz/ramdisk/ramdisk.cpio.gz.uboot
310 22:49:48.281676 - {ROOT_PART}: None
311 22:49:48.282085 - {ROOT}: None
312 22:49:48.282464 - {SERVER_IP}: 192.168.6.3
313 22:49:48.282842 - {TEE_ADDR}: 0x83000000
314 22:49:48.283218 - {TEE}: None
315 22:49:48.283596 Parsed boot commands:
316 22:49:48.283962 - setenv autoload no
317 22:49:48.284336 - setenv initrd_high 0xffffffff
318 22:49:48.284709 - setenv fdt_high 0xffffffff
319 22:49:48.285082 - dhcp
320 22:49:48.285454 - setenv serverip 192.168.6.3
321 22:49:48.285845 - tftp 0x82000000 851213/tftp-deploy-ctcwvbpz/kernel/zImage
322 22:49:48.286227 - tftp 0x83000000 851213/tftp-deploy-ctcwvbpz/ramdisk/ramdisk.cpio.gz.uboot
323 22:49:48.286608 - setenv initrd_size ${filesize}
324 22:49:48.286985 - tftp 0x88000000 851213/tftp-deploy-ctcwvbpz/dtb/am335x-boneblack.dtb
325 22:49:48.287361 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/851213/extract-nfsrootfs-r5r98lox,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 22:49:48.287745 - bootz 0x82000000 0x83000000 0x88000000
327 22:49:48.288230 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 22:49:48.289683 start: 2.3 connect-device (timeout 00:05:00) [common]
330 22:49:48.290148 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 22:49:48.303520 Setting prompt string to ['lava-test: # ']
332 22:49:48.305361 end: 2.3 connect-device (duration 00:00:00) [common]
333 22:49:48.306077 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 22:49:48.306681 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 22:49:48.307250 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 22:49:48.308495 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 22:49:48.341573 >> OK - accepted request
338 22:49:48.343517 Returned 0 in 0 seconds
339 22:49:48.444595 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 22:49:48.446341 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 22:49:48.446970 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 22:49:48.447524 Setting prompt string to ['Hit any key to stop autoboot']
344 22:49:48.448020 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 22:49:48.449775 Trying 192.168.56.22...
346 22:49:48.450328 Connected to conserv3.
347 22:49:48.450807 Escape character is '^]'.
348 22:49:48.451266
349 22:49:48.451730 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 22:49:48.452230
351 22:49:57.188225
352 22:49:57.195125 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 22:49:57.195674 Trying to boot from MMC1
354 22:50:01.247290
355 22:50:01.253983 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 22:50:01.254560 Trying to boot from MMC1
357 22:50:03.939840
358 22:50:03.946770 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 22:50:03.947295 Trying to boot from MMC1
360 22:50:04.530312
361 22:50:04.530975
362 22:50:04.535804 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 22:50:04.536343
364 22:50:04.536830 CPU : AM335X-GP rev 2.0
365 22:50:04.541004 Model: TI AM335x BeagleBone Black
366 22:50:04.541499 DRAM: 512 MiB
367 22:50:04.620705 Core: 160 devices, 18 uclasses, devicetree: separate
368 22:50:04.634729 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 22:50:05.035482 NAND: 0 MiB
370 22:50:05.045747 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 22:50:05.160627 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 22:50:05.181951 <ethaddr> not set. Validating first E-fuse MAC
373 22:50:05.212362 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 22:50:05.270969 Hit any key to stop autoboot: 2
376 22:50:05.271862 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 22:50:05.272579 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 22:50:05.273150 Setting prompt string to ['=>']
379 22:50:05.273691 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 22:50:05.280818 0
381 22:50:05.281790 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 22:50:05.282423 Sending with 10 millisecond of delay
384 22:50:06.418749 => setenv autoload no
385 22:50:06.429540 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 22:50:06.434555 setenv autoload no
387 22:50:06.435277 Sending with 10 millisecond of delay
389 22:50:08.232576 => setenv initrd_high 0xffffffff
390 22:50:08.243356 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 22:50:08.244296 setenv initrd_high 0xffffffff
392 22:50:08.244997 Sending with 10 millisecond of delay
394 22:50:09.862408 => setenv fdt_high 0xffffffff
395 22:50:09.873144 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 22:50:09.874039 setenv fdt_high 0xffffffff
397 22:50:09.874749 Sending with 10 millisecond of delay
399 22:50:10.166496 => dhcp
400 22:50:10.177188 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 22:50:10.178034 dhcp
402 22:50:10.178478 link up on port 0, speed 100, full duplex
403 22:50:10.178886 BOOTP broadcast 1
404 22:50:10.431934 BOOTP broadcast 2
405 22:50:10.933902 BOOTP broadcast 3
406 22:50:11.935799 BOOTP broadcast 4
407 22:50:13.936867 BOOTP broadcast 5
408 22:50:13.998680 DHCP client bound to address 192.168.6.78 (3816 ms)
409 22:50:13.999429 Sending with 10 millisecond of delay
411 22:50:15.690527 => setenv serverip 192.168.6.3
412 22:50:15.701322 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
413 22:50:15.702229 setenv serverip 192.168.6.3
414 22:50:15.702993 Sending with 10 millisecond of delay
416 22:50:19.185858 => tftp 0x82000000 851213/tftp-deploy-ctcwvbpz/kernel/zImage
417 22:50:19.198525 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
418 22:50:19.199656 tftp 0x82000000 851213/tftp-deploy-ctcwvbpz/kernel/zImage
419 22:50:19.200149 link up on port 0, speed 100, full duplex
420 22:50:19.201326 Using ethernet@4a100000 device
421 22:50:19.206851 TFTP from server 192.168.6.3; our IP address is 192.168.6.78
422 22:50:19.214197 Filename '851213/tftp-deploy-ctcwvbpz/kernel/zImage'.
423 22:50:19.214761 Load address: 0x82000000
424 22:50:21.333210 Loading: *################################################## 10.9 MiB
425 22:50:21.333913 5.2 MiB/s
426 22:50:21.334368 done
427 22:50:21.336420 Bytes transferred = 11440640 (ae9200 hex)
428 22:50:21.337190 Sending with 10 millisecond of delay
430 22:50:25.785160 => tftp 0x83000000 851213/tftp-deploy-ctcwvbpz/ramdisk/ramdisk.cpio.gz.uboot
431 22:50:25.796042 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
432 22:50:25.796972 tftp 0x83000000 851213/tftp-deploy-ctcwvbpz/ramdisk/ramdisk.cpio.gz.uboot
433 22:50:25.797482 link up on port 0, speed 100, full duplex
434 22:50:25.800797 Using ethernet@4a100000 device
435 22:50:25.806316 TFTP from server 192.168.6.3; our IP address is 192.168.6.78
436 22:50:25.815019 Filename '851213/tftp-deploy-ctcwvbpz/ramdisk/ramdisk.cpio.gz.uboot'.
437 22:50:25.815511 Load address: 0x83000000
438 22:50:28.633550 Loading: *################################################## 14.1 MiB
439 22:50:28.634231 5 MiB/s
440 22:50:28.634706 done
441 22:50:28.636650 Bytes transferred = 14791244 (e1b24c hex)
442 22:50:28.637426 Sending with 10 millisecond of delay
444 22:50:30.495251 => setenv initrd_size ${filesize}
445 22:50:30.506081 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
446 22:50:30.506952 setenv initrd_size ${filesize}
447 22:50:30.507706 Sending with 10 millisecond of delay
449 22:50:34.654238 => tftp 0x88000000 851213/tftp-deploy-ctcwvbpz/dtb/am335x-boneblack.dtb
450 22:50:34.665083 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
451 22:50:34.666053 tftp 0x88000000 851213/tftp-deploy-ctcwvbpz/dtb/am335x-boneblack.dtb
452 22:50:34.666552 link up on port 0, speed 100, full duplex
453 22:50:34.669924 Using ethernet@4a100000 device
454 22:50:34.675487 TFTP from server 192.168.6.3; our IP address is 192.168.6.78
455 22:50:34.686529 Filename '851213/tftp-deploy-ctcwvbpz/dtb/am335x-boneblack.dtb'.
456 22:50:34.686851 Load address: 0x88000000
457 22:50:34.696921 Loading: *################################################## 68.9 KiB
458 22:50:34.697457 4.8 MiB/s
459 22:50:34.705412 done
460 22:50:34.705936 Bytes transferred = 70568 (113a8 hex)
461 22:50:34.706733 Sending with 10 millisecond of delay
463 22:50:47.883389 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/851213/extract-nfsrootfs-r5r98lox,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
464 22:50:47.894218 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
465 22:50:47.895116 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/851213/extract-nfsrootfs-r5r98lox,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
466 22:50:47.895879 Sending with 10 millisecond of delay
468 22:50:50.235282 => bootz 0x82000000 0x83000000 0x88000000
469 22:50:50.246165 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
470 22:50:50.246767 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
471 22:50:50.247859 bootz 0x82000000 0x83000000 0x88000000
472 22:50:50.248367 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
473 22:50:50.248911 ## Loading init Ramdisk from Legacy Image at 83000000 ...
474 22:50:50.253747 Image Name:
475 22:50:50.254290 Created: 2024-10-16 22:49:48 UTC
476 22:50:50.262645 Image Type: ARM Linux RAMDisk Image (uncompressed)
477 22:50:50.263161 Data Size: 14791180 Bytes = 14.1 MiB
478 22:50:50.271113 Load Address: 00000000
479 22:50:50.271620 Entry Point: 00000000
480 22:50:50.439337 Verifying Checksum ... OK
481 22:50:50.439847 ## Flattened Device Tree blob at 88000000
482 22:50:50.445903 Booting using the fdt blob at 0x88000000
483 22:50:50.446403 Working FDT set to 88000000
484 22:50:50.451449 Using Device Tree in place at 88000000, end 880143a7
485 22:50:50.455843 Working FDT set to 88000000
486 22:50:50.469373
487 22:50:50.469896 Starting kernel ...
488 22:50:50.470348
489 22:50:50.471287 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
490 22:50:50.471926 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
491 22:50:50.472432 Setting prompt string to ['Linux version [0-9]']
492 22:50:50.472925 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
493 22:50:50.473432 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
494 22:50:51.312460 [ 0.000000] Booting Linux on physical CPU 0x0
495 22:50:51.318575 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
496 22:50:51.319146 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
497 22:50:51.319652 Setting prompt string to []
498 22:50:51.320182 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
499 22:50:51.320680 Using line separator: #'\n'#
500 22:50:51.321126 No login prompt set.
501 22:50:51.321592 Parsing kernel messages
502 22:50:51.322097 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
503 22:50:51.322968 [login-action] Waiting for messages, (timeout 00:03:57)
504 22:50:51.323456 Waiting using forced prompt support (timeout 00:01:58)
505 22:50:51.332513 [ 0.000000] Linux version 6.12.0-rc1 (KernelCI@build-j343830-arm-gcc-12-multi-v7-defconfig-8xrg2) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Wed Oct 16 08:45:40 UTC 2024
506 22:50:51.343857 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
507 22:50:51.346956 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
508 22:50:51.352588 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
509 22:50:51.364176 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
510 22:50:51.364666 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
511 22:50:51.369917 [ 0.000000] Memory policy: Data cache writeback
512 22:50:51.376489 [ 0.000000] efi: UEFI not found.
513 22:50:51.380777 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
514 22:50:51.387500 [ 0.000000] Zone ranges:
515 22:50:51.392973 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
516 22:50:51.398827 [ 0.000000] Normal empty
517 22:50:51.399305 [ 0.000000] HighMem empty
518 22:50:51.401751 [ 0.000000] Movable zone start for each node
519 22:50:51.407468 [ 0.000000] Early memory node ranges
520 22:50:51.413205 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
521 22:50:51.421324 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
522 22:50:51.446822 [ 0.000000] CPU: All CPU(s) started in SVC mode.
523 22:50:51.452389 [ 0.000000] AM335X ES2.0 (sgx neon)
524 22:50:51.464150 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
525 22:50:51.481793 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/851213/extract-nfsrootfs-r5r98lox,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
526 22:50:51.493325 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
527 22:50:51.499067 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
528 22:50:51.504810 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
529 22:50:51.514824 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
530 22:50:51.543982 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
531 22:50:51.549869 <6>[ 0.000000] trace event string verifier disabled
532 22:50:51.550378 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
533 22:50:51.557892 <6>[ 0.000000] rcu: RCU event tracing is enabled.
534 22:50:51.563628 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
535 22:50:51.575147 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
536 22:50:51.579985 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
537 22:50:51.594868 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
538 22:50:51.611976 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
539 22:50:51.618725 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
540 22:50:51.710231 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
541 22:50:51.721697 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
542 22:50:51.728562 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
543 22:50:51.741624 <6>[ 0.019143] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
544 22:50:51.748826 <6>[ 0.033920] Console: colour dummy device 80x30
545 22:50:51.754985 Matched prompt #6: WARNING:
546 22:50:51.755548 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
547 22:50:51.760291 <3>[ 0.038816] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
548 22:50:51.766048 <3>[ 0.045886] This ensures that you still see kernel messages. Please
549 22:50:51.769255 <3>[ 0.052613] update your kernel commandline.
550 22:50:51.810079 <6>[ 0.057225] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
551 22:50:51.815744 <6>[ 0.096152] CPU: Testing write buffer coherency: ok
552 22:50:51.821684 <6>[ 0.101518] CPU0: Spectre v2: using BPIALL workaround
553 22:50:51.822225 <6>[ 0.106986] pid_max: default: 32768 minimum: 301
554 22:50:51.833212 <6>[ 0.112180] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 22:50:51.840084 <6>[ 0.120001] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
556 22:50:51.847085 <6>[ 0.129349] CPU0: thread -1, cpu 0, socket -1, mpidr 0
557 22:50:51.922641 <6>[ 0.199525] Setting up static identity map for 0x80300000 - 0x803000ac
558 22:50:51.928561 <6>[ 0.209104] rcu: Hierarchical SRCU implementation.
559 22:50:51.932174 <6>[ 0.214394] rcu: Max phase no-delay instances is 1000.
560 22:50:51.940837 <6>[ 0.225391] EFI services will not be available.
561 22:50:51.946378 <6>[ 0.230765] smp: Bringing up secondary CPUs ...
562 22:50:51.952218 <6>[ 0.235732] smp: Brought up 1 node, 1 CPU
563 22:50:51.960241 <6>[ 0.240204] SMP: Total of 1 processors activated (996.14 BogoMIPS).
564 22:50:51.966193 <6>[ 0.246924] CPU: All CPU(s) started in SVC mode.
565 22:50:51.978324 <6>[ 0.252129] Memory: 405996K/522240K available (16384K kernel code, 2542K rwdata, 6788K rodata, 2048K init, 431K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
566 22:50:51.984226 <6>[ 0.268400] devtmpfs: initialized
567 22:50:52.006642 <6>[ 0.285714] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
568 22:50:52.018130 <6>[ 0.294309] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
569 22:50:52.024119 <6>[ 0.304749] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
570 22:50:52.034794 <6>[ 0.317002] pinctrl core: initialized pinctrl subsystem
571 22:50:52.044064 <6>[ 0.327629] DMI not present or invalid.
572 22:50:52.052378 <6>[ 0.333481] NET: Registered PF_NETLINK/PF_ROUTE protocol family
573 22:50:52.061880 <6>[ 0.342427] DMA: preallocated 256 KiB pool for atomic coherent allocations
574 22:50:52.076926 <6>[ 0.353814] thermal_sys: Registered thermal governor 'step_wise'
575 22:50:52.077423 <6>[ 0.353986] cpuidle: using governor menu
576 22:50:52.104614 <6>[ 0.389742] No ATAGs?
577 22:50:52.110731 <6>[ 0.392385] hw-breakpoint: debug architecture 0x4 unsupported.
578 22:50:52.120904 <6>[ 0.404314] Serial: AMBA PL011 UART driver
579 22:50:52.150595 <6>[ 0.435625] iommu: Default domain type: Translated
580 22:50:52.159686 <6>[ 0.440977] iommu: DMA domain TLB invalidation policy: strict mode
581 22:50:52.186671 <5>[ 0.470388] SCSI subsystem initialized
582 22:50:52.201041 <6>[ 0.480527] usbcore: registered new interface driver usbfs
583 22:50:52.207898 <6>[ 0.486489] usbcore: registered new interface driver hub
584 22:50:52.208375 <6>[ 0.492311] usbcore: registered new device driver usb
585 22:50:52.213701 <6>[ 0.498798] pps_core: LinuxPPS API ver. 1 registered
586 22:50:52.225178 <6>[ 0.504250] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
587 22:50:52.234079 <6>[ 0.513956] PTP clock support registered
588 22:50:52.234561 <6>[ 0.518404] EDAC MC: Ver: 3.0.0
589 22:50:52.281724 <6>[ 0.564159] scmi_core: SCMI protocol bus registered
590 22:50:52.296957 <6>[ 0.581479] vgaarb: loaded
591 22:50:52.303066 <6>[ 0.585245] clocksource: Switched to clocksource dmtimer
592 22:50:52.336717 <6>[ 0.621434] NET: Registered PF_INET protocol family
593 22:50:52.349468 <6>[ 0.627128] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
594 22:50:52.355092 <6>[ 0.635963] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
595 22:50:52.366968 <6>[ 0.644848] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
596 22:50:52.372487 <6>[ 0.653127] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
597 22:50:52.383947 <6>[ 0.661415] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
598 22:50:52.389793 <6>[ 0.669141] TCP: Hash tables configured (established 4096 bind 4096)
599 22:50:52.395628 <6>[ 0.676060] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
600 22:50:52.401513 <6>[ 0.683072] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
601 22:50:52.408986 <6>[ 0.690684] NET: Registered PF_UNIX/PF_LOCAL protocol family
602 22:50:52.495068 <6>[ 0.774451] RPC: Registered named UNIX socket transport module.
603 22:50:52.495662 <6>[ 0.780900] RPC: Registered udp transport module.
604 22:50:52.500883 <6>[ 0.786026] RPC: Registered tcp transport module.
605 22:50:52.506752 <6>[ 0.791131] RPC: Registered tcp-with-tls transport module.
606 22:50:52.519731 <6>[ 0.797050] RPC: Registered tcp NFSv4.1 backchannel transport module.
607 22:50:52.520297 <6>[ 0.803957] PCI: CLS 0 bytes, default 64
608 22:50:52.526789 <5>[ 0.809736] Initialise system trusted keyrings
609 22:50:52.548096 <6>[ 0.830112] Trying to unpack rootfs image as initramfs...
610 22:50:52.626930 <6>[ 0.905816] workingset: timestamp_bits=30 max_order=17 bucket_order=0
611 22:50:52.631768 <6>[ 0.913330] squashfs: version 4.0 (2009/01/31) Phillip Lougher
612 22:50:52.670367 <5>[ 0.955389] NFS: Registering the id_resolver key type
613 22:50:52.676082 <5>[ 0.960972] Key type id_resolver registered
614 22:50:52.681908 <5>[ 0.965595] Key type id_legacy registered
615 22:50:52.690354 <6>[ 0.970030] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
616 22:50:52.697251 <6>[ 0.977220] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
617 22:50:52.767360 <5>[ 1.052365] Key type asymmetric registered
618 22:50:52.773178 <5>[ 1.056941] Asymmetric key parser 'x509' registered
619 22:50:52.781683 <6>[ 1.062369] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
620 22:50:52.787495 <6>[ 1.070291] io scheduler mq-deadline registered
621 22:50:52.796096 <6>[ 1.075260] io scheduler kyber registered
622 22:50:52.796597 <6>[ 1.079712] io scheduler bfq registered
623 22:50:52.904726 <6>[ 1.186090] ledtrig-cpu: registered to indicate activity on CPUs
624 22:50:53.224807 <6>[ 1.505947] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
625 22:50:53.264490 <6>[ 1.549377] msm_serial: driver initialized
626 22:50:53.270551 <6>[ 1.554148] SuperH (H)SCI(F) driver initialized
627 22:50:53.276402 <6>[ 1.559410] STMicroelectronics ASC driver initialized
628 22:50:53.281623 <6>[ 1.565006] STM32 USART driver initialized
629 22:50:53.407551 <6>[ 1.691921] brd: module loaded
630 22:50:53.437944 <6>[ 1.722183] loop: module loaded
631 22:50:53.479112 <6>[ 1.763224] CAN device driver interface
632 22:50:53.485839 <6>[ 1.768503] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
633 22:50:53.491557 <6>[ 1.775587] e1000e: Intel(R) PRO/1000 Network Driver
634 22:50:53.497436 <6>[ 1.780975] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
635 22:50:53.503121 <6>[ 1.787445] igb: Intel(R) Gigabit Ethernet Network Driver
636 22:50:53.511397 <6>[ 1.793267] igb: Copyright (c) 2007-2014 Intel Corporation.
637 22:50:53.523020 <6>[ 1.802458] pegasus: Pegasus/Pegasus II USB Ethernet driver
638 22:50:53.528890 <6>[ 1.808614] usbcore: registered new interface driver pegasus
639 22:50:53.534698 <6>[ 1.814739] usbcore: registered new interface driver asix
640 22:50:53.540481 <6>[ 1.820619] usbcore: registered new interface driver ax88179_178a
641 22:50:53.546225 <6>[ 1.827211] usbcore: registered new interface driver cdc_ether
642 22:50:53.551991 <6>[ 1.833508] usbcore: registered new interface driver smsc75xx
643 22:50:53.557804 <6>[ 1.839750] usbcore: registered new interface driver smsc95xx
644 22:50:53.563570 <6>[ 1.846000] usbcore: registered new interface driver net1080
645 22:50:53.569347 <6>[ 1.852131] usbcore: registered new interface driver cdc_subset
646 22:50:53.575139 <6>[ 1.858543] usbcore: registered new interface driver zaurus
647 22:50:53.582911 <6>[ 1.864588] usbcore: registered new interface driver cdc_ncm
648 22:50:53.592435 <6>[ 1.873956] usbcore: registered new interface driver usb-storage
649 22:50:53.877108 <6>[ 2.160234] i2c_dev: i2c /dev entries driver
650 22:50:53.933225 <5>[ 2.210405] cpuidle: enable-method property 'ti,am3352' found operations
651 22:50:53.939126 <6>[ 2.219924] sdhci: Secure Digital Host Controller Interface driver
652 22:50:53.946867 <6>[ 2.226693] sdhci: Copyright(c) Pierre Ossman
653 22:50:53.954095 <6>[ 2.233071] Synopsys Designware Multimedia Card Interface Driver
654 22:50:53.959136 <6>[ 2.241014] sdhci-pltfm: SDHCI platform and OF driver helper
655 22:50:54.079466 <6>[ 2.357198] usbcore: registered new interface driver usbhid
656 22:50:54.079993 <6>[ 2.363241] usbhid: USB HID core driver
657 22:50:54.119000 <6>[ 2.401499] NET: Registered PF_INET6 protocol family
658 22:50:54.166206 <6>[ 2.451252] Segment Routing with IPv6
659 22:50:54.171999 <6>[ 2.455500] In-situ OAM (IOAM) with IPv6
660 22:50:54.178635 <6>[ 2.459906] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
661 22:50:54.184423 <6>[ 2.467187] NET: Registered PF_PACKET protocol family
662 22:50:54.190229 <6>[ 2.472675] can: controller area network core
663 22:50:54.196114 <6>[ 2.477555] NET: Registered PF_CAN protocol family
664 22:50:54.196581 <6>[ 2.482759] can: raw protocol
665 22:50:54.201920 <6>[ 2.486110] can: broadcast manager protocol
666 22:50:54.208375 <6>[ 2.490690] can: netlink gateway - max_hops=1
667 22:50:54.214443 <5>[ 2.496210] Key type dns_resolver registered
668 22:50:54.220789 <6>[ 2.501200] ThumbEE CPU extension supported.
669 22:50:54.221255 <5>[ 2.505988] Registering SWP/SWPB emulation handler
670 22:50:54.230545 <3>[ 2.511645] omap_voltage_late_init: Voltage driver support not added
671 22:50:54.423807 <5>[ 2.706346] Loading compiled-in X.509 certificates
672 22:50:54.551995 <6>[ 2.823973] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
673 22:50:54.559063 <6>[ 2.840657] pinctrl-single 44e10800.pinmux: 142 pins, size 568
674 22:50:54.585143 <3>[ 2.864214] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
675 22:50:54.777035 <3>[ 3.056052] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
676 22:50:54.992383 <6>[ 3.275796] OMAP GPIO hardware version 0.1
677 22:50:55.011892 <6>[ 3.294321] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
678 22:50:55.096288 <4>[ 3.377486] at24 2-0054: supply vcc not found, using dummy regulator
679 22:50:55.138621 <4>[ 3.419814] at24 2-0055: supply vcc not found, using dummy regulator
680 22:50:55.185690 <4>[ 3.466916] at24 2-0056: supply vcc not found, using dummy regulator
681 22:50:55.219792 <4>[ 3.501006] at24 2-0057: supply vcc not found, using dummy regulator
682 22:50:55.256168 <6>[ 3.538201] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
683 22:50:55.334007 <3>[ 3.611982] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
684 22:50:55.358485 <6>[ 3.632736] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
685 22:50:55.380405 <4>[ 3.658834] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
686 22:50:55.388213 <4>[ 3.668044] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
687 22:50:55.504324 <6>[ 3.785630] omap_rng 48310000.rng: Random Number Generator ver. 20
688 22:50:55.527852 <5>[ 3.811951] random: crng init done
689 22:50:55.565735 <6>[ 3.849688] Freeing initrd memory: 14448K
690 22:50:55.575499 <6>[ 3.855359] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
691 22:50:55.628777 <6>[ 3.907655] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
692 22:50:55.634569 <4>[ 3.917970] ------------[ cut here ]------------
693 22:50:55.646099 <4>[ 3.923002] WARNING: CPU: 0 PID: 38 at drivers/base/regmap/regmap.c:1208 devm_regmap_field_alloc+0xb8/0xc4
694 22:50:55.651910 <4>[ 3.933299] invalid empty mask defined
695 22:50:55.652414 <4>[ 3.937449] Modules linked in:
696 22:50:55.657581 <4>[ 3.940872] CPU: 0 UID: 0 PID: 38 Comm: kworker/u4:4 Not tainted 6.12.0-rc1 #1
697 22:50:55.669072 <4>[ 3.948574] Hardware name: Generic AM33XX (Flattened Device Tree)
698 22:50:55.674852 <4>[ 3.955112] Workqueue: events_unbound deferred_probe_work_func
699 22:50:55.675381 <4>[ 3.961394] Call trace:
700 22:50:55.680596 <4>[ 3.961413] unwind_backtrace from show_stack+0x10/0x14
701 22:50:55.686310 <4>[ 3.969941] show_stack from dump_stack_lvl+0x68/0x74
702 22:50:55.692174 <4>[ 3.975421] dump_stack_lvl from __warn+0x7c/0x12c
703 22:50:55.697848 <4>[ 3.980636] __warn from warn_slowpath_fmt+0x124/0x190
704 22:50:55.703606 <4>[ 3.986202] warn_slowpath_fmt from devm_regmap_field_alloc+0xb8/0xc4
705 22:50:55.709322 <4>[ 3.993107] devm_regmap_field_alloc from cpsw_ale_create+0x124/0x368
706 22:50:55.720725 <4>[ 4.000030] cpsw_ale_create from cpsw_init_common+0x238/0x37c
707 22:50:55.726560 <4>[ 4.006306] cpsw_init_common from cpsw_probe+0x530/0xc60
708 22:50:55.732323 <4>[ 4.012140] cpsw_probe from platform_probe+0x5c/0xb0
709 22:50:55.738092 <4>[ 4.017619] platform_probe from really_probe+0xc8/0x2c8
710 22:50:55.743834 <4>[ 4.023363] really_probe from __driver_probe_device+0x88/0x19c
711 22:50:55.749536 <4>[ 4.029729] __driver_probe_device from driver_probe_device+0x30/0x104
712 22:50:55.755277 <4>[ 4.036723] driver_probe_device from __device_attach_driver+0x94/0x108
713 22:50:55.761006 <4>[ 4.043804] __device_attach_driver from bus_for_each_drv+0x90/0xe4
714 22:50:55.766729 <4>[ 4.050527] bus_for_each_drv from __device_attach+0xa8/0x1a4
715 22:50:55.772474 <4>[ 4.056711] __device_attach from bus_probe_device+0x88/0x8c
716 22:50:55.778244 <4>[ 4.062810] bus_probe_device from device_add+0x5a8/0x77c
717 22:50:55.789623 <4>[ 4.068637] device_add from of_platform_device_create_pdata+0x90/0xbc
718 22:50:55.795439 <4>[ 4.075639] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
719 22:50:55.801183 <4>[ 4.083882] of_platform_bus_create from of_platform_populate+0x70/0xd4
720 22:50:55.806908 <4>[ 4.090965] of_platform_populate from sysc_probe+0x100c/0x1418
721 22:50:55.812660 <4>[ 4.097337] sysc_probe from platform_probe+0x5c/0xb0
722 22:50:55.818360 <4>[ 4.102807] platform_probe from really_probe+0xc8/0x2c8
723 22:50:55.824208 <4>[ 4.108549] really_probe from __driver_probe_device+0x88/0x19c
724 22:50:55.835496 <4>[ 4.114916] __driver_probe_device from driver_probe_device+0x30/0x104
725 22:50:55.841306 <4>[ 4.121907] driver_probe_device from __device_attach_driver+0x94/0x108
726 22:50:55.847170 <4>[ 4.128987] __device_attach_driver from bus_for_each_drv+0x90/0xe4
727 22:50:55.852792 <4>[ 4.135708] bus_for_each_drv from __device_attach+0xa8/0x1a4
728 22:50:55.858533 <4>[ 4.141894] __device_attach from bus_probe_device+0x88/0x8c
729 22:50:55.864250 <4>[ 4.147992] bus_probe_device from device_add+0x5a8/0x77c
730 22:50:55.869995 <4>[ 4.153819] device_add from of_platform_device_create_pdata+0x90/0xbc
731 22:50:55.881377 <4>[ 4.160810] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
732 22:50:55.887186 <4>[ 4.169053] of_platform_bus_create from of_platform_populate+0x70/0xd4
733 22:50:55.892900 <4>[ 4.176136] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
734 22:50:55.898636 <4>[ 4.182949] simple_pm_bus_probe from platform_probe+0x5c/0xb0
735 22:50:55.904387 <4>[ 4.189226] platform_probe from really_probe+0xc8/0x2c8
736 22:50:55.915791 <4>[ 4.194968] really_probe from __driver_probe_device+0x88/0x19c
737 22:50:55.921624 <4>[ 4.201332] __driver_probe_device from driver_probe_device+0x30/0x104
738 22:50:55.927326 <4>[ 4.208324] driver_probe_device from __device_attach_driver+0x94/0x108
739 22:50:55.933142 <4>[ 4.215405] __device_attach_driver from bus_for_each_drv+0x90/0xe4
740 22:50:55.938792 <4>[ 4.222126] bus_for_each_drv from __device_attach+0xa8/0x1a4
741 22:50:55.944540 <4>[ 4.228312] __device_attach from bus_probe_device+0x88/0x8c
742 22:50:55.950278 <4>[ 4.234409] bus_probe_device from device_add+0x5a8/0x77c
743 22:50:55.961706 <4>[ 4.240234] device_add from of_platform_device_create_pdata+0x90/0xbc
744 22:50:55.967477 <4>[ 4.247224] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
745 22:50:55.973202 <4>[ 4.255467] of_platform_bus_create from of_platform_populate+0x70/0xd4
746 22:50:55.978940 <4>[ 4.262549] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
747 22:50:55.984779 <4>[ 4.269359] simple_pm_bus_probe from platform_probe+0x5c/0xb0
748 22:50:55.990437 <4>[ 4.275634] platform_probe from really_probe+0xc8/0x2c8
749 22:50:56.001871 <4>[ 4.281374] really_probe from __driver_probe_device+0x88/0x19c
750 22:50:56.007670 <4>[ 4.287742] __driver_probe_device from driver_probe_device+0x30/0x104
751 22:50:56.013377 <4>[ 4.294734] driver_probe_device from __device_attach_driver+0x94/0x108
752 22:50:56.019140 <4>[ 4.301815] __device_attach_driver from bus_for_each_drv+0x90/0xe4
753 22:50:56.024861 <4>[ 4.308537] bus_for_each_drv from __device_attach+0xa8/0x1a4
754 22:50:56.030580 <4>[ 4.314724] __device_attach from bus_probe_device+0x88/0x8c
755 22:50:56.036331 <4>[ 4.320821] bus_probe_device from device_add+0x5a8/0x77c
756 22:50:56.047764 <4>[ 4.326648] device_add from of_platform_device_create_pdata+0x90/0xbc
757 22:50:56.053547 <4>[ 4.333637] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
758 22:50:56.059282 <4>[ 4.341882] of_platform_bus_create from of_platform_populate+0x70/0xd4
759 22:50:56.065147 <4>[ 4.348965] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
760 22:50:56.076446 <4>[ 4.355775] simple_pm_bus_probe from platform_probe+0x5c/0xb0
761 22:50:56.082219 <4>[ 4.362053] platform_probe from really_probe+0xc8/0x2c8
762 22:50:56.087933 <4>[ 4.367793] really_probe from __driver_probe_device+0x88/0x19c
763 22:50:56.093662 <4>[ 4.374159] __driver_probe_device from driver_probe_device+0x30/0x104
764 22:50:56.099421 <4>[ 4.381151] driver_probe_device from __device_attach_driver+0x94/0x108
765 22:50:56.105191 <4>[ 4.388232] __device_attach_driver from bus_for_each_drv+0x90/0xe4
766 22:50:56.110961 <4>[ 4.394955] bus_for_each_drv from __device_attach+0xa8/0x1a4
767 22:50:56.116663 <4>[ 4.401139] __device_attach from bus_probe_device+0x88/0x8c
768 22:50:56.128260 <4>[ 4.407232] bus_probe_device from deferred_probe_work_func+0x78/0xa4
769 22:50:56.133857 <4>[ 4.414133] deferred_probe_work_func from process_one_work+0x178/0x3c0
770 22:50:56.139606 <4>[ 4.421230] process_one_work from worker_thread+0x264/0x42c
771 22:50:56.145336 <4>[ 4.427334] worker_thread from kthread+0xe0/0xfc
772 22:50:56.151140 <4>[ 4.432463] kthread from ret_from_fork+0x14/0x28
773 22:50:56.156792 <4>[ 4.437579] Exception stack(0xe0131fb0 to 0xe0131ff8)
774 22:50:56.162663 <4>[ 4.443045] 1fa0: 00000000 00000000 00000000 00000000
775 22:50:56.173996 <4>[ 4.451729] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
776 22:50:56.179879 <4>[ 4.460409] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
777 22:50:56.185693 <4>[ 4.467591] ---[ end trace 0000000000000000 ]---
778 22:50:56.186767 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
779 22:50:56.187274 login-action: kernel 'warning'
780 22:50:56.187722 [login-action] Waiting for messages, (timeout 00:03:52)
781 22:50:56.188148 Waiting using forced prompt support (timeout 00:01:56)
782 22:50:56.191448 <6>[ 4.472688] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
783 22:50:56.197623 <6>[ 4.479974] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
784 22:50:56.209141 <6>[ 4.487555] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
785 22:50:56.220656 <6>[ 4.495693] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
786 22:50:56.228212 <6>[ 4.507329] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
787 22:50:56.238984 <5>[ 4.516402] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
788 22:50:56.266502 <3>[ 4.546069] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
789 22:50:56.272328 <6>[ 4.554536] edma 49000000.dma: TI EDMA DMA engine driver
790 22:50:56.343035 <3>[ 4.621787] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
791 22:50:56.357876 <6>[ 4.636253] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
792 22:50:56.370761 <3>[ 4.653321] l3-aon-clkctrl:0000:0: failed to disable
793 22:50:56.424249 <6>[ 4.703553] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
794 22:50:56.430095 <6>[ 4.713066] printk: legacy console [ttyS0] enabled
795 22:50:56.435687 <6>[ 4.713066] printk: legacy console [ttyS0] enabled
796 22:50:56.441300 <6>[ 4.723399] printk: legacy bootconsole [omap8250] disabled
797 22:50:56.447178 <6>[ 4.723399] printk: legacy bootconsole [omap8250] disabled
798 22:50:56.477756 <4>[ 4.756050] tps65217-pmic: Failed to locate of_node [id: -1]
799 22:50:56.481407 <4>[ 4.763430] tps65217-bl: Failed to locate of_node [id: -1]
800 22:50:56.497712 <6>[ 4.783063] tps65217 0-0024: TPS65217 ID 0xe version 1.2
801 22:50:56.518064 <6>[ 4.790053] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
802 22:50:56.529687 <6>[ 4.803750] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
803 22:50:56.533595 <6>[ 4.815632] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
804 22:50:56.555604 <6>[ 4.835392] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
805 22:50:56.561537 <6>[ 4.844450] sdhci-omap 48060000.mmc: Got CD GPIO
806 22:50:56.569611 <4>[ 4.849621] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
807 22:50:56.584252 <4>[ 4.863261] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
808 22:50:56.590700 <4>[ 4.871935] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
809 22:50:56.600419 <4>[ 4.880602] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
810 22:50:56.698968 <6>[ 4.979788] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
811 22:50:56.746554 <6>[ 5.026070] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
812 22:50:56.752954 <6>[ 5.034465] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
813 22:50:56.762062 <6>[ 5.043233] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
814 22:50:56.830683 <6>[ 5.112977] mmc1: new high speed MMC card at address 0001
815 22:50:56.838526 <6>[ 5.121686] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
816 22:50:56.855594 <6>[ 5.134027] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
817 22:50:56.863515 <6>[ 5.146316] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
818 22:50:56.878567 <6>[ 5.161940] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
819 22:50:56.887607 <6>[ 5.169182] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
820 22:50:56.938993 <6>[ 5.215061] mmc0: new high speed SDHC card at address aaaa
821 22:50:56.939473 <6>[ 5.222371] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
822 22:50:56.972627 <6>[ 5.255826] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
823 22:50:58.956891 <6>[ 7.236288] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
824 22:50:59.070314 <5>[ 7.275438] Sending DHCP requests ., OK
825 22:50:59.081621 <6>[ 7.359821] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.78
826 22:50:59.081961 <6>[ 7.367984] IP-Config: Complete:
827 22:50:59.092900 <6>[ 7.371523] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.78, mask=255.255.255.0, gw=192.168.6.1
828 22:50:59.098578 <6>[ 7.382040] host=192.168.6.78, domain=, nis-domain=(none)
829 22:50:59.110967 <6>[ 7.388249] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
830 22:50:59.111303 <6>[ 7.388283] nameserver0=192.168.6.1
831 22:50:59.117162 <6>[ 7.400757] clk: Disabling unused clocks
832 22:50:59.122771 <6>[ 7.405480] PM: genpd: Disabling unused power domains
833 22:50:59.142027 <6>[ 7.423848] Freeing unused kernel image (initmem) memory: 2048K
834 22:50:59.149532 <6>[ 7.433590] Run /init as init process
835 22:50:59.174839 Loading, please wait...
836 22:50:59.250402 Starting systemd-udevd version 252.22-1~deb12u1
837 22:51:02.279343 <4>[ 10.557044] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
838 22:51:02.500209 <4>[ 10.778039] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
839 22:51:02.649335 <6>[ 10.934583] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
840 22:51:02.660262 <6>[ 10.940481] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
841 22:51:02.894007 <6>[ 11.177889] hub 1-0:1.0: USB hub found
842 22:51:02.931715 <6>[ 11.215404] hub 1-0:1.0: 1 port detected
843 22:51:03.072843 <6>[ 11.356274] tda998x 0-0070: found TDA19988
844 22:51:06.024982 Begin: Loading essential drivers ... done.
845 22:51:06.039484 Begin: Running /scripts/init-premount ... done.
846 22:51:06.051442 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
847 22:51:06.066186 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
848 22:51:06.066696 Device /sys/class/net/eth0 found
849 22:51:06.067102 done.
850 22:51:06.126327 Begin: Waiting up to 180 secs for any network device to become available ... done.
851 22:51:06.193244 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
852 22:51:06.338697 IP-Config: eth0 complete (dhcp from 192.168.6.1):
853 22:51:06.349844 address: 192.168.6.78 broadcast: 192.168.6.255 netmask: 255.255.255.0
854 22:51:06.353171 gateway: 192.168.6.1 dns0 : 192.168.6.1 dns1 : 0.0.0.0
855 22:51:06.359493 rootserver: 192.168.6.1 rootpath:
856 22:51:06.359959 filename :
857 22:51:06.394965 done.
858 22:51:06.403209 Begin: Running /scripts/nfs-bottom ... done.
859 22:51:06.458972 Begin: Running /scripts/init-bottom ... done.
860 22:51:08.149082 <30>[ 16.430075] systemd[1]: System time before build time, advancing clock.
861 22:51:08.331063 <30>[ 16.586017] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
862 22:51:08.339844 <30>[ 16.622798] systemd[1]: Detected architecture arm.
863 22:51:08.353315
864 22:51:08.353857 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
865 22:51:08.354291
866 22:51:08.383788 <30>[ 16.665631] systemd[1]: Hostname set to <debian-bookworm-armhf>.
867 22:51:10.549181 <30>[ 18.829665] systemd[1]: Queued start job for default target graphical.target.
868 22:51:10.565608 <30>[ 18.844060] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
869 22:51:10.573305 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
870 22:51:10.603390 <30>[ 18.881308] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
871 22:51:10.610755 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
872 22:51:10.642525 <30>[ 18.921514] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
873 22:51:10.655511 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
874 22:51:10.677700 <30>[ 18.957048] systemd[1]: Created slice user.slice - User and Session Slice.
875 22:51:10.683546 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
876 22:51:10.714115 <30>[ 18.986409] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
877 22:51:10.720389 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
878 22:51:10.749087 <30>[ 19.027444] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
879 22:51:10.760070 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
880 22:51:10.797930 <30>[ 19.066178] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
881 22:51:10.804318 <30>[ 19.086664] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
882 22:51:10.812722 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
883 22:51:10.836320 <30>[ 19.115805] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
884 22:51:10.844592 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
885 22:51:10.867464 <30>[ 19.146188] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
886 22:51:10.874973 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
887 22:51:10.896888 <30>[ 19.176253] systemd[1]: Reached target paths.target - Path Units.
888 22:51:10.901953 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
889 22:51:10.926546 <30>[ 19.205917] systemd[1]: Reached target remote-fs.target - Remote File Systems.
890 22:51:10.933968 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
891 22:51:10.956422 <30>[ 19.235835] systemd[1]: Reached target slices.target - Slice Units.
892 22:51:10.961925 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
893 22:51:10.986680 <30>[ 19.266100] systemd[1]: Reached target swap.target - Swaps.
894 22:51:10.990583 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
895 22:51:11.016756 <30>[ 19.296051] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
896 22:51:11.025606 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
897 22:51:11.049400 <30>[ 19.328637] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
898 22:51:11.061921 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
899 22:51:11.142951 <30>[ 19.417318] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
900 22:51:11.155481 <30>[ 19.434626] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
901 22:51:11.163942 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
902 22:51:11.188347 <30>[ 19.466983] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
903 22:51:11.195753 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
904 22:51:11.219876 <30>[ 19.498819] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
905 22:51:11.227975 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
906 22:51:11.251246 <30>[ 19.530137] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
907 22:51:11.256849 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
908 22:51:11.290550 <30>[ 19.568689] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
909 22:51:11.298127 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
910 22:51:11.323448 <30>[ 19.596839] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
911 22:51:11.340051 <30>[ 19.613274] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
912 22:51:11.386436 <30>[ 19.665807] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
913 22:51:11.392953 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
914 22:51:11.424909 <30>[ 19.704887] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
915 22:51:11.455795 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
916 22:51:11.520225 <30>[ 19.799240] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
917 22:51:11.538397 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
918 22:51:11.577057 <30>[ 19.856686] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
919 22:51:11.605392 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
920 22:51:11.656670 <30>[ 19.936653] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
921 22:51:11.676220 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
922 22:51:11.706165 <30>[ 19.986688] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
923 22:51:11.734489 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
924 22:51:11.788218 <30>[ 20.067454] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
925 22:51:11.816035 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
926 22:51:11.866725 <30>[ 20.147070] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
927 22:51:11.886068 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
928 22:51:11.920788 <30>[ 20.201141] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
929 22:51:11.954496 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
930 22:51:11.983152 <28>[ 20.257452] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
931 22:51:11.991717 <28>[ 20.271177] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
932 22:51:12.035947 <30>[ 20.316718] systemd[1]: Starting systemd-journald.service - Journal Service...
933 22:51:12.054757 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
934 22:51:12.137259 <30>[ 20.417321] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
935 22:51:12.156695 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
936 22:51:12.193053 <30>[ 20.473339] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
937 22:51:12.245320 Starting [0;1;39msystemd-network-g… units from Kernel command line...
938 22:51:12.313011 <30>[ 20.591791] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
939 22:51:12.368798 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
940 22:51:12.440946 <30>[ 20.720544] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
941 22:51:12.508672 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
942 22:51:12.544905 <30>[ 20.825158] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
943 22:51:12.568273 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
944 22:51:12.607121 <30>[ 20.887428] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
945 22:51:12.636350 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
946 22:51:12.660214 <30>[ 20.939482] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
947 22:51:12.689625 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
948 22:51:12.869285 <30>[ 21.149749] systemd[1]: modprobe@configfs.service: Deactivated successfully.
949 22:51:12.896276 <30>[ 21.175825] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
950 22:51:12.905303 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
951 22:51:12.927124 <30>[ 21.208209] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
952 22:51:12.957002 <30>[ 21.237120] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
953 22:51:12.979799 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
954 22:51:12.997655 <30>[ 21.277023] systemd[1]: Started systemd-journald.service - Journal Service.
955 22:51:13.004262 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
956 22:51:13.037308 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
957 22:51:13.067735 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
958 22:51:13.100883 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
959 22:51:13.137401 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
960 22:51:13.166327 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
961 22:51:13.190063 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
962 22:51:13.219349 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
963 22:51:13.249927 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
964 22:51:13.319776 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
965 22:51:13.377685 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
966 22:51:13.417463 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
967 22:51:13.471391 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
968 22:51:13.591250 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
969 22:51:13.749227 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
970 22:51:13.784673 <46>[ 22.065028] systemd-journald[164]: Received client request to flush runtime journal.
971 22:51:13.871754 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
972 22:51:13.928789 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
973 22:51:14.758834 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
974 22:51:14.828417 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
975 22:51:15.461358 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
976 22:51:15.619297 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
977 22:51:15.648289 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
978 22:51:15.675704 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
979 22:51:15.738704 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
980 22:51:15.786170 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
981 22:51:16.778301 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
982 22:51:16.853077 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
983 22:51:16.924570 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
984 22:51:17.056336 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
985 22:51:17.083787 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
986 22:51:18.757388 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
987 22:51:19.793642 <5>[ 28.073697] cfg80211: Loading compiled-in X.509 certificates for regulatory database
988 22:51:19.801912 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
989 22:51:20.664109 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
990 22:51:20.715643 <5>[ 28.998199] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
991 22:51:20.767733 <5>[ 29.048702] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
992 22:51:20.789349 <4>[ 29.069501] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
993 22:51:20.795151 <6>[ 29.078644] cfg80211: failed to load regulatory.db
994 22:51:21.598083 <46>[ 29.869462] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
995 22:51:21.661948 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
996 22:51:21.785190 <46>[ 30.058764] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
997 22:51:22.308141 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
998 22:51:31.264683 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
999 22:51:31.290894 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1000 22:51:31.318210 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1001 22:51:31.338271 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1002 22:51:31.406157 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1003 22:51:31.467894 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1004 22:51:31.538673 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1005 22:51:31.586539 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1006 22:51:31.634149 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1007 22:51:31.662133 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1008 22:51:31.701865 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1009 22:51:31.730411 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1010 22:51:31.772944 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1011 22:51:31.808341 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1012 22:51:31.844343 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1013 22:51:31.867617 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1014 22:51:31.892661 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1015 22:51:31.930731 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1016 22:51:31.957394 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1017 22:51:31.976694 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1018 22:51:32.004796 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1019 22:51:32.026662 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1020 22:51:32.053353 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1021 22:51:32.127060 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1022 22:51:32.195435 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1023 22:51:32.296116 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1024 22:51:32.350247 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1025 22:51:32.406744 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1026 22:51:32.457173 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1027 22:51:32.476986 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1028 22:51:32.666053 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1029 22:51:32.734477 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1030 22:51:32.796053 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1031 22:51:32.815386 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1032 22:51:32.837843 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1033 22:51:33.000736 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
1034 22:51:33.195626 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1035 22:51:33.605583 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
1036 22:51:33.896035 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1037 22:51:33.943428 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1038 22:51:33.970597 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1039 22:51:34.065751 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1040 22:51:34.233996 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1041 22:51:34.368308
1042 22:51:34.371949 Debian GNU/Linux 12 debiworm-armhf login: root (automatic login)
1043 22:51:34.372471
1044 22:51:34.676889 Linux debian-bookworm-armhf 6.12.0-rc1 #1 SMP Wed Oct 16 08:45:40 UTC 2024 armv7l
1045 22:51:34.677545
1046 22:51:34.682634 The programs included with the Debian GNU/Linux system are free software;
1047 22:51:34.685860 the exact distribution terms for each program are described in the
1048 22:51:34.691644 individual files in /usr/share/doc/*/copyright.
1049 22:51:34.692205
1050 22:51:34.697103 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1051 22:51:34.701733 permitted by applicable law.
1052 22:51:39.774721 Matched prompt #10: / #
1054 22:51:39.777580 Kernel warnings or errors detected.
1055 22:51:39.778116 Setting prompt string to ['/ #']
1056 22:51:39.778734 end: 2.4.4.1 login-action (duration 00:00:48) [common]
1058 22:51:39.781376 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
1059 22:51:39.782085 start: 2.4.5 expect-shell-connection (timeout 00:03:08) [common]
1060 22:51:39.782592 Setting prompt string to ['/ #']
1061 22:51:39.783036 Forcing a shell prompt, looking for ['/ #']
1063 22:51:39.834073 / #
1064 22:51:39.834785 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1065 22:51:39.835270 Waiting using forced prompt support (timeout 00:02:30)
1066 22:51:39.839673
1067 22:51:39.845634 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1068 22:51:39.846349 start: 2.4.6 export-device-env (timeout 00:03:08) [common]
1069 22:51:39.846934 Sending with 10 millisecond of delay
1071 22:51:44.834763 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/851213/extract-nfsrootfs-r5r98lox'
1072 22:51:44.845881 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/851213/extract-nfsrootfs-r5r98lox'
1073 22:51:44.846768 Sending with 10 millisecond of delay
1075 22:51:46.944948 / # export NFS_SERVER_IP='192.168.6.3'
1076 22:51:46.955898 export NFS_SERVER_IP='192.168.6.3'
1077 22:51:46.957138 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1078 22:51:46.957771 end: 2.4 uboot-commands (duration 00:01:59) [common]
1079 22:51:46.958528 end: 2 uboot-action (duration 00:01:59) [common]
1080 22:51:46.959173 start: 3 lava-test-retry (timeout 00:06:53) [common]
1081 22:51:46.959831 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1082 22:51:46.960383 Using namespace: common
1084 22:51:47.061644 / # #
1085 22:51:47.062415 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1086 22:51:47.067208 #
1087 22:51:47.073090 Using /lava-851213
1089 22:51:47.174363 / # export SHELL=/bin/bash
1090 22:51:47.179899 export SHELL=/bin/bash
1092 22:51:47.285554 / # . /lava-851213/environment
1093 22:51:47.290017 . /lava-851213/environment
1095 22:51:47.406861 / # /lava-851213/bin/lava-test-runner /lava-851213/0
1096 22:51:47.407539 Test shell timeout: 10s (minimum of the action and connection timeout)
1097 22:51:47.411262 /lava-851213/bin/lava-test-runner /lava-851213/0
1098 22:51:47.799345 + export TESTRUN_ID=0_timesync-off
1099 22:51:47.807224 + TESTRUN_ID=0_timesync-off
1100 22:51:47.807774 + cd /lava-851213/0/tests/0_timesync-off
1101 22:51:47.808246 ++ cat uuid
1102 22:51:47.822949 + UUID=851213_1.6.2.4.1
1103 22:51:47.823462 + set +x
1104 22:51:47.832904 <LAVA_SIGNAL_STARTRUN 0_timesync-off 851213_1.6.2.4.1>
1105 22:51:47.833390 + systemctl stop systemd-timesyncd
1106 22:51:47.834223 Received signal: <STARTRUN> 0_timesync-off 851213_1.6.2.4.1
1107 22:51:47.834727 Starting test lava.0_timesync-off (851213_1.6.2.4.1)
1108 22:51:47.835327 Skipping test definition patterns.
1109 22:51:48.137130 + set +x
1110 22:51:48.137805 <LAVA_SIGNAL_ENDRUN 0_timesync-off 851213_1.6.2.4.1>
1111 22:51:48.138621 Received signal: <ENDRUN> 0_timesync-off 851213_1.6.2.4.1
1112 22:51:48.139165 Ending use of test pattern.
1113 22:51:48.139617 Ending test lava.0_timesync-off (851213_1.6.2.4.1), duration 0.30
1115 22:51:48.288128 + export TESTRUN_ID=1_kselftest-dt
1116 22:51:48.296139 + TESTRUN_ID=1_kselftest-dt
1117 22:51:48.296641 + cd /lava-851213/0/tests/1_kselftest-dt
1118 22:51:48.297102 ++ cat uuid
1119 22:51:48.311606 + UUID=851213_1.6.2.4.5
1120 22:51:48.312104 + set +x
1121 22:51:48.317179 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 851213_1.6.2.4.5>
1122 22:51:48.317665 + cd ./automated/linux/kselftest/
1123 22:51:48.318424 Received signal: <STARTRUN> 1_kselftest-dt 851213_1.6.2.4.5
1124 22:51:48.318893 Starting test lava.1_kselftest-dt (851213_1.6.2.4.5)
1125 22:51:48.319430 Skipping test definition patterns.
1126 22:51:48.347180 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g lee-mfd -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1127 22:51:48.445723 INFO: install_deps skipped
1128 22:51:49.002906 --2024-10-16 22:51:48-- http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1129 22:51:49.030672 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1130 22:51:49.191121 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1131 22:51:49.349328 HTTP request sent, awaiting response... 200 OK
1132 22:51:49.349990 Length: 3809752 (3.6M) [application/octet-stream]
1133 22:51:49.354734 Saving to: 'kselftest_armhf.tar.gz'
1134 22:51:49.355243
1135 22:51:51.470818
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kselftest_armhf.tar 1%[ ] 49.92K 160KB/s
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kselftest_armhf.tar 20%[===> ] 749.26K 686KB/s
kselftest_armhf.tar 51%[=========> ] 1.88M 1.46MB/s
kselftest_armhf.tar 59%[==========> ] 2.16M 1.41MB/s
kselftest_armhf.tar 75%[==============> ] 2.74M 1.58MB/s
kselftest_armhf.tar 88%[================> ] 3.22M 1.65MB/s
kselftest_armhf.tar 100%[===================>] 3.63M 1.72MB/s in 2.1s
1136 22:51:51.471519
1137 22:51:52.055309 2024-10-16 22:51:51 (1.72 MB/s) - 'kselftest_armhf.tar.gz' saved [3809752/3809752]
1138 22:51:52.055977
1139 22:52:06.950493 skiplist:
1140 22:52:06.951138 ========================================
1141 22:52:06.955899 ========================================
1142 22:52:07.058832 dt:test_unprobed_devices.sh
1143 22:52:07.094292 ============== Tests to run ===============
1144 22:52:07.101356 dt:test_unprobed_devices.sh
1145 22:52:07.105234 ===========End Tests to run ===============
1146 22:52:07.113553 shardfile-dt pass
1147 22:52:07.349220 <12>[ 75.634475] kselftest: Running tests in dt
1148 22:52:07.375978 TAP version 13
1149 22:52:07.399469 1..1
1150 22:52:07.451547 # timeout set to 45
1151 22:52:07.451878 # selftests: dt: test_unprobed_devices.sh
1152 22:52:08.239105 # TAP version 13
1153 22:52:33.136056 # 1..257
1154 22:52:33.303111 # ok 1 / # SKIP
1155 22:52:33.323736 # ok 2 /clk_mcasp0
1156 22:52:33.396664 # ok 3 /clk_mcasp0_fixed # SKIP
1157 22:52:33.467272 # ok 4 /cpus/cpu@0 # SKIP
1158 22:52:33.544211 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1159 22:52:33.559475 # ok 6 /fixedregulator0
1160 22:52:33.583920 # ok 7 /leds
1161 22:52:33.605089 # ok 8 /ocp
1162 22:52:33.624020 # ok 9 /ocp/interconnect@44c00000
1163 22:52:33.648813 # ok 10 /ocp/interconnect@44c00000/segment@0
1164 22:52:33.675608 # ok 11 /ocp/interconnect@44c00000/segment@100000
1165 22:52:33.695827 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1166 22:52:33.771286 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1167 22:52:33.789344 # ok 14 /ocp/interconnect@44c00000/segment@200000
1168 22:52:33.816630 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1169 22:52:33.916985 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1170 22:52:33.992475 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1171 22:52:34.060341 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1172 22:52:34.131840 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1173 22:52:34.204569 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1174 22:52:34.273539 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1175 22:52:34.350476 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1176 22:52:34.421499 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1177 22:52:34.493470 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1178 22:52:34.562387 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1179 22:52:34.638437 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1180 22:52:34.705601 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1181 22:52:34.777476 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1182 22:52:34.848762 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1183 22:52:34.918783 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1184 22:52:34.991324 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1185 22:52:35.062157 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1186 22:52:35.140323 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1187 22:52:35.209988 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1188 22:52:35.281854 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1189 22:52:35.352418 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1190 22:52:35.423302 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1191 22:52:35.492020 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1192 22:52:35.566721 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1193 22:52:35.640235 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1194 22:52:35.713392 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1195 22:52:35.784529 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1196 22:52:35.858286 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1197 22:52:35.928007 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1198 22:52:36.000425 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1199 22:52:36.071640 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1200 22:52:36.143318 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1201 22:52:36.217012 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1202 22:52:36.290974 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1203 22:52:36.361998 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1204 22:52:36.433181 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1205 22:52:36.504366 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1206 22:52:36.573543 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1207 22:52:36.650381 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1208 22:52:36.717774 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1209 22:52:36.789395 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1210 22:52:36.860418 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1211 22:52:36.931443 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1212 22:52:37.001870 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1213 22:52:37.079476 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1214 22:52:37.146872 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1215 22:52:37.222245 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1216 22:52:37.293914 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1217 22:52:37.365110 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1218 22:52:37.435522 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1219 22:52:37.505535 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1220 22:52:37.577681 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1221 22:52:37.648834 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1222 22:52:37.719575 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1223 22:52:37.792397 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1224 22:52:37.872097 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1225 22:52:37.942596 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1226 22:52:38.014314 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1227 22:52:38.084277 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1228 22:52:38.159624 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1229 22:52:38.226645 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1230 22:52:38.555297 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1231 22:52:38.555919 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1232 22:52:38.556732 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1233 22:52:38.557981 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1234 22:52:38.583419 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1235 22:52:38.661600 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1236 22:52:38.725584 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1237 22:52:38.801792 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1238 22:52:38.873145 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1239 22:52:38.943206 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1240 22:52:39.011232 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1241 22:52:39.082634 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1242 22:52:39.156635 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1243 22:52:39.229007 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1244 22:52:39.297687 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1245 22:52:39.371028 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1246 22:52:39.442035 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1247 22:52:39.513877 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1248 22:52:39.537309 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1249 22:52:39.560868 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1250 22:52:39.585040 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1251 22:52:39.608687 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1252 22:52:39.637093 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1253 22:52:39.659959 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1254 22:52:39.681962 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1255 22:52:39.702634 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1256 22:52:39.806988 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1257 22:52:39.830544 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1258 22:52:39.855695 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1259 22:52:39.878932 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1260 22:52:39.986740 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1261 22:52:40.062462 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1262 22:52:40.133777 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1263 22:52:40.204900 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1264 22:52:40.274234 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1265 22:52:40.348984 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1266 22:52:40.417963 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1267 22:52:40.488952 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1268 22:52:40.560843 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1269 22:52:40.632964 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1270 22:52:40.705561 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1271 22:52:40.776053 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1272 22:52:40.852881 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1273 22:52:40.926319 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1274 22:52:40.994205 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1275 22:52:41.066000 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1276 22:52:41.091634 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1277 22:52:41.159052 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1278 22:52:41.227478 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1279 22:52:41.302145 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1280 22:52:41.322083 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1281 22:52:41.394489 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1282 22:52:41.416726 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1283 22:52:41.491699 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1284 22:52:41.518991 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1285 22:52:41.540938 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1286 22:52:41.560079 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1287 22:52:41.584985 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1288 22:52:41.607095 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1289 22:52:41.632756 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1290 22:52:41.657638 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1291 22:52:41.730984 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1292 22:52:41.757072 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1293 22:52:41.776440 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1294 22:52:41.847742 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1295 22:52:41.918023 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1296 22:52:41.938796 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1297 22:52:42.037753 # not ok 144 /ocp/interconnect@47c00000
1298 22:52:42.108319 # not ok 145 /ocp/interconnect@47c00000/segment@0
1299 22:52:42.133678 # ok 146 /ocp/interconnect@48000000
1300 22:52:42.156434 # ok 147 /ocp/interconnect@48000000/segment@0
1301 22:52:42.180515 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1302 22:52:42.204601 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1303 22:52:42.227684 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1304 22:52:42.250442 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1305 22:52:42.269348 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1306 22:52:42.294047 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1307 22:52:42.316308 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1308 22:52:42.386589 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1309 22:52:42.461709 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1310 22:52:42.482592 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1311 22:52:42.503720 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1312 22:52:42.526649 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1313 22:52:42.551067 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1314 22:52:42.572273 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1315 22:52:42.597061 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1316 22:52:42.619069 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1317 22:52:42.642359 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1318 22:52:42.665289 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1319 22:52:42.689628 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1320 22:52:42.716538 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1321 22:52:42.740507 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1322 22:52:42.760634 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1323 22:52:42.782884 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1324 22:52:42.809364 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1325 22:52:42.831376 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1326 22:52:42.852198 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1327 22:52:42.881355 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1328 22:52:42.899199 # ok 175 /ocp/interconnect@48000000/segment@100000
1329 22:52:42.926943 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1330 22:52:42.950944 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1331 22:52:43.023151 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1332 22:52:43.092500 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1333 22:52:43.162259 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1334 22:52:43.241329 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1335 22:52:43.305701 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1336 22:52:43.377870 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1337 22:52:43.447209 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1338 22:52:43.520202 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1339 22:52:43.539427 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1340 22:52:43.562686 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1341 22:52:43.585563 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1342 22:52:43.610016 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1343 22:52:43.638440 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1344 22:52:43.661398 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1345 22:52:43.688371 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1346 22:52:43.705643 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1347 22:52:43.728791 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1348 22:52:43.756969 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1349 22:52:43.779968 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1350 22:52:43.801346 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1351 22:52:43.821042 # ok 198 /ocp/interconnect@48000000/segment@200000
1352 22:52:43.849260 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1353 22:52:43.921655 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1354 22:52:43.937328 # ok 201 /ocp/interconnect@48000000/segment@300000
1355 22:52:43.966412 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1356 22:52:43.990056 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1357 22:52:44.011409 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1358 22:52:44.032551 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1359 22:52:44.055564 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1360 22:52:44.080820 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1361 22:52:44.149740 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1362 22:52:44.168333 # ok 209 /ocp/interconnect@4a000000
1363 22:52:44.191748 # ok 210 /ocp/interconnect@4a000000/segment@0
1364 22:52:44.216643 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1365 22:52:44.245473 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1366 22:52:44.270074 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1367 22:52:44.290568 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1368 22:52:44.359086 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1369 22:52:44.468021 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1370 22:52:44.535201 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1371 22:52:44.640357 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1372 22:52:44.711143 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1373 22:52:44.787856 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1374 22:52:44.880172 # not ok 221 /ocp/interconnect@4b140000
1375 22:52:44.951295 # not ok 222 /ocp/interconnect@4b140000/segment@0
1376 22:52:45.021630 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1377 22:52:45.042075 # ok 224 /ocp/target-module@40300000
1378 22:52:45.068478 # ok 225 /ocp/target-module@40300000/sram@0
1379 22:52:45.137472 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1380 22:52:45.210660 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1381 22:52:45.228665 # ok 228 /ocp/target-module@47400000
1382 22:52:45.252925 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1383 22:52:45.274726 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1384 22:52:45.298932 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1385 22:52:45.324143 # ok 232 /ocp/target-module@47400000/usb@1400
1386 22:52:45.342100 # ok 233 /ocp/target-module@47400000/usb@1800
1387 22:52:45.367815 # ok 234 /ocp/target-module@47810000
1388 22:52:45.387818 # ok 235 /ocp/target-module@49000000
1389 22:52:45.413609 # ok 236 /ocp/target-module@49000000/dma@0
1390 22:52:45.436471 # ok 237 /ocp/target-module@49800000
1391 22:52:45.454923 # ok 238 /ocp/target-module@49800000/dma@0
1392 22:52:45.477792 # ok 239 /ocp/target-module@49900000
1393 22:52:45.500075 # ok 240 /ocp/target-module@49900000/dma@0
1394 22:52:45.525730 # ok 241 /ocp/target-module@49a00000
1395 22:52:45.548993 # ok 242 /ocp/target-module@49a00000/dma@0
1396 22:52:45.566092 # ok 243 /ocp/target-module@4c000000
1397 22:52:45.638065 # not ok 244 /ocp/target-module@4c000000/emif@0
1398 22:52:45.663644 # ok 245 /ocp/target-module@50000000
1399 22:52:45.685704 # ok 246 /ocp/target-module@53100000
1400 22:52:45.753513 # not ok 247 /ocp/target-module@53100000/sham@0
1401 22:52:45.777864 # ok 248 /ocp/target-module@53500000
1402 22:52:45.846110 # not ok 249 /ocp/target-module@53500000/aes@0
1403 22:52:45.868138 # ok 250 /ocp/target-module@56000000
1404 22:52:45.971664 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1405 22:52:46.039543 # ok 252 /opp-table # SKIP
1406 22:52:46.112988 # ok 253 /soc # SKIP
1407 22:52:46.134039 # ok 254 /sound
1408 22:52:46.152648 # ok 255 /target-module@4b000000
1409 22:52:46.177617 # ok 256 /target-module@4b000000/target-module@140000
1410 22:52:46.198606 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1411 22:52:46.207075 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1412 22:52:46.214913 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1413 22:52:48.299140 dt_test_unprobed_devices_sh_ skip
1414 22:52:48.304798 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1415 22:52:48.310446 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1416 22:52:48.310932 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1417 22:52:48.315952 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1418 22:52:48.321510 dt_test_unprobed_devices_sh_fixedregulator0 pass
1419 22:52:48.327160 dt_test_unprobed_devices_sh_leds pass
1420 22:52:48.327600 dt_test_unprobed_devices_sh_ocp pass
1421 22:52:48.332686 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1422 22:52:48.338364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1423 22:52:48.343964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1424 22:52:48.355112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1425 22:52:48.360738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1426 22:52:48.366337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1427 22:52:48.377692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1428 22:52:48.383212 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1429 22:52:48.394560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1430 22:52:48.405735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1431 22:52:48.416799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1432 22:52:48.422446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1433 22:52:48.433653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1434 22:52:48.444813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1435 22:52:48.456062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1436 22:52:48.467218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1437 22:52:48.472888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1438 22:52:48.484035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1439 22:52:48.495307 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1440 22:52:48.506430 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1441 22:52:48.517700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1442 22:52:48.523235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1443 22:52:48.534430 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1444 22:52:48.545683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1445 22:52:48.556820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1446 22:52:48.562481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1447 22:52:48.573696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1448 22:52:48.584737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1449 22:52:48.595967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1450 22:52:48.607154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1451 22:52:48.612820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1452 22:52:48.623956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1453 22:52:48.635164 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1454 22:52:48.646338 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1455 22:52:48.657507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1456 22:52:48.668738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1457 22:52:48.679869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1458 22:52:48.691140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1459 22:52:48.702361 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1460 22:52:48.713489 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1461 22:52:48.724703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1462 22:52:48.735857 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1463 22:52:48.747043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1464 22:52:48.758238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1465 22:52:48.769468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1466 22:52:48.780776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1467 22:52:48.791840 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1468 22:52:48.802996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1469 22:52:48.814183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1470 22:52:48.825529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1471 22:52:48.836609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1472 22:52:48.847771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1473 22:52:48.858981 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1474 22:52:48.870157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1475 22:52:48.881326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1476 22:52:48.892557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1477 22:52:48.898211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1478 22:52:48.909331 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1479 22:52:48.920546 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1480 22:52:48.931743 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1481 22:52:48.942884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1482 22:52:48.954136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1483 22:52:48.965302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1484 22:52:48.976480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1485 22:52:48.987755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1486 22:52:48.998887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1487 22:52:49.010068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1488 22:52:49.021301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1489 22:52:49.032514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1490 22:52:49.043780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1491 22:52:49.054854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1492 22:52:49.066113 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1493 22:52:49.077247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1494 22:52:49.088407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1495 22:52:49.094036 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1496 22:52:49.105204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1497 22:52:49.116422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1498 22:52:49.127606 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1499 22:52:49.138763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1500 22:52:49.144426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1501 22:52:49.161125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1502 22:52:49.172362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1503 22:52:49.177986 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1504 22:52:49.194770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1505 22:52:49.205920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1506 22:52:49.217121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1507 22:52:49.222831 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1508 22:52:49.233927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1509 22:52:49.245101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1510 22:52:49.250755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1511 22:52:49.261871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1512 22:52:49.273068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1513 22:52:49.278825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1514 22:52:49.289838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1515 22:52:49.295478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1516 22:52:49.306662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1517 22:52:49.317885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1518 22:52:49.329061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1519 22:52:49.340228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1520 22:52:49.351417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1521 22:52:49.362579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1522 22:52:49.373770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1523 22:52:49.384982 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1524 22:52:49.396214 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1525 22:52:49.407401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1526 22:52:49.418612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1527 22:52:49.429791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1528 22:52:49.446550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1529 22:52:49.457836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1530 22:52:49.468950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1531 22:52:49.480119 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1532 22:52:49.491341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1533 22:52:49.508068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1534 22:52:49.519303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1535 22:52:49.530470 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1536 22:52:49.541669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1537 22:52:49.547323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1538 22:52:49.558497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1539 22:52:49.569651 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1540 22:52:49.575313 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1541 22:52:49.586474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1542 22:52:49.592063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1543 22:52:49.603211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1544 22:52:49.608862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1545 22:52:49.620041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1546 22:52:49.625703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1547 22:52:49.636847 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1548 22:52:49.642455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1549 22:52:49.653567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1550 22:52:49.664858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1551 22:52:49.675976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1552 22:52:49.687227 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1553 22:52:49.698400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1554 22:52:49.704018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1555 22:52:49.715141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1556 22:52:49.720879 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1557 22:52:49.726387 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1558 22:52:49.731953 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1559 22:52:49.737647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1560 22:52:49.743215 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1561 22:52:49.754342 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1562 22:52:49.759990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1563 22:52:49.765659 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1564 22:52:49.776872 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1565 22:52:49.782389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1566 22:52:49.793499 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1567 22:52:49.799162 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1568 22:52:49.810329 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1569 22:52:49.815942 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1570 22:52:49.827066 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1571 22:52:49.832707 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1572 22:52:49.843903 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1573 22:52:49.849516 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1574 22:52:49.860718 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1575 22:52:49.866314 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1576 22:52:49.877492 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1577 22:52:49.883103 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1578 22:52:49.888710 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1579 22:52:49.899876 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1580 22:52:49.905510 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1581 22:52:49.916609 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1582 22:52:49.922290 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1583 22:52:49.933420 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1584 22:52:49.939051 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1585 22:52:49.950197 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1586 22:52:49.955939 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1587 22:52:49.961421 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1588 22:52:49.972620 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1589 22:52:49.978217 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1590 22:52:49.989394 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1591 22:52:50.000554 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1592 22:52:50.011876 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1593 22:52:50.022952 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1594 22:52:50.034141 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1595 22:52:50.045311 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1596 22:52:50.056547 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1597 22:52:50.067680 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1598 22:52:50.073349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1599 22:52:50.084552 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1600 22:52:50.090156 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1601 22:52:50.101320 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1602 22:52:50.106969 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1603 22:52:50.118068 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1604 22:52:50.123721 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1605 22:52:50.134947 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1606 22:52:50.140510 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1607 22:52:50.151654 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1608 22:52:50.157255 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1609 22:52:50.168462 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1610 22:52:50.174101 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1611 22:52:50.185233 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1612 22:52:50.190941 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1613 22:52:50.196463 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1614 22:52:50.207692 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1615 22:52:50.213263 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1616 22:52:50.224425 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1617 22:52:50.230042 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1618 22:52:50.241187 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1619 22:52:50.246855 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1620 22:52:50.257981 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1621 22:52:50.263614 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1622 22:52:50.269209 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1623 22:52:50.274762 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1624 22:52:50.285970 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1625 22:52:50.297105 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1626 22:52:50.302743 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1627 22:52:50.308350 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1628 22:52:50.319535 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1629 22:52:50.330744 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1630 22:52:50.341971 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1631 22:52:50.353072 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1632 22:52:50.358766 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1633 22:52:50.364369 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1634 22:52:50.370019 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1635 22:52:50.375641 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1636 22:52:50.381255 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1637 22:52:50.387002 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1638 22:52:50.398016 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1639 22:52:50.403697 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1640 22:52:50.409293 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1641 22:52:50.415003 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1642 22:52:50.420496 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1643 22:52:50.431677 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1644 22:52:50.437281 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1645 22:52:50.443006 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1646 22:52:50.448529 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1647 22:52:50.454116 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1648 22:52:50.459751 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1649 22:52:50.465298 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1650 22:52:50.471016 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1651 22:52:50.476502 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1652 22:52:50.482131 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1653 22:52:50.487762 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1654 22:52:50.493302 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1655 22:52:50.499016 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1656 22:52:50.504544 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1657 22:52:50.510100 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1658 22:52:50.515698 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1659 22:52:50.521321 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1660 22:52:50.526988 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1661 22:52:50.532528 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1662 22:52:50.538151 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1663 22:52:50.543719 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1664 22:52:50.544180 dt_test_unprobed_devices_sh_opp-table skip
1665 22:52:50.549339 dt_test_unprobed_devices_sh_soc skip
1666 22:52:50.554996 dt_test_unprobed_devices_sh_sound pass
1667 22:52:50.560565 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1668 22:52:50.566166 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1669 22:52:50.571756 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1670 22:52:50.577295 dt_test_unprobed_devices_sh fail
1671 22:52:50.577748 + ../../utils/send-to-lava.sh ./output/result.txt
1672 22:52:50.585174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1673 22:52:50.586075 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1675 22:52:50.594213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1676 22:52:50.594918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1678 22:52:50.684491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1679 22:52:50.685228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1681 22:52:50.775612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1682 22:52:50.776352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1684 22:52:50.865154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1685 22:52:50.865908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1687 22:52:50.958903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1688 22:52:50.959636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1690 22:52:51.048927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1691 22:52:51.049659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1693 22:52:51.138595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1694 22:52:51.139313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1696 22:52:51.230673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1697 22:52:51.231400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1699 22:52:51.325847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1700 22:52:51.326588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1702 22:52:51.412257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1703 22:52:51.412988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1705 22:52:51.505316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1706 22:52:51.506046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1708 22:52:51.599774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1709 22:52:51.600515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1711 22:52:51.692818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1712 22:52:51.693546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1714 22:52:51.784660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1715 22:52:51.785402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1717 22:52:51.879553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1718 22:52:51.880276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1720 22:52:51.972773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1721 22:52:51.973516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1723 22:52:52.067529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1724 22:52:52.068260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1726 22:52:52.162315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1727 22:52:52.163040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1729 22:52:52.255278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1730 22:52:52.255996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1732 22:52:52.347872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1733 22:52:52.348605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1735 22:52:52.440821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1736 22:52:52.441551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1738 22:52:52.533927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1739 22:52:52.534751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1741 22:52:52.627160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1742 22:52:52.627922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1744 22:52:52.720084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1745 22:52:52.720846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1747 22:52:52.812814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1748 22:52:52.813545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1750 22:52:52.905127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1751 22:52:52.905906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1753 22:52:53.006736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1754 22:52:53.007492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1756 22:52:53.108508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1757 22:52:53.109270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1759 22:52:53.206717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1760 22:52:53.207468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1762 22:52:53.305412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1763 22:52:53.306241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1765 22:52:53.400193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1766 22:52:53.400991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1768 22:52:53.500940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1769 22:52:53.501688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1771 22:52:53.603648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1772 22:52:53.604403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1774 22:52:53.696160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1775 22:52:53.696944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1777 22:52:53.790140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1778 22:52:53.791004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1780 22:52:53.882979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1781 22:52:53.883754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1783 22:52:53.975849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1784 22:52:53.976600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1786 22:52:54.069451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1787 22:52:54.070244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1789 22:52:54.162136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1790 22:52:54.162914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1792 22:52:54.284061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1793 22:52:54.284953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1795 22:52:54.381554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1796 22:52:54.382384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1798 22:52:54.473081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1799 22:52:54.473868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1801 22:52:54.566548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1802 22:52:54.567309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1804 22:52:54.660756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1805 22:52:54.661497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1807 22:52:54.754177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1808 22:52:54.754942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1810 22:52:54.844360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1811 22:52:54.845117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1813 22:52:54.935545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1814 22:52:54.936301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1816 22:52:55.029149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1817 22:52:55.029930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1819 22:52:55.120553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1820 22:52:55.121310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1822 22:52:55.212568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1823 22:52:55.213328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1825 22:52:55.304694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1826 22:52:55.305472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1828 22:52:55.396865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1829 22:52:55.397616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1831 22:52:55.488671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1832 22:52:55.489431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1834 22:52:55.580880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1835 22:52:55.581608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1837 22:52:55.681908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1838 22:52:55.682669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1840 22:52:55.773921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1841 22:52:55.774658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1843 22:52:55.865573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1844 22:52:55.866358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1846 22:52:55.955504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1847 22:52:55.956236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1849 22:52:56.047736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1850 22:52:56.048468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1852 22:52:56.139330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1853 22:52:56.140095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1855 22:52:56.229754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1856 22:52:56.230534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1858 22:52:56.320005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1859 22:52:56.320756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1861 22:52:56.410995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1862 22:52:56.411746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1864 22:52:56.503498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1865 22:52:56.504252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1867 22:52:56.595390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1868 22:52:56.596136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1870 22:52:56.688807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1871 22:52:56.689568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1873 22:52:56.783174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1874 22:52:56.783936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1876 22:52:56.872460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1877 22:52:56.873221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1879 22:52:56.964599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1880 22:52:56.965331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1882 22:52:57.057730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1883 22:52:57.058571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1885 22:52:57.148111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1886 22:52:57.148904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1888 22:52:57.238504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1889 22:52:57.239308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1891 22:52:57.329929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1892 22:52:57.330742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1894 22:52:57.420550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1895 22:52:57.421359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1897 22:52:57.512536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1898 22:52:57.513320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1900 22:52:57.601950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1901 22:52:57.602753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1903 22:52:57.691655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1904 22:52:57.692467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1906 22:52:57.782477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1907 22:52:57.783263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1909 22:52:57.872934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1910 22:52:57.873681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1912 22:52:57.964841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1913 22:52:57.965601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1915 22:52:58.055992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1916 22:52:58.056801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1918 22:52:58.205629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1919 22:52:58.206489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1921 22:52:58.304446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1922 22:52:58.305208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1924 22:52:58.395070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1925 22:52:58.395836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1927 22:52:58.485540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1928 22:52:58.486312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1930 22:52:58.577715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1931 22:52:58.578472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1933 22:52:58.670351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1934 22:52:58.671136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1936 22:52:58.761923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1937 22:52:58.762665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1939 22:52:58.855024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1940 22:52:58.855767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1942 22:52:58.946877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1943 22:52:58.947611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1945 22:52:59.035947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1946 22:52:59.036680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1948 22:52:59.128865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1949 22:52:59.129600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1951 22:52:59.219644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1952 22:52:59.220369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1954 22:52:59.311376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1955 22:52:59.312124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1957 22:52:59.400208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1958 22:52:59.400948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1960 22:52:59.491544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1961 22:52:59.492267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1963 22:52:59.580959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1964 22:52:59.581857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1966 22:52:59.673248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1967 22:52:59.674016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1969 22:52:59.763380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1970 22:52:59.764123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1972 22:52:59.865763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1973 22:52:59.866532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1975 22:52:59.966933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1976 22:52:59.967689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1978 22:53:00.058996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1979 22:53:00.059772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1981 22:53:00.149625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1982 22:53:00.150395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1984 22:53:00.241567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1985 22:53:00.242327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1987 22:53:00.330853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1988 22:53:00.331590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1990 22:53:00.420162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1991 22:53:00.420917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1993 22:53:00.510589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1994 22:53:00.511364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1996 22:53:00.603212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1997 22:53:00.603954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1999 22:53:00.692621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
2000 22:53:00.693363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
2002 22:53:00.784200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
2003 22:53:00.784945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
2005 22:53:00.876670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
2006 22:53:00.877416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
2008 22:53:00.968133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
2009 22:53:00.968889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
2011 22:53:01.059668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
2012 22:53:01.060412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
2014 22:53:01.154083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2015 22:53:01.154838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2017 22:53:01.245881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2018 22:53:01.246634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2020 22:53:01.339710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2021 22:53:01.340469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2023 22:53:01.431988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2024 22:53:01.432741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2026 22:53:01.522749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2027 22:53:01.523503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2029 22:53:01.614439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2030 22:53:01.615186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2032 22:53:01.705203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2034 22:53:01.708486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2035 22:53:01.798636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2037 22:53:01.801832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2038 22:53:01.890469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2040 22:53:01.893178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2041 22:53:01.981558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2042 22:53:01.982342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2044 22:53:02.071528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2045 22:53:02.072302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2047 22:53:02.160239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2048 22:53:02.160984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2050 22:53:02.252898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2051 22:53:02.253640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2053 22:53:02.345103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2054 22:53:02.345908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2056 22:53:02.436234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2057 22:53:02.436988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2059 22:53:02.527200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2060 22:53:02.527960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2062 22:53:02.618969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2063 22:53:02.619702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2065 22:53:02.709023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2066 22:53:02.709753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2068 22:53:02.799623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2069 22:53:02.800358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2071 22:53:02.889943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2072 22:53:02.890688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2074 22:53:02.979473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2075 22:53:02.980216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2077 22:53:03.063789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2078 22:53:03.064526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2080 22:53:03.155133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2081 22:53:03.155883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2083 22:53:03.250293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2084 22:53:03.251041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2086 22:53:03.342445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2087 22:53:03.343194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2089 22:53:03.430600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2090 22:53:03.431359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2092 22:53:03.521239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2093 22:53:03.521979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2095 22:53:03.614020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2096 22:53:03.614771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2098 22:53:03.706133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2099 22:53:03.706880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2101 22:53:03.794625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2102 22:53:03.795538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2104 22:53:03.882458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2105 22:53:03.883197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2107 22:53:03.973761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2108 22:53:03.974564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2110 22:53:04.063835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2111 22:53:04.064572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2113 22:53:04.155693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2114 22:53:04.156431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2116 22:53:04.249231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2117 22:53:04.249978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2119 22:53:04.338846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2120 22:53:04.339598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2122 22:53:04.424855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2123 22:53:04.425583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2125 22:53:04.515315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2126 22:53:04.516051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2128 22:53:04.604997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2129 22:53:04.605725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2131 22:53:04.697885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2132 22:53:04.698852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2134 22:53:04.798903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2135 22:53:04.799685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2137 22:53:04.889140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2138 22:53:04.889911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2140 22:53:04.975814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2141 22:53:04.976553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2143 22:53:05.067578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2144 22:53:05.068319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2146 22:53:05.159086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2147 22:53:05.159816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2149 22:53:05.243417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2150 22:53:05.244176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2152 22:53:05.336461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2153 22:53:05.337203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2155 22:53:05.428364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2156 22:53:05.429117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2158 22:53:05.520576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2159 22:53:05.521399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2161 22:53:05.611443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2162 22:53:05.612152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2164 22:53:05.703855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2165 22:53:05.704539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2167 22:53:05.794561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2168 22:53:05.795178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2170 22:53:05.887628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2171 22:53:05.888302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2173 22:53:05.977912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2174 22:53:05.978586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2176 22:53:06.069238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2177 22:53:06.069789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2179 22:53:06.162428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2180 22:53:06.163096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2182 22:53:06.255307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2183 22:53:06.256010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2185 22:53:06.347342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2186 22:53:06.348020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2188 22:53:06.439326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2189 22:53:06.440042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2191 22:53:06.528610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2192 22:53:06.529355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2194 22:53:06.623461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2195 22:53:06.624211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2197 22:53:06.713009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2198 22:53:06.713771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2200 22:53:06.808533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2201 22:53:06.809211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2203 22:53:06.900897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2204 22:53:06.901741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2206 22:53:06.994495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2207 22:53:06.995251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2209 22:53:07.088243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2210 22:53:07.088992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2212 22:53:07.179655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2213 22:53:07.180393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2215 22:53:07.271865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2216 22:53:07.272618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2218 22:53:07.362260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2219 22:53:07.362999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2221 22:53:07.453680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2222 22:53:07.454488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2224 22:53:07.543414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2225 22:53:07.544186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2227 22:53:07.637301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2228 22:53:07.638042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2230 22:53:07.726326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2231 22:53:07.727082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2233 22:53:07.818248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2234 22:53:07.818998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2236 22:53:07.908996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2237 22:53:07.909738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2239 22:53:08.000219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2240 22:53:08.000968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2242 22:53:08.085467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2243 22:53:08.086248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2245 22:53:08.177688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2246 22:53:08.178310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2248 22:53:08.268384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2249 22:53:08.269002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2251 22:53:08.359919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2252 22:53:08.360747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2254 22:53:08.449915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2255 22:53:08.450734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2257 22:53:08.539094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2258 22:53:08.539896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2260 22:53:08.630233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2261 22:53:08.631019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2263 22:53:08.722777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2264 22:53:08.723553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2266 22:53:08.810920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2267 22:53:08.811694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2269 22:53:08.904870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2270 22:53:08.905651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2272 22:53:08.995355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2273 22:53:08.996198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2275 22:53:09.085944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2276 22:53:09.086755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2278 22:53:09.179323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2279 22:53:09.180095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2281 22:53:09.268815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2282 22:53:09.269598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2284 22:53:09.354535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2285 22:53:09.355335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2287 22:53:09.445551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2288 22:53:09.446379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2290 22:53:09.537187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2291 22:53:09.537974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2293 22:53:09.628686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2294 22:53:09.629461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2296 22:53:09.720996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2297 22:53:09.721786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2299 22:53:09.808367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2300 22:53:09.809173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2302 22:53:09.897277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2303 22:53:09.898102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2305 22:53:09.989970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2306 22:53:09.990764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2308 22:53:10.082852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2309 22:53:10.083637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2311 22:53:10.178943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2312 22:53:10.179721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2314 22:53:10.268396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2315 22:53:10.269182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2317 22:53:10.360439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2318 22:53:10.361232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2320 22:53:10.451728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2321 22:53:10.452511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2323 22:53:10.544837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2324 22:53:10.545630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2326 22:53:10.634699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2327 22:53:10.635482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2329 22:53:10.726383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2330 22:53:10.727189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2332 22:53:10.827472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2333 22:53:10.828265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2335 22:53:10.915456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2336 22:53:10.916248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2338 22:53:11.006379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2339 22:53:11.007340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2341 22:53:11.095725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2342 22:53:11.096536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2344 22:53:11.185605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2345 22:53:11.186438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2347 22:53:11.275878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2348 22:53:11.276683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2350 22:53:11.362802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2351 22:53:11.363598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2353 22:53:11.451532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2355 22:53:11.454668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2356 22:53:11.544814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2357 22:53:11.545620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2359 22:53:11.636894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2360 22:53:11.637684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2362 22:53:11.726988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2363 22:53:11.727779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2365 22:53:11.816992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2366 22:53:11.817774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2368 22:53:11.902359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2369 22:53:11.903146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2371 22:53:11.992738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2372 22:53:11.993528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2374 22:53:12.082247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2375 22:53:12.083014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2377 22:53:12.174790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2378 22:53:12.175566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2380 22:53:12.267072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2381 22:53:12.267856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2383 22:53:12.357396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2384 22:53:12.358249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2386 22:53:12.448779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2387 22:53:12.449566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2389 22:53:12.538631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2390 22:53:12.539424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2392 22:53:12.631062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2393 22:53:12.631847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2395 22:53:12.722339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2396 22:53:12.723119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2398 22:53:12.814851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2399 22:53:12.815646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2401 22:53:12.904744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2402 22:53:12.905547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2404 22:53:12.996534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2405 22:53:12.997342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2407 22:53:13.086397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2408 22:53:13.087187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2410 22:53:13.176556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2411 22:53:13.177341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2413 22:53:13.266391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2414 22:53:13.267198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2416 22:53:13.356145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2417 22:53:13.356935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2419 22:53:13.445609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2420 22:53:13.446416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2422 22:53:13.538433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2423 22:53:13.539240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2425 22:53:13.640554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2426 22:53:13.641366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2428 22:53:13.740242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2429 22:53:13.741068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2431 22:53:13.832258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2432 22:53:13.833045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2434 22:53:13.925914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2435 22:53:13.926727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2437 22:53:14.017967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2438 22:53:14.018781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2440 22:53:14.110820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2441 22:53:14.111588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2443 22:53:14.202677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2444 22:53:14.203428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2446 22:53:14.292962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2447 22:53:14.293572 + set +x
2448 22:53:14.294305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2450 22:53:14.297323 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 851213_1.6.2.4.5>
2451 22:53:14.298100 Received signal: <ENDRUN> 1_kselftest-dt 851213_1.6.2.4.5
2452 22:53:14.298563 Ending use of test pattern.
2453 22:53:14.298971 Ending test lava.1_kselftest-dt (851213_1.6.2.4.5), duration 85.98
2455 22:53:14.304673 <LAVA_TEST_RUNNER EXIT>
2456 22:53:14.305440 ok: lava_test_shell seems to have completed
2457 22:53:14.318734 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2458 22:53:14.320726 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2459 22:53:14.321337 end: 3 lava-test-retry (duration 00:01:27) [common]
2460 22:53:14.321968 start: 4 finalize (timeout 00:05:25) [common]
2461 22:53:14.322579 start: 4.1 power-off (timeout 00:00:30) [common]
2462 22:53:14.323583 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2463 22:53:14.357722 >> OK - accepted request
2464 22:53:14.359750 Returned 0 in 0 seconds
2465 22:53:14.460930 end: 4.1 power-off (duration 00:00:00) [common]
2467 22:53:14.462698 start: 4.2 read-feedback (timeout 00:05:25) [common]
2468 22:53:14.463836 Listened to connection for namespace 'common' for up to 1s
2469 22:53:14.464685 Listened to connection for namespace 'common' for up to 1s
2470 22:53:15.464572 Finalising connection for namespace 'common'
2471 22:53:15.465239 Disconnecting from shell: Finalise
2472 22:53:15.465740 / #
2473 22:53:15.566747 end: 4.2 read-feedback (duration 00:00:01) [common]
2474 22:53:15.567432 end: 4 finalize (duration 00:00:01) [common]
2475 22:53:15.568110 Cleaning after the job
2476 22:53:15.568740 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/ramdisk
2477 22:53:15.577862 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/kernel
2478 22:53:15.584374 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/dtb
2479 22:53:15.585587 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/nfsrootfs
2480 22:53:15.722248 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851213/tftp-deploy-ctcwvbpz/modules
2481 22:53:15.731047 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/851213
2482 22:53:18.600570 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/851213
2483 22:53:18.601167 Job finished correctly