Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:42:49.733997 lava-dispatcher, installed at version: 2024.01
2 04:42:49.734788 start: 0 validate
3 04:42:49.735267 Start time: 2024-10-17 04:42:49.735238+00:00 (UTC)
4 04:42:49.735786 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:42:49.736365 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 04:42:49.779841 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:42:49.780412 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:42:49.811595 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:42:49.812227 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:42:50.864936 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:42:50.865560 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 04:42:50.911527 validate duration: 1.18
14 04:42:50.913055 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:42:50.913684 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:42:50.914260 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:42:50.915213 Not decompressing ramdisk as can be used compressed.
18 04:42:50.915962 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 04:42:50.916463 saving as /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/ramdisk/rootfs.cpio.gz
20 04:42:50.916953 total size: 8181887 (7 MB)
21 04:42:50.960895 progress 0 % (0 MB)
22 04:42:50.974370 progress 5 % (0 MB)
23 04:42:50.987080 progress 10 % (0 MB)
24 04:42:50.998419 progress 15 % (1 MB)
25 04:42:51.004767 progress 20 % (1 MB)
26 04:42:51.011473 progress 25 % (1 MB)
27 04:42:51.017616 progress 30 % (2 MB)
28 04:42:51.024200 progress 35 % (2 MB)
29 04:42:51.030896 progress 40 % (3 MB)
30 04:42:51.038181 progress 45 % (3 MB)
31 04:42:51.044553 progress 50 % (3 MB)
32 04:42:51.051027 progress 55 % (4 MB)
33 04:42:51.057122 progress 60 % (4 MB)
34 04:42:51.063621 progress 65 % (5 MB)
35 04:42:51.069717 progress 70 % (5 MB)
36 04:42:51.076279 progress 75 % (5 MB)
37 04:42:51.082308 progress 80 % (6 MB)
38 04:42:51.088855 progress 85 % (6 MB)
39 04:42:51.094844 progress 90 % (7 MB)
40 04:42:51.101344 progress 95 % (7 MB)
41 04:42:51.107314 progress 100 % (7 MB)
42 04:42:51.108138 7 MB downloaded in 0.19 s (40.82 MB/s)
43 04:42:51.108824 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:42:51.109917 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:42:51.110267 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:42:51.110599 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:42:51.111167 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/kernel/Image
49 04:42:51.111485 saving as /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/kernel/Image
50 04:42:51.111740 total size: 45713920 (43 MB)
51 04:42:51.112024 No compression specified
52 04:42:51.147086 progress 0 % (0 MB)
53 04:42:51.174481 progress 5 % (2 MB)
54 04:42:51.202247 progress 10 % (4 MB)
55 04:42:51.230069 progress 15 % (6 MB)
56 04:42:51.257664 progress 20 % (8 MB)
57 04:42:51.285173 progress 25 % (10 MB)
58 04:42:51.312906 progress 30 % (13 MB)
59 04:42:51.340523 progress 35 % (15 MB)
60 04:42:51.367908 progress 40 % (17 MB)
61 04:42:51.395133 progress 45 % (19 MB)
62 04:42:51.422488 progress 50 % (21 MB)
63 04:42:51.449792 progress 55 % (24 MB)
64 04:42:51.477624 progress 60 % (26 MB)
65 04:42:51.504533 progress 65 % (28 MB)
66 04:42:51.532104 progress 70 % (30 MB)
67 04:42:51.559526 progress 75 % (32 MB)
68 04:42:51.587177 progress 80 % (34 MB)
69 04:42:51.614220 progress 85 % (37 MB)
70 04:42:51.641613 progress 90 % (39 MB)
71 04:42:51.669414 progress 95 % (41 MB)
72 04:42:51.698565 progress 100 % (43 MB)
73 04:42:51.699090 43 MB downloaded in 0.59 s (74.23 MB/s)
74 04:42:51.699579 end: 1.2.1 http-download (duration 00:00:01) [common]
76 04:42:51.700430 end: 1.2 download-retry (duration 00:00:01) [common]
77 04:42:51.700708 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:42:51.700972 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:42:51.701437 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 04:42:51.701715 saving as /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/dtb/meson-g12b-a311d-libretech-cc.dtb
81 04:42:51.701924 total size: 54703 (0 MB)
82 04:42:51.702133 No compression specified
83 04:42:51.745481 progress 59 % (0 MB)
84 04:42:51.746336 progress 100 % (0 MB)
85 04:42:51.746896 0 MB downloaded in 0.04 s (1.16 MB/s)
86 04:42:51.747364 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:42:51.748225 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:42:51.748495 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:42:51.748760 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:42:51.749213 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/modules.tar.xz
92 04:42:51.749469 saving as /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/modules/modules.tar
93 04:42:51.749674 total size: 11619040 (11 MB)
94 04:42:51.749884 Using unxz to decompress xz
95 04:42:51.786041 progress 0 % (0 MB)
96 04:42:51.846899 progress 5 % (0 MB)
97 04:42:51.924194 progress 10 % (1 MB)
98 04:42:52.009237 progress 15 % (1 MB)
99 04:42:52.099634 progress 20 % (2 MB)
100 04:42:52.181762 progress 25 % (2 MB)
101 04:42:52.258855 progress 30 % (3 MB)
102 04:42:52.340331 progress 35 % (3 MB)
103 04:42:52.414984 progress 40 % (4 MB)
104 04:42:52.491321 progress 45 % (5 MB)
105 04:42:52.572245 progress 50 % (5 MB)
106 04:42:52.654220 progress 55 % (6 MB)
107 04:42:52.731933 progress 60 % (6 MB)
108 04:42:52.805959 progress 65 % (7 MB)
109 04:42:52.884554 progress 70 % (7 MB)
110 04:42:52.956396 progress 75 % (8 MB)
111 04:42:53.031884 progress 80 % (8 MB)
112 04:42:53.114374 progress 85 % (9 MB)
113 04:42:53.196735 progress 90 % (10 MB)
114 04:42:53.271158 progress 95 % (10 MB)
115 04:42:53.349167 progress 100 % (11 MB)
116 04:42:53.361914 11 MB downloaded in 1.61 s (6.87 MB/s)
117 04:42:53.362527 end: 1.4.1 http-download (duration 00:00:02) [common]
119 04:42:53.363367 end: 1.4 download-retry (duration 00:00:02) [common]
120 04:42:53.363640 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 04:42:53.363913 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 04:42:53.364451 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:42:53.364970 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 04:42:53.365960 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk
125 04:42:53.366799 makedir: /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin
126 04:42:53.367433 makedir: /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/tests
127 04:42:53.368070 makedir: /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/results
128 04:42:53.368710 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-add-keys
129 04:42:53.369654 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-add-sources
130 04:42:53.370581 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-background-process-start
131 04:42:53.371510 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-background-process-stop
132 04:42:53.372522 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-common-functions
133 04:42:53.373447 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-echo-ipv4
134 04:42:53.374338 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-install-packages
135 04:42:53.375228 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-installed-packages
136 04:42:53.376142 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-os-build
137 04:42:53.377042 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-probe-channel
138 04:42:53.377925 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-probe-ip
139 04:42:53.378804 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-target-ip
140 04:42:53.379677 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-target-mac
141 04:42:53.380600 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-target-storage
142 04:42:53.381523 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-test-case
143 04:42:53.382410 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-test-event
144 04:42:53.383286 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-test-feedback
145 04:42:53.384223 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-test-raise
146 04:42:53.385150 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-test-reference
147 04:42:53.386046 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-test-runner
148 04:42:53.386932 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-test-set
149 04:42:53.387810 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-test-shell
150 04:42:53.388757 Updating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-install-packages (oe)
151 04:42:53.389731 Updating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/bin/lava-installed-packages (oe)
152 04:42:53.390562 Creating /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/environment
153 04:42:53.391267 LAVA metadata
154 04:42:53.391762 - LAVA_JOB_ID=851290
155 04:42:53.392230 - LAVA_DISPATCHER_IP=192.168.6.2
156 04:42:53.392867 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 04:42:53.394611 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 04:42:53.395224 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 04:42:53.395636 skipped lava-vland-overlay
160 04:42:53.396152 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 04:42:53.396666 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 04:42:53.397090 skipped lava-multinode-overlay
163 04:42:53.397571 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 04:42:53.398067 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 04:42:53.398535 Loading test definitions
166 04:42:53.399078 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 04:42:53.399520 Using /lava-851290 at stage 0
168 04:42:53.400976 uuid=851290_1.5.2.4.1 testdef=None
169 04:42:53.401331 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 04:42:53.401609 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 04:42:53.403410 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 04:42:53.404273 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 04:42:53.406517 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 04:42:53.407413 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 04:42:53.409625 runner path: /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/0/tests/0_dmesg test_uuid 851290_1.5.2.4.1
178 04:42:53.410208 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 04:42:53.411013 Creating lava-test-runner.conf files
181 04:42:53.411219 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/851290/lava-overlay-yqa26kqk/lava-851290/0 for stage 0
182 04:42:53.411544 - 0_dmesg
183 04:42:53.411902 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 04:42:53.412231 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 04:42:53.435443 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 04:42:53.435851 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 04:42:53.436158 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 04:42:53.436428 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 04:42:53.436695 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 04:42:54.338212 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 04:42:54.338745 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 04:42:54.339249 extracting modules file /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/851290/extract-overlay-ramdisk-_mi55auu/ramdisk
193 04:42:55.651785 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 04:42:55.652302 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 04:42:55.652612 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851290/compress-overlay-f36skcoj/overlay-1.5.2.5.tar.gz to ramdisk
196 04:42:55.652852 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851290/compress-overlay-f36skcoj/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/851290/extract-overlay-ramdisk-_mi55auu/ramdisk
197 04:42:55.682501 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 04:42:55.682899 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 04:42:55.683170 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 04:42:55.683397 Converting downloaded kernel to a uImage
201 04:42:55.683695 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/kernel/Image /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/kernel/uImage
202 04:42:56.159758 output: Image Name:
203 04:42:56.160211 output: Created: Thu Oct 17 04:42:55 2024
204 04:42:56.160425 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 04:42:56.160628 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 04:42:56.160828 output: Load Address: 01080000
207 04:42:56.161029 output: Entry Point: 01080000
208 04:42:56.161224 output:
209 04:42:56.161554 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 04:42:56.161824 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 04:42:56.162095 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 04:42:56.162348 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 04:42:56.162604 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 04:42:56.162857 Building ramdisk /var/lib/lava/dispatcher/tmp/851290/extract-overlay-ramdisk-_mi55auu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/851290/extract-overlay-ramdisk-_mi55auu/ramdisk
215 04:42:58.485696 >> 181555 blocks
216 04:43:07.097157 Adding RAMdisk u-boot header.
217 04:43:07.097824 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/851290/extract-overlay-ramdisk-_mi55auu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/851290/extract-overlay-ramdisk-_mi55auu/ramdisk.cpio.gz.uboot
218 04:43:07.378963 output: Image Name:
219 04:43:07.379371 output: Created: Thu Oct 17 04:43:07 2024
220 04:43:07.379579 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 04:43:07.379781 output: Data Size: 26049180 Bytes = 25438.65 KiB = 24.84 MiB
222 04:43:07.380015 output: Load Address: 00000000
223 04:43:07.380413 output: Entry Point: 00000000
224 04:43:07.380804 output:
225 04:43:07.381880 rename /var/lib/lava/dispatcher/tmp/851290/extract-overlay-ramdisk-_mi55auu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/ramdisk/ramdisk.cpio.gz.uboot
226 04:43:07.382607 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 04:43:07.383137 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 04:43:07.383651 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 04:43:07.384136 No LXC device requested
230 04:43:07.384634 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 04:43:07.385133 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 04:43:07.385616 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 04:43:07.386025 Checking files for TFTP limit of 4294967296 bytes.
234 04:43:07.388697 end: 1 tftp-deploy (duration 00:00:16) [common]
235 04:43:07.389281 start: 2 uboot-action (timeout 00:05:00) [common]
236 04:43:07.389800 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 04:43:07.390292 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 04:43:07.390785 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 04:43:07.391308 Using kernel file from prepare-kernel: 851290/tftp-deploy-klvk4in7/kernel/uImage
240 04:43:07.391919 substitutions:
241 04:43:07.392362 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 04:43:07.392763 - {DTB_ADDR}: 0x01070000
243 04:43:07.393157 - {DTB}: 851290/tftp-deploy-klvk4in7/dtb/meson-g12b-a311d-libretech-cc.dtb
244 04:43:07.393552 - {INITRD}: 851290/tftp-deploy-klvk4in7/ramdisk/ramdisk.cpio.gz.uboot
245 04:43:07.393942 - {KERNEL_ADDR}: 0x01080000
246 04:43:07.394332 - {KERNEL}: 851290/tftp-deploy-klvk4in7/kernel/uImage
247 04:43:07.394722 - {LAVA_MAC}: None
248 04:43:07.395148 - {PRESEED_CONFIG}: None
249 04:43:07.395536 - {PRESEED_LOCAL}: None
250 04:43:07.395923 - {RAMDISK_ADDR}: 0x08000000
251 04:43:07.396334 - {RAMDISK}: 851290/tftp-deploy-klvk4in7/ramdisk/ramdisk.cpio.gz.uboot
252 04:43:07.396725 - {ROOT_PART}: None
253 04:43:07.397110 - {ROOT}: None
254 04:43:07.397495 - {SERVER_IP}: 192.168.6.2
255 04:43:07.397884 - {TEE_ADDR}: 0x83000000
256 04:43:07.398270 - {TEE}: None
257 04:43:07.398655 Parsed boot commands:
258 04:43:07.399028 - setenv autoload no
259 04:43:07.399412 - setenv initrd_high 0xffffffff
260 04:43:07.399793 - setenv fdt_high 0xffffffff
261 04:43:07.400249 - dhcp
262 04:43:07.400643 - setenv serverip 192.168.6.2
263 04:43:07.401025 - tftpboot 0x01080000 851290/tftp-deploy-klvk4in7/kernel/uImage
264 04:43:07.401406 - tftpboot 0x08000000 851290/tftp-deploy-klvk4in7/ramdisk/ramdisk.cpio.gz.uboot
265 04:43:07.401791 - tftpboot 0x01070000 851290/tftp-deploy-klvk4in7/dtb/meson-g12b-a311d-libretech-cc.dtb
266 04:43:07.402174 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 04:43:07.402563 - bootm 0x01080000 0x08000000 0x01070000
268 04:43:07.403051 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 04:43:07.404554 start: 2.3 connect-device (timeout 00:05:00) [common]
271 04:43:07.404994 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 04:43:07.419091 Setting prompt string to ['lava-test: # ']
273 04:43:07.420573 end: 2.3 connect-device (duration 00:00:00) [common]
274 04:43:07.421155 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 04:43:07.421679 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 04:43:07.422197 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 04:43:07.423324 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 04:43:07.459328 >> OK - accepted request
279 04:43:07.461462 Returned 0 in 0 seconds
280 04:43:07.562523 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 04:43:07.564068 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 04:43:07.564633 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 04:43:07.565123 Setting prompt string to ['Hit any key to stop autoboot']
285 04:43:07.565567 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 04:43:07.567106 Trying 192.168.56.21...
287 04:43:07.567591 Connected to conserv1.
288 04:43:07.568025 Escape character is '^]'.
289 04:43:07.568442
290 04:43:07.568861 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 04:43:07.569285
292 04:43:19.000170 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 04:43:19.000783 bl2_stage_init 0x01
294 04:43:19.001205 bl2_stage_init 0x81
295 04:43:19.005717 hw id: 0x0000 - pwm id 0x01
296 04:43:19.006188 bl2_stage_init 0xc1
297 04:43:19.006592 bl2_stage_init 0x02
298 04:43:19.006997
299 04:43:19.011423 L0:00000000
300 04:43:19.011856 L1:20000703
301 04:43:19.012286 L2:00008067
302 04:43:19.012673 L3:14000000
303 04:43:19.014312 B2:00402000
304 04:43:19.014744 B1:e0f83180
305 04:43:19.015132
306 04:43:19.015517 TE: 58124
307 04:43:19.015901
308 04:43:19.025568 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 04:43:19.025994
310 04:43:19.026384 Board ID = 1
311 04:43:19.026766 Set A53 clk to 24M
312 04:43:19.027145 Set A73 clk to 24M
313 04:43:19.031111 Set clk81 to 24M
314 04:43:19.031526 A53 clk: 1200 MHz
315 04:43:19.031910 A73 clk: 1200 MHz
316 04:43:19.034556 CLK81: 166.6M
317 04:43:19.034968 smccc: 00012a92
318 04:43:19.040097 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 04:43:19.045746 board id: 1
320 04:43:19.050822 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 04:43:19.061442 fw parse done
322 04:43:19.067500 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 04:43:19.110117 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 04:43:19.120918 PIEI prepare done
325 04:43:19.121367 fastboot data load
326 04:43:19.121755 fastboot data verify
327 04:43:19.126480 verify result: 266
328 04:43:19.132062 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 04:43:19.132476 LPDDR4 probe
330 04:43:19.132862 ddr clk to 1584MHz
331 04:43:19.140078 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 04:43:19.177292
333 04:43:19.177706 dmc_version 0001
334 04:43:19.184027 Check phy result
335 04:43:19.189860 INFO : End of CA training
336 04:43:19.190274 INFO : End of initialization
337 04:43:19.195526 INFO : Training has run successfully!
338 04:43:19.195937 Check phy result
339 04:43:19.201095 INFO : End of initialization
340 04:43:19.201506 INFO : End of read enable training
341 04:43:19.206678 INFO : End of fine write leveling
342 04:43:19.212270 INFO : End of Write leveling coarse delay
343 04:43:19.212689 INFO : Training has run successfully!
344 04:43:19.213080 Check phy result
345 04:43:19.217835 INFO : End of initialization
346 04:43:19.218245 INFO : End of read dq deskew training
347 04:43:19.223461 INFO : End of MPR read delay center optimization
348 04:43:19.229059 INFO : End of write delay center optimization
349 04:43:19.234717 INFO : End of read delay center optimization
350 04:43:19.235140 INFO : End of max read latency training
351 04:43:19.240264 INFO : Training has run successfully!
352 04:43:19.240678 1D training succeed
353 04:43:19.249514 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 04:43:19.297118 Check phy result
355 04:43:19.297651 INFO : End of initialization
356 04:43:19.319630 INFO : End of 2D read delay Voltage center optimization
357 04:43:19.392186 INFO : End of 2D read delay Voltage center optimization
358 04:43:19.392664 INFO : End of 2D write delay Voltage center optimization
359 04:43:19.441293 INFO : End of 2D write delay Voltage center optimization
360 04:43:19.446831 INFO : Training has run successfully!
361 04:43:19.447252
362 04:43:19.447642 channel==0
363 04:43:19.452416 RxClkDly_Margin_A0==88 ps 9
364 04:43:19.452835 TxDqDly_Margin_A0==98 ps 10
365 04:43:19.455789 RxClkDly_Margin_A1==88 ps 9
366 04:43:19.456239 TxDqDly_Margin_A1==98 ps 10
367 04:43:19.461313 TrainedVREFDQ_A0==74
368 04:43:19.461727 TrainedVREFDQ_A1==74
369 04:43:19.462114 VrefDac_Margin_A0==24
370 04:43:19.466947 DeviceVref_Margin_A0==40
371 04:43:19.467375 VrefDac_Margin_A1==24
372 04:43:19.472583 DeviceVref_Margin_A1==40
373 04:43:19.473009
374 04:43:19.473400
375 04:43:19.473785 channel==1
376 04:43:19.474168 RxClkDly_Margin_A0==98 ps 10
377 04:43:19.478143 TxDqDly_Margin_A0==88 ps 9
378 04:43:19.478567 RxClkDly_Margin_A1==98 ps 10
379 04:43:19.483776 TxDqDly_Margin_A1==88 ps 9
380 04:43:19.484220 TrainedVREFDQ_A0==77
381 04:43:19.484613 TrainedVREFDQ_A1==77
382 04:43:19.489350 VrefDac_Margin_A0==22
383 04:43:19.489757 DeviceVref_Margin_A0==37
384 04:43:19.494929 VrefDac_Margin_A1==22
385 04:43:19.495332 DeviceVref_Margin_A1==37
386 04:43:19.495712
387 04:43:19.500558 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 04:43:19.500977
389 04:43:19.528482 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 04:43:19.534060 2D training succeed
391 04:43:19.539708 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 04:43:19.540152 auto size-- 65535DDR cs0 size: 2048MB
393 04:43:19.545288 DDR cs1 size: 2048MB
394 04:43:19.545698 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 04:43:19.550849 cs0 DataBus test pass
396 04:43:19.551261 cs1 DataBus test pass
397 04:43:19.551643 cs0 AddrBus test pass
398 04:43:19.556497 cs1 AddrBus test pass
399 04:43:19.556925
400 04:43:19.557314 100bdlr_step_size ps== 420
401 04:43:19.557713 result report
402 04:43:19.562051 boot times 0Enable ddr reg access
403 04:43:19.569680 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 04:43:19.583177 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 04:43:20.156795 0.0;M3 CHK:0;cm4_sp_mode 0
406 04:43:20.157272 MVN_1=0x00000000
407 04:43:20.162342 MVN_2=0x00000000
408 04:43:20.168097 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 04:43:20.168525 OPS=0x10
410 04:43:20.168927 ring efuse init
411 04:43:20.169319 chipver efuse init
412 04:43:20.173697 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 04:43:20.179318 [0.018961 Inits done]
414 04:43:20.179743 secure task start!
415 04:43:20.180199 high task start!
416 04:43:20.183861 low task start!
417 04:43:20.184319 run into bl31
418 04:43:20.190567 NOTICE: BL31: v1.3(release):4fc40b1
419 04:43:20.198338 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 04:43:20.198771 NOTICE: BL31: G12A normal boot!
421 04:43:20.223674 NOTICE: BL31: BL33 decompress pass
422 04:43:20.229345 ERROR: Error initializing runtime service opteed_fast
423 04:43:21.462246
424 04:43:21.462739
425 04:43:21.470708 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 04:43:21.471144
427 04:43:21.471548 Model: Libre Computer AML-A311D-CC Alta
428 04:43:21.679112 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 04:43:21.702516 DRAM: 2 GiB (effective 3.8 GiB)
430 04:43:21.845448 Core: 408 devices, 31 uclasses, devicetree: separate
431 04:43:21.851334 WDT: Not starting watchdog@f0d0
432 04:43:21.883598 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 04:43:21.896076 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 04:43:21.901028 ** Bad device specification mmc 0 **
435 04:43:21.911386 Card did not respond to voltage select! : -110
436 04:43:21.919029 ** Bad device specification mmc 0 **
437 04:43:21.919463 Couldn't find partition mmc 0
438 04:43:21.927364 Card did not respond to voltage select! : -110
439 04:43:21.932878 ** Bad device specification mmc 0 **
440 04:43:21.933309 Couldn't find partition mmc 0
441 04:43:21.937931 Error: could not access storage.
442 04:43:23.200402 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 04:43:23.200899 bl2_stage_init 0x01
444 04:43:23.201325 bl2_stage_init 0x81
445 04:43:23.205996 hw id: 0x0000 - pwm id 0x01
446 04:43:23.206424 bl2_stage_init 0xc1
447 04:43:23.206822 bl2_stage_init 0x02
448 04:43:23.207215
449 04:43:23.211592 L0:00000000
450 04:43:23.212059 L1:20000703
451 04:43:23.212468 L2:00008067
452 04:43:23.212859 L3:14000000
453 04:43:23.217181 B2:00402000
454 04:43:23.217609 B1:e0f83180
455 04:43:23.218007
456 04:43:23.218403 TE: 58159
457 04:43:23.218805
458 04:43:23.222865 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 04:43:23.223292
460 04:43:23.223693 Board ID = 1
461 04:43:23.228394 Set A53 clk to 24M
462 04:43:23.228815 Set A73 clk to 24M
463 04:43:23.229214 Set clk81 to 24M
464 04:43:23.233983 A53 clk: 1200 MHz
465 04:43:23.234406 A73 clk: 1200 MHz
466 04:43:23.234804 CLK81: 166.6M
467 04:43:23.235194 smccc: 00012ab5
468 04:43:23.239576 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 04:43:23.245166 board id: 1
470 04:43:23.251042 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 04:43:23.261722 fw parse done
472 04:43:23.267700 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 04:43:23.310503 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 04:43:23.321197 PIEI prepare done
475 04:43:23.321615 fastboot data load
476 04:43:23.322019 fastboot data verify
477 04:43:23.326978 verify result: 266
478 04:43:23.332493 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 04:43:23.332913 LPDDR4 probe
480 04:43:23.333313 ddr clk to 1584MHz
481 04:43:23.340443 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 04:43:23.377690
483 04:43:23.378111 dmc_version 0001
484 04:43:23.384390 Check phy result
485 04:43:23.390278 INFO : End of CA training
486 04:43:23.390708 INFO : End of initialization
487 04:43:23.395870 INFO : Training has run successfully!
488 04:43:23.396336 Check phy result
489 04:43:23.401463 INFO : End of initialization
490 04:43:23.401882 INFO : End of read enable training
491 04:43:23.407077 INFO : End of fine write leveling
492 04:43:23.412696 INFO : End of Write leveling coarse delay
493 04:43:23.413119 INFO : Training has run successfully!
494 04:43:23.413518 Check phy result
495 04:43:23.418345 INFO : End of initialization
496 04:43:23.418760 INFO : End of read dq deskew training
497 04:43:23.423867 INFO : End of MPR read delay center optimization
498 04:43:23.429459 INFO : End of write delay center optimization
499 04:43:23.435061 INFO : End of read delay center optimization
500 04:43:23.435478 INFO : End of max read latency training
501 04:43:23.440655 INFO : Training has run successfully!
502 04:43:23.441076 1D training succeed
503 04:43:23.449865 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 04:43:23.497468 Check phy result
505 04:43:23.497961 INFO : End of initialization
506 04:43:23.519178 INFO : End of 2D read delay Voltage center optimization
507 04:43:23.538560 INFO : End of 2D read delay Voltage center optimization
508 04:43:23.590606 INFO : End of 2D write delay Voltage center optimization
509 04:43:23.640185 INFO : End of 2D write delay Voltage center optimization
510 04:43:23.645522 INFO : Training has run successfully!
511 04:43:23.646024
512 04:43:23.646441 channel==0
513 04:43:23.651146 RxClkDly_Margin_A0==88 ps 9
514 04:43:23.651605 TxDqDly_Margin_A0==98 ps 10
515 04:43:23.656737 RxClkDly_Margin_A1==88 ps 9
516 04:43:23.657199 TxDqDly_Margin_A1==98 ps 10
517 04:43:23.657610 TrainedVREFDQ_A0==74
518 04:43:23.662341 TrainedVREFDQ_A1==74
519 04:43:23.662796 VrefDac_Margin_A0==25
520 04:43:23.663200 DeviceVref_Margin_A0==40
521 04:43:23.668025 VrefDac_Margin_A1==25
522 04:43:23.668511 DeviceVref_Margin_A1==40
523 04:43:23.668917
524 04:43:23.669322
525 04:43:23.673538 channel==1
526 04:43:23.674000 RxClkDly_Margin_A0==88 ps 9
527 04:43:23.674418 TxDqDly_Margin_A0==98 ps 10
528 04:43:23.890256 RxClkDly_Margin_A1==88 ps 9
529 04:43:23.890722 TxDqDly_Margin_A1==88 ps 9
530 04:43:23.891132 TrainedVREFDQ_A0==77
531 04:43:23.891533 TrainedVREFDQ_A1==77
532 04:43:23.891930 VrefDac_Margin_A0==23
533 04:43:24.306393 DeviceVref_Margin_A0==37
534 04:43:24.306856 VrefDac_Margin_A1==24
535 04:43:24.307279 DeviceVref_Margin_A1==37
536 04:43:24.307702
537 04:43:24.308174 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 04:43:24.308590
539 04:43:24.308978 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 04:43:24.309380 2D training succeed
541 04:43:24.309769 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 04:43:24.310153 auto size-- 65535DDR cs0 size: 2048MB
543 04:43:24.310532 DDR cs1 size: 2048MB
544 04:43:24.310907 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 04:43:24.311285 cs0 DataBus test pass
546 04:43:24.311660 cs1 DataBus test pass
547 04:43:24.312067 cs0 AddrBus test pass
548 04:43:24.312450 cs1 AddrBus test pass
549 04:43:24.312827
550 04:43:24.313202 100bdlr_step_size ps== 420
551 04:43:24.313585 result report
552 04:43:24.313958 boot times 0Enable ddr reg access
553 04:43:24.314344 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 04:43:24.314727 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 04:43:24.355475 0.0;M3 CHK:0;cm4_sp_mode 0
556 04:43:24.356021 MVN_1=0x00000000
557 04:43:24.361020 MVN_2=0x00000000
558 04:43:24.366781 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 04:43:24.367203 OPS=0x10
560 04:43:24.367599 ring efuse init
561 04:43:24.367976 chipver efuse init
562 04:43:24.372396 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 04:43:24.378012 [0.018960 Inits done]
564 04:43:24.378426 secure task start!
565 04:43:24.378806 high task start!
566 04:43:24.382544 low task start!
567 04:43:24.382952 run into bl31
568 04:43:24.389174 NOTICE: BL31: v1.3(release):4fc40b1
569 04:43:24.396943 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 04:43:24.397360 NOTICE: BL31: G12A normal boot!
571 04:43:24.422353 NOTICE: BL31: BL33 decompress pass
572 04:43:24.428120 ERROR: Error initializing runtime service opteed_fast
573 04:43:25.661143
574 04:43:25.661620
575 04:43:25.669531 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 04:43:25.669981
577 04:43:25.670391 Model: Libre Computer AML-A311D-CC Alta
578 04:43:25.877947 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 04:43:25.900684 DRAM: 2 GiB (effective 3.8 GiB)
580 04:43:26.044204 Core: 408 devices, 31 uclasses, devicetree: separate
581 04:43:26.050174 WDT: Not starting watchdog@f0d0
582 04:43:26.082379 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 04:43:26.094843 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 04:43:26.110710 ** Bad device specification mmc 0 **
585 04:43:26.111140 Card did not respond to voltage select! : -110
586 04:43:26.116994 ** Bad device specification mmc 0 **
587 04:43:26.117420 Couldn't find partition mmc 0
588 04:43:26.126407 Card did not respond to voltage select! : -110
589 04:43:26.131853 ** Bad device specification mmc 0 **
590 04:43:26.132332 Couldn't find partition mmc 0
591 04:43:26.136647 Error: could not access storage.
592 04:43:26.479141 Net: eth0: ethernet@ff3f0000
593 04:43:26.479583 starting USB...
594 04:43:26.730912 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 04:43:26.731364 Starting the controller
596 04:43:26.737929 USB XHCI 1.10
597 04:43:28.450551 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 04:43:28.451135 bl2_stage_init 0x01
599 04:43:28.451550 bl2_stage_init 0x81
600 04:43:28.456154 hw id: 0x0000 - pwm id 0x01
601 04:43:28.456601 bl2_stage_init 0xc1
602 04:43:28.457004 bl2_stage_init 0x02
603 04:43:28.457401
604 04:43:28.461749 L0:00000000
605 04:43:28.462180 L1:20000703
606 04:43:28.462580 L2:00008067
607 04:43:28.462973 L3:14000000
608 04:43:28.464646 B2:00402000
609 04:43:28.465072 B1:e0f83180
610 04:43:28.465471
611 04:43:28.465869 TE: 58159
612 04:43:28.466265
613 04:43:28.475813 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 04:43:28.476293
615 04:43:28.476703 Board ID = 1
616 04:43:28.477098 Set A53 clk to 24M
617 04:43:28.477491 Set A73 clk to 24M
618 04:43:28.481330 Set clk81 to 24M
619 04:43:28.481759 A53 clk: 1200 MHz
620 04:43:28.482160 A73 clk: 1200 MHz
621 04:43:28.486952 CLK81: 166.6M
622 04:43:28.487376 smccc: 00012ab5
623 04:43:28.492600 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 04:43:28.493034 board id: 1
625 04:43:28.501251 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 04:43:28.511773 fw parse done
627 04:43:28.517802 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 04:43:28.560377 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 04:43:28.571267 PIEI prepare done
630 04:43:28.571708 fastboot data load
631 04:43:28.572144 fastboot data verify
632 04:43:28.576991 verify result: 266
633 04:43:28.590626 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 04:43:28.591049 LPDDR4 probe
635 04:43:28.591445 ddr clk to 1584MHz
636 04:43:28.591838 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 04:43:28.627899
638 04:43:28.628373 dmc_version 0001
639 04:43:28.634492 Check phy result
640 04:43:28.640354 INFO : End of CA training
641 04:43:28.640778 INFO : End of initialization
642 04:43:28.645949 INFO : Training has run successfully!
643 04:43:28.646372 Check phy result
644 04:43:28.651553 INFO : End of initialization
645 04:43:28.651976 INFO : End of read enable training
646 04:43:28.657149 INFO : End of fine write leveling
647 04:43:28.662746 INFO : End of Write leveling coarse delay
648 04:43:28.663167 INFO : Training has run successfully!
649 04:43:28.663563 Check phy result
650 04:43:28.668364 INFO : End of initialization
651 04:43:28.668791 INFO : End of read dq deskew training
652 04:43:28.673926 INFO : End of MPR read delay center optimization
653 04:43:28.679587 INFO : End of write delay center optimization
654 04:43:28.685140 INFO : End of read delay center optimization
655 04:43:28.685564 INFO : End of max read latency training
656 04:43:28.690733 INFO : Training has run successfully!
657 04:43:28.691156 1D training succeed
658 04:43:28.699959 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 04:43:28.747498 Check phy result
660 04:43:28.747930 INFO : End of initialization
661 04:43:28.769314 INFO : End of 2D read delay Voltage center optimization
662 04:43:28.789523 INFO : End of 2D read delay Voltage center optimization
663 04:43:28.841724 INFO : End of 2D write delay Voltage center optimization
664 04:43:28.890950 INFO : End of 2D write delay Voltage center optimization
665 04:43:28.896506 INFO : Training has run successfully!
666 04:43:28.896925
667 04:43:28.897337 channel==0
668 04:43:28.902141 RxClkDly_Margin_A0==88 ps 9
669 04:43:28.902568 TxDqDly_Margin_A0==98 ps 10
670 04:43:28.907762 RxClkDly_Margin_A1==88 ps 9
671 04:43:28.908236 TxDqDly_Margin_A1==98 ps 10
672 04:43:28.908646 TrainedVREFDQ_A0==74
673 04:43:28.913372 TrainedVREFDQ_A1==74
674 04:43:28.913805 VrefDac_Margin_A0==25
675 04:43:28.914200 DeviceVref_Margin_A0==40
676 04:43:28.918870 VrefDac_Margin_A1==25
677 04:43:28.919292 DeviceVref_Margin_A1==40
678 04:43:28.919687
679 04:43:28.920113
680 04:43:28.924480 channel==1
681 04:43:28.924906 RxClkDly_Margin_A0==98 ps 10
682 04:43:28.925302 TxDqDly_Margin_A0==98 ps 10
683 04:43:28.930115 RxClkDly_Margin_A1==98 ps 10
684 04:43:28.930542 TxDqDly_Margin_A1==88 ps 9
685 04:43:28.935722 TrainedVREFDQ_A0==77
686 04:43:28.936180 TrainedVREFDQ_A1==77
687 04:43:28.936586 VrefDac_Margin_A0==22
688 04:43:28.941239 DeviceVref_Margin_A0==37
689 04:43:28.941662 VrefDac_Margin_A1==22
690 04:43:28.946847 DeviceVref_Margin_A1==37
691 04:43:28.947271
692 04:43:28.947666 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 04:43:28.952427
694 04:43:28.986159 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 04:43:28.986622 2D training succeed
696 04:43:28.987034 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 04:43:28.991624 auto size-- 65535DDR cs0 size: 2048MB
698 04:43:28.992079 DDR cs1 size: 2048MB
699 04:43:28.997246 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 04:43:28.997672 cs0 DataBus test pass
701 04:43:29.002848 cs1 DataBus test pass
702 04:43:29.003274 cs0 AddrBus test pass
703 04:43:29.003672 cs1 AddrBus test pass
704 04:43:29.004094
705 04:43:29.008440 100bdlr_step_size ps== 420
706 04:43:29.008877 result report
707 04:43:29.014012 boot times 0Enable ddr reg access
708 04:43:29.019491 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 04:43:29.032973 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 04:43:29.606705 0.0;M3 CHK:0;cm4_sp_mode 0
711 04:43:29.607201 MVN_1=0x00000000
712 04:43:29.612283 MVN_2=0x00000000
713 04:43:29.618038 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 04:43:29.618525 OPS=0x10
715 04:43:29.618913 ring efuse init
716 04:43:29.619288 chipver efuse init
717 04:43:29.623508 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 04:43:29.629182 [0.018960 Inits done]
719 04:43:29.629605 secure task start!
720 04:43:29.629987 high task start!
721 04:43:29.633749 low task start!
722 04:43:29.634160 run into bl31
723 04:43:29.640444 NOTICE: BL31: v1.3(release):4fc40b1
724 04:43:29.648236 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 04:43:29.648657 NOTICE: BL31: G12A normal boot!
726 04:43:29.673664 NOTICE: BL31: BL33 decompress pass
727 04:43:29.679386 ERROR: Error initializing runtime service opteed_fast
728 04:43:30.912238
729 04:43:30.912750
730 04:43:30.920647 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 04:43:30.921084
732 04:43:30.921487 Model: Libre Computer AML-A311D-CC Alta
733 04:43:31.128975 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 04:43:31.152381 DRAM: 2 GiB (effective 3.8 GiB)
735 04:43:31.295374 Core: 408 devices, 31 uclasses, devicetree: separate
736 04:43:31.301287 WDT: Not starting watchdog@f0d0
737 04:43:31.333597 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 04:43:31.351098 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 04:43:31.351525 ** Bad device specification mmc 0 **
740 04:43:31.361238 Card did not respond to voltage select! : -110
741 04:43:31.390410 ** Bad device specification mmc 0 **
742 04:43:31.390838 Couldn't find partition mmc 0
743 04:43:31.391237 Card did not respond to voltage select! : -110
744 04:43:31.391633 ** Bad device specification mmc 0 **
745 04:43:31.392064 Couldn't find partition mmc 0
746 04:43:31.392463 Error: could not access storage.
747 04:43:31.731428 Net: eth0: ethernet@ff3f0000
748 04:43:31.731874 starting USB...
749 04:43:31.983288 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 04:43:31.983743 Starting the controller
751 04:43:31.990185 USB XHCI 1.10
752 04:43:34.152247 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 04:43:34.152788 bl2_stage_init 0x01
754 04:43:34.153202 bl2_stage_init 0x81
755 04:43:34.157841 hw id: 0x0000 - pwm id 0x01
756 04:43:34.158278 bl2_stage_init 0xc1
757 04:43:34.158683 bl2_stage_init 0x02
758 04:43:34.159077
759 04:43:34.163441 L0:00000000
760 04:43:34.163865 L1:20000703
761 04:43:34.164316 L2:00008067
762 04:43:34.164712 L3:14000000
763 04:43:34.169027 B2:00402000
764 04:43:34.169451 B1:e0f83180
765 04:43:34.169849
766 04:43:34.170244 TE: 58124
767 04:43:34.170634
768 04:43:34.174600 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 04:43:34.175033
770 04:43:34.175433 Board ID = 1
771 04:43:34.180219 Set A53 clk to 24M
772 04:43:34.180646 Set A73 clk to 24M
773 04:43:34.181044 Set clk81 to 24M
774 04:43:34.185815 A53 clk: 1200 MHz
775 04:43:34.186236 A73 clk: 1200 MHz
776 04:43:34.186628 CLK81: 166.6M
777 04:43:34.187015 smccc: 00012a92
778 04:43:34.191403 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 04:43:34.197018 board id: 1
780 04:43:34.202895 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 04:43:34.213471 fw parse done
782 04:43:34.219489 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 04:43:34.262111 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 04:43:34.272957 PIEI prepare done
785 04:43:34.273385 fastboot data load
786 04:43:34.273786 fastboot data verify
787 04:43:34.278664 verify result: 266
788 04:43:34.284227 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 04:43:34.284651 LPDDR4 probe
790 04:43:34.285045 ddr clk to 1584MHz
791 04:43:34.292224 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 04:43:34.329490
793 04:43:34.329914 dmc_version 0001
794 04:43:34.336221 Check phy result
795 04:43:34.342088 INFO : End of CA training
796 04:43:34.342508 INFO : End of initialization
797 04:43:34.347701 INFO : Training has run successfully!
798 04:43:34.348167 Check phy result
799 04:43:34.353273 INFO : End of initialization
800 04:43:34.353692 INFO : End of read enable training
801 04:43:34.358805 INFO : End of fine write leveling
802 04:43:34.364547 INFO : End of Write leveling coarse delay
803 04:43:34.364969 INFO : Training has run successfully!
804 04:43:34.365367 Check phy result
805 04:43:34.370089 INFO : End of initialization
806 04:43:34.370510 INFO : End of read dq deskew training
807 04:43:34.375679 INFO : End of MPR read delay center optimization
808 04:43:34.381254 INFO : End of write delay center optimization
809 04:43:34.386870 INFO : End of read delay center optimization
810 04:43:34.387291 INFO : End of max read latency training
811 04:43:34.392612 INFO : Training has run successfully!
812 04:43:34.393032 1D training succeed
813 04:43:34.400717 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 04:43:34.449161 Check phy result
815 04:43:34.449581 INFO : End of initialization
816 04:43:34.470873 INFO : End of 2D read delay Voltage center optimization
817 04:43:34.491100 INFO : End of 2D read delay Voltage center optimization
818 04:43:34.543169 INFO : End of 2D write delay Voltage center optimization
819 04:43:34.592545 INFO : End of 2D write delay Voltage center optimization
820 04:43:34.598116 INFO : Training has run successfully!
821 04:43:34.598536
822 04:43:34.598939 channel==0
823 04:43:34.603719 RxClkDly_Margin_A0==88 ps 9
824 04:43:34.604196 TxDqDly_Margin_A0==98 ps 10
825 04:43:34.609304 RxClkDly_Margin_A1==88 ps 9
826 04:43:34.609725 TxDqDly_Margin_A1==88 ps 9
827 04:43:34.610136 TrainedVREFDQ_A0==74
828 04:43:34.614955 TrainedVREFDQ_A1==74
829 04:43:34.615430 VrefDac_Margin_A0==25
830 04:43:34.615833 DeviceVref_Margin_A0==40
831 04:43:34.620543 VrefDac_Margin_A1==25
832 04:43:34.620989 DeviceVref_Margin_A1==40
833 04:43:34.621371
834 04:43:34.621753
835 04:43:34.622135 channel==1
836 04:43:34.626119 RxClkDly_Margin_A0==98 ps 10
837 04:43:34.626536 TxDqDly_Margin_A0==88 ps 9
838 04:43:34.631714 RxClkDly_Margin_A1==88 ps 9
839 04:43:34.632160 TxDqDly_Margin_A1==88 ps 9
840 04:43:34.637364 TrainedVREFDQ_A0==77
841 04:43:34.637779 TrainedVREFDQ_A1==77
842 04:43:34.638163 VrefDac_Margin_A0==22
843 04:43:34.642931 DeviceVref_Margin_A0==37
844 04:43:34.643338 VrefDac_Margin_A1==24
845 04:43:34.648530 DeviceVref_Margin_A1==37
846 04:43:34.648931
847 04:43:34.649314 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 04:43:34.649690
849 04:43:34.682142 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 04:43:34.682593 2D training succeed
851 04:43:34.687723 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 04:43:34.693326 auto size-- 65535DDR cs0 size: 2048MB
853 04:43:34.693737 DDR cs1 size: 2048MB
854 04:43:34.698914 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 04:43:34.699323 cs0 DataBus test pass
856 04:43:34.704545 cs1 DataBus test pass
857 04:43:34.704955 cs0 AddrBus test pass
858 04:43:34.705336 cs1 AddrBus test pass
859 04:43:34.705713
860 04:43:34.710115 100bdlr_step_size ps== 420
861 04:43:34.710533 result report
862 04:43:34.715739 boot times 0Enable ddr reg access
863 04:43:34.720896 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 04:43:34.734393 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 04:43:35.307488 0.0;M3 CHK:0;cm4_sp_mode 0
866 04:43:35.308040 MVN_1=0x00000000
867 04:43:35.312945 MVN_2=0x00000000
868 04:43:35.318723 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 04:43:35.319155 OPS=0x10
870 04:43:35.319559 ring efuse init
871 04:43:35.319954 chipver efuse init
872 04:43:35.324317 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 04:43:35.329941 [0.018961 Inits done]
874 04:43:35.330364 secure task start!
875 04:43:35.330759 high task start!
876 04:43:35.334492 low task start!
877 04:43:35.334913 run into bl31
878 04:43:35.341147 NOTICE: BL31: v1.3(release):4fc40b1
879 04:43:35.348954 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 04:43:35.349384 NOTICE: BL31: G12A normal boot!
881 04:43:35.374332 NOTICE: BL31: BL33 decompress pass
882 04:43:35.380047 ERROR: Error initializing runtime service opteed_fast
883 04:43:36.612848
884 04:43:36.613308
885 04:43:36.621242 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 04:43:36.621673
887 04:43:36.622070 Model: Libre Computer AML-A311D-CC Alta
888 04:43:36.829683 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 04:43:36.853071 DRAM: 2 GiB (effective 3.8 GiB)
890 04:43:36.996084 Core: 408 devices, 31 uclasses, devicetree: separate
891 04:43:37.001925 WDT: Not starting watchdog@f0d0
892 04:43:37.034178 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 04:43:37.046640 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 04:43:37.051634 ** Bad device specification mmc 0 **
895 04:43:37.061970 Card did not respond to voltage select! : -110
896 04:43:37.069609 ** Bad device specification mmc 0 **
897 04:43:37.070077 Couldn't find partition mmc 0
898 04:43:37.077973 Card did not respond to voltage select! : -110
899 04:43:37.083486 ** Bad device specification mmc 0 **
900 04:43:37.083953 Couldn't find partition mmc 0
901 04:43:37.088562 Error: could not access storage.
902 04:43:37.430046 Net: eth0: ethernet@ff3f0000
903 04:43:37.430558 starting USB...
904 04:43:37.682810 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 04:43:37.683252 Starting the controller
906 04:43:37.689802 USB XHCI 1.10
907 04:43:39.243889 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 04:43:39.251452 scanning usb for storage devices... 0 Storage Device(s) found
910 04:43:39.302902 Hit any key to stop autoboot: 1
911 04:43:39.303657 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 04:43:39.304271 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 04:43:39.304745 Setting prompt string to ['=>']
914 04:43:39.305217 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 04:43:39.308834 0
916 04:43:39.309667 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 04:43:39.310146 Sending with 10 millisecond of delay
919 04:43:40.444504 => setenv autoload no
920 04:43:40.455143 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 04:43:40.460064 setenv autoload no
922 04:43:40.460780 Sending with 10 millisecond of delay
924 04:43:42.257173 => setenv initrd_high 0xffffffff
925 04:43:42.267881 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 04:43:42.268708 setenv initrd_high 0xffffffff
927 04:43:42.269402 Sending with 10 millisecond of delay
929 04:43:43.885170 => setenv fdt_high 0xffffffff
930 04:43:43.895802 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 04:43:43.896590 setenv fdt_high 0xffffffff
932 04:43:43.897287 Sending with 10 millisecond of delay
934 04:43:44.188986 => dhcp
935 04:43:44.199574 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 04:43:44.438269 dhcp
937 04:43:44.438726 Speed: 1000, full duplex
938 04:43:44.439133 BOOTP broadcast 1
939 04:43:44.487784 DHCP client bound to address 192.168.6.244 (260 ms)
940 04:43:44.488508 Sending with 10 millisecond of delay
942 04:43:46.164641 => setenv serverip 192.168.6.2
943 04:43:46.175377 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 04:43:46.176272 setenv serverip 192.168.6.2
945 04:43:46.176951 Sending with 10 millisecond of delay
947 04:43:49.899175 => tftpboot 0x01080000 851290/tftp-deploy-klvk4in7/kernel/uImage
948 04:43:49.909881 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
949 04:43:49.910678 tftpboot 0x01080000 851290/tftp-deploy-klvk4in7/kernel/uImage
950 04:43:49.911112 Speed: 1000, full duplex
951 04:43:49.911519 Using ethernet@ff3f0000 device
952 04:43:49.930455 TFTP from server 192.168.6.2; our IP address is 192.168.6.244
953 04:43:49.930922 Filename '851290/tftp-deploy-klvk4in7/kernel/uImage'.
954 04:43:49.931336 Load address: 0x1080000
955 04:44:44.976951 Loading: *T T T T T T T T T T
956 04:44:44.977573 Retry count exceeded; starting again
958 04:44:44.978968 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
961 04:44:44.980891 end: 2.4 uboot-commands (duration 00:01:38) [common]
963 04:44:44.982258 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
965 04:44:44.983232 end: 2 uboot-action (duration 00:01:38) [common]
967 04:44:44.984732 Cleaning after the job
968 04:44:44.985270 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/ramdisk
969 04:44:44.999642 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/kernel
970 04:44:45.023374 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/dtb
971 04:44:45.024539 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851290/tftp-deploy-klvk4in7/modules
972 04:44:45.045400 start: 4.1 power-off (timeout 00:00:30) [common]
973 04:44:45.046012 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
974 04:44:45.078541 >> OK - accepted request
975 04:44:45.080671 Returned 0 in 0 seconds
976 04:44:45.181609 end: 4.1 power-off (duration 00:00:00) [common]
978 04:44:45.182500 start: 4.2 read-feedback (timeout 00:10:00) [common]
979 04:44:45.183139 Listened to connection for namespace 'common' for up to 1s
980 04:44:46.184154 Finalising connection for namespace 'common'
981 04:44:46.184861 Disconnecting from shell: Finalise
982 04:44:46.185378 =>
983 04:44:46.286270 end: 4.2 read-feedback (duration 00:00:01) [common]
984 04:44:46.286842 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/851290
985 04:44:46.553374 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/851290
986 04:44:46.553979 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.