Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:03:28.739546 lava-dispatcher, installed at version: 2024.01
2 09:03:28.740344 start: 0 validate
3 09:03:28.740822 Start time: 2024-10-16 09:03:28.740792+00:00 (UTC)
4 09:03:28.741379 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:03:28.741906 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:03:28.781291 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:03:28.781864 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:03:28.811953 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:03:28.812639 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 09:03:29.861123 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:03:29.861620 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 09:03:29.895022 validate duration: 1.15
14 09:03:29.895901 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:03:29.896298 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:03:29.896618 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:03:29.897221 Not decompressing ramdisk as can be used compressed.
18 09:03:29.897651 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:03:29.897927 saving as /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/ramdisk/rootfs.cpio.gz
20 09:03:29.898202 total size: 8181887 (7 MB)
21 09:03:29.935034 progress 0 % (0 MB)
22 09:03:29.946792 progress 5 % (0 MB)
23 09:03:29.958022 progress 10 % (0 MB)
24 09:03:29.966683 progress 15 % (1 MB)
25 09:03:29.971995 progress 20 % (1 MB)
26 09:03:29.977665 progress 25 % (1 MB)
27 09:03:29.982820 progress 30 % (2 MB)
28 09:03:29.988458 progress 35 % (2 MB)
29 09:03:29.993634 progress 40 % (3 MB)
30 09:03:29.999236 progress 45 % (3 MB)
31 09:03:30.004398 progress 50 % (3 MB)
32 09:03:30.009975 progress 55 % (4 MB)
33 09:03:30.015164 progress 60 % (4 MB)
34 09:03:30.020754 progress 65 % (5 MB)
35 09:03:30.025978 progress 70 % (5 MB)
36 09:03:30.031552 progress 75 % (5 MB)
37 09:03:30.036799 progress 80 % (6 MB)
38 09:03:30.042405 progress 85 % (6 MB)
39 09:03:30.047567 progress 90 % (7 MB)
40 09:03:30.053283 progress 95 % (7 MB)
41 09:03:30.058018 progress 100 % (7 MB)
42 09:03:30.058686 7 MB downloaded in 0.16 s (48.63 MB/s)
43 09:03:30.059238 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:03:30.060249 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:03:30.060574 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:03:30.060861 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:03:30.061350 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/kernel/Image
49 09:03:30.061624 saving as /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/kernel/Image
50 09:03:30.061846 total size: 45713920 (43 MB)
51 09:03:30.062067 No compression specified
52 09:03:30.096484 progress 0 % (0 MB)
53 09:03:30.131504 progress 5 % (2 MB)
54 09:03:30.167123 progress 10 % (4 MB)
55 09:03:30.202833 progress 15 % (6 MB)
56 09:03:30.238309 progress 20 % (8 MB)
57 09:03:30.273427 progress 25 % (10 MB)
58 09:03:30.308041 progress 30 % (13 MB)
59 09:03:30.343038 progress 35 % (15 MB)
60 09:03:30.377961 progress 40 % (17 MB)
61 09:03:30.412644 progress 45 % (19 MB)
62 09:03:30.447964 progress 50 % (21 MB)
63 09:03:30.482609 progress 55 % (24 MB)
64 09:03:30.515805 progress 60 % (26 MB)
65 09:03:30.545473 progress 65 % (28 MB)
66 09:03:30.576888 progress 70 % (30 MB)
67 09:03:30.606251 progress 75 % (32 MB)
68 09:03:30.634852 progress 80 % (34 MB)
69 09:03:30.663417 progress 85 % (37 MB)
70 09:03:30.692049 progress 90 % (39 MB)
71 09:03:30.720653 progress 95 % (41 MB)
72 09:03:30.749045 progress 100 % (43 MB)
73 09:03:30.749603 43 MB downloaded in 0.69 s (63.39 MB/s)
74 09:03:30.750133 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:03:30.751021 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:03:30.751332 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:03:30.751631 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:03:30.752149 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 09:03:30.752459 saving as /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 09:03:30.752690 total size: 53209 (0 MB)
82 09:03:30.752918 No compression specified
83 09:03:30.789271 progress 61 % (0 MB)
84 09:03:30.790139 progress 100 % (0 MB)
85 09:03:30.790734 0 MB downloaded in 0.04 s (1.33 MB/s)
86 09:03:30.791237 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:03:30.792130 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:03:30.792432 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:03:30.792725 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:03:30.793240 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/modules.tar.xz
92 09:03:30.793513 saving as /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/modules/modules.tar
93 09:03:30.793734 total size: 11619040 (11 MB)
94 09:03:30.793959 Using unxz to decompress xz
95 09:03:30.827870 progress 0 % (0 MB)
96 09:03:30.889144 progress 5 % (0 MB)
97 09:03:30.967255 progress 10 % (1 MB)
98 09:03:31.055097 progress 15 % (1 MB)
99 09:03:31.147223 progress 20 % (2 MB)
100 09:03:31.230766 progress 25 % (2 MB)
101 09:03:31.309078 progress 30 % (3 MB)
102 09:03:31.392110 progress 35 % (3 MB)
103 09:03:31.468398 progress 40 % (4 MB)
104 09:03:31.546241 progress 45 % (5 MB)
105 09:03:31.628950 progress 50 % (5 MB)
106 09:03:31.712254 progress 55 % (6 MB)
107 09:03:31.791727 progress 60 % (6 MB)
108 09:03:31.867168 progress 65 % (7 MB)
109 09:03:31.947152 progress 70 % (7 MB)
110 09:03:32.021094 progress 75 % (8 MB)
111 09:03:32.098472 progress 80 % (8 MB)
112 09:03:32.183051 progress 85 % (9 MB)
113 09:03:32.267343 progress 90 % (10 MB)
114 09:03:32.343520 progress 95 % (10 MB)
115 09:03:32.423339 progress 100 % (11 MB)
116 09:03:32.436546 11 MB downloaded in 1.64 s (6.75 MB/s)
117 09:03:32.437168 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:03:32.438005 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:03:32.438283 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 09:03:32.438556 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 09:03:32.438808 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:03:32.439067 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 09:03:32.439691 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo
125 09:03:32.440398 makedir: /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin
126 09:03:32.441087 makedir: /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/tests
127 09:03:32.441716 makedir: /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/results
128 09:03:32.442342 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-add-keys
129 09:03:32.443293 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-add-sources
130 09:03:32.444286 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-background-process-start
131 09:03:32.445256 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-background-process-stop
132 09:03:32.446250 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-common-functions
133 09:03:32.447170 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-echo-ipv4
134 09:03:32.448119 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-install-packages
135 09:03:32.449095 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-installed-packages
136 09:03:32.450058 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-os-build
137 09:03:32.450984 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-probe-channel
138 09:03:32.451889 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-probe-ip
139 09:03:32.452863 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-target-ip
140 09:03:32.453843 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-target-mac
141 09:03:32.454767 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-target-storage
142 09:03:32.455685 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-test-case
143 09:03:32.456656 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-test-event
144 09:03:32.457560 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-test-feedback
145 09:03:32.458468 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-test-raise
146 09:03:32.459359 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-test-reference
147 09:03:32.460336 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-test-runner
148 09:03:32.461283 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-test-set
149 09:03:32.462195 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-test-shell
150 09:03:32.463107 Updating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-install-packages (oe)
151 09:03:32.464197 Updating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/bin/lava-installed-packages (oe)
152 09:03:32.465077 Creating /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/environment
153 09:03:32.465803 LAVA metadata
154 09:03:32.466293 - LAVA_JOB_ID=851277
155 09:03:32.466724 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:03:32.467387 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 09:03:32.469243 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:03:32.469860 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 09:03:32.470279 skipped lava-vland-overlay
160 09:03:32.470768 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:03:32.471275 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 09:03:32.471702 skipped lava-multinode-overlay
163 09:03:32.472236 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:03:32.472750 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 09:03:32.473238 Loading test definitions
166 09:03:32.473790 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 09:03:32.474238 Using /lava-851277 at stage 0
168 09:03:32.476504 uuid=851277_1.5.2.4.1 testdef=None
169 09:03:32.477092 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:03:32.477613 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 09:03:32.481125 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:03:32.482714 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 09:03:32.487153 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:03:32.488825 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 09:03:32.493086 runner path: /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/0/tests/0_dmesg test_uuid 851277_1.5.2.4.1
178 09:03:32.494120 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:03:32.495637 Creating lava-test-runner.conf files
181 09:03:32.496092 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/851277/lava-overlay-prnsizlo/lava-851277/0 for stage 0
182 09:03:32.496532 - 0_dmesg
183 09:03:32.496918 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:03:32.497231 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 09:03:32.521467 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:03:32.521887 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 09:03:32.522161 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:03:32.522437 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:03:32.522707 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 09:03:33.438601 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:03:33.439055 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 09:03:33.439304 extracting modules file /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/851277/extract-overlay-ramdisk-1k4vgert/ramdisk
193 09:03:34.774317 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 09:03:34.774797 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 09:03:34.775078 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851277/compress-overlay-rk9it_ui/overlay-1.5.2.5.tar.gz to ramdisk
196 09:03:34.775297 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851277/compress-overlay-rk9it_ui/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/851277/extract-overlay-ramdisk-1k4vgert/ramdisk
197 09:03:34.806077 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:03:34.806499 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 09:03:34.806775 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 09:03:34.807006 Converting downloaded kernel to a uImage
201 09:03:34.807318 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/kernel/Image /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/kernel/uImage
202 09:03:35.333671 output: Image Name:
203 09:03:35.334173 output: Created: Wed Oct 16 09:03:34 2024
204 09:03:35.334442 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:03:35.334700 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 09:03:35.334941 output: Load Address: 01080000
207 09:03:35.335186 output: Entry Point: 01080000
208 09:03:35.335430 output:
209 09:03:35.335840 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 09:03:35.336226 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 09:03:35.336570 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 09:03:35.336897 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:03:35.337232 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 09:03:35.337551 Building ramdisk /var/lib/lava/dispatcher/tmp/851277/extract-overlay-ramdisk-1k4vgert/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/851277/extract-overlay-ramdisk-1k4vgert/ramdisk
215 09:03:37.781777 >> 181555 blocks
216 09:03:47.411772 Adding RAMdisk u-boot header.
217 09:03:47.412349 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/851277/extract-overlay-ramdisk-1k4vgert/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/851277/extract-overlay-ramdisk-1k4vgert/ramdisk.cpio.gz.uboot
218 09:03:47.677626 output: Image Name:
219 09:03:47.678047 output: Created: Wed Oct 16 09:03:47 2024
220 09:03:47.678256 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:03:47.678462 output: Data Size: 26048902 Bytes = 25438.38 KiB = 24.84 MiB
222 09:03:47.678664 output: Load Address: 00000000
223 09:03:47.678862 output: Entry Point: 00000000
224 09:03:47.679059 output:
225 09:03:47.679637 rename /var/lib/lava/dispatcher/tmp/851277/extract-overlay-ramdisk-1k4vgert/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/ramdisk/ramdisk.cpio.gz.uboot
226 09:03:47.680124 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 09:03:47.680744 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 09:03:47.681325 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
229 09:03:47.681823 No LXC device requested
230 09:03:47.682368 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:03:47.682928 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
232 09:03:47.683471 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:03:47.683925 Checking files for TFTP limit of 4294967296 bytes.
234 09:03:47.686881 end: 1 tftp-deploy (duration 00:00:18) [common]
235 09:03:47.687502 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:03:47.688111 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:03:47.688666 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:03:47.689236 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:03:47.689812 Using kernel file from prepare-kernel: 851277/tftp-deploy-lg4iml8m/kernel/uImage
240 09:03:47.690473 substitutions:
241 09:03:47.690918 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:03:47.691361 - {DTB_ADDR}: 0x01070000
243 09:03:47.691797 - {DTB}: 851277/tftp-deploy-lg4iml8m/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 09:03:47.692269 - {INITRD}: 851277/tftp-deploy-lg4iml8m/ramdisk/ramdisk.cpio.gz.uboot
245 09:03:47.692709 - {KERNEL_ADDR}: 0x01080000
246 09:03:47.693142 - {KERNEL}: 851277/tftp-deploy-lg4iml8m/kernel/uImage
247 09:03:47.693578 - {LAVA_MAC}: None
248 09:03:47.694054 - {PRESEED_CONFIG}: None
249 09:03:47.694491 - {PRESEED_LOCAL}: None
250 09:03:47.694921 - {RAMDISK_ADDR}: 0x08000000
251 09:03:47.695349 - {RAMDISK}: 851277/tftp-deploy-lg4iml8m/ramdisk/ramdisk.cpio.gz.uboot
252 09:03:47.695787 - {ROOT_PART}: None
253 09:03:47.696255 - {ROOT}: None
254 09:03:47.696691 - {SERVER_IP}: 192.168.6.2
255 09:03:47.697125 - {TEE_ADDR}: 0x83000000
256 09:03:47.697556 - {TEE}: None
257 09:03:47.697985 Parsed boot commands:
258 09:03:47.698406 - setenv autoload no
259 09:03:47.698834 - setenv initrd_high 0xffffffff
260 09:03:47.699264 - setenv fdt_high 0xffffffff
261 09:03:47.699690 - dhcp
262 09:03:47.700146 - setenv serverip 192.168.6.2
263 09:03:47.700576 - tftpboot 0x01080000 851277/tftp-deploy-lg4iml8m/kernel/uImage
264 09:03:47.701004 - tftpboot 0x08000000 851277/tftp-deploy-lg4iml8m/ramdisk/ramdisk.cpio.gz.uboot
265 09:03:47.701432 - tftpboot 0x01070000 851277/tftp-deploy-lg4iml8m/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 09:03:47.701860 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:03:47.702295 - bootm 0x01080000 0x08000000 0x01070000
268 09:03:47.702830 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:03:47.704487 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:03:47.704972 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 09:03:47.720353 Setting prompt string to ['lava-test: # ']
273 09:03:47.721933 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:03:47.722576 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:03:47.723175 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:03:47.723762 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:03:47.725017 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 09:03:47.761859 >> OK - accepted request
279 09:03:47.764026 Returned 0 in 0 seconds
280 09:03:47.865214 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:03:47.866867 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:03:47.867471 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:03:47.868053 Setting prompt string to ['Hit any key to stop autoboot']
285 09:03:47.868542 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:03:47.870232 Trying 192.168.56.21...
287 09:03:47.870759 Connected to conserv1.
288 09:03:47.871206 Escape character is '^]'.
289 09:03:47.871644
290 09:03:47.872130 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 09:03:47.872599
292 09:03:54.881379 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 09:03:54.882067 bl2_stage_init 0x01
294 09:03:54.882553 bl2_stage_init 0x81
295 09:03:54.892526 hw id: 0x0000 - pwm id 0x01
296 09:03:54.893103 bl2_stage_init 0xc1
297 09:03:54.893566 bl2_stage_init 0x02
298 09:03:54.894018
299 09:03:54.894466 L0:00000000
300 09:03:54.894914 L1:00000703
301 09:03:54.895344 L2:00008067
302 09:03:54.895769 L3:15000000
303 09:03:54.897997 S1:00000000
304 09:03:54.898517 B2:20282000
305 09:03:54.898959 B1:a0f83180
306 09:03:54.899393
307 09:03:54.899825 TE: 69891
308 09:03:54.900295
309 09:03:54.909197 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 09:03:54.909768
311 09:03:54.910217 Board ID = 1
312 09:03:54.910654 Set cpu clk to 24M
313 09:03:54.911083 Set clk81 to 24M
314 09:03:54.912587 Use GP1_pll as DSU clk.
315 09:03:54.913067 DSU clk: 1200 Mhz
316 09:03:54.917940 CPU clk: 1200 MHz
317 09:03:54.918474 Set clk81 to 166.6M
318 09:03:54.923614 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 09:03:54.924171 board id: 1
320 09:03:54.933291 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:03:54.943928 fw parse done
322 09:03:54.949910 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:03:54.992446 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:03:55.003340 PIEI prepare done
325 09:03:55.003882 fastboot data load
326 09:03:55.004400 fastboot data verify
327 09:03:55.008936 verify result: 266
328 09:03:55.014503 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 09:03:55.015027 LPDDR4 probe
330 09:03:55.015468 ddr clk to 1584MHz
331 09:03:55.022507 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:03:55.059945
333 09:03:55.060609 dmc_version 0001
334 09:03:55.066491 Check phy result
335 09:03:55.072353 INFO : End of CA training
336 09:03:55.072899 INFO : End of initialization
337 09:03:55.077929 INFO : Training has run successfully!
338 09:03:55.078452 Check phy result
339 09:03:55.083600 INFO : End of initialization
340 09:03:55.084160 INFO : End of read enable training
341 09:03:55.086900 INFO : End of fine write leveling
342 09:03:55.092543 INFO : End of Write leveling coarse delay
343 09:03:55.098130 INFO : Training has run successfully!
344 09:03:55.098670 Check phy result
345 09:03:55.099127 INFO : End of initialization
346 09:03:55.103730 INFO : End of read dq deskew training
347 09:03:55.109307 INFO : End of MPR read delay center optimization
348 09:03:55.109841 INFO : End of write delay center optimization
349 09:03:55.114888 INFO : End of read delay center optimization
350 09:03:55.120621 INFO : End of max read latency training
351 09:03:55.121157 INFO : Training has run successfully!
352 09:03:55.126123 1D training succeed
353 09:03:55.132017 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:03:55.179619 Check phy result
355 09:03:55.180283 INFO : End of initialization
356 09:03:55.202041 INFO : End of 2D read delay Voltage center optimization
357 09:03:55.221148 INFO : End of 2D read delay Voltage center optimization
358 09:03:55.273323 INFO : End of 2D write delay Voltage center optimization
359 09:03:55.322316 INFO : End of 2D write delay Voltage center optimization
360 09:03:55.327824 INFO : Training has run successfully!
361 09:03:55.328404
362 09:03:55.328864 channel==0
363 09:03:55.334981 RxClkDly_Margin_A0==78 ps 8
364 09:03:55.335525 TxDqDly_Margin_A0==88 ps 9
365 09:03:55.336638 RxClkDly_Margin_A1==88 ps 9
366 09:03:55.337115 TxDqDly_Margin_A1==98 ps 10
367 09:03:55.342088 TrainedVREFDQ_A0==74
368 09:03:55.342611 TrainedVREFDQ_A1==75
369 09:03:55.343108 VrefDac_Margin_A0==23
370 09:03:55.353637 DeviceVref_Margin_A0==40
371 09:03:55.354277 VrefDac_Margin_A1==23
372 09:03:55.354751 DeviceVref_Margin_A1==39
373 09:03:55.355237
374 09:03:55.355732
375 09:03:55.356233 channel==1
376 09:03:55.356666 RxClkDly_Margin_A0==78 ps 8
377 09:03:55.357418 TxDqDly_Margin_A0==98 ps 10
378 09:03:55.362379 RxClkDly_Margin_A1==78 ps 8
379 09:03:55.362897 TxDqDly_Margin_A1==88 ps 9
380 09:03:55.363340 TrainedVREFDQ_A0==78
381 09:03:55.368794 TrainedVREFDQ_A1==75
382 09:03:55.369309 VrefDac_Margin_A0==23
383 09:03:55.369741 DeviceVref_Margin_A0==36
384 09:03:55.374224 VrefDac_Margin_A1==20
385 09:03:55.374736 DeviceVref_Margin_A1==39
386 09:03:55.375173
387 09:03:55.379795 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:03:55.380342
389 09:03:55.419291 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000019 00000018 00000019 00000015 00000018 00000014 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000015 00000017 dram_vref_reg_value 0x 00000061
390 09:03:55.419967 2D training succeed
391 09:03:55.420498 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:03:55.424570 auto size-- 65535DDR cs0 size: 2048MB
393 09:03:55.425054 DDR cs1 size: 2048MB
394 09:03:55.430111 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:03:55.430622 cs0 DataBus test pass
396 09:03:55.431060 cs1 DataBus test pass
397 09:03:55.435728 cs0 AddrBus test pass
398 09:03:55.436269 cs1 AddrBus test pass
399 09:03:55.436705
400 09:03:55.437172 100bdlr_step_size ps== 478
401 09:03:55.441355 result report
402 09:03:55.441832 boot times 0Enable ddr reg access
403 09:03:55.450436 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:03:55.464281 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 09:03:56.119670 bl2z: ptr: 05129330, size: 00001e40
406 09:03:56.125166 0.0;M3 CHK:0;cm4_sp_mode 0
407 09:03:56.125584 MVN_1=0x00000000
408 09:03:56.125837 MVN_2=0x00000000
409 09:03:56.136839 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 09:03:56.137285 OPS=0x04
411 09:03:56.137528 ring efuse init
412 09:03:56.142289 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 09:03:56.142694 [0.017319 Inits done]
414 09:03:56.142949 secure task start!
415 09:03:56.149102 high task start!
416 09:03:56.149511 low task start!
417 09:03:56.149720 run into bl31
418 09:03:56.157616 NOTICE: BL31: v1.3(release):4fc40b1
419 09:03:56.165304 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 09:03:56.165645 NOTICE: BL31: G12A normal boot!
421 09:03:56.180995 NOTICE: BL31: BL33 decompress pass
422 09:03:56.186624 ERROR: Error initializing runtime service opteed_fast
423 09:03:58.879977 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 09:03:58.880643 bl2_stage_init 0x01
425 09:03:58.881079 bl2_stage_init 0x81
426 09:03:58.885552 hw id: 0x0000 - pwm id 0x01
427 09:03:58.886043 bl2_stage_init 0xc1
428 09:03:58.891297 bl2_stage_init 0x02
429 09:03:58.891805
430 09:03:58.892182 L0:00000000
431 09:03:58.892385 L1:00000703
432 09:03:58.892582 L2:00008067
433 09:03:58.892777 L3:15000000
434 09:03:58.896795 S1:00000000
435 09:03:58.897278 B2:20282000
436 09:03:58.897692 B1:a0f83180
437 09:03:58.898095
438 09:03:58.898498 TE: 69060
439 09:03:58.898898
440 09:03:58.902364 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 09:03:58.902833
442 09:03:58.907923 Board ID = 1
443 09:03:58.908415 Set cpu clk to 24M
444 09:03:58.908840 Set clk81 to 24M
445 09:03:58.913568 Use GP1_pll as DSU clk.
446 09:03:58.914074 DSU clk: 1200 Mhz
447 09:03:58.914464 CPU clk: 1200 MHz
448 09:03:58.919253 Set clk81 to 166.6M
449 09:03:58.924730 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 09:03:58.925187 board id: 1
451 09:03:58.931929 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 09:03:58.942575 fw parse done
453 09:03:58.948520 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 09:03:58.991329 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 09:03:59.002250 PIEI prepare done
456 09:03:59.002745 fastboot data load
457 09:03:59.003147 fastboot data verify
458 09:03:59.007799 verify result: 266
459 09:03:59.013456 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 09:03:59.013919 LPDDR4 probe
461 09:03:59.014308 ddr clk to 1584MHz
462 09:03:59.021476 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 09:03:59.058755
464 09:03:59.059305 dmc_version 0001
465 09:03:59.065381 Check phy result
466 09:03:59.071277 INFO : End of CA training
467 09:03:59.071741 INFO : End of initialization
468 09:03:59.076854 INFO : Training has run successfully!
469 09:03:59.077324 Check phy result
470 09:03:59.082467 INFO : End of initialization
471 09:03:59.082933 INFO : End of read enable training
472 09:03:59.088076 INFO : End of fine write leveling
473 09:03:59.093645 INFO : End of Write leveling coarse delay
474 09:03:59.094109 INFO : Training has run successfully!
475 09:03:59.094514 Check phy result
476 09:03:59.099234 INFO : End of initialization
477 09:03:59.099694 INFO : End of read dq deskew training
478 09:03:59.104847 INFO : End of MPR read delay center optimization
479 09:03:59.110442 INFO : End of write delay center optimization
480 09:03:59.116042 INFO : End of read delay center optimization
481 09:03:59.116502 INFO : End of max read latency training
482 09:03:59.121646 INFO : Training has run successfully!
483 09:03:59.122105 1D training succeed
484 09:03:59.130809 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 09:03:59.178545 Check phy result
486 09:03:59.179044 INFO : End of initialization
487 09:03:59.200787 INFO : End of 2D read delay Voltage center optimization
488 09:03:59.219939 INFO : End of 2D read delay Voltage center optimization
489 09:03:59.271802 INFO : End of 2D write delay Voltage center optimization
490 09:03:59.320961 INFO : End of 2D write delay Voltage center optimization
491 09:03:59.326633 INFO : Training has run successfully!
492 09:03:59.327262
493 09:03:59.327599 channel==0
494 09:03:59.332311 RxClkDly_Margin_A0==78 ps 8
495 09:03:59.332925 TxDqDly_Margin_A0==98 ps 10
496 09:03:59.337785 RxClkDly_Margin_A1==69 ps 7
497 09:03:59.338242 TxDqDly_Margin_A1==88 ps 9
498 09:03:59.338644 TrainedVREFDQ_A0==74
499 09:03:59.343470 TrainedVREFDQ_A1==74
500 09:03:59.343916 VrefDac_Margin_A0==23
501 09:03:59.344368 DeviceVref_Margin_A0==40
502 09:03:59.349029 VrefDac_Margin_A1==23
503 09:03:59.349539 DeviceVref_Margin_A1==40
504 09:03:59.349958
505 09:03:59.350407
506 09:03:59.350858 channel==1
507 09:03:59.354629 RxClkDly_Margin_A0==78 ps 8
508 09:03:59.355199 TxDqDly_Margin_A0==88 ps 9
509 09:03:59.360243 RxClkDly_Margin_A1==88 ps 9
510 09:03:59.360780 TxDqDly_Margin_A1==88 ps 9
511 09:03:59.365785 TrainedVREFDQ_A0==76
512 09:03:59.366338 TrainedVREFDQ_A1==77
513 09:03:59.366756 VrefDac_Margin_A0==22
514 09:03:59.371344 DeviceVref_Margin_A0==38
515 09:03:59.371816 VrefDac_Margin_A1==22
516 09:03:59.372267 DeviceVref_Margin_A1==37
517 09:03:59.376942
518 09:03:59.377428 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 09:03:59.377834
520 09:03:59.410476 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000063
521 09:03:59.410845 2D training succeed
522 09:03:59.421760 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 09:03:59.422082 auto size-- 65535DDR cs0 size: 2048MB
524 09:03:59.422295 DDR cs1 size: 2048MB
525 09:03:59.427380 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 09:03:59.427658 cs0 DataBus test pass
527 09:03:59.432884 cs1 DataBus test pass
528 09:03:59.433171 cs0 AddrBus test pass
529 09:03:59.433381 cs1 AddrBus test pass
530 09:03:59.433583
531 09:03:59.438427 100bdlr_step_size ps== 478
532 09:03:59.438709 result report
533 09:03:59.444059 boot times 0Enable ddr reg access
534 09:03:59.458474 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 09:03:59.462977 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 09:04:00.119364 bl2z: ptr: 05129330, size: 00001e40
537 09:04:00.127230 0.0;M3 CHK:0;cm4_sp_mode 0
538 09:04:00.127572 MVN_1=0x00000000
539 09:04:00.127822 MVN_2=0x00000000
540 09:04:00.138785 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 09:04:00.139163 OPS=0x04
542 09:04:00.139416 ring efuse init
543 09:04:00.141686 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 09:04:00.147835 [0.017319 Inits done]
545 09:04:00.148475 secure task start!
546 09:04:00.148927 high task start!
547 09:04:00.149334 low task start!
548 09:04:00.152134 run into bl31
549 09:04:00.160757 NOTICE: BL31: v1.3(release):4fc40b1
550 09:04:00.168562 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 09:04:00.169024 NOTICE: BL31: G12A normal boot!
552 09:04:00.184112 NOTICE: BL31: BL33 decompress pass
553 09:04:00.189702 ERROR: Error initializing runtime service opteed_fast
554 09:04:01.582065 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 09:04:01.582672 bl2_stage_init 0x01
556 09:04:01.583104 bl2_stage_init 0x81
557 09:04:01.587549 hw id: 0x0000 - pwm id 0x01
558 09:04:01.588045 bl2_stage_init 0xc1
559 09:04:01.593117 bl2_stage_init 0x02
560 09:04:01.593565
561 09:04:01.593980 L0:00000000
562 09:04:01.594386 L1:00000703
563 09:04:01.594785 L2:00008067
564 09:04:01.595181 L3:15000000
565 09:04:01.598736 S1:00000000
566 09:04:01.599177 B2:20282000
567 09:04:01.599581 B1:a0f83180
568 09:04:01.600004
569 09:04:01.600724 TE: 69916
570 09:04:01.601213
571 09:04:01.604430 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 09:04:01.604966
573 09:04:01.610030 Board ID = 1
574 09:04:01.610558 Set cpu clk to 24M
575 09:04:01.611025 Set clk81 to 24M
576 09:04:01.621458 Use GP1_pll as DSU clk.
577 09:04:01.622010 DSU clk: 1200 Mhz
578 09:04:01.622478 CPU clk: 1200 MHz
579 09:04:01.622924 Set clk81 to 166.6M
580 09:04:01.626831 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 09:04:01.627371 board id: 1
582 09:04:01.634023 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 09:04:01.644905 fw parse done
584 09:04:01.650864 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 09:04:01.693952 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 09:04:01.705171 PIEI prepare done
587 09:04:01.705706 fastboot data load
588 09:04:01.706181 fastboot data verify
589 09:04:01.710796 verify result: 266
590 09:04:01.716304 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 09:04:01.716840 LPDDR4 probe
592 09:04:01.717296 ddr clk to 1584MHz
593 09:04:01.724324 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 09:04:01.769189
595 09:04:01.769767 dmc_version 0001
596 09:04:01.770234 Check phy result
597 09:04:01.775045 INFO : End of CA training
598 09:04:01.775580 INFO : End of initialization
599 09:04:01.780639 INFO : Training has run successfully!
600 09:04:01.781174 Check phy result
601 09:04:01.786232 INFO : End of initialization
602 09:04:01.786766 INFO : End of read enable training
603 09:04:01.789561 INFO : End of fine write leveling
604 09:04:01.795099 INFO : End of Write leveling coarse delay
605 09:04:01.800817 INFO : Training has run successfully!
606 09:04:01.801349 Check phy result
607 09:04:01.801813 INFO : End of initialization
608 09:04:01.806324 INFO : End of read dq deskew training
609 09:04:01.811910 INFO : End of MPR read delay center optimization
610 09:04:01.812477 INFO : End of write delay center optimization
611 09:04:01.817467 INFO : End of read delay center optimization
612 09:04:01.823136 INFO : End of max read latency training
613 09:04:01.823667 INFO : Training has run successfully!
614 09:04:01.828831 1D training succeed
615 09:04:01.834693 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 09:04:01.882978 Check phy result
617 09:04:01.883521 INFO : End of initialization
618 09:04:01.910384 INFO : End of 2D read delay Voltage center optimization
619 09:04:01.934603 INFO : End of 2D read delay Voltage center optimization
620 09:04:01.991261 INFO : End of 2D write delay Voltage center optimization
621 09:04:02.045343 INFO : End of 2D write delay Voltage center optimization
622 09:04:02.050959 INFO : Training has run successfully!
623 09:04:02.051493
624 09:04:02.051965 channel==0
625 09:04:02.056413 RxClkDly_Margin_A0==88 ps 9
626 09:04:02.056943 TxDqDly_Margin_A0==98 ps 10
627 09:04:02.059794 RxClkDly_Margin_A1==88 ps 9
628 09:04:02.060359 TxDqDly_Margin_A1==88 ps 9
629 09:04:02.065350 TrainedVREFDQ_A0==75
630 09:04:02.065957 TrainedVREFDQ_A1==74
631 09:04:02.066448 VrefDac_Margin_A0==24
632 09:04:02.070948 DeviceVref_Margin_A0==39
633 09:04:02.071493 VrefDac_Margin_A1==23
634 09:04:02.082326 DeviceVref_Margin_A1==40
635 09:04:02.082888
636 09:04:02.083360
637 09:04:02.083816 channel==1
638 09:04:02.084310 RxClkDly_Margin_A0==78 ps 8
639 09:04:02.084774 TxDqDly_Margin_A0==98 ps 10
640 09:04:02.085227 RxClkDly_Margin_A1==88 ps 9
641 09:04:02.087740 TxDqDly_Margin_A1==88 ps 9
642 09:04:02.088319 TrainedVREFDQ_A0==78
643 09:04:02.088786 TrainedVREFDQ_A1==77
644 09:04:02.093360 VrefDac_Margin_A0==22
645 09:04:02.093902 DeviceVref_Margin_A0==36
646 09:04:02.098949 VrefDac_Margin_A1==23
647 09:04:02.099486 DeviceVref_Margin_A1==37
648 09:04:02.099949
649 09:04:02.104588 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 09:04:02.105130
651 09:04:02.132445 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 09:04:02.137975 2D training succeed
653 09:04:02.143636 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 09:04:02.144201 auto size-- 65535DDR cs0 size: 2048MB
655 09:04:02.149259 DDR cs1 size: 2048MB
656 09:04:02.149790 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 09:04:02.154859 cs0 DataBus test pass
658 09:04:02.155390 cs1 DataBus test pass
659 09:04:02.155845 cs0 AddrBus test pass
660 09:04:02.160389 cs1 AddrBus test pass
661 09:04:02.160919
662 09:04:02.161380 100bdlr_step_size ps== 478
663 09:04:02.161842 result report
664 09:04:02.166022 boot times 0Enable ddr reg access
665 09:04:02.183012 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 09:04:02.187432 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 09:04:02.846738 bl2z: ptr: 05129330, size: 00001e40
668 09:04:02.855298 0.0;M3 CHK:0;cm4_sp_mode 0
669 09:04:02.855872 MVN_1=0x00000000
670 09:04:02.856398 MVN_2=0x00000000
671 09:04:02.866962 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 09:04:02.867539 OPS=0x04
673 09:04:02.868041 ring efuse init
674 09:04:02.872518 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 09:04:02.873080 [0.017354 Inits done]
676 09:04:02.873542 secure task start!
677 09:04:02.880140 high task start!
678 09:04:02.880695 low task start!
679 09:04:02.881153 run into bl31
680 09:04:02.888748 NOTICE: BL31: v1.3(release):4fc40b1
681 09:04:02.896533 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 09:04:02.897100 NOTICE: BL31: G12A normal boot!
683 09:04:02.912144 NOTICE: BL31: BL33 decompress pass
684 09:04:02.917756 ERROR: Error initializing runtime service opteed_fast
685 09:04:03.713168
686 09:04:03.713821
687 09:04:03.718558 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 09:04:03.719124
689 09:04:03.722196 Model: Libre Computer AML-S905D3-CC Solitude
690 09:04:03.869072 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 09:04:03.884492 DRAM: 2 GiB (effective 3.8 GiB)
692 09:04:03.985446 Core: 406 devices, 33 uclasses, devicetree: separate
693 09:04:03.991293 WDT: Not starting watchdog@f0d0
694 09:04:04.016348 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 09:04:04.028550 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 09:04:04.033649 ** Bad device specification mmc 0 **
697 09:04:04.043687 Card did not respond to voltage select! : -110
698 09:04:04.051278 ** Bad device specification mmc 0 **
699 09:04:04.051836 Couldn't find partition mmc 0
700 09:04:04.059635 Card did not respond to voltage select! : -110
701 09:04:04.065124 ** Bad device specification mmc 0 **
702 09:04:04.065673 Couldn't find partition mmc 0
703 09:04:04.070214 Error: could not access storage.
704 09:04:04.365828 Net: eth0: ethernet@ff3f0000
705 09:04:04.366477 starting USB...
706 09:04:04.611341 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 09:04:04.612037 Starting the controller
708 09:04:04.618323 USB XHCI 1.10
709 09:04:06.172103 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 09:04:06.180445 scanning usb for storage devices... 0 Storage Device(s) found
712 09:04:06.231518 Hit any key to stop autoboot: 1
713 09:04:06.232332 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
714 09:04:06.232818 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 09:04:06.233090 Setting prompt string to ['=>']
716 09:04:06.233365 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 09:04:06.246496 0
718 09:04:06.247163 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 09:04:06.348112 => setenv autoload no
721 09:04:06.348962 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 09:04:06.354638 setenv autoload no
724 09:04:06.456381 => setenv initrd_high 0xffffffff
725 09:04:06.457232 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 09:04:06.461715 setenv initrd_high 0xffffffff
728 09:04:06.563430 => setenv fdt_high 0xffffffff
729 09:04:06.564271 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 09:04:06.568646 setenv fdt_high 0xffffffff
732 09:04:06.670310 => dhcp
733 09:04:06.671134 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 09:04:06.675384 dhcp
735 09:04:07.230987 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 09:04:07.231665 Speed: 1000, full duplex
737 09:04:07.232216 BOOTP broadcast 1
738 09:04:07.478963 BOOTP broadcast 2
739 09:04:07.522004 DHCP client bound to address 192.168.6.19 (291 ms)
741 09:04:07.623259 => setenv serverip 192.168.6.2
742 09:04:07.623916 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
743 09:04:07.628275 setenv serverip 192.168.6.2
745 09:04:07.729318 => tftpboot 0x01080000 851277/tftp-deploy-lg4iml8m/kernel/uImage
746 09:04:07.730006 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
747 09:04:07.736656 tftpboot 0x01080000 851277/tftp-deploy-lg4iml8m/kernel/uImage
748 09:04:07.736955 Speed: 1000, full duplex
749 09:04:07.737171 Using ethernet@ff3f0000 device
750 09:04:07.747825 TFTP from server 192.168.6.2; our IP address is 192.168.6.19
751 09:04:07.748342 Filename '851277/tftp-deploy-lg4iml8m/kernel/uImage'.
752 09:04:07.751669 Load address: 0x1080000
753 09:05:02.852357 Loading: *T T T T T T T T T T #
754 09:05:02.852993 Retry count exceeded; starting again
756 09:05:02.854564 end: 2.4.3 bootloader-commands (duration 00:00:57) [common]
759 09:05:02.856501 end: 2.4 uboot-commands (duration 00:01:15) [common]
761 09:05:02.857906 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
763 09:05:02.858963 end: 2 uboot-action (duration 00:01:15) [common]
765 09:05:02.860593 Cleaning after the job
766 09:05:02.861170 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/ramdisk
767 09:05:02.876033 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/kernel
768 09:05:02.900598 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/dtb
769 09:05:02.902004 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851277/tftp-deploy-lg4iml8m/modules
770 09:05:02.924549 start: 4.1 power-off (timeout 00:00:30) [common]
771 09:05:02.925217 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
772 09:05:02.959131 >> OK - accepted request
773 09:05:02.961230 Returned 0 in 0 seconds
774 09:05:03.062205 end: 4.1 power-off (duration 00:00:00) [common]
776 09:05:03.063161 start: 4.2 read-feedback (timeout 00:10:00) [common]
777 09:05:03.063828 Listened to connection for namespace 'common' for up to 1s
778 09:05:04.063892 Finalising connection for namespace 'common'
779 09:05:04.064659 Disconnecting from shell: Finalise
780 09:05:04.065177 =>
781 09:05:04.166168 end: 4.2 read-feedback (duration 00:00:01) [common]
782 09:05:04.166842 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/851277
783 09:05:04.451423 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/851277
784 09:05:04.452052 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.