Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:22:51.358671 lava-dispatcher, installed at version: 2024.01
2 05:22:51.359427 start: 0 validate
3 05:22:51.359919 Start time: 2024-10-17 05:22:51.359890+00:00 (UTC)
4 05:22:51.360501 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:22:51.361039 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:22:51.403559 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:22:51.404148 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:22:51.431865 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:22:51.432499 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:22:51.461438 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:22:51.461914 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:22:51.495190 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:22:51.495924 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 05:22:51.533698 validate duration: 0.17
16 05:22:51.534546 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:22:51.534888 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:22:51.535218 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:22:51.535804 Not decompressing ramdisk as can be used compressed.
20 05:22:51.536272 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 05:22:51.536566 saving as /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/ramdisk/initrd.cpio.gz
22 05:22:51.536850 total size: 5628182 (5 MB)
23 05:22:51.573522 progress 0 % (0 MB)
24 05:22:51.580915 progress 5 % (0 MB)
25 05:22:51.589201 progress 10 % (0 MB)
26 05:22:51.596388 progress 15 % (0 MB)
27 05:22:51.602400 progress 20 % (1 MB)
28 05:22:51.606073 progress 25 % (1 MB)
29 05:22:51.610145 progress 30 % (1 MB)
30 05:22:51.614317 progress 35 % (1 MB)
31 05:22:51.618066 progress 40 % (2 MB)
32 05:22:51.622128 progress 45 % (2 MB)
33 05:22:51.625869 progress 50 % (2 MB)
34 05:22:51.629997 progress 55 % (2 MB)
35 05:22:51.634131 progress 60 % (3 MB)
36 05:22:51.637874 progress 65 % (3 MB)
37 05:22:51.642082 progress 70 % (3 MB)
38 05:22:51.645999 progress 75 % (4 MB)
39 05:22:51.650158 progress 80 % (4 MB)
40 05:22:51.653782 progress 85 % (4 MB)
41 05:22:51.657863 progress 90 % (4 MB)
42 05:22:51.661855 progress 95 % (5 MB)
43 05:22:51.665205 progress 100 % (5 MB)
44 05:22:51.665863 5 MB downloaded in 0.13 s (41.61 MB/s)
45 05:22:51.666435 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:22:51.667385 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:22:51.667715 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:22:51.668043 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:22:51.668543 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/kernel/Image
51 05:22:51.668839 saving as /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/kernel/Image
52 05:22:51.669067 total size: 45713920 (43 MB)
53 05:22:51.669293 No compression specified
54 05:22:51.705985 progress 0 % (0 MB)
55 05:22:51.733348 progress 5 % (2 MB)
56 05:22:51.761172 progress 10 % (4 MB)
57 05:22:51.789124 progress 15 % (6 MB)
58 05:22:51.816902 progress 20 % (8 MB)
59 05:22:51.844734 progress 25 % (10 MB)
60 05:22:51.872549 progress 30 % (13 MB)
61 05:22:51.900281 progress 35 % (15 MB)
62 05:22:51.928079 progress 40 % (17 MB)
63 05:22:51.955307 progress 45 % (19 MB)
64 05:22:51.982963 progress 50 % (21 MB)
65 05:22:52.010438 progress 55 % (24 MB)
66 05:22:52.038336 progress 60 % (26 MB)
67 05:22:52.065490 progress 65 % (28 MB)
68 05:22:52.093290 progress 70 % (30 MB)
69 05:22:52.121414 progress 75 % (32 MB)
70 05:22:52.149125 progress 80 % (34 MB)
71 05:22:52.176433 progress 85 % (37 MB)
72 05:22:52.204176 progress 90 % (39 MB)
73 05:22:52.232137 progress 95 % (41 MB)
74 05:22:52.259312 progress 100 % (43 MB)
75 05:22:52.259836 43 MB downloaded in 0.59 s (73.80 MB/s)
76 05:22:52.260374 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:22:52.261249 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:22:52.261556 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:22:52.261854 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:22:52.262342 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:22:52.262605 saving as /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:22:52.262828 total size: 54703 (0 MB)
84 05:22:52.263050 No compression specified
85 05:22:52.302455 progress 59 % (0 MB)
86 05:22:52.303306 progress 100 % (0 MB)
87 05:22:52.303890 0 MB downloaded in 0.04 s (1.27 MB/s)
88 05:22:52.304421 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:22:52.305290 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:22:52.305581 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:22:52.305870 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:22:52.306328 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 05:22:52.306586 saving as /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/nfsrootfs/full.rootfs.tar
95 05:22:52.306809 total size: 107552908 (102 MB)
96 05:22:52.307032 Using unxz to decompress xz
97 05:22:52.342958 progress 0 % (0 MB)
98 05:22:52.974072 progress 5 % (5 MB)
99 05:22:53.691014 progress 10 % (10 MB)
100 05:22:54.406241 progress 15 % (15 MB)
101 05:22:55.152931 progress 20 % (20 MB)
102 05:22:55.719915 progress 25 % (25 MB)
103 05:22:56.339458 progress 30 % (30 MB)
104 05:22:57.161517 progress 35 % (35 MB)
105 05:22:57.535923 progress 40 % (41 MB)
106 05:22:57.965113 progress 45 % (46 MB)
107 05:22:58.642450 progress 50 % (51 MB)
108 05:22:59.311753 progress 55 % (56 MB)
109 05:23:00.066081 progress 60 % (61 MB)
110 05:23:00.812861 progress 65 % (66 MB)
111 05:23:01.538093 progress 70 % (71 MB)
112 05:23:02.298033 progress 75 % (76 MB)
113 05:23:02.970035 progress 80 % (82 MB)
114 05:23:03.670358 progress 85 % (87 MB)
115 05:23:04.391029 progress 90 % (92 MB)
116 05:23:05.098169 progress 95 % (97 MB)
117 05:23:05.838821 progress 100 % (102 MB)
118 05:23:05.850539 102 MB downloaded in 13.54 s (7.57 MB/s)
119 05:23:05.851294 end: 1.4.1 http-download (duration 00:00:14) [common]
121 05:23:05.853193 end: 1.4 download-retry (duration 00:00:14) [common]
122 05:23:05.853780 start: 1.5 download-retry (timeout 00:09:46) [common]
123 05:23:05.854356 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 05:23:05.855543 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/modules.tar.xz
125 05:23:05.856115 saving as /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/modules/modules.tar
126 05:23:05.856580 total size: 11619040 (11 MB)
127 05:23:05.857048 Using unxz to decompress xz
128 05:23:05.902189 progress 0 % (0 MB)
129 05:23:05.963700 progress 5 % (0 MB)
130 05:23:06.041056 progress 10 % (1 MB)
131 05:23:06.126048 progress 15 % (1 MB)
132 05:23:06.217920 progress 20 % (2 MB)
133 05:23:06.301336 progress 25 % (2 MB)
134 05:23:06.378367 progress 30 % (3 MB)
135 05:23:06.459704 progress 35 % (3 MB)
136 05:23:06.534700 progress 40 % (4 MB)
137 05:23:06.610914 progress 45 % (5 MB)
138 05:23:06.694799 progress 50 % (5 MB)
139 05:23:06.778159 progress 55 % (6 MB)
140 05:23:06.856112 progress 60 % (6 MB)
141 05:23:06.930287 progress 65 % (7 MB)
142 05:23:07.008959 progress 70 % (7 MB)
143 05:23:07.082301 progress 75 % (8 MB)
144 05:23:07.157670 progress 80 % (8 MB)
145 05:23:07.240364 progress 85 % (9 MB)
146 05:23:07.322941 progress 90 % (10 MB)
147 05:23:07.397450 progress 95 % (10 MB)
148 05:23:07.475564 progress 100 % (11 MB)
149 05:23:07.488338 11 MB downloaded in 1.63 s (6.79 MB/s)
150 05:23:07.489072 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:23:07.490749 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:23:07.491298 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 05:23:07.491839 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 05:23:17.005038 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/851274/extract-nfsrootfs-25bnig8v
156 05:23:17.005650 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 05:23:17.005946 start: 1.6.2 lava-overlay (timeout 00:09:35) [common]
158 05:23:17.006564 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7
159 05:23:17.007006 makedir: /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin
160 05:23:17.007339 makedir: /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/tests
161 05:23:17.007662 makedir: /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/results
162 05:23:17.008043 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-add-keys
163 05:23:17.008590 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-add-sources
164 05:23:17.009103 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-background-process-start
165 05:23:17.009635 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-background-process-stop
166 05:23:17.010169 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-common-functions
167 05:23:17.010675 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-echo-ipv4
168 05:23:17.011186 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-install-packages
169 05:23:17.011708 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-installed-packages
170 05:23:17.012239 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-os-build
171 05:23:17.012738 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-probe-channel
172 05:23:17.013224 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-probe-ip
173 05:23:17.013704 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-target-ip
174 05:23:17.014185 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-target-mac
175 05:23:17.014665 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-target-storage
176 05:23:17.015182 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-test-case
177 05:23:17.015697 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-test-event
178 05:23:17.016208 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-test-feedback
179 05:23:17.016701 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-test-raise
180 05:23:17.017189 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-test-reference
181 05:23:17.017692 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-test-runner
182 05:23:17.018185 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-test-set
183 05:23:17.018667 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-test-shell
184 05:23:17.019182 Updating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-install-packages (oe)
185 05:23:17.019745 Updating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/bin/lava-installed-packages (oe)
186 05:23:17.020240 Creating /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/environment
187 05:23:17.020686 LAVA metadata
188 05:23:17.020968 - LAVA_JOB_ID=851274
189 05:23:17.021190 - LAVA_DISPATCHER_IP=192.168.6.2
190 05:23:17.021537 start: 1.6.2.1 ssh-authorize (timeout 00:09:35) [common]
191 05:23:17.022462 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 05:23:17.022792 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:35) [common]
193 05:23:17.023004 skipped lava-vland-overlay
194 05:23:17.023249 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 05:23:17.023507 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:35) [common]
196 05:23:17.023727 skipped lava-multinode-overlay
197 05:23:17.023971 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 05:23:17.024270 start: 1.6.2.4 test-definition (timeout 00:09:35) [common]
199 05:23:17.024523 Loading test definitions
200 05:23:17.024805 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:35) [common]
201 05:23:17.025027 Using /lava-851274 at stage 0
202 05:23:17.026177 uuid=851274_1.6.2.4.1 testdef=None
203 05:23:17.026492 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 05:23:17.026762 start: 1.6.2.4.2 test-overlay (timeout 00:09:35) [common]
205 05:23:17.028599 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 05:23:17.029412 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:35) [common]
208 05:23:17.031643 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 05:23:17.032528 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:35) [common]
211 05:23:17.034676 runner path: /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/0/tests/0_dmesg test_uuid 851274_1.6.2.4.1
212 05:23:17.035223 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 05:23:17.036020 Creating lava-test-runner.conf files
215 05:23:17.036226 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/851274/lava-overlay-_501guq7/lava-851274/0 for stage 0
216 05:23:17.036554 - 0_dmesg
217 05:23:17.036896 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 05:23:17.037176 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 05:23:17.058684 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 05:23:17.059049 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 05:23:17.059315 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 05:23:17.059580 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 05:23:17.059843 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 05:23:17.667918 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 05:23:17.668466 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
226 05:23:17.668725 extracting modules file /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/851274/extract-nfsrootfs-25bnig8v
227 05:23:19.002826 extracting modules file /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/851274/extract-overlay-ramdisk-xhrn6wsh/ramdisk
228 05:23:20.386803 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 05:23:20.387286 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
230 05:23:20.387567 [common] Applying overlay to NFS
231 05:23:20.387780 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851274/compress-overlay-ezkmizxn/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/851274/extract-nfsrootfs-25bnig8v
232 05:23:20.416976 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 05:23:20.417348 start: 1.6.6 prepare-kernel (timeout 00:09:31) [common]
234 05:23:20.417624 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:31) [common]
235 05:23:20.417856 Converting downloaded kernel to a uImage
236 05:23:20.418162 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/kernel/Image /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/kernel/uImage
237 05:23:20.915049 output: Image Name:
238 05:23:20.915474 output: Created: Thu Oct 17 05:23:20 2024
239 05:23:20.915688 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 05:23:20.915896 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 05:23:20.916142 output: Load Address: 01080000
242 05:23:20.916348 output: Entry Point: 01080000
243 05:23:20.916547 output:
244 05:23:20.916884 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 05:23:20.917153 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 05:23:20.917423 start: 1.6.7 configure-preseed-file (timeout 00:09:31) [common]
247 05:23:20.917681 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 05:23:20.917943 start: 1.6.8 compress-ramdisk (timeout 00:09:31) [common]
249 05:23:20.918200 Building ramdisk /var/lib/lava/dispatcher/tmp/851274/extract-overlay-ramdisk-xhrn6wsh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/851274/extract-overlay-ramdisk-xhrn6wsh/ramdisk
250 05:23:23.060834 >> 166772 blocks
251 05:23:30.738732 Adding RAMdisk u-boot header.
252 05:23:30.739393 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/851274/extract-overlay-ramdisk-xhrn6wsh/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/851274/extract-overlay-ramdisk-xhrn6wsh/ramdisk.cpio.gz.uboot
253 05:23:30.984687 output: Image Name:
254 05:23:30.985119 output: Created: Thu Oct 17 05:23:30 2024
255 05:23:30.985602 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 05:23:30.986024 output: Data Size: 23424798 Bytes = 22875.78 KiB = 22.34 MiB
257 05:23:30.986454 output: Load Address: 00000000
258 05:23:30.986858 output: Entry Point: 00000000
259 05:23:30.987259 output:
260 05:23:30.988414 rename /var/lib/lava/dispatcher/tmp/851274/extract-overlay-ramdisk-xhrn6wsh/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/ramdisk/ramdisk.cpio.gz.uboot
261 05:23:30.989145 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 05:23:30.989703 end: 1.6 prepare-tftp-overlay (duration 00:00:23) [common]
263 05:23:30.990244 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
264 05:23:30.990708 No LXC device requested
265 05:23:30.991219 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 05:23:30.991740 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
267 05:23:30.992292 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 05:23:30.992716 Checking files for TFTP limit of 4294967296 bytes.
269 05:23:30.995362 end: 1 tftp-deploy (duration 00:00:39) [common]
270 05:23:30.995937 start: 2 uboot-action (timeout 00:05:00) [common]
271 05:23:30.996512 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 05:23:30.997020 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 05:23:30.997532 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 05:23:30.998061 Using kernel file from prepare-kernel: 851274/tftp-deploy-65rctfy2/kernel/uImage
275 05:23:30.998692 substitutions:
276 05:23:30.999106 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 05:23:30.999520 - {DTB_ADDR}: 0x01070000
278 05:23:30.999929 - {DTB}: 851274/tftp-deploy-65rctfy2/dtb/meson-g12b-a311d-libretech-cc.dtb
279 05:23:31.000364 - {INITRD}: 851274/tftp-deploy-65rctfy2/ramdisk/ramdisk.cpio.gz.uboot
280 05:23:31.000770 - {KERNEL_ADDR}: 0x01080000
281 05:23:31.001167 - {KERNEL}: 851274/tftp-deploy-65rctfy2/kernel/uImage
282 05:23:31.001564 - {LAVA_MAC}: None
283 05:23:31.002002 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/851274/extract-nfsrootfs-25bnig8v
284 05:23:31.002407 - {NFS_SERVER_IP}: 192.168.6.2
285 05:23:31.002804 - {PRESEED_CONFIG}: None
286 05:23:31.003198 - {PRESEED_LOCAL}: None
287 05:23:31.003589 - {RAMDISK_ADDR}: 0x08000000
288 05:23:31.004018 - {RAMDISK}: 851274/tftp-deploy-65rctfy2/ramdisk/ramdisk.cpio.gz.uboot
289 05:23:31.004331 - {ROOT_PART}: None
290 05:23:31.004538 - {ROOT}: None
291 05:23:31.004741 - {SERVER_IP}: 192.168.6.2
292 05:23:31.004943 - {TEE_ADDR}: 0x83000000
293 05:23:31.005143 - {TEE}: None
294 05:23:31.005581 Parsed boot commands:
295 05:23:31.005971 - setenv autoload no
296 05:23:31.006388 - setenv initrd_high 0xffffffff
297 05:23:31.006780 - setenv fdt_high 0xffffffff
298 05:23:31.007174 - dhcp
299 05:23:31.007566 - setenv serverip 192.168.6.2
300 05:23:31.007956 - tftpboot 0x01080000 851274/tftp-deploy-65rctfy2/kernel/uImage
301 05:23:31.008379 - tftpboot 0x08000000 851274/tftp-deploy-65rctfy2/ramdisk/ramdisk.cpio.gz.uboot
302 05:23:31.008777 - tftpboot 0x01070000 851274/tftp-deploy-65rctfy2/dtb/meson-g12b-a311d-libretech-cc.dtb
303 05:23:31.009171 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/851274/extract-nfsrootfs-25bnig8v,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 05:23:31.009576 - bootm 0x01080000 0x08000000 0x01070000
305 05:23:31.010079 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 05:23:31.011570 start: 2.3 connect-device (timeout 00:05:00) [common]
308 05:23:31.012015 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 05:23:31.026575 Setting prompt string to ['lava-test: # ']
310 05:23:31.028065 end: 2.3 connect-device (duration 00:00:00) [common]
311 05:23:31.028695 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 05:23:31.029258 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 05:23:31.029789 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 05:23:31.030913 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 05:23:31.068051 >> OK - accepted request
316 05:23:31.070139 Returned 0 in 0 seconds
317 05:23:31.171228 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 05:23:31.172838 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 05:23:31.173417 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 05:23:31.173945 Setting prompt string to ['Hit any key to stop autoboot']
322 05:23:31.174425 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 05:23:31.175968 Trying 192.168.56.21...
324 05:23:31.176480 Connected to conserv1.
325 05:23:31.176919 Escape character is '^]'.
326 05:23:31.177356
327 05:23:31.177795 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 05:23:31.178226
329 05:23:42.754599 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 05:23:42.755216 bl2_stage_init 0x01
331 05:23:42.755656 bl2_stage_init 0x81
332 05:23:42.760341 hw id: 0x0000 - pwm id 0x01
333 05:23:42.760834 bl2_stage_init 0xc1
334 05:23:42.761232 bl2_stage_init 0x02
335 05:23:42.761621
336 05:23:42.765784 L0:00000000
337 05:23:42.766214 L1:20000703
338 05:23:42.766620 L2:00008067
339 05:23:42.767005 L3:14000000
340 05:23:42.771367 B2:00402000
341 05:23:42.771791 B1:e0f83180
342 05:23:42.772219
343 05:23:42.772609 TE: 58159
344 05:23:42.773004
345 05:23:42.776893 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 05:23:42.777320
347 05:23:42.777713 Board ID = 1
348 05:23:42.782484 Set A53 clk to 24M
349 05:23:42.782901 Set A73 clk to 24M
350 05:23:42.783289 Set clk81 to 24M
351 05:23:42.788218 A53 clk: 1200 MHz
352 05:23:42.788635 A73 clk: 1200 MHz
353 05:23:42.789024 CLK81: 166.6M
354 05:23:42.789408 smccc: 00012ab5
355 05:23:42.793614 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 05:23:42.799219 board id: 1
357 05:23:42.805080 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 05:23:42.815740 fw parse done
359 05:23:42.821698 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 05:23:42.864359 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 05:23:42.875247 PIEI prepare done
362 05:23:42.875658 fastboot data load
363 05:23:42.876079 fastboot data verify
364 05:23:42.880819 verify result: 266
365 05:23:42.886393 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 05:23:42.886810 LPDDR4 probe
367 05:23:42.887199 ddr clk to 1584MHz
368 05:23:42.894409 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 05:23:42.931781
370 05:23:42.932234 dmc_version 0001
371 05:23:42.938378 Check phy result
372 05:23:42.949992 INFO : End of CA training
373 05:23:42.950404 INFO : End of initialization
374 05:23:42.950799 INFO : Training has run successfully!
375 05:23:42.951191 Check phy result
376 05:23:42.955390 INFO : End of initialization
377 05:23:42.955804 INFO : End of read enable training
378 05:23:42.961020 INFO : End of fine write leveling
379 05:23:42.966648 INFO : End of Write leveling coarse delay
380 05:23:42.967066 INFO : Training has run successfully!
381 05:23:42.967456 Check phy result
382 05:23:42.972226 INFO : End of initialization
383 05:23:42.972644 INFO : End of read dq deskew training
384 05:23:43.189523 INFO : End of MPR read delay center optimization
385 05:23:43.189952 INFO : End of write delay center optimization
386 05:23:43.190658 INFO : End of read delay center optimization
387 05:23:43.191067 INFO : End of max read latency training
388 05:23:43.191457 INFO : Training has run successfully!
389 05:23:43.191846 1D training succeed
390 05:23:43.192287 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 05:23:43.192687 Check phy result
392 05:23:43.193075 INFO : End of initialization
393 05:23:43.193457 INFO : End of 2D read delay Voltage center optimization
394 05:23:43.193845 INFO : End of 2D read delay Voltage center optimization
395 05:23:43.194236 INFO : End of 2D write delay Voltage center optimization
396 05:23:43.194697 INFO : End of 2D write delay Voltage center optimization
397 05:23:43.199866 INFO : Training has run successfully!
398 05:23:43.200312
399 05:23:43.200708 channel==0
400 05:23:43.205575 RxClkDly_Margin_A0==88 ps 9
401 05:23:43.206004 TxDqDly_Margin_A0==98 ps 10
402 05:23:43.208957 RxClkDly_Margin_A1==88 ps 9
403 05:23:43.209372 TxDqDly_Margin_A1==88 ps 9
404 05:23:43.214531 TrainedVREFDQ_A0==74
405 05:23:43.214950 TrainedVREFDQ_A1==74
406 05:23:43.215342 VrefDac_Margin_A0==25
407 05:23:43.220059 DeviceVref_Margin_A0==40
408 05:23:43.220478 VrefDac_Margin_A1==25
409 05:23:43.225766 DeviceVref_Margin_A1==40
410 05:23:43.226180
411 05:23:43.226573
412 05:23:43.226963 channel==1
413 05:23:43.227350 RxClkDly_Margin_A0==98 ps 10
414 05:23:43.229294 TxDqDly_Margin_A0==98 ps 10
415 05:23:43.234903 RxClkDly_Margin_A1==98 ps 10
416 05:23:43.235320 TxDqDly_Margin_A1==88 ps 9
417 05:23:43.235722 TrainedVREFDQ_A0==77
418 05:23:43.240417 TrainedVREFDQ_A1==77
419 05:23:43.240832 VrefDac_Margin_A0==22
420 05:23:43.265678 DeviceVref_Margin_A0==37
421 05:23:43.266091 VrefDac_Margin_A1==22
422 05:23:43.266480 DeviceVref_Margin_A1==37
423 05:23:43.266866
424 05:23:43.267251 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 05:23:43.267638
426 05:23:43.285118 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 05:23:43.285601 2D training succeed
428 05:23:43.290879 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 05:23:43.296280 auto size-- 65535DDR cs0 size: 2048MB
430 05:23:43.296696 DDR cs1 size: 2048MB
431 05:23:43.301855 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 05:23:43.302273 cs0 DataBus test pass
433 05:23:43.302664 cs1 DataBus test pass
434 05:23:43.307449 cs0 AddrBus test pass
435 05:23:43.307867 cs1 AddrBus test pass
436 05:23:43.308297
437 05:23:43.313056 100bdlr_step_size ps== 420
438 05:23:43.313482 result report
439 05:23:43.313871 boot times 0Enable ddr reg access
440 05:23:43.322704 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 05:23:43.336189 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 05:23:43.908197 0.0;M3 CHK:0;cm4_sp_mode 0
443 05:23:43.908659 MVN_1=0x00000000
444 05:23:43.913734 MVN_2=0x00000000
445 05:23:43.925223 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 05:23:43.925655 OPS=0x10
447 05:23:43.926066 ring efuse init
448 05:23:43.926464 chipver efuse init
449 05:23:43.926857 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 05:23:43.930719 [0.018960 Inits done]
451 05:23:43.931145 secure task start!
452 05:23:43.931549 high task start!
453 05:23:43.935225 low task start!
454 05:23:43.935659 run into bl31
455 05:23:43.941889 NOTICE: BL31: v1.3(release):4fc40b1
456 05:23:43.949685 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 05:23:43.950120 NOTICE: BL31: G12A normal boot!
458 05:23:43.975024 NOTICE: BL31: BL33 decompress pass
459 05:23:43.980721 ERROR: Error initializing runtime service opteed_fast
460 05:23:45.213601
461 05:23:45.214080
462 05:23:45.221991 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 05:23:45.222427
464 05:23:45.222834 Model: Libre Computer AML-A311D-CC Alta
465 05:23:45.430358 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 05:23:45.453754 DRAM: 2 GiB (effective 3.8 GiB)
467 05:23:45.596762 Core: 408 devices, 31 uclasses, devicetree: separate
468 05:23:45.602656 WDT: Not starting watchdog@f0d0
469 05:23:45.638315 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 05:23:45.647393 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 05:23:45.652354 ** Bad device specification mmc 0 **
472 05:23:45.662673 Card did not respond to voltage select! : -110
473 05:23:45.670326 ** Bad device specification mmc 0 **
474 05:23:45.670753 Couldn't find partition mmc 0
475 05:23:45.678665 Card did not respond to voltage select! : -110
476 05:23:45.684206 ** Bad device specification mmc 0 **
477 05:23:45.684632 Couldn't find partition mmc 0
478 05:23:45.689252 Error: could not access storage.
479 05:23:46.954768 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 05:23:46.955247 bl2_stage_init 0x01
481 05:23:46.955664 bl2_stage_init 0x81
482 05:23:46.960323 hw id: 0x0000 - pwm id 0x01
483 05:23:46.960767 bl2_stage_init 0xc1
484 05:23:46.961174 bl2_stage_init 0x02
485 05:23:46.961573
486 05:23:46.965923 L0:00000000
487 05:23:46.966350 L1:20000703
488 05:23:46.966751 L2:00008067
489 05:23:46.967149 L3:14000000
490 05:23:46.971513 B2:00402000
491 05:23:46.971953 B1:e0f83180
492 05:23:46.972390
493 05:23:46.972794 TE: 58159
494 05:23:46.973195
495 05:23:46.982877 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 05:23:46.983316
497 05:23:46.983735 Board ID = 1
498 05:23:46.984167 Set A53 clk to 24M
499 05:23:46.984568 Set A73 clk to 24M
500 05:23:46.984964 Set clk81 to 24M
501 05:23:46.988312 A53 clk: 1200 MHz
502 05:23:46.988741 A73 clk: 1200 MHz
503 05:23:46.989144 CLK81: 166.6M
504 05:23:46.989547 smccc: 00012ab5
505 05:23:46.993913 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 05:23:46.999515 board id: 1
507 05:23:47.005384 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 05:23:47.016153 fw parse done
509 05:23:47.022028 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 05:23:47.064662 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 05:23:47.075530 PIEI prepare done
512 05:23:47.075953 fastboot data load
513 05:23:47.076390 fastboot data verify
514 05:23:47.081153 verify result: 266
515 05:23:47.086747 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 05:23:47.087177 LPDDR4 probe
517 05:23:47.087581 ddr clk to 1584MHz
518 05:23:47.094752 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 05:23:47.132003
520 05:23:47.132436 dmc_version 0001
521 05:23:47.138666 Check phy result
522 05:23:47.150296 INFO : End of CA training
523 05:23:47.150723 INFO : End of initialization
524 05:23:47.151127 INFO : Training has run successfully!
525 05:23:47.151529 Check phy result
526 05:23:47.155735 INFO : End of initialization
527 05:23:47.156194 INFO : End of read enable training
528 05:23:47.161336 INFO : End of fine write leveling
529 05:23:47.166927 INFO : End of Write leveling coarse delay
530 05:23:47.167352 INFO : Training has run successfully!
531 05:23:47.167758 Check phy result
532 05:23:47.172545 INFO : End of initialization
533 05:23:47.172968 INFO : End of read dq deskew training
534 05:23:47.178169 INFO : End of MPR read delay center optimization
535 05:23:47.183719 INFO : End of write delay center optimization
536 05:23:47.189348 INFO : End of read delay center optimization
537 05:23:47.189775 INFO : End of max read latency training
538 05:23:47.194903 INFO : Training has run successfully!
539 05:23:47.195325 1D training succeed
540 05:23:47.204154 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 05:23:47.251683 Check phy result
542 05:23:47.252148 INFO : End of initialization
543 05:23:47.273395 INFO : End of 2D read delay Voltage center optimization
544 05:23:47.293402 INFO : End of 2D read delay Voltage center optimization
545 05:23:47.345417 INFO : End of 2D write delay Voltage center optimization
546 05:23:47.394529 INFO : End of 2D write delay Voltage center optimization
547 05:23:47.400204 INFO : Training has run successfully!
548 05:23:47.400628
549 05:23:47.401036 channel==0
550 05:23:47.405729 RxClkDly_Margin_A0==88 ps 9
551 05:23:47.406154 TxDqDly_Margin_A0==98 ps 10
552 05:23:47.411332 RxClkDly_Margin_A1==88 ps 9
553 05:23:47.411758 TxDqDly_Margin_A1==98 ps 10
554 05:23:47.412214 TrainedVREFDQ_A0==74
555 05:23:47.416949 TrainedVREFDQ_A1==74
556 05:23:47.417379 VrefDac_Margin_A0==25
557 05:23:47.417782 DeviceVref_Margin_A0==40
558 05:23:47.422527 VrefDac_Margin_A1==25
559 05:23:47.422952 DeviceVref_Margin_A1==40
560 05:23:47.423351
561 05:23:47.423751
562 05:23:47.433878 channel==1
563 05:23:47.434302 RxClkDly_Margin_A0==98 ps 10
564 05:23:47.434701 TxDqDly_Margin_A0==88 ps 9
565 05:23:47.435098 RxClkDly_Margin_A1==98 ps 10
566 05:23:47.435491 TxDqDly_Margin_A1==88 ps 9
567 05:23:47.439340 TrainedVREFDQ_A0==77
568 05:23:47.439770 TrainedVREFDQ_A1==77
569 05:23:47.440204 VrefDac_Margin_A0==22
570 05:23:47.444920 DeviceVref_Margin_A0==37
571 05:23:47.445346 VrefDac_Margin_A1==22
572 05:23:47.450523 DeviceVref_Margin_A1==37
573 05:23:47.450941
574 05:23:47.451345 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 05:23:47.451742
576 05:23:47.484157 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 05:23:47.484611 2D training succeed
578 05:23:47.489716 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 05:23:47.495350 auto size-- 65535DDR cs0 size: 2048MB
580 05:23:47.495780 DDR cs1 size: 2048MB
581 05:23:47.500915 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 05:23:47.501351 cs0 DataBus test pass
583 05:23:47.506526 cs1 DataBus test pass
584 05:23:47.506960 cs0 AddrBus test pass
585 05:23:47.507365 cs1 AddrBus test pass
586 05:23:47.507763
587 05:23:47.512133 100bdlr_step_size ps== 420
588 05:23:47.512575 result report
589 05:23:47.517722 boot times 0Enable ddr reg access
590 05:23:47.532136 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 05:23:47.536564 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 05:23:48.108551 0.0;M3 CHK:0;cm4_sp_mode 0
593 05:23:48.108996 MVN_1=0x00000000
594 05:23:48.114088 MVN_2=0x00000000
595 05:23:48.122684 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 05:23:48.123172 OPS=0x10
597 05:23:48.123565 ring efuse init
598 05:23:48.123947 chipver efuse init
599 05:23:48.128065 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 05:23:48.128500 [0.018961 Inits done]
601 05:23:48.135603 secure task start!
602 05:23:48.136043 high task start!
603 05:23:48.136434 low task start!
604 05:23:48.136817 run into bl31
605 05:23:48.142266 NOTICE: BL31: v1.3(release):4fc40b1
606 05:23:48.150042 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 05:23:48.150464 NOTICE: BL31: G12A normal boot!
608 05:23:48.175533 NOTICE: BL31: BL33 decompress pass
609 05:23:48.181190 ERROR: Error initializing runtime service opteed_fast
610 05:23:49.414337
611 05:23:49.414879
612 05:23:49.422606 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 05:23:49.423075
614 05:23:49.423491 Model: Libre Computer AML-A311D-CC Alta
615 05:23:49.631090 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 05:23:49.654438 DRAM: 2 GiB (effective 3.8 GiB)
617 05:23:49.797356 Core: 408 devices, 31 uclasses, devicetree: separate
618 05:23:49.835704 WDT: Not starting watchdog@f0d0
619 05:23:49.836185 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 05:23:49.853124 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 05:23:49.853568 ** Bad device specification mmc 0 **
622 05:23:49.863167 Card did not respond to voltage select! : -110
623 05:23:49.870879 ** Bad device specification mmc 0 **
624 05:23:49.871313 Couldn't find partition mmc 0
625 05:23:49.879245 Card did not respond to voltage select! : -110
626 05:23:49.884797 ** Bad device specification mmc 0 **
627 05:23:49.885232 Couldn't find partition mmc 0
628 05:23:49.889866 Error: could not access storage.
629 05:23:50.232405 Net: eth0: ethernet@ff3f0000
630 05:23:50.232860 starting USB...
631 05:23:50.484098 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 05:23:50.484543 Starting the controller
633 05:23:50.491189 USB XHCI 1.10
634 05:23:52.206856 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 05:23:52.207346 bl2_stage_init 0x01
636 05:23:52.207758 bl2_stage_init 0x81
637 05:23:52.213798 hw id: 0x0000 - pwm id 0x01
638 05:23:52.214228 bl2_stage_init 0xc1
639 05:23:52.214635 bl2_stage_init 0x02
640 05:23:52.215034
641 05:23:52.218225 L0:00000000
642 05:23:52.218653 L1:20000703
643 05:23:52.219058 L2:00008067
644 05:23:52.219457 L3:14000000
645 05:23:52.223647 B2:00402000
646 05:23:52.224098 B1:e0f83180
647 05:23:52.224503
648 05:23:52.224904 TE: 58159
649 05:23:52.225305
650 05:23:52.229266 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 05:23:52.229698
652 05:23:52.230104 Board ID = 1
653 05:23:52.233988 Set A53 clk to 24M
654 05:23:52.234417 Set A73 clk to 24M
655 05:23:52.234820 Set clk81 to 24M
656 05:23:52.239493 A53 clk: 1200 MHz
657 05:23:52.239919 A73 clk: 1200 MHz
658 05:23:52.240354 CLK81: 166.6M
659 05:23:52.245179 smccc: 00012ab5
660 05:23:52.250681 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 05:23:52.251107 board id: 1
662 05:23:52.257535 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 05:23:52.268058 fw parse done
664 05:23:52.274148 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 05:23:52.316763 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 05:23:52.333351 PIEI prepare done
667 05:23:52.333772 fastboot data load
668 05:23:52.334181 fastboot data verify
669 05:23:52.334584 verify result: 266
670 05:23:52.338823 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 05:23:52.339249 LPDDR4 probe
672 05:23:52.339653 ddr clk to 1584MHz
673 05:23:52.346787 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 05:23:52.384071
675 05:23:52.384508 dmc_version 0001
676 05:23:52.390734 Check phy result
677 05:23:52.396569 INFO : End of CA training
678 05:23:52.397011 INFO : End of initialization
679 05:23:52.402218 INFO : Training has run successfully!
680 05:23:52.402648 Check phy result
681 05:23:52.621510 INFO : End of initialization
682 05:23:52.621958 INFO : End of read enable training
683 05:23:52.622366 INFO : End of fine write leveling
684 05:23:52.853670 INFO : End of Write leveling coarse delay
685 05:23:52.854113 INFO : Training has run successfully!
686 05:23:52.854521 Check phy result
687 05:23:52.854920 INFO : End of initialization
688 05:23:52.855317 INFO : End of read dq deskew training
689 05:23:52.855716 INFO : End of MPR read delay center optimization
690 05:23:52.856156 INFO : End of write delay center optimization
691 05:23:52.856563 INFO : End of read delay center optimization
692 05:23:52.856962 INFO : End of max read latency training
693 05:23:52.857358 INFO : Training has run successfully!
694 05:23:52.857758 1D training succeed
695 05:23:52.858161 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 05:23:52.858561 Check phy result
697 05:23:52.858957 INFO : End of initialization
698 05:23:52.859351 INFO : End of 2D read delay Voltage center optimization
699 05:23:52.859750 INFO : End of 2D read delay Voltage center optimization
700 05:23:52.860173 INFO : End of 2D write delay Voltage center optimization
701 05:23:52.860567 INFO : End of 2D write delay Voltage center optimization
702 05:23:53.497849 INFO : Training has run successfully!
703 05:23:53.498313
704 05:23:53.498735 channel==0
705 05:23:53.499153 RxClkDly_Margin_A0==88 ps 9
706 05:23:53.499556 TxDqDly_Margin_A0==98 ps 10
707 05:23:53.499956 RxClkDly_Margin_A1==88 ps 9
708 05:23:53.500425 TxDqDly_Margin_A1==98 ps 10
709 05:23:53.500816 TrainedVREFDQ_A0==74
710 05:23:53.501202 TrainedVREFDQ_A1==74
711 05:23:53.501587 VrefDac_Margin_A0==25
712 05:23:53.501967 DeviceVref_Margin_A0==40
713 05:23:53.502348 VrefDac_Margin_A1==25
714 05:23:53.502728 DeviceVref_Margin_A1==40
715 05:23:53.503122
716 05:23:53.503520
717 05:23:53.503916 channel==1
718 05:23:53.504413 RxClkDly_Margin_A0==98 ps 10
719 05:23:53.504831 TxDqDly_Margin_A0==88 ps 9
720 05:23:53.505255 RxClkDly_Margin_A1==98 ps 10
721 05:23:53.505643 TxDqDly_Margin_A1==88 ps 9
722 05:23:53.506026 TrainedVREFDQ_A0==76
723 05:23:53.506406 TrainedVREFDQ_A1==77
724 05:23:53.506786 VrefDac_Margin_A0==22
725 05:23:53.507160 DeviceVref_Margin_A0==38
726 05:23:53.507534 VrefDac_Margin_A1==24
727 05:23:53.507907 DeviceVref_Margin_A1==37
728 05:23:53.508321
729 05:23:53.508704 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 05:23:53.509084
731 05:23:53.509461 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 05:23:53.509855 2D training succeed
733 05:23:53.510241 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 05:23:53.510619 auto size-- 65535DDR cs0 size: 2048MB
735 05:23:53.510995 DDR cs1 size: 2048MB
736 05:23:53.511368 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 05:23:53.511743 cs0 DataBus test pass
738 05:23:53.512149 cs1 DataBus test pass
739 05:23:53.512528 cs0 AddrBus test pass
740 05:23:53.512904 cs1 AddrBus test pass
741 05:23:53.513279
742 05:23:53.513661 100bdlr_step_size ps== 420
743 05:23:53.514047 result report
744 05:23:53.514420 boot times 0Enable ddr reg access
745 05:23:53.514795 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 05:23:53.515185 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 05:23:53.515565 0.0;M3 CHK:0;cm4_sp_mode 0
748 05:23:53.515951 MVN_1=0x00000000
749 05:23:53.516353 MVN_2=0x00000000
750 05:23:53.516729 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 05:23:53.517110 OPS=0x10
752 05:23:53.517489 ring efuse init
753 05:23:53.517865 chipver efuse init
754 05:23:53.518239 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 05:23:53.518624 [0.018961 Inits done]
756 05:23:53.519003 secure task start!
757 05:23:53.519376 high task start!
758 05:23:53.519750 low task start!
759 05:23:53.520148 run into bl31
760 05:23:53.520522 NOTICE: BL31: v1.3(release):4fc40b1
761 05:23:53.520902 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 05:23:53.521284 NOTICE: BL31: G12A normal boot!
763 05:23:53.521664 NOTICE: BL31: BL33 decompress pass
764 05:23:53.522046 ERROR: Error initializing runtime service opteed_fast
765 05:23:54.668382
766 05:23:54.669025
767 05:23:54.676591 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 05:23:54.677047
769 05:23:54.677469 Model: Libre Computer AML-A311D-CC Alta
770 05:23:54.884961 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 05:23:54.908440 DRAM: 2 GiB (effective 3.8 GiB)
772 05:23:55.051427 Core: 408 devices, 31 uclasses, devicetree: separate
773 05:23:55.057252 WDT: Not starting watchdog@f0d0
774 05:23:55.092890 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 05:23:55.102002 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 05:23:55.106963 ** Bad device specification mmc 0 **
777 05:23:55.117396 Card did not respond to voltage select! : -110
778 05:23:55.124950 ** Bad device specification mmc 0 **
779 05:23:55.125386 Couldn't find partition mmc 0
780 05:23:55.138940 Card did not respond to voltage select! : -110
781 05:23:55.139375 ** Bad device specification mmc 0 **
782 05:23:55.139790 Couldn't find partition mmc 0
783 05:23:55.143864 Error: could not access storage.
784 05:23:55.486305 Net: eth0: ethernet@ff3f0000
785 05:23:55.486754 starting USB...
786 05:23:55.738095 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 05:23:55.738532 Starting the controller
788 05:23:55.745102 USB XHCI 1.10
789 05:23:57.911152 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 05:23:57.911642 bl2_stage_init 0x01
791 05:23:57.912112 bl2_stage_init 0x81
792 05:23:57.912531 hw id: 0x0000 - pwm id 0x01
793 05:23:57.912937 bl2_stage_init 0xc1
794 05:23:57.913338 bl2_stage_init 0x02
795 05:23:57.913740
796 05:23:57.916452 L0:00000000
797 05:23:57.916894 L1:20000703
798 05:23:57.917299 L2:00008067
799 05:23:57.917697 L3:14000000
800 05:23:57.922124 B2:00402000
801 05:23:57.922553 B1:e0f83180
802 05:23:57.922958
803 05:23:57.923361 TE: 58167
804 05:23:57.923763
805 05:23:57.927620 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 05:23:57.928088
807 05:23:57.928504 Board ID = 1
808 05:23:57.933211 Set A53 clk to 24M
809 05:23:57.933644 Set A73 clk to 24M
810 05:23:57.934049 Set clk81 to 24M
811 05:23:57.939669 A53 clk: 1200 MHz
812 05:23:57.940123 A73 clk: 1200 MHz
813 05:23:57.940530 CLK81: 166.6M
814 05:23:57.940928 smccc: 00012abe
815 05:23:57.944447 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 05:23:57.950052 board id: 1
817 05:23:57.956158 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 05:23:57.966406 fw parse done
819 05:23:57.972365 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 05:23:58.015011 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 05:23:58.025893 PIEI prepare done
822 05:23:58.026318 fastboot data load
823 05:23:58.026728 fastboot data verify
824 05:23:58.031502 verify result: 266
825 05:23:58.037089 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 05:23:58.037523 LPDDR4 probe
827 05:23:58.037922 ddr clk to 1584MHz
828 05:23:58.045066 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 05:23:58.082310
830 05:23:58.082737 dmc_version 0001
831 05:23:58.089026 Check phy result
832 05:23:58.094908 INFO : End of CA training
833 05:23:58.095334 INFO : End of initialization
834 05:23:58.100496 INFO : Training has run successfully!
835 05:23:58.100925 Check phy result
836 05:23:58.106078 INFO : End of initialization
837 05:23:58.106504 INFO : End of read enable training
838 05:23:58.111680 INFO : End of fine write leveling
839 05:23:58.117288 INFO : End of Write leveling coarse delay
840 05:23:58.117722 INFO : Training has run successfully!
841 05:23:58.118127 Check phy result
842 05:23:58.122877 INFO : End of initialization
843 05:23:58.123302 INFO : End of read dq deskew training
844 05:23:58.128463 INFO : End of MPR read delay center optimization
845 05:23:58.134091 INFO : End of write delay center optimization
846 05:23:58.139672 INFO : End of read delay center optimization
847 05:23:58.140118 INFO : End of max read latency training
848 05:23:58.145288 INFO : Training has run successfully!
849 05:23:58.145716 1D training succeed
850 05:23:58.154496 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 05:23:58.202047 Check phy result
852 05:23:58.202481 INFO : End of initialization
853 05:23:58.224670 INFO : End of 2D read delay Voltage center optimization
854 05:23:58.244901 INFO : End of 2D read delay Voltage center optimization
855 05:23:58.296914 INFO : End of 2D write delay Voltage center optimization
856 05:23:58.346294 INFO : End of 2D write delay Voltage center optimization
857 05:23:58.351883 INFO : Training has run successfully!
858 05:23:58.352343
859 05:23:58.352755 channel==0
860 05:23:58.357481 RxClkDly_Margin_A0==88 ps 9
861 05:23:58.357910 TxDqDly_Margin_A0==98 ps 10
862 05:23:58.360862 RxClkDly_Margin_A1==88 ps 9
863 05:23:58.361286 TxDqDly_Margin_A1==98 ps 10
864 05:23:58.366402 TrainedVREFDQ_A0==74
865 05:23:58.366829 TrainedVREFDQ_A1==74
866 05:23:58.367235 VrefDac_Margin_A0==24
867 05:23:58.372010 DeviceVref_Margin_A0==40
868 05:23:58.372434 VrefDac_Margin_A1==26
869 05:23:58.377603 DeviceVref_Margin_A1==40
870 05:23:58.378030
871 05:23:58.378437
872 05:23:58.378838 channel==1
873 05:23:58.379235 RxClkDly_Margin_A0==98 ps 10
874 05:23:58.380916 TxDqDly_Margin_A0==98 ps 10
875 05:23:58.386530 RxClkDly_Margin_A1==98 ps 10
876 05:23:58.386956 TxDqDly_Margin_A1==88 ps 9
877 05:23:58.387362 TrainedVREFDQ_A0==77
878 05:23:58.392162 TrainedVREFDQ_A1==77
879 05:23:58.392592 VrefDac_Margin_A0==22
880 05:23:58.397705 DeviceVref_Margin_A0==37
881 05:23:58.398146 VrefDac_Margin_A1==22
882 05:23:58.398552 DeviceVref_Margin_A1==37
883 05:23:58.398949
884 05:23:58.403319 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 05:23:58.403748
886 05:23:58.437045 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000017 00000016 00000018 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 05:23:58.437513 2D training succeed
888 05:23:58.442530 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 05:23:58.453852 auto size-- 65535DDR cs0 size: 2048MB
890 05:23:58.454279 DDR cs1 size: 2048MB
891 05:23:58.454683 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 05:23:58.455083 cs0 DataBus test pass
893 05:23:58.455479 cs1 DataBus test pass
894 05:23:58.459316 cs0 AddrBus test pass
895 05:23:58.459743 cs1 AddrBus test pass
896 05:23:58.460191
897 05:23:58.464932 100bdlr_step_size ps== 420
898 05:23:58.465373 result report
899 05:23:58.465774 boot times 0Enable ddr reg access
900 05:23:58.475051 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 05:23:58.488413 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 05:23:59.062074 0.0;M3 CHK:0;cm4_sp_mode 0
903 05:23:59.062534 MVN_1=0x00000000
904 05:23:59.067636 MVN_2=0x00000000
905 05:23:59.073404 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 05:23:59.073891 OPS=0x10
907 05:23:59.074284 ring efuse init
908 05:23:59.074670 chipver efuse init
909 05:23:59.078982 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 05:23:59.084580 [0.018960 Inits done]
911 05:23:59.084994 secure task start!
912 05:23:59.085379 high task start!
913 05:23:59.089161 low task start!
914 05:23:59.089575 run into bl31
915 05:23:59.095798 NOTICE: BL31: v1.3(release):4fc40b1
916 05:23:59.103554 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 05:23:59.103977 NOTICE: BL31: G12A normal boot!
918 05:23:59.128955 NOTICE: BL31: BL33 decompress pass
919 05:23:59.134619 ERROR: Error initializing runtime service opteed_fast
920 05:24:00.367519
921 05:24:00.368090
922 05:24:00.375899 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 05:24:00.376366
924 05:24:00.376789 Model: Libre Computer AML-A311D-CC Alta
925 05:24:00.584278 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 05:24:00.607706 DRAM: 2 GiB (effective 3.8 GiB)
927 05:24:00.750667 Core: 408 devices, 31 uclasses, devicetree: separate
928 05:24:00.756578 WDT: Not starting watchdog@f0d0
929 05:24:00.788795 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 05:24:00.801287 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 05:24:00.806269 ** Bad device specification mmc 0 **
932 05:24:00.816606 Card did not respond to voltage select! : -110
933 05:24:00.824308 ** Bad device specification mmc 0 **
934 05:24:00.824738 Couldn't find partition mmc 0
935 05:24:00.832601 Card did not respond to voltage select! : -110
936 05:24:00.838161 ** Bad device specification mmc 0 **
937 05:24:00.838593 Couldn't find partition mmc 0
938 05:24:00.843239 Error: could not access storage.
939 05:24:01.185647 Net: eth0: ethernet@ff3f0000
940 05:24:01.186081 starting USB...
941 05:24:01.437419 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 05:24:01.437845 Starting the controller
943 05:24:01.444410 USB XHCI 1.10
944 05:24:03.305208 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 05:24:03.305827 bl2_stage_init 0x01
946 05:24:03.306251 bl2_stage_init 0x81
947 05:24:03.310794 hw id: 0x0000 - pwm id 0x01
948 05:24:03.311237 bl2_stage_init 0xc1
949 05:24:03.311649 bl2_stage_init 0x02
950 05:24:03.312096
951 05:24:03.316332 L0:00000000
952 05:24:03.316774 L1:20000703
953 05:24:03.317178 L2:00008067
954 05:24:03.317577 L3:14000000
955 05:24:03.321980 B2:00402000
956 05:24:03.322410 B1:e0f83180
957 05:24:03.322815
958 05:24:03.323216 TE: 58124
959 05:24:03.323618
960 05:24:03.327711 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 05:24:03.328176
962 05:24:03.328585 Board ID = 1
963 05:24:03.333196 Set A53 clk to 24M
964 05:24:03.333627 Set A73 clk to 24M
965 05:24:03.334030 Set clk81 to 24M
966 05:24:03.338866 A53 clk: 1200 MHz
967 05:24:03.339305 A73 clk: 1200 MHz
968 05:24:03.339707 CLK81: 166.6M
969 05:24:03.340131 smccc: 00012a92
970 05:24:03.344304 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 05:24:03.349885 board id: 1
972 05:24:03.355795 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 05:24:03.366436 fw parse done
974 05:24:03.372433 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 05:24:03.415354 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 05:24:03.425999 PIEI prepare done
977 05:24:03.426470 fastboot data load
978 05:24:03.426883 fastboot data verify
979 05:24:03.431597 verify result: 266
980 05:24:03.437113 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 05:24:03.437547 LPDDR4 probe
982 05:24:03.437948 ddr clk to 1584MHz
983 05:24:03.445071 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 05:24:03.482332
985 05:24:03.482771 dmc_version 0001
986 05:24:03.489044 Check phy result
987 05:24:03.494898 INFO : End of CA training
988 05:24:03.495325 INFO : End of initialization
989 05:24:03.500623 INFO : Training has run successfully!
990 05:24:03.501054 Check phy result
991 05:24:03.506097 INFO : End of initialization
992 05:24:03.506523 INFO : End of read enable training
993 05:24:03.509491 INFO : End of fine write leveling
994 05:24:03.515023 INFO : End of Write leveling coarse delay
995 05:24:03.520667 INFO : Training has run successfully!
996 05:24:03.521092 Check phy result
997 05:24:03.521493 INFO : End of initialization
998 05:24:03.526230 INFO : End of read dq deskew training
999 05:24:03.529638 INFO : End of MPR read delay center optimization
1000 05:24:03.535152 INFO : End of write delay center optimization
1001 05:24:03.546521 INFO : End of read delay center optimization
1002 05:24:03.546946 INFO : End of max read latency training
1003 05:24:03.547352 INFO : Training has run successfully!
1004 05:24:03.547751 1D training succeed
1005 05:24:03.554558 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 05:24:03.602065 Check phy result
1007 05:24:03.602492 INFO : End of initialization
1008 05:24:03.623723 INFO : End of 2D read delay Voltage center optimization
1009 05:24:03.643873 INFO : End of 2D read delay Voltage center optimization
1010 05:24:03.695813 INFO : End of 2D write delay Voltage center optimization
1011 05:24:03.744963 INFO : End of 2D write delay Voltage center optimization
1012 05:24:03.750556 INFO : Training has run successfully!
1013 05:24:03.750984
1014 05:24:03.751388 channel==0
1015 05:24:03.756207 RxClkDly_Margin_A0==88 ps 9
1016 05:24:03.756637 TxDqDly_Margin_A0==98 ps 10
1017 05:24:03.761689 RxClkDly_Margin_A1==88 ps 9
1018 05:24:03.762114 TxDqDly_Margin_A1==98 ps 10
1019 05:24:03.762519 TrainedVREFDQ_A0==74
1020 05:24:03.767301 TrainedVREFDQ_A1==74
1021 05:24:03.767733 VrefDac_Margin_A0==25
1022 05:24:03.768175 DeviceVref_Margin_A0==40
1023 05:24:03.772995 VrefDac_Margin_A1==25
1024 05:24:03.773417 DeviceVref_Margin_A1==40
1025 05:24:03.773813
1026 05:24:03.774209
1027 05:24:03.778568 channel==1
1028 05:24:03.778994 RxClkDly_Margin_A0==98 ps 10
1029 05:24:03.779396 TxDqDly_Margin_A0==98 ps 10
1030 05:24:03.784175 RxClkDly_Margin_A1==88 ps 9
1031 05:24:03.784602 TxDqDly_Margin_A1==88 ps 9
1032 05:24:03.789670 TrainedVREFDQ_A0==77
1033 05:24:03.790098 TrainedVREFDQ_A1==77
1034 05:24:03.790502 VrefDac_Margin_A0==22
1035 05:24:03.795290 DeviceVref_Margin_A0==37
1036 05:24:03.795714 VrefDac_Margin_A1==24
1037 05:24:03.800903 DeviceVref_Margin_A1==37
1038 05:24:03.801332
1039 05:24:03.801733 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 05:24:03.802131
1041 05:24:03.834656 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 05:24:03.835113 2D training succeed
1043 05:24:03.840178 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 05:24:03.845633 auto size-- 65535DDR cs0 size: 2048MB
1045 05:24:03.846056 DDR cs1 size: 2048MB
1046 05:24:03.851235 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 05:24:03.851662 cs0 DataBus test pass
1048 05:24:03.856834 cs1 DataBus test pass
1049 05:24:03.857259 cs0 AddrBus test pass
1050 05:24:03.857661 cs1 AddrBus test pass
1051 05:24:03.858054
1052 05:24:03.862461 100bdlr_step_size ps== 420
1053 05:24:03.862897 result report
1054 05:24:03.873522 boot times 0Enable ddr reg access
1055 05:24:03.873947 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 05:24:03.886835 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 05:24:04.458876 0.0;M3 CHK:0;cm4_sp_mode 0
1058 05:24:04.459354 MVN_1=0x00000000
1059 05:24:04.464405 MVN_2=0x00000000
1060 05:24:04.470154 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 05:24:04.470643 OPS=0x10
1062 05:24:04.471036 ring efuse init
1063 05:24:04.471420 chipver efuse init
1064 05:24:04.475739 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 05:24:04.481329 [0.018961 Inits done]
1066 05:24:04.481743 secure task start!
1067 05:24:04.482127 high task start!
1068 05:24:04.485914 low task start!
1069 05:24:04.486330 run into bl31
1070 05:24:04.492673 NOTICE: BL31: v1.3(release):4fc40b1
1071 05:24:04.500346 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 05:24:04.500765 NOTICE: BL31: G12A normal boot!
1073 05:24:04.526270 NOTICE: BL31: BL33 decompress pass
1074 05:24:04.531962 ERROR: Error initializing runtime service opteed_fast
1075 05:24:05.764968
1076 05:24:05.765456
1077 05:24:05.773276 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 05:24:05.773715
1079 05:24:05.774122 Model: Libre Computer AML-A311D-CC Alta
1080 05:24:05.981669 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 05:24:06.005092 DRAM: 2 GiB (effective 3.8 GiB)
1082 05:24:06.148086 Core: 408 devices, 31 uclasses, devicetree: separate
1083 05:24:06.153981 WDT: Not starting watchdog@f0d0
1084 05:24:06.186183 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 05:24:06.203797 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 05:24:06.204257 ** Bad device specification mmc 0 **
1087 05:24:06.213968 Card did not respond to voltage select! : -110
1088 05:24:06.221622 ** Bad device specification mmc 0 **
1089 05:24:06.222049 Couldn't find partition mmc 0
1090 05:24:06.229967 Card did not respond to voltage select! : -110
1091 05:24:06.235475 ** Bad device specification mmc 0 **
1092 05:24:06.235906 Couldn't find partition mmc 0
1093 05:24:06.240549 Error: could not access storage.
1094 05:24:06.583044 Net: eth0: ethernet@ff3f0000
1095 05:24:06.583476 starting USB...
1096 05:24:06.834799 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 05:24:06.835230 Starting the controller
1098 05:24:06.841785 USB XHCI 1.10
1099 05:24:08.395927 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 05:24:08.404305 scanning usb for storage devices... 0 Storage Device(s) found
1102 05:24:08.455712 Hit any key to stop autoboot: 1
1103 05:24:08.456474 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 05:24:08.457043 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 05:24:08.457511 Setting prompt string to ['=>']
1106 05:24:08.457986 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 05:24:08.471700 0
1108 05:24:08.472557 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 05:24:08.473042 Sending with 10 millisecond of delay
1111 05:24:09.607458 => setenv autoload no
1112 05:24:09.618093 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1113 05:24:09.622804 setenv autoload no
1114 05:24:09.623497 Sending with 10 millisecond of delay
1116 05:24:11.419890 => setenv initrd_high 0xffffffff
1117 05:24:11.430629 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 05:24:11.431429 setenv initrd_high 0xffffffff
1119 05:24:11.432129 Sending with 10 millisecond of delay
1121 05:24:13.047950 => setenv fdt_high 0xffffffff
1122 05:24:13.058611 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 05:24:13.059355 setenv fdt_high 0xffffffff
1124 05:24:13.060059 Sending with 10 millisecond of delay
1126 05:24:13.351758 => dhcp
1127 05:24:13.362387 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 05:24:13.363107 dhcp
1129 05:24:13.363530 Speed: 1000, full duplex
1130 05:24:13.363932 BOOTP broadcast 1
1131 05:24:13.643325 DHCP client bound to address 192.168.6.244 (280 ms)
1132 05:24:13.644058 Sending with 10 millisecond of delay
1134 05:24:15.320036 => setenv serverip 192.168.6.2
1135 05:24:15.330694 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 05:24:15.331508 setenv serverip 192.168.6.2
1137 05:24:15.332182 Sending with 10 millisecond of delay
1139 05:24:19.054464 => tftpboot 0x01080000 851274/tftp-deploy-65rctfy2/kernel/uImage
1140 05:24:19.065209 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 05:24:19.066007 tftpboot 0x01080000 851274/tftp-deploy-65rctfy2/kernel/uImage
1142 05:24:19.066445 Speed: 1000, full duplex
1143 05:24:19.066860 Using ethernet@ff3f0000 device
1144 05:24:19.067825 TFTP from server 192.168.6.2; our IP address is 192.168.6.244
1145 05:24:19.073439 Filename '851274/tftp-deploy-65rctfy2/kernel/uImage'.
1146 05:24:19.077451 Load address: 0x1080000
1147 05:25:14.122809 Loading: *T T T T T T T T T T
1148 05:25:14.123447 Retry count exceeded; starting again
1150 05:25:14.124836 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
1153 05:25:14.126690 end: 2.4 uboot-commands (duration 00:01:43) [common]
1155 05:25:14.128184 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1157 05:25:14.129162 end: 2 uboot-action (duration 00:01:43) [common]
1159 05:25:14.130652 Cleaning after the job
1160 05:25:14.131181 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/ramdisk
1161 05:25:14.144433 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/kernel
1162 05:25:14.168128 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/dtb
1163 05:25:14.169213 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/nfsrootfs
1164 05:25:14.322319 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851274/tftp-deploy-65rctfy2/modules
1165 05:25:14.342533 start: 4.1 power-off (timeout 00:00:30) [common]
1166 05:25:14.343178 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1167 05:25:14.376293 >> OK - accepted request
1168 05:25:14.378299 Returned 0 in 0 seconds
1169 05:25:14.479021 end: 4.1 power-off (duration 00:00:00) [common]
1171 05:25:14.479922 start: 4.2 read-feedback (timeout 00:10:00) [common]
1172 05:25:14.480611 Listened to connection for namespace 'common' for up to 1s
1173 05:25:15.481418 Finalising connection for namespace 'common'
1174 05:25:15.481775 Disconnecting from shell: Finalise
1175 05:25:15.482047 =>
1176 05:25:15.583440 end: 4.2 read-feedback (duration 00:00:01) [common]
1177 05:25:15.583805 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/851274
1178 05:25:17.204861 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/851274
1179 05:25:17.205483 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.