Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:51:15.031212 lava-dispatcher, installed at version: 2024.01
2 06:51:15.031969 start: 0 validate
3 06:51:15.032477 Start time: 2024-10-17 06:51:15.032448+00:00 (UTC)
4 06:51:15.032996 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:51:15.033530 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 06:51:15.078034 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:51:15.078568 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:51:15.110657 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:51:15.111387 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:51:15.145938 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:51:15.146514 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 06:51:15.187760 validate duration: 0.16
14 06:51:15.188803 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:51:15.189224 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:51:15.189608 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:51:15.190312 Not decompressing ramdisk as can be used compressed.
18 06:51:15.190840 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 06:51:15.191147 saving as /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/ramdisk/rootfs.cpio.gz
20 06:51:15.191475 total size: 47897469 (45 MB)
21 06:51:15.230811 progress 0 % (0 MB)
22 06:51:15.267916 progress 5 % (2 MB)
23 06:51:15.303703 progress 10 % (4 MB)
24 06:51:15.339111 progress 15 % (6 MB)
25 06:51:15.374833 progress 20 % (9 MB)
26 06:51:15.410032 progress 25 % (11 MB)
27 06:51:15.445714 progress 30 % (13 MB)
28 06:51:15.481168 progress 35 % (16 MB)
29 06:51:15.516752 progress 40 % (18 MB)
30 06:51:15.552147 progress 45 % (20 MB)
31 06:51:15.587646 progress 50 % (22 MB)
32 06:51:15.623753 progress 55 % (25 MB)
33 06:51:15.659427 progress 60 % (27 MB)
34 06:51:15.695333 progress 65 % (29 MB)
35 06:51:15.730714 progress 70 % (32 MB)
36 06:51:15.766203 progress 75 % (34 MB)
37 06:51:15.801674 progress 80 % (36 MB)
38 06:51:15.836927 progress 85 % (38 MB)
39 06:51:15.872716 progress 90 % (41 MB)
40 06:51:15.908018 progress 95 % (43 MB)
41 06:51:15.943296 progress 100 % (45 MB)
42 06:51:15.944191 45 MB downloaded in 0.75 s (60.69 MB/s)
43 06:51:15.944892 end: 1.1.1 http-download (duration 00:00:01) [common]
45 06:51:15.946000 end: 1.1 download-retry (duration 00:00:01) [common]
46 06:51:15.946377 start: 1.2 download-retry (timeout 00:09:59) [common]
47 06:51:15.946733 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 06:51:15.947309 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/kernel/Image
49 06:51:15.947643 saving as /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/kernel/Image
50 06:51:15.947916 total size: 45713920 (43 MB)
51 06:51:15.948231 No compression specified
52 06:51:15.991463 progress 0 % (0 MB)
53 06:51:16.024252 progress 5 % (2 MB)
54 06:51:16.057198 progress 10 % (4 MB)
55 06:51:16.090146 progress 15 % (6 MB)
56 06:51:16.122956 progress 20 % (8 MB)
57 06:51:16.155492 progress 25 % (10 MB)
58 06:51:16.188457 progress 30 % (13 MB)
59 06:51:16.221382 progress 35 % (15 MB)
60 06:51:16.254374 progress 40 % (17 MB)
61 06:51:16.286698 progress 45 % (19 MB)
62 06:51:16.319383 progress 50 % (21 MB)
63 06:51:16.352018 progress 55 % (24 MB)
64 06:51:16.384987 progress 60 % (26 MB)
65 06:51:16.417178 progress 65 % (28 MB)
66 06:51:16.449934 progress 70 % (30 MB)
67 06:51:16.482747 progress 75 % (32 MB)
68 06:51:16.515581 progress 80 % (34 MB)
69 06:51:16.548275 progress 85 % (37 MB)
70 06:51:16.580949 progress 90 % (39 MB)
71 06:51:16.613776 progress 95 % (41 MB)
72 06:51:16.645787 progress 100 % (43 MB)
73 06:51:16.646401 43 MB downloaded in 0.70 s (62.42 MB/s)
74 06:51:16.647009 end: 1.2.1 http-download (duration 00:00:01) [common]
76 06:51:16.648060 end: 1.2 download-retry (duration 00:00:01) [common]
77 06:51:16.648435 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:51:16.648781 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:51:16.649352 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 06:51:16.649661 saving as /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/dtb/meson-g12b-a311d-libretech-cc.dtb
81 06:51:16.649930 total size: 54703 (0 MB)
82 06:51:16.650195 No compression specified
83 06:51:16.690092 progress 59 % (0 MB)
84 06:51:16.691089 progress 100 % (0 MB)
85 06:51:16.691767 0 MB downloaded in 0.04 s (1.25 MB/s)
86 06:51:16.692367 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:51:16.693476 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:51:16.693821 start: 1.4 download-retry (timeout 00:09:58) [common]
90 06:51:16.694170 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 06:51:16.694817 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-29-g38d09a34b422/arm64/defconfig/gcc-12/modules.tar.xz
92 06:51:16.695135 saving as /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/modules/modules.tar
93 06:51:16.695392 total size: 11619040 (11 MB)
94 06:51:16.695654 Using unxz to decompress xz
95 06:51:16.733744 progress 0 % (0 MB)
96 06:51:16.794753 progress 5 % (0 MB)
97 06:51:16.872164 progress 10 % (1 MB)
98 06:51:16.957048 progress 15 % (1 MB)
99 06:51:17.047470 progress 20 % (2 MB)
100 06:51:17.129584 progress 25 % (2 MB)
101 06:51:17.206623 progress 30 % (3 MB)
102 06:51:17.288002 progress 35 % (3 MB)
103 06:51:17.362659 progress 40 % (4 MB)
104 06:51:17.438832 progress 45 % (5 MB)
105 06:51:17.519537 progress 50 % (5 MB)
106 06:51:17.601482 progress 55 % (6 MB)
107 06:51:17.679269 progress 60 % (6 MB)
108 06:51:17.753192 progress 65 % (7 MB)
109 06:51:17.831570 progress 70 % (7 MB)
110 06:51:17.903835 progress 75 % (8 MB)
111 06:51:17.979158 progress 80 % (8 MB)
112 06:51:18.061620 progress 85 % (9 MB)
113 06:51:18.144250 progress 90 % (10 MB)
114 06:51:18.218651 progress 95 % (10 MB)
115 06:51:18.296730 progress 100 % (11 MB)
116 06:51:18.309470 11 MB downloaded in 1.61 s (6.87 MB/s)
117 06:51:18.310124 end: 1.4.1 http-download (duration 00:00:02) [common]
119 06:51:18.311130 end: 1.4 download-retry (duration 00:00:02) [common]
120 06:51:18.311453 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 06:51:18.311776 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 06:51:18.312281 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:51:18.312950 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 06:51:18.314189 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160
125 06:51:18.315224 makedir: /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin
126 06:51:18.316044 makedir: /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/tests
127 06:51:18.316835 makedir: /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/results
128 06:51:18.317611 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-add-keys
129 06:51:18.318789 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-add-sources
130 06:51:18.319933 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-background-process-start
131 06:51:18.321139 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-background-process-stop
132 06:51:18.322352 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-common-functions
133 06:51:18.323457 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-echo-ipv4
134 06:51:18.324790 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-install-packages
135 06:51:18.325904 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-installed-packages
136 06:51:18.326985 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-os-build
137 06:51:18.328107 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-probe-channel
138 06:51:18.329213 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-probe-ip
139 06:51:18.330310 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-target-ip
140 06:51:18.331407 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-target-mac
141 06:51:18.332580 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-target-storage
142 06:51:18.333716 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-test-case
143 06:51:18.334821 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-test-event
144 06:51:18.335908 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-test-feedback
145 06:51:18.337202 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-test-raise
146 06:51:18.338313 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-test-reference
147 06:51:18.339422 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-test-runner
148 06:51:18.340575 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-test-set
149 06:51:18.341681 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-test-shell
150 06:51:18.342788 Updating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-install-packages (oe)
151 06:51:18.343970 Updating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/bin/lava-installed-packages (oe)
152 06:51:18.345039 Creating /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/environment
153 06:51:18.345913 LAVA metadata
154 06:51:18.346522 - LAVA_JOB_ID=851280
155 06:51:18.347069 - LAVA_DISPATCHER_IP=192.168.6.2
156 06:51:18.347872 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 06:51:18.349205 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 06:51:18.349591 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 06:51:18.349854 skipped lava-vland-overlay
160 06:51:18.350151 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 06:51:18.350460 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 06:51:18.350731 skipped lava-multinode-overlay
163 06:51:18.351024 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 06:51:18.351327 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 06:51:18.351623 Loading test definitions
166 06:51:18.351957 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 06:51:18.352271 Using /lava-851280 at stage 0
168 06:51:18.353604 uuid=851280_1.5.2.4.1 testdef=None
169 06:51:18.353961 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 06:51:18.354286 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 06:51:18.356322 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 06:51:18.357283 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 06:51:18.359799 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 06:51:18.360849 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 06:51:18.363277 runner path: /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/0/tests/0_igt-gpu-panfrost test_uuid 851280_1.5.2.4.1
178 06:51:18.363918 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 06:51:18.364915 Creating lava-test-runner.conf files
181 06:51:18.365165 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/851280/lava-overlay-qo1i7160/lava-851280/0 for stage 0
182 06:51:18.365550 - 0_igt-gpu-panfrost
183 06:51:18.365962 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 06:51:18.366300 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 06:51:18.394067 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 06:51:18.394510 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 06:51:18.394832 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 06:51:18.395152 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 06:51:18.395470 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 06:51:25.117954 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 06:51:25.118654 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 06:51:25.119303 extracting modules file /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/851280/extract-overlay-ramdisk-0cye6iyf/ramdisk
193 06:51:26.534048 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 06:51:26.534532 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 06:51:26.534812 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851280/compress-overlay-6phiyrtb/overlay-1.5.2.5.tar.gz to ramdisk
196 06:51:26.535026 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851280/compress-overlay-6phiyrtb/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/851280/extract-overlay-ramdisk-0cye6iyf/ramdisk
197 06:51:26.565106 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 06:51:26.565486 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 06:51:26.565755 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 06:51:26.565981 Converting downloaded kernel to a uImage
201 06:51:26.566285 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/kernel/Image /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/kernel/uImage
202 06:51:27.052512 output: Image Name:
203 06:51:27.052924 output: Created: Thu Oct 17 06:51:26 2024
204 06:51:27.053134 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 06:51:27.053336 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 06:51:27.053537 output: Load Address: 01080000
207 06:51:27.053734 output: Entry Point: 01080000
208 06:51:27.053931 output:
209 06:51:27.054260 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 06:51:27.054527 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 06:51:27.054792 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 06:51:27.055041 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 06:51:27.055296 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 06:51:27.055548 Building ramdisk /var/lib/lava/dispatcher/tmp/851280/extract-overlay-ramdisk-0cye6iyf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/851280/extract-overlay-ramdisk-0cye6iyf/ramdisk
215 06:51:33.483485 >> 502360 blocks
216 06:51:54.066567 Adding RAMdisk u-boot header.
217 06:51:54.067223 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/851280/extract-overlay-ramdisk-0cye6iyf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/851280/extract-overlay-ramdisk-0cye6iyf/ramdisk.cpio.gz.uboot
218 06:51:54.750428 output: Image Name:
219 06:51:54.750847 output: Created: Thu Oct 17 06:51:54 2024
220 06:51:54.751308 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 06:51:54.751764 output: Data Size: 65707181 Bytes = 64167.17 KiB = 62.66 MiB
222 06:51:54.752278 output: Load Address: 00000000
223 06:51:54.752726 output: Entry Point: 00000000
224 06:51:54.753161 output:
225 06:51:54.754287 rename /var/lib/lava/dispatcher/tmp/851280/extract-overlay-ramdisk-0cye6iyf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/ramdisk/ramdisk.cpio.gz.uboot
226 06:51:54.755062 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 06:51:54.755659 end: 1.5 prepare-tftp-overlay (duration 00:00:36) [common]
228 06:51:54.756287 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 06:51:54.756791 No LXC device requested
230 06:51:54.757348 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 06:51:54.757915 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 06:51:54.758461 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 06:51:54.758912 Checking files for TFTP limit of 4294967296 bytes.
234 06:51:54.761820 end: 1 tftp-deploy (duration 00:00:40) [common]
235 06:51:54.762449 start: 2 uboot-action (timeout 00:05:00) [common]
236 06:51:54.763026 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 06:51:54.763579 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 06:51:54.764162 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 06:51:54.764746 Using kernel file from prepare-kernel: 851280/tftp-deploy-cbh5688c/kernel/uImage
240 06:51:54.765428 substitutions:
241 06:51:54.765879 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 06:51:54.766323 - {DTB_ADDR}: 0x01070000
243 06:51:54.766758 - {DTB}: 851280/tftp-deploy-cbh5688c/dtb/meson-g12b-a311d-libretech-cc.dtb
244 06:51:54.767195 - {INITRD}: 851280/tftp-deploy-cbh5688c/ramdisk/ramdisk.cpio.gz.uboot
245 06:51:54.767628 - {KERNEL_ADDR}: 0x01080000
246 06:51:54.768090 - {KERNEL}: 851280/tftp-deploy-cbh5688c/kernel/uImage
247 06:51:54.768533 - {LAVA_MAC}: None
248 06:51:54.769014 - {PRESEED_CONFIG}: None
249 06:51:54.769455 - {PRESEED_LOCAL}: None
250 06:51:54.769885 - {RAMDISK_ADDR}: 0x08000000
251 06:51:54.770313 - {RAMDISK}: 851280/tftp-deploy-cbh5688c/ramdisk/ramdisk.cpio.gz.uboot
252 06:51:54.770748 - {ROOT_PART}: None
253 06:51:54.771176 - {ROOT}: None
254 06:51:54.771604 - {SERVER_IP}: 192.168.6.2
255 06:51:54.772087 - {TEE_ADDR}: 0x83000000
256 06:51:54.772520 - {TEE}: None
257 06:51:54.772939 Parsed boot commands:
258 06:51:54.773345 - setenv autoload no
259 06:51:54.773763 - setenv initrd_high 0xffffffff
260 06:51:54.774181 - setenv fdt_high 0xffffffff
261 06:51:54.774594 - dhcp
262 06:51:54.775010 - setenv serverip 192.168.6.2
263 06:51:54.775424 - tftpboot 0x01080000 851280/tftp-deploy-cbh5688c/kernel/uImage
264 06:51:54.775840 - tftpboot 0x08000000 851280/tftp-deploy-cbh5688c/ramdisk/ramdisk.cpio.gz.uboot
265 06:51:54.776308 - tftpboot 0x01070000 851280/tftp-deploy-cbh5688c/dtb/meson-g12b-a311d-libretech-cc.dtb
266 06:51:54.776737 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 06:51:54.777176 - bootm 0x01080000 0x08000000 0x01070000
268 06:51:54.777723 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 06:51:54.779356 start: 2.3 connect-device (timeout 00:05:00) [common]
271 06:51:54.779846 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 06:51:54.795099 Setting prompt string to ['lava-test: # ']
273 06:51:54.796740 end: 2.3 connect-device (duration 00:00:00) [common]
274 06:51:54.797414 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 06:51:54.798029 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 06:51:54.798612 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 06:51:54.799865 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 06:51:54.837327 >> OK - accepted request
279 06:51:54.839532 Returned 0 in 0 seconds
280 06:51:54.940768 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 06:51:54.942485 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 06:51:54.943121 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 06:51:54.943684 Setting prompt string to ['Hit any key to stop autoboot']
285 06:51:54.944242 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 06:51:54.945963 Trying 192.168.56.21...
287 06:51:54.946485 Connected to conserv1.
288 06:51:54.946955 Escape character is '^]'.
289 06:51:54.947429
290 06:51:54.947907 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 06:51:54.948424
292 06:52:06.238628 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 06:52:06.239309 bl2_stage_init 0x81
294 06:52:06.244388 hw id: 0x0000 - pwm id 0x01
295 06:52:06.244956 bl2_stage_init 0xc1
296 06:52:06.245409 bl2_stage_init 0x02
297 06:52:06.245855
298 06:52:06.249830 L0:00000000
299 06:52:06.250311 L1:20000703
300 06:52:06.250741 L2:00008067
301 06:52:06.251162 L3:14000000
302 06:52:06.251595 B2:00402000
303 06:52:06.252707 B1:e0f83180
304 06:52:06.253168
305 06:52:06.253596 TE: 58150
306 06:52:06.254022
307 06:52:06.263867 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 06:52:06.264371
309 06:52:06.264802 Board ID = 1
310 06:52:06.265223 Set A53 clk to 24M
311 06:52:06.265640 Set A73 clk to 24M
312 06:52:06.269428 Set clk81 to 24M
313 06:52:06.269891 A53 clk: 1200 MHz
314 06:52:06.270316 A73 clk: 1200 MHz
315 06:52:06.275027 CLK81: 166.6M
316 06:52:06.275478 smccc: 00012aac
317 06:52:06.280559 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 06:52:06.281013 board id: 1
319 06:52:06.289297 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 06:52:06.299862 fw parse done
321 06:52:06.343935 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 06:52:06.348456 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 06:52:06.359364 PIEI prepare done
324 06:52:06.359813 fastboot data load
325 06:52:06.360284 fastboot data verify
326 06:52:06.364886 verify result: 266
327 06:52:06.370603 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 06:52:06.371065 LPDDR4 probe
329 06:52:06.371510 ddr clk to 1584MHz
330 06:52:06.415923 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 06:52:06.416432
332 06:52:06.416882 dmc_version 0001
333 06:52:06.422525 Check phy result
334 06:52:06.638487 INFO : End of CA training
335 06:52:06.638973 INFO : End of initialization
336 06:52:06.639425 INFO : Training has run successfully!
337 06:52:06.639864 Check phy result
338 06:52:06.640712 INFO : End of initialization
339 06:52:06.641176 INFO : End of read enable training
340 06:52:06.641620 INFO : End of fine write leveling
341 06:52:06.642058 INFO : End of Write leveling coarse delay
342 06:52:06.642491 INFO : Training has run successfully!
343 06:52:06.642923 Check phy result
344 06:52:06.643355 INFO : End of initialization
345 06:52:06.643784 INFO : End of read dq deskew training
346 06:52:06.644258 INFO : End of MPR read delay center optimization
347 06:52:06.644698 INFO : End of write delay center optimization
348 06:52:06.645128 INFO : End of read delay center optimization
349 06:52:06.645558 INFO : End of max read latency training
350 06:52:06.645992 INFO : Training has run successfully!
351 06:52:06.646419 1D training succeed
352 06:52:06.646858 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 06:52:06.647289 Check phy result
354 06:52:06.647717 INFO : End of initialization
355 06:52:06.648177 INFO : End of 2D read delay Voltage center optimization
356 06:52:06.648614 INFO : End of 2D read delay Voltage center optimization
357 06:52:06.649044 INFO : End of 2D write delay Voltage center optimization
358 06:52:06.679759 INFO : End of 2D write delay Voltage center optimization
359 06:52:06.685286 INFO : Training has run successfully!
360 06:52:06.685763
361 06:52:06.686217 channel==0
362 06:52:06.690903 RxClkDly_Margin_A0==88 ps 9
363 06:52:06.691387 TxDqDly_Margin_A0==98 ps 10
364 06:52:06.696488 RxClkDly_Margin_A1==88 ps 9
365 06:52:06.696951 TxDqDly_Margin_A1==98 ps 10
366 06:52:06.697393 TrainedVREFDQ_A0==74
367 06:52:06.702019 TrainedVREFDQ_A1==74
368 06:52:06.702483 VrefDac_Margin_A0==24
369 06:52:06.702922 DeviceVref_Margin_A0==40
370 06:52:06.707690 VrefDac_Margin_A1==25
371 06:52:06.708187 DeviceVref_Margin_A1==40
372 06:52:06.708661
373 06:52:06.709112
374 06:52:06.713425 channel==1
375 06:52:06.714014 RxClkDly_Margin_A0==98 ps 10
376 06:52:06.714475 TxDqDly_Margin_A0==98 ps 10
377 06:52:06.718938 RxClkDly_Margin_A1==98 ps 10
378 06:52:06.719482 TxDqDly_Margin_A1==88 ps 9
379 06:52:06.724515 TrainedVREFDQ_A0==77
380 06:52:06.725252 TrainedVREFDQ_A1==77
381 06:52:06.725914 VrefDac_Margin_A0==22
382 06:52:06.730001 DeviceVref_Margin_A0==37
383 06:52:06.730505 VrefDac_Margin_A1==22
384 06:52:06.741328 DeviceVref_Margin_A1==37
385 06:52:06.741801
386 06:52:06.742254 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 06:52:06.742703
388 06:52:06.769231 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000018 00000017 00000018 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
389 06:52:06.769776 2D training succeed
390 06:52:06.774802 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 06:52:06.780441 auto size-- 65535DDR cs0 size: 2048MB
392 06:52:06.780907 DDR cs1 size: 2048MB
393 06:52:06.785992 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 06:52:06.786458 cs0 DataBus test pass
395 06:52:06.791567 cs1 DataBus test pass
396 06:52:06.792093 cs0 AddrBus test pass
397 06:52:06.792545 cs1 AddrBus test pass
398 06:52:06.792982
399 06:52:06.797196 100bdlr_step_size ps== 420
400 06:52:06.797677 result report
401 06:52:06.802783 boot times 0Enable ddr reg access
402 06:52:06.808246 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 06:52:06.821767 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 06:52:07.395753 0.0;M3 CHK:0;cm4_sp_mode 0
405 06:52:07.396434 MVN_1=0x00000000
406 06:52:07.400980 MVN_2=0x00000000
407 06:52:07.406834 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 06:52:07.407313 OPS=0x10
409 06:52:07.407768 ring efuse init
410 06:52:07.408251 chipver efuse init
411 06:52:07.412408 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 06:52:07.417996 [0.018961 Inits done]
413 06:52:07.418485 secure task start!
414 06:52:07.418928 high task start!
415 06:52:07.422700 low task start!
416 06:52:07.423168 run into bl31
417 06:52:07.429261 NOTICE: BL31: v1.3(release):4fc40b1
418 06:52:07.437104 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 06:52:07.437579 NOTICE: BL31: G12A normal boot!
420 06:52:07.462394 NOTICE: BL31: BL33 decompress pass
421 06:52:07.468106 ERROR: Error initializing runtime service opteed_fast
422 06:52:08.701213
423 06:52:08.701847
424 06:52:08.709478 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 06:52:08.709998
426 06:52:08.710450 Model: Libre Computer AML-A311D-CC Alta
427 06:52:08.917981 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 06:52:08.941186 DRAM: 2 GiB (effective 3.8 GiB)
429 06:52:09.084298 Core: 408 devices, 31 uclasses, devicetree: separate
430 06:52:09.090035 WDT: Not starting watchdog@f0d0
431 06:52:09.122314 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 06:52:09.134866 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 06:52:09.139700 ** Bad device specification mmc 0 **
434 06:52:09.150070 Card did not respond to voltage select! : -110
435 06:52:09.157732 ** Bad device specification mmc 0 **
436 06:52:09.158200 Couldn't find partition mmc 0
437 06:52:09.165962 Card did not respond to voltage select! : -110
438 06:52:09.171475 ** Bad device specification mmc 0 **
439 06:52:09.171950 Couldn't find partition mmc 0
440 06:52:09.176655 Error: could not access storage.
441 06:52:10.439099 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
442 06:52:10.439636 bl2_stage_init 0x01
443 06:52:10.440151 bl2_stage_init 0x81
444 06:52:10.444713 hw id: 0x0000 - pwm id 0x01
445 06:52:10.445189 bl2_stage_init 0xc1
446 06:52:10.445635 bl2_stage_init 0x02
447 06:52:10.446073
448 06:52:10.450231 L0:00000000
449 06:52:10.450695 L1:20000703
450 06:52:10.451134 L2:00008067
451 06:52:10.451570 L3:14000000
452 06:52:10.455932 B2:00402000
453 06:52:10.456426 B1:e0f83180
454 06:52:10.456865
455 06:52:10.457300 TE: 58159
456 06:52:10.457736
457 06:52:10.461397 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 06:52:10.461866
459 06:52:10.462309 Board ID = 1
460 06:52:10.467052 Set A53 clk to 24M
461 06:52:10.467514 Set A73 clk to 24M
462 06:52:10.467958 Set clk81 to 24M
463 06:52:10.472611 A53 clk: 1200 MHz
464 06:52:10.473078 A73 clk: 1200 MHz
465 06:52:10.473520 CLK81: 166.6M
466 06:52:10.473950 smccc: 00012ab5
467 06:52:10.478224 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 06:52:10.483810 board id: 1
469 06:52:10.489729 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 06:52:10.500322 fw parse done
471 06:52:10.506354 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 06:52:10.754472 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 06:52:10.757975 PIEI prepare done
474 06:52:10.758439 fastboot data load
475 06:52:10.758883 fastboot data verify
476 06:52:10.759331 verify result: 266
477 06:52:10.759765 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 06:52:10.760262 LPDDR4 probe
479 06:52:10.760695 ddr clk to 1584MHz
480 06:52:10.761127 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 06:52:10.761559
482 06:52:10.761986 dmc_version 0001
483 06:52:10.762408 Check phy result
484 06:52:10.762831 INFO : End of CA training
485 06:52:10.763257 INFO : End of initialization
486 06:52:10.763688 INFO : Training has run successfully!
487 06:52:10.764143 Check phy result
488 06:52:10.764577 INFO : End of initialization
489 06:52:10.765011 INFO : End of read enable training
490 06:52:10.765440 INFO : End of fine write leveling
491 06:52:10.765868 INFO : End of Write leveling coarse delay
492 06:52:10.766297 INFO : Training has run successfully!
493 06:52:10.766724 Check phy result
494 06:52:10.767150 INFO : End of initialization
495 06:52:10.767578 INFO : End of read dq deskew training
496 06:52:10.768025 INFO : End of MPR read delay center optimization
497 06:52:10.768457 INFO : End of write delay center optimization
498 06:52:10.768884 INFO : End of read delay center optimization
499 06:52:10.769309 INFO : End of max read latency training
500 06:52:10.769735 INFO : Training has run successfully!
501 06:52:10.770160 1D training succeed
502 06:52:10.770594 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 06:52:10.771023 Check phy result
504 06:52:10.771448 INFO : End of initialization
505 06:52:10.771870 INFO : End of 2D read delay Voltage center optimization
506 06:52:10.778021 INFO : End of 2D read delay Voltage center optimization
507 06:52:10.830038 INFO : End of 2D write delay Voltage center optimization
508 06:52:10.879424 INFO : End of 2D write delay Voltage center optimization
509 06:52:10.885027 INFO : Training has run successfully!
510 06:52:10.885503
511 06:52:10.885951 channel==0
512 06:52:10.890576 RxClkDly_Margin_A0==88 ps 9
513 06:52:10.891065 TxDqDly_Margin_A0==98 ps 10
514 06:52:10.893960 RxClkDly_Margin_A1==88 ps 9
515 06:52:10.894420 TxDqDly_Margin_A1==98 ps 10
516 06:52:10.899426 TrainedVREFDQ_A0==74
517 06:52:10.899893 TrainedVREFDQ_A1==74
518 06:52:10.905013 VrefDac_Margin_A0==25
519 06:52:10.905475 DeviceVref_Margin_A0==40
520 06:52:10.905911 VrefDac_Margin_A1==25
521 06:52:10.910580 DeviceVref_Margin_A1==40
522 06:52:10.911042
523 06:52:10.911484
524 06:52:10.911920 channel==1
525 06:52:10.912385 RxClkDly_Margin_A0==98 ps 10
526 06:52:10.914194 TxDqDly_Margin_A0==88 ps 9
527 06:52:10.919736 RxClkDly_Margin_A1==98 ps 10
528 06:52:10.920230 TxDqDly_Margin_A1==88 ps 9
529 06:52:10.920672 TrainedVREFDQ_A0==76
530 06:52:10.925324 TrainedVREFDQ_A1==77
531 06:52:10.925788 VrefDac_Margin_A0==22
532 06:52:10.930934 DeviceVref_Margin_A0==38
533 06:52:10.931393 VrefDac_Margin_A1==24
534 06:52:10.931829 DeviceVref_Margin_A1==37
535 06:52:10.932293
536 06:52:10.940055 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 06:52:10.940527
538 06:52:10.968069 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
539 06:52:10.968565 2D training succeed
540 06:52:10.979000 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 06:52:10.979486 auto size-- 65535DDR cs0 size: 2048MB
542 06:52:10.979932 DDR cs1 size: 2048MB
543 06:52:10.984607 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 06:52:10.985076 cs0 DataBus test pass
545 06:52:10.990211 cs1 DataBus test pass
546 06:52:10.990647 cs0 AddrBus test pass
547 06:52:10.995835 cs1 AddrBus test pass
548 06:52:10.996295
549 06:52:10.996712 100bdlr_step_size ps== 420
550 06:52:10.997126 result report
551 06:52:11.001407 boot times 0Enable ddr reg access
552 06:52:11.007826 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 06:52:11.021302 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 06:52:11.594976 0.0;M3 CHK:0;cm4_sp_mode 0
555 06:52:11.595427 MVN_1=0x00000000
556 06:52:11.600547 MVN_2=0x00000000
557 06:52:11.606319 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 06:52:11.606820 OPS=0x10
559 06:52:11.607274 ring efuse init
560 06:52:11.607673 chipver efuse init
561 06:52:11.611999 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 06:52:11.617459 [0.018960 Inits done]
563 06:52:11.617881 secure task start!
564 06:52:11.618269 high task start!
565 06:52:11.622027 low task start!
566 06:52:11.622448 run into bl31
567 06:52:11.636659 NOTICE: BL31: v1.3(release):4fc40b1
568 06:52:11.637088 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 06:52:11.637482 NOTICE: BL31: G12A normal boot!
570 06:52:11.661972 NOTICE: BL31: BL33 decompress pass
571 06:52:11.667594 ERROR: Error initializing runtime service opteed_fast
572 06:52:12.900505
573 06:52:12.900950
574 06:52:12.908877 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 06:52:12.909320
576 06:52:12.909734 Model: Libre Computer AML-A311D-CC Alta
577 06:52:13.117341 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 06:52:13.140694 DRAM: 2 GiB (effective 3.8 GiB)
579 06:52:13.283641 Core: 408 devices, 31 uclasses, devicetree: separate
580 06:52:13.289545 WDT: Not starting watchdog@f0d0
581 06:52:13.321768 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 06:52:13.334274 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 06:52:13.339265 ** Bad device specification mmc 0 **
584 06:52:13.349579 Card did not respond to voltage select! : -110
585 06:52:13.357233 ** Bad device specification mmc 0 **
586 06:52:13.357676 Couldn't find partition mmc 0
587 06:52:13.365584 Card did not respond to voltage select! : -110
588 06:52:13.371181 ** Bad device specification mmc 0 **
589 06:52:13.371622 Couldn't find partition mmc 0
590 06:52:13.376145 Error: could not access storage.
591 06:52:13.718622 Net: eth0: ethernet@ff3f0000
592 06:52:13.719115 starting USB...
593 06:52:13.970426 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 06:52:13.970876 Starting the controller
595 06:52:13.977399 USB XHCI 1.10
596 06:52:15.693422 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 06:52:15.693988 bl2_stage_init 0x01
598 06:52:15.694420 bl2_stage_init 0x81
599 06:52:15.694835 hw id: 0x0000 - pwm id 0x01
600 06:52:15.695241 bl2_stage_init 0xc1
601 06:52:15.695643 bl2_stage_init 0x02
602 06:52:15.696097
603 06:52:15.698835 L0:00000000
604 06:52:15.699290 L1:20000703
605 06:52:15.699698 L2:00008067
606 06:52:15.700133 L3:14000000
607 06:52:15.704515 B2:00402000
608 06:52:15.704960 B1:e0f83180
609 06:52:15.705370
610 06:52:15.705770 TE: 58124
611 06:52:15.706167
612 06:52:15.710019 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 06:52:15.710469
614 06:52:15.710880 Board ID = 1
615 06:52:15.715628 Set A53 clk to 24M
616 06:52:15.716106 Set A73 clk to 24M
617 06:52:15.716520 Set clk81 to 24M
618 06:52:15.721228 A53 clk: 1200 MHz
619 06:52:15.721673 A73 clk: 1200 MHz
620 06:52:15.722086 CLK81: 166.6M
621 06:52:15.722483 smccc: 00012a91
622 06:52:15.726817 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 06:52:15.732497 board id: 1
624 06:52:15.738309 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 06:52:15.748943 fw parse done
626 06:52:15.754926 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 06:52:15.797582 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 06:52:15.808506 PIEI prepare done
629 06:52:15.808970 fastboot data load
630 06:52:15.809390 fastboot data verify
631 06:52:15.814053 verify result: 266
632 06:52:15.819646 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 06:52:15.820140 LPDDR4 probe
634 06:52:15.820561 ddr clk to 1584MHz
635 06:52:15.827629 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 06:52:15.864887
637 06:52:15.865335 dmc_version 0001
638 06:52:15.871579 Check phy result
639 06:52:15.877500 INFO : End of CA training
640 06:52:15.877951 INFO : End of initialization
641 06:52:15.883030 INFO : Training has run successfully!
642 06:52:15.883474 Check phy result
643 06:52:15.888688 INFO : End of initialization
644 06:52:15.889139 INFO : End of read enable training
645 06:52:15.894248 INFO : End of fine write leveling
646 06:52:15.899846 INFO : End of Write leveling coarse delay
647 06:52:15.900323 INFO : Training has run successfully!
648 06:52:15.900732 Check phy result
649 06:52:15.905511 INFO : End of initialization
650 06:52:15.905956 INFO : End of read dq deskew training
651 06:52:15.911030 INFO : End of MPR read delay center optimization
652 06:52:15.916639 INFO : End of write delay center optimization
653 06:52:15.922247 INFO : End of read delay center optimization
654 06:52:15.922695 INFO : End of max read latency training
655 06:52:15.927837 INFO : Training has run successfully!
656 06:52:15.928319 1D training succeed
657 06:52:15.937028 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 06:52:15.984797 Check phy result
659 06:52:15.985243 INFO : End of initialization
660 06:52:16.006539 INFO : End of 2D read delay Voltage center optimization
661 06:52:16.026816 INFO : End of 2D read delay Voltage center optimization
662 06:52:16.078919 INFO : End of 2D write delay Voltage center optimization
663 06:52:16.128098 INFO : End of 2D write delay Voltage center optimization
664 06:52:16.133654 INFO : Training has run successfully!
665 06:52:16.134090
666 06:52:16.134496 channel==0
667 06:52:16.139218 RxClkDly_Margin_A0==88 ps 9
668 06:52:16.139670 TxDqDly_Margin_A0==98 ps 10
669 06:52:16.144834 RxClkDly_Margin_A1==88 ps 9
670 06:52:16.145287 TxDqDly_Margin_A1==88 ps 9
671 06:52:16.145699 TrainedVREFDQ_A0==74
672 06:52:16.150462 TrainedVREFDQ_A1==74
673 06:52:16.150908 VrefDac_Margin_A0==25
674 06:52:16.151315 DeviceVref_Margin_A0==40
675 06:52:16.156081 VrefDac_Margin_A1==25
676 06:52:16.156528 DeviceVref_Margin_A1==40
677 06:52:16.156935
678 06:52:16.157337
679 06:52:16.157733 channel==1
680 06:52:16.161632 RxClkDly_Margin_A0==98 ps 10
681 06:52:16.162073 TxDqDly_Margin_A0==88 ps 9
682 06:52:16.167242 RxClkDly_Margin_A1==88 ps 9
683 06:52:16.167682 TxDqDly_Margin_A1==98 ps 10
684 06:52:16.172843 TrainedVREFDQ_A0==77
685 06:52:16.173288 TrainedVREFDQ_A1==77
686 06:52:16.173701 VrefDac_Margin_A0==22
687 06:52:16.178436 DeviceVref_Margin_A0==37
688 06:52:16.178942 VrefDac_Margin_A1==24
689 06:52:16.183969 DeviceVref_Margin_A1==37
690 06:52:16.184451
691 06:52:16.184864 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 06:52:16.185268
693 06:52:16.217610 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
694 06:52:16.218089 2D training succeed
695 06:52:16.223162 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 06:52:16.228739 auto size-- 65535DDR cs0 size: 2048MB
697 06:52:16.229189 DDR cs1 size: 2048MB
698 06:52:16.234354 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 06:52:16.234794 cs0 DataBus test pass
700 06:52:16.240023 cs1 DataBus test pass
701 06:52:16.240492 cs0 AddrBus test pass
702 06:52:16.240905 cs1 AddrBus test pass
703 06:52:16.241310
704 06:52:16.245594 100bdlr_step_size ps== 420
705 06:52:16.246059 result report
706 06:52:16.251147 boot times 0Enable ddr reg access
707 06:52:16.256436 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 06:52:16.269943 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 06:52:16.843704 0.0;M3 CHK:0;cm4_sp_mode 0
710 06:52:16.844272 MVN_1=0x00000000
711 06:52:16.849215 MVN_2=0x00000000
712 06:52:16.855080 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 06:52:16.855612 OPS=0x10
714 06:52:16.856045 ring efuse init
715 06:52:16.856438 chipver efuse init
716 06:52:16.860619 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 06:52:16.866244 [0.018961 Inits done]
718 06:52:16.866673 secure task start!
719 06:52:16.867057 high task start!
720 06:52:16.870918 low task start!
721 06:52:16.871340 run into bl31
722 06:52:16.885505 NOTICE: BL31: v1.3(release):4fc40b1
723 06:52:16.885941 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 06:52:16.886338 NOTICE: BL31: G12A normal boot!
725 06:52:16.910629 NOTICE: BL31: BL33 decompress pass
726 06:52:16.916322 ERROR: Error initializing runtime service opteed_fast
727 06:52:18.149132
728 06:52:18.149654
729 06:52:18.157537 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 06:52:18.157996
731 06:52:18.158412 Model: Libre Computer AML-A311D-CC Alta
732 06:52:18.366072 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 06:52:18.389319 DRAM: 2 GiB (effective 3.8 GiB)
734 06:52:18.532287 Core: 408 devices, 31 uclasses, devicetree: separate
735 06:52:18.538177 WDT: Not starting watchdog@f0d0
736 06:52:18.570424 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 06:52:18.582813 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 06:52:18.587876 ** Bad device specification mmc 0 **
739 06:52:18.598170 Card did not respond to voltage select! : -110
740 06:52:18.605846 ** Bad device specification mmc 0 **
741 06:52:18.606295 Couldn't find partition mmc 0
742 06:52:18.614167 Card did not respond to voltage select! : -110
743 06:52:18.619602 ** Bad device specification mmc 0 **
744 06:52:18.620078 Couldn't find partition mmc 0
745 06:52:18.624781 Error: could not access storage.
746 06:52:18.967289 Net: eth0: ethernet@ff3f0000
747 06:52:18.967779 starting USB...
748 06:52:19.219061 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 06:52:19.219529 Starting the controller
750 06:52:19.225992 USB XHCI 1.10
751 06:52:21.407737 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 06:52:21.408290 bl2_stage_init 0x01
753 06:52:21.408720 bl2_stage_init 0x81
754 06:52:21.413408 hw id: 0x0000 - pwm id 0x01
755 06:52:21.413870 bl2_stage_init 0xc1
756 06:52:21.414291 bl2_stage_init 0x02
757 06:52:21.414700
758 06:52:21.418995 L0:00000000
759 06:52:21.419446 L1:20000703
760 06:52:21.419855 L2:00008067
761 06:52:21.420353 L3:14000000
762 06:52:21.421928 B2:00402000
763 06:52:21.422382 B1:e0f83180
764 06:52:21.422787
765 06:52:21.423191 TE: 58159
766 06:52:21.423592
767 06:52:21.433078 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 06:52:21.433532
769 06:52:21.433945 Board ID = 1
770 06:52:21.434346 Set A53 clk to 24M
771 06:52:21.434741 Set A73 clk to 24M
772 06:52:21.438766 Set clk81 to 24M
773 06:52:21.439209 A53 clk: 1200 MHz
774 06:52:21.439620 A73 clk: 1200 MHz
775 06:52:21.449919 CLK81: 166.6M
776 06:52:21.450363 smccc: 00012ab5
777 06:52:21.450768 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 06:52:21.451173 board id: 1
779 06:52:21.458417 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 06:52:21.469016 fw parse done
781 06:52:21.474998 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 06:52:21.517649 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 06:52:21.528556 PIEI prepare done
784 06:52:21.528998 fastboot data load
785 06:52:21.529410 fastboot data verify
786 06:52:21.534105 verify result: 266
787 06:52:21.539714 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 06:52:21.540209 LPDDR4 probe
789 06:52:21.540626 ddr clk to 1584MHz
790 06:52:21.547733 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 06:52:21.583953
792 06:52:21.584432 dmc_version 0001
793 06:52:21.591649 Check phy result
794 06:52:21.603244 INFO : End of CA training
795 06:52:21.603682 INFO : End of initialization
796 06:52:21.604131 INFO : Training has run successfully!
797 06:52:21.604542 Check phy result
798 06:52:21.608712 INFO : End of initialization
799 06:52:21.609163 INFO : End of read enable training
800 06:52:21.612012 INFO : End of fine write leveling
801 06:52:21.623291 INFO : End of Write leveling coarse delay
802 06:52:21.623796 INFO : Training has run successfully!
803 06:52:21.624256 Check phy result
804 06:52:21.624671 INFO : End of initialization
805 06:52:21.628789 INFO : End of read dq deskew training
806 06:52:21.634536 INFO : End of MPR read delay center optimization
807 06:52:21.635020 INFO : End of write delay center optimization
808 06:52:21.640070 INFO : End of read delay center optimization
809 06:52:21.645608 INFO : End of max read latency training
810 06:52:21.646060 INFO : Training has run successfully!
811 06:52:21.651185 1D training succeed
812 06:52:21.657142 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 06:52:21.704795 Check phy result
814 06:52:21.705282 INFO : End of initialization
815 06:52:21.726542 INFO : End of 2D read delay Voltage center optimization
816 06:52:21.746740 INFO : End of 2D read delay Voltage center optimization
817 06:52:21.798829 INFO : End of 2D write delay Voltage center optimization
818 06:52:21.848323 INFO : End of 2D write delay Voltage center optimization
819 06:52:21.853773 INFO : Training has run successfully!
820 06:52:21.854304
821 06:52:21.854708 channel==0
822 06:52:21.859397 RxClkDly_Margin_A0==88 ps 9
823 06:52:21.859854 TxDqDly_Margin_A0==98 ps 10
824 06:52:21.864883 RxClkDly_Margin_A1==88 ps 9
825 06:52:21.865348 TxDqDly_Margin_A1==98 ps 10
826 06:52:21.865752 TrainedVREFDQ_A0==74
827 06:52:21.870579 TrainedVREFDQ_A1==74
828 06:52:21.871056 VrefDac_Margin_A0==25
829 06:52:21.871449 DeviceVref_Margin_A0==40
830 06:52:21.876074 VrefDac_Margin_A1==25
831 06:52:21.876533 DeviceVref_Margin_A1==40
832 06:52:21.876923
833 06:52:21.877309
834 06:52:21.881751 channel==1
835 06:52:21.882185 RxClkDly_Margin_A0==98 ps 10
836 06:52:21.882573 TxDqDly_Margin_A0==98 ps 10
837 06:52:21.887333 RxClkDly_Margin_A1==98 ps 10
838 06:52:21.887766 TxDqDly_Margin_A1==88 ps 9
839 06:52:21.892851 TrainedVREFDQ_A0==77
840 06:52:21.893288 TrainedVREFDQ_A1==77
841 06:52:21.893677 VrefDac_Margin_A0==22
842 06:52:21.898483 DeviceVref_Margin_A0==37
843 06:52:21.898915 VrefDac_Margin_A1==22
844 06:52:21.904093 DeviceVref_Margin_A1==37
845 06:52:21.904521
846 06:52:21.904910 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 06:52:21.909750
848 06:52:21.937750 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
849 06:52:21.938215 2D training succeed
850 06:52:21.943300 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 06:52:21.948942 auto size-- 65535DDR cs0 size: 2048MB
852 06:52:21.949378 DDR cs1 size: 2048MB
853 06:52:21.954423 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 06:52:21.954898 cs0 DataBus test pass
855 06:52:21.960037 cs1 DataBus test pass
856 06:52:21.960480 cs0 AddrBus test pass
857 06:52:21.960866 cs1 AddrBus test pass
858 06:52:21.961245
859 06:52:21.965602 100bdlr_step_size ps== 420
860 06:52:21.966039 result report
861 06:52:21.971202 boot times 0Enable ddr reg access
862 06:52:21.976647 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 06:52:21.990125 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 06:52:22.563734 0.0;M3 CHK:0;cm4_sp_mode 0
865 06:52:22.564289 MVN_1=0x00000000
866 06:52:22.569215 MVN_2=0x00000000
867 06:52:22.575013 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 06:52:22.575467 OPS=0x10
869 06:52:22.575881 ring efuse init
870 06:52:22.576333 chipver efuse init
871 06:52:22.580590 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 06:52:22.586176 [0.018960 Inits done]
873 06:52:22.586624 secure task start!
874 06:52:22.587035 high task start!
875 06:52:22.590770 low task start!
876 06:52:22.591215 run into bl31
877 06:52:22.597429 NOTICE: BL31: v1.3(release):4fc40b1
878 06:52:22.605249 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 06:52:22.605706 NOTICE: BL31: G12A normal boot!
880 06:52:22.630554 NOTICE: BL31: BL33 decompress pass
881 06:52:22.636267 ERROR: Error initializing runtime service opteed_fast
882 06:52:23.869170
883 06:52:23.869666
884 06:52:23.877649 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 06:52:23.878103
886 06:52:23.878518 Model: Libre Computer AML-A311D-CC Alta
887 06:52:24.085978 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 06:52:24.109407 DRAM: 2 GiB (effective 3.8 GiB)
889 06:52:24.252417 Core: 408 devices, 31 uclasses, devicetree: separate
890 06:52:24.258273 WDT: Not starting watchdog@f0d0
891 06:52:24.290517 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 06:52:24.302982 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 06:52:24.307961 ** Bad device specification mmc 0 **
894 06:52:24.318318 Card did not respond to voltage select! : -110
895 06:52:24.325947 ** Bad device specification mmc 0 **
896 06:52:24.326428 Couldn't find partition mmc 0
897 06:52:24.334299 Card did not respond to voltage select! : -110
898 06:52:24.339806 ** Bad device specification mmc 0 **
899 06:52:24.340311 Couldn't find partition mmc 0
900 06:52:24.344868 Error: could not access storage.
901 06:52:24.688360 Net: eth0: ethernet@ff3f0000
902 06:52:24.688840 starting USB...
903 06:52:24.940169 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 06:52:24.940624 Starting the controller
905 06:52:25.154422 USB XHCI 1.10
906 06:52:26.501086 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 06:52:26.509338 scanning usb for storage devices... 0 Storage Device(s) found
909 06:52:26.560861 Hit any key to stop autoboot: 1
910 06:52:26.561646 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 06:52:26.562250 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 06:52:26.562742 Setting prompt string to ['=>']
913 06:52:26.563232 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 06:52:26.576771 0
915 06:52:26.577662 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 06:52:26.578170 Sending with 10 millisecond of delay
918 06:52:27.712611 => setenv autoload no
919 06:52:27.723323 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 06:52:27.728244 setenv autoload no
921 06:52:27.728986 Sending with 10 millisecond of delay
923 06:52:29.525368 => setenv initrd_high 0xffffffff
924 06:52:29.536034 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 06:52:29.536836 setenv initrd_high 0xffffffff
926 06:52:29.537557 Sending with 10 millisecond of delay
928 06:52:31.153369 => setenv fdt_high 0xffffffff
929 06:52:31.164035 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
930 06:52:31.164801 setenv fdt_high 0xffffffff
931 06:52:31.165514 Sending with 10 millisecond of delay
933 06:52:31.457241 => dhcp
934 06:52:31.467845 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 06:52:31.468652 dhcp
936 06:52:31.469095 Speed: 1000, full duplex
937 06:52:31.469504 BOOTP broadcast 1
938 06:52:31.506631 DHCP client bound to address 192.168.6.244 (38 ms)
939 06:52:31.507320 Sending with 10 millisecond of delay
941 06:52:33.183401 => setenv serverip 192.168.6.2
942 06:52:33.194087 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
943 06:52:33.194939 setenv serverip 192.168.6.2
944 06:52:33.195618 Sending with 10 millisecond of delay
946 06:52:36.918060 => tftpboot 0x01080000 851280/tftp-deploy-cbh5688c/kernel/uImage
947 06:52:36.928826 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
948 06:52:36.929634 tftpboot 0x01080000 851280/tftp-deploy-cbh5688c/kernel/uImage
949 06:52:36.930087 Speed: 1000, full duplex
950 06:52:36.930501 Using ethernet@ff3f0000 device
951 06:52:36.931603 TFTP from server 192.168.6.2; our IP address is 192.168.6.244
952 06:52:36.937107 Filename '851280/tftp-deploy-cbh5688c/kernel/uImage'.
953 06:52:36.941023 Load address: 0x1080000
954 06:53:08.986245 Loading: *T T T T T T UDP wrong checksum 000000ff 0000f8bb
955 06:53:09.016067 UDP wrong checksum 000000ff 000086ae
956 06:53:31.984062 T T T T
957 06:53:31.984681 Retry count exceeded; starting again
959 06:53:31.986071 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
962 06:53:31.987937 end: 2.4 uboot-commands (duration 00:01:37) [common]
964 06:53:31.989371 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
966 06:53:31.990357 end: 2 uboot-action (duration 00:01:37) [common]
968 06:53:31.991808 Cleaning after the job
969 06:53:31.992383 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/ramdisk
970 06:53:32.027084 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/kernel
971 06:53:32.044390 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/dtb
972 06:53:32.045079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851280/tftp-deploy-cbh5688c/modules
973 06:53:32.064668 start: 4.1 power-off (timeout 00:00:30) [common]
974 06:53:32.065296 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
975 06:53:32.097182 >> OK - accepted request
976 06:53:32.099203 Returned 0 in 0 seconds
977 06:53:32.199870 end: 4.1 power-off (duration 00:00:00) [common]
979 06:53:32.200766 start: 4.2 read-feedback (timeout 00:10:00) [common]
980 06:53:32.201411 Listened to connection for namespace 'common' for up to 1s
981 06:53:33.202320 Finalising connection for namespace 'common'
982 06:53:33.202954 Disconnecting from shell: Finalise
983 06:53:33.203467 =>
984 06:53:33.304349 end: 4.2 read-feedback (duration 00:00:01) [common]
985 06:53:33.304915 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/851280
986 06:53:33.902335 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/851280
987 06:53:33.902950 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.