Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 8
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 18:08:02.364438 lava-dispatcher, installed at version: 2024.01
2 18:08:02.365213 start: 0 validate
3 18:08:02.365690 Start time: 2024-11-05 18:08:02.365660+00:00 (UTC)
4 18:08:02.366238 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 18:08:02.366788 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:08:02.404677 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 18:08:02.405208 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-49-g76c6217c31266%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 18:08:02.434504 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 18:08:02.435156 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-49-g76c6217c31266%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 18:08:02.464266 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 18:08:02.464957 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:08:02.500870 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 18:08:02.501365 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fib-mfd-gpio-i2c-watchdog-v6.13-49-g76c6217c31266%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 18:08:02.538293 validate duration: 0.17
16 18:08:02.539117 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:08:02.539425 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:08:02.539723 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:08:02.540312 Not decompressing ramdisk as can be used compressed.
20 18:08:02.540757 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 18:08:02.541030 saving as /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/ramdisk/initrd.cpio.gz
22 18:08:02.541295 total size: 5628169 (5 MB)
23 18:08:02.577546 progress 0 % (0 MB)
24 18:08:02.583107 progress 5 % (0 MB)
25 18:08:02.588874 progress 10 % (0 MB)
26 18:08:02.594014 progress 15 % (0 MB)
27 18:08:02.599549 progress 20 % (1 MB)
28 18:08:02.604370 progress 25 % (1 MB)
29 18:08:02.609637 progress 30 % (1 MB)
30 18:08:02.615007 progress 35 % (1 MB)
31 18:08:02.619898 progress 40 % (2 MB)
32 18:08:02.625366 progress 45 % (2 MB)
33 18:08:02.630176 progress 50 % (2 MB)
34 18:08:02.635585 progress 55 % (2 MB)
35 18:08:02.641103 progress 60 % (3 MB)
36 18:08:02.646221 progress 65 % (3 MB)
37 18:08:02.652169 progress 70 % (3 MB)
38 18:08:02.657032 progress 75 % (4 MB)
39 18:08:02.662324 progress 80 % (4 MB)
40 18:08:02.667013 progress 85 % (4 MB)
41 18:08:02.672284 progress 90 % (4 MB)
42 18:08:02.677642 progress 95 % (5 MB)
43 18:08:02.681946 progress 100 % (5 MB)
44 18:08:02.682843 5 MB downloaded in 0.14 s (37.93 MB/s)
45 18:08:02.683546 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:08:02.684818 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:08:02.685225 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:08:02.685599 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:08:02.686183 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-49-g76c6217c31266/arm64/defconfig/gcc-12/kernel/Image
51 18:08:02.686553 saving as /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/kernel/Image
52 18:08:02.686839 total size: 45713920 (43 MB)
53 18:08:02.687141 No compression specified
54 18:08:02.724308 progress 0 % (0 MB)
55 18:08:02.759636 progress 5 % (2 MB)
56 18:08:02.794783 progress 10 % (4 MB)
57 18:08:02.830472 progress 15 % (6 MB)
58 18:08:02.866517 progress 20 % (8 MB)
59 18:08:02.901754 progress 25 % (10 MB)
60 18:08:02.936849 progress 30 % (13 MB)
61 18:08:02.972202 progress 35 % (15 MB)
62 18:08:03.007814 progress 40 % (17 MB)
63 18:08:03.042699 progress 45 % (19 MB)
64 18:08:03.077857 progress 50 % (21 MB)
65 18:08:03.113159 progress 55 % (24 MB)
66 18:08:03.148085 progress 60 % (26 MB)
67 18:08:03.182894 progress 65 % (28 MB)
68 18:08:03.218185 progress 70 % (30 MB)
69 18:08:03.253690 progress 75 % (32 MB)
70 18:08:03.289103 progress 80 % (34 MB)
71 18:08:03.323905 progress 85 % (37 MB)
72 18:08:03.359370 progress 90 % (39 MB)
73 18:08:03.395237 progress 95 % (41 MB)
74 18:08:03.428631 progress 100 % (43 MB)
75 18:08:03.429281 43 MB downloaded in 0.74 s (58.72 MB/s)
76 18:08:03.429905 end: 1.2.1 http-download (duration 00:00:01) [common]
78 18:08:03.430931 end: 1.2 download-retry (duration 00:00:01) [common]
79 18:08:03.431284 start: 1.3 download-retry (timeout 00:09:59) [common]
80 18:08:03.431621 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 18:08:03.432266 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-49-g76c6217c31266/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 18:08:03.432624 saving as /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/dtb/meson-g12b-a311d-libretech-cc.dtb
83 18:08:03.432902 total size: 54703 (0 MB)
84 18:08:03.433179 No compression specified
85 18:08:03.470505 progress 59 % (0 MB)
86 18:08:03.471622 progress 100 % (0 MB)
87 18:08:03.472439 0 MB downloaded in 0.04 s (1.32 MB/s)
88 18:08:03.473119 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:08:03.474274 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:08:03.474670 start: 1.4 download-retry (timeout 00:09:59) [common]
92 18:08:03.475070 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 18:08:03.475724 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 18:08:03.476099 saving as /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/nfsrootfs/full.rootfs.tar
95 18:08:03.476430 total size: 120894716 (115 MB)
96 18:08:03.476728 Using unxz to decompress xz
97 18:08:03.511739 progress 0 % (0 MB)
98 18:08:04.303837 progress 5 % (5 MB)
99 18:08:05.141807 progress 10 % (11 MB)
100 18:08:05.938198 progress 15 % (17 MB)
101 18:08:06.677327 progress 20 % (23 MB)
102 18:08:07.269584 progress 25 % (28 MB)
103 18:08:08.098045 progress 30 % (34 MB)
104 18:08:08.890712 progress 35 % (40 MB)
105 18:08:09.258459 progress 40 % (46 MB)
106 18:08:09.632533 progress 45 % (51 MB)
107 18:08:10.358810 progress 50 % (57 MB)
108 18:08:11.348044 progress 55 % (63 MB)
109 18:08:12.158319 progress 60 % (69 MB)
110 18:08:12.924091 progress 65 % (74 MB)
111 18:08:13.705742 progress 70 % (80 MB)
112 18:08:14.536233 progress 75 % (86 MB)
113 18:08:15.330823 progress 80 % (92 MB)
114 18:08:16.113633 progress 85 % (98 MB)
115 18:08:17.033471 progress 90 % (103 MB)
116 18:08:17.810775 progress 95 % (109 MB)
117 18:08:18.637215 progress 100 % (115 MB)
118 18:08:18.649630 115 MB downloaded in 15.17 s (7.60 MB/s)
119 18:08:18.650501 end: 1.4.1 http-download (duration 00:00:15) [common]
121 18:08:18.652141 end: 1.4 download-retry (duration 00:00:15) [common]
122 18:08:18.652660 start: 1.5 download-retry (timeout 00:09:44) [common]
123 18:08:18.653166 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 18:08:18.653966 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-49-g76c6217c31266/arm64/defconfig/gcc-12/modules.tar.xz
125 18:08:18.654440 saving as /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/modules/modules.tar
126 18:08:18.654844 total size: 11605788 (11 MB)
127 18:08:18.655261 Using unxz to decompress xz
128 18:08:18.697211 progress 0 % (0 MB)
129 18:08:18.763596 progress 5 % (0 MB)
130 18:08:18.837217 progress 10 % (1 MB)
131 18:08:18.932348 progress 15 % (1 MB)
132 18:08:19.024346 progress 20 % (2 MB)
133 18:08:19.103404 progress 25 % (2 MB)
134 18:08:19.180344 progress 30 % (3 MB)
135 18:08:19.256560 progress 35 % (3 MB)
136 18:08:19.333850 progress 40 % (4 MB)
137 18:08:19.410363 progress 45 % (5 MB)
138 18:08:19.494163 progress 50 % (5 MB)
139 18:08:19.570700 progress 55 % (6 MB)
140 18:08:19.655122 progress 60 % (6 MB)
141 18:08:19.735337 progress 65 % (7 MB)
142 18:08:19.811147 progress 70 % (7 MB)
143 18:08:19.892938 progress 75 % (8 MB)
144 18:08:19.975454 progress 80 % (8 MB)
145 18:08:20.054457 progress 85 % (9 MB)
146 18:08:20.132060 progress 90 % (9 MB)
147 18:08:20.208809 progress 95 % (10 MB)
148 18:08:20.285078 progress 100 % (11 MB)
149 18:08:20.295781 11 MB downloaded in 1.64 s (6.75 MB/s)
150 18:08:20.296755 end: 1.5.1 http-download (duration 00:00:02) [common]
152 18:08:20.298426 end: 1.5 download-retry (duration 00:00:02) [common]
153 18:08:20.298963 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 18:08:20.299497 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 18:08:37.472418 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/941220/extract-nfsrootfs-61pgpkhz
156 18:08:37.473032 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 18:08:37.473315 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 18:08:37.474013 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux
159 18:08:37.474515 makedir: /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin
160 18:08:37.474860 makedir: /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/tests
161 18:08:37.475175 makedir: /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/results
162 18:08:37.475508 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-add-keys
163 18:08:37.476089 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-add-sources
164 18:08:37.476623 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-background-process-start
165 18:08:37.477136 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-background-process-stop
166 18:08:37.477663 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-common-functions
167 18:08:37.478166 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-echo-ipv4
168 18:08:37.478654 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-install-packages
169 18:08:37.479130 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-installed-packages
170 18:08:37.479639 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-os-build
171 18:08:37.480152 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-probe-channel
172 18:08:37.480638 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-probe-ip
173 18:08:37.481107 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-target-ip
174 18:08:37.481572 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-target-mac
175 18:08:37.482039 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-target-storage
176 18:08:37.482516 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-test-case
177 18:08:37.482989 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-test-event
178 18:08:37.483454 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-test-feedback
179 18:08:37.484019 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-test-raise
180 18:08:37.484522 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-test-reference
181 18:08:37.485001 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-test-runner
182 18:08:37.485480 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-test-set
183 18:08:37.485957 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-test-shell
184 18:08:37.486455 Updating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-add-keys (debian)
185 18:08:37.487010 Updating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-add-sources (debian)
186 18:08:37.487527 Updating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-install-packages (debian)
187 18:08:37.488064 Updating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-installed-packages (debian)
188 18:08:37.488593 Updating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/bin/lava-os-build (debian)
189 18:08:37.489037 Creating /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/environment
190 18:08:37.489422 LAVA metadata
191 18:08:37.489685 - LAVA_JOB_ID=941220
192 18:08:37.489899 - LAVA_DISPATCHER_IP=192.168.6.2
193 18:08:37.490269 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 18:08:37.491248 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 18:08:37.491571 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 18:08:37.491776 skipped lava-vland-overlay
197 18:08:37.492048 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 18:08:37.492311 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 18:08:37.492532 skipped lava-multinode-overlay
200 18:08:37.492772 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 18:08:37.493021 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 18:08:37.493268 Loading test definitions
203 18:08:37.493542 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 18:08:37.493759 Using /lava-941220 at stage 0
205 18:08:37.494848 uuid=941220_1.6.2.4.1 testdef=None
206 18:08:37.495155 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 18:08:37.495412 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 18:08:37.497096 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 18:08:37.497911 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 18:08:37.499862 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 18:08:37.500720 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 18:08:37.502547 runner path: /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/0/tests/0_timesync-off test_uuid 941220_1.6.2.4.1
215 18:08:37.503106 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 18:08:37.503919 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 18:08:37.504219 Using /lava-941220 at stage 0
219 18:08:37.504581 Fetching tests from https://github.com/kernelci/test-definitions.git
220 18:08:37.504875 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/0/tests/1_kselftest-alsa'
221 18:08:40.895817 Running '/usr/bin/git checkout kernelci.org
222 18:08:41.342507 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 18:08:41.345062 uuid=941220_1.6.2.4.5 testdef=None
224 18:08:41.345736 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 18:08:41.347356 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 18:08:41.353322 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 18:08:41.355078 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 18:08:41.362993 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 18:08:41.364876 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 18:08:41.372682 runner path: /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/0/tests/1_kselftest-alsa test_uuid 941220_1.6.2.4.5
234 18:08:41.373271 BOARD='meson-g12b-a311d-libretech-cc'
235 18:08:41.373744 BRANCH='lee-mfd'
236 18:08:41.374191 SKIPFILE='/dev/null'
237 18:08:41.374637 SKIP_INSTALL='True'
238 18:08:41.375080 TESTPROG_URL='http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-49-g76c6217c31266/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 18:08:41.375537 TST_CASENAME=''
240 18:08:41.375975 TST_CMDFILES='alsa'
241 18:08:41.377122 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 18:08:41.378820 Creating lava-test-runner.conf files
244 18:08:41.379273 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/941220/lava-overlay-ezhp4qux/lava-941220/0 for stage 0
245 18:08:41.380031 - 0_timesync-off
246 18:08:41.380547 - 1_kselftest-alsa
247 18:08:41.381257 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 18:08:41.381865 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 18:09:04.700133 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 18:09:04.700596 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 18:09:04.700898 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 18:09:04.701218 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 18:09:04.701517 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 18:09:05.374420 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 18:09:05.374920 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 18:09:05.375210 extracting modules file /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/modules/modules.tar to /var/lib/lava/dispatcher/tmp/941220/extract-nfsrootfs-61pgpkhz
257 18:09:06.781474 extracting modules file /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/modules/modules.tar to /var/lib/lava/dispatcher/tmp/941220/extract-overlay-ramdisk-8o0nlipj/ramdisk
258 18:09:08.222855 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 18:09:08.223348 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 18:09:08.223651 [common] Applying overlay to NFS
261 18:09:08.223882 [common] Applying overlay /var/lib/lava/dispatcher/tmp/941220/compress-overlay-9g55r37h/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/941220/extract-nfsrootfs-61pgpkhz
262 18:09:11.004837 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 18:09:11.005344 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 18:09:11.005659 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 18:09:11.005933 Converting downloaded kernel to a uImage
266 18:09:11.006269 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/kernel/Image /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/kernel/uImage
267 18:09:11.479347 output: Image Name:
268 18:09:11.479774 output: Created: Tue Nov 5 18:09:11 2024
269 18:09:11.480032 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 18:09:11.480260 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 18:09:11.480469 output: Load Address: 01080000
272 18:09:11.480678 output: Entry Point: 01080000
273 18:09:11.480884 output:
274 18:09:11.481220 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 18:09:11.481500 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 18:09:11.481779 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 18:09:11.482045 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 18:09:11.482330 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 18:09:11.482606 Building ramdisk /var/lib/lava/dispatcher/tmp/941220/extract-overlay-ramdisk-8o0nlipj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/941220/extract-overlay-ramdisk-8o0nlipj/ramdisk
280 18:09:13.739405 >> 166772 blocks
281 18:09:21.469764 Adding RAMdisk u-boot header.
282 18:09:21.470281 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/941220/extract-overlay-ramdisk-8o0nlipj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/941220/extract-overlay-ramdisk-8o0nlipj/ramdisk.cpio.gz.uboot
283 18:09:21.722882 output: Image Name:
284 18:09:21.723311 output: Created: Tue Nov 5 18:09:21 2024
285 18:09:21.723522 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 18:09:21.723726 output: Data Size: 23427518 Bytes = 22878.44 KiB = 22.34 MiB
287 18:09:21.723928 output: Load Address: 00000000
288 18:09:21.724366 output: Entry Point: 00000000
289 18:09:21.724774 output:
290 18:09:21.725816 rename /var/lib/lava/dispatcher/tmp/941220/extract-overlay-ramdisk-8o0nlipj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/ramdisk/ramdisk.cpio.gz.uboot
291 18:09:21.726529 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 18:09:21.727073 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 18:09:21.727595 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 18:09:21.728079 No LXC device requested
295 18:09:21.728585 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 18:09:21.729091 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 18:09:21.729579 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 18:09:21.729988 Checking files for TFTP limit of 4294967296 bytes.
299 18:09:21.732692 end: 1 tftp-deploy (duration 00:01:19) [common]
300 18:09:21.733268 start: 2 uboot-action (timeout 00:05:00) [common]
301 18:09:21.733788 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 18:09:21.734280 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 18:09:21.734779 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 18:09:21.735302 Using kernel file from prepare-kernel: 941220/tftp-deploy-3kekei07/kernel/uImage
305 18:09:21.735924 substitutions:
306 18:09:21.736370 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 18:09:21.736776 - {DTB_ADDR}: 0x01070000
308 18:09:21.737182 - {DTB}: 941220/tftp-deploy-3kekei07/dtb/meson-g12b-a311d-libretech-cc.dtb
309 18:09:21.737585 - {INITRD}: 941220/tftp-deploy-3kekei07/ramdisk/ramdisk.cpio.gz.uboot
310 18:09:21.737984 - {KERNEL_ADDR}: 0x01080000
311 18:09:21.738376 - {KERNEL}: 941220/tftp-deploy-3kekei07/kernel/uImage
312 18:09:21.738770 - {LAVA_MAC}: None
313 18:09:21.739203 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/941220/extract-nfsrootfs-61pgpkhz
314 18:09:21.739600 - {NFS_SERVER_IP}: 192.168.6.2
315 18:09:21.740025 - {PRESEED_CONFIG}: None
316 18:09:21.740441 - {PRESEED_LOCAL}: None
317 18:09:21.740831 - {RAMDISK_ADDR}: 0x08000000
318 18:09:21.741219 - {RAMDISK}: 941220/tftp-deploy-3kekei07/ramdisk/ramdisk.cpio.gz.uboot
319 18:09:21.741609 - {ROOT_PART}: None
320 18:09:21.741996 - {ROOT}: None
321 18:09:21.742383 - {SERVER_IP}: 192.168.6.2
322 18:09:21.742768 - {TEE_ADDR}: 0x83000000
323 18:09:21.743153 - {TEE}: None
324 18:09:21.743537 Parsed boot commands:
325 18:09:21.743913 - setenv autoload no
326 18:09:21.744325 - setenv initrd_high 0xffffffff
327 18:09:21.744709 - setenv fdt_high 0xffffffff
328 18:09:21.745096 - dhcp
329 18:09:21.745478 - setenv serverip 192.168.6.2
330 18:09:21.745865 - tftpboot 0x01080000 941220/tftp-deploy-3kekei07/kernel/uImage
331 18:09:21.746255 - tftpboot 0x08000000 941220/tftp-deploy-3kekei07/ramdisk/ramdisk.cpio.gz.uboot
332 18:09:21.746643 - tftpboot 0x01070000 941220/tftp-deploy-3kekei07/dtb/meson-g12b-a311d-libretech-cc.dtb
333 18:09:21.747031 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/941220/extract-nfsrootfs-61pgpkhz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 18:09:21.747427 - bootm 0x01080000 0x08000000 0x01070000
335 18:09:21.747930 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 18:09:21.749493 start: 2.3 connect-device (timeout 00:05:00) [common]
338 18:09:21.749911 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 18:09:21.765100 Setting prompt string to ['lava-test: # ']
340 18:09:21.766646 end: 2.3 connect-device (duration 00:00:00) [common]
341 18:09:21.767254 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 18:09:21.767816 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 18:09:21.768377 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 18:09:21.769525 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 18:09:21.806697 >> OK - accepted request
346 18:09:21.808855 Returned 0 in 0 seconds
347 18:09:21.909951 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 18:09:21.911550 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 18:09:21.912149 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 18:09:21.912675 Setting prompt string to ['Hit any key to stop autoboot']
352 18:09:21.913126 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 18:09:21.914685 Trying 192.168.56.21...
354 18:09:21.915163 Connected to conserv1.
355 18:09:21.915565 Escape character is '^]'.
356 18:09:21.916007
357 18:09:21.916428 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 18:09:21.916869
359 18:09:33.287164 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 18:09:33.287815 bl2_stage_init 0x01
361 18:09:33.288305 bl2_stage_init 0x81
362 18:09:33.292548 hw id: 0x0000 - pwm id 0x01
363 18:09:33.293093 bl2_stage_init 0xc1
364 18:09:33.293491 bl2_stage_init 0x02
365 18:09:33.293882
366 18:09:33.298119 L0:00000000
367 18:09:33.298616 L1:20000703
368 18:09:33.299015 L2:00008067
369 18:09:33.299417 L3:14000000
370 18:09:33.301031 B2:00402000
371 18:09:33.301473 B1:e0f83180
372 18:09:33.301866
373 18:09:33.302258 TE: 58167
374 18:09:33.302648
375 18:09:33.312183 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 18:09:33.312639
377 18:09:33.313033 Board ID = 1
378 18:09:33.313419 Set A53 clk to 24M
379 18:09:33.313802 Set A73 clk to 24M
380 18:09:33.317725 Set clk81 to 24M
381 18:09:33.318150 A53 clk: 1200 MHz
382 18:09:33.318543 A73 clk: 1200 MHz
383 18:09:33.321237 CLK81: 166.6M
384 18:09:33.321672 smccc: 00012abd
385 18:09:33.326752 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 18:09:33.332396 board id: 1
387 18:09:33.337558 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 18:09:33.348266 fw parse done
389 18:09:33.354179 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 18:09:33.396864 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 18:09:33.407869 PIEI prepare done
392 18:09:33.408384 fastboot data load
393 18:09:33.408786 fastboot data verify
394 18:09:33.413527 verify result: 266
395 18:09:33.418972 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 18:09:33.419405 LPDDR4 probe
397 18:09:33.419796 ddr clk to 1584MHz
398 18:09:33.426051 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 18:09:33.464250
400 18:09:33.464750 dmc_version 0001
401 18:09:33.470983 Check phy result
402 18:09:33.476793 INFO : End of CA training
403 18:09:33.477257 INFO : End of initialization
404 18:09:33.482373 INFO : Training has run successfully!
405 18:09:33.482821 Check phy result
406 18:09:33.487884 INFO : End of initialization
407 18:09:33.488367 INFO : End of read enable training
408 18:09:33.491223 INFO : End of fine write leveling
409 18:09:33.496815 INFO : End of Write leveling coarse delay
410 18:09:33.502520 INFO : Training has run successfully!
411 18:09:33.502963 Check phy result
412 18:09:33.503385 INFO : End of initialization
413 18:09:33.508070 INFO : End of read dq deskew training
414 18:09:33.513573 INFO : End of MPR read delay center optimization
415 18:09:33.514038 INFO : End of write delay center optimization
416 18:09:33.519179 INFO : End of read delay center optimization
417 18:09:33.524826 INFO : End of max read latency training
418 18:09:33.525285 INFO : Training has run successfully!
419 18:09:33.530479 1D training succeed
420 18:09:33.536349 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 18:09:33.584051 Check phy result
422 18:09:33.584626 INFO : End of initialization
423 18:09:33.605427 INFO : End of 2D read delay Voltage center optimization
424 18:09:33.625985 INFO : End of 2D read delay Voltage center optimization
425 18:09:33.678006 INFO : End of 2D write delay Voltage center optimization
426 18:09:33.727392 INFO : End of 2D write delay Voltage center optimization
427 18:09:33.733314 INFO : Training has run successfully!
428 18:09:33.733759
429 18:09:33.734175 channel==0
430 18:09:33.738733 RxClkDly_Margin_A0==88 ps 9
431 18:09:33.739170 TxDqDly_Margin_A0==98 ps 10
432 18:09:33.744173 RxClkDly_Margin_A1==88 ps 9
433 18:09:33.744607 TxDqDly_Margin_A1==98 ps 10
434 18:09:33.745015 TrainedVREFDQ_A0==74
435 18:09:33.749721 TrainedVREFDQ_A1==75
436 18:09:33.750161 VrefDac_Margin_A0==25
437 18:09:33.750567 DeviceVref_Margin_A0==40
438 18:09:33.755385 VrefDac_Margin_A1==24
439 18:09:33.755819 DeviceVref_Margin_A1==39
440 18:09:33.756279
441 18:09:33.756690
442 18:09:33.760992 channel==1
443 18:09:33.761434 RxClkDly_Margin_A0==98 ps 10
444 18:09:33.761836 TxDqDly_Margin_A0==88 ps 9
445 18:09:33.766570 RxClkDly_Margin_A1==98 ps 10
446 18:09:33.767003 TxDqDly_Margin_A1==88 ps 9
447 18:09:33.772177 TrainedVREFDQ_A0==75
448 18:09:33.772670 TrainedVREFDQ_A1==77
449 18:09:33.773081 VrefDac_Margin_A0==22
450 18:09:33.777654 DeviceVref_Margin_A0==38
451 18:09:33.778097 VrefDac_Margin_A1==24
452 18:09:33.783257 DeviceVref_Margin_A1==37
453 18:09:33.783694
454 18:09:33.784139 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 18:09:33.784550
456 18:09:33.817117 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 18:09:33.817739 2D training succeed
458 18:09:33.822621 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 18:09:33.827975 auto size-- 65535DDR cs0 size: 2048MB
460 18:09:33.828458 DDR cs1 size: 2048MB
461 18:09:33.833592 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 18:09:33.834036 cs0 DataBus test pass
463 18:09:33.839183 cs1 DataBus test pass
464 18:09:33.839636 cs0 AddrBus test pass
465 18:09:33.840075 cs1 AddrBus test pass
466 18:09:33.840488
467 18:09:33.844772 100bdlr_step_size ps== 420
468 18:09:33.845234 result report
469 18:09:33.850486 boot times 0Enable ddr reg access
470 18:09:33.855739 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 18:09:33.869207 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 18:09:34.442907 0.0;M3 CHK:0;cm4_sp_mode 0
473 18:09:34.443524 MVN_1=0x00000000
474 18:09:34.448361 MVN_2=0x00000000
475 18:09:34.454152 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 18:09:34.454615 OPS=0x10
477 18:09:34.455036 ring efuse init
478 18:09:34.455443 chipver efuse init
479 18:09:34.459740 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 18:09:34.465361 [0.018960 Inits done]
481 18:09:34.465811 secure task start!
482 18:09:34.466219 high task start!
483 18:09:34.469908 low task start!
484 18:09:34.470356 run into bl31
485 18:09:34.476564 NOTICE: BL31: v1.3(release):4fc40b1
486 18:09:34.483482 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 18:09:34.484032 NOTICE: BL31: G12A normal boot!
488 18:09:34.509706 NOTICE: BL31: BL33 decompress pass
489 18:09:34.515443 ERROR: Error initializing runtime service opteed_fast
490 18:09:35.748264
491 18:09:35.748900
492 18:09:35.756784 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 18:09:35.757309
494 18:09:35.757744 Model: Libre Computer AML-A311D-CC Alta
495 18:09:35.965154 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 18:09:35.987571 DRAM: 2 GiB (effective 3.8 GiB)
497 18:09:36.131531 Core: 408 devices, 31 uclasses, devicetree: separate
498 18:09:36.137414 WDT: Not starting watchdog@f0d0
499 18:09:36.169722 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 18:09:36.182144 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 18:09:36.187119 ** Bad device specification mmc 0 **
502 18:09:36.197465 Card did not respond to voltage select! : -110
503 18:09:36.205130 ** Bad device specification mmc 0 **
504 18:09:36.205624 Couldn't find partition mmc 0
505 18:09:36.213484 Card did not respond to voltage select! : -110
506 18:09:36.218992 ** Bad device specification mmc 0 **
507 18:09:36.219649 Couldn't find partition mmc 0
508 18:09:36.224088 Error: could not access storage.
509 18:09:37.487354 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 18:09:37.487972 bl2_stage_init 0x01
511 18:09:37.488303 bl2_stage_init 0x81
512 18:09:37.492928 hw id: 0x0000 - pwm id 0x01
513 18:09:37.493289 bl2_stage_init 0xc1
514 18:09:37.493550 bl2_stage_init 0x02
515 18:09:37.493785
516 18:09:37.498454 L0:00000000
517 18:09:37.498800 L1:20000703
518 18:09:37.499035 L2:00008067
519 18:09:37.499250 L3:14000000
520 18:09:37.504074 B2:00402000
521 18:09:37.504430 B1:e0f83180
522 18:09:37.504688
523 18:09:37.504945 TE: 58167
524 18:09:37.505197
525 18:09:37.509731 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 18:09:37.510091
527 18:09:37.510337 Board ID = 1
528 18:09:37.515330 Set A53 clk to 24M
529 18:09:37.515790 Set A73 clk to 24M
530 18:09:37.516279 Set clk81 to 24M
531 18:09:37.521018 A53 clk: 1200 MHz
532 18:09:37.521589 A73 clk: 1200 MHz
533 18:09:37.522055 CLK81: 166.6M
534 18:09:37.522501 smccc: 00012abe
535 18:09:37.526544 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 18:09:37.532193 board id: 1
537 18:09:37.538050 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 18:09:37.548751 fw parse done
539 18:09:37.554705 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 18:09:37.597363 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 18:09:37.608223 PIEI prepare done
542 18:09:37.608798 fastboot data load
543 18:09:37.609256 fastboot data verify
544 18:09:37.613927 verify result: 266
545 18:09:37.619450 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 18:09:37.620062 LPDDR4 probe
547 18:09:37.620510 ddr clk to 1584MHz
548 18:09:37.627546 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 18:09:37.664882
550 18:09:37.665520 dmc_version 0001
551 18:09:37.671416 Check phy result
552 18:09:37.677244 INFO : End of CA training
553 18:09:37.677819 INFO : End of initialization
554 18:09:37.682915 INFO : Training has run successfully!
555 18:09:37.683493 Check phy result
556 18:09:37.688523 INFO : End of initialization
557 18:09:37.689113 INFO : End of read enable training
558 18:09:37.694195 INFO : End of fine write leveling
559 18:09:37.699734 INFO : End of Write leveling coarse delay
560 18:09:37.700102 INFO : Training has run successfully!
561 18:09:37.700368 Check phy result
562 18:09:37.705224 INFO : End of initialization
563 18:09:37.705616 INFO : End of read dq deskew training
564 18:09:37.710924 INFO : End of MPR read delay center optimization
565 18:09:37.716455 INFO : End of write delay center optimization
566 18:09:37.722166 INFO : End of read delay center optimization
567 18:09:37.722728 INFO : End of max read latency training
568 18:09:37.728347 INFO : Training has run successfully!
569 18:09:37.728932 1D training succeed
570 18:09:37.736209 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 18:09:37.787033 Check phy result
572 18:09:37.787482 INFO : End of initialization
573 18:09:37.806208 INFO : End of 2D read delay Voltage center optimization
574 18:09:37.826937 INFO : End of 2D read delay Voltage center optimization
575 18:09:37.878487 INFO : End of 2D write delay Voltage center optimization
576 18:09:37.927792 INFO : End of 2D write delay Voltage center optimization
577 18:09:37.933376 INFO : Training has run successfully!
578 18:09:37.933786
579 18:09:37.934021 channel==0
580 18:09:37.939062 RxClkDly_Margin_A0==88 ps 9
581 18:09:37.939425 TxDqDly_Margin_A0==98 ps 10
582 18:09:37.944555 RxClkDly_Margin_A1==88 ps 9
583 18:09:37.944933 TxDqDly_Margin_A1==98 ps 10
584 18:09:37.945181 TrainedVREFDQ_A0==74
585 18:09:37.950303 TrainedVREFDQ_A1==74
586 18:09:37.950811 VrefDac_Margin_A0==25
587 18:09:37.951070 DeviceVref_Margin_A0==40
588 18:09:37.955755 VrefDac_Margin_A1==25
589 18:09:37.956128 DeviceVref_Margin_A1==40
590 18:09:37.956377
591 18:09:37.956630
592 18:09:37.961510 channel==1
593 18:09:37.962027 RxClkDly_Margin_A0==98 ps 10
594 18:09:37.962523 TxDqDly_Margin_A0==98 ps 10
595 18:09:37.967291 RxClkDly_Margin_A1==88 ps 9
596 18:09:37.967648 TxDqDly_Margin_A1==88 ps 9
597 18:09:37.972567 TrainedVREFDQ_A0==77
598 18:09:37.972986 TrainedVREFDQ_A1==77
599 18:09:37.973218 VrefDac_Margin_A0==22
600 18:09:37.978113 DeviceVref_Margin_A0==37
601 18:09:37.978519 VrefDac_Margin_A1==24
602 18:09:37.984117 DeviceVref_Margin_A1==37
603 18:09:37.984792
604 18:09:37.985252 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 18:09:37.985711
606 18:09:38.017248 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 18:09:38.017890 2D training succeed
608 18:09:38.022805 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 18:09:38.028455 auto size-- 65535DDR cs0 size: 2048MB
610 18:09:38.028958 DDR cs1 size: 2048MB
611 18:09:38.034104 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 18:09:38.034597 cs0 DataBus test pass
613 18:09:38.039710 cs1 DataBus test pass
614 18:09:38.040246 cs0 AddrBus test pass
615 18:09:38.040671 cs1 AddrBus test pass
616 18:09:38.041083
617 18:09:38.045458 100bdlr_step_size ps== 420
618 18:09:38.046132 result report
619 18:09:38.051101 boot times 0Enable ddr reg access
620 18:09:38.056380 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 18:09:38.069823 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 18:09:38.642833 0.0;M3 CHK:0;cm4_sp_mode 0
623 18:09:38.643471 MVN_1=0x00000000
624 18:09:38.648367 MVN_2=0x00000000
625 18:09:38.654103 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 18:09:38.654618 OPS=0x10
627 18:09:38.655063 ring efuse init
628 18:09:38.655502 chipver efuse init
629 18:09:38.659738 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 18:09:38.665240 [0.018961 Inits done]
631 18:09:38.665667 secure task start!
632 18:09:38.666062 high task start!
633 18:09:38.669831 low task start!
634 18:09:38.670248 run into bl31
635 18:09:38.676444 NOTICE: BL31: v1.3(release):4fc40b1
636 18:09:38.684262 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 18:09:38.684686 NOTICE: BL31: G12A normal boot!
638 18:09:38.709653 NOTICE: BL31: BL33 decompress pass
639 18:09:38.715325 ERROR: Error initializing runtime service opteed_fast
640 18:09:39.948429
641 18:09:39.949055
642 18:09:39.956773 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 18:09:39.957242
644 18:09:39.957662 Model: Libre Computer AML-A311D-CC Alta
645 18:09:40.165322 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 18:09:40.188699 DRAM: 2 GiB (effective 3.8 GiB)
647 18:09:40.332482 Core: 408 devices, 31 uclasses, devicetree: separate
648 18:09:40.337834 WDT: Not starting watchdog@f0d0
649 18:09:40.369849 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 18:09:40.382389 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 18:09:40.387243 ** Bad device specification mmc 0 **
652 18:09:40.397796 Card did not respond to voltage select! : -110
653 18:09:40.405244 ** Bad device specification mmc 0 **
654 18:09:40.405744 Couldn't find partition mmc 0
655 18:09:40.414354 Card did not respond to voltage select! : -110
656 18:09:40.418980 ** Bad device specification mmc 0 **
657 18:09:40.419354 Couldn't find partition mmc 0
658 18:09:40.423144 Error: could not access storage.
659 18:09:40.765679 Net: eth0: ethernet@ff3f0000
660 18:09:40.766267 starting USB...
661 18:09:41.018395 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 18:09:41.019051 Starting the controller
663 18:09:41.025337 USB XHCI 1.10
664 18:09:42.739326 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 18:09:42.740030 bl2_stage_init 0x01
666 18:09:42.740911 bl2_stage_init 0x81
667 18:09:42.742131 hw id: 0x0000 - pwm id 0x01
668 18:09:42.742588 bl2_stage_init 0xc1
669 18:09:42.742991 bl2_stage_init 0x02
670 18:09:42.743387
671 18:09:42.747179 L0:00000000
672 18:09:42.747608 L1:20000703
673 18:09:42.748030 L2:00008067
674 18:09:42.748425 L3:14000000
675 18:09:42.753723 B2:00402000
676 18:09:42.755020 B1:e0f83180
677 18:09:42.755430
678 18:09:42.755934 TE: 58159
679 18:09:42.757817
680 18:09:42.761266 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 18:09:42.761721
682 18:09:42.762121 Board ID = 1
683 18:09:42.762514 Set A53 clk to 24M
684 18:09:42.762903 Set A73 clk to 24M
685 18:09:42.767039 Set clk81 to 24M
686 18:09:42.767705 A53 clk: 1200 MHz
687 18:09:42.768342 A73 clk: 1200 MHz
688 18:09:42.772616 CLK81: 166.6M
689 18:09:42.773239 smccc: 00012ab5
690 18:09:42.778202 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 18:09:42.778795 board id: 1
692 18:09:42.786836 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 18:09:42.797340 fw parse done
694 18:09:42.803257 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 18:09:42.845989 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 18:09:42.856826 PIEI prepare done
697 18:09:42.857479 fastboot data load
698 18:09:42.858028 fastboot data verify
699 18:09:42.862427 verify result: 266
700 18:09:42.868046 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 18:09:42.868681 LPDDR4 probe
702 18:09:42.869233 ddr clk to 1584MHz
703 18:09:42.876060 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 18:09:42.913370
705 18:09:42.914128 dmc_version 0001
706 18:09:42.920009 Check phy result
707 18:09:42.925801 INFO : End of CA training
708 18:09:42.926407 INFO : End of initialization
709 18:09:42.931413 INFO : Training has run successfully!
710 18:09:42.932012 Check phy result
711 18:09:42.937018 INFO : End of initialization
712 18:09:42.937568 INFO : End of read enable training
713 18:09:42.940270 INFO : End of fine write leveling
714 18:09:42.945849 INFO : End of Write leveling coarse delay
715 18:09:42.951451 INFO : Training has run successfully!
716 18:09:42.952042 Check phy result
717 18:09:42.952572 INFO : End of initialization
718 18:09:42.957020 INFO : End of read dq deskew training
719 18:09:42.962658 INFO : End of MPR read delay center optimization
720 18:09:42.963246 INFO : End of write delay center optimization
721 18:09:42.968271 INFO : End of read delay center optimization
722 18:09:42.973877 INFO : End of max read latency training
723 18:09:42.974437 INFO : Training has run successfully!
724 18:09:42.979410 1D training succeed
725 18:09:42.985328 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 18:09:43.032946 Check phy result
727 18:09:43.033316 INFO : End of initialization
728 18:09:43.054653 INFO : End of 2D read delay Voltage center optimization
729 18:09:43.074912 INFO : End of 2D read delay Voltage center optimization
730 18:09:43.126909 INFO : End of 2D write delay Voltage center optimization
731 18:09:43.176652 INFO : End of 2D write delay Voltage center optimization
732 18:09:43.181816 INFO : Training has run successfully!
733 18:09:43.182143
734 18:09:43.182369 channel==0
735 18:09:43.187468 RxClkDly_Margin_A0==88 ps 9
736 18:09:43.187826 TxDqDly_Margin_A0==98 ps 10
737 18:09:43.193009 RxClkDly_Margin_A1==88 ps 9
738 18:09:43.193332 TxDqDly_Margin_A1==98 ps 10
739 18:09:43.193550 TrainedVREFDQ_A0==74
740 18:09:43.198627 TrainedVREFDQ_A1==74
741 18:09:43.198966 VrefDac_Margin_A0==25
742 18:09:43.199189 DeviceVref_Margin_A0==40
743 18:09:43.204290 VrefDac_Margin_A1==25
744 18:09:43.204650 DeviceVref_Margin_A1==40
745 18:09:43.204881
746 18:09:43.205098
747 18:09:43.209836 channel==1
748 18:09:43.210174 RxClkDly_Margin_A0==98 ps 10
749 18:09:43.210400 TxDqDly_Margin_A0==98 ps 10
750 18:09:43.215430 RxClkDly_Margin_A1==88 ps 9
751 18:09:43.215777 TxDqDly_Margin_A1==98 ps 10
752 18:09:43.221087 TrainedVREFDQ_A0==77
753 18:09:43.221452 TrainedVREFDQ_A1==77
754 18:09:43.221680 VrefDac_Margin_A0==22
755 18:09:43.226610 DeviceVref_Margin_A0==37
756 18:09:43.226985 VrefDac_Margin_A1==24
757 18:09:43.232172 DeviceVref_Margin_A1==37
758 18:09:43.232491
759 18:09:43.232742 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 18:09:43.237769
761 18:09:43.265774 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 18:09:43.266190 2D training succeed
763 18:09:43.271322 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 18:09:43.276933 auto size-- 65535DDR cs0 size: 2048MB
765 18:09:43.277458 DDR cs1 size: 2048MB
766 18:09:43.282550 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 18:09:43.283008 cs0 DataBus test pass
768 18:09:43.288154 cs1 DataBus test pass
769 18:09:43.288620 cs0 AddrBus test pass
770 18:09:43.289018 cs1 AddrBus test pass
771 18:09:43.289410
772 18:09:43.293741 100bdlr_step_size ps== 420
773 18:09:43.294208 result report
774 18:09:43.299362 boot times 0Enable ddr reg access
775 18:09:43.303975 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 18:09:43.318405 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 18:09:43.892142 0.0;M3 CHK:0;cm4_sp_mode 0
778 18:09:43.892787 MVN_1=0x00000000
779 18:09:43.897554 MVN_2=0x00000000
780 18:09:43.903283 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 18:09:43.903803 OPS=0x10
782 18:09:43.904253 ring efuse init
783 18:09:43.904647 chipver efuse init
784 18:09:43.908816 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 18:09:43.914432 [0.018961 Inits done]
786 18:09:43.914954 secure task start!
787 18:09:43.915368 high task start!
788 18:09:43.919025 low task start!
789 18:09:43.919491 run into bl31
790 18:09:43.925812 NOTICE: BL31: v1.3(release):4fc40b1
791 18:09:43.933501 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 18:09:43.933992 NOTICE: BL31: G12A normal boot!
793 18:09:43.958986 NOTICE: BL31: BL33 decompress pass
794 18:09:43.964343 ERROR: Error initializing runtime service opteed_fast
795 18:09:45.197542
796 18:09:45.198164
797 18:09:45.206017 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 18:09:45.206492
799 18:09:45.206913 Model: Libre Computer AML-A311D-CC Alta
800 18:09:45.414346 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 18:09:45.437744 DRAM: 2 GiB (effective 3.8 GiB)
802 18:09:45.580758 Core: 408 devices, 31 uclasses, devicetree: separate
803 18:09:45.586586 WDT: Not starting watchdog@f0d0
804 18:09:45.618928 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 18:09:45.631331 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 18:09:45.636238 ** Bad device specification mmc 0 **
807 18:09:45.646596 Card did not respond to voltage select! : -110
808 18:09:45.653341 ** Bad device specification mmc 0 **
809 18:09:45.653665 Couldn't find partition mmc 0
810 18:09:45.662617 Card did not respond to voltage select! : -110
811 18:09:45.668115 ** Bad device specification mmc 0 **
812 18:09:45.668428 Couldn't find partition mmc 0
813 18:09:45.673161 Error: could not access storage.
814 18:09:46.015706 Net: eth0: ethernet@ff3f0000
815 18:09:46.016324 starting USB...
816 18:09:46.267456 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 18:09:46.267888 Starting the controller
818 18:09:46.274414 USB XHCI 1.10
819 18:09:48.436280 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
820 18:09:48.436711 bl2_stage_init 0x81
821 18:09:48.441693 hw id: 0x0000 - pwm id 0x01
822 18:09:48.441984 bl2_stage_init 0xc1
823 18:09:48.442194 bl2_stage_init 0x02
824 18:09:48.442409
825 18:09:48.447467 L0:00000000
826 18:09:48.447726 L1:20000703
827 18:09:48.447942 L2:00008067
828 18:09:48.448178 L3:14000000
829 18:09:48.448384 B2:00402000
830 18:09:48.452991 B1:e0f83180
831 18:09:48.453250
832 18:09:48.453457 TE: 58150
833 18:09:48.453661
834 18:09:48.458594 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 18:09:48.458855
836 18:09:48.459061 Board ID = 1
837 18:09:48.464215 Set A53 clk to 24M
838 18:09:48.464475 Set A73 clk to 24M
839 18:09:48.464683 Set clk81 to 24M
840 18:09:48.469852 A53 clk: 1200 MHz
841 18:09:48.470127 A73 clk: 1200 MHz
842 18:09:48.470336 CLK81: 166.6M
843 18:09:48.470540 smccc: 00012aac
844 18:09:48.475509 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 18:09:48.481000 board id: 1
846 18:09:48.486767 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 18:09:48.497521 fw parse done
848 18:09:48.503435 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 18:09:48.545953 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 18:09:48.556859 PIEI prepare done
851 18:09:48.557132 fastboot data load
852 18:09:48.557350 fastboot data verify
853 18:09:48.562574 verify result: 266
854 18:09:48.568159 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 18:09:48.568431 LPDDR4 probe
856 18:09:48.568641 ddr clk to 1584MHz
857 18:09:48.576113 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 18:09:48.613411
859 18:09:48.613704 dmc_version 0001
860 18:09:48.620063 Check phy result
861 18:09:48.625917 INFO : End of CA training
862 18:09:48.626192 INFO : End of initialization
863 18:09:48.631567 INFO : Training has run successfully!
864 18:09:48.631840 Check phy result
865 18:09:48.637126 INFO : End of initialization
866 18:09:48.637403 INFO : End of read enable training
867 18:09:48.642753 INFO : End of fine write leveling
868 18:09:48.648401 INFO : End of Write leveling coarse delay
869 18:09:48.648791 INFO : Training has run successfully!
870 18:09:48.649031 Check phy result
871 18:09:48.653970 INFO : End of initialization
872 18:09:48.654236 INFO : End of read dq deskew training
873 18:09:48.659515 INFO : End of MPR read delay center optimization
874 18:09:48.665203 INFO : End of write delay center optimization
875 18:09:48.670758 INFO : End of read delay center optimization
876 18:09:48.671025 INFO : End of max read latency training
877 18:09:48.676361 INFO : Training has run successfully!
878 18:09:48.676624 1D training succeed
879 18:09:48.685713 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 18:09:48.733168 Check phy result
881 18:09:48.733594 INFO : End of initialization
882 18:09:48.754789 INFO : End of 2D read delay Voltage center optimization
883 18:09:48.774863 INFO : End of 2D read delay Voltage center optimization
884 18:09:48.826739 INFO : End of 2D write delay Voltage center optimization
885 18:09:48.876022 INFO : End of 2D write delay Voltage center optimization
886 18:09:48.881602 INFO : Training has run successfully!
887 18:09:48.881877
888 18:09:48.882091 channel==0
889 18:09:48.887098 RxClkDly_Margin_A0==88 ps 9
890 18:09:48.887468 TxDqDly_Margin_A0==98 ps 10
891 18:09:48.892229 RxClkDly_Margin_A1==88 ps 9
892 18:09:48.892641 TxDqDly_Margin_A1==98 ps 10
893 18:09:48.896068 TrainedVREFDQ_A0==74
894 18:09:48.896630 TrainedVREFDQ_A1==74
895 18:09:48.901728 VrefDac_Margin_A0==25
896 18:09:48.902264 DeviceVref_Margin_A0==40
897 18:09:48.902710 VrefDac_Margin_A1==25
898 18:09:48.907187 DeviceVref_Margin_A1==40
899 18:09:48.907712
900 18:09:48.908190
901 18:09:48.908631 channel==1
902 18:09:48.909064 RxClkDly_Margin_A0==88 ps 9
903 18:09:48.910646 TxDqDly_Margin_A0==88 ps 9
904 18:09:48.916339 RxClkDly_Margin_A1==98 ps 10
905 18:09:48.916872 TxDqDly_Margin_A1==88 ps 9
906 18:09:48.917321 TrainedVREFDQ_A0==77
907 18:09:48.921995 TrainedVREFDQ_A1==77
908 18:09:48.922522 VrefDac_Margin_A0==22
909 18:09:48.927561 DeviceVref_Margin_A0==37
910 18:09:48.928158 VrefDac_Margin_A1==22
911 18:09:48.928607 DeviceVref_Margin_A1==37
912 18:09:48.929039
913 18:09:48.936552 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 18:09:48.937101
915 18:09:48.962275 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
916 18:09:48.967914 2D training succeed
917 18:09:48.973537 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 18:09:48.979073 auto size-- 65535DDR cs0 size: 2048MB
919 18:09:48.979644 DDR cs1 size: 2048MB
920 18:09:48.980168 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 18:09:48.984694 cs0 DataBus test pass
922 18:09:48.985244 cs1 DataBus test pass
923 18:09:48.990285 cs0 AddrBus test pass
924 18:09:48.990829 cs1 AddrBus test pass
925 18:09:48.991267
926 18:09:48.991701 100bdlr_step_size ps== 420
927 18:09:48.995877 result report
928 18:09:48.996460 boot times 0Enable ddr reg access
929 18:09:49.004512 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 18:09:49.017894 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 18:09:49.589747 0.0;M3 CHK:0;cm4_sp_mode 0
932 18:09:49.590186 MVN_1=0x00000000
933 18:09:49.595310 MVN_2=0x00000000
934 18:09:49.601090 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 18:09:49.601445 OPS=0x10
936 18:09:49.601678 ring efuse init
937 18:09:49.601894 chipver efuse init
938 18:09:49.606667 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 18:09:49.612359 [0.018961 Inits done]
940 18:09:49.612845 secure task start!
941 18:09:49.613234 high task start!
942 18:09:49.616696 low task start!
943 18:09:49.617043 run into bl31
944 18:09:49.623656 NOTICE: BL31: v1.3(release):4fc40b1
945 18:09:49.631467 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 18:09:49.632132 NOTICE: BL31: G12A normal boot!
947 18:09:49.656692 NOTICE: BL31: BL33 decompress pass
948 18:09:49.662359 ERROR: Error initializing runtime service opteed_fast
949 18:09:50.895052
950 18:09:50.895752
951 18:09:50.903501 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 18:09:50.904075
953 18:09:50.904573 Model: Libre Computer AML-A311D-CC Alta
954 18:09:51.112109 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 18:09:51.135304 DRAM: 2 GiB (effective 3.8 GiB)
956 18:09:51.278289 Core: 408 devices, 31 uclasses, devicetree: separate
957 18:09:51.284163 WDT: Not starting watchdog@f0d0
958 18:09:51.316443 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 18:09:51.328898 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 18:09:51.333890 ** Bad device specification mmc 0 **
961 18:09:51.344195 Card did not respond to voltage select! : -110
962 18:09:51.351883 ** Bad device specification mmc 0 **
963 18:09:51.352437 Couldn't find partition mmc 0
964 18:09:51.360191 Card did not respond to voltage select! : -110
965 18:09:51.365706 ** Bad device specification mmc 0 **
966 18:09:51.366194 Couldn't find partition mmc 0
967 18:09:51.370765 Error: could not access storage.
968 18:09:51.713253 Net: eth0: ethernet@ff3f0000
969 18:09:51.713807 starting USB...
970 18:09:51.964996 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 18:09:51.965527 Starting the controller
972 18:09:51.972072 USB XHCI 1.10
973 18:09:53.835779 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 18:09:53.836206 bl2_stage_init 0x01
975 18:09:53.836682 bl2_stage_init 0x81
976 18:09:53.841530 hw id: 0x0000 - pwm id 0x01
977 18:09:53.842072 bl2_stage_init 0xc1
978 18:09:53.842541 bl2_stage_init 0x02
979 18:09:53.842996
980 18:09:53.847232 L0:00000000
981 18:09:53.847746 L1:20000703
982 18:09:53.848238 L2:00008067
983 18:09:53.848691 L3:14000000
984 18:09:53.852748 B2:00402000
985 18:09:53.853263 B1:e0f83180
986 18:09:53.853720
987 18:09:53.854172 TE: 58167
988 18:09:53.854618
989 18:09:53.858354 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 18:09:53.858870
991 18:09:53.859327 Board ID = 1
992 18:09:53.863920 Set A53 clk to 24M
993 18:09:53.864458 Set A73 clk to 24M
994 18:09:53.864913 Set clk81 to 24M
995 18:09:53.869558 A53 clk: 1200 MHz
996 18:09:53.870072 A73 clk: 1200 MHz
997 18:09:53.870525 CLK81: 166.6M
998 18:09:53.870965 smccc: 00012abd
999 18:09:53.875159 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 18:09:53.880712 board id: 1
1001 18:09:53.886588 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 18:09:53.897225 fw parse done
1003 18:09:53.903340 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 18:09:53.945841 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 18:09:53.956969 PIEI prepare done
1006 18:09:53.957494 fastboot data load
1007 18:09:53.957928 fastboot data verify
1008 18:09:53.962646 verify result: 266
1009 18:09:53.968234 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 18:09:53.968532 LPDDR4 probe
1011 18:09:53.968755 ddr clk to 1584MHz
1012 18:09:53.976187 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 18:09:54.013556
1014 18:09:54.014158 dmc_version 0001
1015 18:09:54.020136 Check phy result
1016 18:09:54.025930 INFO : End of CA training
1017 18:09:54.026490 INFO : End of initialization
1018 18:09:54.031602 INFO : Training has run successfully!
1019 18:09:54.032188 Check phy result
1020 18:09:54.037274 INFO : End of initialization
1021 18:09:54.037878 INFO : End of read enable training
1022 18:09:54.042755 INFO : End of fine write leveling
1023 18:09:54.048452 INFO : End of Write leveling coarse delay
1024 18:09:54.049028 INFO : Training has run successfully!
1025 18:09:54.049531 Check phy result
1026 18:09:54.054000 INFO : End of initialization
1027 18:09:54.054320 INFO : End of read dq deskew training
1028 18:09:54.059450 INFO : End of MPR read delay center optimization
1029 18:09:54.065037 INFO : End of write delay center optimization
1030 18:09:54.070633 INFO : End of read delay center optimization
1031 18:09:54.071201 INFO : End of max read latency training
1032 18:09:54.076189 INFO : Training has run successfully!
1033 18:09:54.076768 1D training succeed
1034 18:09:54.085401 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 18:09:54.132986 Check phy result
1036 18:09:54.133545 INFO : End of initialization
1037 18:09:54.155441 INFO : End of 2D read delay Voltage center optimization
1038 18:09:54.175486 INFO : End of 2D read delay Voltage center optimization
1039 18:09:54.227454 INFO : End of 2D write delay Voltage center optimization
1040 18:09:54.276634 INFO : End of 2D write delay Voltage center optimization
1041 18:09:54.282250 INFO : Training has run successfully!
1042 18:09:54.282774
1043 18:09:54.283209 channel==0
1044 18:09:54.287810 RxClkDly_Margin_A0==88 ps 9
1045 18:09:54.288362 TxDqDly_Margin_A0==98 ps 10
1046 18:09:54.293428 RxClkDly_Margin_A1==88 ps 9
1047 18:09:54.293944 TxDqDly_Margin_A1==98 ps 10
1048 18:09:54.294374 TrainedVREFDQ_A0==74
1049 18:09:54.299001 TrainedVREFDQ_A1==75
1050 18:09:54.299515 VrefDac_Margin_A0==24
1051 18:09:54.299937 DeviceVref_Margin_A0==40
1052 18:09:54.304620 VrefDac_Margin_A1==24
1053 18:09:54.305137 DeviceVref_Margin_A1==39
1054 18:09:54.305562
1055 18:09:54.305974
1056 18:09:54.310254 channel==1
1057 18:09:54.310755 RxClkDly_Margin_A0==98 ps 10
1058 18:09:54.311176 TxDqDly_Margin_A0==98 ps 10
1059 18:09:54.315794 RxClkDly_Margin_A1==88 ps 9
1060 18:09:54.316327 TxDqDly_Margin_A1==88 ps 9
1061 18:09:54.321410 TrainedVREFDQ_A0==77
1062 18:09:54.321931 TrainedVREFDQ_A1==77
1063 18:09:54.322351 VrefDac_Margin_A0==22
1064 18:09:54.327019 DeviceVref_Margin_A0==37
1065 18:09:54.327524 VrefDac_Margin_A1==24
1066 18:09:54.332611 DeviceVref_Margin_A1==37
1067 18:09:54.333118
1068 18:09:54.333536 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 18:09:54.333943
1070 18:09:54.366195 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1071 18:09:54.366762 2D training succeed
1072 18:09:54.371812 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 18:09:54.377410 auto size-- 65535DDR cs0 size: 2048MB
1074 18:09:54.377918 DDR cs1 size: 2048MB
1075 18:09:54.382997 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 18:09:54.383503 cs0 DataBus test pass
1077 18:09:54.388604 cs1 DataBus test pass
1078 18:09:54.389110 cs0 AddrBus test pass
1079 18:09:54.389526 cs1 AddrBus test pass
1080 18:09:54.389924
1081 18:09:54.394232 100bdlr_step_size ps== 420
1082 18:09:54.394740 result report
1083 18:09:54.399786 boot times 0Enable ddr reg access
1084 18:09:54.405125 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 18:09:54.418563 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 18:09:54.990555 0.0;M3 CHK:0;cm4_sp_mode 0
1087 18:09:54.991197 MVN_1=0x00000000
1088 18:09:54.996089 MVN_2=0x00000000
1089 18:09:55.001758 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 18:09:55.002065 OPS=0x10
1091 18:09:55.002305 ring efuse init
1092 18:09:55.002531 chipver efuse init
1093 18:09:55.007329 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 18:09:55.012950 [0.018961 Inits done]
1095 18:09:55.013356 secure task start!
1096 18:09:55.013677 high task start!
1097 18:09:55.017517 low task start!
1098 18:09:55.017929 run into bl31
1099 18:09:55.024177 NOTICE: BL31: v1.3(release):4fc40b1
1100 18:09:55.031995 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 18:09:55.032346 NOTICE: BL31: G12A normal boot!
1102 18:09:55.057386 NOTICE: BL31: BL33 decompress pass
1103 18:09:55.063029 ERROR: Error initializing runtime service opteed_fast
1104 18:09:56.295926
1105 18:09:56.296592
1106 18:09:56.304354 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 18:09:56.304820
1108 18:09:56.305239 Model: Libre Computer AML-A311D-CC Alta
1109 18:09:56.512769 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 18:09:56.536148 DRAM: 2 GiB (effective 3.8 GiB)
1111 18:09:56.679392 Core: 408 devices, 31 uclasses, devicetree: separate
1112 18:09:56.685011 WDT: Not starting watchdog@f0d0
1113 18:09:56.717273 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 18:09:56.729754 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 18:09:56.734697 ** Bad device specification mmc 0 **
1116 18:09:56.745053 Card did not respond to voltage select! : -110
1117 18:09:56.753195 ** Bad device specification mmc 0 **
1118 18:09:56.753644 Couldn't find partition mmc 0
1119 18:09:56.761231 Card did not respond to voltage select! : -110
1120 18:09:56.766671 ** Bad device specification mmc 0 **
1121 18:09:56.767121 Couldn't find partition mmc 0
1122 18:09:56.770736 Error: could not access storage.
1123 18:09:57.114160 Net: eth0: ethernet@ff3f0000
1124 18:09:57.114779 starting USB...
1125 18:09:57.365954 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 18:09:57.366575 Starting the controller
1127 18:09:57.372997 USB XHCI 1.10
1128 18:09:58.929193 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 18:09:58.937538 scanning usb for storage devices... 0 Storage Device(s) found
1131 18:09:58.989163 Hit any key to stop autoboot: 1
1132 18:09:58.989930 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 18:09:58.990498 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 18:09:58.990953 Setting prompt string to ['=>']
1135 18:09:58.991429 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 18:09:59.004741 0
1137 18:09:59.005643 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 18:09:59.006127 Sending with 10 millisecond of delay
1140 18:10:00.140849 => setenv autoload no
1141 18:10:00.151385 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1142 18:10:00.153915 setenv autoload no
1143 18:10:00.154390 Sending with 10 millisecond of delay
1145 18:10:01.952920 => setenv initrd_high 0xffffffff
1146 18:10:01.963506 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 18:10:01.964134 setenv initrd_high 0xffffffff
1148 18:10:01.964621 Sending with 10 millisecond of delay
1150 18:10:03.582527 => setenv fdt_high 0xffffffff
1151 18:10:03.593092 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1152 18:10:03.593653 setenv fdt_high 0xffffffff
1153 18:10:03.594119 Sending with 10 millisecond of delay
1155 18:10:03.885625 => dhcp
1156 18:10:03.896230 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 18:10:03.896830 dhcp
1158 18:10:03.897073 Speed: 1000, full duplex
1159 18:10:03.897284 BOOTP broadcast 1
1160 18:10:03.921401 DHCP client bound to address 192.168.6.27 (25 ms)
1161 18:10:03.922003 Sending with 10 millisecond of delay
1163 18:10:05.598774 => setenv serverip 192.168.6.2
1164 18:10:05.609617 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1165 18:10:05.610566 setenv serverip 192.168.6.2
1166 18:10:05.611247 Sending with 10 millisecond of delay
1168 18:10:09.341492 => tftpboot 0x01080000 941220/tftp-deploy-3kekei07/kernel/uImage
1169 18:10:09.352306 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1170 18:10:09.353151 tftpboot 0x01080000 941220/tftp-deploy-3kekei07/kernel/uImage
1171 18:10:09.353657 Speed: 1000, full duplex
1172 18:10:09.354096 Using ethernet@ff3f0000 device
1173 18:10:09.354967 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 18:10:09.360637 Filename '941220/tftp-deploy-3kekei07/kernel/uImage'.
1175 18:10:09.364597 Load address: 0x1080000
1176 18:10:12.520025 Loading: *################################################## 43.6 MiB
1177 18:10:12.520669 13.8 MiB/s
1178 18:10:12.521121 done
1179 18:10:12.523446 Bytes transferred = 45713984 (2b98a40 hex)
1180 18:10:12.524386 Sending with 10 millisecond of delay
1182 18:10:17.214908 => tftpboot 0x08000000 941220/tftp-deploy-3kekei07/ramdisk/ramdisk.cpio.gz.uboot
1183 18:10:17.225755 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1184 18:10:17.226690 tftpboot 0x08000000 941220/tftp-deploy-3kekei07/ramdisk/ramdisk.cpio.gz.uboot
1185 18:10:17.227192 Speed: 1000, full duplex
1186 18:10:17.227639 Using ethernet@ff3f0000 device
1187 18:10:17.228754 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 18:10:17.237285 Filename '941220/tftp-deploy-3kekei07/ramdisk/ramdisk.cpio.gz.uboot'.
1189 18:10:17.237862 Load address: 0x8000000
1190 18:10:24.378484 Loading: *#############T ##################################### 22.3 MiB
1191 18:10:24.379161 3.1 MiB/s
1192 18:10:24.379633 done
1193 18:10:24.382955 Bytes transferred = 23427582 (16579fe hex)
1194 18:10:24.383810 Sending with 10 millisecond of delay
1196 18:10:29.555763 => tftpboot 0x01070000 941220/tftp-deploy-3kekei07/dtb/meson-g12b-a311d-libretech-cc.dtb
1197 18:10:29.566862 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:52)
1198 18:10:29.568307 tftpboot 0x01070000 941220/tftp-deploy-3kekei07/dtb/meson-g12b-a311d-libretech-cc.dtb
1199 18:10:29.568929 Speed: 1000, full duplex
1200 18:10:29.569481 Using ethernet@ff3f0000 device
1201 18:10:29.572355 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1202 18:10:29.585514 Filename '941220/tftp-deploy-3kekei07/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1203 18:10:29.586276 Load address: 0x1070000
1204 18:10:29.601493 Loading: *################################################## 53.4 KiB
1205 18:10:29.602296 2.9 MiB/s
1206 18:10:29.602862 done
1207 18:10:29.607660 Bytes transferred = 54703 (d5af hex)
1208 18:10:29.608714 Sending with 10 millisecond of delay
1210 18:10:42.916083 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/941220/extract-nfsrootfs-61pgpkhz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1211 18:10:42.926970 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:39)
1212 18:10:42.927918 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/941220/extract-nfsrootfs-61pgpkhz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1213 18:10:42.928726 Sending with 10 millisecond of delay
1215 18:10:45.268505 => bootm 0x01080000 0x08000000 0x01070000
1216 18:10:45.279354 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1217 18:10:45.279922 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:36)
1218 18:10:45.281043 bootm 0x01080000 0x08000000 0x01070000
1219 18:10:45.281526 ## Booting kernel from Legacy Image at 01080000 ...
1220 18:10:45.284292 Image Name:
1221 18:10:45.289851 Image Type: AArch64 Linux Kernel Image (uncompressed)
1222 18:10:45.290340 Data Size: 45713920 Bytes = 43.6 MiB
1223 18:10:45.295277 Load Address: 01080000
1224 18:10:45.295765 Entry Point: 01080000
1225 18:10:45.490617 Verifying Checksum ... OK
1226 18:10:45.491201 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1227 18:10:45.496026 Image Name:
1228 18:10:45.501449 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1229 18:10:45.501922 Data Size: 23427518 Bytes = 22.3 MiB
1230 18:10:45.503777 Load Address: 00000000
1231 18:10:45.511001 Entry Point: 00000000
1232 18:10:45.609063 Verifying Checksum ... OK
1233 18:10:45.609537 ## Flattened Device Tree blob at 01070000
1234 18:10:45.614559 Booting using the fdt blob at 0x1070000
1235 18:10:45.615021 Working FDT set to 1070000
1236 18:10:45.618981 Loading Kernel Image
1237 18:10:45.781856 Loading Ramdisk to 7e9a8000, end 7ffff9be ... OK
1238 18:10:45.790025 Loading Device Tree to 000000007e997000, end 000000007e9a75ae ... OK
1239 18:10:45.790498 Working FDT set to 7e997000
1240 18:10:45.790939
1241 18:10:45.791877 end: 2.4.3 bootloader-commands (duration 00:00:47) [common]
1242 18:10:45.792554 start: 2.4.4 auto-login-action (timeout 00:03:36) [common]
1243 18:10:45.793051 Setting prompt string to ['Linux version [0-9]']
1244 18:10:45.793541 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1245 18:10:45.794032 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1246 18:10:45.795100 Starting kernel ...
1247 18:10:45.795563
1248 18:10:45.830377 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1249 18:10:45.831363 start: 2.4.4.1 login-action (timeout 00:03:36) [common]
1250 18:10:45.831919 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1251 18:10:45.832464 Setting prompt string to []
1252 18:10:45.832975 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1253 18:10:45.833455 Using line separator: #'\n'#
1254 18:10:45.833898 No login prompt set.
1255 18:10:45.834353 Parsing kernel messages
1256 18:10:45.834779 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1257 18:10:45.835605 [login-action] Waiting for messages, (timeout 00:03:36)
1258 18:10:45.836104 Waiting using forced prompt support (timeout 00:01:48)
1259 18:10:45.850452 [ 0.000000] Linux version 6.12.0-rc1 (KernelCI@build-j363578-arm64-gcc-12-defconfig-lbfhq) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Tue Nov 5 17:11:02 UTC 2024
1260 18:10:45.850979 [ 0.000000] KASLR disabled due to lack of seed
1261 18:10:45.856041 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1262 18:10:45.861542 [ 0.000000] efi: UEFI not found.
1263 18:10:45.867047 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1264 18:10:45.878006 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1265 18:10:45.883621 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1266 18:10:45.894704 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1267 18:10:45.905711 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1268 18:10:45.916798 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1269 18:10:45.922184 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1270 18:10:45.927651 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1271 18:10:45.933145 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1272 18:10:45.938674 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1273 18:10:45.944270 [ 0.000000] Zone ranges:
1274 18:10:45.949699 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1275 18:10:45.950176 [ 0.000000] DMA32 empty
1276 18:10:45.955278 [ 0.000000] Normal empty
1277 18:10:45.960741 [ 0.000000] Movable zone start for each node
1278 18:10:45.961216 [ 0.000000] Early memory node ranges
1279 18:10:45.966245 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1280 18:10:45.971815 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1281 18:10:45.982821 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1282 18:10:45.987895 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1283 18:10:46.012141 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1284 18:10:46.017719 [ 0.000000] psci: probing for conduit method from DT.
1285 18:10:46.018198 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1286 18:10:46.026714 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1287 18:10:46.027191 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1288 18:10:46.032253 [ 0.000000] psci: SMC Calling Convention v1.1
1289 18:10:46.037780 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1290 18:10:46.043297 [ 0.000000] Detected VIPT I-cache on CPU0
1291 18:10:46.048803 [ 0.000000] CPU features: detected: ARM erratum 845719
1292 18:10:46.054327 [ 0.000000] alternatives: applying boot alternatives
1293 18:10:46.076445 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/941220/extract-nfsrootfs-61pgpkhz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1294 18:10:46.081935 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1295 18:10:46.092938 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1296 18:10:46.093424 <6>[ 0.000000] Fallback order for Node 0: 0
1297 18:10:46.104016 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1298 18:10:46.104504 <6>[ 0.000000] Policy zone: DMA
1299 18:10:46.109571 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1300 18:10:46.120640 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1301 18:10:46.121118 <6>[ 0.000000] software IO TLB: area num 8.
1302 18:10:46.131637 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1303 18:10:46.178140 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1304 18:10:46.183717 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1305 18:10:46.187319 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1306 18:10:46.192825 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1307 18:10:46.198346 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1308 18:10:46.203858 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1309 18:10:46.214879 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1310 18:10:46.220476 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1311 18:10:46.225960 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1312 18:10:46.236971 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1313 18:10:46.242496 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1314 18:10:46.248054 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1315 18:10:46.253538 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1316 18:10:46.259814 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1317 18:10:46.272450 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1318 18:10:46.283469 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1319 18:10:46.288974 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1320 18:10:46.294564 <6>[ 0.008799] Console: colour dummy device 80x25
1321 18:10:46.305599 <6>[ 0.012938] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1322 18:10:46.311093 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1323 18:10:46.316631 <6>[ 0.028191] LSM: initializing lsm=capability
1324 18:10:46.322231 <6>[ 0.032731] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1325 18:10:46.327698 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1326 18:10:46.333168 <6>[ 0.052301] rcu: Hierarchical SRCU implementation.
1327 18:10:46.338703 <6>[ 0.053216] rcu: Max phase no-delay instances is 1000.
1328 18:10:46.349731 <6>[ 0.058877] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1329 18:10:46.358186 <6>[ 0.071577] EFI services will not be available.
1330 18:10:46.358661 <6>[ 0.075229] smp: Bringing up secondary CPUs ...
1331 18:10:46.374579 <6>[ 0.077131] Detected VIPT I-cache on CPU1
1332 18:10:46.380086 <6>[ 0.077250] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1333 18:10:46.385644 <6>[ 0.078590] CPU features: detected: Spectre-v2
1334 18:10:46.391182 <6>[ 0.078604] CPU features: detected: Spectre-v4
1335 18:10:46.396613 <6>[ 0.078609] CPU features: detected: Spectre-BHB
1336 18:10:46.402071 <6>[ 0.078615] CPU features: detected: ARM erratum 858921
1337 18:10:46.407523 <6>[ 0.078623] Detected VIPT I-cache on CPU2
1338 18:10:46.413097 <6>[ 0.078694] arch_timer: Enabling local workaround for ARM erratum 858921
1339 18:10:46.418869 <6>[ 0.078712] arch_timer: CPU2: Trapping CNTVCT access
1340 18:10:46.424200 <6>[ 0.078722] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1341 18:10:46.429649 <6>[ 0.083581] Detected VIPT I-cache on CPU3
1342 18:10:46.435190 <6>[ 0.083626] arch_timer: Enabling local workaround for ARM erratum 858921
1343 18:10:46.440692 <6>[ 0.083636] arch_timer: CPU3: Trapping CNTVCT access
1344 18:10:46.446189 <6>[ 0.083643] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1345 18:10:46.451724 <6>[ 0.087615] Detected VIPT I-cache on CPU4
1346 18:10:46.457331 <6>[ 0.087662] arch_timer: Enabling local workaround for ARM erratum 858921
1347 18:10:46.462773 <6>[ 0.087671] arch_timer: CPU4: Trapping CNTVCT access
1348 18:10:46.473819 <6>[ 0.087678] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1349 18:10:46.474299 <6>[ 0.095644] Detected VIPT I-cache on CPU5
1350 18:10:46.484831 <6>[ 0.095692] arch_timer: Enabling local workaround for ARM erratum 858921
1351 18:10:46.485324 <6>[ 0.095701] arch_timer: CPU5: Trapping CNTVCT access
1352 18:10:46.495847 <6>[ 0.095708] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1353 18:10:46.496381 <6>[ 0.095830] smp: Brought up 1 node, 6 CPUs
1354 18:10:46.501396 <6>[ 0.217061] SMP: Total of 6 processors activated.
1355 18:10:46.506896 <6>[ 0.221964] CPU: All CPU(s) started at EL2
1356 18:10:46.512493 <6>[ 0.226307] CPU features: detected: 32-bit EL0 Support
1357 18:10:46.517979 <6>[ 0.231623] CPU features: detected: 32-bit EL1 Support
1358 18:10:46.523552 <6>[ 0.236971] CPU features: detected: CRC32 instructions
1359 18:10:46.529009 <6>[ 0.242375] alternatives: applying system-wide alternatives
1360 18:10:46.546991 <6>[ 0.249557] Memory: 3557440K/4012396K available (17280K kernel code, 4898K rwdata, 11880K rodata, 10432K init, 742K bss, 187792K reserved, 262144K cma-reserved)
1361 18:10:46.547485 <6>[ 0.263901] devtmpfs: initialized
1362 18:10:46.557985 <6>[ 0.273090] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1363 18:10:46.563502 <6>[ 0.277447] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1364 18:10:46.569045 <6>[ 0.288240] 21392 pages in range for non-PLT usage
1365 18:10:46.574560 <6>[ 0.288250] 512912 pages in range for PLT usage
1366 18:10:46.580068 <6>[ 0.289798] pinctrl core: initialized pinctrl subsystem
1367 18:10:46.585578 <6>[ 0.301864] DMI not present or invalid.
1368 18:10:46.591151 <6>[ 0.306167] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1369 18:10:46.596651 <6>[ 0.310909] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1370 18:10:46.607669 <6>[ 0.317688] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1371 18:10:46.613217 <6>[ 0.325787] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1372 18:10:46.618712 <6>[ 0.333281] audit: initializing netlink subsys (disabled)
1373 18:10:46.629714 <5>[ 0.339010] audit: type=2000 audit(0.260:1): state=initialized audit_enabled=0 res=1
1374 18:10:46.635383 <6>[ 0.340426] thermal_sys: Registered thermal governor 'step_wise'
1375 18:10:46.640788 <6>[ 0.346786] thermal_sys: Registered thermal governor 'power_allocator'
1376 18:10:46.646359 <6>[ 0.353047] cpuidle: using governor menu
1377 18:10:46.651850 <6>[ 0.364085] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1378 18:10:46.657355 <6>[ 0.370960] ASID allocator initialised with 65536 entries
1379 18:10:46.661815 <6>[ 0.378460] Serial: AMBA PL011 UART driver
1380 18:10:46.673433 <6>[ 0.389105] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1381 18:10:46.688638 <6>[ 0.404525] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1382 18:10:46.697693 <6>[ 0.407181] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1383 18:10:46.703242 <6>[ 0.420326] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1384 18:10:46.714208 <6>[ 0.423566] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1385 18:10:46.719806 <6>[ 0.431986] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1386 18:10:46.730793 <6>[ 0.439610] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1387 18:10:46.736390 <6>[ 0.453211] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1388 18:10:46.741886 <6>[ 0.455432] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1389 18:10:46.752884 <6>[ 0.461913] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1390 18:10:46.758408 <6>[ 0.468892] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1391 18:10:46.763915 <6>[ 0.475360] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1392 18:10:46.769435 <6>[ 0.482344] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1393 18:10:46.774987 <6>[ 0.488814] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1394 18:10:46.786030 <6>[ 0.495799] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1395 18:10:46.786516 <6>[ 0.503816] ACPI: Interpreter disabled.
1396 18:10:46.791543 <6>[ 0.509292] iommu: Default domain type: Translated
1397 18:10:46.797050 <6>[ 0.511332] iommu: DMA domain TLB invalidation policy: strict mode
1398 18:10:46.802576 <5>[ 0.518082] SCSI subsystem initialized
1399 18:10:46.808123 <6>[ 0.521956] usbcore: registered new interface driver usbfs
1400 18:10:46.813627 <6>[ 0.527393] usbcore: registered new interface driver hub
1401 18:10:46.819156 <6>[ 0.532907] usbcore: registered new device driver usb
1402 18:10:46.824665 <6>[ 0.539174] pps_core: LinuxPPS API ver. 1 registered
1403 18:10:46.835670 <6>[ 0.543327] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1404 18:10:46.836176 <6>[ 0.552646] PTP clock support registered
1405 18:10:46.841249 <6>[ 0.556886] EDAC MC: Ver: 3.0.0
1406 18:10:46.846763 <6>[ 0.560545] scmi_core: SCMI protocol bus registered
1407 18:10:46.852261 <6>[ 0.566149] FPGA manager framework
1408 18:10:46.857766 <6>[ 0.568907] Advanced Linux Sound Architecture Driver Initialized.
1409 18:10:46.858244 <6>[ 0.575861] vgaarb: loaded
1410 18:10:46.863378 <6>[ 0.578400] clocksource: Switched to clocksource arch_sys_counter
1411 18:10:46.868797 <5>[ 0.584554] VFS: Disk quotas dquot_6.6.0
1412 18:10:46.874376 <6>[ 0.588541] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1413 18:10:46.879878 <6>[ 0.595749] pnp: PnP ACPI: disabled
1414 18:10:46.885407 <6>[ 0.604204] NET: Registered PF_INET protocol family
1415 18:10:46.890927 <6>[ 0.604569] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1416 18:10:46.901929 <6>[ 0.614733] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1417 18:10:46.907456 <6>[ 0.620742] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1418 18:10:46.918518 <6>[ 0.628639] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1419 18:10:46.924074 <6>[ 0.636877] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1420 18:10:46.935034 <6>[ 0.644672] TCP: Hash tables configured (established 32768 bind 32768)
1421 18:10:46.940564 <6>[ 0.651149] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1422 18:10:46.946094 <6>[ 0.657994] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1423 18:10:46.951614 <6>[ 0.665419] NET: Registered PF_UNIX/PF_LOCAL protocol family
1424 18:10:46.957137 <6>[ 0.671503] RPC: Registered named UNIX socket transport module.
1425 18:10:46.962671 <6>[ 0.677284] RPC: Registered udp transport module.
1426 18:10:46.968195 <6>[ 0.682189] RPC: Registered tcp transport module.
1427 18:10:46.973907 <6>[ 0.687103] RPC: Registered tcp-with-tls transport module.
1428 18:10:46.979383 <6>[ 0.692797] RPC: Registered tcp NFSv4.1 backchannel transport module.
1429 18:10:46.984813 <6>[ 0.699445] PCI: CLS 0 bytes, default 64
1430 18:10:46.990340 <6>[ 0.703768] Unpacking initramfs...
1431 18:10:46.995850 <6>[ 0.709942] kvm [1]: nv: 554 coarse grained trap handlers
1432 18:10:47.001473 <6>[ 0.713127] kvm [1]: IPA Size Limit: 40 bits
1433 18:10:47.001958 <6>[ 0.718732] kvm [1]: vgic interrupt IRQ9
1434 18:10:47.006869 <6>[ 0.721455] kvm [1]: Hyp nVHE mode initialized successfully
1435 18:10:47.012463 <5>[ 0.728668] Initialise system trusted keyrings
1436 18:10:47.017912 <6>[ 0.732127] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1437 18:10:47.023535 <6>[ 0.738748] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1438 18:10:47.028997 <5>[ 0.744847] NFS: Registering the id_resolver key type
1439 18:10:47.034482 <5>[ 0.749838] Key type id_resolver registered
1440 18:10:47.040075 <5>[ 0.754209] Key type id_legacy registered
1441 18:10:47.045559 <6>[ 0.758446] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1442 18:10:47.056584 <6>[ 0.765334] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1443 18:10:47.060434 <6>[ 0.773144] 9p: Installing v9fs 9p2000 file system support
1444 18:10:47.098212 <5>[ 0.819455] Key type asymmetric registered
1445 18:10:47.103751 <5>[ 0.819498] Asymmetric key parser 'x509' registered
1446 18:10:47.114735 <6>[ 0.823365] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1447 18:10:47.115265 <6>[ 0.830881] io scheduler mq-deadline registered
1448 18:10:47.120224 <6>[ 0.835625] io scheduler kyber registered
1449 18:10:47.125824 <6>[ 0.839882] io scheduler bfq registered
1450 18:10:47.132209 <6>[ 0.848133] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1451 18:10:47.148590 <6>[ 0.866076] ledtrig-cpu: registered to indicate activity on CPUs
1452 18:10:47.180336 <6>[ 0.897481] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1453 18:10:47.200693 <6>[ 0.910758] Serial: 8250/16550 driver, 4 ports<6>[ 0.915367] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1454 18:10:47.206247 <6>[ 0.924996] printk: legacy console [ttyAML0] enabled
1455 18:10:47.211762 <6>[ 0.924996] printk: legacy console [ttyAML0] enabled
1456 18:10:47.217322 <6>[ 0.929797] printk: legacy bootconsole [meson0] disabled
1457 18:10:47.222925 <6>[ 0.929797] printk: legacy bootconsole [meson0] disabled
1458 18:10:47.228415 <6>[ 0.943227] msm_serial: driver initialized
1459 18:10:47.233964 <6>[ 0.945757] SuperH (H)SCI(F) driver initialized
1460 18:10:47.234448 <6>[ 0.950277] STM32 USART driver initialized
1461 18:10:47.241779 <5>[ 0.956482] random: crng init done
1462 18:10:47.248833 <6>[ 0.965826] loop: module loaded
1463 18:10:47.249306 <6>[ 0.967156] megasas: 07.727.03.00-rc1
1464 18:10:47.254415 <6>[ 0.974600] tun: Universal TUN/TAP device driver, 1.6
1465 18:10:47.259910 <6>[ 0.975821] thunder_xcv, ver 1.0
1466 18:10:47.265540 <6>[ 0.977759] thunder_bgx, ver 1.0
1467 18:10:47.266018 <6>[ 0.981244] nicpf, ver 1.0
1468 18:10:47.270992 <6>[ 0.985795] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1469 18:10:47.276546 <6>[ 0.991617] hns3: Copyright (c) 2017 Huawei Corporation.
1470 18:10:47.282080 <6>[ 0.997204] hclge is initializing
1471 18:10:47.287679 <6>[ 1.000748] e1000: Intel(R) PRO/1000 Network Driver
1472 18:10:47.293196 <6>[ 1.005825] e1000: Copyright (c) 1999-2006 Intel Corporation.
1473 18:10:47.298711 <6>[ 1.011847] e1000e: Intel(R) PRO/1000 Network Driver
1474 18:10:47.304311 <6>[ 1.017005] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1475 18:10:47.309853 <6>[ 1.023187] igb: Intel(R) Gigabit Ethernet Network Driver
1476 18:10:47.315431 <6>[ 1.028790] igb: Copyright (c) 2007-2014 Intel Corporation.
1477 18:10:47.320902 <6>[ 1.034624] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1478 18:10:47.326594 <6>[ 1.041098] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1479 18:10:47.332054 <6>[ 1.047860] sky2: driver version 1.30
1480 18:10:47.337563 <6>[ 1.052936] VFIO - User Level meta-driver version: 0.3
1481 18:10:47.343114 <6>[ 1.060485] usbcore: registered new interface driver usb-storage
1482 18:10:47.348219 <6>[ 1.066708] i2c_dev: i2c /dev entries driver
1483 18:10:47.362053 <6>[ 1.077754] sdhci: Secure Digital Host Controller Interface driver
1484 18:10:47.362528 <6>[ 1.078578] sdhci: Copyright(c) Pierre Ossman
1485 18:10:47.373103 <6>[ 1.084279] Synopsys Designware Multimedia Card Interface Driver
1486 18:10:47.378639 <6>[ 1.090848] sdhci-pltfm: SDHCI platform and OF driver helper
1487 18:10:47.379111 <6>[ 1.098488] meson-sm: secure-monitor enabled
1488 18:10:47.391648 <6>[ 1.101028] usbcore: registered new interface driver usbhid
1489 18:10:47.392151 <6>[ 1.105624] usbhid: USB HID core driver
1490 18:10:47.399207 <6>[ 1.120482] NET: Registered PF_PACKET protocol family
1491 18:10:47.404759 <6>[ 1.120573] 9pnet: Installing 9P2000 support
1492 18:10:47.411939 <5>[ 1.124735] Key type dns_resolver registered
1493 18:10:47.419323 <6>[ 1.136401] registered taskstats version 1
1494 18:10:47.419803 <5>[ 1.136561] Loading compiled-in X.509 certificates
1495 18:10:47.426689 <6>[ 1.145194] Demotion targets for Node 0: null
1496 18:10:47.466868 <6>[ 1.188091] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1497 18:10:47.472364 <6>[ 1.188135] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1498 18:10:47.483436 <4>[ 1.198297] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1499 18:10:47.489027 <4>[ 1.200931] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1500 18:10:47.494578 <6>[ 1.208470] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1501 18:10:47.500109 <6>[ 1.217689] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1502 18:10:47.511215 <6>[ 1.221204] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1503 18:10:47.522308 <6>[ 1.229172] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1504 18:10:47.527932 <6>[ 1.238697] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1505 18:10:47.533396 <6>[ 1.244919] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1506 18:10:47.538986 <6>[ 1.250542] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1507 18:10:47.544587 <6>[ 1.258428] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1508 18:10:47.550023 <6>[ 1.265659] hub 1-0:1.0: USB hub found
1509 18:10:47.555582 <6>[ 1.269194] hub 1-0:1.0: 2 ports detected
1510 18:10:47.561112 <6>[ 1.275262] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1511 18:10:47.566665 <6>[ 1.282155] hub 2-0:1.0: USB hub found
1512 18:10:47.571745 <6>[ 1.285739] hub 2-0:1.0: 1 port detected
1513 18:10:47.592670 <6>[ 1.311320] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1514 18:10:47.608793 <6>[ 1.326752] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1515 18:10:47.644343 <6>[ 1.361917] Trying to probe devices needed for running init ...
1516 18:10:47.800550 <6>[ 1.518436] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1517 18:10:47.946012 <6>[ 1.661690] mmc0: new ultra high speed SDR104 SDXC card at address e624
1518 18:10:47.951267 <6>[ 1.663651] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1519 18:10:47.951787 <6>[ 1.669252] mmcblk0: p1
1520 18:10:47.958084 <6>[ 1.678452] Freeing initrd memory: 22876K
1521 18:10:47.992293 <6>[ 1.713521] hub 1-1:1.0: USB hub found
1522 18:10:47.997077 <6>[ 1.713835] hub 1-1:1.0: 4 ports detected
1523 18:10:48.057602 <6>[ 1.774542] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1524 18:10:48.104912 <6>[ 1.826167] hub 2-1:1.0: USB hub found
1525 18:10:48.110006 <6>[ 1.826997] hub 2-1:1.0: 4 ports detected
1526 18:10:59.925533 <6>[ 13.646491] clk: Disabling unused clocks
1527 18:10:59.930882 <6>[ 13.646731] PM: genpd: Disabling unused power domains
1528 18:10:59.939229 <6>[ 13.650367] ALSA device list:
1529 18:10:59.939786 <6>[ 13.653563] No soundcards found.
1530 18:10:59.946214 <6>[ 13.667444] Freeing unused kernel memory: 10432K
1531 18:10:59.951876 <6>[ 13.667570] Run /init as init process
1532 18:10:59.959559 Loading, please wait...
1533 18:10:59.993323 Starting systemd-udevd version 252.22-1~deb12u1
1534 18:11:00.382379 <6>[ 14.101376] mc: Linux media interface: v0.10
1535 18:11:00.399403 <6>[ 14.117316] videodev: Linux video capture interface: v2.00
1536 18:11:00.413522 <4>[ 14.127108] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1537 18:11:00.439644 <6>[ 14.155232] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1538 18:11:00.445029 <6>[ 14.156478] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1539 18:11:00.449651 <6>[ 14.164222] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1540 18:11:00.457287 <6>[ 14.169210] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1541 18:11:00.468696 <6>[ 14.184292] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1542 18:11:00.474244 <6>[ 14.188097] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1543 18:11:00.483263 <6>[ 14.193516] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1544 18:11:00.488807 <6>[ 14.199328] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1545 18:11:00.494288 <6>[ 14.207034] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1546 18:11:00.503362 <6>[ 14.212449] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1547 18:11:00.508849 <6>[ 14.219707] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1548 18:11:00.514396 <6>[ 14.226589] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1549 18:11:00.519937 <6>[ 14.228040] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1550 18:11:00.531040 <4>[ 14.228078] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1551 18:11:00.536567 <3>[ 14.231082] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1552 18:11:00.542095 <6>[ 14.232546] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1553 18:11:00.553225 <6>[ 14.260834] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1554 18:11:00.558794 <6>[ 14.262012] panfrost ffe40000.gpu: clock rate = 24000000
1555 18:11:00.564386 <3>[ 14.276344] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1556 18:11:00.575565 <6>[ 14.279015] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1557 18:11:00.581107 <6>[ 14.286069] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1558 18:11:00.592266 <6>[ 14.301645] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1559 18:11:00.603277 <6>[ 14.310016] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1560 18:11:00.614395 <6>[ 14.317488] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1561 18:11:00.619947 <6>[ 14.322054] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1562 18:11:00.620464 <6>[ 14.337639] Registered IR keymap rc-empty
1563 18:11:00.630949 <6>[ 14.345225] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1564 18:11:00.642054 <6>[ 14.345586] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1565 18:11:00.647615 <6>[ 14.350094] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 1
1566 18:11:00.653135 <3>[ 14.358443] meson-drm ff900000.vpu: DSI transceiver device is disabled
1567 18:11:00.658680 <6>[ 14.358952] meson-vrtc ff8000a8.rtc: registered as rtc0
1568 18:11:00.669698 <6>[ 14.359114] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1569 18:11:00.675322 <6>[ 14.360747] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1570 18:11:00.680879 <6>[ 14.372401] usbcore: registered new device driver onboard-usb-dev
1571 18:11:00.686492 <6>[ 14.377904] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 0
1572 18:11:00.691966 <6>[ 14.378245] rc rc0: sw decoder init
1573 18:11:00.697535 <6>[ 14.378292] meson-ir ff808000.ir: receiver initialized
1574 18:11:00.704836 <6>[ 14.406779] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1575 18:11:00.894464 <6>[ 14.591197] Console: switching to colour frame buffer device 128x48
1576 18:11:00.905551 <6>[ 14.605820] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1577 18:11:00.910844 <6>[ 14.622032] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1578 18:11:01.025321 <4>[ 14.746444] rc rc0: two consecutive events of type space
1579 18:11:01.144318 <6>[ 14.865497] hub 1-1:1.0: USB hub found
1580 18:11:01.149989 <6>[ 14.865854] hub 1-1:1.0: 4 ports detected
1581 18:11:01.290984 <4>[ 15.006663] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1582 18:11:01.296457 <3>[ 15.009062] onboard-usb-dev 1-1: Failed to suspend device, error -32
1583 18:11:01.303508 <3>[ 15.015479] onboard-usb-dev 1-1: can't set config #1, error -71
1584 18:11:01.322682 <4>[ 15.038446] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1585 18:11:01.328233 <6>[ 15.040766] onboard-usb-dev 1-1: USB disconnect, device number 2
1586 18:11:01.333786 <3>[ 15.046941] onboard-usb-dev 1-1: Failed to suspend device, error -32
1587 18:11:01.339310 Begin: Loading essential drivers ... done.
1588 18:11:01.344897 Begin: Running /scripts/init-premount ... done.
1589 18:11:01.350462 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1590 18:11:01.356006 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1591 18:11:01.361533 Device /sys/class/net/end0 found
1592 18:11:01.361981 done.
1593 18:11:01.369894 Begin: Waiting up to 180 secs for any network device to become available ... done.
1594 18:11:01.412264 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.124033] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1595 18:11:01.412733
1596 18:11:01.452693 <6>[ 15.169505] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1597 18:11:01.501455 <6>[ 15.214500] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=28)
1598 18:11:01.514795 <6>[ 15.230538] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1599 18:11:01.520353 <6>[ 15.232726] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1600 18:11:01.529618 <6>[ 15.240455] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1601 18:11:01.589441 <6>[ 15.306446] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1602 18:11:01.784496 <6>[ 15.505651] hub 1-1:1.0: USB hub found
1603 18:11:01.790154 <6>[ 15.506000] hub 1-1:1.0: 4 ports detected
1604 18:11:03.138988 IP-Config: no response after 2 secs - giving up
1605 18:11:03.180312 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1606 18:11:04.484982 <6>[ 18.200159] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1607 18:11:05.389931 IP-Config: end0 guessed broadcast address 192.168.6.255
1608 18:11:05.395820 IP-Config: end0 complete (dhcp from 192.168.6.1):
1609 18:11:05.401070 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1610 18:11:05.412147 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1611 18:11:05.412613 rootserver: 192.168.6.1 rootpath:
1612 18:11:05.415442 filename :
1613 18:11:05.514725 done.
1614 18:11:05.525584 Begin: Running /scripts/nfs-bottom ... done.
1615 18:11:05.539505 Begin: Running /scripts/init-bottom ... done.
1616 18:11:05.866809 <30>[ 19.583289] systemd[1]: System time before build time, advancing clock.
1617 18:11:05.915755 <6>[ 19.636778] NET: Registered PF_INET6 protocol family
1618 18:11:05.921325 <6>[ 19.638584] Segment Routing with IPv6
1619 18:11:05.926690 <6>[ 19.640285] In-situ OAM (IOAM) with IPv6
1620 18:11:06.012806 <30>[ 19.702693] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1621 18:11:06.018260 <30>[ 19.730468] systemd[1]: Detected architecture arm64.
1622 18:11:06.018862
1623 18:11:06.026077 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1624 18:11:06.026643
1625 18:11:06.030807 <30>[ 19.748107] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1626 18:11:06.685139 <30>[ 20.401370] systemd[1]: Queued start job for default target graphical.target.
1627 18:11:06.713248 <30>[ 20.428815] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1628 18:11:06.721772 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1629 18:11:06.732854 <30>[ 20.447409] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1630 18:11:06.740203 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1631 18:11:06.751793 <30>[ 20.467464] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1632 18:11:06.765125 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1633 18:11:06.770620 <30>[ 20.487163] systemd[1]: Created slice user.slice - User and Session Slice.
1634 18:11:06.777180 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1635 18:11:06.788132 <30>[ 20.502674] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1636 18:11:06.799545 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1637 18:11:06.810771 <30>[ 20.522601] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1638 18:11:06.817398 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1639 18:11:06.839498 <30>[ 20.542585] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1640 18:11:06.845180 <30>[ 20.556651] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1641 18:11:06.852860 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1642 18:11:06.863839 <30>[ 20.578495] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1643 18:11:06.870398 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1644 18:11:06.886856 <30>[ 20.602516] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1645 18:11:06.895313 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1646 18:11:06.906944 <30>[ 20.622535] systemd[1]: Reached target paths.target - Path Units.
1647 18:11:06.911477 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1648 18:11:06.922806 <30>[ 20.638508] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1649 18:11:06.929046 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1650 18:11:06.937351 <30>[ 20.654492] systemd[1]: Reached target slices.target - Slice Units.
1651 18:11:06.945556 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1652 18:11:06.951089 <30>[ 20.670520] systemd[1]: Reached target swap.target - Swaps.
1653 18:11:06.958940 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1654 18:11:06.970843 <30>[ 20.686529] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1655 18:11:06.979685 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1656 18:11:06.994967 <30>[ 20.710683] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1657 18:11:07.004301 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1658 18:11:07.015954 <30>[ 20.731633] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1659 18:11:07.029989 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1660 18:11:07.035527 <30>[ 20.751347] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1661 18:11:07.048691 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1662 18:11:07.054302 <30>[ 20.770840] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1663 18:11:07.061053 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1664 18:11:07.072108 <30>[ 20.787398] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1665 18:11:07.080861 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1666 18:11:07.092657 <30>[ 20.808342] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1667 18:11:07.098279 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1668 18:11:07.112695 <30>[ 20.826735] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1669 18:11:07.119601 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1670 18:11:07.158970 <30>[ 20.874621] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1671 18:11:07.164698 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1672 18:11:07.177389 <30>[ 20.893084] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1673 18:11:07.184066 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1674 18:11:07.197344 <30>[ 20.913010] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1675 18:11:07.203879 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1676 18:11:07.224724 <30>[ 20.934799] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1677 18:11:07.235747 <30>[ 20.948275] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1678 18:11:07.242913 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1679 18:11:07.261613 <30>[ 20.977305] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1680 18:11:07.269635 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1681 18:11:07.281623 <30>[ 20.997317] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1682 18:11:07.289262 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1683 18:11:07.301545 <30>[ 21.017174] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1684 18:11:07.307069 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1685 18:11:07.317464 <6>[ 21.029850] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1686 18:11:07.329763 <30>[ 21.045411] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1687 18:11:07.338063 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1688 18:11:07.349485 <30>[ 21.065158] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1689 18:11:07.356777 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1690 18:11:07.369376 <30>[ 21.084966] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1691 18:11:07.374917 Starting [0;1;39mmodpro<6>[ 21.090312] fuse: init (API version 7.41)
1692 18:11:07.378835 be@loop.ser…e[0m - Load Kernel Module loop...
1693 18:11:07.395520 <30>[ 21.111224] systemd[1]: Starting systemd-journald.service - Journal Service...
1694 18:11:07.401968 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1695 18:11:07.417983 <30>[ 21.133640] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1696 18:11:07.425553 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1697 18:11:07.440381 <30>[ 21.155996] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1698 18:11:07.449894 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1699 18:11:07.461248 <30>[ 21.176882] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1700 18:11:07.469984 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1701 18:11:07.482626 <30>[ 21.198322] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1702 18:11:07.490772 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1703 18:11:07.503702 <30>[ 21.219385] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
1704 18:11:07.510940 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1705 18:11:07.527547 <30>[ 21.243186] systemd[1]: Started systemd-journald.service - Journal Service.
1706 18:11:07.534403 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1707 18:11:07.546879 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1708 18:11:07.564050 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1709 18:11:07.580607 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1710 18:11:07.593637 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1711 18:11:07.605715 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1712 18:11:07.617626 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1713 18:11:07.629694 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1714 18:11:07.641488 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1715 18:11:07.653476 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1716 18:11:07.664839 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1717 18:11:07.676732 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1718 18:11:07.688824 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1719 18:11:07.700674 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1720 18:11:07.750647 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1721 18:11:07.763156 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1722 18:11:07.780057 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1723 18:11:07.796560 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1724 18:11:07.820803 <46>[ 21.536500] systemd-journald[228]: Received client request to flush runtime journal.
1725 18:11:07.828313 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1726 18:11:07.845709 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1727 18:11:07.899090 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1728 18:11:07.916257 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1729 18:11:07.928117 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1730 18:11:07.944523 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1731 18:11:07.956657 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1732 18:11:08.025331 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1733 18:11:08.068057 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1734 18:11:08.088933 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1735 18:11:08.141963 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1736 18:11:08.158887 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1737 18:11:08.173798 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1738 18:11:08.233538 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1739 18:11:08.245884 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1740 18:11:08.462693 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1741 18:11:08.502686 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1742 18:11:08.553134 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1743 18:11:08.581101 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1744 18:11:08.637584 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1745 18:11:08.651482 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1746 18:11:08.665729 <5>[ 22.382132] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1747 18:11:08.712841 <5>[ 22.428679] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1748 18:11:08.718523 <5>[ 22.429368] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1749 18:11:08.724109 <4>[ 22.441040] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1750 18:11:08.729651 <6>[ 22.445299] cfg80211: failed to load regulatory.db
1751 18:11:08.739420 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1752 18:11:08.784080 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1753 18:11:08.789697 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1754 18:11:08.842579 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1755 18:11:08.875249 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1756 18:11:08.882482 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1757 18:11:08.907873 <46>[ 22.614625] systemd-journald[228]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1758 18:11:08.924582 <46>[ 22.627058] systemd-journald[228]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1759 18:11:08.930312 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1760 18:11:08.946437 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1761 18:11:08.996797 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1762 18:11:09.010472 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1763 18:11:09.044092 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1764 18:11:09.061673 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1765 18:11:09.076304 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1766 18:11:09.082446 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1767 18:11:09.110746 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1768 18:11:09.117342 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1769 18:11:09.126363 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1770 18:11:09.137220 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1771 18:11:09.196915 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1772 18:11:09.213516 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1773 18:11:09.231726 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1774 18:11:09.243690 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1775 18:11:09.295885 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1776 18:11:09.302271 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1777 18:11:09.337946 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1778 18:11:09.343072 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1779 18:11:09.356471 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1780 18:11:09.372529 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1781 18:11:09.378193 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1782 18:11:09.401738 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1783 18:11:09.420700 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1784 18:11:09.427052 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1785 18:11:09.442964 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1786 18:11:09.455441 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1787 18:11:09.503069 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1788 18:11:09.562258 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1789 18:11:09.649415
1790 18:11:09.650071 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1791 18:11:09.650507
1792 18:11:09.656456 debian-bookworm-arm64 login: root (automatic login)
1793 18:11:09.656775
1794 18:11:09.786602 Linux debian-bookworm-arm64 6.12.0-rc1 #1 SMP PREEMPT Tue Nov 5 17:11:02 UTC 2024 aarch64
1795 18:11:09.787235
1796 18:11:09.792231 The programs included with the Debian GNU/Linux system are free software;
1797 18:11:09.801036 the exact distribution terms for each program are described in the
1798 18:11:09.801716 individual files in /usr/share/doc/*/copyright.
1799 18:11:09.802308
1800 18:11:09.806794 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1801 18:11:09.810987 permitted by applicable law.
1802 18:11:10.437039 Matched prompt #10: / #
1804 18:11:10.438578 Setting prompt string to ['/ #']
1805 18:11:10.439164 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1807 18:11:10.440630 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1808 18:11:10.441245 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
1809 18:11:10.441760 Setting prompt string to ['/ #']
1810 18:11:10.442191 Forcing a shell prompt, looking for ['/ #']
1812 18:11:10.493168 / #
1813 18:11:10.493912 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1814 18:11:10.494451 Waiting using forced prompt support (timeout 00:02:30)
1815 18:11:10.498410
1816 18:11:10.499003 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1817 18:11:10.499336 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
1818 18:11:10.499586 Sending with 10 millisecond of delay
1820 18:11:15.487397 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/941220/extract-nfsrootfs-61pgpkhz'
1821 18:11:15.498401 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/941220/extract-nfsrootfs-61pgpkhz'
1822 18:11:15.499191 Sending with 10 millisecond of delay
1824 18:11:17.596685 / # export NFS_SERVER_IP='192.168.6.2'
1825 18:11:17.607662 export NFS_SERVER_IP='192.168.6.2'
1826 18:11:17.608334 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1827 18:11:17.608724 end: 2.4 uboot-commands (duration 00:01:56) [common]
1828 18:11:17.609354 end: 2 uboot-action (duration 00:01:56) [common]
1829 18:11:17.609953 start: 3 lava-test-retry (timeout 00:06:45) [common]
1830 18:11:17.610608 start: 3.1 lava-test-shell (timeout 00:06:45) [common]
1831 18:11:17.611136 Using namespace: common
1833 18:11:17.712507 / # #
1834 18:11:17.713308 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1835 18:11:17.719275 #
1836 18:11:17.720111 Using /lava-941220
1838 18:11:17.821426 / # export SHELL=/bin/bash
1839 18:11:17.828213 export SHELL=/bin/bash
1841 18:11:17.930365 / # . /lava-941220/environment
1842 18:11:17.935642 . /lava-941220/environment
1844 18:11:18.041708 / # /lava-941220/bin/lava-test-runner /lava-941220/0
1845 18:11:18.042752 Test shell timeout: 10s (minimum of the action and connection timeout)
1846 18:11:18.045895 /lava-941220/bin/lava-test-runner /lava-941220/0
1847 18:11:18.252018 + export TESTRUN_ID=0_timesync-off
1848 18:11:18.259841 + TESTRUN_ID=0_timesync-off
1849 18:11:18.260595 + cd /lava-941220/0/tests/0_timesync-off
1850 18:11:18.261143 ++ cat uuid
1851 18:11:18.269903 + UUID=941220_1.6.2.4.1
1852 18:11:18.270628 + set +x
1853 18:11:18.278386 <LAVA_SIGNAL_STARTRUN 0_timesync-off 941220_1.6.2.4.1>
1854 18:11:18.279145 + systemctl stop systemd-timesyncd
1855 18:11:18.280062 Received signal: <STARTRUN> 0_timesync-off 941220_1.6.2.4.1
1856 18:11:18.280667 Starting test lava.0_timesync-off (941220_1.6.2.4.1)
1857 18:11:18.281344 Skipping test definition patterns.
1858 18:11:18.335663 + set +x
1859 18:11:18.336388 <LAVA_SIGNAL_ENDRUN 0_timesync-off 941220_1.6.2.4.1>
1860 18:11:18.337255 Received signal: <ENDRUN> 0_timesync-off 941220_1.6.2.4.1
1861 18:11:18.337911 Ending use of test pattern.
1862 18:11:18.338480 Ending test lava.0_timesync-off (941220_1.6.2.4.1), duration 0.06
1864 18:11:18.420688 + export TESTRUN_ID=1_kselftest-alsa
1865 18:11:18.427219 + TESTRUN_ID=1_kselftest-alsa
1866 18:11:18.427900 + cd /lava-941220/0/tests/1_kselftest-alsa
1867 18:11:18.428503 ++ cat uuid
1868 18:11:18.432740 + UUID=941220_1.6.2.4.5
1869 18:11:18.433341 + set +x
1870 18:11:18.435234 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 941220_1.6.2.4.5>
1871 18:11:18.436113 Received signal: <STARTRUN> 1_kselftest-alsa 941220_1.6.2.4.5
1872 18:11:18.436702 Starting test lava.1_kselftest-alsa (941220_1.6.2.4.5)
1873 18:11:18.437366 Skipping test definition patterns.
1874 18:11:18.440916 + cd ./automated/linux/kselftest/
1875 18:11:18.468949 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-49-g76c6217c31266/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g lee-mfd -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1876 18:11:18.503067 INFO: install_deps skipped
1877 18:11:18.622344 --2024-11-05 18:11:18-- http://storage.kernelci.org/lee-mfd/for-mfd-next/ib-mfd-gpio-i2c-watchdog-v6.13-49-g76c6217c31266/arm64/defconfig/gcc-12/kselftest.tar.xz
1878 18:11:18.644087 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1879 18:11:18.790249 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1880 18:11:18.932614 HTTP request sent, awaiting response... 200 OK
1881 18:11:18.933476 Length: 5043688 (4.8M) [application/octet-stream]
1882 18:11:18.937972 Saving to: 'kselftest_armhf.tar.gz'
1883 18:11:18.938616
1884 18:11:20.097912
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 44.73K 156KB/s
kselftest_armhf.tar 4%[ ] 218.67K 382KB/s
kselftest_armhf.tar 18%[==> ] 893.67K 1.02MB/s
kselftest_armhf.tar 72%[=============> ] 3.51M 3.06MB/s
kselftest_armhf.tar 100%[===================>] 4.81M 4.15MB/s in 1.2s
1885 18:11:20.098565
1886 18:11:20.173083 2024-11-05 18:11:20 (4.15 MB/s) - 'kselftest_armhf.tar.gz' saved [5043688/5043688]
1887 18:11:20.173647
1888 18:11:28.678869 skiplist:
1889 18:11:28.679463 ========================================
1890 18:11:28.684615 ========================================
1891 18:11:28.725319 alsa:mixer-test
1892 18:11:28.725809 alsa:pcm-test
1893 18:11:28.726226 alsa:test-pcmtest-driver
1894 18:11:28.729336 alsa:utimer-test
1895 18:11:28.743419 ============== Tests to run ===============
1896 18:11:28.743900 alsa:mixer-test
1897 18:11:28.748982 alsa:pcm-test
1898 18:11:28.749426 alsa:test-pcmtest-driver
1899 18:11:28.749832 alsa:utimer-test
1900 18:11:28.757115 ===========End Tests to run ===============
1901 18:11:28.757565 shardfile-alsa pass
1902 18:11:28.865403 <12>[ 42.584469] kselftest: Running tests in alsa
1903 18:11:28.872466 TAP version 13
1904 18:11:28.882750 1..4
1905 18:11:28.904177 # timeout set to 45
1906 18:11:28.904638 # selftests: alsa: mixer-test
1907 18:11:29.100493 # TAP version 13
1908 18:11:29.101038 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1909 18:11:29.105966 # 1..427
1910 18:11:29.106410 # ok 1 get_value.LCALTA.60
1911 18:11:29.106818 # # LCALTA.60 TDMOUT_A SRC SEL
1912 18:11:29.111561 # ok 2 name.LCALTA.60
1913 18:11:29.112043 # ok 3 write_default.LCALTA.60
1914 18:11:29.115030 # ok 4 write_valid.LCALTA.60
1915 18:11:29.120483 # ok 5 write_invalid.LCALTA.60
1916 18:11:29.121121 # ok 6 event_missing.LCALTA.60
1917 18:11:29.126087 # ok 7 event_spurious.LCALTA.60
1918 18:11:29.126656 # ok 8 get_value.LCALTA.59
1919 18:11:29.131753 # # LCALTA.59 TDMOUT_B SRC SEL
1920 18:11:29.132374 # ok 9 name.LCALTA.59
1921 18:11:29.135272 # ok 10 write_default.LCALTA.59
1922 18:11:29.135850 # ok 11 write_valid.LCALTA.59
1923 18:11:29.140753 # ok 12 write_invalid.LCALTA.59
1924 18:11:29.141343 # ok 13 event_missing.LCALTA.59
1925 18:11:29.146387 # ok 14 event_spurious.LCALTA.59
1926 18:11:29.146973 # ok 15 get_value.LCALTA.58
1927 18:11:29.151852 # # LCALTA.58 TDMOUT_C SRC SEL
1928 18:11:29.152455 # ok 16 name.LCALTA.58
1929 18:11:29.155607 # ok 17 write_default.LCALTA.58
1930 18:11:29.160968 # ok 18 write_valid.LCALTA.58
1931 18:11:29.161562 # ok 19 write_invalid.LCALTA.58
1932 18:11:29.166656 # ok 20 event_missing.LCALTA.58
1933 18:11:29.167274 # ok 21 event_spurious.LCALTA.58
1934 18:11:29.172150 # ok 22 get_value.LCALTA.57
1935 18:11:29.172775 # # LCALTA.57 TDMIN_A SRC SEL
1936 18:11:29.173315 # ok 23 name.LCALTA.57
1937 18:11:29.177633 # ok 24 write_default.LCALTA.57
1938 18:11:29.178203 # ok 25 write_valid.LCALTA.57
1939 18:11:29.183217 # ok 26 write_invalid.LCALTA.57
1940 18:11:29.183785 # ok 27 event_missing.LCALTA.57
1941 18:11:29.188758 # ok 28 event_spurious.LCALTA.57
1942 18:11:29.189314 # ok 29 get_value.LCALTA.56
1943 18:11:29.194298 # # LCALTA.56 TDMIN_B SRC SEL
1944 18:11:29.194873 # ok 30 name.LCALTA.56
1945 18:11:29.210844 # ok 31 write_defaul<3>[ 42.917248] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1946 18:11:29.211482 t.LCALTA.56
1947 18:11:29.216311 # ok 32 write_valid.LCALTA.56
1948 18:11:29.216880 # ok 33 write_invalid.LCALTA.56
1949 18:11:29.221903 # ok 34 event_missing.LCALTA.56
1950 18:11:29.222503 # ok 35 event_spurious.LCALTA.56
1951 18:11:29.227426 # ok 36 get_value.LCALTA.55
1952 18:11:29.228026 # # LCALTA.55 TDMIN_C SRC SEL
1953 18:11:29.228567 # ok 37 name.LCALTA.55
1954 18:11:29.232956 # ok 38 write_default.LCALTA.55
1955 18:11:29.233548 # ok 39 write_valid.LCALTA.55
1956 18:11:29.238557 # ok 40 write_invalid.LCALTA.55
1957 18:11:29.239164 # ok 41 event_missing.LCALTA.55
1958 18:11:29.244101 # ok 42 event_spurious.LCALTA.55
1959 18:11:29.244704 # ok 43 get_value.LCALTA.54
1960 18:11:29.249617 # # LCALTA.54 ACODEC Left DAC Sel
1961 18:11:29.250093 # ok 44 name.LCALTA.54
1962 18:11:29.255183 # ok 45 write_default.LCALTA.54
1963 18:11:29.255639 # ok 46 write_valid.LCALTA.54
1964 18:11:29.260699 # ok 47 write_invalid.LCALTA.54
1965 18:11:29.261173 # ok 48 event_missing.LCALTA.54
1966 18:11:29.266206 # ok 49 event_spurious.LCALTA.54
1967 18:11:29.266650 # ok 50 get_value.LCALTA.53
1968 18:11:29.271773 # # LCALTA.53 ACODEC Right DAC Sel
1969 18:11:29.272246 # ok 51 name.LCALTA.53
1970 18:11:29.277323 # ok 52 write_default.LCALTA.53
1971 18:11:29.277774 # ok 53 write_valid.LCALTA.53
1972 18:11:29.282876 # ok 54 write_invalid.LCALTA.53
1973 18:11:29.283313 # ok 55 event_missing.LCALTA.53
1974 18:11:29.288419 # ok 56 event_spurious.LCALTA.53
1975 18:11:29.288862 # ok 57 get_value.LCALTA.52
1976 18:11:29.293962 # # LCALTA.52 TOACODEC OUT EN Switch
1977 18:11:29.294402 # ok 58 name.LCALTA.52
1978 18:11:29.299495 # ok 59 write_default.LCALTA.52
1979 18:11:29.299933 # ok 60 write_valid.LCALTA.52
1980 18:11:29.305045 # ok 61 write_invalid.LCALTA.52
1981 18:11:29.305487 # ok 62 event_missing.LCALTA.52
1982 18:11:29.310619 # ok 63 event_spurious.LCALTA.52
1983 18:11:29.311094 # ok 64 get_value.LCALTA.51
1984 18:11:29.316201 # # LCALTA.51 TOACODEC SRC
1985 18:11:29.316642 # ok 65 name.LCALTA.51
1986 18:11:29.321704 # ok 66 write_default.LCALTA.51
1987 18:11:29.322135 # ok 67 write_valid.LCALTA.51
1988 18:11:29.327293 # ok 68 write_invalid.LCALTA.51
1989 18:11:29.327739 # ok 69 event_missing.LCALTA.51
1990 18:11:29.332857 # ok 70 event_spurious.LCALTA.51
1991 18:11:29.333481 # ok 71 get_value.LCALTA.50
1992 18:11:29.338379 # # LCALTA.50 TOHDMITX SPDIF SRC
1993 18:11:29.338961 # ok 72 name.LCALTA.50
1994 18:11:29.343927 # ok 73 write_default.LCALTA.50
1995 18:11:29.344632 # ok 74 write_valid.LCALTA.50
1996 18:11:29.349465 # ok 75 write_invalid.LCALTA.50
1997 18:11:29.350060 # ok 76 event_missing.LCALTA.50
1998 18:11:29.354966 # ok 77 event_spurious.LCALTA.50
1999 18:11:29.355550 # ok 78 get_value.LCALTA.49
2000 18:11:29.360557 # # LCALTA.49 TOHDMITX Switch
2001 18:11:29.361122 # ok 79 name.LCALTA.49
2002 18:11:29.361658 # ok 80 write_default.LCALTA.49
2003 18:11:29.366086 # ok 81 write_valid.LCALTA.49
2004 18:11:29.366655 # ok 82 write_invalid.LCALTA.49
2005 18:11:29.371624 # ok 83 event_missing.LCALTA.49
2006 18:11:29.372211 # ok 84 event_spurious.LCALTA.49
2007 18:11:29.377234 # ok 85 get_value.LCALTA.48
2008 18:11:29.377851 # # LCALTA.48 TOHDMITX I2S SRC
2009 18:11:29.382726 # ok 86 name.LCALTA.48
2010 18:11:29.383312 # ok 87 write_default.LCALTA.48
2011 18:11:29.388268 # ok 88 write_valid.LCALTA.48
2012 18:11:29.388845 # ok 89 write_invalid.LCALTA.48
2013 18:11:29.393826 # ok 90 event_missing.LCALTA.48
2014 18:11:29.394407 # ok 91 event_spurious.LCALTA.48
2015 18:11:29.399380 # ok 92 get_value.LCALTA.47
2016 18:11:29.399938 # # LCALTA.47 TODDR_C SRC SEL
2017 18:11:29.404908 # ok 93 name.LCALTA.47
2018 18:11:29.405483 # ok 94 write_default.LCALTA.47
2019 18:11:29.410464 # ok 95 write_valid.LCALTA.47
2020 18:11:29.410954 # ok 96 write_invalid.LCALTA.47
2021 18:11:29.416021 # ok 97 event_missing.LCALTA.47
2022 18:11:29.416474 # ok 98 event_spurious.LCALTA.47
2023 18:11:29.421561 # ok 99 get_value.LCALTA.46
2024 18:11:29.421997 # # LCALTA.46 TODDR_B SRC SEL
2025 18:11:29.427098 # ok 100 name.LCALTA.46
2026 18:11:29.427533 # ok 101 write_default.LCALTA.46
2027 18:11:29.432647 # ok 102 write_valid.LCALTA.46
2028 18:11:29.433076 # ok 103 write_invalid.LCALTA.46
2029 18:11:29.438177 # ok 104 event_missing.LCALTA.46
2030 18:11:29.438605 # ok 105 event_spurious.LCALTA.46
2031 18:11:29.443883 # ok 106 get_value.LCALTA.45
2032 18:11:29.444424 # # LCALTA.45 TODDR_A SRC SEL
2033 18:11:29.449259 # ok 107 name.LCALTA.45
2034 18:11:29.449713 # ok 108 write_default.LCALTA.45
2035 18:11:29.454854 # ok 109 write_valid.LCALTA.45
2036 18:11:29.455282 # ok 110 write_invalid.LCALTA.45
2037 18:11:29.460390 # ok 111 event_missing.LCALTA.45
2038 18:11:29.460821 # ok 112 event_spurious.LCALTA.45
2039 18:11:29.465915 # ok 113 get_value.LCALTA.44
2040 18:11:29.466353 # # LCALTA.44 FRDDR_C SINK 3 SEL
2041 18:11:29.471450 # ok 114 name.LCALTA.44
2042 18:11:29.471871 # ok 115 write_default.LCALTA.44
2043 18:11:29.477031 # ok 116 write_valid.LCALTA.44
2044 18:11:29.477460 # ok 117 write_invalid.LCALTA.44
2045 18:11:29.482574 # ok 118 event_missing.LCALTA.44
2046 18:11:29.483054 # ok 119 event_spurious.LCALTA.44
2047 18:11:29.488111 # ok 120 get_value.LCALTA.43
2048 18:11:29.488577 # # LCALTA.43 FRDDR_C SINK 2 SEL
2049 18:11:29.493626 # ok 121 name.LCALTA.43
2050 18:11:29.494059 # ok 122 write_default.LCALTA.43
2051 18:11:29.499163 # ok 123 write_valid.LCALTA.43
2052 18:11:29.499622 # ok 124 write_invalid.LCALTA.43
2053 18:11:29.505338 # ok 125 event_missing.LCALTA.43
2054 18:11:29.505805 # ok 126 event_spurious.LCALTA.43
2055 18:11:29.510284 # ok 127 get_value.LCALTA.42
2056 18:11:29.510708 # # LCALTA.42 FRDDR_C SINK 1 SEL
2057 18:11:29.515866 # ok 128 name.LCALTA.42
2058 18:11:29.516389 # ok 129 write_default.LCALTA.42
2059 18:11:29.521490 # ok 130 write_valid.LCALTA.42
2060 18:11:29.521956 # ok 131 write_invalid.LCALTA.42
2061 18:11:29.526973 # ok 132 event_missing.LCALTA.42
2062 18:11:29.527411 # ok 133 event_spurious.LCALTA.42
2063 18:11:29.532501 # ok 134 get_value.LCALTA.41
2064 18:11:29.532964 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2065 18:11:29.538022 # ok 135 name.LCALTA.41
2066 18:11:29.538438 # ok 136 write_default.LCALTA.41
2067 18:11:29.543550 # ok 137 write_valid.LCALTA.41
2068 18:11:29.544018 # ok 138 write_invalid.LCALTA.41
2069 18:11:29.549172 # ok 139 event_missing.LCALTA.41
2070 18:11:29.549598 # ok 140 event_spurious.LCALTA.41
2071 18:11:29.554681 # ok 141 get_value.LCALTA.40
2072 18:11:29.555115 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2073 18:11:29.560260 # ok 142 name.LCALTA.40
2074 18:11:29.560852 # ok 143 write_default.LCALTA.40
2075 18:11:29.565785 # ok 144 write_valid.LCALTA.40
2076 18:11:29.566334 # ok 145 write_invalid.LCALTA.40
2077 18:11:29.571330 # ok 146 event_missing.LCALTA.40
2078 18:11:29.576902 # ok 147 event_spurious.LCALTA.40
2079 18:11:29.577512 # ok 148 get_value.LCALTA.39
2080 18:11:29.582422 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2081 18:11:29.582983 # ok 149 name.LCALTA.39
2082 18:11:29.588014 # ok 150 write_default.LCALTA.39
2083 18:11:29.588586 # ok 151 write_valid.LCALTA.39
2084 18:11:29.593512 # ok 152 write_invalid.LCALTA.39
2085 18:11:29.594068 # ok 153 event_missing.LCALTA.39
2086 18:11:29.599049 # ok 154 event_spurious.LCALTA.39
2087 18:11:29.599615 # ok 155 get_value.LCALTA.38
2088 18:11:29.604639 # # LCALTA.38 FRDDR_B SINK 3 SEL
2089 18:11:29.605181 # ok 156 name.LCALTA.38
2090 18:11:29.610235 # ok 157 write_default.LCALTA.38
2091 18:11:29.610851 # ok 158 write_valid.LCALTA.38
2092 18:11:29.615711 # ok 159 write_invalid.LCALTA.38
2093 18:11:29.616350 # ok 160 event_missing.LCALTA.38
2094 18:11:29.621250 # ok 161 event_spurious.LCALTA.38
2095 18:11:29.621809 # ok 162 get_value.LCALTA.37
2096 18:11:29.626804 # # LCALTA.37 FRDDR_B SINK 2 SEL
2097 18:11:29.627398 # ok 163 name.LCALTA.37
2098 18:11:29.632360 # ok 164 write_default.LCALTA.37
2099 18:11:29.632930 # ok 165 write_valid.LCALTA.37
2100 18:11:29.637912 # ok 166 write_invalid.LCALTA.37
2101 18:11:29.638523 # ok 167 event_missing.LCALTA.37
2102 18:11:29.643433 # ok 168 event_spurious.LCALTA.37
2103 18:11:29.643901 # ok 169 get_value.LCALTA.36
2104 18:11:29.648965 # # LCALTA.36 FRDDR_B SINK 1 SEL
2105 18:11:29.649399 # ok 170 name.LCALTA.36
2106 18:11:29.654475 # ok 171 write_default.LCALTA.36
2107 18:11:29.654942 # ok 172 write_valid.LCALTA.36
2108 18:11:29.660069 # ok 173 write_invalid.LCALTA.36
2109 18:11:29.660503 # ok 174 event_missing.LCALTA.36
2110 18:11:29.665613 # ok 175 event_spurious.LCALTA.36
2111 18:11:29.666076 # ok 176 get_value.LCALTA.35
2112 18:11:29.671163 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2113 18:11:29.671618 # ok 177 name.LCALTA.35
2114 18:11:29.676717 # ok 178 write_default.LCALTA.35
2115 18:11:29.677177 # ok 179 write_valid.LCALTA.35
2116 18:11:29.682299 # ok 180 write_invalid.LCALTA.35
2117 18:11:29.682771 # ok 181 event_missing.LCALTA.35
2118 18:11:29.687782 # ok 182 event_spurious.LCALTA.35
2119 18:11:29.688248 # ok 183 get_value.LCALTA.34
2120 18:11:29.693385 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2121 18:11:29.693841 # ok 184 name.LCALTA.34
2122 18:11:29.698896 # ok 185 write_default.LCALTA.34
2123 18:11:29.699360 # ok 186 write_valid.LCALTA.34
2124 18:11:29.704417 # ok 187 write_invalid.LCALTA.34
2125 18:11:29.704855 # ok 188 event_missing.LCALTA.34
2126 18:11:29.710004 # ok 189 event_spurious.LCALTA.34
2127 18:11:29.710434 # ok 190 get_value.LCALTA.33
2128 18:11:29.715521 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2129 18:11:29.715946 # ok 191 name.LCALTA.33
2130 18:11:29.721066 # ok 192 write_default.LCALTA.33
2131 18:11:29.721495 # ok 193 write_valid.LCALTA.33
2132 18:11:29.726636 # ok 194 write_invalid.LCALTA.33
2133 18:11:29.727067 # ok 195 event_missing.LCALTA.33
2134 18:11:29.732244 # ok 196 event_spurious.LCALTA.33
2135 18:11:29.737739 # ok 197 get_value.LCALTA.32
2136 18:11:29.738219 # # LCALTA.32 FRDDR_A SINK 3 SEL
2137 18:11:29.738617 # ok 198 name.LCALTA.32
2138 18:11:29.743298 # ok 199 write_default.LCALTA.32
2139 18:11:29.743758 # ok 200 write_valid.LCALTA.32
2140 18:11:29.748805 # ok 201 write_invalid.LCALTA.32
2141 18:11:29.754363 # ok 202 event_missing.LCALTA.32
2142 18:11:29.754796 # ok 203 event_spurious.LCALTA.32
2143 18:11:29.759893 # ok 204 get_value.LCALTA.31
2144 18:11:29.760376 # # LCALTA.31 FRDDR_A SINK 2 SEL
2145 18:11:29.760773 # ok 205 name.LCALTA.31
2146 18:11:29.765408 # ok 206 write_default.LCALTA.31
2147 18:11:29.765832 # ok 207 write_valid.LCALTA.31
2148 18:11:29.771015 # ok 208 write_invalid.LCALTA.31
2149 18:11:29.776519 # ok 209 event_missing.LCALTA.31
2150 18:11:29.776964 # ok 210 event_spurious.LCALTA.31
2151 18:11:29.782115 # ok 211 get_value.LCALTA.30
2152 18:11:29.782584 # # LCALTA.30 FRDDR_A SINK 1 SEL
2153 18:11:29.782982 # ok 212 name.LCALTA.30
2154 18:11:29.787636 # ok 213 write_default.LCALTA.30
2155 18:11:29.793281 # ok 214 write_valid.LCALTA.30
2156 18:11:29.793734 # ok 215 write_invalid.LCALTA.30
2157 18:11:29.798718 # ok 216 event_missing.LCALTA.30
2158 18:11:29.799180 # ok 217 event_spurious.LCALTA.30
2159 18:11:29.804261 # ok 218 get_value.LCALTA.29
2160 18:11:29.804707 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2161 18:11:29.809821 # ok 219 name.LCALTA.29
2162 18:11:29.810284 # ok 220 write_default.LCALTA.29
2163 18:11:29.815388 # ok 221 write_valid.LCALTA.29
2164 18:11:29.815853 # ok 222 write_invalid.LCALTA.29
2165 18:11:29.820898 # ok 223 event_missing.LCALTA.29
2166 18:11:29.821339 # ok 224 event_spurious.LCALTA.29
2167 18:11:29.826446 # ok 225 get_value.LCALTA.28
2168 18:11:29.826920 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2169 18:11:29.832017 # ok 226 name.LCALTA.28
2170 18:11:29.832453 # ok 227 write_default.LCALTA.28
2171 18:11:29.837572 # ok 228 write_valid.LCALTA.28
2172 18:11:29.838035 # ok 229 write_invalid.LCALTA.28
2173 18:11:29.843136 # ok 230 event_missing.LCALTA.28
2174 18:11:29.843597 # ok 231 event_spurious.LCALTA.28
2175 18:11:29.848651 # ok 232 get_value.LCALTA.27
2176 18:11:29.849095 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2177 18:11:29.854254 # ok 233 name.LCALTA.27
2178 18:11:29.854686 # ok 234 write_default.LCALTA.27
2179 18:11:29.859741 # ok 235 write_valid.LCALTA.27
2180 18:11:29.860199 # ok 236 write_invalid.LCALTA.27
2181 18:11:29.865286 # ok 237 event_missing.LCALTA.27
2182 18:11:29.865714 # ok 238 event_spurious.LCALTA.27
2183 18:11:29.870815 # ok 239 get_value.LCALTA.26
2184 18:11:29.871234 # # LCALTA.26 ELD
2185 18:11:29.876380 # ok 240 name.LCALTA.26
2186 18:11:29.876803 # # ELD is not writeable
2187 18:11:29.881921 # ok 241 # SKIP write_default.LCALTA.26
2188 18:11:29.882342 # # ELD is not writeable
2189 18:11:29.887458 # ok 242 # SKIP write_valid.LCALTA.26
2190 18:11:29.887892 # # ELD is not writeable
2191 18:11:29.892993 # ok 243 # SKIP write_invalid.LCALTA.26
2192 18:11:29.893424 # ok 244 event_missing.LCALTA.26
2193 18:11:29.898537 # ok 245 event_spurious.LCALTA.26
2194 18:11:29.898975 # ok 246 get_value.LCALTA.25
2195 18:11:29.904123 # # LCALTA.25 IEC958 Playback Default
2196 18:11:29.904601 # ok 247 name.LCALTA.25
2197 18:11:29.909646 # ok 248 write_default.LCALTA.25
2198 18:11:29.910083 # ok 249 # SKIP write_valid.LCALTA.25
2199 18:11:29.915310 # ok 250 # SKIP write_invalid.LCALTA.25
2200 18:11:29.920745 # ok 251 event_missing.LCALTA.25
2201 18:11:29.921195 # ok 252 event_spurious.LCALTA.25
2202 18:11:29.926317 # ok 253 get_value.LCALTA.24
2203 18:11:29.926783 # # LCALTA.24 IEC958 Playback Mask
2204 18:11:29.931864 # ok 254 name.LCALTA.24
2205 18:11:29.932354 # # IEC958 Playback Mask is not writeable
2206 18:11:29.937382 # ok 255 # SKIP write_default.LCALTA.24
2207 18:11:29.942945 # # IEC958 Playback Mask is not writeable
2208 18:11:29.943399 # ok 256 # SKIP write_valid.LCALTA.24
2209 18:11:29.948497 # # IEC958 Playback Mask is not writeable
2210 18:11:29.948930 # ok 257 # SKIP write_invalid.LCALTA.24
2211 18:11:29.954028 # ok 258 event_missing.LCALTA.24
2212 18:11:29.959578 # ok 259 event_spurious.LCALTA.24
2213 18:11:29.960031 # ok 260 get_value.LCALTA.23
2214 18:11:29.965138 # # LCALTA.23 Playback Channel Map
2215 18:11:29.965599 # ok 261 name.LCALTA.23
2216 18:11:29.970648 # # Playback Channel Map is not writeable
2217 18:11:29.971107 # ok 262 # SKIP write_default.LCALTA.23
2218 18:11:29.976254 # # Playback Channel Map is not writeable
2219 18:11:29.981777 # ok 263 # SKIP write_valid.LCALTA.23
2220 18:11:29.982234 # # Playback Channel Map is not writeable
2221 18:11:29.987319 # ok 264 # SKIP write_invalid.LCALTA.23
2222 18:11:29.987751 # ok 265 event_missing.LCALTA.23
2223 18:11:29.992860 # ok 266 event_spurious.LCALTA.23
2224 18:11:29.993329 # ok 267 get_value.LCALTA.22
2225 18:11:29.998511 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2226 18:11:29.998982 # ok 268 name.LCALTA.22
2227 18:11:30.003957 # ok 269 write_default.LCALTA.22
2228 18:11:30.009515 # ok 270 write_valid.LCALTA.22
2229 18:11:30.009975 # ok 271 write_invalid.LCALTA.22
2230 18:11:30.015029 # ok 272 event_missing.LCALTA.22
2231 18:11:30.015466 # ok 273 event_spurious.LCALTA.22
2232 18:11:30.020601 # ok 274 get_value.LCALTA.21
2233 18:11:30.021062 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2234 18:11:30.026221 # ok 275 name.LCALTA.21
2235 18:11:30.026779 # ok 276 write_default.LCALTA.21
2236 18:11:30.031880 # ok 277 write_valid.LCALTA.21
2237 18:11:30.032447 # ok 278 write_invalid.LCALTA.21
2238 18:11:30.037360 # ok 279 event_missing.LCALTA.21
2239 18:11:30.037884 # ok 280 event_spurious.LCALTA.21
2240 18:11:30.042881 # ok 281 get_value.LCALTA.20
2241 18:11:30.043406 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2242 18:11:30.048433 # ok 282 name.LCALTA.20
2243 18:11:30.048960 # ok 283 write_default.LCALTA.20
2244 18:11:30.054010 # ok 284 write_valid.LCALTA.20
2245 18:11:30.054531 # ok 285 write_invalid.LCALTA.20
2246 18:11:30.059536 # ok 286 event_missing.LCALTA.20
2247 18:11:30.060098 # ok 287 event_spurious.LCALTA.20
2248 18:11:30.065084 # ok 288 get_value.LCALTA.19
2249 18:11:30.065613 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2250 18:11:30.070633 # ok 289 name.LCALTA.19
2251 18:11:30.071165 # ok 290 write_default.LCALTA.19
2252 18:11:30.076191 # ok 291 write_valid.LCALTA.19
2253 18:11:30.076724 # ok 292 write_invalid.LCALTA.19
2254 18:11:30.081734 # ok 293 event_missing.LCALTA.19
2255 18:11:30.082265 # ok 294 event_spurious.LCALTA.19
2256 18:11:30.087263 # ok 295 get_value.LCALTA.18
2257 18:11:30.087788 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2258 18:11:30.092808 # ok 296 name.LCALTA.18
2259 18:11:30.093333 # ok 297 write_default.LCALTA.18
2260 18:11:30.098440 # ok 298 write_valid.LCALTA.18
2261 18:11:30.098976 # ok 299 write_invalid.LCALTA.18
2262 18:11:30.103891 # ok 300 event_missing.LCALTA.18
2263 18:11:30.104468 # ok 301 event_spurious.LCALTA.18
2264 18:11:30.109457 # ok 302 get_value.LCALTA.17
2265 18:11:30.115000 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2266 18:11:30.115541 # ok 303 name.LCALTA.17
2267 18:11:30.120502 # ok 304 write_default.LCALTA.17
2268 18:11:30.121046 # ok 305 write_valid.LCALTA.17
2269 18:11:30.126076 # ok 306 write_invalid.LCALTA.17
2270 18:11:30.126623 # ok 307 event_missing.LCALTA.17
2271 18:11:30.131629 # ok 308 event_spurious.LCALTA.17
2272 18:11:30.132212 # ok 309 get_value.LCALTA.16
2273 18:11:30.137202 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2274 18:11:30.137752 # ok 310 name.LCALTA.16
2275 18:11:30.142707 # ok 311 write_default.LCALTA.16
2276 18:11:30.143265 # ok 312 write_valid.LCALTA.16
2277 18:11:30.148317 # ok 313 write_invalid.LCALTA.16
2278 18:11:30.148883 # ok 314 event_missing.LCALTA.16
2279 18:11:30.153805 # ok 315 event_spurious.LCALTA.16
2280 18:11:30.154355 # ok 316 get_value.LCALTA.15
2281 18:11:30.159442 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2282 18:11:30.160032 # ok 317 name.LCALTA.15
2283 18:11:30.164955 # ok 318 write_default.LCALTA.15
2284 18:11:30.165505 # ok 319 write_valid.LCALTA.15
2285 18:11:30.170470 # ok 320 write_invalid.LCALTA.15
2286 18:11:30.171016 # ok 321 event_missing.LCALTA.15
2287 18:11:30.176061 # ok 322 event_spurious.LCALTA.15
2288 18:11:30.176617 # ok 323 get_value.LCALTA.14
2289 18:11:30.181559 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2290 18:11:30.182110 # ok 324 name.LCALTA.14
2291 18:11:30.187092 # ok 325 write_default.LCALTA.14
2292 18:11:30.187639 # ok 326 write_valid.LCALTA.14
2293 18:11:30.192641 # ok 327 write_invalid.LCALTA.14
2294 18:11:30.193186 # ok 328 event_missing.LCALTA.14
2295 18:11:30.198156 # ok 329 event_spurious.LCALTA.14
2296 18:11:30.198713 # ok 330 get_value.LCALTA.13
2297 18:11:30.203754 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2298 18:11:30.204361 # ok 331 name.LCALTA.13
2299 18:11:30.209308 # ok 332 write_default.LCALTA.13
2300 18:11:30.209863 # ok 333 write_valid.LCALTA.13
2301 18:11:30.214836 # ok 334 write_invalid.LCALTA.13
2302 18:11:30.215379 # ok 335 event_missing.LCALTA.13
2303 18:11:30.220385 # ok 336 event_spurious.LCALTA.13
2304 18:11:30.225956 # ok 337 get_value.LCALTA.12
2305 18:11:30.226498 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2306 18:11:30.231458 # ok 338 name.LCALTA.12
2307 18:11:30.232032 # ok 339 write_default.LCALTA.12
2308 18:11:30.237039 # ok 340 write_valid.LCALTA.12
2309 18:11:30.237583 # ok 341 write_invalid.LCALTA.12
2310 18:11:30.242559 # ok 342 event_missing.LCALTA.12
2311 18:11:30.243104 # ok 343 event_spurious.LCALTA.12
2312 18:11:30.248152 # ok 344 get_value.LCALTA.11
2313 18:11:30.248708 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2314 18:11:30.253748 # ok 345 name.LCALTA.11
2315 18:11:30.254298 # ok 346 write_default.LCALTA.11
2316 18:11:30.259214 # ok 347 write_valid.LCALTA.11
2317 18:11:30.259763 # ok 348 write_invalid.LCALTA.11
2318 18:11:30.264755 # ok 349 event_missing.LCALTA.11
2319 18:11:30.265308 # ok 350 event_spurious.LCALTA.11
2320 18:11:30.270322 # ok 351 get_value.LCALTA.10
2321 18:11:30.270874 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2322 18:11:30.275835 # ok 352 name.LCALTA.10
2323 18:11:30.276424 # ok 353 write_default.LCALTA.10
2324 18:11:30.281457 # ok 354 write_valid.LCALTA.10
2325 18:11:30.282011 # ok 355 write_invalid.LCALTA.10
2326 18:11:30.286967 # ok 356 event_missing.LCALTA.10
2327 18:11:30.287516 # ok 357 event_spurious.LCALTA.10
2328 18:11:30.292473 # ok 358 get_value.LCALTA.9
2329 18:11:30.293037 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2330 18:11:30.298032 # ok 359 name.LCALTA.9
2331 18:11:30.298584 # ok 360 write_default.LCALTA.9
2332 18:11:30.303586 # ok 361 write_valid.LCALTA.9
2333 18:11:30.304165 # ok 362 write_invalid.LCALTA.9
2334 18:11:30.309123 # ok 363 event_missing.LCALTA.9
2335 18:11:30.309670 # ok 364 event_spurious.LCALTA.9
2336 18:11:30.314687 # ok 365 get_value.LCALTA.8
2337 18:11:30.315223 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2338 18:11:30.320241 # ok 366 name.LCALTA.8
2339 18:11:30.320789 # ok 367 write_default.LCALTA.8
2340 18:11:30.325787 # ok 368 write_valid.LCALTA.8
2341 18:11:30.326345 # ok 369 write_invalid.LCALTA.8
2342 18:11:30.331305 # ok 370 event_missing.LCALTA.8
2343 18:11:30.331852 # ok 371 event_spurious.LCALTA.8
2344 18:11:30.336886 # ok 372 get_value.LCALTA.7
2345 18:11:30.337440 # # LCALTA.7 ACODEC Unmute Ramp Switch
2346 18:11:30.342468 # ok 373 name.LCALTA.7
2347 18:11:30.343012 # ok 374 write_default.LCALTA.7
2348 18:11:30.348015 # ok 375 write_valid.LCALTA.7
2349 18:11:30.348570 # ok 376 write_invalid.LCALTA.7
2350 18:11:30.353528 # ok 377 event_missing.LCALTA.7
2351 18:11:30.354090 # ok 378 event_spurious.LCALTA.7
2352 18:11:30.359077 # ok 379 get_value.LCALTA.6
2353 18:11:30.359655 # # LCALTA.6 ACODEC Mute Ramp Switch
2354 18:11:30.364605 # ok 380 name.LCALTA.6
2355 18:11:30.365174 # ok 381 write_default.LCALTA.6
2356 18:11:30.370152 # ok 382 write_valid.LCALTA.6
2357 18:11:30.370694 # ok 383 write_invalid.LCALTA.6
2358 18:11:30.375695 # ok 384 event_missing.LCALTA.6
2359 18:11:30.376277 # ok 385 event_spurious.LCALTA.6
2360 18:11:30.381225 # ok 386 get_value.LCALTA.5
2361 18:11:30.381778 # # LCALTA.5 ACODEC Volume Ramp Switch
2362 18:11:30.386765 # ok 387 name.LCALTA.5
2363 18:11:30.387319 # ok 388 write_default.LCALTA.5
2364 18:11:30.392353 # ok 389 write_valid.LCALTA.5
2365 18:11:30.392925 # ok 390 write_invalid.LCALTA.5
2366 18:11:30.397941 # ok 391 event_missing.LCALTA.5
2367 18:11:30.398498 # ok 392 event_spurious.LCALTA.5
2368 18:11:30.403462 # ok 393 get_value.LCALTA.4
2369 18:11:30.404045 # # LCALTA.4 ACODEC Ramp Rate
2370 18:11:30.409003 # ok 394 name.LCALTA.4
2371 18:11:30.409559 # ok 395 write_default.LCALTA.4
2372 18:11:30.414543 # ok 396 write_valid.LCALTA.4
2373 18:11:30.415104 # ok 397 write_invalid.LCALTA.4
2374 18:11:30.420118 # ok 398 event_missing.LCALTA.4
2375 18:11:30.420682 # ok 399 event_spurious.LCALTA.4
2376 18:11:30.425634 # ok 400 get_value.LCALTA.3
2377 18:11:30.426189 # # LCALTA.3 ACODEC Playback Volume
2378 18:11:30.431169 # ok 401 name.LCALTA.3
2379 18:11:30.431730 # ok 402 write_default.LCALTA.3
2380 18:11:30.436717 # ok 403 write_valid.LCALTA.3
2381 18:11:30.437299 # ok 404 write_invalid.LCALTA.3
2382 18:11:30.442296 # ok 405 event_missing.LCALTA.3
2383 18:11:30.442864 # ok 406 event_spurious.LCALTA.3
2384 18:11:30.447827 # ok 407 get_value.LCALTA.2
2385 18:11:30.448423 # # LCALTA.2 ACODEC Playback Switch
2386 18:11:30.453364 # ok 408 name.LCALTA.2
2387 18:11:30.453926 # ok 409 write_default.LCALTA.2
2388 18:11:30.458909 # ok 410 write_valid.LCALTA.2
2389 18:11:30.459489 # ok 411 write_invalid.LCALTA.2
2390 18:11:30.464465 # ok 412 event_missing.LCALTA.2
2391 18:11:30.465030 # ok 413 event_spurious.LCALTA.2
2392 18:11:30.470026 # ok 414 get_value.LCALTA.1
2393 18:11:30.470587 # # LCALTA.1 ACODEC Playback Channel Mode
2394 18:11:30.475523 # ok 415 name.LCALTA.1
2395 18:11:30.476127 # ok 416 write_default.LCALTA.1
2396 18:11:30.481060 # ok 417 write_valid.LCALTA.1
2397 18:11:30.481617 # ok 418 write_invalid.LCALTA.1
2398 18:11:30.486598 # ok 419 event_missing.LCALTA.1
2399 18:11:30.487159 # ok 420 event_spurious.LCALTA.1
2400 18:11:30.492243 # ok 421 get_value.LCALTA.0
2401 18:11:30.492822 # # LCALTA.0 TOACODEC Lane Select
2402 18:11:30.497712 # ok 422 name.LCALTA.0
2403 18:11:30.498282 # ok 423 write_default.LCALTA.0
2404 18:11:30.503259 # ok 424 write_valid.LCALTA.0
2405 18:11:30.503818 # ok 425 write_invalid.LCALTA.0
2406 18:11:30.508805 # ok 426 event_missing.LCALTA.0
2407 18:11:30.509379 # ok 427 event_spurious.LCALTA.0
2408 18:11:30.514393 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2409 18:11:30.519952 ok 1 selftests: alsa: mixer-test
2410 18:11:30.520552 # timeout set to 45
2411 18:11:30.521016 # selftests: alsa: pcm-test
2412 18:11:30.525493 # TAP version 13
2413 18:11:30.526053 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2414 18:11:30.531015 # # LCALTA.0 - fe.dai-link-0 (*)
2415 18:11:30.531580 # # LCALTA.0 - fe.dai-link-1 (*)
2416 18:11:30.536546 # # LCALTA.0 - fe.dai-link-2 (*)
2417 18:11:30.537125 # # LCALTA.0 - fe.dai-link-3 (*)
2418 18:11:30.542110 # # LCALTA.0 - fe.dai-link-4 (*)
2419 18:11:30.547562 # # LCALTA.0 - fe.dai-link-5 (*)
2420 18:11:30.548166 # 1..42
2421 18:11:30.553193 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2422 18:11:30.553758 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2423 18:11:30.558791 # # snd_pcm_hw_params: Invalid argument
2424 18:11:30.564293 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2425 18:11:30.569825 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2426 18:11:30.570389 # # snd_pcm_hw_params: Invalid argument
2427 18:11:30.580875 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2428 18:11:30.581451 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2429 18:11:30.586462 # # snd_pcm_hw_params: Invalid argument
2430 18:11:30.592048 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2431 18:11:30.597551 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2432 18:11:30.598104 # # snd_pcm_hw_params: Invalid argument
2433 18:11:30.603112 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2434 18:11:30.608645 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2435 18:11:30.614236 # # snd_pcm_hw_params: Invalid argument
2436 18:11:30.619818 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2437 18:11:30.625302 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2438 18:11:30.625863 # # snd_pcm_hw_params: Invalid argument
2439 18:11:30.630868 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2440 18:11:30.636394 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2441 18:11:30.641926 # # snd_pcm_hw_params: Invalid argument
2442 18:11:30.647485 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2443 18:11:30.648074 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2444 18:11:30.653041 # # snd_pcm_hw_params: Invalid argument
2445 18:11:30.658620 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2446 18:11:30.664131 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2447 18:11:30.669705 # # snd_pcm_hw_params: Invalid argument
2448 18:11:30.675254 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2449 18:11:30.675828 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2450 18:11:30.680767 # # snd_pcm_hw_params: Invalid argument
2451 18:11:30.686314 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2452 18:11:30.691851 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2453 18:11:30.692461 # # snd_pcm_hw_params: Invalid argument
2454 18:11:30.702924 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2455 18:11:30.703499 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2456 18:11:30.708507 # # snd_pcm_hw_params: Invalid argument
2457 18:11:30.714068 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2458 18:11:30.719621 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2459 18:11:30.720220 # # snd_pcm_hw_params: Invalid argument
2460 18:11:30.725145 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2461 18:11:30.730677 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2462 18:11:30.736277 # # snd_pcm_hw_params: Invalid argument
2463 18:11:30.741790 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2464 18:11:30.747349 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2465 18:11:30.747907 # # snd_pcm_hw_params: Invalid argument
2466 18:11:30.752935 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2467 18:11:30.758400 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2468 18:11:30.764020 # # snd_pcm_hw_params: Invalid argument
2469 18:11:30.769479 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2470 18:11:30.775071 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2471 18:11:30.775652 # # snd_pcm_hw_params: Invalid argument
2472 18:11:30.780643 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2473 18:11:30.786148 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2474 18:11:30.791721 # # snd_pcm_hw_params: Invalid argument
2475 18:11:30.797272 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2476 18:11:30.797847 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2477 18:11:30.802811 # # snd_pcm_hw_params: Invalid argument
2478 18:11:30.808374 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2479 18:11:30.813880 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2480 18:11:30.819512 # # snd_pcm_hw_params: Invalid argument
2481 18:11:30.824984 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2482 18:11:30.825549 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2483 18:11:30.830555 # # snd_pcm_hw_params: Invalid argument
2484 18:11:30.836067 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2485 18:11:30.841617 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2486 18:11:30.847189 # # snd_pcm_hw_params: Invalid argument
2487 18:11:30.852721 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2488 18:11:30.853287 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2489 18:11:30.858272 # # snd_pcm_hw_params: Invalid argument
2490 18:11:30.863826 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2491 18:11:30.869352 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2492 18:11:30.869909 # # snd_pcm_hw_params: Invalid argument
2493 18:11:30.880532 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2494 18:11:30.881171 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2495 18:11:30.886096 # # snd_pcm_hw_params: Invalid argument
2496 18:11:30.891637 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2497 18:11:30.897180 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2498 18:11:30.897789 # # snd_pcm_hw_params: Invalid argument
2499 18:11:30.908206 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2500 18:11:30.908833 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2501 18:11:30.913794 # # snd_pcm_hw_params: Invalid argument
2502 18:11:30.919335 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2503 18:11:30.924882 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2504 18:11:30.925456 # # snd_pcm_hw_params: Invalid argument
2505 18:11:30.930414 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2506 18:11:30.935917 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2507 18:11:30.941537 # # snd_pcm_hw_params: Invalid argument
2508 18:11:30.947029 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2509 18:11:30.952584 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2510 18:11:30.953130 # # snd_pcm_hw_params: Invalid argument
2511 18:11:30.958128 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2512 18:11:30.963667 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2513 18:11:30.969166 # # snd_pcm_hw_params: Invalid argument
2514 18:11:30.974744 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2515 18:11:30.980359 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2516 18:11:30.980945 # # snd_pcm_hw_params: Invalid argument
2517 18:11:30.985886 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2518 18:11:30.991428 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2519 18:11:30.996994 # # snd_pcm_hw_params: Invalid argument
2520 18:11:31.002608 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2521 18:11:31.008092 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2522 18:11:31.008686 # # snd_pcm_hw_params: Invalid argument
2523 18:11:31.013627 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2524 18:11:31.019156 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2525 18:11:31.024784 # # snd_pcm_hw_params: Invalid argument
2526 18:11:31.030287 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2527 18:11:31.035781 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2528 18:11:31.036401 # # snd_pcm_hw_params: Invalid argument
2529 18:11:31.041310 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2530 18:11:31.046900 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2531 18:11:31.052446 # # snd_pcm_hw_params: Invalid argument
2532 18:11:31.057975 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2533 18:11:31.063610 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2534 18:11:31.064238 # # snd_pcm_hw_params: Invalid argument
2535 18:11:31.069090 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2536 18:11:31.074610 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2537 18:11:31.080143 # # snd_pcm_hw_params: Invalid argument
2538 18:11:31.085704 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2539 18:11:31.091239 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2540 18:11:31.091815 # # snd_pcm_hw_params: Invalid argument
2541 18:11:31.096801 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2542 18:11:31.102335 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2543 18:11:31.107862 # # snd_pcm_hw_params: Invalid argument
2544 18:11:31.113408 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2545 18:11:31.118975 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2546 18:11:31.119509 # # snd_pcm_hw_params: Invalid argument
2547 18:11:31.124581 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2548 18:11:31.130040 ok 2 selftests: alsa: pcm-test
2549 18:11:31.130575 # timeout set to 45
2550 18:11:31.135618 # selftests: alsa: test-pcmtest-driver
2551 18:11:31.136186 # TAP version 13
2552 18:11:31.136651 # 1..5
2553 18:11:31.141138 # # Starting 5 tests from 1 test cases.
2554 18:11:31.141674 # # RUN pcmtest.playback ...
2555 18:11:31.146693 # # SKIP Can't read patterns. Probably, module isn't loaded
2556 18:11:31.152259 # # OK pcmtest.playback
2557 18:11:31.157797 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2558 18:11:31.163350 # # RUN pcmtest.capture ...
2559 18:11:31.168879 # # SKIP Can't read patterns. Probably, module isn't loaded
2560 18:11:31.174422 # # OK pcmtest.capture
2561 18:11:31.179962 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2562 18:11:31.185565 # # RUN pcmtest.ni_capture ...
2563 18:11:31.191036 # # SKIP Can't read patterns. Probably, module isn't loaded
2564 18:11:31.191580 # # OK pcmtest.ni_capture
2565 18:11:31.202142 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2566 18:11:31.202725 # # RUN pcmtest.ni_playback ...
2567 18:11:31.207707 # # SKIP Can't read patterns. Probably, module isn't loaded
2568 18:11:31.213257 # # OK pcmtest.ni_playback
2569 18:11:31.218797 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2570 18:11:31.224319 # # RUN pcmtest.reset_ioctl ...
2571 18:11:31.229871 # # SKIP Can't read patterns. Probably, module isn't loaded
2572 18:11:31.235433 # # OK pcmtest.reset_ioctl
2573 18:11:31.240960 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2574 18:11:31.246534 # # PASSED: 5 / 5 tests passed.
2575 18:11:31.252080 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2576 18:11:31.252640 ok 3 selftests: alsa: test-pcmtest-driver
2577 18:11:31.257625 # timeout set to 45
2578 18:11:31.258213 # selftests: alsa: utimer-test
2579 18:11:31.258732 # TAP version 13
2580 18:11:31.259202 # 1..2
2581 18:11:31.263160 # # Starting 2 tests from 2 test cases.
2582 18:11:31.268677 # # RUN global.wrong_timers_test ...
2583 18:11:31.274261 # # OK global.wrong_timers_test
2584 18:11:31.274813 # ok 1 global.wrong_timers_test
2585 18:11:31.279773 # # RUN timer_f.utimer ...
2586 18:11:31.290788 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2587 18:11:31.291328 # # utimer: Test terminated by assertion
2588 18:11:31.296400 # # FAIL timer_f.utimer
2589 18:11:31.296921 # not ok 2 timer_f.utimer
2590 18:11:31.301915 # # FAILED: 1 / 2 tests passed.
2591 18:11:31.309749 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2592 18:11:31.310265 not ok 4 selftests: alsa: utimer-test # exit=1
2593 18:11:31.840856 alsa_mixer-test_get_value_LCALTA_60 pass
2594 18:11:31.846322 alsa_mixer-test_name_LCALTA_60 pass
2595 18:11:31.846847 alsa_mixer-test_write_default_LCALTA_60 pass
2596 18:11:31.851846 alsa_mixer-test_write_valid_LCALTA_60 pass
2597 18:11:31.855320 alsa_mixer-test_write_invalid_LCALTA_60 pass
2598 18:11:31.860885 alsa_mixer-test_event_missing_LCALTA_60 pass
2599 18:11:31.866418 alsa_mixer-test_event_spurious_LCALTA_60 pass
2600 18:11:31.866929 alsa_mixer-test_get_value_LCALTA_59 pass
2601 18:11:31.871951 alsa_mixer-test_name_LCALTA_59 pass
2602 18:11:31.877600 alsa_mixer-test_write_default_LCALTA_59 pass
2603 18:11:31.878111 alsa_mixer-test_write_valid_LCALTA_59 pass
2604 18:11:31.883030 alsa_mixer-test_write_invalid_LCALTA_59 pass
2605 18:11:31.888578 alsa_mixer-test_event_missing_LCALTA_59 pass
2606 18:11:31.889085 alsa_mixer-test_event_spurious_LCALTA_59 pass
2607 18:11:31.894198 alsa_mixer-test_get_value_LCALTA_58 pass
2608 18:11:31.899677 alsa_mixer-test_name_LCALTA_58 pass
2609 18:11:31.900236 alsa_mixer-test_write_default_LCALTA_58 pass
2610 18:11:31.905248 alsa_mixer-test_write_valid_LCALTA_58 pass
2611 18:11:31.910766 alsa_mixer-test_write_invalid_LCALTA_58 pass
2612 18:11:31.916341 alsa_mixer-test_event_missing_LCALTA_58 pass
2613 18:11:31.916874 alsa_mixer-test_event_spurious_LCALTA_58 pass
2614 18:11:31.921967 alsa_mixer-test_get_value_LCALTA_57 pass
2615 18:11:31.927485 alsa_mixer-test_name_LCALTA_57 pass
2616 18:11:31.928042 alsa_mixer-test_write_default_LCALTA_57 pass
2617 18:11:31.933047 alsa_mixer-test_write_valid_LCALTA_57 pass
2618 18:11:31.938593 alsa_mixer-test_write_invalid_LCALTA_57 pass
2619 18:11:31.939110 alsa_mixer-test_event_missing_LCALTA_57 pass
2620 18:11:31.944170 alsa_mixer-test_event_spurious_LCALTA_57 pass
2621 18:11:31.949696 alsa_mixer-test_get_value_LCALTA_56 pass
2622 18:11:31.950219 alsa_mixer-test_name_LCALTA_56 pass
2623 18:11:31.955214 alsa_mixer-test_write_default_LCALTA_56 pass
2624 18:11:31.960749 alsa_mixer-test_write_valid_LCALTA_56 pass
2625 18:11:31.961264 alsa_mixer-test_write_invalid_LCALTA_56 pass
2626 18:11:31.966319 alsa_mixer-test_event_missing_LCALTA_56 pass
2627 18:11:31.971850 alsa_mixer-test_event_spurious_LCALTA_56 pass
2628 18:11:31.977510 alsa_mixer-test_get_value_LCALTA_55 pass
2629 18:11:31.978084 alsa_mixer-test_name_LCALTA_55 pass
2630 18:11:31.983036 alsa_mixer-test_write_default_LCALTA_55 pass
2631 18:11:31.988509 alsa_mixer-test_write_valid_LCALTA_55 pass
2632 18:11:31.989052 alsa_mixer-test_write_invalid_LCALTA_55 pass
2633 18:11:31.994053 alsa_mixer-test_event_missing_LCALTA_55 pass
2634 18:11:31.999594 alsa_mixer-test_event_spurious_LCALTA_55 pass
2635 18:11:32.000147 alsa_mixer-test_get_value_LCALTA_54 pass
2636 18:11:32.005118 alsa_mixer-test_name_LCALTA_54 pass
2637 18:11:32.010666 alsa_mixer-test_write_default_LCALTA_54 pass
2638 18:11:32.011204 alsa_mixer-test_write_valid_LCALTA_54 pass
2639 18:11:32.016262 alsa_mixer-test_write_invalid_LCALTA_54 pass
2640 18:11:32.021758 alsa_mixer-test_event_missing_LCALTA_54 pass
2641 18:11:32.027351 alsa_mixer-test_event_spurious_LCALTA_54 pass
2642 18:11:32.027885 alsa_mixer-test_get_value_LCALTA_53 pass
2643 18:11:32.032926 alsa_mixer-test_name_LCALTA_53 pass
2644 18:11:32.038477 alsa_mixer-test_write_default_LCALTA_53 pass
2645 18:11:32.039015 alsa_mixer-test_write_valid_LCALTA_53 pass
2646 18:11:32.044008 alsa_mixer-test_write_invalid_LCALTA_53 pass
2647 18:11:32.049501 alsa_mixer-test_event_missing_LCALTA_53 pass
2648 18:11:32.050033 alsa_mixer-test_event_spurious_LCALTA_53 pass
2649 18:11:32.055064 alsa_mixer-test_get_value_LCALTA_52 pass
2650 18:11:32.060718 alsa_mixer-test_name_LCALTA_52 pass
2651 18:11:32.061251 alsa_mixer-test_write_default_LCALTA_52 pass
2652 18:11:32.066170 alsa_mixer-test_write_valid_LCALTA_52 pass
2653 18:11:32.071727 alsa_mixer-test_write_invalid_LCALTA_52 pass
2654 18:11:32.072294 alsa_mixer-test_event_missing_LCALTA_52 pass
2655 18:11:32.077240 alsa_mixer-test_event_spurious_LCALTA_52 pass
2656 18:11:32.082765 alsa_mixer-test_get_value_LCALTA_51 pass
2657 18:11:32.083290 alsa_mixer-test_name_LCALTA_51 pass
2658 18:11:32.088410 alsa_mixer-test_write_default_LCALTA_51 pass
2659 18:11:32.093912 alsa_mixer-test_write_valid_LCALTA_51 pass
2660 18:11:32.099431 alsa_mixer-test_write_invalid_LCALTA_51 pass
2661 18:11:32.099965 alsa_mixer-test_event_missing_LCALTA_51 pass
2662 18:11:32.104978 alsa_mixer-test_event_spurious_LCALTA_51 pass
2663 18:11:32.110544 alsa_mixer-test_get_value_LCALTA_50 pass
2664 18:11:32.111076 alsa_mixer-test_name_LCALTA_50 pass
2665 18:11:32.116094 alsa_mixer-test_write_default_LCALTA_50 pass
2666 18:11:32.121712 alsa_mixer-test_write_valid_LCALTA_50 pass
2667 18:11:32.122242 alsa_mixer-test_write_invalid_LCALTA_50 pass
2668 18:11:32.127171 alsa_mixer-test_event_missing_LCALTA_50 pass
2669 18:11:32.132749 alsa_mixer-test_event_spurious_LCALTA_50 pass
2670 18:11:32.133274 alsa_mixer-test_get_value_LCALTA_49 pass
2671 18:11:32.138278 alsa_mixer-test_name_LCALTA_49 pass
2672 18:11:32.143793 alsa_mixer-test_write_default_LCALTA_49 pass
2673 18:11:32.144342 alsa_mixer-test_write_valid_LCALTA_49 pass
2674 18:11:32.149322 alsa_mixer-test_write_invalid_LCALTA_49 pass
2675 18:11:32.154909 alsa_mixer-test_event_missing_LCALTA_49 pass
2676 18:11:32.160428 alsa_mixer-test_event_spurious_LCALTA_49 pass
2677 18:11:32.160938 alsa_mixer-test_get_value_LCALTA_48 pass
2678 18:11:32.165988 alsa_mixer-test_name_LCALTA_48 pass
2679 18:11:32.171544 alsa_mixer-test_write_default_LCALTA_48 pass
2680 18:11:32.172120 alsa_mixer-test_write_valid_LCALTA_48 pass
2681 18:11:32.177091 alsa_mixer-test_write_invalid_LCALTA_48 pass
2682 18:11:32.182672 alsa_mixer-test_event_missing_LCALTA_48 pass
2683 18:11:32.183204 alsa_mixer-test_event_spurious_LCALTA_48 pass
2684 18:11:32.188233 alsa_mixer-test_get_value_LCALTA_47 pass
2685 18:11:32.193695 alsa_mixer-test_name_LCALTA_47 pass
2686 18:11:32.194220 alsa_mixer-test_write_default_LCALTA_47 pass
2687 18:11:32.199266 alsa_mixer-test_write_valid_LCALTA_47 pass
2688 18:11:32.204802 alsa_mixer-test_write_invalid_LCALTA_47 pass
2689 18:11:32.210348 alsa_mixer-test_event_missing_LCALTA_47 pass
2690 18:11:32.210875 alsa_mixer-test_event_spurious_LCALTA_47 pass
2691 18:11:32.215938 alsa_mixer-test_get_value_LCALTA_46 pass
2692 18:11:32.216525 alsa_mixer-test_name_LCALTA_46 pass
2693 18:11:32.221523 alsa_mixer-test_write_default_LCALTA_46 pass
2694 18:11:32.226996 alsa_mixer-test_write_valid_LCALTA_46 pass
2695 18:11:32.232542 alsa_mixer-test_write_invalid_LCALTA_46 pass
2696 18:11:32.233070 alsa_mixer-test_event_missing_LCALTA_46 pass
2697 18:11:32.238076 alsa_mixer-test_event_spurious_LCALTA_46 pass
2698 18:11:32.243637 alsa_mixer-test_get_value_LCALTA_45 pass
2699 18:11:32.244186 alsa_mixer-test_name_LCALTA_45 pass
2700 18:11:32.249168 alsa_mixer-test_write_default_LCALTA_45 pass
2701 18:11:32.254731 alsa_mixer-test_write_valid_LCALTA_45 pass
2702 18:11:32.255260 alsa_mixer-test_write_invalid_LCALTA_45 pass
2703 18:11:32.260295 alsa_mixer-test_event_missing_LCALTA_45 pass
2704 18:11:32.265806 alsa_mixer-test_event_spurious_LCALTA_45 pass
2705 18:11:32.271364 alsa_mixer-test_get_value_LCALTA_44 pass
2706 18:11:32.271900 alsa_mixer-test_name_LCALTA_44 pass
2707 18:11:32.276956 alsa_mixer-test_write_default_LCALTA_44 pass
2708 18:11:32.282521 alsa_mixer-test_write_valid_LCALTA_44 pass
2709 18:11:32.283050 alsa_mixer-test_write_invalid_LCALTA_44 pass
2710 18:11:32.288039 alsa_mixer-test_event_missing_LCALTA_44 pass
2711 18:11:32.293555 alsa_mixer-test_event_spurious_LCALTA_44 pass
2712 18:11:32.294088 alsa_mixer-test_get_value_LCALTA_43 pass
2713 18:11:32.299102 alsa_mixer-test_name_LCALTA_43 pass
2714 18:11:32.304650 alsa_mixer-test_write_default_LCALTA_43 pass
2715 18:11:32.305170 alsa_mixer-test_write_valid_LCALTA_43 pass
2716 18:11:32.310171 alsa_mixer-test_write_invalid_LCALTA_43 pass
2717 18:11:32.315761 alsa_mixer-test_event_missing_LCALTA_43 pass
2718 18:11:32.316315 alsa_mixer-test_event_spurious_LCALTA_43 pass
2719 18:11:32.321273 alsa_mixer-test_get_value_LCALTA_42 pass
2720 18:11:32.326818 alsa_mixer-test_name_LCALTA_42 pass
2721 18:11:32.327343 alsa_mixer-test_write_default_LCALTA_42 pass
2722 18:11:32.332399 alsa_mixer-test_write_valid_LCALTA_42 pass
2723 18:11:32.337937 alsa_mixer-test_write_invalid_LCALTA_42 pass
2724 18:11:32.343501 alsa_mixer-test_event_missing_LCALTA_42 pass
2725 18:11:32.344073 alsa_mixer-test_event_spurious_LCALTA_42 pass
2726 18:11:32.349049 alsa_mixer-test_get_value_LCALTA_41 pass
2727 18:11:32.354569 alsa_mixer-test_name_LCALTA_41 pass
2728 18:11:32.355106 alsa_mixer-test_write_default_LCALTA_41 pass
2729 18:11:32.360113 alsa_mixer-test_write_valid_LCALTA_41 pass
2730 18:11:32.365664 alsa_mixer-test_write_invalid_LCALTA_41 pass
2731 18:11:32.366190 alsa_mixer-test_event_missing_LCALTA_41 pass
2732 18:11:32.371196 alsa_mixer-test_event_spurious_LCALTA_41 pass
2733 18:11:32.376751 alsa_mixer-test_get_value_LCALTA_40 pass
2734 18:11:32.377280 alsa_mixer-test_name_LCALTA_40 pass
2735 18:11:32.382327 alsa_mixer-test_write_default_LCALTA_40 pass
2736 18:11:32.387831 alsa_mixer-test_write_valid_LCALTA_40 pass
2737 18:11:32.388401 alsa_mixer-test_write_invalid_LCALTA_40 pass
2738 18:11:32.393410 alsa_mixer-test_event_missing_LCALTA_40 pass
2739 18:11:32.398989 alsa_mixer-test_event_spurious_LCALTA_40 pass
2740 18:11:32.404493 alsa_mixer-test_get_value_LCALTA_39 pass
2741 18:11:32.405015 alsa_mixer-test_name_LCALTA_39 pass
2742 18:11:32.410031 alsa_mixer-test_write_default_LCALTA_39 pass
2743 18:11:32.415587 alsa_mixer-test_write_valid_LCALTA_39 pass
2744 18:11:32.416158 alsa_mixer-test_write_invalid_LCALTA_39 pass
2745 18:11:32.421120 alsa_mixer-test_event_missing_LCALTA_39 pass
2746 18:11:32.426692 alsa_mixer-test_event_spurious_LCALTA_39 pass
2747 18:11:32.427210 alsa_mixer-test_get_value_LCALTA_38 pass
2748 18:11:32.432268 alsa_mixer-test_name_LCALTA_38 pass
2749 18:11:32.437758 alsa_mixer-test_write_default_LCALTA_38 pass
2750 18:11:32.438283 alsa_mixer-test_write_valid_LCALTA_38 pass
2751 18:11:32.443301 alsa_mixer-test_write_invalid_LCALTA_38 pass
2752 18:11:32.448861 alsa_mixer-test_event_missing_LCALTA_38 pass
2753 18:11:32.454391 alsa_mixer-test_event_spurious_LCALTA_38 pass
2754 18:11:32.454920 alsa_mixer-test_get_value_LCALTA_37 pass
2755 18:11:32.460056 alsa_mixer-test_name_LCALTA_37 pass
2756 18:11:32.465519 alsa_mixer-test_write_default_LCALTA_37 pass
2757 18:11:32.466042 alsa_mixer-test_write_valid_LCALTA_37 pass
2758 18:11:32.471036 alsa_mixer-test_write_invalid_LCALTA_37 pass
2759 18:11:32.476576 alsa_mixer-test_event_missing_LCALTA_37 pass
2760 18:11:32.477103 alsa_mixer-test_event_spurious_LCALTA_37 pass
2761 18:11:32.482124 alsa_mixer-test_get_value_LCALTA_36 pass
2762 18:11:32.487675 alsa_mixer-test_name_LCALTA_36 pass
2763 18:11:32.488243 alsa_mixer-test_write_default_LCALTA_36 pass
2764 18:11:32.493221 alsa_mixer-test_write_valid_LCALTA_36 pass
2765 18:11:32.498778 alsa_mixer-test_write_invalid_LCALTA_36 pass
2766 18:11:32.499308 alsa_mixer-test_event_missing_LCALTA_36 pass
2767 18:11:32.504311 alsa_mixer-test_event_spurious_LCALTA_36 pass
2768 18:11:32.510174 alsa_mixer-test_get_value_LCALTA_35 pass
2769 18:11:32.510847 alsa_mixer-test_name_LCALTA_35 pass
2770 18:11:32.515395 alsa_mixer-test_write_default_LCALTA_35 pass
2771 18:11:32.520996 alsa_mixer-test_write_valid_LCALTA_35 pass
2772 18:11:32.526527 alsa_mixer-test_write_invalid_LCALTA_35 pass
2773 18:11:32.527118 alsa_mixer-test_event_missing_LCALTA_35 pass
2774 18:11:32.532064 alsa_mixer-test_event_spurious_LCALTA_35 pass
2775 18:11:32.537510 alsa_mixer-test_get_value_LCALTA_34 pass
2776 18:11:32.537966 alsa_mixer-test_name_LCALTA_34 pass
2777 18:11:32.543033 alsa_mixer-test_write_default_LCALTA_34 pass
2778 18:11:32.548588 alsa_mixer-test_write_valid_LCALTA_34 pass
2779 18:11:32.549035 alsa_mixer-test_write_invalid_LCALTA_34 pass
2780 18:11:32.554142 alsa_mixer-test_event_missing_LCALTA_34 pass
2781 18:11:32.559770 alsa_mixer-test_event_spurious_LCALTA_34 pass
2782 18:11:32.560286 alsa_mixer-test_get_value_LCALTA_33 pass
2783 18:11:32.565268 alsa_mixer-test_name_LCALTA_33 pass
2784 18:11:32.570856 alsa_mixer-test_write_default_LCALTA_33 pass
2785 18:11:32.571315 alsa_mixer-test_write_valid_LCALTA_33 pass
2786 18:11:32.576530 alsa_mixer-test_write_invalid_LCALTA_33 pass
2787 18:11:32.581959 alsa_mixer-test_event_missing_LCALTA_33 pass
2788 18:11:32.587474 alsa_mixer-test_event_spurious_LCALTA_33 pass
2789 18:11:32.588019 alsa_mixer-test_get_value_LCALTA_32 pass
2790 18:11:32.593038 alsa_mixer-test_name_LCALTA_32 pass
2791 18:11:32.598535 alsa_mixer-test_write_default_LCALTA_32 pass
2792 18:11:32.599179 alsa_mixer-test_write_valid_LCALTA_32 pass
2793 18:11:32.604116 alsa_mixer-test_write_invalid_LCALTA_32 pass
2794 18:11:32.609657 alsa_mixer-test_event_missing_LCALTA_32 pass
2795 18:11:32.610291 alsa_mixer-test_event_spurious_LCALTA_32 pass
2796 18:11:32.615198 alsa_mixer-test_get_value_LCALTA_31 pass
2797 18:11:32.620774 alsa_mixer-test_name_LCALTA_31 pass
2798 18:11:32.621392 alsa_mixer-test_write_default_LCALTA_31 pass
2799 18:11:32.626307 alsa_mixer-test_write_valid_LCALTA_31 pass
2800 18:11:32.631850 alsa_mixer-test_write_invalid_LCALTA_31 pass
2801 18:11:32.637444 alsa_mixer-test_event_missing_LCALTA_31 pass
2802 18:11:32.638030 alsa_mixer-test_event_spurious_LCALTA_31 pass
2803 18:11:32.642915 alsa_mixer-test_get_value_LCALTA_30 pass
2804 18:11:32.643543 alsa_mixer-test_name_LCALTA_30 pass
2805 18:11:32.648512 alsa_mixer-test_write_default_LCALTA_30 pass
2806 18:11:32.654001 alsa_mixer-test_write_valid_LCALTA_30 pass
2807 18:11:32.659568 alsa_mixer-test_write_invalid_LCALTA_30 pass
2808 18:11:32.660232 alsa_mixer-test_event_missing_LCALTA_30 pass
2809 18:11:32.665139 alsa_mixer-test_event_spurious_LCALTA_30 pass
2810 18:11:32.670702 alsa_mixer-test_get_value_LCALTA_29 pass
2811 18:11:32.671333 alsa_mixer-test_name_LCALTA_29 pass
2812 18:11:32.676247 alsa_mixer-test_write_default_LCALTA_29 pass
2813 18:11:32.681777 alsa_mixer-test_write_valid_LCALTA_29 pass
2814 18:11:32.682405 alsa_mixer-test_write_invalid_LCALTA_29 pass
2815 18:11:32.687306 alsa_mixer-test_event_missing_LCALTA_29 pass
2816 18:11:32.692814 alsa_mixer-test_event_spurious_LCALTA_29 pass
2817 18:11:32.698420 alsa_mixer-test_get_value_LCALTA_28 pass
2818 18:11:32.699082 alsa_mixer-test_name_LCALTA_28 pass
2819 18:11:32.704007 alsa_mixer-test_write_default_LCALTA_28 pass
2820 18:11:32.709525 alsa_mixer-test_write_valid_LCALTA_28 pass
2821 18:11:32.710169 alsa_mixer-test_write_invalid_LCALTA_28 pass
2822 18:11:32.715004 alsa_mixer-test_event_missing_LCALTA_28 pass
2823 18:11:32.720646 alsa_mixer-test_event_spurious_LCALTA_28 pass
2824 18:11:32.721242 alsa_mixer-test_get_value_LCALTA_27 pass
2825 18:11:32.726179 alsa_mixer-test_name_LCALTA_27 pass
2826 18:11:32.731697 alsa_mixer-test_write_default_LCALTA_27 pass
2827 18:11:32.732308 alsa_mixer-test_write_valid_LCALTA_27 pass
2828 18:11:32.737214 alsa_mixer-test_write_invalid_LCALTA_27 pass
2829 18:11:32.742767 alsa_mixer-test_event_missing_LCALTA_27 pass
2830 18:11:32.743344 alsa_mixer-test_event_spurious_LCALTA_27 pass
2831 18:11:32.748333 alsa_mixer-test_get_value_LCALTA_26 pass
2832 18:11:32.753897 alsa_mixer-test_name_LCALTA_26 pass
2833 18:11:32.754472 alsa_mixer-test_write_default_LCALTA_26 skip
2834 18:11:32.759433 alsa_mixer-test_write_valid_LCALTA_26 skip
2835 18:11:32.764951 alsa_mixer-test_write_invalid_LCALTA_26 skip
2836 18:11:32.770493 alsa_mixer-test_event_missing_LCALTA_26 pass
2837 18:11:32.770959 alsa_mixer-test_event_spurious_LCALTA_26 pass
2838 18:11:32.776014 alsa_mixer-test_get_value_LCALTA_25 pass
2839 18:11:32.781613 alsa_mixer-test_name_LCALTA_25 pass
2840 18:11:32.782059 alsa_mixer-test_write_default_LCALTA_25 pass
2841 18:11:32.787101 alsa_mixer-test_write_valid_LCALTA_25 skip
2842 18:11:32.792672 alsa_mixer-test_write_invalid_LCALTA_25 skip
2843 18:11:32.793136 alsa_mixer-test_event_missing_LCALTA_25 pass
2844 18:11:32.798200 alsa_mixer-test_event_spurious_LCALTA_25 pass
2845 18:11:32.803767 alsa_mixer-test_get_value_LCALTA_24 pass
2846 18:11:32.804261 alsa_mixer-test_name_LCALTA_24 pass
2847 18:11:32.809339 alsa_mixer-test_write_default_LCALTA_24 skip
2848 18:11:32.814943 alsa_mixer-test_write_valid_LCALTA_24 skip
2849 18:11:32.815394 alsa_mixer-test_write_invalid_LCALTA_24 skip
2850 18:11:32.820484 alsa_mixer-test_event_missing_LCALTA_24 pass
2851 18:11:32.825958 alsa_mixer-test_event_spurious_LCALTA_24 pass
2852 18:11:32.831517 alsa_mixer-test_get_value_LCALTA_23 pass
2853 18:11:32.832031 alsa_mixer-test_name_LCALTA_23 pass
2854 18:11:32.837094 alsa_mixer-test_write_default_LCALTA_23 skip
2855 18:11:32.842694 alsa_mixer-test_write_valid_LCALTA_23 skip
2856 18:11:32.843146 alsa_mixer-test_write_invalid_LCALTA_23 skip
2857 18:11:32.848168 alsa_mixer-test_event_missing_LCALTA_23 pass
2858 18:11:32.853683 alsa_mixer-test_event_spurious_LCALTA_23 pass
2859 18:11:32.854133 alsa_mixer-test_get_value_LCALTA_22 pass
2860 18:11:32.859232 alsa_mixer-test_name_LCALTA_22 pass
2861 18:11:32.864792 alsa_mixer-test_write_default_LCALTA_22 pass
2862 18:11:32.865240 alsa_mixer-test_write_valid_LCALTA_22 pass
2863 18:11:32.870392 alsa_mixer-test_write_invalid_LCALTA_22 pass
2864 18:11:32.875851 alsa_mixer-test_event_missing_LCALTA_22 pass
2865 18:11:32.881397 alsa_mixer-test_event_spurious_LCALTA_22 pass
2866 18:11:32.881908 alsa_mixer-test_get_value_LCALTA_21 pass
2867 18:11:32.886938 alsa_mixer-test_name_LCALTA_21 pass
2868 18:11:32.892559 alsa_mixer-test_write_default_LCALTA_21 pass
2869 18:11:32.893014 alsa_mixer-test_write_valid_LCALTA_21 pass
2870 18:11:32.898064 alsa_mixer-test_write_invalid_LCALTA_21 pass
2871 18:11:32.903661 alsa_mixer-test_event_missing_LCALTA_21 pass
2872 18:11:32.904149 alsa_mixer-test_event_spurious_LCALTA_21 pass
2873 18:11:32.909164 alsa_mixer-test_get_value_LCALTA_20 pass
2874 18:11:32.914719 alsa_mixer-test_name_LCALTA_20 pass
2875 18:11:32.915173 alsa_mixer-test_write_default_LCALTA_20 pass
2876 18:11:32.920267 alsa_mixer-test_write_valid_LCALTA_20 pass
2877 18:11:32.925825 alsa_mixer-test_write_invalid_LCALTA_20 pass
2878 18:11:32.926359 alsa_mixer-test_event_missing_LCALTA_20 pass
2879 18:11:32.931347 alsa_mixer-test_event_spurious_LCALTA_20 pass
2880 18:11:32.936903 alsa_mixer-test_get_value_LCALTA_19 pass
2881 18:11:32.937516 alsa_mixer-test_name_LCALTA_19 pass
2882 18:11:32.942406 alsa_mixer-test_write_default_LCALTA_19 pass
2883 18:11:32.947945 alsa_mixer-test_write_valid_LCALTA_19 pass
2884 18:11:32.953513 alsa_mixer-test_write_invalid_LCALTA_19 pass
2885 18:11:32.953954 alsa_mixer-test_event_missing_LCALTA_19 pass
2886 18:11:32.959039 alsa_mixer-test_event_spurious_LCALTA_19 pass
2887 18:11:32.964675 alsa_mixer-test_get_value_LCALTA_18 pass
2888 18:11:32.965131 alsa_mixer-test_name_LCALTA_18 pass
2889 18:11:32.970155 alsa_mixer-test_write_default_LCALTA_18 pass
2890 18:11:32.975721 alsa_mixer-test_write_valid_LCALTA_18 pass
2891 18:11:32.976198 alsa_mixer-test_write_invalid_LCALTA_18 pass
2892 18:11:32.981302 alsa_mixer-test_event_missing_LCALTA_18 pass
2893 18:11:32.986866 alsa_mixer-test_event_spurious_LCALTA_18 pass
2894 18:11:32.987308 alsa_mixer-test_get_value_LCALTA_17 pass
2895 18:11:32.992368 alsa_mixer-test_name_LCALTA_17 pass
2896 18:11:32.997924 alsa_mixer-test_write_default_LCALTA_17 pass
2897 18:11:32.998451 alsa_mixer-test_write_valid_LCALTA_17 pass
2898 18:11:33.003410 alsa_mixer-test_write_invalid_LCALTA_17 pass
2899 18:11:33.008974 alsa_mixer-test_event_missing_LCALTA_17 pass
2900 18:11:33.014541 alsa_mixer-test_event_spurious_LCALTA_17 pass
2901 18:11:33.014985 alsa_mixer-test_get_value_LCALTA_16 pass
2902 18:11:33.020069 alsa_mixer-test_name_LCALTA_16 pass
2903 18:11:33.025630 alsa_mixer-test_write_default_LCALTA_16 pass
2904 18:11:33.026071 alsa_mixer-test_write_valid_LCALTA_16 pass
2905 18:11:33.031197 alsa_mixer-test_write_invalid_LCALTA_16 pass
2906 18:11:33.036735 alsa_mixer-test_event_missing_LCALTA_16 pass
2907 18:11:33.037179 alsa_mixer-test_event_spurious_LCALTA_16 pass
2908 18:11:33.042315 alsa_mixer-test_get_value_LCALTA_15 pass
2909 18:11:33.047850 alsa_mixer-test_name_LCALTA_15 pass
2910 18:11:33.048506 alsa_mixer-test_write_default_LCALTA_15 pass
2911 18:11:33.053373 alsa_mixer-test_write_valid_LCALTA_15 pass
2912 18:11:33.058937 alsa_mixer-test_write_invalid_LCALTA_15 pass
2913 18:11:33.064479 alsa_mixer-test_event_missing_LCALTA_15 pass
2914 18:11:33.064948 alsa_mixer-test_event_spurious_LCALTA_15 pass
2915 18:11:33.069989 alsa_mixer-test_get_value_LCALTA_14 pass
2916 18:11:33.070441 alsa_mixer-test_name_LCALTA_14 pass
2917 18:11:33.075566 alsa_mixer-test_write_default_LCALTA_14 pass
2918 18:11:33.081088 alsa_mixer-test_write_valid_LCALTA_14 pass
2919 18:11:33.086714 alsa_mixer-test_write_invalid_LCALTA_14 pass
2920 18:11:33.087181 alsa_mixer-test_event_missing_LCALTA_14 pass
2921 18:11:33.092222 alsa_mixer-test_event_spurious_LCALTA_14 pass
2922 18:11:33.097839 alsa_mixer-test_get_value_LCALTA_13 pass
2923 18:11:33.098297 alsa_mixer-test_name_LCALTA_13 pass
2924 18:11:33.103309 alsa_mixer-test_write_default_LCALTA_13 pass
2925 18:11:33.108919 alsa_mixer-test_write_valid_LCALTA_13 pass
2926 18:11:33.109455 alsa_mixer-test_write_invalid_LCALTA_13 pass
2927 18:11:33.114382 alsa_mixer-test_event_missing_LCALTA_13 pass
2928 18:11:33.119938 alsa_mixer-test_event_spurious_LCALTA_13 pass
2929 18:11:33.125479 alsa_mixer-test_get_value_LCALTA_12 pass
2930 18:11:33.125937 alsa_mixer-test_name_LCALTA_12 pass
2931 18:11:33.131027 alsa_mixer-test_write_default_LCALTA_12 pass
2932 18:11:33.136567 alsa_mixer-test_write_valid_LCALTA_12 pass
2933 18:11:33.137022 alsa_mixer-test_write_invalid_LCALTA_12 pass
2934 18:11:33.142131 alsa_mixer-test_event_missing_LCALTA_12 pass
2935 18:11:33.147693 alsa_mixer-test_event_spurious_LCALTA_12 pass
2936 18:11:33.148173 alsa_mixer-test_get_value_LCALTA_11 pass
2937 18:11:33.153293 alsa_mixer-test_name_LCALTA_11 pass
2938 18:11:33.158770 alsa_mixer-test_write_default_LCALTA_11 pass
2939 18:11:33.159226 alsa_mixer-test_write_valid_LCALTA_11 pass
2940 18:11:33.164411 alsa_mixer-test_write_invalid_LCALTA_11 pass
2941 18:11:33.169845 alsa_mixer-test_event_missing_LCALTA_11 pass
2942 18:11:33.170308 alsa_mixer-test_event_spurious_LCALTA_11 pass
2943 18:11:33.175399 alsa_mixer-test_get_value_LCALTA_10 pass
2944 18:11:33.180959 alsa_mixer-test_name_LCALTA_10 pass
2945 18:11:33.181429 alsa_mixer-test_write_default_LCALTA_10 pass
2946 18:11:33.186529 alsa_mixer-test_write_valid_LCALTA_10 pass
2947 18:11:33.192066 alsa_mixer-test_write_invalid_LCALTA_10 pass
2948 18:11:33.197679 alsa_mixer-test_event_missing_LCALTA_10 pass
2949 18:11:33.198156 alsa_mixer-test_event_spurious_LCALTA_10 pass
2950 18:11:33.203134 alsa_mixer-test_get_value_LCALTA_9 pass
2951 18:11:33.208840 alsa_mixer-test_name_LCALTA_9 pass
2952 18:11:33.209318 alsa_mixer-test_write_default_LCALTA_9 pass
2953 18:11:33.214232 alsa_mixer-test_write_valid_LCALTA_9 pass
2954 18:11:33.219823 alsa_mixer-test_write_invalid_LCALTA_9 pass
2955 18:11:33.220390 alsa_mixer-test_event_missing_LCALTA_9 pass
2956 18:11:33.225330 alsa_mixer-test_event_spurious_LCALTA_9 pass
2957 18:11:33.230838 alsa_mixer-test_get_value_LCALTA_8 pass
2958 18:11:33.231298 alsa_mixer-test_name_LCALTA_8 pass
2959 18:11:33.236361 alsa_mixer-test_write_default_LCALTA_8 pass
2960 18:11:33.241930 alsa_mixer-test_write_valid_LCALTA_8 pass
2961 18:11:33.242379 alsa_mixer-test_write_invalid_LCALTA_8 pass
2962 18:11:33.247468 alsa_mixer-test_event_missing_LCALTA_8 pass
2963 18:11:33.253016 alsa_mixer-test_event_spurious_LCALTA_8 pass
2964 18:11:33.253483 alsa_mixer-test_get_value_LCALTA_7 pass
2965 18:11:33.258573 alsa_mixer-test_name_LCALTA_7 pass
2966 18:11:33.264245 alsa_mixer-test_write_default_LCALTA_7 pass
2967 18:11:33.264698 alsa_mixer-test_write_valid_LCALTA_7 pass
2968 18:11:33.269786 alsa_mixer-test_write_invalid_LCALTA_7 pass
2969 18:11:33.275223 alsa_mixer-test_event_missing_LCALTA_7 pass
2970 18:11:33.275835 alsa_mixer-test_event_spurious_LCALTA_7 pass
2971 18:11:33.280734 alsa_mixer-test_get_value_LCALTA_6 pass
2972 18:11:33.286292 alsa_mixer-test_name_LCALTA_6 pass
2973 18:11:33.286758 alsa_mixer-test_write_default_LCALTA_6 pass
2974 18:11:33.291815 alsa_mixer-test_write_valid_LCALTA_6 pass
2975 18:11:33.297356 alsa_mixer-test_write_invalid_LCALTA_6 pass
2976 18:11:33.297800 alsa_mixer-test_event_missing_LCALTA_6 pass
2977 18:11:33.302944 alsa_mixer-test_event_spurious_LCALTA_6 pass
2978 18:11:33.308468 alsa_mixer-test_get_value_LCALTA_5 pass
2979 18:11:33.308918 alsa_mixer-test_name_LCALTA_5 pass
2980 18:11:33.314023 alsa_mixer-test_write_default_LCALTA_5 pass
2981 18:11:33.319552 alsa_mixer-test_write_valid_LCALTA_5 pass
2982 18:11:33.320042 alsa_mixer-test_write_invalid_LCALTA_5 pass
2983 18:11:33.325108 alsa_mixer-test_event_missing_LCALTA_5 pass
2984 18:11:33.330694 alsa_mixer-test_event_spurious_LCALTA_5 pass
2985 18:11:33.331218 alsa_mixer-test_get_value_LCALTA_4 pass
2986 18:11:33.336246 alsa_mixer-test_name_LCALTA_4 pass
2987 18:11:33.341756 alsa_mixer-test_write_default_LCALTA_4 pass
2988 18:11:33.342231 alsa_mixer-test_write_valid_LCALTA_4 pass
2989 18:11:33.347296 alsa_mixer-test_write_invalid_LCALTA_4 pass
2990 18:11:33.352833 alsa_mixer-test_event_missing_LCALTA_4 pass
2991 18:11:33.358383 alsa_mixer-test_event_spurious_LCALTA_4 pass
2992 18:11:33.358823 alsa_mixer-test_get_value_LCALTA_3 pass
2993 18:11:33.363925 alsa_mixer-test_name_LCALTA_3 pass
2994 18:11:33.364384 alsa_mixer-test_write_default_LCALTA_3 pass
2995 18:11:33.369484 alsa_mixer-test_write_valid_LCALTA_3 pass
2996 18:11:33.375058 alsa_mixer-test_write_invalid_LCALTA_3 pass
2997 18:11:33.380573 alsa_mixer-test_event_missing_LCALTA_3 pass
2998 18:11:33.381014 alsa_mixer-test_event_spurious_LCALTA_3 pass
2999 18:11:33.386147 alsa_mixer-test_get_value_LCALTA_2 pass
3000 18:11:33.386653 alsa_mixer-test_name_LCALTA_2 pass
3001 18:11:33.391695 alsa_mixer-test_write_default_LCALTA_2 pass
3002 18:11:33.397217 alsa_mixer-test_write_valid_LCALTA_2 pass
3003 18:11:33.402730 alsa_mixer-test_write_invalid_LCALTA_2 pass
3004 18:11:33.403177 alsa_mixer-test_event_missing_LCALTA_2 pass
3005 18:11:33.408298 alsa_mixer-test_event_spurious_LCALTA_2 pass
3006 18:11:33.413847 alsa_mixer-test_get_value_LCALTA_1 pass
3007 18:11:33.414277 alsa_mixer-test_name_LCALTA_1 pass
3008 18:11:33.419402 alsa_mixer-test_write_default_LCALTA_1 pass
3009 18:11:33.424927 alsa_mixer-test_write_valid_LCALTA_1 pass
3010 18:11:33.425361 alsa_mixer-test_write_invalid_LCALTA_1 pass
3011 18:11:33.430538 alsa_mixer-test_event_missing_LCALTA_1 pass
3012 18:11:33.436086 alsa_mixer-test_event_spurious_LCALTA_1 pass
3013 18:11:33.436533 alsa_mixer-test_get_value_LCALTA_0 pass
3014 18:11:33.441621 alsa_mixer-test_name_LCALTA_0 pass
3015 18:11:33.447161 alsa_mixer-test_write_default_LCALTA_0 pass
3016 18:11:33.447663 alsa_mixer-test_write_valid_LCALTA_0 pass
3017 18:11:33.452682 alsa_mixer-test_write_invalid_LCALTA_0 pass
3018 18:11:33.458234 alsa_mixer-test_event_missing_LCALTA_0 pass
3019 18:11:33.458674 alsa_mixer-test_event_spurious_LCALTA_0 pass
3020 18:11:33.463764 alsa_mixer-test pass
3021 18:11:33.469305 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3022 18:11:33.469742 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3023 18:11:33.474838 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3024 18:11:33.480412 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3025 18:11:33.485934 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3026 18:11:33.491502 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3027 18:11:33.491933 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3028 18:11:33.497045 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3029 18:11:33.502620 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3030 18:11:33.508194 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3031 18:11:33.513690 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3032 18:11:33.519295 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3033 18:11:33.519845 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3034 18:11:33.524784 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3035 18:11:33.530362 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3036 18:11:33.535886 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3037 18:11:33.541438 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3038 18:11:33.547020 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3039 18:11:33.547561 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3040 18:11:33.552637 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3041 18:11:33.558159 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3042 18:11:33.563736 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3043 18:11:33.569262 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3044 18:11:33.574771 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3045 18:11:33.575250 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3046 18:11:33.580321 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3047 18:11:33.585843 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3048 18:11:33.591409 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3049 18:11:33.596932 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3050 18:11:33.602500 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3051 18:11:33.608026 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3052 18:11:33.608498 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3053 18:11:33.613700 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3054 18:11:33.619184 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3055 18:11:33.624669 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3056 18:11:33.630256 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3057 18:11:33.635759 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3058 18:11:33.636263 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3059 18:11:33.641314 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3060 18:11:33.646880 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3061 18:11:33.652388 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3062 18:11:33.657940 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3063 18:11:33.658406 alsa_pcm-test pass
3064 18:11:33.669113 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3065 18:11:33.674630 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3066 18:11:33.685677 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3067 18:11:33.691256 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3068 18:11:33.702337 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3069 18:11:33.702844 alsa_test-pcmtest-driver pass
3070 18:11:33.707923 alsa_utimer-test_global_wrong_timers_test pass
3071 18:11:33.713409 alsa_utimer-test_timer_f_utimer fail
3072 18:11:33.713886 alsa_utimer-test fail
3073 18:11:33.718937 + ../../utils/send-to-lava.sh ./output/result.txt
3074 18:11:33.724535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3075 18:11:33.725506 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3077 18:11:33.730061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3078 18:11:33.730796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3080 18:11:33.735609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3081 18:11:33.736350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3083 18:11:33.745633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3084 18:11:33.746371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3086 18:11:33.794929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3087 18:11:33.795727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3089 18:11:33.842592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3090 18:11:33.843383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3092 18:11:33.891728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3093 18:11:33.892539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3095 18:11:33.949797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3096 18:11:33.950579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3098 18:11:34.000768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3099 18:11:34.001566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3101 18:11:34.045862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3102 18:11:34.046646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3104 18:11:34.362236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3105 18:11:34.363095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3107 18:11:34.409465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3108 18:11:34.410249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3110 18:11:34.468077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3111 18:11:34.468848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3113 18:11:34.523817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3114 18:11:34.524646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3116 18:11:34.569689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3117 18:11:34.570456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3119 18:11:34.618226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3120 18:11:34.618990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3122 18:11:34.660467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3123 18:11:34.661224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3125 18:11:34.706461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3126 18:11:34.707208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3128 18:11:34.751405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3129 18:11:34.752126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3131 18:11:34.804187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3132 18:11:34.804943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3134 18:11:34.852381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3135 18:11:34.853132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3137 18:11:34.906546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3138 18:11:34.907296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3140 18:11:34.951267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3141 18:11:34.952039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3143 18:11:35.001037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3144 18:11:35.001797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3146 18:11:35.059251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3147 18:11:35.060047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3149 18:11:35.114519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3150 18:11:35.115275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3152 18:11:35.161330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3153 18:11:35.162061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3155 18:11:35.212069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3156 18:11:35.212834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3158 18:11:35.267634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3159 18:11:35.268455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3161 18:11:35.309693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3162 18:11:35.310442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3164 18:11:35.359238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3165 18:11:35.360003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3167 18:11:35.409668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3168 18:11:35.410403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3170 18:11:35.461398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3171 18:11:35.462333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3173 18:11:35.510214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3174 18:11:35.511110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3176 18:11:35.557917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3177 18:11:35.558913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3179 18:11:35.610594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3180 18:11:35.611530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3182 18:11:35.663508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3183 18:11:35.664456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3185 18:11:35.714602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3186 18:11:35.715531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3188 18:11:35.764763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3189 18:11:35.765693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3191 18:11:35.815699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3192 18:11:35.816663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3194 18:11:35.876550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3195 18:11:35.877507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3197 18:11:35.927011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3198 18:11:35.927941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3200 18:11:35.980065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3201 18:11:35.980980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3203 18:11:36.034989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3204 18:11:36.035940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3206 18:11:36.090581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3207 18:11:36.091510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3209 18:11:36.148293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3210 18:11:36.149221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3212 18:11:36.198042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3213 18:11:36.198964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3215 18:11:36.257521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3216 18:11:36.258434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3218 18:11:36.301478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3219 18:11:36.302401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3221 18:11:36.359535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3222 18:11:36.360506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3224 18:11:36.414249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3225 18:11:36.415166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3227 18:11:36.472024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3228 18:11:36.472944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3230 18:11:36.532084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3231 18:11:36.533026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3233 18:11:36.580258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3234 18:11:36.581197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3236 18:11:36.640268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3237 18:11:36.641205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3239 18:11:36.691348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3240 18:11:36.692325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3242 18:11:36.741215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3243 18:11:36.742131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3245 18:11:36.798383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3246 18:11:36.799302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3248 18:11:36.844494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3249 18:11:36.845390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3251 18:11:36.900063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3252 18:11:36.900989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3254 18:11:36.956036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3255 18:11:36.956948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3257 18:11:37.015954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3258 18:11:37.016872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3260 18:11:37.070066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3261 18:11:37.070981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3263 18:11:37.126177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3264 18:11:37.127087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3266 18:11:37.178919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3267 18:11:37.179818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3269 18:11:37.227801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3270 18:11:37.228761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3272 18:11:37.292836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3273 18:11:37.293755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3275 18:11:37.337267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3276 18:11:37.338190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3278 18:11:37.401392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3279 18:11:37.402320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3281 18:11:37.453780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3282 18:11:37.454663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3284 18:11:37.507938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3285 18:11:37.508877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3287 18:11:37.562826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3288 18:11:37.563760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3290 18:11:37.619239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3291 18:11:37.620142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3293 18:11:37.671586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3294 18:11:37.672534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3296 18:11:37.722601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3297 18:11:37.723505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3299 18:11:37.778658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3300 18:11:37.779579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3302 18:11:37.842283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3303 18:11:37.843196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3305 18:11:37.886277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3306 18:11:37.887205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3308 18:11:37.936847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3309 18:11:37.937756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3311 18:11:37.987487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3312 18:11:37.988394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3314 18:11:38.042232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3315 18:11:38.043162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3317 18:11:38.086723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3318 18:11:38.087648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3320 18:11:38.146979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3321 18:11:38.147898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3323 18:11:38.210509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3324 18:11:38.211416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3326 18:11:38.265612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3327 18:11:38.266516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3329 18:11:38.321797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3330 18:11:38.322719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3332 18:11:38.370336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3333 18:11:38.371259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3335 18:11:38.423003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3336 18:11:38.423938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3338 18:11:38.486412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3339 18:11:38.487282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3341 18:11:38.532539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3342 18:11:38.533444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3344 18:11:38.590938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3345 18:11:38.591799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3347 18:11:38.647427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3348 18:11:38.648323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3350 18:11:38.702796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3351 18:11:38.703642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3353 18:11:38.757875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3354 18:11:38.758753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3356 18:11:38.816337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3357 18:11:38.817201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3359 18:11:38.862525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3360 18:11:38.863378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3362 18:11:38.909725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3363 18:11:38.910579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3365 18:11:38.955357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3366 18:11:38.956210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3368 18:11:39.006808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3369 18:11:39.007662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3371 18:11:39.059947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3372 18:11:39.061003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3374 18:11:39.115500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3375 18:11:39.116402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3377 18:11:39.163518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3378 18:11:39.164387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3380 18:11:39.213754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3381 18:11:39.214605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3383 18:11:39.267965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3384 18:11:39.268829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3386 18:11:39.326220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3387 18:11:39.327149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3389 18:11:39.377901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3390 18:11:39.378781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3392 18:11:39.438369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3393 18:11:39.439229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3395 18:11:39.488784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3396 18:11:39.489652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3398 18:11:39.807041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3399 18:11:39.807828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3400 18:11:39.808746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3402 18:11:39.810431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3404 18:11:39.812171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3405 18:11:39.812751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3406 18:11:39.813301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3407 18:11:39.813837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3408 18:11:39.814657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3410 18:11:39.816320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3412 18:11:39.817936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3414 18:11:39.819506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3416 18:11:39.852466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3417 18:11:39.853371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3419 18:11:39.904724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3420 18:11:39.905661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3422 18:11:39.955126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3423 18:11:39.956069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3425 18:11:40.007383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3426 18:11:40.008314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3428 18:11:40.059523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3429 18:11:40.060449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3431 18:11:40.105225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3432 18:11:40.106117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3434 18:11:40.150707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3435 18:11:40.151588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3437 18:11:40.200893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3438 18:11:40.201796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3440 18:11:40.248751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3441 18:11:40.249664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3443 18:11:40.296709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3444 18:11:40.297691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3446 18:11:40.349770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3447 18:11:40.350664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3449 18:11:40.400747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3450 18:11:40.401640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3452 18:11:40.452466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3453 18:11:40.453345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3455 18:11:40.507184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3456 18:11:40.508072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3458 18:11:40.552011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3459 18:11:40.553026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3461 18:11:40.604047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3462 18:11:40.604951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3464 18:11:40.652473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3465 18:11:40.653389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3467 18:11:40.698324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3468 18:11:40.699218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3470 18:11:40.742738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3471 18:11:40.743635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3473 18:11:40.793661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3474 18:11:40.794572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3476 18:11:40.848071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3477 18:11:40.848970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3479 18:11:40.894541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3480 18:11:40.895456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3482 18:11:40.941167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3483 18:11:40.942057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3485 18:11:41.001241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3486 18:11:41.002146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3488 18:11:41.046041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3489 18:11:41.046934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3491 18:11:41.099288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3492 18:11:41.100165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3494 18:11:41.143207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3495 18:11:41.144111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3497 18:11:41.193420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3498 18:11:41.194312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3500 18:11:41.252398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3501 18:11:41.253301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3503 18:11:41.308205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3504 18:11:41.309145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3506 18:11:41.359650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3507 18:11:41.360769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3509 18:11:41.413422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3510 18:11:41.414361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3512 18:11:41.467295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3513 18:11:41.468208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3515 18:11:41.526073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3516 18:11:41.527023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3518 18:11:41.585811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3519 18:11:41.586755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3521 18:11:41.643651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3522 18:11:41.644618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3524 18:11:41.699267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3525 18:11:41.700173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3527 18:11:41.751172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3528 18:11:41.752107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3530 18:11:41.803482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3531 18:11:41.804428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3533 18:11:41.858978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3534 18:11:41.859889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3536 18:11:41.912917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3537 18:11:41.913869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3539 18:11:41.956305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3540 18:11:41.957197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3542 18:11:42.000938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3543 18:11:42.001823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3545 18:11:42.051235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3546 18:11:42.052110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3548 18:11:42.103685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3549 18:11:42.104658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3551 18:11:42.160466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3552 18:11:42.161369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3554 18:11:42.204215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3555 18:11:42.205104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3557 18:11:42.261853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3558 18:11:42.262739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3560 18:11:42.308000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3561 18:11:42.308910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3563 18:11:42.363690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3564 18:11:42.364695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3566 18:11:42.417644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3567 18:11:42.418568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3569 18:11:42.475015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3570 18:11:42.475904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3572 18:11:42.535783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3573 18:11:42.536768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3575 18:11:42.588949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3576 18:11:42.589881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3578 18:11:42.641664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3579 18:11:42.642556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3581 18:11:42.706382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3582 18:11:42.707276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3584 18:11:42.757426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3585 18:11:42.758317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3587 18:11:42.808167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3588 18:11:42.809074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3590 18:11:42.862717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3591 18:11:42.863675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3593 18:11:42.917243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3594 18:11:42.918166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3596 18:11:42.969886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3597 18:11:42.970772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3599 18:11:43.021537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3600 18:11:43.022426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3602 18:11:43.071058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3603 18:11:43.071944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3605 18:11:43.121115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3606 18:11:43.122018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3608 18:11:43.177398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3609 18:11:43.178348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3611 18:11:43.233285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3612 18:11:43.234239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3614 18:11:43.287421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3615 18:11:43.288388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3617 18:11:43.339142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3618 18:11:43.340057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3620 18:11:43.394136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3621 18:11:43.395022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3623 18:11:43.452498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3624 18:11:43.453389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3626 18:11:43.503958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3627 18:11:43.504881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3629 18:11:43.556212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3630 18:11:43.557112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3632 18:11:43.613712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3633 18:11:43.614568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3635 18:11:43.656339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3636 18:11:43.657191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3638 18:11:43.713587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3639 18:11:43.714414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3641 18:11:43.767402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3642 18:11:43.768237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3644 18:11:43.824401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3645 18:11:43.825240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3647 18:11:43.874923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3648 18:11:43.875806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3650 18:11:43.937028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3651 18:11:43.937887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3653 18:11:43.992090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3654 18:11:43.992925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3656 18:11:44.047962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3657 18:11:44.048818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3659 18:11:44.101648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3660 18:11:44.102472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3662 18:11:44.156455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3663 18:11:44.157294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3665 18:11:44.207882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3666 18:11:44.208749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3668 18:11:44.265644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3669 18:11:44.266489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3671 18:11:44.312255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3672 18:11:44.313105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3674 18:11:44.373117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3675 18:11:44.373971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3677 18:11:44.429999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3678 18:11:44.430825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3680 18:11:44.485025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3681 18:11:44.485877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3683 18:11:44.538644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3684 18:11:44.539524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3686 18:11:44.592925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3687 18:11:44.593799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3689 18:11:44.648530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3690 18:11:44.649429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3692 18:11:44.703887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3693 18:11:44.704818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3695 18:11:44.754831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3696 18:11:44.755710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3698 18:11:44.807489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3699 18:11:44.808417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3701 18:11:44.857836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3702 18:11:44.858715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3704 18:11:44.910641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3705 18:11:44.911518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3707 18:11:44.963091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3708 18:11:44.963952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3710 18:11:45.009610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3711 18:11:45.010465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3713 18:11:45.067382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3714 18:11:45.068272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3716 18:11:45.122192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3717 18:11:45.123046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3719 18:11:45.182503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3720 18:11:45.183350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3722 18:11:45.225985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3723 18:11:45.226851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3725 18:11:45.275094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3726 18:11:45.276030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3728 18:11:45.325980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3729 18:11:45.326906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3731 18:11:45.379878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3732 18:11:45.380793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3734 18:11:45.439408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3735 18:11:45.440305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3737 18:11:45.482157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3738 18:11:45.482986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3740 18:11:45.529646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3741 18:11:45.530536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3743 18:11:45.579182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3744 18:11:45.580119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3746 18:11:45.631428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3747 18:11:45.632414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3749 18:11:45.686319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3750 18:11:45.687186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3752 18:11:45.743555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3753 18:11:45.744483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3755 18:11:45.800275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3756 18:11:45.801180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3758 18:11:45.851597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3759 18:11:45.852539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3761 18:11:45.904670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3762 18:11:45.905569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3764 18:11:45.959943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3765 18:11:45.960931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3767 18:11:46.006977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3768 18:11:46.007830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3770 18:11:46.053672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3771 18:11:46.054562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3773 18:11:46.113343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3774 18:11:46.114242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3776 18:11:46.165228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3777 18:11:46.166129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3779 18:11:46.214720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3780 18:11:46.215615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3782 18:11:46.270968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3783 18:11:46.271864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3785 18:11:46.322764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3786 18:11:46.323658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3788 18:11:46.376535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3789 18:11:46.377416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3791 18:11:46.428621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3792 18:11:46.429540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3794 18:11:46.485174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3795 18:11:46.486105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3797 18:11:46.538250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3798 18:11:46.539198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3800 18:11:46.594547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3801 18:11:46.595472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3803 18:11:46.644964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3804 18:11:46.645876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3806 18:11:46.696703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3807 18:11:46.697617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3809 18:11:46.742194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3810 18:11:46.743097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3812 18:11:46.799882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3813 18:11:46.800824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3815 18:11:46.846346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3816 18:11:46.847252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3818 18:11:46.903813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3819 18:11:46.904873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3821 18:11:46.958891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3822 18:11:46.959823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3824 18:11:47.013966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3825 18:11:47.014877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3827 18:11:47.066760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3828 18:11:47.067660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3830 18:11:47.117098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3831 18:11:47.118016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3833 18:11:47.167109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3834 18:11:47.167966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3836 18:11:47.220637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3837 18:11:47.221545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3839 18:11:47.274298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3840 18:11:47.275211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3842 18:11:47.321349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3843 18:11:47.322119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3845 18:11:47.371352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3846 18:11:47.372110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3848 18:11:47.428180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3849 18:11:47.428933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3851 18:11:47.479400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3852 18:11:47.480149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3854 18:11:47.531289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3855 18:11:47.532045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3857 18:11:47.571567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3858 18:11:47.572371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3860 18:11:47.624057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3861 18:11:47.624785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3863 18:11:47.675055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3864 18:11:47.675775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3866 18:11:47.728742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3867 18:11:47.729451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3869 18:11:47.780134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3870 18:11:47.781027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3872 18:11:47.840383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3873 18:11:47.841252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3875 18:11:47.890853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3876 18:11:47.891739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3878 18:11:47.942210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3879 18:11:47.943078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3881 18:11:47.992244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3882 18:11:47.993131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3884 18:11:48.051526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3885 18:11:48.052446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3887 18:11:48.109539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3888 18:11:48.110376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3890 18:11:48.157671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3891 18:11:48.158513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3893 18:11:48.218004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3894 18:11:48.218937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3896 18:11:48.275261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3897 18:11:48.276167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3899 18:11:48.326427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3900 18:11:48.327286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3902 18:11:48.375507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3903 18:11:48.376410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3905 18:11:48.425443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3906 18:11:48.426318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3908 18:11:48.476188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3909 18:11:48.477047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3911 18:11:48.529590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3912 18:11:48.530450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3914 18:11:48.588299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3915 18:11:48.589236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3917 18:11:48.650057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3918 18:11:48.650928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3920 18:11:48.704362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3921 18:11:48.705289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3923 18:11:48.761109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3924 18:11:48.762021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3926 18:11:48.809115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3927 18:11:48.809991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3929 18:11:48.858170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3930 18:11:48.859015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3932 18:11:48.916231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3933 18:11:48.917082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3935 18:11:48.970568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3936 18:11:48.971426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3938 18:11:49.022610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3939 18:11:49.023459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3941 18:11:49.078136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3942 18:11:49.078997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3944 18:11:49.127561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3945 18:11:49.128411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3947 18:11:49.176812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3948 18:11:49.177655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3950 18:11:49.235047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3951 18:11:49.235887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3953 18:11:49.285947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3954 18:11:49.286833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3956 18:11:49.333379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3957 18:11:49.334263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3959 18:11:49.384732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3960 18:11:49.385614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3962 18:11:49.434184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3963 18:11:49.435061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3965 18:11:49.482383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3966 18:11:49.483234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3968 18:11:49.535074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3969 18:11:49.535926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3971 18:11:49.586600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3972 18:11:49.587538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3974 18:11:49.640733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3975 18:11:49.641591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3977 18:11:49.685705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3978 18:11:49.686560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3980 18:11:49.738584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3981 18:11:49.739428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3983 18:11:49.789014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3984 18:11:49.789878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3986 18:11:49.845350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3987 18:11:49.846212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3989 18:11:49.896626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3990 18:11:49.897494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3992 18:11:49.948029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3993 18:11:49.948888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3995 18:11:50.000551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3996 18:11:50.001407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3998 18:11:50.055812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3999 18:11:50.056730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
4001 18:11:50.102304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
4002 18:11:50.103157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
4004 18:11:50.156320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4005 18:11:50.157171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4007 18:11:50.208631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4008 18:11:50.209476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4010 18:11:50.254046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4011 18:11:50.254889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4013 18:11:50.306242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4014 18:11:50.307096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4016 18:11:50.355629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4017 18:11:50.356595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4019 18:11:50.400197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4020 18:11:50.401042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4022 18:11:50.447100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4023 18:11:50.447911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4025 18:11:50.489280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4026 18:11:50.490102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4028 18:11:50.542641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4029 18:11:50.543621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4031 18:11:50.606450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4032 18:11:50.607387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4034 18:11:50.661619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4035 18:11:50.662631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4037 18:11:50.713450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4038 18:11:50.714393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4040 18:11:50.768220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4041 18:11:50.769124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4043 18:11:50.820694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4044 18:11:50.821617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4046 18:11:50.870337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4047 18:11:50.871263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4049 18:11:50.927657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4050 18:11:50.928653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4052 18:11:50.986981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4053 18:11:50.987889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4055 18:11:51.036456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4056 18:11:51.037391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4058 18:11:51.092209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4059 18:11:51.093172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4061 18:11:51.148252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4062 18:11:51.149180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4064 18:11:51.200231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4065 18:11:51.201132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4067 18:11:51.252738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4068 18:11:51.253624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4070 18:11:51.304327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4071 18:11:51.305272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4073 18:11:51.359172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4074 18:11:51.360108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4076 18:11:51.413982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4077 18:11:51.414871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4079 18:11:51.465736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4080 18:11:51.466589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4082 18:11:51.520034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4083 18:11:51.520917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4085 18:11:51.566199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4086 18:11:51.567109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4088 18:11:51.616100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4089 18:11:51.617035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4091 18:11:51.670204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4092 18:11:51.671065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4094 18:11:51.733541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4095 18:11:51.734424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4097 18:11:51.786231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4098 18:11:51.787077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4100 18:11:51.838945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4101 18:11:51.839798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4103 18:11:51.889305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4104 18:11:51.890159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4106 18:11:51.937591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4107 18:11:51.938450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4109 18:11:51.991376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4110 18:11:51.992281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4112 18:11:52.044845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4113 18:11:52.045715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4115 18:11:52.102591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4116 18:11:52.103446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4118 18:11:52.157086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4119 18:11:52.157940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4121 18:11:52.198934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4122 18:11:52.199789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4124 18:11:52.260329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4125 18:11:52.261175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4127 18:11:52.310265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4128 18:11:52.311117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4130 18:11:52.362053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4131 18:11:52.362904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4133 18:11:52.411324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4134 18:11:52.412181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4136 18:11:52.463615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4137 18:11:52.464516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4139 18:11:52.513755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4140 18:11:52.514585 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4142 18:11:52.570255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4143 18:11:52.571151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4145 18:11:52.627065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4146 18:11:52.627941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4148 18:11:52.709421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4149 18:11:52.710405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4151 18:11:52.770480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4152 18:11:52.771369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4154 18:11:52.826114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4155 18:11:52.826981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4157 18:11:52.884121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4158 18:11:52.885001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4160 18:11:52.935755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4161 18:11:52.936681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4163 18:11:52.990490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4164 18:11:52.991347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4166 18:11:53.039823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4167 18:11:53.040715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4169 18:11:53.092520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4170 18:11:53.093391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4172 18:11:53.137358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4173 18:11:53.138232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4175 18:11:53.199041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4176 18:11:53.199916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4178 18:11:53.252080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4179 18:11:53.252936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4181 18:11:53.302290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4182 18:11:53.303141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4184 18:11:53.355356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4185 18:11:53.356213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4187 18:11:53.409373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4188 18:11:53.410349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4190 18:11:53.455054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4191 18:11:53.456063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4193 18:11:53.511723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4194 18:11:53.512708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4196 18:11:53.561504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4197 18:11:53.562542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4199 18:11:53.612403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4200 18:11:53.613452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4202 18:11:53.662625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4203 18:11:53.663585 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4205 18:11:53.711354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4206 18:11:53.712338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4208 18:11:53.768153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4209 18:11:53.769120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4211 18:11:53.822302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4212 18:11:53.823245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4214 18:11:53.865814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4215 18:11:53.866758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4217 18:11:53.909848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4218 18:11:53.910818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4220 18:11:53.964755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4221 18:11:53.965710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4223 18:11:54.019830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4224 18:11:54.020837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4226 18:11:54.073615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4227 18:11:54.074559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4229 18:11:54.123473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4230 18:11:54.124478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4232 18:11:54.176233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4233 18:11:54.177247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4235 18:11:54.233324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4236 18:11:54.234285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4238 18:11:54.279663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4239 18:11:54.280628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4241 18:11:54.330070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4242 18:11:54.331021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4244 18:11:54.383606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4245 18:11:54.384616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4247 18:11:54.442571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4248 18:11:54.443506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4250 18:11:54.492965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4251 18:11:54.493904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4253 18:11:54.543302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4254 18:11:54.544380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4256 18:11:54.602708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4257 18:11:54.603655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4259 18:11:54.658736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4260 18:11:54.659670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4262 18:11:54.721509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4263 18:11:54.722445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4265 18:11:54.772353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4266 18:11:54.773291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4268 18:11:54.816637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4269 18:11:54.817607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4271 18:11:54.866192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4272 18:11:54.867137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4274 18:11:54.919509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4275 18:11:54.920497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4277 18:11:54.972413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4278 18:11:54.973361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4280 18:11:55.031369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4281 18:11:55.032353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4283 18:11:55.085230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4284 18:11:55.086175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4286 18:11:55.146997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4287 18:11:55.147972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4289 18:11:55.195453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4290 18:11:55.196424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4292 18:11:55.245954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4293 18:11:55.246888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4295 18:11:55.296346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4296 18:11:55.297287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4298 18:11:55.348635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4299 18:11:55.349595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4301 18:11:55.400751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4302 18:11:55.401824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4304 18:11:55.451952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4305 18:11:55.452957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4307 18:11:55.501652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4308 18:11:55.502548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4310 18:11:55.555213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4311 18:11:55.556255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4313 18:11:55.599882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4314 18:11:55.600824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4316 18:11:55.650863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4317 18:11:55.651931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4319 18:11:55.703865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4320 18:11:55.704851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4322 18:11:55.753743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4323 18:11:55.754707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4325 18:11:55.799281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4326 18:11:55.800235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4328 18:11:55.855510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4329 18:11:55.856501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4331 18:11:55.901691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4332 18:11:55.902680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4334 18:11:55.948110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4335 18:11:55.949092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4337 18:11:56.004339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4338 18:11:56.005287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4340 18:11:56.057991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4341 18:11:56.058933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4343 18:11:56.104895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4344 18:11:56.105861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4346 18:11:56.159548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4347 18:11:56.160542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4349 18:11:56.213969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4350 18:11:56.214902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4352 18:11:56.262442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4353 18:11:56.263363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4355 18:11:56.313528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4356 18:11:56.314412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4358 18:11:56.353497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4360 18:11:56.356468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4361 18:11:56.404722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4362 18:11:56.405607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4364 18:11:56.460793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4365 18:11:56.461660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4367 18:11:56.507795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4368 18:11:56.508695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4370 18:11:56.554882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4371 18:11:56.555805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4373 18:11:56.604032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4374 18:11:56.604919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4376 18:11:56.656390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4377 18:11:56.657278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4379 18:11:56.705630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4380 18:11:56.706505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4382 18:11:56.757415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4383 18:11:56.758296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4385 18:11:56.804049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4386 18:11:56.804912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4388 18:11:56.854136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4389 18:11:56.855005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4391 18:11:56.905401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4392 18:11:56.906263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4394 18:11:56.957067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4395 18:11:56.957914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4397 18:11:57.007720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4398 18:11:57.008649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4400 18:11:57.058179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4401 18:11:57.059081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4403 18:11:57.112369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4404 18:11:57.113275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4406 18:11:57.165125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4407 18:11:57.166009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4409 18:11:57.222766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4410 18:11:57.223651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4412 18:11:57.277034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4413 18:11:57.277896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4415 18:11:57.331019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4416 18:11:57.331889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4418 18:11:57.383632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4419 18:11:57.384538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4421 18:11:57.440246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4422 18:11:57.441094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4424 18:11:57.490291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4425 18:11:57.491169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4427 18:11:57.542747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4428 18:11:57.543677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4430 18:11:57.589218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4431 18:11:57.590077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4433 18:11:57.637322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4434 18:11:57.638184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4436 18:11:57.691772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4437 18:11:57.692779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4439 18:11:57.746630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4440 18:11:57.747515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4442 18:11:57.809607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4443 18:11:57.810468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4445 18:11:57.861639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4446 18:11:57.862507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4448 18:11:57.912639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4449 18:11:57.913509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4451 18:11:57.961987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4452 18:11:57.962864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4454 18:11:58.012289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4455 18:11:58.013162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4457 18:11:58.068228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4458 18:11:58.069101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4460 18:11:58.121161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4461 18:11:58.122034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4463 18:11:58.173147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4464 18:11:58.174026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4466 18:11:58.230960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4467 18:11:58.231820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4469 18:11:58.284375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4470 18:11:58.285236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4472 18:11:58.335603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4473 18:11:58.336506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4475 18:11:58.390275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4476 18:11:58.391145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4478 18:11:58.443372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4479 18:11:58.444286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4481 18:11:58.495631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4482 18:11:58.496515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4484 18:11:58.547852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4485 18:11:58.548790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4487 18:11:58.597353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4488 18:11:58.598205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4490 18:11:58.649331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4491 18:11:58.650195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4493 18:11:58.695154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4494 18:11:58.696058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4496 18:11:58.753301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4497 18:11:58.754180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4499 18:11:58.812091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4500 18:11:58.812973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4502 18:11:58.864635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4503 18:11:58.865506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4505 18:11:58.905698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4506 18:11:58.906579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4508 18:11:58.954166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4509 18:11:58.955031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4511 18:11:59.003557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4512 18:11:59.004431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4514 18:11:59.057199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4516 18:11:59.062365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4517 18:11:59.062928 + set +x
4518 18:11:59.068346 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 941220_1.6.2.4.5>
4519 18:11:59.068901 <LAVA_TEST_RUNNER EXIT>
4520 18:11:59.069680 Received signal: <ENDRUN> 1_kselftest-alsa 941220_1.6.2.4.5
4521 18:11:59.070260 Ending use of test pattern.
4522 18:11:59.070789 Ending test lava.1_kselftest-alsa (941220_1.6.2.4.5), duration 40.63
4524 18:11:59.072807 ok: lava_test_shell seems to have completed
4525 18:11:59.101783 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4526 18:11:59.103920 end: 3.1 lava-test-shell (duration 00:00:41) [common]
4527 18:11:59.104690 end: 3 lava-test-retry (duration 00:00:41) [common]
4528 18:11:59.105428 start: 4 finalize (timeout 00:06:03) [common]
4529 18:11:59.106148 start: 4.1 power-off (timeout 00:00:30) [common]
4530 18:11:59.107362 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4531 18:11:59.143440 >> OK - accepted request
4532 18:11:59.145577 Returned 0 in 0 seconds
4533 18:11:59.246955 end: 4.1 power-off (duration 00:00:00) [common]
4535 18:11:59.249131 start: 4.2 read-feedback (timeout 00:06:03) [common]
4536 18:11:59.250520 Listened to connection for namespace 'common' for up to 1s
4537 18:12:00.251276 Finalising connection for namespace 'common'
4538 18:12:00.252200 Disconnecting from shell: Finalise
4539 18:12:00.252880 / #
4540 18:12:00.354063 end: 4.2 read-feedback (duration 00:00:01) [common]
4541 18:12:00.354934 end: 4 finalize (duration 00:00:01) [common]
4542 18:12:00.355843 Cleaning after the job
4543 18:12:00.356737 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/ramdisk
4544 18:12:00.373329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/kernel
4545 18:12:00.406098 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/dtb
4546 18:12:00.407002 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/nfsrootfs
4547 18:12:00.463955 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/941220/tftp-deploy-3kekei07/modules
4548 18:12:00.474475 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/941220
4549 18:12:04.235339 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/941220
4550 18:12:04.235896 Job finished correctly