Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 18:58:53.547332 lava-dispatcher, installed at version: 2024.01
2 18:58:53.548200 start: 0 validate
3 18:58:53.548677 Start time: 2024-10-08 18:58:53.548648+00:00 (UTC)
4 18:58:53.549232 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 18:58:53.549785 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 18:58:53.588732 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 18:58:53.589310 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-5-gf7efea4fcf4b9%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 18:58:53.620684 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 18:58:53.621305 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-5-gf7efea4fcf4b9%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 18:58:54.676576 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 18:58:54.677294 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-5-gf7efea4fcf4b9%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 18:58:54.719117 validate duration: 1.17
14 18:58:54.719971 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 18:58:54.720323 start: 1.1 download-retry (timeout 00:10:00) [common]
16 18:58:54.720631 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 18:58:54.721234 Not decompressing ramdisk as can be used compressed.
18 18:58:54.721660 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 18:58:54.721928 saving as /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/ramdisk/rootfs.cpio.gz
20 18:58:54.722202 total size: 8181887 (7 MB)
21 18:58:54.759652 progress 0 % (0 MB)
22 18:58:54.767533 progress 5 % (0 MB)
23 18:58:54.776750 progress 10 % (0 MB)
24 18:58:54.787741 progress 15 % (1 MB)
25 18:58:54.793280 progress 20 % (1 MB)
26 18:58:54.799031 progress 25 % (1 MB)
27 18:58:54.804359 progress 30 % (2 MB)
28 18:58:54.810069 progress 35 % (2 MB)
29 18:58:54.815357 progress 40 % (3 MB)
30 18:58:54.821076 progress 45 % (3 MB)
31 18:58:54.826481 progress 50 % (3 MB)
32 18:58:54.832171 progress 55 % (4 MB)
33 18:58:54.837444 progress 60 % (4 MB)
34 18:58:54.843171 progress 65 % (5 MB)
35 18:58:54.848437 progress 70 % (5 MB)
36 18:58:54.854051 progress 75 % (5 MB)
37 18:58:54.859213 progress 80 % (6 MB)
38 18:58:54.864816 progress 85 % (6 MB)
39 18:58:54.870070 progress 90 % (7 MB)
40 18:58:54.875688 progress 95 % (7 MB)
41 18:58:54.880606 progress 100 % (7 MB)
42 18:58:54.881255 7 MB downloaded in 0.16 s (49.06 MB/s)
43 18:58:54.881796 end: 1.1.1 http-download (duration 00:00:00) [common]
45 18:58:54.882670 end: 1.1 download-retry (duration 00:00:00) [common]
46 18:58:54.882955 start: 1.2 download-retry (timeout 00:10:00) [common]
47 18:58:54.883220 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 18:58:54.883746 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-5-gf7efea4fcf4b9/arm64/defconfig/gcc-12/kernel/Image
49 18:58:54.884034 saving as /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/kernel/Image
50 18:58:54.884248 total size: 45713920 (43 MB)
51 18:58:54.884456 No compression specified
52 18:58:54.915501 progress 0 % (0 MB)
53 18:58:54.947119 progress 5 % (2 MB)
54 18:58:54.979132 progress 10 % (4 MB)
55 18:58:55.009372 progress 15 % (6 MB)
56 18:58:55.039270 progress 20 % (8 MB)
57 18:58:55.068745 progress 25 % (10 MB)
58 18:58:55.098253 progress 30 % (13 MB)
59 18:58:55.128291 progress 35 % (15 MB)
60 18:58:55.157895 progress 40 % (17 MB)
61 18:58:55.187300 progress 45 % (19 MB)
62 18:58:55.217588 progress 50 % (21 MB)
63 18:58:55.247437 progress 55 % (24 MB)
64 18:58:55.277276 progress 60 % (26 MB)
65 18:58:55.306782 progress 65 % (28 MB)
66 18:58:55.336460 progress 70 % (30 MB)
67 18:58:55.365922 progress 75 % (32 MB)
68 18:58:55.395371 progress 80 % (34 MB)
69 18:58:55.425084 progress 85 % (37 MB)
70 18:58:55.454849 progress 90 % (39 MB)
71 18:58:55.484289 progress 95 % (41 MB)
72 18:58:55.512984 progress 100 % (43 MB)
73 18:58:55.513508 43 MB downloaded in 0.63 s (69.28 MB/s)
74 18:58:55.513989 end: 1.2.1 http-download (duration 00:00:01) [common]
76 18:58:55.514792 end: 1.2 download-retry (duration 00:00:01) [common]
77 18:58:55.515061 start: 1.3 download-retry (timeout 00:09:59) [common]
78 18:58:55.515323 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 18:58:55.515796 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-5-gf7efea4fcf4b9/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 18:58:55.516101 saving as /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 18:58:55.516312 total size: 53209 (0 MB)
82 18:58:55.516520 No compression specified
83 18:58:55.558356 progress 61 % (0 MB)
84 18:58:55.559206 progress 100 % (0 MB)
85 18:58:55.559746 0 MB downloaded in 0.04 s (1.17 MB/s)
86 18:58:55.560258 end: 1.3.1 http-download (duration 00:00:00) [common]
88 18:58:55.561079 end: 1.3 download-retry (duration 00:00:00) [common]
89 18:58:55.561339 start: 1.4 download-retry (timeout 00:09:59) [common]
90 18:58:55.561600 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 18:58:55.562056 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-5-gf7efea4fcf4b9/arm64/defconfig/gcc-12/modules.tar.xz
92 18:58:55.562306 saving as /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/modules/modules.tar
93 18:58:55.562509 total size: 11593096 (11 MB)
94 18:58:55.562717 Using unxz to decompress xz
95 18:58:55.604787 progress 0 % (0 MB)
96 18:58:55.675512 progress 5 % (0 MB)
97 18:58:55.752140 progress 10 % (1 MB)
98 18:58:55.835294 progress 15 % (1 MB)
99 18:58:55.912052 progress 20 % (2 MB)
100 18:58:55.989915 progress 25 % (2 MB)
101 18:58:56.072009 progress 30 % (3 MB)
102 18:58:56.147473 progress 35 % (3 MB)
103 18:58:56.229135 progress 40 % (4 MB)
104 18:58:56.314984 progress 45 % (5 MB)
105 18:58:56.391613 progress 50 % (5 MB)
106 18:58:56.476808 progress 55 % (6 MB)
107 18:58:56.561371 progress 60 % (6 MB)
108 18:58:56.641516 progress 65 % (7 MB)
109 18:58:56.724724 progress 70 % (7 MB)
110 18:58:56.806749 progress 75 % (8 MB)
111 18:58:56.889938 progress 80 % (8 MB)
112 18:58:56.968440 progress 85 % (9 MB)
113 18:58:57.037668 progress 90 % (9 MB)
114 18:58:57.136223 progress 95 % (10 MB)
115 18:58:57.227752 progress 100 % (11 MB)
116 18:58:57.245248 11 MB downloaded in 1.68 s (6.57 MB/s)
117 18:58:57.246202 end: 1.4.1 http-download (duration 00:00:02) [common]
119 18:58:57.247796 end: 1.4 download-retry (duration 00:00:02) [common]
120 18:58:57.248364 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 18:58:57.248883 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 18:58:57.249373 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 18:58:57.249868 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 18:58:57.250834 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr
125 18:58:57.251672 makedir: /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin
126 18:58:57.252353 makedir: /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/tests
127 18:58:57.252979 makedir: /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/results
128 18:58:57.253627 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-add-keys
129 18:58:57.254604 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-add-sources
130 18:58:57.255541 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-background-process-start
131 18:58:57.256519 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-background-process-stop
132 18:58:57.257500 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-common-functions
133 18:58:57.258414 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-echo-ipv4
134 18:58:57.259321 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-install-packages
135 18:58:57.260258 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-installed-packages
136 18:58:57.261210 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-os-build
137 18:58:57.262132 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-probe-channel
138 18:58:57.263036 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-probe-ip
139 18:58:57.263928 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-target-ip
140 18:58:57.264880 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-target-mac
141 18:58:57.265779 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-target-storage
142 18:58:57.266684 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-test-case
143 18:58:57.267586 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-test-event
144 18:58:57.268539 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-test-feedback
145 18:58:57.269461 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-test-raise
146 18:58:57.270357 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-test-reference
147 18:58:57.271249 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-test-runner
148 18:58:57.272181 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-test-set
149 18:58:57.273085 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-test-shell
150 18:58:57.274104 Updating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-install-packages (oe)
151 18:58:57.275095 Updating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/bin/lava-installed-packages (oe)
152 18:58:57.275925 Creating /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/environment
153 18:58:57.276452 LAVA metadata
154 18:58:57.276735 - LAVA_JOB_ID=823095
155 18:58:57.276956 - LAVA_DISPATCHER_IP=192.168.6.2
156 18:58:57.277329 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 18:58:57.278345 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 18:58:57.278701 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 18:58:57.278920 skipped lava-vland-overlay
160 18:58:57.279166 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 18:58:57.279423 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 18:58:57.279644 skipped lava-multinode-overlay
163 18:58:57.279890 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 18:58:57.280195 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 18:58:57.280453 Loading test definitions
166 18:58:57.280739 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 18:58:57.280968 Using /lava-823095 at stage 0
168 18:58:57.282242 uuid=823095_1.5.2.4.1 testdef=None
169 18:58:57.282585 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 18:58:57.282859 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 18:58:57.284767 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 18:58:57.285599 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 18:58:57.287845 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 18:58:57.288790 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 18:58:57.290988 runner path: /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/0/tests/0_dmesg test_uuid 823095_1.5.2.4.1
178 18:58:57.291572 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 18:58:57.292406 Creating lava-test-runner.conf files
181 18:58:57.292614 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/823095/lava-overlay-v1wi3zhr/lava-823095/0 for stage 0
182 18:58:57.292959 - 0_dmesg
183 18:58:57.293320 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 18:58:57.293609 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 18:58:57.317905 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 18:58:57.318334 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 18:58:57.318658 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 18:58:57.318942 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 18:58:57.319210 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 18:58:58.238561 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 18:58:58.239089 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 18:58:58.239599 extracting modules file /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823095/extract-overlay-ramdisk-q8_9uj02/ramdisk
193 18:58:59.643932 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 18:58:59.644437 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 18:58:59.644728 [common] Applying overlay /var/lib/lava/dispatcher/tmp/823095/compress-overlay-l3pnfrt8/overlay-1.5.2.5.tar.gz to ramdisk
196 18:58:59.644956 [common] Applying overlay /var/lib/lava/dispatcher/tmp/823095/compress-overlay-l3pnfrt8/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/823095/extract-overlay-ramdisk-q8_9uj02/ramdisk
197 18:58:59.675685 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 18:58:59.676185 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 18:58:59.676467 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 18:58:59.676695 Converting downloaded kernel to a uImage
201 18:58:59.677008 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/kernel/Image /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/kernel/uImage
202 18:59:00.133357 output: Image Name:
203 18:59:00.133779 output: Created: Tue Oct 8 18:58:59 2024
204 18:59:00.133989 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 18:59:00.134195 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 18:59:00.134395 output: Load Address: 01080000
207 18:59:00.134593 output: Entry Point: 01080000
208 18:59:00.134790 output:
209 18:59:00.135122 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 18:59:00.135387 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 18:59:00.135654 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 18:59:00.135905 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 18:59:00.136205 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 18:59:00.136475 Building ramdisk /var/lib/lava/dispatcher/tmp/823095/extract-overlay-ramdisk-q8_9uj02/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/823095/extract-overlay-ramdisk-q8_9uj02/ramdisk
215 18:59:02.778254 >> 181555 blocks
216 18:59:11.300461 Adding RAMdisk u-boot header.
217 18:59:11.301121 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/823095/extract-overlay-ramdisk-q8_9uj02/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/823095/extract-overlay-ramdisk-q8_9uj02/ramdisk.cpio.gz.uboot
218 18:59:11.594228 output: Image Name:
219 18:59:11.594635 output: Created: Tue Oct 8 18:59:11 2024
220 18:59:11.595103 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 18:59:11.595566 output: Data Size: 26056579 Bytes = 25445.88 KiB = 24.85 MiB
222 18:59:11.596066 output: Load Address: 00000000
223 18:59:11.596376 output: Entry Point: 00000000
224 18:59:11.596586 output:
225 18:59:11.597353 rename /var/lib/lava/dispatcher/tmp/823095/extract-overlay-ramdisk-q8_9uj02/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/ramdisk/ramdisk.cpio.gz.uboot
226 18:59:11.597788 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 18:59:11.598147 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 18:59:11.598741 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 18:59:11.599263 No LXC device requested
230 18:59:11.599829 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 18:59:11.600448 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 18:59:11.601005 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 18:59:11.601462 Checking files for TFTP limit of 4294967296 bytes.
234 18:59:11.604467 end: 1 tftp-deploy (duration 00:00:17) [common]
235 18:59:11.605134 start: 2 uboot-action (timeout 00:05:00) [common]
236 18:59:11.605737 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 18:59:11.606302 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 18:59:11.606863 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 18:59:11.607461 Using kernel file from prepare-kernel: 823095/tftp-deploy-v8rygn0a/kernel/uImage
240 18:59:11.608214 substitutions:
241 18:59:11.608694 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 18:59:11.609144 - {DTB_ADDR}: 0x01070000
243 18:59:11.609451 - {DTB}: 823095/tftp-deploy-v8rygn0a/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 18:59:11.609673 - {INITRD}: 823095/tftp-deploy-v8rygn0a/ramdisk/ramdisk.cpio.gz.uboot
245 18:59:11.609886 - {KERNEL_ADDR}: 0x01080000
246 18:59:11.610094 - {KERNEL}: 823095/tftp-deploy-v8rygn0a/kernel/uImage
247 18:59:11.610304 - {LAVA_MAC}: None
248 18:59:11.610794 - {PRESEED_CONFIG}: None
249 18:59:11.611253 - {PRESEED_LOCAL}: None
250 18:59:11.611564 - {RAMDISK_ADDR}: 0x08000000
251 18:59:11.611770 - {RAMDISK}: 823095/tftp-deploy-v8rygn0a/ramdisk/ramdisk.cpio.gz.uboot
252 18:59:11.611974 - {ROOT_PART}: None
253 18:59:11.612192 - {ROOT}: None
254 18:59:11.612394 - {SERVER_IP}: 192.168.6.2
255 18:59:11.612755 - {TEE_ADDR}: 0x83000000
256 18:59:11.613206 - {TEE}: None
257 18:59:11.613646 Parsed boot commands:
258 18:59:11.614071 - setenv autoload no
259 18:59:11.614357 - setenv initrd_high 0xffffffff
260 18:59:11.614564 - setenv fdt_high 0xffffffff
261 18:59:11.614764 - dhcp
262 18:59:11.614962 - setenv serverip 192.168.6.2
263 18:59:11.615159 - tftpboot 0x01080000 823095/tftp-deploy-v8rygn0a/kernel/uImage
264 18:59:11.615358 - tftpboot 0x08000000 823095/tftp-deploy-v8rygn0a/ramdisk/ramdisk.cpio.gz.uboot
265 18:59:11.615557 - tftpboot 0x01070000 823095/tftp-deploy-v8rygn0a/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 18:59:11.615919 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 18:59:11.616392 - bootm 0x01080000 0x08000000 0x01070000
268 18:59:11.616960 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 18:59:11.617809 start: 2.3 connect-device (timeout 00:05:00) [common]
271 18:59:11.618058 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 18:59:11.632203 Setting prompt string to ['lava-test: # ']
273 18:59:11.633820 end: 2.3 connect-device (duration 00:00:00) [common]
274 18:59:11.634479 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 18:59:11.635067 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 18:59:11.635803 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 18:59:11.637136 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 18:59:11.675921 >> OK - accepted request
279 18:59:11.678072 Returned 0 in 0 seconds
280 18:59:11.779290 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 18:59:11.781167 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 18:59:11.781792 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 18:59:11.782343 Setting prompt string to ['Hit any key to stop autoboot']
285 18:59:11.782830 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 18:59:11.784666 Trying 192.168.56.21...
287 18:59:11.785264 Connected to conserv1.
288 18:59:11.785725 Escape character is '^]'.
289 18:59:11.786191
290 18:59:11.786647 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 18:59:11.787115
292 18:59:19.222639 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 18:59:19.223321 bl2_stage_init 0x01
294 18:59:19.223819 bl2_stage_init 0x81
295 18:59:19.228241 hw id: 0x0000 - pwm id 0x01
296 18:59:19.228746 bl2_stage_init 0xc1
297 18:59:19.233678 bl2_stage_init 0x02
298 18:59:19.234170
299 18:59:19.234637 L0:00000000
300 18:59:19.235116 L1:00000703
301 18:59:19.235586 L2:00008067
302 18:59:19.236060 L3:15000000
303 18:59:19.239338 S1:00000000
304 18:59:19.239816 B2:20282000
305 18:59:19.240297 B1:a0f83180
306 18:59:19.240742
307 18:59:19.241185 TE: 71038
308 18:59:19.241626
309 18:59:19.244947 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 18:59:19.245426
311 18:59:19.250557 Board ID = 1
312 18:59:19.251029 Set cpu clk to 24M
313 18:59:19.251470 Set clk81 to 24M
314 18:59:19.256081 Use GP1_pll as DSU clk.
315 18:59:19.256553 DSU clk: 1200 Mhz
316 18:59:19.256996 CPU clk: 1200 MHz
317 18:59:19.261658 Set clk81 to 166.6M
318 18:59:19.267310 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 18:59:19.267781 board id: 1
320 18:59:19.273655 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 18:59:19.285184 fw parse done
322 18:59:19.291203 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 18:59:19.333708 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 18:59:19.344714 PIEI prepare done
325 18:59:19.345180 fastboot data load
326 18:59:19.345629 fastboot data verify
327 18:59:19.350297 verify result: 266
328 18:59:19.355852 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 18:59:19.356359 LPDDR4 probe
330 18:59:19.356807 ddr clk to 1584MHz
331 18:59:19.363856 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 18:59:19.401063
333 18:59:19.401536 dmc_version 0001
334 18:59:19.407764 Check phy result
335 18:59:19.413673 INFO : End of CA training
336 18:59:19.414139 INFO : End of initialization
337 18:59:19.419322 INFO : Training has run successfully!
338 18:59:19.419790 Check phy result
339 18:59:19.424877 INFO : End of initialization
340 18:59:19.425338 INFO : End of read enable training
341 18:59:19.430495 INFO : End of fine write leveling
342 18:59:19.436079 INFO : End of Write leveling coarse delay
343 18:59:19.436543 INFO : Training has run successfully!
344 18:59:19.436989 Check phy result
345 18:59:19.441681 INFO : End of initialization
346 18:59:19.442144 INFO : End of read dq deskew training
347 18:59:19.447328 INFO : End of MPR read delay center optimization
348 18:59:19.452886 INFO : End of write delay center optimization
349 18:59:19.458500 INFO : End of read delay center optimization
350 18:59:19.458966 INFO : End of max read latency training
351 18:59:19.464082 INFO : Training has run successfully!
352 18:59:19.464545 1D training succeed
353 18:59:19.473270 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 18:59:19.520811 Check phy result
355 18:59:19.521289 INFO : End of initialization
356 18:59:19.543172 INFO : End of 2D read delay Voltage center optimization
357 18:59:19.562357 INFO : End of 2D read delay Voltage center optimization
358 18:59:19.614239 INFO : End of 2D write delay Voltage center optimization
359 18:59:19.663496 INFO : End of 2D write delay Voltage center optimization
360 18:59:19.669004 INFO : Training has run successfully!
361 18:59:19.669475
362 18:59:19.669928 channel==0
363 18:59:19.674611 RxClkDly_Margin_A0==88 ps 9
364 18:59:19.675089 TxDqDly_Margin_A0==98 ps 10
365 18:59:19.680214 RxClkDly_Margin_A1==69 ps 7
366 18:59:19.680671 TxDqDly_Margin_A1==88 ps 9
367 18:59:19.681120 TrainedVREFDQ_A0==74
368 18:59:19.685793 TrainedVREFDQ_A1==74
369 18:59:19.686262 VrefDac_Margin_A0==24
370 18:59:19.686702 DeviceVref_Margin_A0==40
371 18:59:19.691488 VrefDac_Margin_A1==22
372 18:59:19.691951 DeviceVref_Margin_A1==40
373 18:59:19.692435
374 18:59:19.692881
375 18:59:19.693316 channel==1
376 18:59:19.697003 RxClkDly_Margin_A0==78 ps 8
377 18:59:19.697470 TxDqDly_Margin_A0==98 ps 10
378 18:59:19.702593 RxClkDly_Margin_A1==88 ps 9
379 18:59:19.703055 TxDqDly_Margin_A1==78 ps 8
380 18:59:19.708210 TrainedVREFDQ_A0==78
381 18:59:19.708676 TrainedVREFDQ_A1==75
382 18:59:19.709118 VrefDac_Margin_A0==22
383 18:59:19.713799 DeviceVref_Margin_A0==36
384 18:59:19.714262 VrefDac_Margin_A1==22
385 18:59:19.719496 DeviceVref_Margin_A1==39
386 18:59:19.719958
387 18:59:19.720434 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 18:59:19.720873
389 18:59:19.753001 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 18:59:19.753538 2D training succeed
391 18:59:19.758608 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 18:59:19.764204 auto size-- 65535DDR cs0 size: 2048MB
393 18:59:19.764668 DDR cs1 size: 2048MB
394 18:59:19.769789 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 18:59:19.770254 cs0 DataBus test pass
396 18:59:19.775502 cs1 DataBus test pass
397 18:59:19.775967 cs0 AddrBus test pass
398 18:59:19.776451 cs1 AddrBus test pass
399 18:59:19.776891
400 18:59:19.780988 100bdlr_step_size ps== 478
401 18:59:19.781468 result report
402 18:59:19.786569 boot times 0Enable ddr reg access
403 18:59:19.791750 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 18:59:19.805638 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 18:59:20.460082 bl2z: ptr: 05129330, size: 00001e40
406 18:59:20.468191 0.0;M3 CHK:0;cm4_sp_mode 0
407 18:59:20.468466 MVN_1=0x00000000
408 18:59:20.468679 MVN_2=0x00000000
409 18:59:20.479685 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 18:59:20.480105 OPS=0x04
411 18:59:20.480423 ring efuse init
412 18:59:20.485360 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 18:59:20.485715 [0.017318 Inits done]
414 18:59:20.486023 secure task start!
415 18:59:20.493309 high task start!
416 18:59:20.493563 low task start!
417 18:59:20.493769 run into bl31
418 18:59:20.501914 NOTICE: BL31: v1.3(release):4fc40b1
419 18:59:20.509721 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 18:59:20.510072 NOTICE: BL31: G12A normal boot!
421 18:59:20.525367 NOTICE: BL31: BL33 decompress pass
422 18:59:20.531045 ERROR: Error initializing runtime service opteed_fast
423 18:59:23.274340 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 18:59:23.274757 bl2_stage_init 0x01
425 18:59:23.274971 bl2_stage_init 0x81
426 18:59:23.279910 hw id: 0x0000 - pwm id 0x01
427 18:59:23.280231 bl2_stage_init 0xc1
428 18:59:23.285424 bl2_stage_init 0x02
429 18:59:23.285662
430 18:59:23.285871 L0:00000000
431 18:59:23.286073 L1:00000703
432 18:59:23.286272 L2:00008067
433 18:59:23.286469 L3:15000000
434 18:59:23.291030 S1:00000000
435 18:59:23.291272 B2:20282000
436 18:59:23.291474 B1:a0f83180
437 18:59:23.291671
438 18:59:23.291870 TE: 71736
439 18:59:23.292091
440 18:59:23.296661 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 18:59:23.296890
442 18:59:23.302224 Board ID = 1
443 18:59:23.302468 Set cpu clk to 24M
444 18:59:23.302673 Set clk81 to 24M
445 18:59:23.307912 Use GP1_pll as DSU clk.
446 18:59:23.308170 DSU clk: 1200 Mhz
447 18:59:23.308375 CPU clk: 1200 MHz
448 18:59:23.313540 Set clk81 to 166.6M
449 18:59:23.319116 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 18:59:23.319357 board id: 1
451 18:59:23.326320 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 18:59:23.337233 fw parse done
453 18:59:23.343197 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 18:59:23.386314 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 18:59:23.397433 PIEI prepare done
456 18:59:23.397675 fastboot data load
457 18:59:23.397880 fastboot data verify
458 18:59:23.403015 verify result: 266
459 18:59:23.408610 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 18:59:23.408843 LPDDR4 probe
461 18:59:23.409044 ddr clk to 1584MHz
462 18:59:23.416600 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 18:59:23.454322
464 18:59:23.454581 dmc_version 0001
465 18:59:23.461365 Check phy result
466 18:59:23.467349 INFO : End of CA training
467 18:59:23.467589 INFO : End of initialization
468 18:59:23.472952 INFO : Training has run successfully!
469 18:59:23.473197 Check phy result
470 18:59:23.478475 INFO : End of initialization
471 18:59:23.478734 INFO : End of read enable training
472 18:59:23.481896 INFO : End of fine write leveling
473 18:59:23.487400 INFO : End of Write leveling coarse delay
474 18:59:23.492969 INFO : Training has run successfully!
475 18:59:23.493229 Check phy result
476 18:59:23.493437 INFO : End of initialization
477 18:59:23.498586 INFO : End of read dq deskew training
478 18:59:23.504155 INFO : End of MPR read delay center optimization
479 18:59:23.504387 INFO : End of write delay center optimization
480 18:59:23.509914 INFO : End of read delay center optimization
481 18:59:23.517026 INFO : End of max read latency training
482 18:59:23.517279 INFO : Training has run successfully!
483 18:59:23.521364 1D training succeed
484 18:59:23.527086 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 18:59:23.575152 Check phy result
486 18:59:23.575420 INFO : End of initialization
487 18:59:23.602535 INFO : End of 2D read delay Voltage center optimization
488 18:59:23.626744 INFO : End of 2D read delay Voltage center optimization
489 18:59:23.683387 INFO : End of 2D write delay Voltage center optimization
490 18:59:23.737516 INFO : End of 2D write delay Voltage center optimization
491 18:59:23.743087 INFO : Training has run successfully!
492 18:59:23.743411
493 18:59:23.743623 channel==0
494 18:59:23.748556 RxClkDly_Margin_A0==78 ps 8
495 18:59:23.749015 TxDqDly_Margin_A0==98 ps 10
496 18:59:23.754262 RxClkDly_Margin_A1==88 ps 9
497 18:59:23.754735 TxDqDly_Margin_A1==88 ps 9
498 18:59:23.755125 TrainedVREFDQ_A0==74
499 18:59:23.759863 TrainedVREFDQ_A1==74
500 18:59:23.760260 VrefDac_Margin_A0==23
501 18:59:23.760589 DeviceVref_Margin_A0==40
502 18:59:23.765500 VrefDac_Margin_A1==22
503 18:59:23.766082 DeviceVref_Margin_A1==40
504 18:59:23.766343
505 18:59:23.766549
506 18:59:23.766749 channel==1
507 18:59:23.771068 RxClkDly_Margin_A0==78 ps 8
508 18:59:23.771445 TxDqDly_Margin_A0==98 ps 10
509 18:59:23.776647 RxClkDly_Margin_A1==78 ps 8
510 18:59:23.776997 TxDqDly_Margin_A1==88 ps 9
511 18:59:23.782239 TrainedVREFDQ_A0==78
512 18:59:23.782595 TrainedVREFDQ_A1==78
513 18:59:23.782826 VrefDac_Margin_A0==22
514 18:59:23.787857 DeviceVref_Margin_A0==36
515 18:59:23.788135 VrefDac_Margin_A1==22
516 18:59:23.793455 DeviceVref_Margin_A1==36
517 18:59:23.793703
518 18:59:23.793908 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 18:59:23.794106
520 18:59:23.827033 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
521 18:59:23.827446 2D training succeed
522 18:59:23.832631 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 18:59:23.838251 auto size-- 65535DDR cs0 size: 2048MB
524 18:59:23.838629 DDR cs1 size: 2048MB
525 18:59:23.843845 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 18:59:23.844231 cs0 DataBus test pass
527 18:59:23.849417 cs1 DataBus test pass
528 18:59:23.849691 cs0 AddrBus test pass
529 18:59:23.849900 cs1 AddrBus test pass
530 18:59:23.850104
531 18:59:23.855011 100bdlr_step_size ps== 471
532 18:59:23.855272 result report
533 18:59:23.860608 boot times 0Enable ddr reg access
534 18:59:23.865755 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 18:59:23.879609 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 18:59:24.539130 bl2z: ptr: 05129330, size: 00001e40
537 18:59:24.546866 0.0;M3 CHK:0;cm4_sp_mode 0
538 18:59:24.547150 MVN_1=0x00000000
539 18:59:24.547361 MVN_2=0x00000000
540 18:59:24.558467 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 18:59:24.558875 OPS=0x04
542 18:59:24.559217 ring efuse init
543 18:59:24.561322 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 18:59:24.567123 [0.017354 Inits done]
545 18:59:24.567367 secure task start!
546 18:59:24.567567 high task start!
547 18:59:24.567762 low task start!
548 18:59:24.571455 run into bl31
549 18:59:24.580137 NOTICE: BL31: v1.3(release):4fc40b1
550 18:59:24.587816 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 18:59:24.588198 NOTICE: BL31: G12A normal boot!
552 18:59:24.603344 NOTICE: BL31: BL33 decompress pass
553 18:59:24.609134 ERROR: Error initializing runtime service opteed_fast
554 18:59:25.972478 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 18:59:25.972894 bl2_stage_init 0x01
556 18:59:25.973108 bl2_stage_init 0x81
557 18:59:25.977903 hw id: 0x0000 - pwm id 0x01
558 18:59:25.978136 bl2_stage_init 0xc1
559 18:59:25.983513 bl2_stage_init 0x02
560 18:59:25.983754
561 18:59:25.983961 L0:00000000
562 18:59:25.984190 L1:00000703
563 18:59:25.984389 L2:00008067
564 18:59:25.984588 L3:15000000
565 18:59:25.989239 S1:00000000
566 18:59:25.989469 B2:20282000
567 18:59:25.989670 B1:a0f83180
568 18:59:25.989867
569 18:59:25.990066 TE: 70892
570 18:59:25.990264
571 18:59:25.994732 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 18:59:25.994963
573 18:59:26.000316 Board ID = 1
574 18:59:26.000550 Set cpu clk to 24M
575 18:59:26.000752 Set clk81 to 24M
576 18:59:26.005925 Use GP1_pll as DSU clk.
577 18:59:26.006181 DSU clk: 1200 Mhz
578 18:59:26.006385 CPU clk: 1200 MHz
579 18:59:26.011532 Set clk81 to 166.6M
580 18:59:26.017219 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 18:59:26.017449 board id: 1
582 18:59:26.024319 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 18:59:26.034994 fw parse done
584 18:59:26.040944 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 18:59:26.083635 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 18:59:26.094648 PIEI prepare done
587 18:59:26.095029 fastboot data load
588 18:59:26.095251 fastboot data verify
589 18:59:26.100194 verify result: 266
590 18:59:26.105735 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 18:59:26.106068 LPDDR4 probe
592 18:59:26.106274 ddr clk to 1584MHz
593 18:59:26.113661 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 18:59:26.150919
595 18:59:26.151227 dmc_version 0001
596 18:59:26.157585 Check phy result
597 18:59:26.163506 INFO : End of CA training
598 18:59:26.163744 INFO : End of initialization
599 18:59:26.169091 INFO : Training has run successfully!
600 18:59:26.169323 Check phy result
601 18:59:26.174678 INFO : End of initialization
602 18:59:26.174911 INFO : End of read enable training
603 18:59:26.180279 INFO : End of fine write leveling
604 18:59:26.185888 INFO : End of Write leveling coarse delay
605 18:59:26.186134 INFO : Training has run successfully!
606 18:59:26.186338 Check phy result
607 18:59:26.191487 INFO : End of initialization
608 18:59:26.191720 INFO : End of read dq deskew training
609 18:59:26.197107 INFO : End of MPR read delay center optimization
610 18:59:26.202716 INFO : End of write delay center optimization
611 18:59:26.208298 INFO : End of read delay center optimization
612 18:59:26.208543 INFO : End of max read latency training
613 18:59:26.213909 INFO : Training has run successfully!
614 18:59:26.214145 1D training succeed
615 18:59:26.223077 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 18:59:26.270717 Check phy result
617 18:59:26.271020 INFO : End of initialization
618 18:59:26.293054 INFO : End of 2D read delay Voltage center optimization
619 18:59:26.312244 INFO : End of 2D read delay Voltage center optimization
620 18:59:26.364132 INFO : End of 2D write delay Voltage center optimization
621 18:59:26.413334 INFO : End of 2D write delay Voltage center optimization
622 18:59:26.418815 INFO : Training has run successfully!
623 18:59:26.419052
624 18:59:26.419257 channel==0
625 18:59:26.424431 RxClkDly_Margin_A0==88 ps 9
626 18:59:26.424678 TxDqDly_Margin_A0==98 ps 10
627 18:59:26.430015 RxClkDly_Margin_A1==88 ps 9
628 18:59:26.430248 TxDqDly_Margin_A1==88 ps 9
629 18:59:26.430451 TrainedVREFDQ_A0==74
630 18:59:26.435600 TrainedVREFDQ_A1==74
631 18:59:26.435842 VrefDac_Margin_A0==24
632 18:59:26.436088 DeviceVref_Margin_A0==40
633 18:59:26.441258 VrefDac_Margin_A1==23
634 18:59:26.441489 DeviceVref_Margin_A1==40
635 18:59:26.441689
636 18:59:26.441889
637 18:59:26.442086 channel==1
638 18:59:26.446809 RxClkDly_Margin_A0==88 ps 9
639 18:59:26.447053 TxDqDly_Margin_A0==88 ps 9
640 18:59:26.452400 RxClkDly_Margin_A1==78 ps 8
641 18:59:26.452630 TxDqDly_Margin_A1==78 ps 8
642 18:59:26.458027 TrainedVREFDQ_A0==75
643 18:59:26.458254 TrainedVREFDQ_A1==75
644 18:59:26.458455 VrefDac_Margin_A0==22
645 18:59:26.463614 DeviceVref_Margin_A0==39
646 18:59:26.463851 VrefDac_Margin_A1==22
647 18:59:26.464071 DeviceVref_Margin_A1==38
648 18:59:26.469252
649 18:59:26.469486 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 18:59:26.469686
651 18:59:26.502815 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000062
652 18:59:26.503110 2D training succeed
653 18:59:26.508434 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 18:59:26.514021 auto size-- 65535DDR cs0 size: 2048MB
655 18:59:26.514281 DDR cs1 size: 2048MB
656 18:59:26.519613 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 18:59:26.519860 cs0 DataBus test pass
658 18:59:26.525289 cs1 DataBus test pass
659 18:59:26.525540 cs0 AddrBus test pass
660 18:59:26.525746 cs1 AddrBus test pass
661 18:59:26.525947
662 18:59:26.530817 100bdlr_step_size ps== 471
663 18:59:26.531076 result report
664 18:59:26.536413 boot times 0Enable ddr reg access
665 18:59:26.541513 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 18:59:26.555361 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 18:59:27.211339 bl2z: ptr: 05129330, size: 00001e40
668 18:59:27.219266 0.0;M3 CHK:0;cm4_sp_mode 0
669 18:59:27.219526 MVN_1=0x00000000
670 18:59:27.219727 MVN_2=0x00000000
671 18:59:27.230690 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 18:59:27.230951 OPS=0x04
673 18:59:27.231159 ring efuse init
674 18:59:27.236356 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 18:59:27.236601 [0.017319 Inits done]
676 18:59:27.236804 secure task start!
677 18:59:27.243566 high task start!
678 18:59:27.243808 low task start!
679 18:59:27.244215 run into bl31
680 18:59:27.252166 NOTICE: BL31: v1.3(release):4fc40b1
681 18:59:27.259958 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 18:59:27.260220 NOTICE: BL31: G12A normal boot!
683 18:59:27.275502 NOTICE: BL31: BL33 decompress pass
684 18:59:27.281168 ERROR: Error initializing runtime service opteed_fast
685 18:59:28.076787
686 18:59:28.077180
687 18:59:28.082026 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 18:59:28.082266
689 18:59:28.085596 Model: Libre Computer AML-S905D3-CC Solitude
690 18:59:28.232562 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 18:59:28.247903 DRAM: 2 GiB (effective 3.8 GiB)
692 18:59:28.348914 Core: 406 devices, 33 uclasses, devicetree: separate
693 18:59:28.354834 WDT: Not starting watchdog@f0d0
694 18:59:28.379882 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 18:59:28.392199 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 18:59:28.397091 ** Bad device specification mmc 0 **
697 18:59:28.407130 Card did not respond to voltage select! : -110
698 18:59:28.414805 ** Bad device specification mmc 0 **
699 18:59:28.415244 Couldn't find partition mmc 0
700 18:59:28.423128 Card did not respond to voltage select! : -110
701 18:59:28.428687 ** Bad device specification mmc 0 **
702 18:59:28.429199 Couldn't find partition mmc 0
703 18:59:28.433731 Error: could not access storage.
704 18:59:28.730384 Net: eth0: ethernet@ff3f0000
705 18:59:28.730995 starting USB...
706 18:59:28.974853 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 18:59:28.975455 Starting the controller
708 18:59:28.981774 USB XHCI 1.10
709 18:59:30.538317 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 18:59:30.546632 scanning usb for storage devices... 0 Storage Device(s) found
712 18:59:30.598277 Hit any key to stop autoboot: 1
713 18:59:30.599152 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 18:59:30.599749 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 18:59:30.600263 Setting prompt string to ['=>']
716 18:59:30.600747 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 18:59:30.612546 0
718 18:59:30.613418 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 18:59:30.714557 => setenv autoload no
721 18:59:30.715185 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 18:59:30.719951 setenv autoload no
724 18:59:30.821421 => setenv initrd_high 0xffffffff
725 18:59:30.822119 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 18:59:30.826677 setenv initrd_high 0xffffffff
728 18:59:30.928063 => setenv fdt_high 0xffffffff
729 18:59:30.928687 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 18:59:30.933297 setenv fdt_high 0xffffffff
732 18:59:31.034714 => dhcp
733 18:59:31.035336 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 18:59:31.039799 dhcp
735 18:59:31.495227 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 18:59:31.495838 Speed: 1000, full duplex
737 18:59:31.496309 BOOTP broadcast 1
738 18:59:31.743727 BOOTP broadcast 2
739 18:59:32.247772 BOOTP broadcast 3
740 18:59:33.247611 BOOTP broadcast 4
741 18:59:34.607104 UDP wrong checksum 000000ff 0000ee5a
742 18:59:34.801936 UDP wrong checksum 000000ff 0000884d
743 18:59:35.246869 BOOTP broadcast 5
744 18:59:35.259527 DHCP client bound to address 192.168.6.12 (3763 ms)
746 18:59:35.361138 => setenv serverip 192.168.6.2
747 18:59:35.361843 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
748 18:59:35.366193 setenv serverip 192.168.6.2
750 18:59:35.467191 => tftpboot 0x01080000 823095/tftp-deploy-v8rygn0a/kernel/uImage
751 18:59:35.468239 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
752 18:59:35.474817 tftpboot 0x01080000 823095/tftp-deploy-v8rygn0a/kernel/uImage
753 18:59:35.475354 Speed: 1000, full duplex
754 18:59:35.475818 Using ethernet@ff3f0000 device
755 18:59:35.480277 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
756 18:59:35.485627 Filename '823095/tftp-deploy-v8rygn0a/kernel/uImage'.
757 18:59:35.489828 Load address: 0x1080000
758 18:59:39.030241 Loading: *################################################## 43.6 MiB
759 18:59:39.030677 12.3 MiB/s
760 18:59:39.030900 done
761 18:59:39.034674 Bytes transferred = 45713984 (2b98a40 hex)
763 18:59:39.135953 => tftpboot 0x08000000 823095/tftp-deploy-v8rygn0a/ramdisk/ramdisk.cpio.gz.uboot
764 18:59:39.136687 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
765 18:59:39.143404 tftpboot 0x08000000 823095/tftp-deploy-v8rygn0a/ramdisk/ramdisk.cpio.gz.uboot
766 18:59:39.143694 Speed: 1000, full duplex
767 18:59:39.143903 Using ethernet@ff3f0000 device
768 18:59:39.148981 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
769 18:59:39.158795 Filename '823095/tftp-deploy-v8rygn0a/ramdisk/ramdisk.cpio.gz.uboot'.
770 18:59:39.159265 Load address: 0x8000000
771 18:59:46.110422 Loading: *#####################################T ############ UDP wrong checksum 00000005 0000ab96
772 18:59:51.110808 T UDP wrong checksum 00000005 0000ab96
773 19:00:01.112661 T T UDP wrong checksum 00000005 0000ab96
774 19:00:21.115734 T T T T UDP wrong checksum 00000005 0000ab96
775 19:00:36.120511 T T
776 19:00:36.120934 Retry count exceeded; starting again
778 19:00:36.121813 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
781 19:00:36.122812 end: 2.4 uboot-commands (duration 00:01:24) [common]
783 19:00:36.123560 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
785 19:00:36.124141 end: 2 uboot-action (duration 00:01:25) [common]
787 19:00:36.125001 Cleaning after the job
788 19:00:36.125308 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/ramdisk
789 19:00:36.126115 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/kernel
790 19:00:36.153807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/dtb
791 19:00:36.154626 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823095/tftp-deploy-v8rygn0a/modules
792 19:00:36.176213 start: 4.1 power-off (timeout 00:00:30) [common]
793 19:00:36.176853 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
794 19:00:36.210280 >> OK - accepted request
795 19:00:36.212399 Returned 0 in 0 seconds
796 19:00:36.313155 end: 4.1 power-off (duration 00:00:00) [common]
798 19:00:36.314133 start: 4.2 read-feedback (timeout 00:10:00) [common]
799 19:00:36.314780 Listened to connection for namespace 'common' for up to 1s
800 19:00:37.315692 Finalising connection for namespace 'common'
801 19:00:37.316224 Disconnecting from shell: Finalise
802 19:00:37.316550 =>
803 19:00:37.417256 end: 4.2 read-feedback (duration 00:00:01) [common]
804 19:00:37.417757 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/823095
805 19:00:37.888391 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/823095
806 19:00:37.888999 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.