Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:03:16.103502 lava-dispatcher, installed at version: 2024.01
2 20:03:16.104342 start: 0 validate
3 20:03:16.104836 Start time: 2024-10-08 20:03:16.104805+00:00 (UTC)
4 20:03:16.105390 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:03:16.105926 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 20:03:16.145612 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:03:16.146157 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-5-gf7efea4fcf4b9%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:03:16.175364 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:03:16.175970 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-5-gf7efea4fcf4b9%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:03:16.208273 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:03:16.208788 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-5-gf7efea4fcf4b9%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 20:03:16.245327 validate duration: 0.14
14 20:03:16.246173 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:03:16.246520 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:03:16.246832 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:03:16.247520 Not decompressing ramdisk as can be used compressed.
18 20:03:16.247975 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 20:03:16.248264 saving as /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/ramdisk/rootfs.cpio.gz
20 20:03:16.248533 total size: 47897469 (45 MB)
21 20:03:16.279647 progress 0 % (0 MB)
22 20:03:16.309322 progress 5 % (2 MB)
23 20:03:16.338257 progress 10 % (4 MB)
24 20:03:16.367547 progress 15 % (6 MB)
25 20:03:16.396555 progress 20 % (9 MB)
26 20:03:16.425294 progress 25 % (11 MB)
27 20:03:16.454655 progress 30 % (13 MB)
28 20:03:16.483742 progress 35 % (16 MB)
29 20:03:16.512738 progress 40 % (18 MB)
30 20:03:16.541738 progress 45 % (20 MB)
31 20:03:16.571093 progress 50 % (22 MB)
32 20:03:16.600050 progress 55 % (25 MB)
33 20:03:16.629506 progress 60 % (27 MB)
34 20:03:16.658718 progress 65 % (29 MB)
35 20:03:16.687696 progress 70 % (32 MB)
36 20:03:16.716974 progress 75 % (34 MB)
37 20:03:16.746036 progress 80 % (36 MB)
38 20:03:16.774887 progress 85 % (38 MB)
39 20:03:16.803869 progress 90 % (41 MB)
40 20:03:16.832861 progress 95 % (43 MB)
41 20:03:16.861114 progress 100 % (45 MB)
42 20:03:16.861851 45 MB downloaded in 0.61 s (74.48 MB/s)
43 20:03:16.862422 end: 1.1.1 http-download (duration 00:00:01) [common]
45 20:03:16.863337 end: 1.1 download-retry (duration 00:00:01) [common]
46 20:03:16.863649 start: 1.2 download-retry (timeout 00:09:59) [common]
47 20:03:16.863932 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 20:03:16.864438 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-5-gf7efea4fcf4b9/arm64/defconfig/gcc-12/kernel/Image
49 20:03:16.864704 saving as /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/kernel/Image
50 20:03:16.864924 total size: 45713920 (43 MB)
51 20:03:16.865142 No compression specified
52 20:03:16.903052 progress 0 % (0 MB)
53 20:03:16.931036 progress 5 % (2 MB)
54 20:03:16.958932 progress 10 % (4 MB)
55 20:03:16.986744 progress 15 % (6 MB)
56 20:03:17.014657 progress 20 % (8 MB)
57 20:03:17.042016 progress 25 % (10 MB)
58 20:03:17.069869 progress 30 % (13 MB)
59 20:03:17.097671 progress 35 % (15 MB)
60 20:03:17.125649 progress 40 % (17 MB)
61 20:03:17.153099 progress 45 % (19 MB)
62 20:03:17.181005 progress 50 % (21 MB)
63 20:03:17.209299 progress 55 % (24 MB)
64 20:03:17.237326 progress 60 % (26 MB)
65 20:03:17.264917 progress 65 % (28 MB)
66 20:03:17.292457 progress 70 % (30 MB)
67 20:03:17.320499 progress 75 % (32 MB)
68 20:03:17.348295 progress 80 % (34 MB)
69 20:03:17.375781 progress 85 % (37 MB)
70 20:03:17.404139 progress 90 % (39 MB)
71 20:03:17.432008 progress 95 % (41 MB)
72 20:03:17.458923 progress 100 % (43 MB)
73 20:03:17.459445 43 MB downloaded in 0.59 s (73.33 MB/s)
74 20:03:17.459945 end: 1.2.1 http-download (duration 00:00:01) [common]
76 20:03:17.460818 end: 1.2 download-retry (duration 00:00:01) [common]
77 20:03:17.461120 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:03:17.461404 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:03:17.461901 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-5-gf7efea4fcf4b9/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 20:03:17.462204 saving as /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/dtb/meson-g12b-a311d-libretech-cc.dtb
81 20:03:17.462430 total size: 54703 (0 MB)
82 20:03:17.462652 No compression specified
83 20:03:17.501199 progress 59 % (0 MB)
84 20:03:17.502085 progress 100 % (0 MB)
85 20:03:17.502643 0 MB downloaded in 0.04 s (1.30 MB/s)
86 20:03:17.503172 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:03:17.504110 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:03:17.504434 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:03:17.504727 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:03:17.505198 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-5-gf7efea4fcf4b9/arm64/defconfig/gcc-12/modules.tar.xz
92 20:03:17.505477 saving as /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/modules/modules.tar
93 20:03:17.505685 total size: 11593096 (11 MB)
94 20:03:17.505898 Using unxz to decompress xz
95 20:03:17.540435 progress 0 % (0 MB)
96 20:03:17.610023 progress 5 % (0 MB)
97 20:03:17.686213 progress 10 % (1 MB)
98 20:03:17.768689 progress 15 % (1 MB)
99 20:03:17.844963 progress 20 % (2 MB)
100 20:03:17.921242 progress 25 % (2 MB)
101 20:03:18.000560 progress 30 % (3 MB)
102 20:03:18.073170 progress 35 % (3 MB)
103 20:03:18.152727 progress 40 % (4 MB)
104 20:03:18.237442 progress 45 % (5 MB)
105 20:03:18.313562 progress 50 % (5 MB)
106 20:03:18.396250 progress 55 % (6 MB)
107 20:03:18.477528 progress 60 % (6 MB)
108 20:03:18.556511 progress 65 % (7 MB)
109 20:03:18.642512 progress 70 % (7 MB)
110 20:03:18.739039 progress 75 % (8 MB)
111 20:03:18.837502 progress 80 % (8 MB)
112 20:03:18.928004 progress 85 % (9 MB)
113 20:03:19.014566 progress 90 % (9 MB)
114 20:03:19.131698 progress 95 % (10 MB)
115 20:03:19.241142 progress 100 % (11 MB)
116 20:03:19.258604 11 MB downloaded in 1.75 s (6.31 MB/s)
117 20:03:19.259188 end: 1.4.1 http-download (duration 00:00:02) [common]
119 20:03:19.260053 end: 1.4 download-retry (duration 00:00:02) [common]
120 20:03:19.260596 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 20:03:19.261113 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 20:03:19.261603 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:03:19.262098 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 20:03:19.263079 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np
125 20:03:19.264024 makedir: /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin
126 20:03:19.264719 makedir: /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/tests
127 20:03:19.265340 makedir: /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/results
128 20:03:19.265951 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-add-keys
129 20:03:19.266879 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-add-sources
130 20:03:19.267802 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-background-process-start
131 20:03:19.268784 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-background-process-stop
132 20:03:19.269756 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-common-functions
133 20:03:19.270658 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-echo-ipv4
134 20:03:19.271549 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-install-packages
135 20:03:19.272464 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-installed-packages
136 20:03:19.273381 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-os-build
137 20:03:19.274266 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-probe-channel
138 20:03:19.275180 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-probe-ip
139 20:03:19.276097 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-target-ip
140 20:03:19.277042 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-target-mac
141 20:03:19.277967 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-target-storage
142 20:03:19.278871 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-test-case
143 20:03:19.279757 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-test-event
144 20:03:19.280676 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-test-feedback
145 20:03:19.281551 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-test-raise
146 20:03:19.282421 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-test-reference
147 20:03:19.283289 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-test-runner
148 20:03:19.284242 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-test-set
149 20:03:19.285157 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-test-shell
150 20:03:19.286085 Updating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-install-packages (oe)
151 20:03:19.287032 Updating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/bin/lava-installed-packages (oe)
152 20:03:19.287839 Creating /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/environment
153 20:03:19.288590 LAVA metadata
154 20:03:19.289081 - LAVA_JOB_ID=823126
155 20:03:19.289507 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:03:19.290155 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 20:03:19.291927 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:03:19.292559 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 20:03:19.292975 skipped lava-vland-overlay
160 20:03:19.293461 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:03:19.293967 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 20:03:19.294389 skipped lava-multinode-overlay
163 20:03:19.294866 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:03:19.295361 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 20:03:19.295836 Loading test definitions
166 20:03:19.296406 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 20:03:19.296848 Using /lava-823126 at stage 0
168 20:03:19.298944 uuid=823126_1.5.2.4.1 testdef=None
169 20:03:19.299519 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:03:19.300060 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 20:03:19.303290 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:03:19.304507 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 20:03:19.306845 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:03:19.307712 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 20:03:19.309837 runner path: /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/0/tests/0_igt-gpu-panfrost test_uuid 823126_1.5.2.4.1
178 20:03:19.310433 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:03:19.311248 Creating lava-test-runner.conf files
181 20:03:19.311457 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/823126/lava-overlay-ej1_x_np/lava-823126/0 for stage 0
182 20:03:19.311796 - 0_igt-gpu-panfrost
183 20:03:19.312168 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:03:19.312455 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 20:03:19.335820 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:03:19.336234 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 20:03:19.336501 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:03:19.336766 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:03:19.337033 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 20:03:26.361852 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 20:03:26.362312 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 20:03:26.362559 extracting modules file /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823126/extract-overlay-ramdisk-4q3ybicf/ramdisk
193 20:03:27.864979 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 20:03:27.865459 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 20:03:27.865737 [common] Applying overlay /var/lib/lava/dispatcher/tmp/823126/compress-overlay-oiw__q60/overlay-1.5.2.5.tar.gz to ramdisk
196 20:03:27.865952 [common] Applying overlay /var/lib/lava/dispatcher/tmp/823126/compress-overlay-oiw__q60/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/823126/extract-overlay-ramdisk-4q3ybicf/ramdisk
197 20:03:27.896364 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:03:27.896780 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 20:03:27.897055 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 20:03:27.897285 Converting downloaded kernel to a uImage
201 20:03:27.897589 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/kernel/Image /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/kernel/uImage
202 20:03:28.346528 output: Image Name:
203 20:03:28.346938 output: Created: Tue Oct 8 20:03:27 2024
204 20:03:28.347150 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:03:28.347358 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 20:03:28.347563 output: Load Address: 01080000
207 20:03:28.347765 output: Entry Point: 01080000
208 20:03:28.347966 output:
209 20:03:28.348338 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 20:03:28.348604 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 20:03:28.348875 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 20:03:28.349134 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:03:28.349390 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 20:03:28.349644 Building ramdisk /var/lib/lava/dispatcher/tmp/823126/extract-overlay-ramdisk-4q3ybicf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/823126/extract-overlay-ramdisk-4q3ybicf/ramdisk
215 20:03:35.333198 >> 502360 blocks
216 20:03:56.090081 Adding RAMdisk u-boot header.
217 20:03:56.090517 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/823126/extract-overlay-ramdisk-4q3ybicf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/823126/extract-overlay-ramdisk-4q3ybicf/ramdisk.cpio.gz.uboot
218 20:03:56.767813 output: Image Name:
219 20:03:56.768490 output: Created: Tue Oct 8 20:03:56 2024
220 20:03:56.768988 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:03:56.769441 output: Data Size: 65711815 Bytes = 64171.69 KiB = 62.67 MiB
222 20:03:56.769882 output: Load Address: 00000000
223 20:03:56.770327 output: Entry Point: 00000000
224 20:03:56.770763 output:
225 20:03:56.771923 rename /var/lib/lava/dispatcher/tmp/823126/extract-overlay-ramdisk-4q3ybicf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/ramdisk/ramdisk.cpio.gz.uboot
226 20:03:56.772739 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 20:03:56.773380 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 20:03:56.774041 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 20:03:56.774565 No LXC device requested
230 20:03:56.775119 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:03:56.775676 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 20:03:56.776255 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:03:56.776722 Checking files for TFTP limit of 4294967296 bytes.
234 20:03:56.779681 end: 1 tftp-deploy (duration 00:00:41) [common]
235 20:03:56.780383 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:03:56.781022 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:03:56.781622 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:03:56.782273 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:03:56.782906 Using kernel file from prepare-kernel: 823126/tftp-deploy-3_9h8a0j/kernel/uImage
240 20:03:56.783594 substitutions:
241 20:03:56.784072 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:03:56.784518 - {DTB_ADDR}: 0x01070000
243 20:03:56.784957 - {DTB}: 823126/tftp-deploy-3_9h8a0j/dtb/meson-g12b-a311d-libretech-cc.dtb
244 20:03:56.785401 - {INITRD}: 823126/tftp-deploy-3_9h8a0j/ramdisk/ramdisk.cpio.gz.uboot
245 20:03:56.785838 - {KERNEL_ADDR}: 0x01080000
246 20:03:56.786271 - {KERNEL}: 823126/tftp-deploy-3_9h8a0j/kernel/uImage
247 20:03:56.786705 - {LAVA_MAC}: None
248 20:03:56.787181 - {PRESEED_CONFIG}: None
249 20:03:56.787618 - {PRESEED_LOCAL}: None
250 20:03:56.788073 - {RAMDISK_ADDR}: 0x08000000
251 20:03:56.788508 - {RAMDISK}: 823126/tftp-deploy-3_9h8a0j/ramdisk/ramdisk.cpio.gz.uboot
252 20:03:56.788946 - {ROOT_PART}: None
253 20:03:56.789376 - {ROOT}: None
254 20:03:56.789807 - {SERVER_IP}: 192.168.6.2
255 20:03:56.790240 - {TEE_ADDR}: 0x83000000
256 20:03:56.790670 - {TEE}: None
257 20:03:56.791101 Parsed boot commands:
258 20:03:56.791520 - setenv autoload no
259 20:03:56.791947 - setenv initrd_high 0xffffffff
260 20:03:56.792402 - setenv fdt_high 0xffffffff
261 20:03:56.792832 - dhcp
262 20:03:56.793263 - setenv serverip 192.168.6.2
263 20:03:56.793689 - tftpboot 0x01080000 823126/tftp-deploy-3_9h8a0j/kernel/uImage
264 20:03:56.794120 - tftpboot 0x08000000 823126/tftp-deploy-3_9h8a0j/ramdisk/ramdisk.cpio.gz.uboot
265 20:03:56.794551 - tftpboot 0x01070000 823126/tftp-deploy-3_9h8a0j/dtb/meson-g12b-a311d-libretech-cc.dtb
266 20:03:56.794981 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:03:56.795415 - bootm 0x01080000 0x08000000 0x01070000
268 20:03:56.796002 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:03:56.797657 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:03:56.798144 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 20:03:56.813391 Setting prompt string to ['lava-test: # ']
273 20:03:56.814894 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:03:56.815485 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:03:56.816070 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:03:56.816667 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:03:56.818110 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 20:03:56.856371 >> OK - accepted request
279 20:03:56.858906 Returned 0 in 0 seconds
280 20:03:56.960029 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:03:56.961306 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:03:56.961978 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:03:56.962547 Setting prompt string to ['Hit any key to stop autoboot']
285 20:03:56.963055 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:03:56.964803 Trying 192.168.56.21...
287 20:03:56.965340 Connected to conserv1.
288 20:03:56.965806 Escape character is '^]'.
289 20:03:56.966266
290 20:03:56.966739 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:03:56.967215
292 20:04:07.770447 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 20:04:07.771142 bl2_stage_init 0x01
294 20:04:07.771623 bl2_stage_init 0x81
295 20:04:07.776110 hw id: 0x0000 - pwm id 0x01
296 20:04:07.776649 bl2_stage_init 0xc1
297 20:04:07.777107 bl2_stage_init 0x02
298 20:04:07.777558
299 20:04:07.781633 L0:00000000
300 20:04:07.782130 L1:20000703
301 20:04:07.782567 L2:00008067
302 20:04:07.782997 L3:14000000
303 20:04:07.787238 B2:00402000
304 20:04:07.787734 B1:e0f83180
305 20:04:07.788205
306 20:04:07.788642 TE: 58124
307 20:04:07.789077
308 20:04:07.792768 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 20:04:07.793259
310 20:04:07.793696 Board ID = 1
311 20:04:07.798493 Set A53 clk to 24M
312 20:04:07.798977 Set A73 clk to 24M
313 20:04:07.799413 Set clk81 to 24M
314 20:04:07.804069 A53 clk: 1200 MHz
315 20:04:07.804557 A73 clk: 1200 MHz
316 20:04:07.804995 CLK81: 166.6M
317 20:04:07.805422 smccc: 00012a92
318 20:04:07.809954 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 20:04:07.815344 board id: 1
320 20:04:07.820811 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:04:07.831844 fw parse done
322 20:04:07.836924 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:04:07.879559 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:04:07.891233 PIEI prepare done
325 20:04:07.891721 fastboot data load
326 20:04:07.892223 fastboot data verify
327 20:04:07.896905 verify result: 266
328 20:04:07.902495 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 20:04:07.902977 LPDDR4 probe
330 20:04:07.903429 ddr clk to 1584MHz
331 20:04:07.910194 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:04:07.946800
333 20:04:07.947296 dmc_version 0001
334 20:04:07.953450 Check phy result
335 20:04:07.960286 INFO : End of CA training
336 20:04:07.960779 INFO : End of initialization
337 20:04:07.965911 INFO : Training has run successfully!
338 20:04:07.966405 Check phy result
339 20:04:07.971702 INFO : End of initialization
340 20:04:07.972221 INFO : End of read enable training
341 20:04:07.977070 INFO : End of fine write leveling
342 20:04:07.982811 INFO : End of Write leveling coarse delay
343 20:04:07.983296 INFO : Training has run successfully!
344 20:04:07.983736 Check phy result
345 20:04:07.988648 INFO : End of initialization
346 20:04:07.989143 INFO : End of read dq deskew training
347 20:04:07.993842 INFO : End of MPR read delay center optimization
348 20:04:07.999678 INFO : End of write delay center optimization
349 20:04:08.005040 INFO : End of read delay center optimization
350 20:04:08.005527 INFO : End of max read latency training
351 20:04:08.011822 INFO : Training has run successfully!
352 20:04:08.012337 1D training succeed
353 20:04:08.019230 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:04:08.067282 Check phy result
355 20:04:08.067777 INFO : End of initialization
356 20:04:08.089220 INFO : End of 2D read delay Voltage center optimization
357 20:04:08.109148 INFO : End of 2D read delay Voltage center optimization
358 20:04:08.161052 INFO : End of 2D write delay Voltage center optimization
359 20:04:08.211173 INFO : End of 2D write delay Voltage center optimization
360 20:04:08.216669 INFO : Training has run successfully!
361 20:04:08.217166
362 20:04:08.217609 channel==0
363 20:04:08.222384 RxClkDly_Margin_A0==88 ps 9
364 20:04:08.222886 TxDqDly_Margin_A0==98 ps 10
365 20:04:08.225718 RxClkDly_Margin_A1==88 ps 9
366 20:04:08.226195 TxDqDly_Margin_A1==98 ps 10
367 20:04:08.231429 TrainedVREFDQ_A0==74
368 20:04:08.231913 TrainedVREFDQ_A1==74
369 20:04:08.232398 VrefDac_Margin_A0==25
370 20:04:08.236893 DeviceVref_Margin_A0==40
371 20:04:08.237371 VrefDac_Margin_A1==24
372 20:04:08.242565 DeviceVref_Margin_A1==40
373 20:04:08.243045
374 20:04:08.243491
375 20:04:08.243927 channel==1
376 20:04:08.244397 RxClkDly_Margin_A0==88 ps 9
377 20:04:08.248092 TxDqDly_Margin_A0==88 ps 9
378 20:04:08.248583 RxClkDly_Margin_A1==88 ps 9
379 20:04:08.253694 TxDqDly_Margin_A1==88 ps 9
380 20:04:08.254178 TrainedVREFDQ_A0==77
381 20:04:08.254621 TrainedVREFDQ_A1==77
382 20:04:08.259354 VrefDac_Margin_A0==22
383 20:04:08.259830 DeviceVref_Margin_A0==37
384 20:04:08.260296 VrefDac_Margin_A1==24
385 20:04:08.264893 DeviceVref_Margin_A1==37
386 20:04:08.265371
387 20:04:08.270491 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:04:08.270970
389 20:04:08.298416 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 20:04:08.303943 2D training succeed
391 20:04:08.309585 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:04:08.310067 auto size-- 65535DDR cs0 size: 2048MB
393 20:04:08.315138 DDR cs1 size: 2048MB
394 20:04:08.315616 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:04:08.320767 cs0 DataBus test pass
396 20:04:08.321249 cs1 DataBus test pass
397 20:04:08.321685 cs0 AddrBus test pass
398 20:04:08.326439 cs1 AddrBus test pass
399 20:04:08.326923
400 20:04:08.327364 100bdlr_step_size ps== 420
401 20:04:08.327810 result report
402 20:04:08.331936 boot times 0Enable ddr reg access
403 20:04:08.338444 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:04:08.352193 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 20:04:08.924764 0.0;M3 CHK:0;cm4_sp_mode 0
406 20:04:08.925368 MVN_1=0x00000000
407 20:04:08.930338 MVN_2=0x00000000
408 20:04:08.936091 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 20:04:08.936592 OPS=0x10
410 20:04:08.937057 ring efuse init
411 20:04:08.937508 chipver efuse init
412 20:04:08.941674 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 20:04:08.947289 [0.018960 Inits done]
414 20:04:08.947792 secure task start!
415 20:04:08.948294 high task start!
416 20:04:08.950928 low task start!
417 20:04:08.951425 run into bl31
418 20:04:08.958642 NOTICE: BL31: v1.3(release):4fc40b1
419 20:04:08.965391 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 20:04:08.965897 NOTICE: BL31: G12A normal boot!
421 20:04:08.991715 NOTICE: BL31: BL33 decompress pass
422 20:04:08.996499 ERROR: Error initializing runtime service opteed_fast
423 20:04:10.230282
424 20:04:10.230928
425 20:04:10.238556 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 20:04:10.239094
427 20:04:10.239552 Model: Libre Computer AML-A311D-CC Alta
428 20:04:10.446503 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 20:04:10.469559 DRAM: 2 GiB (effective 3.8 GiB)
430 20:04:10.613478 Core: 408 devices, 31 uclasses, devicetree: separate
431 20:04:10.618430 WDT: Not starting watchdog@f0d0
432 20:04:10.651528 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 20:04:10.664121 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 20:04:10.668997 ** Bad device specification mmc 0 **
435 20:04:10.679325 Card did not respond to voltage select! : -110
436 20:04:10.686074 ** Bad device specification mmc 0 **
437 20:04:10.686343 Couldn't find partition mmc 0
438 20:04:10.695387 Card did not respond to voltage select! : -110
439 20:04:10.700899 ** Bad device specification mmc 0 **
440 20:04:10.701855 Couldn't find partition mmc 0
441 20:04:10.704970 Error: could not access storage.
442 20:04:11.970947 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 20:04:11.971591 bl2_stage_init 0x01
444 20:04:11.972114 bl2_stage_init 0x81
445 20:04:11.976512 hw id: 0x0000 - pwm id 0x01
446 20:04:11.977022 bl2_stage_init 0xc1
447 20:04:11.977480 bl2_stage_init 0x02
448 20:04:11.977928
449 20:04:11.982101 L0:00000000
450 20:04:11.982602 L1:20000703
451 20:04:11.983057 L2:00008067
452 20:04:11.983498 L3:14000000
453 20:04:11.987727 B2:00402000
454 20:04:11.988256 B1:e0f83180
455 20:04:11.988707
456 20:04:11.989154 TE: 58159
457 20:04:11.989599
458 20:04:11.993291 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 20:04:11.993795
460 20:04:11.994251 Board ID = 1
461 20:04:11.998938 Set A53 clk to 24M
462 20:04:11.999441 Set A73 clk to 24M
463 20:04:11.999894 Set clk81 to 24M
464 20:04:12.004477 A53 clk: 1200 MHz
465 20:04:12.004974 A73 clk: 1200 MHz
466 20:04:12.005430 CLK81: 166.6M
467 20:04:12.005874 smccc: 00012ab5
468 20:04:12.010101 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 20:04:12.015675 board id: 1
470 20:04:12.021422 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 20:04:12.032218 fw parse done
472 20:04:12.037242 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 20:04:12.079836 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 20:04:12.091720 PIEI prepare done
475 20:04:12.092281 fastboot data load
476 20:04:12.092741 fastboot data verify
477 20:04:12.097421 verify result: 266
478 20:04:12.103001 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 20:04:12.103501 LPDDR4 probe
480 20:04:12.103948 ddr clk to 1584MHz
481 20:04:12.110853 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 20:04:12.147353
483 20:04:12.147641 dmc_version 0001
484 20:04:12.154160 Check phy result
485 20:04:12.160846 INFO : End of CA training
486 20:04:12.161362 INFO : End of initialization
487 20:04:12.166441 INFO : Training has run successfully!
488 20:04:12.166950 Check phy result
489 20:04:12.172102 INFO : End of initialization
490 20:04:12.172607 INFO : End of read enable training
491 20:04:12.177639 INFO : End of fine write leveling
492 20:04:12.183262 INFO : End of Write leveling coarse delay
493 20:04:12.183773 INFO : Training has run successfully!
494 20:04:12.184279 Check phy result
495 20:04:12.188854 INFO : End of initialization
496 20:04:12.189375 INFO : End of read dq deskew training
497 20:04:12.194435 INFO : End of MPR read delay center optimization
498 20:04:12.200090 INFO : End of write delay center optimization
499 20:04:12.205629 INFO : End of read delay center optimization
500 20:04:12.206141 INFO : End of max read latency training
501 20:04:12.211222 INFO : Training has run successfully!
502 20:04:12.211728 1D training succeed
503 20:04:12.219435 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 20:04:12.267071 Check phy result
505 20:04:12.267617 INFO : End of initialization
506 20:04:12.289683 INFO : End of 2D read delay Voltage center optimization
507 20:04:12.309276 INFO : End of 2D read delay Voltage center optimization
508 20:04:12.361562 INFO : End of 2D write delay Voltage center optimization
509 20:04:12.410916 INFO : End of 2D write delay Voltage center optimization
510 20:04:12.416446 INFO : Training has run successfully!
511 20:04:12.416971
512 20:04:12.417428 channel==0
513 20:04:12.422034 RxClkDly_Margin_A0==88 ps 9
514 20:04:12.422546 TxDqDly_Margin_A0==98 ps 10
515 20:04:12.425335 RxClkDly_Margin_A1==88 ps 9
516 20:04:12.425837 TxDqDly_Margin_A1==98 ps 10
517 20:04:12.430847 TrainedVREFDQ_A0==74
518 20:04:12.431359 TrainedVREFDQ_A1==74
519 20:04:12.436467 VrefDac_Margin_A0==25
520 20:04:12.436987 DeviceVref_Margin_A0==40
521 20:04:12.437441 VrefDac_Margin_A1==25
522 20:04:12.442112 DeviceVref_Margin_A1==40
523 20:04:12.442620
524 20:04:12.443071
525 20:04:12.443513 channel==1
526 20:04:12.443950 RxClkDly_Margin_A0==98 ps 10
527 20:04:12.447672 TxDqDly_Margin_A0==88 ps 9
528 20:04:12.448217 RxClkDly_Margin_A1==98 ps 10
529 20:04:12.453263 TxDqDly_Margin_A1==88 ps 9
530 20:04:12.453774 TrainedVREFDQ_A0==77
531 20:04:12.454229 TrainedVREFDQ_A1==77
532 20:04:12.458875 VrefDac_Margin_A0==22
533 20:04:12.459373 DeviceVref_Margin_A0==37
534 20:04:12.464435 VrefDac_Margin_A1==22
535 20:04:12.464932 DeviceVref_Margin_A1==37
536 20:04:12.465382
537 20:04:12.470133 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 20:04:12.470635
539 20:04:12.498023 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 20:04:12.503664 2D training succeed
541 20:04:12.509241 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 20:04:12.509755 auto size-- 65535DDR cs0 size: 2048MB
543 20:04:12.514868 DDR cs1 size: 2048MB
544 20:04:12.515377 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 20:04:12.520476 cs0 DataBus test pass
546 20:04:12.520983 cs1 DataBus test pass
547 20:04:12.521433 cs0 AddrBus test pass
548 20:04:12.526132 cs1 AddrBus test pass
549 20:04:12.526644
550 20:04:12.527100 100bdlr_step_size ps== 420
551 20:04:12.527560 result report
552 20:04:12.531647 boot times 0Enable ddr reg access
553 20:04:12.538768 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 20:04:12.551893 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 20:04:13.124822 0.0;M3 CHK:0;cm4_sp_mode 0
556 20:04:13.125442 MVN_1=0x00000000
557 20:04:13.130379 MVN_2=0x00000000
558 20:04:13.136180 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 20:04:13.136707 OPS=0x10
560 20:04:13.137181 ring efuse init
561 20:04:13.137644 chipver efuse init
562 20:04:13.144233 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 20:04:13.144788 [0.018960 Inits done]
564 20:04:13.151302 secure task start!
565 20:04:13.151808 high task start!
566 20:04:13.152306 low task start!
567 20:04:13.152746 run into bl31
568 20:04:13.158473 NOTICE: BL31: v1.3(release):4fc40b1
569 20:04:13.165485 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 20:04:13.165987 NOTICE: BL31: G12A normal boot!
571 20:04:13.191616 NOTICE: BL31: BL33 decompress pass
572 20:04:13.196374 ERROR: Error initializing runtime service opteed_fast
573 20:04:14.430477
574 20:04:14.431086
575 20:04:14.438862 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 20:04:14.439395
577 20:04:14.439860 Model: Libre Computer AML-A311D-CC Alta
578 20:04:14.646985 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 20:04:14.669808 DRAM: 2 GiB (effective 3.8 GiB)
580 20:04:14.813649 Core: 408 devices, 31 uclasses, devicetree: separate
581 20:04:14.818558 WDT: Not starting watchdog@f0d0
582 20:04:14.851697 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 20:04:14.864086 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 20:04:14.868347 ** Bad device specification mmc 0 **
585 20:04:14.879541 Card did not respond to voltage select! : -110
586 20:04:14.886263 ** Bad device specification mmc 0 **
587 20:04:14.886809 Couldn't find partition mmc 0
588 20:04:14.895480 Card did not respond to voltage select! : -110
589 20:04:14.900939 ** Bad device specification mmc 0 **
590 20:04:14.901490 Couldn't find partition mmc 0
591 20:04:14.905348 Error: could not access storage.
592 20:04:15.247862 Net: eth0: ethernet@ff3f0000
593 20:04:15.248568 starting USB...
594 20:04:15.500462 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 20:04:15.501147 Starting the controller
596 20:04:15.506779 USB XHCI 1.10
597 20:04:17.221381 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
598 20:04:17.222077 bl2_stage_init 0x81
599 20:04:17.227058 hw id: 0x0000 - pwm id 0x01
600 20:04:17.227583 bl2_stage_init 0xc1
601 20:04:17.228133 bl2_stage_init 0x02
602 20:04:17.228602
603 20:04:17.232577 L0:00000000
604 20:04:17.233096 L1:20000703
605 20:04:17.233556 L2:00008067
606 20:04:17.234006 L3:14000000
607 20:04:17.234450 B2:00402000
608 20:04:17.238125 B1:e0f83180
609 20:04:17.238639
610 20:04:17.239094 TE: 58150
611 20:04:17.239541
612 20:04:17.243747 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 20:04:17.244319
614 20:04:17.244796 Board ID = 1
615 20:04:17.249360 Set A53 clk to 24M
616 20:04:17.249874 Set A73 clk to 24M
617 20:04:17.250331 Set clk81 to 24M
618 20:04:17.255118 A53 clk: 1200 MHz
619 20:04:17.255626 A73 clk: 1200 MHz
620 20:04:17.256116 CLK81: 166.6M
621 20:04:17.256566 smccc: 00012aac
622 20:04:17.260380 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 20:04:17.265973 board id: 1
624 20:04:17.271493 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 20:04:17.282447 fw parse done
626 20:04:17.287463 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 20:04:17.330429 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 20:04:17.341944 PIEI prepare done
629 20:04:17.342461 fastboot data load
630 20:04:17.342920 fastboot data verify
631 20:04:17.347620 verify result: 266
632 20:04:17.353219 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 20:04:17.353728 LPDDR4 probe
634 20:04:17.354182 ddr clk to 1584MHz
635 20:04:17.360866 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 20:04:17.397569
637 20:04:17.398121 dmc_version 0001
638 20:04:17.405305 Check phy result
639 20:04:17.410988 INFO : End of CA training
640 20:04:17.411500 INFO : End of initialization
641 20:04:17.416606 INFO : Training has run successfully!
642 20:04:17.417111 Check phy result
643 20:04:17.422236 INFO : End of initialization
644 20:04:17.422740 INFO : End of read enable training
645 20:04:17.425594 INFO : End of fine write leveling
646 20:04:17.431043 INFO : End of Write leveling coarse delay
647 20:04:17.436651 INFO : Training has run successfully!
648 20:04:17.437159 Check phy result
649 20:04:17.437617 INFO : End of initialization
650 20:04:17.442268 INFO : End of read dq deskew training
651 20:04:17.447850 INFO : End of MPR read delay center optimization
652 20:04:17.448403 INFO : End of write delay center optimization
653 20:04:17.453475 INFO : End of read delay center optimization
654 20:04:17.458998 INFO : End of max read latency training
655 20:04:17.459506 INFO : Training has run successfully!
656 20:04:17.464654 1D training succeed
657 20:04:17.469857 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 20:04:17.518032 Check phy result
659 20:04:17.518698 INFO : End of initialization
660 20:04:17.539799 INFO : End of 2D read delay Voltage center optimization
661 20:04:17.559127 INFO : End of 2D read delay Voltage center optimization
662 20:04:17.611596 INFO : End of 2D write delay Voltage center optimization
663 20:04:17.661478 INFO : End of 2D write delay Voltage center optimization
664 20:04:17.667028 INFO : Training has run successfully!
665 20:04:17.667564
666 20:04:17.668071 channel==0
667 20:04:17.672649 RxClkDly_Margin_A0==88 ps 9
668 20:04:17.673174 TxDqDly_Margin_A0==98 ps 10
669 20:04:17.675974 RxClkDly_Margin_A1==88 ps 9
670 20:04:17.676512 TxDqDly_Margin_A1==98 ps 10
671 20:04:17.681560 TrainedVREFDQ_A0==74
672 20:04:17.682085 TrainedVREFDQ_A1==74
673 20:04:17.682544 VrefDac_Margin_A0==25
674 20:04:17.687182 DeviceVref_Margin_A0==40
675 20:04:17.687709 VrefDac_Margin_A1==25
676 20:04:17.692752 DeviceVref_Margin_A1==40
677 20:04:17.693271
678 20:04:17.693732
679 20:04:17.694180 channel==1
680 20:04:17.694660 RxClkDly_Margin_A0==98 ps 10
681 20:04:17.698389 TxDqDly_Margin_A0==98 ps 10
682 20:04:17.699113 RxClkDly_Margin_A1==98 ps 10
683 20:04:17.704123 TxDqDly_Margin_A1==88 ps 9
684 20:04:17.704699 TrainedVREFDQ_A0==77
685 20:04:17.705178 TrainedVREFDQ_A1==77
686 20:04:17.709568 VrefDac_Margin_A0==22
687 20:04:17.710091 DeviceVref_Margin_A0==37
688 20:04:17.715147 VrefDac_Margin_A1==22
689 20:04:17.715672 DeviceVref_Margin_A1==37
690 20:04:17.716174
691 20:04:17.720743 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 20:04:17.721271
693 20:04:17.748773 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
694 20:04:17.754338 2D training succeed
695 20:04:17.759955 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 20:04:17.760529 auto size-- 65535DDR cs0 size: 2048MB
697 20:04:17.765576 DDR cs1 size: 2048MB
698 20:04:17.766105 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 20:04:17.771131 cs0 DataBus test pass
700 20:04:17.771654 cs1 DataBus test pass
701 20:04:17.772163 cs0 AddrBus test pass
702 20:04:17.776808 cs1 AddrBus test pass
703 20:04:17.777335
704 20:04:17.777802 100bdlr_step_size ps== 420
705 20:04:17.778264 result report
706 20:04:17.782382 boot times 0Enable ddr reg access
707 20:04:17.789850 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 20:04:17.803175 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 20:04:18.377318 0.0;M3 CHK:0;cm4_sp_mode 0
710 20:04:18.378001 MVN_1=0x00000000
711 20:04:18.382829 MVN_2=0x00000000
712 20:04:18.388551 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 20:04:18.389126 OPS=0x10
714 20:04:18.389635 ring efuse init
715 20:04:18.390093 chipver efuse init
716 20:04:18.394163 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 20:04:18.399702 [0.018961 Inits done]
718 20:04:18.400251 secure task start!
719 20:04:18.400694 high task start!
720 20:04:18.403490 low task start!
721 20:04:18.404014 run into bl31
722 20:04:18.411038 NOTICE: BL31: v1.3(release):4fc40b1
723 20:04:18.418794 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 20:04:18.419308 NOTICE: BL31: G12A normal boot!
725 20:04:18.444199 NOTICE: BL31: BL33 decompress pass
726 20:04:18.448965 ERROR: Error initializing runtime service opteed_fast
727 20:04:19.682773
728 20:04:19.683445
729 20:04:19.690143 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 20:04:19.690667
731 20:04:19.691130 Model: Libre Computer AML-A311D-CC Alta
732 20:04:19.898987 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 20:04:19.922418 DRAM: 2 GiB (effective 3.8 GiB)
734 20:04:20.065850 Core: 408 devices, 31 uclasses, devicetree: separate
735 20:04:20.070821 WDT: Not starting watchdog@f0d0
736 20:04:20.103945 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 20:04:20.116381 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 20:04:20.121495 ** Bad device specification mmc 0 **
739 20:04:20.131735 Card did not respond to voltage select! : -110
740 20:04:20.138536 ** Bad device specification mmc 0 **
741 20:04:20.139048 Couldn't find partition mmc 0
742 20:04:20.147732 Card did not respond to voltage select! : -110
743 20:04:20.153300 ** Bad device specification mmc 0 **
744 20:04:20.153813 Couldn't find partition mmc 0
745 20:04:20.157504 Error: could not access storage.
746 20:04:20.500829 Net: eth0: ethernet@ff3f0000
747 20:04:20.501439 starting USB...
748 20:04:20.753546 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 20:04:20.753888 Starting the controller
750 20:04:20.760402 USB XHCI 1.10
751 20:04:22.943550 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 20:04:22.944289 bl2_stage_init 0x01
753 20:04:22.944768 bl2_stage_init 0x81
754 20:04:22.945223 hw id: 0x0000 - pwm id 0x01
755 20:04:22.945902 bl2_stage_init 0xc1
756 20:04:22.946389 bl2_stage_init 0x02
757 20:04:22.946836
758 20:04:22.947283 L0:00000000
759 20:04:22.947725 L1:20000703
760 20:04:22.948203 L2:00008067
761 20:04:22.948645 L3:14000000
762 20:04:22.949076 B2:00402000
763 20:04:22.949509 B1:e0f83180
764 20:04:22.949943
765 20:04:22.950376 TE: 58124
766 20:04:22.950811
767 20:04:22.951864 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 20:04:22.952405
769 20:04:22.952861 Board ID = 1
770 20:04:22.953304 Set A53 clk to 24M
771 20:04:22.953743 Set A73 clk to 24M
772 20:04:22.954178 Set clk81 to 24M
773 20:04:22.954612 A53 clk: 1200 MHz
774 20:04:22.957084 A73 clk: 1200 MHz
775 20:04:22.957620 CLK81: 166.6M
776 20:04:22.958094 smccc: 00012a92
777 20:04:22.962804 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 20:04:22.963759 board id: 1
779 20:04:22.973307 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 20:04:22.984020 fw parse done
781 20:04:22.989947 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 20:04:23.032493 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 20:04:23.043520 PIEI prepare done
784 20:04:23.044089 fastboot data load
785 20:04:23.044565 fastboot data verify
786 20:04:23.049117 verify result: 266
787 20:04:23.054644 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 20:04:23.055157 LPDDR4 probe
789 20:04:23.055616 ddr clk to 1584MHz
790 20:04:23.062602 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 20:04:23.099915
792 20:04:23.100505 dmc_version 0001
793 20:04:23.106613 Check phy result
794 20:04:23.112453 INFO : End of CA training
795 20:04:23.112976 INFO : End of initialization
796 20:04:23.118049 INFO : Training has run successfully!
797 20:04:23.118576 Check phy result
798 20:04:23.123686 INFO : End of initialization
799 20:04:23.124239 INFO : End of read enable training
800 20:04:23.126914 INFO : End of fine write leveling
801 20:04:23.132475 INFO : End of Write leveling coarse delay
802 20:04:23.138054 INFO : Training has run successfully!
803 20:04:23.138559 Check phy result
804 20:04:23.139009 INFO : End of initialization
805 20:04:23.143723 INFO : End of read dq deskew training
806 20:04:23.149269 INFO : End of MPR read delay center optimization
807 20:04:23.149785 INFO : End of write delay center optimization
808 20:04:23.154879 INFO : End of read delay center optimization
809 20:04:23.160462 INFO : End of max read latency training
810 20:04:23.160974 INFO : Training has run successfully!
811 20:04:23.166041 1D training succeed
812 20:04:23.172064 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 20:04:23.219634 Check phy result
814 20:04:23.220210 INFO : End of initialization
815 20:04:23.241409 INFO : End of 2D read delay Voltage center optimization
816 20:04:23.260785 INFO : End of 2D read delay Voltage center optimization
817 20:04:23.312802 INFO : End of 2D write delay Voltage center optimization
818 20:04:23.362229 INFO : End of 2D write delay Voltage center optimization
819 20:04:23.367738 INFO : Training has run successfully!
820 20:04:23.368290
821 20:04:23.368752 channel==0
822 20:04:23.373313 RxClkDly_Margin_A0==88 ps 9
823 20:04:23.373820 TxDqDly_Margin_A0==98 ps 10
824 20:04:23.378996 RxClkDly_Margin_A1==88 ps 9
825 20:04:23.379508 TxDqDly_Margin_A1==98 ps 10
826 20:04:23.380010 TrainedVREFDQ_A0==74
827 20:04:23.384649 TrainedVREFDQ_A1==74
828 20:04:23.385186 VrefDac_Margin_A0==25
829 20:04:23.385643 DeviceVref_Margin_A0==40
830 20:04:23.390188 VrefDac_Margin_A1==25
831 20:04:23.390707 DeviceVref_Margin_A1==40
832 20:04:23.391140
833 20:04:23.391572
834 20:04:23.395723 channel==1
835 20:04:23.396248 RxClkDly_Margin_A0==88 ps 9
836 20:04:23.396690 TxDqDly_Margin_A0==98 ps 10
837 20:04:23.401399 RxClkDly_Margin_A1==88 ps 9
838 20:04:23.401890 TxDqDly_Margin_A1==88 ps 9
839 20:04:23.406999 TrainedVREFDQ_A0==77
840 20:04:23.407502 TrainedVREFDQ_A1==77
841 20:04:23.407940 VrefDac_Margin_A0==23
842 20:04:23.412514 DeviceVref_Margin_A0==37
843 20:04:23.413011 VrefDac_Margin_A1==24
844 20:04:23.418179 DeviceVref_Margin_A1==37
845 20:04:23.418669
846 20:04:23.419105 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 20:04:23.419537
848 20:04:23.451735 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
849 20:04:23.452342 2D training succeed
850 20:04:23.457383 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 20:04:23.462848 auto size-- 65535DDR cs0 size: 2048MB
852 20:04:23.463343 DDR cs1 size: 2048MB
853 20:04:23.468419 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 20:04:23.468913 cs0 DataBus test pass
855 20:04:23.474042 cs1 DataBus test pass
856 20:04:23.474537 cs0 AddrBus test pass
857 20:04:23.474970 cs1 AddrBus test pass
858 20:04:23.475398
859 20:04:23.479644 100bdlr_step_size ps== 420
860 20:04:23.480190 result report
861 20:04:23.485240 boot times 0Enable ddr reg access
862 20:04:23.490495 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 20:04:23.503964 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 20:04:24.077666 0.0;M3 CHK:0;cm4_sp_mode 0
865 20:04:24.078330 MVN_1=0x00000000
866 20:04:24.083056 MVN_2=0x00000000
867 20:04:24.088775 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 20:04:24.089290 OPS=0x10
869 20:04:24.089723 ring efuse init
870 20:04:24.090138 chipver efuse init
871 20:04:24.094418 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 20:04:24.099971 [0.018961 Inits done]
873 20:04:24.100494 secure task start!
874 20:04:24.100915 high task start!
875 20:04:24.104619 low task start!
876 20:04:24.105095 run into bl31
877 20:04:24.111210 NOTICE: BL31: v1.3(release):4fc40b1
878 20:04:24.119072 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 20:04:24.119590 NOTICE: BL31: G12A normal boot!
880 20:04:24.144431 NOTICE: BL31: BL33 decompress pass
881 20:04:24.150144 ERROR: Error initializing runtime service opteed_fast
882 20:04:25.383238
883 20:04:25.383871
884 20:04:25.391498 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 20:04:25.392045
886 20:04:25.392478 Model: Libre Computer AML-A311D-CC Alta
887 20:04:25.599972 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 20:04:25.623335 DRAM: 2 GiB (effective 3.8 GiB)
889 20:04:25.766333 Core: 408 devices, 31 uclasses, devicetree: separate
890 20:04:25.772157 WDT: Not starting watchdog@f0d0
891 20:04:25.804434 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 20:04:25.816877 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 20:04:25.821955 ** Bad device specification mmc 0 **
894 20:04:25.832197 Card did not respond to voltage select! : -110
895 20:04:25.839846 ** Bad device specification mmc 0 **
896 20:04:25.840342 Couldn't find partition mmc 0
897 20:04:25.848181 Card did not respond to voltage select! : -110
898 20:04:25.853724 ** Bad device specification mmc 0 **
899 20:04:25.854172 Couldn't find partition mmc 0
900 20:04:25.859014 Error: could not access storage.
901 20:04:26.201231 Net: eth0: ethernet@ff3f0000
902 20:04:26.201842 starting USB...
903 20:04:26.453079 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 20:04:26.453693 Starting the controller
905 20:04:26.460054 USB XHCI 1.10
906 20:04:28.322418 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 20:04:28.322958 bl2_stage_init 0x01
908 20:04:28.323246 bl2_stage_init 0x81
909 20:04:28.327931 hw id: 0x0000 - pwm id 0x01
910 20:04:28.328611 bl2_stage_init 0xc1
911 20:04:28.329041 bl2_stage_init 0x02
912 20:04:28.329441
913 20:04:28.333521 L0:00000000
914 20:04:28.334054 L1:20000703
915 20:04:28.334357 L2:00008067
916 20:04:28.334637 L3:14000000
917 20:04:28.339293 B2:00402000
918 20:04:28.339789 B1:e0f83180
919 20:04:28.340104
920 20:04:28.340382 TE: 58167
921 20:04:28.340655
922 20:04:28.344735 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 20:04:28.345268
924 20:04:28.345562 Board ID = 1
925 20:04:28.350362 Set A53 clk to 24M
926 20:04:28.351100 Set A73 clk to 24M
927 20:04:28.351468 Set clk81 to 24M
928 20:04:28.356266 A53 clk: 1200 MHz
929 20:04:28.356812 A73 clk: 1200 MHz
930 20:04:28.357088 CLK81: 166.6M
931 20:04:28.357302 smccc: 00012abd
932 20:04:28.361481 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 20:04:28.367148 board id: 1
934 20:04:28.373147 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 20:04:28.383783 fw parse done
936 20:04:28.389749 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 20:04:28.432336 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 20:04:28.443309 PIEI prepare done
939 20:04:28.443942 fastboot data load
940 20:04:28.444452 fastboot data verify
941 20:04:28.448877 verify result: 266
942 20:04:28.454501 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 20:04:28.455062 LPDDR4 probe
944 20:04:28.455511 ddr clk to 1584MHz
945 20:04:28.462649 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 20:04:28.499907
947 20:04:28.500522 dmc_version 0001
948 20:04:28.506617 Check phy result
949 20:04:28.512518 INFO : End of CA training
950 20:04:28.513056 INFO : End of initialization
951 20:04:28.518030 INFO : Training has run successfully!
952 20:04:28.518562 Check phy result
953 20:04:28.523621 INFO : End of initialization
954 20:04:28.524178 INFO : End of read enable training
955 20:04:28.529141 INFO : End of fine write leveling
956 20:04:28.534753 INFO : End of Write leveling coarse delay
957 20:04:28.535288 INFO : Training has run successfully!
958 20:04:28.535735 Check phy result
959 20:04:28.540562 INFO : End of initialization
960 20:04:28.541111 INFO : End of read dq deskew training
961 20:04:28.546059 INFO : End of MPR read delay center optimization
962 20:04:28.551621 INFO : End of write delay center optimization
963 20:04:28.557251 INFO : End of read delay center optimization
964 20:04:28.557798 INFO : End of max read latency training
965 20:04:28.562690 INFO : Training has run successfully!
966 20:04:28.563237 1D training succeed
967 20:04:28.571807 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 20:04:28.619484 Check phy result
969 20:04:28.620081 INFO : End of initialization
970 20:04:28.641186 INFO : End of 2D read delay Voltage center optimization
971 20:04:28.660556 INFO : End of 2D read delay Voltage center optimization
972 20:04:28.712591 INFO : End of 2D write delay Voltage center optimization
973 20:04:28.761976 INFO : End of 2D write delay Voltage center optimization
974 20:04:28.767554 INFO : Training has run successfully!
975 20:04:28.768140
976 20:04:28.768626 channel==0
977 20:04:28.773149 RxClkDly_Margin_A0==88 ps 9
978 20:04:28.773694 TxDqDly_Margin_A0==98 ps 10
979 20:04:28.778756 RxClkDly_Margin_A1==88 ps 9
980 20:04:28.779297 TxDqDly_Margin_A1==98 ps 10
981 20:04:28.779767 TrainedVREFDQ_A0==74
982 20:04:28.784403 TrainedVREFDQ_A1==74
983 20:04:28.784948 VrefDac_Margin_A0==25
984 20:04:28.785403 DeviceVref_Margin_A0==40
985 20:04:28.789964 VrefDac_Margin_A1==25
986 20:04:28.790510 DeviceVref_Margin_A1==40
987 20:04:28.790966
988 20:04:28.791412
989 20:04:28.795532 channel==1
990 20:04:28.796101 RxClkDly_Margin_A0==88 ps 9
991 20:04:28.796567 TxDqDly_Margin_A0==98 ps 10
992 20:04:28.801133 RxClkDly_Margin_A1==88 ps 9
993 20:04:28.801668 TxDqDly_Margin_A1==88 ps 9
994 20:04:28.806738 TrainedVREFDQ_A0==77
995 20:04:28.807276 TrainedVREFDQ_A1==77
996 20:04:28.807739 VrefDac_Margin_A0==23
997 20:04:28.812397 DeviceVref_Margin_A0==37
998 20:04:28.812935 VrefDac_Margin_A1==24
999 20:04:28.817958 DeviceVref_Margin_A1==37
1000 20:04:28.818492
1001 20:04:28.818953 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 20:04:28.819413
1003 20:04:28.851495 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
1004 20:04:28.852129 2D training succeed
1005 20:04:28.857171 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 20:04:28.862749 auto size-- 65535DDR cs0 size: 2048MB
1007 20:04:28.863285 DDR cs1 size: 2048MB
1008 20:04:28.868420 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 20:04:28.868986 cs0 DataBus test pass
1010 20:04:28.873967 cs1 DataBus test pass
1011 20:04:28.874506 cs0 AddrBus test pass
1012 20:04:28.874973 cs1 AddrBus test pass
1013 20:04:28.875422
1014 20:04:28.879540 100bdlr_step_size ps== 420
1015 20:04:28.880131 result report
1016 20:04:28.885132 boot times 0Enable ddr reg access
1017 20:04:28.890452 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 20:04:28.903868 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 20:04:29.476894 0.0;M3 CHK:0;cm4_sp_mode 0
1020 20:04:29.477335 MVN_1=0x00000000
1021 20:04:29.482354 MVN_2=0x00000000
1022 20:04:29.488123 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 20:04:29.488574 OPS=0x10
1024 20:04:29.488836 ring efuse init
1025 20:04:29.489077 chipver efuse init
1026 20:04:29.493710 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 20:04:29.499343 [0.018961 Inits done]
1028 20:04:29.499795 secure task start!
1029 20:04:29.500189 high task start!
1030 20:04:29.503903 low task start!
1031 20:04:29.504236 run into bl31
1032 20:04:29.510528 NOTICE: BL31: v1.3(release):4fc40b1
1033 20:04:29.518335 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 20:04:29.518782 NOTICE: BL31: G12A normal boot!
1035 20:04:29.543695 NOTICE: BL31: BL33 decompress pass
1036 20:04:29.549427 ERROR: Error initializing runtime service opteed_fast
1037 20:04:30.782303
1038 20:04:30.782721
1039 20:04:30.790740 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 20:04:30.791330
1041 20:04:30.791812 Model: Libre Computer AML-A311D-CC Alta
1042 20:04:30.999105 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 20:04:31.022434 DRAM: 2 GiB (effective 3.8 GiB)
1044 20:04:31.165361 Core: 408 devices, 31 uclasses, devicetree: separate
1045 20:04:31.171277 WDT: Not starting watchdog@f0d0
1046 20:04:31.203494 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 20:04:31.215968 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 20:04:31.220969 ** Bad device specification mmc 0 **
1049 20:04:31.231285 Card did not respond to voltage select! : -110
1050 20:04:31.238957 ** Bad device specification mmc 0 **
1051 20:04:31.239468 Couldn't find partition mmc 0
1052 20:04:31.247266 Card did not respond to voltage select! : -110
1053 20:04:31.252810 ** Bad device specification mmc 0 **
1054 20:04:31.253321 Couldn't find partition mmc 0
1055 20:04:31.257842 Error: could not access storage.
1056 20:04:31.600397 Net: eth0: ethernet@ff3f0000
1057 20:04:31.600967 starting USB...
1058 20:04:31.852232 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 20:04:31.852821 Starting the controller
1060 20:04:31.859243 USB XHCI 1.10
1061 20:04:33.413237 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 20:04:33.421593 scanning usb for storage devices... 0 Storage Device(s) found
1064 20:04:33.473413 Hit any key to stop autoboot: 1
1065 20:04:33.474239 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 20:04:33.474876 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 20:04:33.475382 Setting prompt string to ['=>']
1068 20:04:33.475890 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 20:04:33.489001 0
1070 20:04:33.489931 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 20:04:33.490476 Sending with 10 millisecond of delay
1073 20:04:34.625131 => setenv autoload no
1074 20:04:34.635970 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 20:04:34.641419 setenv autoload no
1076 20:04:34.642237 Sending with 10 millisecond of delay
1078 20:04:36.439697 => setenv initrd_high 0xffffffff
1079 20:04:36.450325 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 20:04:36.450924 setenv initrd_high 0xffffffff
1081 20:04:36.451469 Sending with 10 millisecond of delay
1083 20:04:38.068632 => setenv fdt_high 0xffffffff
1084 20:04:38.079424 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1085 20:04:38.080200 setenv fdt_high 0xffffffff
1086 20:04:38.080712 Sending with 10 millisecond of delay
1088 20:04:38.372298 => dhcp
1089 20:04:38.383115 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 20:04:38.383812 dhcp
1091 20:04:38.384099 Speed: 1000, full duplex
1092 20:04:38.384321 BOOTP broadcast 1
1093 20:04:38.630965 BOOTP broadcast 2
1094 20:04:38.655234 DHCP client bound to address 192.168.6.33 (272 ms)
1095 20:04:38.655883 Sending with 10 millisecond of delay
1097 20:04:40.337242 => setenv serverip 192.168.6.2
1098 20:04:40.348030 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 20:04:40.348583 setenv serverip 192.168.6.2
1100 20:04:40.349041 Sending with 10 millisecond of delay
1102 20:04:44.072512 => tftpboot 0x01080000 823126/tftp-deploy-3_9h8a0j/kernel/uImage
1103 20:04:44.083335 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1104 20:04:44.084282 tftpboot 0x01080000 823126/tftp-deploy-3_9h8a0j/kernel/uImage
1105 20:04:44.084736 Speed: 1000, full duplex
1106 20:04:44.085137 Using ethernet@ff3f0000 device
1107 20:04:44.086077 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1108 20:04:44.091865 Filename '823126/tftp-deploy-3_9h8a0j/kernel/uImage'.
1109 20:04:44.095491 Load address: 0x1080000
1110 20:04:48.010330 Loading: *################################################## 43.6 MiB
1111 20:04:48.010756 11.1 MiB/s
1112 20:04:48.010983 done
1113 20:04:48.014366 Bytes transferred = 45713984 (2b98a40 hex)
1114 20:04:48.014873 Sending with 10 millisecond of delay
1116 20:04:52.712409 => tftpboot 0x08000000 823126/tftp-deploy-3_9h8a0j/ramdisk/ramdisk.cpio.gz.uboot
1117 20:04:52.724042 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1118 20:04:52.724612 tftpboot 0x08000000 823126/tftp-deploy-3_9h8a0j/ramdisk/ramdisk.cpio.gz.uboot
1119 20:04:52.724855 Speed: 1000, full duplex
1120 20:04:52.725063 Using ethernet@ff3f0000 device
1121 20:04:52.727465 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1122 20:04:52.735450 Filename '823126/tftp-deploy-3_9h8a0j/ramdisk/ramdisk.cpio.gz.uboot'.
1123 20:04:52.735800 Load address: 0x8000000
1124 20:04:57.890384 Loading: *################################################# UDP wrong checksum 0000000f 000011a0
1125 20:05:02.892692 T UDP wrong checksum 0000000f 000011a0
1126 20:05:12.894471 T T UDP wrong checksum 0000000f 000011a0
1127 20:05:32.898304 T T T T UDP wrong checksum 0000000f 000011a0
1128 20:05:36.820401 UDP wrong checksum 000000ff 0000a8c6
1129 20:05:36.860354 UDP wrong checksum 000000ff 00003ab9
1130 20:05:52.903327 T T T
1131 20:05:52.903956 Retry count exceeded; starting again
1133 20:05:52.905427 end: 2.4.3 bootloader-commands (duration 00:01:19) [common]
1136 20:05:52.907283 end: 2.4 uboot-commands (duration 00:01:56) [common]
1138 20:05:52.908871 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1140 20:05:52.909933 end: 2 uboot-action (duration 00:01:56) [common]
1142 20:05:52.911429 Cleaning after the job
1143 20:05:52.911975 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/ramdisk
1144 20:05:52.913210 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/kernel
1145 20:05:52.920627 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/dtb
1146 20:05:52.921857 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823126/tftp-deploy-3_9h8a0j/modules
1147 20:05:52.927899 start: 4.1 power-off (timeout 00:00:30) [common]
1148 20:05:52.928969 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1149 20:05:52.963589 >> OK - accepted request
1150 20:05:52.965327 Returned 0 in 0 seconds
1151 20:05:53.066467 end: 4.1 power-off (duration 00:00:00) [common]
1153 20:05:53.068240 start: 4.2 read-feedback (timeout 00:10:00) [common]
1154 20:05:53.069356 Listened to connection for namespace 'common' for up to 1s
1155 20:05:54.070217 Finalising connection for namespace 'common'
1156 20:05:54.071036 Disconnecting from shell: Finalise
1157 20:05:54.071609 =>
1158 20:05:54.172747 end: 4.2 read-feedback (duration 00:00:01) [common]
1159 20:05:54.173459 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/823126
1160 20:05:54.816431 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/823126
1161 20:05:54.817029 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.