Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 12:29:32.739241 lava-dispatcher, installed at version: 2024.01
2 12:29:32.740041 start: 0 validate
3 12:29:32.740525 Start time: 2024-10-09 12:29:32.740495+00:00 (UTC)
4 12:29:32.741070 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 12:29:32.741605 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 12:29:32.786408 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 12:29:32.786974 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-7-g556be13a9b36%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 12:29:32.819157 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 12:29:32.819808 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-7-g556be13a9b36%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 12:29:32.853411 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 12:29:32.853921 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:29:32.888427 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 12:29:32.888957 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-7-g556be13a9b36%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 12:29:32.934417 validate duration: 0.19
16 12:29:32.935625 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:29:32.936368 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:29:32.936975 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:29:32.937988 Not decompressing ramdisk as can be used compressed.
20 12:29:32.938796 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 12:29:32.939344 saving as /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/ramdisk/initrd.cpio.gz
22 12:29:32.939882 total size: 5628169 (5 MB)
23 12:29:32.983695 progress 0 % (0 MB)
24 12:29:32.991553 progress 5 % (0 MB)
25 12:29:32.999629 progress 10 % (0 MB)
26 12:29:33.006687 progress 15 % (0 MB)
27 12:29:33.013595 progress 20 % (1 MB)
28 12:29:33.017832 progress 25 % (1 MB)
29 12:29:33.022026 progress 30 % (1 MB)
30 12:29:33.026123 progress 35 % (1 MB)
31 12:29:33.029886 progress 40 % (2 MB)
32 12:29:33.034026 progress 45 % (2 MB)
33 12:29:33.037721 progress 50 % (2 MB)
34 12:29:33.041830 progress 55 % (2 MB)
35 12:29:33.045899 progress 60 % (3 MB)
36 12:29:33.049590 progress 65 % (3 MB)
37 12:29:33.053678 progress 70 % (3 MB)
38 12:29:33.057422 progress 75 % (4 MB)
39 12:29:33.061619 progress 80 % (4 MB)
40 12:29:33.065282 progress 85 % (4 MB)
41 12:29:33.069323 progress 90 % (4 MB)
42 12:29:33.073282 progress 95 % (5 MB)
43 12:29:33.076621 progress 100 % (5 MB)
44 12:29:33.077303 5 MB downloaded in 0.14 s (39.06 MB/s)
45 12:29:33.077831 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:29:33.078731 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:29:33.079024 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:29:33.079294 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:29:33.079777 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/kernel/Image
51 12:29:33.080057 saving as /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/kernel/Image
52 12:29:33.080275 total size: 45713920 (43 MB)
53 12:29:33.080486 No compression specified
54 12:29:33.116988 progress 0 % (0 MB)
55 12:29:33.147201 progress 5 % (2 MB)
56 12:29:33.178181 progress 10 % (4 MB)
57 12:29:33.208658 progress 15 % (6 MB)
58 12:29:33.239314 progress 20 % (8 MB)
59 12:29:33.268632 progress 25 % (10 MB)
60 12:29:33.298132 progress 30 % (13 MB)
61 12:29:33.329591 progress 35 % (15 MB)
62 12:29:33.360462 progress 40 % (17 MB)
63 12:29:33.389797 progress 45 % (19 MB)
64 12:29:33.419224 progress 50 % (21 MB)
65 12:29:33.448905 progress 55 % (24 MB)
66 12:29:33.478551 progress 60 % (26 MB)
67 12:29:33.508352 progress 65 % (28 MB)
68 12:29:33.538766 progress 70 % (30 MB)
69 12:29:33.568882 progress 75 % (32 MB)
70 12:29:33.598523 progress 80 % (34 MB)
71 12:29:33.627559 progress 85 % (37 MB)
72 12:29:33.657169 progress 90 % (39 MB)
73 12:29:33.686771 progress 95 % (41 MB)
74 12:29:33.715947 progress 100 % (43 MB)
75 12:29:33.716508 43 MB downloaded in 0.64 s (68.52 MB/s)
76 12:29:33.716984 end: 1.2.1 http-download (duration 00:00:01) [common]
78 12:29:33.717838 end: 1.2 download-retry (duration 00:00:01) [common]
79 12:29:33.718115 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:29:33.718380 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:29:33.718853 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 12:29:33.719122 saving as /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/dtb/meson-g12b-a311d-libretech-cc.dtb
83 12:29:33.719333 total size: 54703 (0 MB)
84 12:29:33.719543 No compression specified
85 12:29:33.760964 progress 59 % (0 MB)
86 12:29:33.761834 progress 100 % (0 MB)
87 12:29:33.762403 0 MB downloaded in 0.04 s (1.21 MB/s)
88 12:29:33.762919 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:29:33.763773 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:29:33.764078 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:29:33.764371 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:29:33.764868 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 12:29:33.765135 saving as /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/nfsrootfs/full.rootfs.tar
95 12:29:33.765349 total size: 120894716 (115 MB)
96 12:29:33.765564 Using unxz to decompress xz
97 12:29:33.804098 progress 0 % (0 MB)
98 12:29:34.606630 progress 5 % (5 MB)
99 12:29:35.449137 progress 10 % (11 MB)
100 12:29:36.249264 progress 15 % (17 MB)
101 12:29:36.989069 progress 20 % (23 MB)
102 12:29:37.587925 progress 25 % (28 MB)
103 12:29:38.412047 progress 30 % (34 MB)
104 12:29:39.206853 progress 35 % (40 MB)
105 12:29:39.551891 progress 40 % (46 MB)
106 12:29:39.923262 progress 45 % (51 MB)
107 12:29:40.673249 progress 50 % (57 MB)
108 12:29:41.568356 progress 55 % (63 MB)
109 12:29:42.356947 progress 60 % (69 MB)
110 12:29:43.125320 progress 65 % (74 MB)
111 12:29:43.912361 progress 70 % (80 MB)
112 12:29:44.747378 progress 75 % (86 MB)
113 12:29:45.539221 progress 80 % (92 MB)
114 12:29:46.306296 progress 85 % (98 MB)
115 12:29:47.173166 progress 90 % (103 MB)
116 12:29:47.975162 progress 95 % (109 MB)
117 12:29:48.821297 progress 100 % (115 MB)
118 12:29:48.833835 115 MB downloaded in 15.07 s (7.65 MB/s)
119 12:29:48.834783 end: 1.4.1 http-download (duration 00:00:15) [common]
121 12:29:48.836575 end: 1.4 download-retry (duration 00:00:15) [common]
122 12:29:48.837153 start: 1.5 download-retry (timeout 00:09:44) [common]
123 12:29:48.837714 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 12:29:48.838701 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/modules.tar.xz
125 12:29:48.839231 saving as /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/modules/modules.tar
126 12:29:48.839677 total size: 11609636 (11 MB)
127 12:29:48.840168 Using unxz to decompress xz
128 12:29:48.887201 progress 0 % (0 MB)
129 12:29:48.951120 progress 5 % (0 MB)
130 12:29:49.029897 progress 10 % (1 MB)
131 12:29:49.123229 progress 15 % (1 MB)
132 12:29:49.216398 progress 20 % (2 MB)
133 12:29:49.300424 progress 25 % (2 MB)
134 12:29:49.379170 progress 30 % (3 MB)
135 12:29:49.463131 progress 35 % (3 MB)
136 12:29:49.539825 progress 40 % (4 MB)
137 12:29:49.618271 progress 45 % (5 MB)
138 12:29:49.701618 progress 50 % (5 MB)
139 12:29:49.780572 progress 55 % (6 MB)
140 12:29:49.868909 progress 60 % (6 MB)
141 12:29:49.944756 progress 65 % (7 MB)
142 12:29:50.025593 progress 70 % (7 MB)
143 12:29:50.099440 progress 75 % (8 MB)
144 12:29:50.177059 progress 80 % (8 MB)
145 12:29:50.262220 progress 85 % (9 MB)
146 12:29:50.341936 progress 90 % (9 MB)
147 12:29:50.424010 progress 95 % (10 MB)
148 12:29:50.504809 progress 100 % (11 MB)
149 12:29:50.516698 11 MB downloaded in 1.68 s (6.60 MB/s)
150 12:29:50.517281 end: 1.5.1 http-download (duration 00:00:02) [common]
152 12:29:50.518110 end: 1.5 download-retry (duration 00:00:02) [common]
153 12:29:50.518377 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 12:29:50.518640 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 12:30:07.235225 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/826935/extract-nfsrootfs-f0ktqxdm
156 12:30:07.235821 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 12:30:07.236172 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 12:30:07.236825 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf
159 12:30:07.237306 makedir: /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin
160 12:30:07.237718 makedir: /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/tests
161 12:30:07.238102 makedir: /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/results
162 12:30:07.238475 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-add-keys
163 12:30:07.239020 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-add-sources
164 12:30:07.239581 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-background-process-start
165 12:30:07.240172 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-background-process-stop
166 12:30:07.240710 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-common-functions
167 12:30:07.241205 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-echo-ipv4
168 12:30:07.241686 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-install-packages
169 12:30:07.242180 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-installed-packages
170 12:30:07.242677 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-os-build
171 12:30:07.243150 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-probe-channel
172 12:30:07.243619 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-probe-ip
173 12:30:07.244116 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-target-ip
174 12:30:07.244597 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-target-mac
175 12:30:07.245075 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-target-storage
176 12:30:07.245563 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-test-case
177 12:30:07.246080 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-test-event
178 12:30:07.246590 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-test-feedback
179 12:30:07.247077 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-test-raise
180 12:30:07.247552 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-test-reference
181 12:30:07.248064 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-test-runner
182 12:30:07.248576 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-test-set
183 12:30:07.249056 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-test-shell
184 12:30:07.249558 Updating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-add-keys (debian)
185 12:30:07.250099 Updating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-add-sources (debian)
186 12:30:07.250615 Updating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-install-packages (debian)
187 12:30:07.251122 Updating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-installed-packages (debian)
188 12:30:07.251611 Updating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/bin/lava-os-build (debian)
189 12:30:07.252080 Creating /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/environment
190 12:30:07.252473 LAVA metadata
191 12:30:07.252731 - LAVA_JOB_ID=826935
192 12:30:07.252946 - LAVA_DISPATCHER_IP=192.168.6.2
193 12:30:07.253316 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 12:30:07.254332 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 12:30:07.254643 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 12:30:07.254850 skipped lava-vland-overlay
197 12:30:07.255088 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 12:30:07.255338 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 12:30:07.255553 skipped lava-multinode-overlay
200 12:30:07.255792 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 12:30:07.256072 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 12:30:07.256327 Loading test definitions
203 12:30:07.256602 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 12:30:07.256818 Using /lava-826935 at stage 0
205 12:30:07.257886 uuid=826935_1.6.2.4.1 testdef=None
206 12:30:07.258185 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 12:30:07.258444 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 12:30:07.260032 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 12:30:07.260822 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 12:30:07.262752 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 12:30:07.263563 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 12:30:07.265428 runner path: /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/0/tests/0_timesync-off test_uuid 826935_1.6.2.4.1
215 12:30:07.265982 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 12:30:07.266789 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 12:30:07.267022 Using /lava-826935 at stage 0
219 12:30:07.267375 Fetching tests from https://github.com/kernelci/test-definitions.git
220 12:30:07.267662 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/0/tests/1_kselftest-alsa'
221 12:30:10.615974 Running '/usr/bin/git checkout kernelci.org
222 12:30:11.082379 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 12:30:11.083920 uuid=826935_1.6.2.4.5 testdef=None
224 12:30:11.084598 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 12:30:11.086209 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 12:30:11.092395 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 12:30:11.094199 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 12:30:11.102449 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 12:30:11.104373 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 12:30:11.112135 runner path: /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/0/tests/1_kselftest-alsa test_uuid 826935_1.6.2.4.5
234 12:30:11.112717 BOARD='meson-g12b-a311d-libretech-cc'
235 12:30:11.113165 BRANCH='lee-mfd'
236 12:30:11.113597 SKIPFILE='/dev/null'
237 12:30:11.114027 SKIP_INSTALL='True'
238 12:30:11.114456 TESTPROG_URL='http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 12:30:11.114896 TST_CASENAME=''
240 12:30:11.115324 TST_CMDFILES='alsa'
241 12:30:11.116429 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 12:30:11.118113 Creating lava-test-runner.conf files
244 12:30:11.118553 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/826935/lava-overlay-avpydxkf/lava-826935/0 for stage 0
245 12:30:11.119270 - 0_timesync-off
246 12:30:11.119780 - 1_kselftest-alsa
247 12:30:11.120500 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 12:30:11.121087 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 12:30:35.324695 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 12:30:35.325117 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 12:30:35.325412 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 12:30:35.325721 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 12:30:35.326018 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 12:30:35.939515 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 12:30:35.940139 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 12:30:35.940478 extracting modules file /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/826935/extract-nfsrootfs-f0ktqxdm
257 12:30:37.564286 extracting modules file /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/826935/extract-overlay-ramdisk-p0ffbzd2/ramdisk
258 12:30:38.985881 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 12:30:38.986374 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 12:30:38.986665 [common] Applying overlay to NFS
261 12:30:38.986880 [common] Applying overlay /var/lib/lava/dispatcher/tmp/826935/compress-overlay-aubr7mvp/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/826935/extract-nfsrootfs-f0ktqxdm
262 12:30:41.738173 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 12:30:41.738614 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 12:30:41.738887 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 12:30:41.739120 Converting downloaded kernel to a uImage
266 12:30:41.739434 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/kernel/Image /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/kernel/uImage
267 12:30:42.209572 output: Image Name:
268 12:30:42.209974 output: Created: Wed Oct 9 12:30:41 2024
269 12:30:42.210208 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 12:30:42.210414 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 12:30:42.210615 output: Load Address: 01080000
272 12:30:42.210836 output: Entry Point: 01080000
273 12:30:42.211042 output:
274 12:30:42.211375 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 12:30:42.211642 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 12:30:42.211917 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 12:30:42.212214 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 12:30:42.212474 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 12:30:42.212732 Building ramdisk /var/lib/lava/dispatcher/tmp/826935/extract-overlay-ramdisk-p0ffbzd2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/826935/extract-overlay-ramdisk-p0ffbzd2/ramdisk
280 12:30:44.383006 >> 166772 blocks
281 12:30:52.101866 Adding RAMdisk u-boot header.
282 12:30:52.102312 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/826935/extract-overlay-ramdisk-p0ffbzd2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/826935/extract-overlay-ramdisk-p0ffbzd2/ramdisk.cpio.gz.uboot
283 12:30:52.347214 output: Image Name:
284 12:30:52.347627 output: Created: Wed Oct 9 12:30:52 2024
285 12:30:52.347833 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 12:30:52.348122 output: Data Size: 23425164 Bytes = 22876.14 KiB = 22.34 MiB
287 12:30:52.348570 output: Load Address: 00000000
288 12:30:52.349002 output: Entry Point: 00000000
289 12:30:52.349435 output:
290 12:30:52.350636 rename /var/lib/lava/dispatcher/tmp/826935/extract-overlay-ramdisk-p0ffbzd2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/ramdisk/ramdisk.cpio.gz.uboot
291 12:30:52.351411 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 12:30:52.352026 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 12:30:52.352613 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 12:30:52.353107 No LXC device requested
295 12:30:52.353652 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 12:30:52.354204 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 12:30:52.354740 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 12:30:52.355187 Checking files for TFTP limit of 4294967296 bytes.
299 12:30:52.358104 end: 1 tftp-deploy (duration 00:01:19) [common]
300 12:30:52.358723 start: 2 uboot-action (timeout 00:05:00) [common]
301 12:30:52.359289 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 12:30:52.359829 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 12:30:52.360409 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 12:30:52.360981 Using kernel file from prepare-kernel: 826935/tftp-deploy-xv3srcgq/kernel/uImage
305 12:30:52.361664 substitutions:
306 12:30:52.362113 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 12:30:52.362554 - {DTB_ADDR}: 0x01070000
308 12:30:52.362989 - {DTB}: 826935/tftp-deploy-xv3srcgq/dtb/meson-g12b-a311d-libretech-cc.dtb
309 12:30:52.363425 - {INITRD}: 826935/tftp-deploy-xv3srcgq/ramdisk/ramdisk.cpio.gz.uboot
310 12:30:52.363856 - {KERNEL_ADDR}: 0x01080000
311 12:30:52.364317 - {KERNEL}: 826935/tftp-deploy-xv3srcgq/kernel/uImage
312 12:30:52.364754 - {LAVA_MAC}: None
313 12:30:52.365224 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/826935/extract-nfsrootfs-f0ktqxdm
314 12:30:52.365657 - {NFS_SERVER_IP}: 192.168.6.2
315 12:30:52.366080 - {PRESEED_CONFIG}: None
316 12:30:52.366508 - {PRESEED_LOCAL}: None
317 12:30:52.366936 - {RAMDISK_ADDR}: 0x08000000
318 12:30:52.367358 - {RAMDISK}: 826935/tftp-deploy-xv3srcgq/ramdisk/ramdisk.cpio.gz.uboot
319 12:30:52.367785 - {ROOT_PART}: None
320 12:30:52.368243 - {ROOT}: None
321 12:30:52.368667 - {SERVER_IP}: 192.168.6.2
322 12:30:52.369089 - {TEE_ADDR}: 0x83000000
323 12:30:52.369508 - {TEE}: None
324 12:30:52.369930 Parsed boot commands:
325 12:30:52.370338 - setenv autoload no
326 12:30:52.370753 - setenv initrd_high 0xffffffff
327 12:30:52.371173 - setenv fdt_high 0xffffffff
328 12:30:52.371588 - dhcp
329 12:30:52.372021 - setenv serverip 192.168.6.2
330 12:30:52.372446 - tftpboot 0x01080000 826935/tftp-deploy-xv3srcgq/kernel/uImage
331 12:30:52.372872 - tftpboot 0x08000000 826935/tftp-deploy-xv3srcgq/ramdisk/ramdisk.cpio.gz.uboot
332 12:30:52.373296 - tftpboot 0x01070000 826935/tftp-deploy-xv3srcgq/dtb/meson-g12b-a311d-libretech-cc.dtb
333 12:30:52.373720 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/826935/extract-nfsrootfs-f0ktqxdm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 12:30:52.374155 - bootm 0x01080000 0x08000000 0x01070000
335 12:30:52.374700 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 12:30:52.376339 start: 2.3 connect-device (timeout 00:05:00) [common]
338 12:30:52.376796 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 12:30:52.391674 Setting prompt string to ['lava-test: # ']
340 12:30:52.393328 end: 2.3 connect-device (duration 00:00:00) [common]
341 12:30:52.394007 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 12:30:52.394611 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 12:30:52.395342 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 12:30:52.396613 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 12:30:52.431142 >> OK - accepted request
346 12:30:52.433291 Returned 0 in 0 seconds
347 12:30:52.534430 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 12:30:52.536212 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 12:30:52.536812 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 12:30:52.537351 Setting prompt string to ['Hit any key to stop autoboot']
352 12:30:52.537835 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 12:30:52.539493 Trying 192.168.56.21...
354 12:30:52.540045 Connected to conserv1.
355 12:30:52.540496 Escape character is '^]'.
356 12:30:52.540949
357 12:30:52.541406 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 12:30:52.541868
359 12:31:04.043887 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 12:31:04.044559 bl2_stage_init 0x01
361 12:31:04.045021 bl2_stage_init 0x81
362 12:31:04.049435 hw id: 0x0000 - pwm id 0x01
363 12:31:04.049934 bl2_stage_init 0xc1
364 12:31:04.050383 bl2_stage_init 0x02
365 12:31:04.050826
366 12:31:04.054999 L0:00000000
367 12:31:04.055495 L1:20000703
368 12:31:04.055949 L2:00008067
369 12:31:04.056436 L3:14000000
370 12:31:04.057806 B2:00402000
371 12:31:04.058287 B1:e0f83180
372 12:31:04.058730
373 12:31:04.059160 TE: 58124
374 12:31:04.059600
375 12:31:04.068943 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 12:31:04.069417
377 12:31:04.069849 Board ID = 1
378 12:31:04.070517 Set A53 clk to 24M
379 12:31:04.070966 Set A73 clk to 24M
380 12:31:04.074571 Set clk81 to 24M
381 12:31:04.075035 A53 clk: 1200 MHz
382 12:31:04.075461 A73 clk: 1200 MHz
383 12:31:04.077957 CLK81: 166.6M
384 12:31:04.078410 smccc: 00012a92
385 12:31:04.083520 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 12:31:04.089156 board id: 1
387 12:31:04.093517 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 12:31:04.105147 fw parse done
389 12:31:04.110102 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 12:31:04.152788 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 12:31:04.164680 PIEI prepare done
392 12:31:04.165133 fastboot data load
393 12:31:04.165772 fastboot data verify
394 12:31:04.170425 verify result: 266
395 12:31:04.175959 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 12:31:04.176479 LPDDR4 probe
397 12:31:04.176958 ddr clk to 1584MHz
398 12:31:04.182909 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 12:31:04.220205
400 12:31:04.220783 dmc_version 0001
401 12:31:04.226790 Check phy result
402 12:31:04.233634 INFO : End of CA training
403 12:31:04.234135 INFO : End of initialization
404 12:31:04.239367 INFO : Training has run successfully!
405 12:31:04.239864 Check phy result
406 12:31:04.244867 INFO : End of initialization
407 12:31:04.245368 INFO : End of read enable training
408 12:31:04.250506 INFO : End of fine write leveling
409 12:31:04.256077 INFO : End of Write leveling coarse delay
410 12:31:04.256573 INFO : Training has run successfully!
411 12:31:04.257025 Check phy result
412 12:31:04.261628 INFO : End of initialization
413 12:31:04.262135 INFO : End of read dq deskew training
414 12:31:04.267327 INFO : End of MPR read delay center optimization
415 12:31:04.272918 INFO : End of write delay center optimization
416 12:31:04.278496 INFO : End of read delay center optimization
417 12:31:04.278980 INFO : End of max read latency training
418 12:31:04.284098 INFO : Training has run successfully!
419 12:31:04.284634 1D training succeed
420 12:31:04.292329 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 12:31:04.339850 Check phy result
422 12:31:04.340438 INFO : End of initialization
423 12:31:04.362577 INFO : End of 2D read delay Voltage center optimization
424 12:31:04.382746 INFO : End of 2D read delay Voltage center optimization
425 12:31:04.434852 INFO : End of 2D write delay Voltage center optimization
426 12:31:04.485154 INFO : End of 2D write delay Voltage center optimization
427 12:31:04.490675 INFO : Training has run successfully!
428 12:31:04.491142
429 12:31:04.491584 channel==0
430 12:31:04.496309 RxClkDly_Margin_A0==88 ps 9
431 12:31:04.496777 TxDqDly_Margin_A0==98 ps 10
432 12:31:04.501935 RxClkDly_Margin_A1==88 ps 9
433 12:31:04.502392 TxDqDly_Margin_A1==88 ps 9
434 12:31:04.502827 TrainedVREFDQ_A0==74
435 12:31:04.507503 TrainedVREFDQ_A1==74
436 12:31:04.508025 VrefDac_Margin_A0==24
437 12:31:04.508468 DeviceVref_Margin_A0==40
438 12:31:04.513095 VrefDac_Margin_A1==25
439 12:31:04.513598 DeviceVref_Margin_A1==40
440 12:31:04.514037
441 12:31:04.514469
442 12:31:04.514903 channel==1
443 12:31:04.518763 RxClkDly_Margin_A0==98 ps 10
444 12:31:04.519291 TxDqDly_Margin_A0==98 ps 10
445 12:31:04.524336 RxClkDly_Margin_A1==98 ps 10
446 12:31:04.524809 TxDqDly_Margin_A1==88 ps 9
447 12:31:04.529942 TrainedVREFDQ_A0==77
448 12:31:04.530417 TrainedVREFDQ_A1==77
449 12:31:04.530853 VrefDac_Margin_A0==22
450 12:31:04.535459 DeviceVref_Margin_A0==37
451 12:31:04.535926 VrefDac_Margin_A1==23
452 12:31:04.541063 DeviceVref_Margin_A1==37
453 12:31:04.541515
454 12:31:04.541952 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 12:31:04.542384
456 12:31:04.574791 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 12:31:04.575426 2D training succeed
458 12:31:04.580313 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 12:31:04.585987 auto size-- 65535DDR cs0 size: 2048MB
460 12:31:04.586495 DDR cs1 size: 2048MB
461 12:31:04.591551 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 12:31:04.592082 cs0 DataBus test pass
463 12:31:04.597101 cs1 DataBus test pass
464 12:31:04.597586 cs0 AddrBus test pass
465 12:31:04.598028 cs1 AddrBus test pass
466 12:31:04.598458
467 12:31:04.602696 100bdlr_step_size ps== 420
468 12:31:04.603197 result report
469 12:31:04.608285 boot times 0Enable ddr reg access
470 12:31:04.612644 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 12:31:04.626159 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 12:31:05.200704 0.0;M3 CHK:0;cm4_sp_mode 0
473 12:31:05.201329 MVN_1=0x00000000
474 12:31:05.206265 MVN_2=0x00000000
475 12:31:05.211956 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 12:31:05.212488 OPS=0x10
477 12:31:05.212933 ring efuse init
478 12:31:05.213364 chipver efuse init
479 12:31:05.220205 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 12:31:05.220696 [0.018961 Inits done]
481 12:31:05.226787 secure task start!
482 12:31:05.227317 high task start!
483 12:31:05.227783 low task start!
484 12:31:05.228267 run into bl31
485 12:31:05.234478 NOTICE: BL31: v1.3(release):4fc40b1
486 12:31:05.241281 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 12:31:05.241757 NOTICE: BL31: G12A normal boot!
488 12:31:05.267564 NOTICE: BL31: BL33 decompress pass
489 12:31:05.272338 ERROR: Error initializing runtime service opteed_fast
490 12:31:06.506060
491 12:31:06.506705
492 12:31:06.514484 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 12:31:06.514980
494 12:31:06.515436 Model: Libre Computer AML-A311D-CC Alta
495 12:31:06.726649 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 12:31:06.746218 DRAM: 2 GiB (effective 3.8 GiB)
497 12:31:06.889274 Core: 408 devices, 31 uclasses, devicetree: separate
498 12:31:06.895154 WDT: Not starting watchdog@f0d0
499 12:31:06.927415 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 12:31:06.939880 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 12:31:06.944815 ** Bad device specification mmc 0 **
502 12:31:06.955166 Card did not respond to voltage select! : -110
503 12:31:06.962787 ** Bad device specification mmc 0 **
504 12:31:06.963305 Couldn't find partition mmc 0
505 12:31:06.971173 Card did not respond to voltage select! : -110
506 12:31:06.976671 ** Bad device specification mmc 0 **
507 12:31:06.977200 Couldn't find partition mmc 0
508 12:31:06.981740 Error: could not access storage.
509 12:31:08.244306 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 12:31:08.244941 bl2_stage_init 0x01
511 12:31:08.245437 bl2_stage_init 0x81
512 12:31:08.249865 hw id: 0x0000 - pwm id 0x01
513 12:31:08.250427 bl2_stage_init 0xc1
514 12:31:08.250925 bl2_stage_init 0x02
515 12:31:08.251417
516 12:31:08.255436 L0:00000000
517 12:31:08.256053 L1:20000703
518 12:31:08.256579 L2:00008067
519 12:31:08.257072 L3:14000000
520 12:31:08.261054 B2:00402000
521 12:31:08.261640 B1:e0f83180
522 12:31:08.262165
523 12:31:08.262686 TE: 58167
524 12:31:08.263172
525 12:31:08.266640 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 12:31:08.267197
527 12:31:08.267666 Board ID = 1
528 12:31:08.272277 Set A53 clk to 24M
529 12:31:08.272825 Set A73 clk to 24M
530 12:31:08.273291 Set clk81 to 24M
531 12:31:08.277893 A53 clk: 1200 MHz
532 12:31:08.278569 A73 clk: 1200 MHz
533 12:31:08.279081 CLK81: 166.6M
534 12:31:08.279545 smccc: 00012abe
535 12:31:08.283439 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 12:31:08.289018 board id: 1
537 12:31:08.294938 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 12:31:08.305579 fw parse done
539 12:31:08.311521 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 12:31:08.354153 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 12:31:08.365074 PIEI prepare done
542 12:31:08.365615 fastboot data load
543 12:31:08.366083 fastboot data verify
544 12:31:08.370742 verify result: 266
545 12:31:08.376383 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 12:31:08.376953 LPDDR4 probe
547 12:31:08.377434 ddr clk to 1584MHz
548 12:31:08.384397 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 12:31:08.421431
550 12:31:08.422033 dmc_version 0001
551 12:31:08.428343 Check phy result
552 12:31:08.434163 INFO : End of CA training
553 12:31:08.434701 INFO : End of initialization
554 12:31:08.439779 INFO : Training has run successfully!
555 12:31:08.440348 Check phy result
556 12:31:08.445393 INFO : End of initialization
557 12:31:08.445919 INFO : End of read enable training
558 12:31:08.451015 INFO : End of fine write leveling
559 12:31:08.456540 INFO : End of Write leveling coarse delay
560 12:31:08.457075 INFO : Training has run successfully!
561 12:31:08.457543 Check phy result
562 12:31:08.462157 INFO : End of initialization
563 12:31:08.462685 INFO : End of read dq deskew training
564 12:31:08.467781 INFO : End of MPR read delay center optimization
565 12:31:08.473374 INFO : End of write delay center optimization
566 12:31:08.478978 INFO : End of read delay center optimization
567 12:31:08.479518 INFO : End of max read latency training
568 12:31:08.484564 INFO : Training has run successfully!
569 12:31:08.485098 1D training succeed
570 12:31:08.493718 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 12:31:08.541450 Check phy result
572 12:31:08.542032 INFO : End of initialization
573 12:31:08.563141 INFO : End of 2D read delay Voltage center optimization
574 12:31:08.583347 INFO : End of 2D read delay Voltage center optimization
575 12:31:08.634512 INFO : End of 2D write delay Voltage center optimization
576 12:31:08.684812 INFO : End of 2D write delay Voltage center optimization
577 12:31:08.690423 INFO : Training has run successfully!
578 12:31:08.690953
579 12:31:08.691412 channel==0
580 12:31:08.695970 RxClkDly_Margin_A0==88 ps 9
581 12:31:08.696540 TxDqDly_Margin_A0==98 ps 10
582 12:31:08.701674 RxClkDly_Margin_A1==88 ps 9
583 12:31:08.702202 TxDqDly_Margin_A1==98 ps 10
584 12:31:08.702667 TrainedVREFDQ_A0==74
585 12:31:08.707218 TrainedVREFDQ_A1==74
586 12:31:08.707938 VrefDac_Margin_A0==25
587 12:31:08.708486 DeviceVref_Margin_A0==40
588 12:31:08.712784 VrefDac_Margin_A1==25
589 12:31:08.713327 DeviceVref_Margin_A1==40
590 12:31:08.713789
591 12:31:08.714243
592 12:31:08.718490 channel==1
593 12:31:08.719039 RxClkDly_Margin_A0==98 ps 10
594 12:31:08.719500 TxDqDly_Margin_A0==88 ps 9
595 12:31:08.724265 RxClkDly_Margin_A1==98 ps 10
596 12:31:08.724798 TxDqDly_Margin_A1==88 ps 9
597 12:31:08.729746 TrainedVREFDQ_A0==76
598 12:31:08.730291 TrainedVREFDQ_A1==77
599 12:31:08.730754 VrefDac_Margin_A0==22
600 12:31:08.735106 DeviceVref_Margin_A0==38
601 12:31:08.735636 VrefDac_Margin_A1==22
602 12:31:08.740817 DeviceVref_Margin_A1==37
603 12:31:08.741368
604 12:31:08.741830 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 12:31:08.742283
606 12:31:08.774435 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000018 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 12:31:08.775021 2D training succeed
608 12:31:08.780025 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 12:31:08.785583 auto size-- 65535DDR cs0 size: 2048MB
610 12:31:08.786115 DDR cs1 size: 2048MB
611 12:31:08.791112 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 12:31:08.791659 cs0 DataBus test pass
613 12:31:08.796710 cs1 DataBus test pass
614 12:31:08.797247 cs0 AddrBus test pass
615 12:31:08.797711 cs1 AddrBus test pass
616 12:31:08.798158
617 12:31:08.802245 100bdlr_step_size ps== 420
618 12:31:08.802787 result report
619 12:31:08.807870 boot times 0Enable ddr reg access
620 12:31:08.813296 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 12:31:08.826737 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 12:31:09.400362 0.0;M3 CHK:0;cm4_sp_mode 0
623 12:31:09.400995 MVN_1=0x00000000
624 12:31:09.405877 MVN_2=0x00000000
625 12:31:09.411780 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 12:31:09.412397 OPS=0x10
627 12:31:09.412909 ring efuse init
628 12:31:09.413389 chipver efuse init
629 12:31:09.417299 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 12:31:09.422814 [0.018961 Inits done]
631 12:31:09.423294 secure task start!
632 12:31:09.423728 high task start!
633 12:31:09.426463 low task start!
634 12:31:09.426921 run into bl31
635 12:31:09.434079 NOTICE: BL31: v1.3(release):4fc40b1
636 12:31:09.441260 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 12:31:09.441808 NOTICE: BL31: G12A normal boot!
638 12:31:09.467233 NOTICE: BL31: BL33 decompress pass
639 12:31:09.472990 ERROR: Error initializing runtime service opteed_fast
640 12:31:10.751421
641 12:31:10.752166
642 12:31:10.753709 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 12:31:10.754251
644 12:31:10.754731 Model: Libre Computer AML-A311D-CC Alta
645 12:31:10.922652 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 12:31:10.945089 DRAM: 2 GiB (effective 3.8 GiB)
647 12:31:11.089074 Core: 408 devices, 31 uclasses, devicetree: separate
648 12:31:11.094924 WDT: Not starting watchdog@f0d0
649 12:31:11.127245 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 12:31:11.139595 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 12:31:11.143665 ** Bad device specification mmc 0 **
652 12:31:11.154958 Card did not respond to voltage select! : -110
653 12:31:11.162538 ** Bad device specification mmc 0 **
654 12:31:11.163087 Couldn't find partition mmc 0
655 12:31:11.170915 Card did not respond to voltage select! : -110
656 12:31:11.176398 ** Bad device specification mmc 0 **
657 12:31:11.176921 Couldn't find partition mmc 0
658 12:31:11.181452 Error: could not access storage.
659 12:31:11.523911 Net: eth0: ethernet@ff3f0000
660 12:31:11.524286 starting USB...
661 12:31:11.775712 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 12:31:11.776098 Starting the controller
663 12:31:11.782788 USB XHCI 1.10
664 12:31:13.496331 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 12:31:13.496965 bl2_stage_init 0x01
666 12:31:13.497401 bl2_stage_init 0x81
667 12:31:13.501706 hw id: 0x0000 - pwm id 0x01
668 12:31:13.502235 bl2_stage_init 0xc1
669 12:31:13.502703 bl2_stage_init 0x02
670 12:31:13.503138
671 12:31:13.507295 L0:00000000
672 12:31:13.507808 L1:20000703
673 12:31:13.508282 L2:00008067
674 12:31:13.508725 L3:14000000
675 12:31:13.512968 B2:00402000
676 12:31:13.513498 B1:e0f83180
677 12:31:13.513919
678 12:31:13.514329 TE: 58124
679 12:31:13.514735
680 12:31:13.518528 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 12:31:13.518990
682 12:31:13.519399 Board ID = 1
683 12:31:13.524191 Set A53 clk to 24M
684 12:31:13.524648 Set A73 clk to 24M
685 12:31:13.525055 Set clk81 to 24M
686 12:31:13.529724 A53 clk: 1200 MHz
687 12:31:13.530166 A73 clk: 1200 MHz
688 12:31:13.530568 CLK81: 166.6M
689 12:31:13.530966 smccc: 00012a92
690 12:31:13.535341 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 12:31:13.540881 board id: 1
692 12:31:13.546812 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 12:31:13.557585 fw parse done
694 12:31:13.563352 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 12:31:13.605119 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 12:31:13.617122 PIEI prepare done
697 12:31:13.617618 fastboot data load
698 12:31:13.618039 fastboot data verify
699 12:31:13.622659 verify result: 266
700 12:31:13.628244 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 12:31:13.628709 LPDDR4 probe
702 12:31:13.629120 ddr clk to 1584MHz
703 12:31:13.636317 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 12:31:13.672524
705 12:31:13.673159 dmc_version 0001
706 12:31:13.679315 Check phy result
707 12:31:13.686156 INFO : End of CA training
708 12:31:13.686715 INFO : End of initialization
709 12:31:13.691800 INFO : Training has run successfully!
710 12:31:13.692405 Check phy result
711 12:31:13.697252 INFO : End of initialization
712 12:31:13.697808 INFO : End of read enable training
713 12:31:13.700635 INFO : End of fine write leveling
714 12:31:13.706252 INFO : End of Write leveling coarse delay
715 12:31:13.711836 INFO : Training has run successfully!
716 12:31:13.712417 Check phy result
717 12:31:13.712889 INFO : End of initialization
718 12:31:13.717449 INFO : End of read dq deskew training
719 12:31:13.723046 INFO : End of MPR read delay center optimization
720 12:31:13.723596 INFO : End of write delay center optimization
721 12:31:13.728651 INFO : End of read delay center optimization
722 12:31:13.734243 INFO : End of max read latency training
723 12:31:13.734790 INFO : Training has run successfully!
724 12:31:13.739832 1D training succeed
725 12:31:13.744915 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 12:31:13.792543 Check phy result
727 12:31:13.793189 INFO : End of initialization
728 12:31:13.814636 INFO : End of 2D read delay Voltage center optimization
729 12:31:13.835670 INFO : End of 2D read delay Voltage center optimization
730 12:31:13.887303 INFO : End of 2D write delay Voltage center optimization
731 12:31:13.936718 INFO : End of 2D write delay Voltage center optimization
732 12:31:13.942032 INFO : Training has run successfully!
733 12:31:13.942495
734 12:31:13.942822 channel==0
735 12:31:13.947651 RxClkDly_Margin_A0==88 ps 9
736 12:31:13.948133 TxDqDly_Margin_A0==98 ps 10
737 12:31:13.950967 RxClkDly_Margin_A1==88 ps 9
738 12:31:13.951275 TxDqDly_Margin_A1==98 ps 10
739 12:31:13.956762 TrainedVREFDQ_A0==74
740 12:31:13.957225 TrainedVREFDQ_A1==74
741 12:31:13.962519 VrefDac_Margin_A0==25
742 12:31:13.963063 DeviceVref_Margin_A0==40
743 12:31:13.963525 VrefDac_Margin_A1==24
744 12:31:13.967819 DeviceVref_Margin_A1==40
745 12:31:13.968381
746 12:31:13.968850
747 12:31:13.969307 channel==1
748 12:31:13.969747 RxClkDly_Margin_A0==98 ps 10
749 12:31:13.971349 TxDqDly_Margin_A0==98 ps 10
750 12:31:13.976860 RxClkDly_Margin_A1==98 ps 10
751 12:31:13.977450 TxDqDly_Margin_A1==88 ps 9
752 12:31:13.977928 TrainedVREFDQ_A0==77
753 12:31:13.982388 TrainedVREFDQ_A1==77
754 12:31:13.982916 VrefDac_Margin_A0==22
755 12:31:13.988241 DeviceVref_Margin_A0==37
756 12:31:13.988756 VrefDac_Margin_A1==22
757 12:31:13.989219 DeviceVref_Margin_A1==37
758 12:31:13.989666
759 12:31:13.997007 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 12:31:13.997607
761 12:31:14.022876 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 12:31:14.028455 2D training succeed
763 12:31:14.031822 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 12:31:14.037338 auto size-- 65535DDR cs0 size: 2048MB
765 12:31:14.037862 DDR cs1 size: 2048MB
766 12:31:14.042916 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 12:31:14.043440 cs0 DataBus test pass
768 12:31:14.048514 cs1 DataBus test pass
769 12:31:14.049040 cs0 AddrBus test pass
770 12:31:14.049476 cs1 AddrBus test pass
771 12:31:14.049903
772 12:31:14.051959 100bdlr_step_size ps== 420
773 12:31:14.052532 result report
774 12:31:14.057551 boot times 0Enable ddr reg access
775 12:31:14.064239 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 12:31:14.077765 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 12:31:14.652128 0.0;M3 CHK:0;cm4_sp_mode 0
778 12:31:14.652533 MVN_1=0x00000000
779 12:31:14.657786 MVN_2=0x00000000
780 12:31:14.663598 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 12:31:14.663961 OPS=0x10
782 12:31:14.664243 ring efuse init
783 12:31:14.664461 chipver efuse init
784 12:31:14.671720 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 12:31:14.672098 [0.018960 Inits done]
786 12:31:14.678449 secure task start!
787 12:31:14.679006 high task start!
788 12:31:14.679561 low task start!
789 12:31:14.680070 run into bl31
790 12:31:14.685972 NOTICE: BL31: v1.3(release):4fc40b1
791 12:31:14.692763 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 12:31:14.693121 NOTICE: BL31: G12A normal boot!
793 12:31:14.719030 NOTICE: BL31: BL33 decompress pass
794 12:31:14.723847 ERROR: Error initializing runtime service opteed_fast
795 12:31:15.957696
796 12:31:15.958346
797 12:31:15.965141 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 12:31:15.965651
799 12:31:15.966099 Model: Libre Computer AML-A311D-CC Alta
800 12:31:16.173639 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 12:31:16.197961 DRAM: 2 GiB (effective 3.8 GiB)
802 12:31:16.340936 Core: 408 devices, 31 uclasses, devicetree: separate
803 12:31:16.346748 WDT: Not starting watchdog@f0d0
804 12:31:16.379017 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 12:31:16.391597 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 12:31:16.396504 ** Bad device specification mmc 0 **
807 12:31:16.406910 Card did not respond to voltage select! : -110
808 12:31:16.414536 ** Bad device specification mmc 0 **
809 12:31:16.415124 Couldn't find partition mmc 0
810 12:31:16.422895 Card did not respond to voltage select! : -110
811 12:31:16.428318 ** Bad device specification mmc 0 **
812 12:31:16.428906 Couldn't find partition mmc 0
813 12:31:16.433366 Error: could not access storage.
814 12:31:16.775920 Net: eth0: ethernet@ff3f0000
815 12:31:16.776627 starting USB...
816 12:31:17.027645 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 12:31:17.028068 Starting the controller
818 12:31:17.034545 USB XHCI 1.10
819 12:31:19.194717 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 12:31:19.195391 bl2_stage_init 0x01
821 12:31:19.195936 bl2_stage_init 0x81
822 12:31:19.200398 hw id: 0x0000 - pwm id 0x01
823 12:31:19.201027 bl2_stage_init 0xc1
824 12:31:19.201597 bl2_stage_init 0x02
825 12:31:19.202101
826 12:31:19.205955 L0:00000000
827 12:31:19.206495 L1:20000703
828 12:31:19.206968 L2:00008067
829 12:31:19.207428 L3:14000000
830 12:31:19.211501 B2:00402000
831 12:31:19.212180 B1:e0f83180
832 12:31:19.212666
833 12:31:19.213122 TE: 58124
834 12:31:19.213570
835 12:31:19.217036 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 12:31:19.217636
837 12:31:19.218122 Board ID = 1
838 12:31:19.222637 Set A53 clk to 24M
839 12:31:19.223247 Set A73 clk to 24M
840 12:31:19.223739 Set clk81 to 24M
841 12:31:19.228431 A53 clk: 1200 MHz
842 12:31:19.228961 A73 clk: 1200 MHz
843 12:31:19.229401 CLK81: 166.6M
844 12:31:19.229952 smccc: 00012a91
845 12:31:19.233926 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 12:31:19.239498 board id: 1
847 12:31:19.246093 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 12:31:19.257324 fw parse done
849 12:31:19.260979 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 12:31:19.304715 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 12:31:19.315435 PIEI prepare done
852 12:31:19.316034 fastboot data load
853 12:31:19.316484 fastboot data verify
854 12:31:19.321125 verify result: 266
855 12:31:19.326822 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 12:31:19.327437 LPDDR4 probe
857 12:31:19.327897 ddr clk to 1584MHz
858 12:31:19.334667 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 12:31:19.372024
860 12:31:19.372699 dmc_version 0001
861 12:31:19.383024 Check phy result
862 12:31:19.383608 INFO : End of CA training
863 12:31:19.388478 INFO : End of initialization
864 12:31:19.389089 INFO : Training has run successfully!
865 12:31:19.394048 Check phy result
866 12:31:19.394644 INFO : End of initialization
867 12:31:19.399647 INFO : End of read enable training
868 12:31:19.400299 INFO : End of fine write leveling
869 12:31:19.405188 INFO : End of Write leveling coarse delay
870 12:31:19.405711 INFO : Training has run successfully!
871 12:31:19.410811 Check phy result
872 12:31:19.411328 INFO : End of initialization
873 12:31:19.416422 INFO : End of read dq deskew training
874 12:31:19.422011 INFO : End of MPR read delay center optimization
875 12:31:19.422529 INFO : End of write delay center optimization
876 12:31:19.427674 INFO : End of read delay center optimization
877 12:31:19.433229 INFO : End of max read latency training
878 12:31:19.433817 INFO : Training has run successfully!
879 12:31:19.438806 1D training succeed
880 12:31:19.444123 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 12:31:19.491678 Check phy result
882 12:31:19.492416 INFO : End of initialization
883 12:31:19.514195 INFO : End of 2D read delay Voltage center optimization
884 12:31:19.533199 INFO : End of 2D read delay Voltage center optimization
885 12:31:19.586242 INFO : End of 2D write delay Voltage center optimization
886 12:31:19.635541 INFO : End of 2D write delay Voltage center optimization
887 12:31:19.640949 INFO : Training has run successfully!
888 12:31:19.641474
889 12:31:19.641923 channel==0
890 12:31:19.646535 RxClkDly_Margin_A0==88 ps 9
891 12:31:19.647125 TxDqDly_Margin_A0==98 ps 10
892 12:31:19.652247 RxClkDly_Margin_A1==88 ps 9
893 12:31:19.652771 TxDqDly_Margin_A1==88 ps 9
894 12:31:19.653311 TrainedVREFDQ_A0==74
895 12:31:19.657750 TrainedVREFDQ_A1==74
896 12:31:19.658266 VrefDac_Margin_A0==25
897 12:31:19.658794 DeviceVref_Margin_A0==40
898 12:31:19.663448 VrefDac_Margin_A1==25
899 12:31:19.663962 DeviceVref_Margin_A1==40
900 12:31:19.664443
901 12:31:19.664877
902 12:31:19.665306 channel==1
903 12:31:19.668941 RxClkDly_Margin_A0==98 ps 10
904 12:31:19.669456 TxDqDly_Margin_A0==98 ps 10
905 12:31:19.674547 RxClkDly_Margin_A1==98 ps 10
906 12:31:19.675123 TxDqDly_Margin_A1==88 ps 9
907 12:31:19.680157 TrainedVREFDQ_A0==77
908 12:31:19.680674 TrainedVREFDQ_A1==77
909 12:31:19.681202 VrefDac_Margin_A0==22
910 12:31:19.685697 DeviceVref_Margin_A0==37
911 12:31:19.686268 VrefDac_Margin_A1==22
912 12:31:19.691419 DeviceVref_Margin_A1==37
913 12:31:19.691924
914 12:31:19.692403 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 12:31:19.692837
916 12:31:19.725006 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 12:31:19.725704 2D training succeed
918 12:31:19.730522 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 12:31:19.736124 auto size-- 65535DDR cs0 size: 2048MB
920 12:31:19.736659 DDR cs1 size: 2048MB
921 12:31:19.741710 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 12:31:19.742232 cs0 DataBus test pass
923 12:31:19.747545 cs1 DataBus test pass
924 12:31:19.748091 cs0 AddrBus test pass
925 12:31:19.748534 cs1 AddrBus test pass
926 12:31:19.748959
927 12:31:19.752865 100bdlr_step_size ps== 420
928 12:31:19.753463 result report
929 12:31:19.758550 boot times 0Enable ddr reg access
930 12:31:19.763873 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 12:31:19.777356 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 12:31:20.349350 0.0;M3 CHK:0;cm4_sp_mode 0
933 12:31:20.350020 MVN_1=0x00000000
934 12:31:20.354820 MVN_2=0x00000000
935 12:31:20.360644 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 12:31:20.361197 OPS=0x10
937 12:31:20.361744 ring efuse init
938 12:31:20.362188 chipver efuse init
939 12:31:20.366179 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 12:31:20.371745 [0.018961 Inits done]
941 12:31:20.372315 secure task start!
942 12:31:20.372762 high task start!
943 12:31:20.375417 low task start!
944 12:31:20.375910 run into bl31
945 12:31:20.383019 NOTICE: BL31: v1.3(release):4fc40b1
946 12:31:20.390813 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 12:31:20.391403 NOTICE: BL31: G12A normal boot!
948 12:31:20.416223 NOTICE: BL31: BL33 decompress pass
949 12:31:20.421827 ERROR: Error initializing runtime service opteed_fast
950 12:31:21.654758
951 12:31:21.655475
952 12:31:21.663101 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 12:31:21.663637
954 12:31:21.664246 Model: Libre Computer AML-A311D-CC Alta
955 12:31:21.871774 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 12:31:21.894895 DRAM: 2 GiB (effective 3.8 GiB)
957 12:31:22.038027 Core: 408 devices, 31 uclasses, devicetree: separate
958 12:31:22.043755 WDT: Not starting watchdog@f0d0
959 12:31:22.076128 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 12:31:22.088529 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 12:31:22.093469 ** Bad device specification mmc 0 **
962 12:31:22.103790 Card did not respond to voltage select! : -110
963 12:31:22.111482 ** Bad device specification mmc 0 **
964 12:31:22.111812 Couldn't find partition mmc 0
965 12:31:22.119790 Card did not respond to voltage select! : -110
966 12:31:22.125285 ** Bad device specification mmc 0 **
967 12:31:22.125577 Couldn't find partition mmc 0
968 12:31:22.130357 Error: could not access storage.
969 12:31:22.472976 Net: eth0: ethernet@ff3f0000
970 12:31:22.473647 starting USB...
971 12:31:22.724676 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 12:31:22.725321 Starting the controller
973 12:31:22.731618 USB XHCI 1.10
974 12:31:24.285734 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 12:31:24.294115 scanning usb for storage devices... 0 Storage Device(s) found
977 12:31:24.345743 Hit any key to stop autoboot: 1
978 12:31:24.346355 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
979 12:31:24.346706 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
980 12:31:24.346960 Setting prompt string to ['=>']
981 12:31:24.347212 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
982 12:31:24.361802 0
983 12:31:24.362816 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 12:31:24.363347 Sending with 10 millisecond of delay
986 12:31:25.498978 => setenv autoload no
987 12:31:25.509870 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
988 12:31:25.701120 setenv autoload no
989 12:31:25.702080 Sending with 10 millisecond of delay
991 12:31:27.500569 => setenv initrd_high 0xffffffff
992 12:31:27.511387 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
993 12:31:27.512348 setenv initrd_high 0xffffffff
994 12:31:27.513065 Sending with 10 millisecond of delay
996 12:31:29.132199 => setenv fdt_high 0xffffffff
997 12:31:29.143042 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
998 12:31:29.143535 setenv fdt_high 0xffffffff
999 12:31:29.144012 Sending with 10 millisecond of delay
1001 12:31:29.435479 => dhcp
1002 12:31:29.446087 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1003 12:31:29.449602 dhcp
1004 12:31:29.449863 Speed: 1000, full duplex
1005 12:31:29.450072 BOOTP broadcast 1
1006 12:31:29.607519 DHCP client bound to address 192.168.6.33 (162 ms)
1007 12:31:29.608124 Sending with 10 millisecond of delay
1009 12:31:31.284252 => setenv serverip 192.168.6.2
1010 12:31:31.295674 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1011 12:31:31.296366 setenv serverip 192.168.6.2
1012 12:31:31.296840 Sending with 10 millisecond of delay
1014 12:31:35.040572 => tftpboot 0x01080000 826935/tftp-deploy-xv3srcgq/kernel/uImage
1015 12:31:35.051382 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1016 12:31:35.052290 tftpboot 0x01080000 826935/tftp-deploy-xv3srcgq/kernel/uImage
1017 12:31:35.052747 Speed: 1000, full duplex
1018 12:31:35.053163 Using ethernet@ff3f0000 device
1019 12:31:35.054047 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1020 12:31:35.059712 Filename '826935/tftp-deploy-xv3srcgq/kernel/uImage'.
1021 12:31:35.063655 Load address: 0x1080000
1022 12:31:38.549290 Loading: *################################################## 43.6 MiB
1023 12:31:38.549972 12.5 MiB/s
1024 12:31:38.550473 done
1025 12:31:38.553788 Bytes transferred = 45713984 (2b98a40 hex)
1026 12:31:38.554634 Sending with 10 millisecond of delay
1028 12:31:43.244568 => tftpboot 0x08000000 826935/tftp-deploy-xv3srcgq/ramdisk/ramdisk.cpio.gz.uboot
1029 12:31:43.255400 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
1030 12:31:43.256315 tftpboot 0x08000000 826935/tftp-deploy-xv3srcgq/ramdisk/ramdisk.cpio.gz.uboot
1031 12:31:43.256767 Speed: 1000, full duplex
1032 12:31:43.257187 Using ethernet@ff3f0000 device
1033 12:31:43.258111 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1034 12:31:43.270044 Filename '826935/tftp-deploy-xv3srcgq/ramdisk/ramdisk.cpio.gz.uboot'.
1035 12:31:43.270556 Load address: 0x8000000
1036 12:31:50.224323 Loading: *T ################################################## 22.3 MiB
1037 12:31:50.224771 3.2 MiB/s
1038 12:31:50.225020 done
1039 12:31:50.228236 Bytes transferred = 23425228 (16570cc hex)
1040 12:31:50.228968 Sending with 10 millisecond of delay
1042 12:31:55.422029 => tftpboot 0x01070000 826935/tftp-deploy-xv3srcgq/dtb/meson-g12b-a311d-libretech-cc.dtb
1043 12:31:55.432875 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:57)
1044 12:31:55.433810 tftpboot 0x01070000 826935/tftp-deploy-xv3srcgq/dtb/meson-g12b-a311d-libretech-cc.dtb
1045 12:31:55.434330 Speed: 1000, full duplex
1046 12:31:55.434791 Using ethernet@ff3f0000 device
1047 12:31:55.438295 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1048 12:31:55.445950 Filename '826935/tftp-deploy-xv3srcgq/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1049 12:31:55.457620 Load address: 0x1070000
1050 12:31:55.469519 Loading: *################################################## 53.4 KiB
1051 12:31:55.470063 2.9 MiB/s
1052 12:31:55.470520 done
1053 12:31:55.473759 Bytes transferred = 54703 (d5af hex)
1054 12:31:55.474550 Sending with 10 millisecond of delay
1056 12:32:08.774595 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/826935/extract-nfsrootfs-f0ktqxdm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1057 12:32:08.785867 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:44)
1058 12:32:08.786537 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/826935/extract-nfsrootfs-f0ktqxdm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1059 12:32:08.787022 Sending with 10 millisecond of delay
1061 12:32:11.127355 => bootm 0x01080000 0x08000000 0x01070000
1062 12:32:11.138198 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1063 12:32:11.138747 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:41)
1064 12:32:11.139723 bootm 0x01080000 0x08000000 0x01070000
1065 12:32:11.140198 ## Booting kernel from Legacy Image at 01080000 ...
1066 12:32:11.143629 Image Name:
1067 12:32:11.149017 Image Type: AArch64 Linux Kernel Image (uncompressed)
1068 12:32:11.149486 Data Size: 45713920 Bytes = 43.6 MiB
1069 12:32:11.154294 Load Address: 01080000
1070 12:32:11.154754 Entry Point: 01080000
1071 12:32:11.349845 Verifying Checksum ... OK
1072 12:32:11.350246 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1073 12:32:11.355091 Image Name:
1074 12:32:11.360688 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1075 12:32:11.360957 Data Size: 23425164 Bytes = 22.3 MiB
1076 12:32:11.366498 Load Address: 00000000
1077 12:32:11.366769 Entry Point: 00000000
1078 12:32:11.468065 Verifying Checksum ... OK
1079 12:32:11.468451 ## Flattened Device Tree blob at 01070000
1080 12:32:11.473445 Booting using the fdt blob at 0x1070000
1081 12:32:11.473858 Working FDT set to 1070000
1082 12:32:11.478088 Loading Kernel Image
1083 12:32:11.629434 Loading Ramdisk to 7e9a8000, end 7ffff08c ... OK
1084 12:32:11.637672 Loading Device Tree to 000000007e997000, end 000000007e9a75ae ... OK
1085 12:32:11.637974 Working FDT set to 7e997000
1086 12:32:11.638190
1087 12:32:11.638827 end: 2.4.3 bootloader-commands (duration 00:00:47) [common]
1088 12:32:11.639269 start: 2.4.4 auto-login-action (timeout 00:03:41) [common]
1089 12:32:11.639632 Setting prompt string to ['Linux version [0-9]']
1090 12:32:11.639977 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1091 12:32:11.640366 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1092 12:32:11.641050 Starting kernel ...
1093 12:32:11.641318
1094 12:32:11.678095 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1095 12:32:11.679105 start: 2.4.4.1 login-action (timeout 00:03:41) [common]
1096 12:32:11.679623 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1097 12:32:11.680112 Setting prompt string to []
1098 12:32:11.680600 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1099 12:32:11.681054 Using line separator: #'\n'#
1100 12:32:11.681459 No login prompt set.
1101 12:32:11.681890 Parsing kernel messages
1102 12:32:11.682285 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1103 12:32:11.683069 [login-action] Waiting for messages, (timeout 00:03:41)
1104 12:32:11.683519 Waiting using forced prompt support (timeout 00:01:50)
1105 12:32:11.694601 [ 0.000000] Linux version 6.12.0-rc1 (KernelCI@build-j338553-arm64-gcc-12-defconfig-9xtmt) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Oct 9 11:51:54 UTC 2024
1106 12:32:11.700107 [ 0.000000] KASLR disabled due to lack of seed
1107 12:32:11.705578 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1108 12:32:11.711175 [ 0.000000] efi: UEFI not found.
1109 12:32:11.716785 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1110 12:32:11.722193 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1111 12:32:11.733169 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1112 12:32:11.744306 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1113 12:32:11.749654 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1114 12:32:11.760691 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1115 12:32:11.771697 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1116 12:32:11.777254 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1117 12:32:11.782743 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1118 12:32:11.788274 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1119 12:32:11.788721 [ 0.000000] Zone ranges:
1120 12:32:11.793820 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1121 12:32:11.799340 [ 0.000000] DMA32 empty
1122 12:32:11.799784 [ 0.000000] Normal empty
1123 12:32:11.804853 [ 0.000000] Movable zone start for each node
1124 12:32:11.810493 [ 0.000000] Early memory node ranges
1125 12:32:11.815872 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1126 12:32:11.821410 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1127 12:32:11.826911 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1128 12:32:11.832458 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1129 12:32:11.859896 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1130 12:32:11.865387 [ 0.000000] psci: probing for conduit method from DT.
1131 12:32:11.865832 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1132 12:32:11.870864 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1133 12:32:11.876432 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1134 12:32:11.881904 [ 0.000000] psci: SMC Calling Convention v1.1
1135 12:32:11.887432 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1136 12:32:11.892957 [ 0.000000] Detected VIPT I-cache on CPU0
1137 12:32:11.898462 [ 0.000000] CPU features: detected: ARM erratum 845719
1138 12:32:11.903968 [ 0.000000] alternatives: applying boot alternatives
1139 12:32:11.920522 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/826935/extract-nfsrootfs-f0ktqxdm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1140 12:32:11.931575 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1141 12:32:11.937185 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1142 12:32:11.942630 <6>[ 0.000000] Fallback order for Node 0: 0
1143 12:32:11.948242 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1144 12:32:11.953643 <6>[ 0.000000] Policy zone: DMA
1145 12:32:11.959203 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1146 12:32:11.964697 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1147 12:32:11.970288 <6>[ 0.000000] software IO TLB: area num 8.
1148 12:32:11.979272 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1149 12:32:12.025886 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1150 12:32:12.031454 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1151 12:32:12.036924 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1152 12:32:12.042500 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1153 12:32:12.048022 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1154 12:32:12.053504 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1155 12:32:12.059016 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1156 12:32:12.064528 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1157 12:32:12.075573 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1158 12:32:12.086595 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1159 12:32:12.092228 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1160 12:32:12.097675 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1161 12:32:12.098115 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1162 12:32:12.107508 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1163 12:32:12.120221 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1164 12:32:12.131219 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1165 12:32:12.136720 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1166 12:32:12.142248 <6>[ 0.008794] Console: colour dummy device 80x25
1167 12:32:12.153327 <6>[ 0.012939] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1168 12:32:12.158815 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1169 12:32:12.164344 <6>[ 0.028188] LSM: initializing lsm=capability
1170 12:32:12.169850 <6>[ 0.032732] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1171 12:32:12.175357 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 12:32:12.180908 <6>[ 0.052298] rcu: Hierarchical SRCU implementation.
1173 12:32:12.186409 <6>[ 0.053214] rcu: Max phase no-delay instances is 1000.
1174 12:32:12.197461 <6>[ 0.058883] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1175 12:32:12.202984 <6>[ 0.071562] EFI services will not be available.
1176 12:32:12.203436 <6>[ 0.072090] smp: Bringing up secondary CPUs ...
1177 12:32:12.208495 <6>[ 0.077154] Detected VIPT I-cache on CPU1
1178 12:32:12.214059 <6>[ 0.077274] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1179 12:32:12.219534 <6>[ 0.078617] CPU features: detected: Spectre-v2
1180 12:32:12.225108 <6>[ 0.078632] CPU features: detected: Spectre-v4
1181 12:32:12.230587 <6>[ 0.078636] CPU features: detected: Spectre-BHB
1182 12:32:12.236153 <6>[ 0.078642] CPU features: detected: ARM erratum 858921
1183 12:32:12.241633 <6>[ 0.078650] Detected VIPT I-cache on CPU2
1184 12:32:12.247265 <6>[ 0.078724] arch_timer: Enabling local workaround for ARM erratum 858921
1185 12:32:12.252676 <6>[ 0.078741] arch_timer: CPU2: Trapping CNTVCT access
1186 12:32:12.258265 <6>[ 0.078751] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1187 12:32:12.263703 <6>[ 0.079509] Detected VIPT I-cache on CPU3
1188 12:32:12.269252 <6>[ 0.079554] arch_timer: Enabling local workaround for ARM erratum 858921
1189 12:32:12.274784 <6>[ 0.079564] arch_timer: CPU3: Trapping CNTVCT access
1190 12:32:12.280283 <6>[ 0.079571] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1191 12:32:12.285761 <6>[ 0.080273] Detected VIPT I-cache on CPU4
1192 12:32:12.291264 <6>[ 0.080320] arch_timer: Enabling local workaround for ARM erratum 858921
1193 12:32:12.296808 <6>[ 0.080329] arch_timer: CPU4: Trapping CNTVCT access
1194 12:32:12.302329 <6>[ 0.080336] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1195 12:32:12.307825 <6>[ 0.081106] Detected VIPT I-cache on CPU5
1196 12:32:12.313369 <6>[ 0.081153] arch_timer: Enabling local workaround for ARM erratum 858921
1197 12:32:12.318882 <6>[ 0.081163] arch_timer: CPU5: Trapping CNTVCT access
1198 12:32:12.329914 <6>[ 0.081170] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1199 12:32:12.330240 <6>[ 0.081290] smp: Brought up 1 node, 6 CPUs
1200 12:32:12.335464 <6>[ 0.203224] SMP: Total of 6 processors activated.
1201 12:32:12.340944 <6>[ 0.208130] CPU: All CPU(s) started at EL2
1202 12:32:12.346495 <6>[ 0.212472] CPU features: detected: 32-bit EL0 Support
1203 12:32:12.352015 <6>[ 0.217788] CPU features: detected: 32-bit EL1 Support
1204 12:32:12.357526 <6>[ 0.223148] CPU features: detected: CRC32 instructions
1205 12:32:12.363080 <6>[ 0.228539] alternatives: applying system-wide alternatives
1206 12:32:12.380990 <6>[ 0.235835] Memory: 3557440K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187792K reserved, 262144K cma-reserved)
1207 12:32:12.381675 <6>[ 0.250066] devtmpfs: initialized
1208 12:32:12.392044 <6>[ 0.259194] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1209 12:32:12.397568 <6>[ 0.263553] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1210 12:32:12.403054 <6>[ 0.274352] 21392 pages in range for non-PLT usage
1211 12:32:12.408566 <6>[ 0.274363] 512912 pages in range for PLT usage
1212 12:32:12.414165 <6>[ 0.275904] pinctrl core: initialized pinctrl subsystem
1213 12:32:12.419618 <6>[ 0.287962] DMI not present or invalid.
1214 12:32:12.425159 <6>[ 0.292274] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1215 12:32:12.430661 <6>[ 0.297015] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1216 12:32:12.441678 <6>[ 0.303788] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1217 12:32:12.447303 <6>[ 0.311888] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1218 12:32:12.452822 <6>[ 0.319385] audit: initializing netlink subsys (disabled)
1219 12:32:12.463778 <5>[ 0.325134] audit: type=2000 audit(0.244:1): state=initialized audit_enabled=0 res=1
1220 12:32:12.469317 <6>[ 0.326602] thermal_sys: Registered thermal governor 'step_wise'
1221 12:32:12.474807 <6>[ 0.332895] thermal_sys: Registered thermal governor 'power_allocator'
1222 12:32:12.480327 <6>[ 0.339151] cpuidle: using governor menu
1223 12:32:12.485840 <6>[ 0.350131] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1224 12:32:12.491386 <6>[ 0.357067] ASID allocator initialised with 65536 entries
1225 12:32:12.499665 <6>[ 0.364585] Serial: AMBA PL011 UART driver
1226 12:32:12.507386 <6>[ 0.375199] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1227 12:32:12.522480 <6>[ 0.390627] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 12:32:12.533554 <6>[ 0.393296] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1229 12:32:12.539058 <6>[ 0.406426] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1230 12:32:12.544572 <6>[ 0.409668] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1231 12:32:12.555608 <6>[ 0.418091] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1232 12:32:12.561188 <6>[ 0.425716] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1233 12:32:12.572172 <6>[ 0.439275] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1234 12:32:12.577716 <6>[ 0.441536] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1235 12:32:12.583317 <6>[ 0.448018] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1236 12:32:12.588710 <6>[ 0.454995] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1237 12:32:12.599764 <6>[ 0.461464] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1238 12:32:12.605298 <6>[ 0.468450] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1239 12:32:12.610798 <6>[ 0.474919] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1240 12:32:12.616360 <6>[ 0.481903] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1241 12:32:12.621843 <6>[ 0.489908] ACPI: Interpreter disabled.
1242 12:32:12.627360 <6>[ 0.495346] iommu: Default domain type: Translated
1243 12:32:12.632917 <6>[ 0.497437] iommu: DMA domain TLB invalidation policy: strict mode
1244 12:32:12.638443 <5>[ 0.504119] SCSI subsystem initialized
1245 12:32:12.643943 <6>[ 0.508015] usbcore: registered new interface driver usbfs
1246 12:32:12.649443 <6>[ 0.513498] usbcore: registered new interface driver hub
1247 12:32:12.654943 <6>[ 0.519011] usbcore: registered new device driver usb
1248 12:32:12.660494 <6>[ 0.525285] pps_core: LinuxPPS API ver. 1 registered
1249 12:32:12.666004 <6>[ 0.529431] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1250 12:32:12.671519 <6>[ 0.538750] PTP clock support registered
1251 12:32:12.677051 <6>[ 0.542992] EDAC MC: Ver: 3.0.0
1252 12:32:12.682590 <6>[ 0.546624] scmi_core: SCMI protocol bus registered
1253 12:32:12.683162 <6>[ 0.552239] FPGA manager framework
1254 12:32:12.688097 <6>[ 0.555012] Advanced Linux Sound Architecture Driver Initialized.
1255 12:32:12.693625 <6>[ 0.561953] vgaarb: loaded
1256 12:32:12.699232 <6>[ 0.564484] clocksource: Switched to clocksource arch_sys_counter
1257 12:32:12.704657 <5>[ 0.570815] VFS: Disk quotas dquot_6.6.0
1258 12:32:12.710184 <6>[ 0.574643] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1259 12:32:12.715690 <6>[ 0.581856] pnp: PnP ACPI: disabled
1260 12:32:12.721330 <6>[ 0.590295] NET: Registered PF_INET protocol family
1261 12:32:12.726724 <6>[ 0.590677] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1262 12:32:12.737766 <6>[ 0.600842] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1263 12:32:12.743314 <6>[ 0.606844] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1264 12:32:12.754355 <6>[ 0.614745] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1265 12:32:12.759843 <6>[ 0.622978] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1266 12:32:12.765361 <6>[ 0.630777] TCP: Hash tables configured (established 32768 bind 32768)
1267 12:32:12.770872 <6>[ 0.637251] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1268 12:32:12.781919 <6>[ 0.644102] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 12:32:12.787455 <6>[ 0.651521] NET: Registered PF_UNIX/PF_LOCAL protocol family
1270 12:32:12.793042 <6>[ 0.657631] RPC: Registered named UNIX socket transport module.
1271 12:32:12.798506 <6>[ 0.663389] RPC: Registered udp transport module.
1272 12:32:12.804028 <6>[ 0.668294] RPC: Registered tcp transport module.
1273 12:32:12.809523 <6>[ 0.673208] RPC: Registered tcp-with-tls transport module.
1274 12:32:12.815071 <6>[ 0.678901] RPC: Registered tcp NFSv4.1 backchannel transport module.
1275 12:32:12.820829 <6>[ 0.685549] PCI: CLS 0 bytes, default 64
1276 12:32:12.821476 <6>[ 0.689868] Unpacking initramfs...
1277 12:32:12.826351 <6>[ 0.699127] kvm [1]: nv: 554 coarse grained trap handlers
1278 12:32:12.831817 <6>[ 0.699438] kvm [1]: IPA Size Limit: 40 bits
1279 12:32:12.837357 <6>[ 0.705106] kvm [1]: vgic interrupt IRQ9
1280 12:32:12.842854 <6>[ 0.707799] kvm [1]: Hyp nVHE mode initialized successfully
1281 12:32:12.848435 <5>[ 0.714941] Initialise system trusted keyrings
1282 12:32:12.853936 <6>[ 0.718433] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1283 12:32:12.859471 <6>[ 0.725113] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1284 12:32:12.864994 <5>[ 0.731151] NFS: Registering the id_resolver key type
1285 12:32:12.870538 <5>[ 0.736192] Key type id_resolver registered
1286 12:32:12.876036 <5>[ 0.740556] Key type id_legacy registered
1287 12:32:12.881541 <6>[ 0.744807] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1288 12:32:12.887065 <6>[ 0.751681] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1289 12:32:12.894526 <6>[ 0.759462] 9p: Installing v9fs 9p2000 file system support
1290 12:32:12.932255 <5>[ 0.805736] Key type asymmetric registered
1291 12:32:12.937642 <5>[ 0.805776] Asymmetric key parser 'x509' registered
1292 12:32:12.948677 <6>[ 0.809641] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1293 12:32:12.949352 <6>[ 0.817161] io scheduler mq-deadline registered
1294 12:32:12.954236 <6>[ 0.821899] io scheduler kyber registered
1295 12:32:12.959684 <6>[ 0.826163] io scheduler bfq registered
1296 12:32:12.966152 <6>[ 0.832058] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1297 12:32:12.982428 <6>[ 0.852320] ledtrig-cpu: registered to indicate activity on CPUs
1298 12:32:13.015080 <6>[ 0.883740] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1299 12:32:13.034799 <6>[ 0.897200] Serial: 8250/16550 driver, 4 ports<6>[ 0.901803] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1300 12:32:13.040373 <6>[ 0.911423] printk: legacy console [ttyAML0] enabled
1301 12:32:13.045849 <6>[ 0.911423] printk: legacy console [ttyAML0] enabled
1302 12:32:13.051453 <6>[ 0.916227] printk: legacy bootconsole [meson0] disabled
1303 12:32:13.056948 <6>[ 0.916227] printk: legacy bootconsole [meson0] disabled
1304 12:32:13.062493 <6>[ 0.929331] msm_serial: driver initialized
1305 12:32:13.068063 <6>[ 0.932165] SuperH (H)SCI(F) driver initialized
1306 12:32:13.068668 <6>[ 0.936701] STM32 USART driver initialized
1307 12:32:13.073594 <5>[ 0.942876] random: crng init done
1308 12:32:13.080621 <6>[ 0.948543] loop: module loaded
1309 12:32:13.081224 <6>[ 0.949825] megasas: 07.727.03.00-rc1
1310 12:32:13.086188 <6>[ 0.958753] tun: Universal TUN/TAP device driver, 1.6
1311 12:32:13.091738 <6>[ 0.959934] thunder_xcv, ver 1.0
1312 12:32:13.097262 <6>[ 0.961946] thunder_bgx, ver 1.0
1313 12:32:13.097885 <6>[ 0.965404] nicpf, ver 1.0
1314 12:32:13.102821 <6>[ 0.970007] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1315 12:32:13.108416 <6>[ 0.975777] hns3: Copyright (c) 2017 Huawei Corporation.
1316 12:32:13.113908 <6>[ 0.981365] hclge is initializing
1317 12:32:13.119506 <6>[ 0.984906] e1000: Intel(R) PRO/1000 Network Driver
1318 12:32:13.125038 <6>[ 0.989985] e1000: Copyright (c) 1999-2006 Intel Corporation.
1319 12:32:13.130521 <6>[ 0.996009] e1000e: Intel(R) PRO/1000 Network Driver
1320 12:32:13.136090 <6>[ 1.001166] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1321 12:32:13.141636 <6>[ 1.007349] igb: Intel(R) Gigabit Ethernet Network Driver
1322 12:32:13.147175 <6>[ 1.012952] igb: Copyright (c) 2007-2014 Intel Corporation.
1323 12:32:13.152726 <6>[ 1.018804] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1324 12:32:13.158386 <6>[ 1.025259] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1325 12:32:13.163834 <6>[ 1.032029] sky2: driver version 1.30
1326 12:32:13.169456 <6>[ 1.037160] VFIO - User Level meta-driver version: 0.3
1327 12:32:13.174934 <6>[ 1.044669] usbcore: registered new interface driver usb-storage
1328 12:32:13.180959 <6>[ 1.050927] i2c_dev: i2c /dev entries driver
1329 12:32:13.193781 <6>[ 1.061849] sdhci: Secure Digital Host Controller Interface driver
1330 12:32:13.194386 <6>[ 1.062649] sdhci: Copyright(c) Pierre Ossman
1331 12:32:13.204850 <6>[ 1.068318] Synopsys Designware Multimedia Card Interface Driver
1332 12:32:13.210503 <6>[ 1.074891] sdhci-pltfm: SDHCI platform and OF driver helper
1333 12:32:13.211099 <6>[ 1.082581] meson-sm: secure-monitor enabled
1334 12:32:13.223270 <6>[ 1.085145] usbcore: registered new interface driver usbhid
1335 12:32:13.223868 <6>[ 1.089707] usbhid: USB HID core driver
1336 12:32:13.231001 <6>[ 1.104570] NET: Registered PF_PACKET protocol family
1337 12:32:13.236462 <6>[ 1.104666] 9pnet: Installing 9P2000 support
1338 12:32:13.243582 <5>[ 1.108825] Key type dns_resolver registered
1339 12:32:13.251023 <6>[ 1.120406] registered taskstats version 1
1340 12:32:13.251615 <5>[ 1.120580] Loading compiled-in X.509 certificates
1341 12:32:13.258283 <6>[ 1.129218] Demotion targets for Node 0: null
1342 12:32:13.298687 <6>[ 1.172158] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1343 12:32:13.304111 <6>[ 1.172202] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1344 12:32:13.315181 <4>[ 1.182377] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1345 12:32:13.320732 <4>[ 1.184972] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1346 12:32:13.326279 <6>[ 1.192532] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1347 12:32:13.331822 <6>[ 1.201810] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1348 12:32:13.342885 <6>[ 1.205233] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1349 12:32:13.353995 <6>[ 1.213229] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1350 12:32:13.359574 <6>[ 1.222756] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1351 12:32:13.365087 <6>[ 1.228993] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1352 12:32:13.370630 <6>[ 1.234604] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1353 12:32:13.376169 <6>[ 1.242492] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1354 12:32:13.381699 <6>[ 1.249768] hub 1-0:1.0: USB hub found
1355 12:32:13.387272 <6>[ 1.253255] hub 1-0:1.0: 2 ports detected
1356 12:32:13.392820 <6>[ 1.259269] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1357 12:32:13.398433 <6>[ 1.266233] hub 2-0:1.0: USB hub found
1358 12:32:13.403484 <6>[ 1.269805] hub 2-0:1.0: 1 port detected
1359 12:32:13.427420 <6>[ 1.298407] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1360 12:32:13.438344 <6>[ 1.308662] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1361 12:32:13.473501 <6>[ 1.343396] Trying to probe devices needed for running init ...
1362 12:32:13.639218 <6>[ 1.508521] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1363 12:32:13.783817 <6>[ 1.651884] mmc0: new ultra high speed SDR104 SDXC card at address e624
1364 12:32:13.789352 <6>[ 1.653748] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1365 12:32:13.789862 <6>[ 1.657429] Freeing initrd memory: 22876K
1366 12:32:13.793306 <6>[ 1.659362] mmcblk0: p1
1367 12:32:13.824076 <6>[ 1.697596] hub 1-1:1.0: USB hub found
1368 12:32:13.829732 <6>[ 1.697908] hub 1-1:1.0: 4 ports detected
1369 12:32:13.899301 <6>[ 1.768623] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1370 12:32:13.936665 <6>[ 1.810258] hub 2-1:1.0: USB hub found
1371 12:32:13.942404 <6>[ 1.811079] hub 2-1:1.0: 4 ports detected
1372 12:32:25.743362 <6>[ 13.616595] clk: Disabling unused clocks
1373 12:32:25.748679 <6>[ 13.616834] PM: genpd: Disabling unused power domains
1374 12:32:25.756959 <6>[ 13.620497] ALSA device list:
1375 12:32:25.757430 <6>[ 13.623641] No soundcards found.
1376 12:32:25.763797 <6>[ 13.637284] Freeing unused kernel memory: 10432K
1377 12:32:25.770102 <6>[ 13.637411] Run /init as init process
1378 12:32:25.777355 Loading, please wait...
1379 12:32:25.817358 Starting systemd-udevd version 252.22-1~deb12u1
1380 12:32:26.334132 <6>[ 14.102910] mc: Linux media interface: v0.10
1381 12:32:26.334556 <6>[ 14.120447] videodev: Linux video capture interface: v2.00
1382 12:32:26.335327 <4>[ 14.143104] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1383 12:32:26.335567 <6>[ 14.183056] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1384 12:32:26.335816 <4>[ 14.189967] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1385 12:32:26.336059 <3>[ 14.190467] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1386 12:32:26.336450 <6>[ 14.205396] meson-vrtc ff8000a8.rtc: registered as rtc0
1387 12:32:26.347408 <6>[ 14.207765] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1388 12:32:26.352977 <6>[ 14.220465] panfrost ffe40000.gpu: clock rate = 24000000
1389 12:32:26.358574 <3>[ 14.221768] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1390 12:32:26.364110 <6>[ 14.223854] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1391 12:32:26.375229 <6>[ 14.228576] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1392 12:32:26.386339 <6>[ 14.237950] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1393 12:32:26.391877 <6>[ 14.238972] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1394 12:32:26.402968 <6>[ 14.238985] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1395 12:32:26.414053 <6>[ 14.238992] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1396 12:32:26.419593 <6>[ 14.239001] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1397 12:32:26.425161 <6>[ 14.247613] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1398 12:32:26.430706 <6>[ 14.297113] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1399 12:32:26.436351 <6>[ 14.304265] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1400 12:32:26.447241 <6>[ 14.304886] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1401 12:32:26.452718 <3>[ 14.318856] meson-drm ff900000.vpu: DSI transceiver device is disabled
1402 12:32:26.463797 <6>[ 14.319713] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1403 12:32:26.469346 <6>[ 14.330068] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 0
1404 12:32:26.474900 <6>[ 14.332844] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1405 12:32:26.480446 <6>[ 14.344694] Registered IR keymap rc-empty
1406 12:32:26.485993 <6>[ 14.344941] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 1
1407 12:32:26.491550 <6>[ 14.344990] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1408 12:32:26.502616 <6>[ 14.344998] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1409 12:32:26.508206 <6>[ 14.345003] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1410 12:32:26.513707 <6>[ 14.345008] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1411 12:32:26.519255 <6>[ 14.345012] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1412 12:32:26.524784 <6>[ 14.351076] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1413 12:32:26.535890 <6>[ 14.353197] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1414 12:32:26.547000 <6>[ 14.368456] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1415 12:32:26.552547 <6>[ 14.371510] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1416 12:32:26.558172 <6>[ 14.394736] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1417 12:32:26.569313 <6>[ 14.397074] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1418 12:32:26.569749 <6>[ 14.414766] rc rc0: sw decoder init
1419 12:32:26.580365 <6>[ 14.440645] usbcore: registered new device driver onboard-usb-dev
1420 12:32:26.584100 <6>[ 14.442727] meson-ir ff808000.ir: receiver initialized
1421 12:32:26.760201 <6>[ 14.456716] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1422 12:32:26.765728 <6>[ 14.609295] Console: switching to colour frame buffer device 128x48
1423 12:32:26.772522 <6>[ 14.635641] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1424 12:32:27.008082 <6>[ 14.881581] hub 1-1:1.0: USB hub found
1425 12:32:27.013528 <6>[ 14.881901] hub 1-1:1.0: 4 ports detected
1426 12:32:27.020017 <6>[ 14.886599] onboard-usb-dev 1-1: USB disconnect, device number 2
1427 12:32:27.151756 Begin: Loading essential drivers ... done.
1428 12:32:27.157257 Begin: Running /scripts/init-premount ... done.
1429 12:32:27.162802 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1430 12:32:27.176917 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1431 12:32:27.177310 Device /sys/class/net/end0 found
1432 12:32:27.177582 done.
1433 12:32:27.192876 Begin: Waiting up to 180 secs for any network device to become available ... done.
1434 12:32:27.246095 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.111194] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1435 12:32:27.246705
1436 12:32:27.335326 <6>[ 15.200663] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=38)
1437 12:32:27.348767 <6>[ 15.216795] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1438 12:32:27.354326 <6>[ 15.218997] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1439 12:32:27.363637 <6>[ 15.226507] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1440 12:32:27.391260 <6>[ 15.260548] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1441 12:32:27.584222 <6>[ 15.457670] hub 1-1:1.0: USB hub found
1442 12:32:27.589879 <6>[ 15.458003] hub 1-1:1.0: 4 ports detected
1443 12:32:27.780401 <6>[ 15.649524] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1444 12:32:28.036367 <6>[ 15.905506] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1445 12:32:28.146920 <4>[ 16.020508] rc rc0: two consecutive events of type space
1446 12:32:28.836032 IP-Config: no response after 2 secs - giving up
1447 12:32:28.878155 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1448 12:32:30.317471 <6>[ 18.184851] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1449 12:32:32.079801 IP-Config: no response after 3 secs - giving up
1450 12:32:32.131172 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1451 12:32:35.242595 IP-Config: end0 guessed broadcast address 192.168.6.255
1452 12:32:35.247961 IP-Config: end0 complete (dhcp from 192.168.6.1):
1453 12:32:35.253520 address: 192.168.6.33 broadcast: 192.168.6.255 netmask: 255.255.255.0
1454 12:32:35.264609 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1455 12:32:35.265200 rootserver: 192.168.6.1 rootpath:
1456 12:32:35.268067 filename :
1457 12:32:35.351255 done.
1458 12:32:35.361741 Begin: Running /scripts/nfs-bottom ... done.
1459 12:32:35.377055 Begin: Running /scripts/init-bottom ... done.
1460 12:32:35.684897 <30>[ 23.553936] systemd[1]: System time before build time, advancing clock.
1461 12:32:35.751872 <6>[ 23.625332] NET: Registered PF_INET6 protocol family
1462 12:32:35.757376 <6>[ 23.627921] Segment Routing with IPv6
1463 12:32:35.762701 <6>[ 23.628907] In-situ OAM (IOAM) with IPv6
1464 12:32:35.841204 <30>[ 23.683357] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1465 12:32:35.846712 <30>[ 23.710770] systemd[1]: Detected architecture arm64.
1466 12:32:35.847197
1467 12:32:35.850559 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1468 12:32:35.851009
1469 12:32:35.864617 <30>[ 23.734284] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1470 12:32:36.744549 <30>[ 24.613013] systemd[1]: Queued start job for default target graphical.target.
1471 12:32:36.781301 <30>[ 24.649190] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1472 12:32:36.789030 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1473 12:32:36.807039 <30>[ 24.674530] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1474 12:32:36.814109 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1475 12:32:36.826594 <30>[ 24.694638] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1476 12:32:36.835497 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1477 12:32:36.846575 <30>[ 24.714134] systemd[1]: Created slice user.slice - User and Session Slice.
1478 12:32:36.852698 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1479 12:32:36.874708 <30>[ 24.737089] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1480 12:32:36.878699 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1481 12:32:36.899945 <30>[ 24.765026] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1482 12:32:36.909385 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1483 12:32:36.925905 <30>[ 24.784917] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1484 12:32:36.936786 <30>[ 24.799110] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1485 12:32:36.944412 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1486 12:32:36.949957 <30>[ 24.820746] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1487 12:32:36.960993 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1488 12:32:36.976754 <30>[ 24.844807] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1489 12:32:36.990527 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1490 12:32:36.995967 <30>[ 24.864836] systemd[1]: Reached target paths.target - Path Units.
1491 12:32:37.004588 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1492 12:32:37.011610 <30>[ 24.880778] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1493 12:32:37.021810 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1494 12:32:37.027331 <30>[ 24.896728] systemd[1]: Reached target slices.target - Slice Units.
1495 12:32:37.035558 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1496 12:32:37.041020 <30>[ 24.912829] systemd[1]: Reached target swap.target - Swaps.
1497 12:32:37.048917 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1498 12:32:37.060805 <30>[ 24.928837] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1499 12:32:37.069681 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1500 12:32:37.085118 <30>[ 24.953163] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1501 12:32:37.094383 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1502 12:32:37.106648 <30>[ 24.974666] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1503 12:32:37.115510 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1504 12:32:37.127181 <30>[ 24.994941] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1505 12:32:37.139410 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1506 12:32:37.145054 <30>[ 25.013490] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1507 12:32:37.152807 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1508 12:32:37.171715 <30>[ 25.039286] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1509 12:32:37.180476 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1510 12:32:37.191489 <30>[ 25.059541] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1511 12:32:37.196985 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1512 12:32:37.209293 <30>[ 25.077329] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1513 12:32:37.217846 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1514 12:32:37.268856 <30>[ 25.136865] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1515 12:32:37.275578 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1516 12:32:37.287117 <30>[ 25.155161] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1517 12:32:37.294603 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1518 12:32:37.306904 <30>[ 25.174973] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1519 12:32:37.314932 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1520 12:32:37.331746 <30>[ 25.192859] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1521 12:32:37.342716 <30>[ 25.206074] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1522 12:32:37.348544 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1523 12:32:37.361672 <30>[ 25.229589] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1524 12:32:37.369586 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1525 12:32:37.385498 <30>[ 25.253539] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1526 12:32:37.393110 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1527 12:32:37.408644 <6>[ 25.276712] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1528 12:32:37.417799 <30>[ 25.280993] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1529 12:32:37.424730 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1530 12:32:37.441208 <30>[ 25.309200] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1531 12:32:37.449525 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1532 12:32:37.489160 <30>[ 25.357195] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1533 12:32:37.496455 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1534 12:32:37.509293 <30>[ 25.377276] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1535 12:32:37.514853 Starting [0;1;39mmodprobe<6>[ 25.383620] fuse: init (API version 7.41)
1536 12:32:37.518843 @loop.ser…e[0m - Load Kernel Module loop...
1537 12:32:37.539912 <30>[ 25.407350] systemd[1]: Starting systemd-journald.service - Journal Service...
1538 12:32:37.545805 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1539 12:32:37.567258 <30>[ 25.435262] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1540 12:32:37.574816 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1541 12:32:37.590647 <30>[ 25.458555] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1542 12:32:37.600021 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1543 12:32:37.617452 <30>[ 25.485452] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1544 12:32:37.626443 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1545 12:32:37.640293 <30>[ 25.508297] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1546 12:32:37.648537 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1547 12:32:37.662766 <30>[ 25.530735] systemd[1]: Started systemd-journald.service - Journal Service.
1548 12:32:37.669606 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1549 12:32:37.686142 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1550 12:32:37.701335 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1551 12:32:37.713568 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1552 12:32:37.725536 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1553 12:32:37.741955 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1554 12:32:37.753847 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1555 12:32:37.769477 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1556 12:32:37.790027 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1557 12:32:37.801615 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1558 12:32:37.813580 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1559 12:32:37.825624 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1560 12:32:37.841505 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1561 12:32:37.857598 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1562 12:32:37.877842 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1563 12:32:37.924494 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1564 12:32:37.944698 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1565 12:32:37.965094 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1566 12:32:37.981377 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1567 12:32:38.000052 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1568 12:32:38.007576 <46>[ 25.875310] systemd-journald[230]: Received client request to flush runtime journal.
1569 12:32:38.023794 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1570 12:32:38.040918 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1571 12:32:38.049331 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1572 12:32:38.065737 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1573 12:32:38.081762 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1574 12:32:38.098057 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1575 12:32:38.162058 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1576 12:32:38.212400 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1577 12:32:38.292618 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1578 12:32:38.325292 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1579 12:32:38.337164 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1580 12:32:38.348354 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1581 12:32:38.391904 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1582 12:32:38.398404 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1583 12:32:38.644774 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1584 12:32:38.661722 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1585 12:32:38.712736 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1586 12:32:38.737051 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1587 12:32:38.753333 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1588 12:32:38.780740 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1589 12:32:38.813026 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1590 12:32:38.874903 <5>[ 26.743111] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1591 12:32:38.912056 <5>[ 26.780112] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1592 12:32:38.917510 <5>[ 26.780975] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1593 12:32:38.923019 <4>[ 26.788668] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1594 12:32:38.928620 <6>[ 26.796773] cfg80211: failed to load regulatory.db
1595 12:32:38.941313 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1596 12:32:38.948850 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1597 12:32:38.965583 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1598 12:32:38.980294 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1599 12:32:39.020902 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1600 12:32:39.040988 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1601 12:32:39.057038 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1602 12:32:39.095699 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata<46>[ 26.949617] systemd-journald[230]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1603 12:32:39.106921 <46>[ 26.965281] systemd-journald[230]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1604 12:32:39.112401 Check for All Filesystems.
1605 12:32:39.123913 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1606 12:32:39.135328 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1607 12:32:39.212374 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1608 12:32:39.229576 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1609 12:32:39.235475 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1610 12:32:39.271641 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1611 12:32:39.299488 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1612 12:32:39.321312 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1613 12:32:39.337267 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1614 12:32:39.423885 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1615 12:32:39.437099 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1616 12:32:39.453143 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1617 12:32:39.491147 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1618 12:32:39.497608 Starting [0;1;39mdpkg-db-backup.se…ly dpkg database backup service...
1619 12:32:39.509566 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1620 12:32:39.519337 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1621 12:32:39.542739 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1622 12:32:39.554009 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1623 12:32:39.569777 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1624 12:32:39.579869 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1625 12:32:39.619715 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1626 12:32:39.635362 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1627 12:32:39.650539 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1628 12:32:39.657393 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1629 12:32:39.674018 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1630 12:32:39.684984 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1631 12:32:39.728804 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1632 12:32:39.788995 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1633 12:32:40.260418 [[0;32m OK [0m] Finished [0;1;39mdpkg-db-backup.se…aily dpkg database backup service.
1634 12:32:40.335270
1635 12:32:40.335795 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1636 12:32:40.336158
1637 12:32:40.342443 debian-bookworm-arm64 login: root (automatic login)
1638 12:32:40.342782
1639 12:32:40.467177 Linux debian-bookworm-arm64 6.12.0-rc1 #1 SMP PREEMPT Wed Oct 9 11:51:54 UTC 2024 aarch64
1640 12:32:40.467734
1641 12:32:40.472694 The programs included with the Debian GNU/Linux system are free software;
1642 12:32:40.481661 the exact distribution terms for each program are described in the
1643 12:32:40.481993 individual files in /usr/share/doc/*/copyright.
1644 12:32:40.482247
1645 12:32:40.487207 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1646 12:32:40.492436 permitted by applicable law.
1647 12:32:41.117767 Matched prompt #10: / #
1649 12:32:41.119380 Setting prompt string to ['/ #']
1650 12:32:41.119954 end: 2.4.4.1 login-action (duration 00:00:29) [common]
1652 12:32:41.121391 end: 2.4.4 auto-login-action (duration 00:00:29) [common]
1653 12:32:41.121939 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
1654 12:32:41.122374 Setting prompt string to ['/ #']
1655 12:32:41.122784 Forcing a shell prompt, looking for ['/ #']
1657 12:32:41.173748 / #
1658 12:32:41.174678 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1659 12:32:41.175180 Waiting using forced prompt support (timeout 00:02:30)
1660 12:32:41.179740
1661 12:32:41.180382 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1662 12:32:41.180754 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
1663 12:32:41.181065 Sending with 10 millisecond of delay
1665 12:32:46.171562 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/826935/extract-nfsrootfs-f0ktqxdm'
1666 12:32:46.182242 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/826935/extract-nfsrootfs-f0ktqxdm'
1667 12:32:46.182722 Sending with 10 millisecond of delay
1669 12:32:48.280342 / # export NFS_SERVER_IP='192.168.6.2'
1670 12:32:48.290989 export NFS_SERVER_IP='192.168.6.2'
1671 12:32:48.291630 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1672 12:32:48.292021 end: 2.4 uboot-commands (duration 00:01:56) [common]
1673 12:32:48.292340 end: 2 uboot-action (duration 00:01:56) [common]
1674 12:32:48.292653 start: 3 lava-test-retry (timeout 00:06:45) [common]
1675 12:32:48.292960 start: 3.1 lava-test-shell (timeout 00:06:45) [common]
1676 12:32:48.293223 Using namespace: common
1678 12:32:48.393999 / # #
1679 12:32:48.394742 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1680 12:32:48.400509 #
1681 12:32:48.401329 Using /lava-826935
1683 12:32:48.502115 / # export SHELL=/bin/bash
1684 12:32:48.508912 export SHELL=/bin/bash
1686 12:32:48.610687 / # . /lava-826935/environment
1687 12:32:48.614759 . /lava-826935/environment
1689 12:32:48.722090 / # /lava-826935/bin/lava-test-runner /lava-826935/0
1690 12:32:48.722936 Test shell timeout: 10s (minimum of the action and connection timeout)
1691 12:32:48.727207 /lava-826935/bin/lava-test-runner /lava-826935/0
1692 12:32:48.907935 + export TESTRUN_ID=0_timesync-off
1693 12:32:48.916050 + TESTRUN_ID=0_timesync-off
1694 12:32:48.916441 + cd /lava-826935/0/tests/0_timesync-off
1695 12:32:48.916688 ++ cat uuid
1696 12:32:48.921587 + UUID=826935_1.6.2.4.1
1697 12:32:48.921925 + set +x
1698 12:32:48.929510 <LAVA_SIGNAL_STARTRUN 0_timesync-off 826935_1.6.2.4.1>
1699 12:32:48.929859 + systemctl stop systemd-timesyncd
1700 12:32:48.930349 Received signal: <STARTRUN> 0_timesync-off 826935_1.6.2.4.1
1701 12:32:48.930616 Starting test lava.0_timesync-off (826935_1.6.2.4.1)
1702 12:32:48.930922 Skipping test definition patterns.
1703 12:32:48.966803 + set +x
1704 12:32:48.967203 <LAVA_SIGNAL_ENDRUN 0_timesync-off 826935_1.6.2.4.1>
1705 12:32:48.967690 Received signal: <ENDRUN> 0_timesync-off 826935_1.6.2.4.1
1706 12:32:48.968045 Ending use of test pattern.
1707 12:32:48.968317 Ending test lava.0_timesync-off (826935_1.6.2.4.1), duration 0.04
1709 12:32:49.038642 + export TESTRUN_ID=1_kselftest-alsa
1710 12:32:49.044185 + TESTRUN_ID=1_kselftest-alsa
1711 12:32:49.044512 + cd /lava-826935/0/tests/1_kselftest-alsa
1712 12:32:49.044762 ++ cat uuid
1713 12:32:49.049654 + UUID=826935_1.6.2.4.5
1714 12:32:49.049974 + set +x
1715 12:32:49.055195 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 826935_1.6.2.4.5>
1716 12:32:49.055519 + cd ./automated/linux/kselftest/
1717 12:32:49.056029 Received signal: <STARTRUN> 1_kselftest-alsa 826935_1.6.2.4.5
1718 12:32:49.056321 Starting test lava.1_kselftest-alsa (826935_1.6.2.4.5)
1719 12:32:49.056608 Skipping test definition patterns.
1720 12:32:49.084059 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g lee-mfd -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1721 12:32:49.123008 INFO: install_deps skipped
1722 12:32:49.247029 --2024-10-09 12:32:49-- http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/kselftest.tar.xz
1723 12:32:49.271352 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1724 12:32:49.412248 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1725 12:32:49.550807 HTTP request sent, awaiting response... 200 OK
1726 12:32:49.551440 Length: 5070884 (4.8M) [application/octet-stream]
1727 12:32:49.556217 Saving to: 'kselftest_armhf.tar.gz'
1728 12:32:49.556718
1729 12:32:50.690963
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 179KB/s
kselftest_armhf.tar 4%[ ] 218.67K 393KB/s
kselftest_armhf.tar 18%[==> ] 893.67K 1.05MB/s
kselftest_armhf.tar 72%[=============> ] 3.51M 3.15MB/s
kselftest_armhf.tar 100%[===================>] 4.84M 4.26MB/s in 1.1s
1730 12:32:50.691652
1731 12:32:50.768747 2024-10-09 12:32:50 (4.26 MB/s) - 'kselftest_armhf.tar.gz' saved [5070884/5070884]
1732 12:32:50.769352
1733 12:32:59.297015 skiplist:
1734 12:32:59.297452 ========================================
1735 12:32:59.302814 ========================================
1736 12:32:59.342985 alsa:mixer-test
1737 12:32:59.343355 alsa:pcm-test
1738 12:32:59.343597 alsa:test-pcmtest-driver
1739 12:32:59.347123 alsa:utimer-test
1740 12:32:59.360701 ============== Tests to run ===============
1741 12:32:59.361267 alsa:mixer-test
1742 12:32:59.366219 alsa:pcm-test
1743 12:32:59.366760 alsa:test-pcmtest-driver
1744 12:32:59.367246 alsa:utimer-test
1745 12:32:59.373369 ===========End Tests to run ===============
1746 12:32:59.373946 shardfile-alsa pass
1747 12:32:59.509531 <12>[ 47.380024] kselftest: Running tests in alsa
1748 12:32:59.513060 TAP version 13
1749 12:32:59.525180 1..4
1750 12:32:59.545998 # timeout set to 45
1751 12:32:59.546581 # selftests: alsa: mixer-test
1752 12:32:59.723844 # TAP version 13
1753 12:32:59.724304 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1754 12:32:59.729628 # 1..427
1755 12:32:59.730026 # ok 1 get_value.LCALTA.60
1756 12:32:59.730240 # # LCALTA.60 TDMOUT_A SRC SEL
1757 12:32:59.733873 # ok 2 name.LCALTA.60
1758 12:32:59.734448 # ok 3 write_default.LCALTA.60
1759 12:32:59.741532 # ok 4 write_valid.LCALTA.60
1760 12:32:59.741962 # ok 5 write_invalid.LCALTA.60
1761 12:32:59.744656 # ok 6 event_missing.LCALTA.60
1762 12:32:59.746216 # ok 7 event_spurious.LCALTA.60
1763 12:32:59.753062 # ok 8 get_value.LCALTA.59
1764 12:32:59.753490 # # LCALTA.59 TDMOUT_B SRC SEL
1765 12:32:59.756243 # ok 9 name.LCALTA.59
1766 12:32:59.757578 # ok 10 write_default.LCALTA.59
1767 12:32:59.761610 # ok 11 write_valid.LCALTA.59
1768 12:32:59.762031 # ok 12 write_invalid.LCALTA.59
1769 12:32:59.766766 # ok 13 event_missing.LCALTA.59
1770 12:32:59.767162 # ok 14 event_spurious.LCALTA.59
1771 12:32:59.772322 # ok 15 get_value.LCALTA.58
1772 12:32:59.772722 # # LCALTA.58 TDMOUT_C SRC SEL
1773 12:32:59.777955 # ok 16 name.LCALTA.58
1774 12:32:59.778555 # ok 17 write_default.LCALTA.58
1775 12:32:59.783558 # ok 18 write_valid.LCALTA.58
1776 12:32:59.784198 # ok 19 write_invalid.LCALTA.58
1777 12:32:59.789064 # ok 20 event_missing.LCALTA.58
1778 12:32:59.789609 # ok 21 event_spurious.LCALTA.58
1779 12:32:59.794662 # ok 22 get_value.LCALTA.57
1780 12:32:59.795240 # # LCALTA.57 TDMIN_A SRC SEL
1781 12:32:59.795707 # ok 23 name.LCALTA.57
1782 12:32:59.800077 # ok 24 write_default.LCALTA.57
1783 12:32:59.800710 # ok 25 write_valid.LCALTA.57
1784 12:32:59.805699 # ok 26 write_invalid.LCALTA.57
1785 12:32:59.806224 # ok 27 event_missing.LCALTA.57
1786 12:32:59.811273 # ok 28 event_spurious.LCALTA.57
1787 12:32:59.811849 # ok 29 get_value.LCALTA.56
1788 12:32:59.816892 # # LCALTA.56 TDMIN_B SRC SEL
1789 12:32:59.817551 # ok 30 name.LCALTA.56
1790 12:32:59.822422 # ok 31 write_default.LCALTA.56
1791 12:32:59.822959 # ok 32 write_valid.LCALTA.56
1792 12:32:59.827851 # ok 33 write_invalid.LCALTA.56
1793 12:32:59.828223 # ok 34 event_missing.LCALTA.56
1794 12:32:59.833482 # ok 35 event_spurious.LCALTA.56
1795 12:32:59.834000 # ok 36 get_value.LCALTA.55
1796 12:32:59.838975 # # LCALTA.55 TDMIN_C SRC SEL
1797 12:32:59.850093 # ok 37 name.<3>[ 47.711749] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1798 12:32:59.850781 LCALTA.55
1799 12:32:59.855605 # ok 38 write_default.LCALTA.55
1800 12:32:59.856284 # ok 39 write_valid.LCALTA.55
1801 12:32:59.861076 # ok 40 write_invalid.LCALTA.55
1802 12:32:59.861647 # ok 41 event_missing.LCALTA.55
1803 12:32:59.866629 # ok 42 event_spurious.LCALTA.55
1804 12:32:59.867201 # ok 43 get_value.LCALTA.54
1805 12:32:59.872132 # # LCALTA.54 ACODEC Left DAC Sel
1806 12:32:59.872711 # ok 44 name.LCALTA.54
1807 12:32:59.877713 # ok 45 write_default.LCALTA.54
1808 12:32:59.878036 # ok 46 write_valid.LCALTA.54
1809 12:32:59.883292 # ok 47 write_invalid.LCALTA.54
1810 12:32:59.883876 # ok 48 event_missing.LCALTA.54
1811 12:32:59.889079 # ok 49 event_spurious.LCALTA.54
1812 12:32:59.889702 # ok 50 get_value.LCALTA.53
1813 12:32:59.894405 # # LCALTA.53 ACODEC Right DAC Sel
1814 12:32:59.894760 # ok 51 name.LCALTA.53
1815 12:32:59.900003 # ok 52 write_default.LCALTA.53
1816 12:32:59.900604 # ok 53 write_valid.LCALTA.53
1817 12:32:59.905499 # ok 54 write_invalid.LCALTA.53
1818 12:32:59.906075 # ok 55 event_missing.LCALTA.53
1819 12:32:59.911076 # ok 56 event_spurious.LCALTA.53
1820 12:32:59.911657 # ok 57 get_value.LCALTA.52
1821 12:32:59.916640 # # LCALTA.52 TOACODEC OUT EN Switch
1822 12:32:59.917240 # ok 58 name.LCALTA.52
1823 12:32:59.922171 # ok 59 write_default.LCALTA.52
1824 12:32:59.922797 # ok 60 write_valid.LCALTA.52
1825 12:32:59.927572 # ok 61 write_invalid.LCALTA.52
1826 12:32:59.928239 # ok 62 event_missing.LCALTA.52
1827 12:32:59.933223 # ok 63 event_spurious.LCALTA.52
1828 12:32:59.933840 # ok 64 get_value.LCALTA.51
1829 12:32:59.938752 # # LCALTA.51 TOACODEC SRC
1830 12:32:59.939323 # ok 65 name.LCALTA.51
1831 12:32:59.944320 # ok 66 write_default.LCALTA.51
1832 12:32:59.944912 # ok 67 write_valid.LCALTA.51
1833 12:32:59.949868 # ok 68 write_invalid.LCALTA.51
1834 12:32:59.950186 # ok 69 event_missing.LCALTA.51
1835 12:32:59.955377 # ok 70 event_spurious.LCALTA.51
1836 12:32:59.955699 # ok 71 get_value.LCALTA.50
1837 12:32:59.960933 # # LCALTA.50 TOHDMITX SPDIF SRC
1838 12:32:59.961517 # ok 72 name.LCALTA.50
1839 12:32:59.961980 # ok 73 write_default.LCALTA.50
1840 12:32:59.966442 # ok 74 write_valid.LCALTA.50
1841 12:32:59.966746 # ok 75 write_invalid.LCALTA.50
1842 12:32:59.972054 # ok 76 event_missing.LCALTA.50
1843 12:32:59.977572 # ok 77 event_spurious.LCALTA.50
1844 12:32:59.978128 # ok 78 get_value.LCALTA.49
1845 12:32:59.978589 # # LCALTA.49 TOHDMITX Switch
1846 12:32:59.983111 # ok 79 name.LCALTA.49
1847 12:32:59.983667 # ok 80 write_default.LCALTA.49
1848 12:32:59.988658 # ok 81 write_valid.LCALTA.49
1849 12:32:59.989209 # ok 82 write_invalid.LCALTA.49
1850 12:32:59.994169 # ok 83 event_missing.LCALTA.49
1851 12:32:59.994786 # ok 84 event_spurious.LCALTA.49
1852 12:32:59.999663 # ok 85 get_value.LCALTA.48
1853 12:33:00.000284 # # LCALTA.48 TOHDMITX I2S SRC
1854 12:33:00.005314 # ok 86 name.LCALTA.48
1855 12:33:00.005889 # ok 87 write_default.LCALTA.48
1856 12:33:00.010876 # ok 88 write_valid.LCALTA.48
1857 12:33:00.011431 # ok 89 write_invalid.LCALTA.48
1858 12:33:00.016406 # ok 90 event_missing.LCALTA.48
1859 12:33:00.017012 # ok 91 event_spurious.LCALTA.48
1860 12:33:00.021954 # ok 92 get_value.LCALTA.47
1861 12:33:00.022543 # # LCALTA.47 TODDR_C SRC SEL
1862 12:33:00.027501 # ok 93 name.LCALTA.47
1863 12:33:00.028162 # ok 94 write_default.LCALTA.47
1864 12:33:00.033043 # ok 95 write_valid.LCALTA.47
1865 12:33:00.033624 # ok 96 write_invalid.LCALTA.47
1866 12:33:00.038558 # ok 97 event_missing.LCALTA.47
1867 12:33:00.039128 # ok 98 event_spurious.LCALTA.47
1868 12:33:00.044127 # ok 99 get_value.LCALTA.46
1869 12:33:00.044689 # # LCALTA.46 TODDR_B SRC SEL
1870 12:33:00.045155 # ok 100 name.LCALTA.46
1871 12:33:00.049753 # ok 101 write_default.LCALTA.46
1872 12:33:00.055270 # ok 102 write_valid.LCALTA.46
1873 12:33:00.055864 # ok 103 write_invalid.LCALTA.46
1874 12:33:00.060757 # ok 104 event_missing.LCALTA.46
1875 12:33:00.061331 # ok 105 event_spurious.LCALTA.46
1876 12:33:00.066297 # ok 106 get_value.LCALTA.45
1877 12:33:00.066848 # # LCALTA.45 TODDR_A SRC SEL
1878 12:33:00.067304 # ok 107 name.LCALTA.45
1879 12:33:00.071864 # ok 108 write_default.LCALTA.45
1880 12:33:00.077387 # ok 109 write_valid.LCALTA.45
1881 12:33:00.077991 # ok 110 write_invalid.LCALTA.45
1882 12:33:00.082935 # ok 111 event_missing.LCALTA.45
1883 12:33:00.083494 # ok 112 event_spurious.LCALTA.45
1884 12:33:00.088484 # ok 113 get_value.LCALTA.44
1885 12:33:00.089047 # # LCALTA.44 FRDDR_C SINK 3 SEL
1886 12:33:00.094037 # ok 114 name.LCALTA.44
1887 12:33:00.094642 # ok 115 write_default.LCALTA.44
1888 12:33:00.099583 # ok 116 write_valid.LCALTA.44
1889 12:33:00.100169 # ok 117 write_invalid.LCALTA.44
1890 12:33:00.105137 # ok 118 event_missing.LCALTA.44
1891 12:33:00.105689 # ok 119 event_spurious.LCALTA.44
1892 12:33:00.110655 # ok 120 get_value.LCALTA.43
1893 12:33:00.111207 # # LCALTA.43 FRDDR_C SINK 2 SEL
1894 12:33:00.116257 # ok 121 name.LCALTA.43
1895 12:33:00.116813 # ok 122 write_default.LCALTA.43
1896 12:33:00.121779 # ok 123 write_valid.LCALTA.43
1897 12:33:00.122341 # ok 124 write_invalid.LCALTA.43
1898 12:33:00.127303 # ok 125 event_missing.LCALTA.43
1899 12:33:00.127866 # ok 126 event_spurious.LCALTA.43
1900 12:33:00.132881 # ok 127 get_value.LCALTA.42
1901 12:33:00.133424 # # LCALTA.42 FRDDR_C SINK 1 SEL
1902 12:33:00.138411 # ok 128 name.LCALTA.42
1903 12:33:00.139020 # ok 129 write_default.LCALTA.42
1904 12:33:00.143938 # ok 130 write_valid.LCALTA.42
1905 12:33:00.144597 # ok 131 write_invalid.LCALTA.42
1906 12:33:00.149525 # ok 132 event_missing.LCALTA.42
1907 12:33:00.149999 # ok 133 event_spurious.LCALTA.42
1908 12:33:00.155029 # ok 134 get_value.LCALTA.41
1909 12:33:00.155669 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1910 12:33:00.160570 # ok 135 name.LCALTA.41
1911 12:33:00.161183 # ok 136 write_default.LCALTA.41
1912 12:33:00.166157 # ok 137 write_valid.LCALTA.41
1913 12:33:00.166758 # ok 138 write_invalid.LCALTA.41
1914 12:33:00.171675 # ok 139 event_missing.LCALTA.41
1915 12:33:00.172319 # ok 140 event_spurious.LCALTA.41
1916 12:33:00.177206 # ok 141 get_value.LCALTA.40
1917 12:33:00.177818 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1918 12:33:00.182819 # ok 142 name.LCALTA.40
1919 12:33:00.183462 # ok 143 write_default.LCALTA.40
1920 12:33:00.188339 # ok 144 write_valid.LCALTA.40
1921 12:33:00.188954 # ok 145 write_invalid.LCALTA.40
1922 12:33:00.193884 # ok 146 event_missing.LCALTA.40
1923 12:33:00.194500 # ok 147 event_spurious.LCALTA.40
1924 12:33:00.199431 # ok 148 get_value.LCALTA.39
1925 12:33:00.204958 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1926 12:33:00.205570 # ok 149 name.LCALTA.39
1927 12:33:00.206062 # ok 150 write_default.LCALTA.39
1928 12:33:00.210889 # ok 151 write_valid.LCALTA.39
1929 12:33:00.211549 # ok 152 write_invalid.LCALTA.39
1930 12:33:00.216080 # ok 153 event_missing.LCALTA.39
1931 12:33:00.221626 # ok 154 event_spurious.LCALTA.39
1932 12:33:00.222243 # ok 155 get_value.LCALTA.38
1933 12:33:00.227264 # # LCALTA.38 FRDDR_B SINK 3 SEL
1934 12:33:00.227949 # ok 156 name.LCALTA.38
1935 12:33:00.228501 # ok 157 write_default.LCALTA.38
1936 12:33:00.232801 # ok 158 write_valid.LCALTA.38
1937 12:33:00.233385 # ok 159 write_invalid.LCALTA.38
1938 12:33:00.238182 # ok 160 event_missing.LCALTA.38
1939 12:33:00.243894 # ok 161 event_spurious.LCALTA.38
1940 12:33:00.244572 # ok 162 get_value.LCALTA.37
1941 12:33:00.249720 # # LCALTA.37 FRDDR_B SINK 2 SEL
1942 12:33:00.250108 # ok 163 name.LCALTA.37
1943 12:33:00.250316 # ok 164 write_default.LCALTA.37
1944 12:33:00.254933 # ok 165 write_valid.LCALTA.37
1945 12:33:00.260610 # ok 166 write_invalid.LCALTA.37
1946 12:33:00.261411 # ok 167 event_missing.LCALTA.37
1947 12:33:00.265943 # ok 168 event_spurious.LCALTA.37
1948 12:33:00.266621 # ok 169 get_value.LCALTA.36
1949 12:33:00.271403 # # LCALTA.36 FRDDR_B SINK 1 SEL
1950 12:33:00.272091 # ok 170 name.LCALTA.36
1951 12:33:00.276948 # ok 171 write_default.LCALTA.36
1952 12:33:00.277485 # ok 172 write_valid.LCALTA.36
1953 12:33:00.282538 # ok 173 write_invalid.LCALTA.36
1954 12:33:00.283066 # ok 174 event_missing.LCALTA.36
1955 12:33:00.288067 # ok 175 event_spurious.LCALTA.36
1956 12:33:00.288577 # ok 176 get_value.LCALTA.35
1957 12:33:00.293641 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1958 12:33:00.294116 # ok 177 name.LCALTA.35
1959 12:33:00.299188 # ok 178 write_default.LCALTA.35
1960 12:33:00.299702 # ok 179 write_valid.LCALTA.35
1961 12:33:00.304734 # ok 180 write_invalid.LCALTA.35
1962 12:33:00.305209 # ok 181 event_missing.LCALTA.35
1963 12:33:00.310255 # ok 182 event_spurious.LCALTA.35
1964 12:33:00.310736 # ok 183 get_value.LCALTA.34
1965 12:33:00.315859 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1966 12:33:00.316304 # ok 184 name.LCALTA.34
1967 12:33:00.321375 # ok 185 write_default.LCALTA.34
1968 12:33:00.321824 # ok 186 write_valid.LCALTA.34
1969 12:33:00.326914 # ok 187 write_invalid.LCALTA.34
1970 12:33:00.327352 # ok 188 event_missing.LCALTA.34
1971 12:33:00.332436 # ok 189 event_spurious.LCALTA.34
1972 12:33:00.333538 # ok 190 get_value.LCALTA.33
1973 12:33:00.338260 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1974 12:33:00.338710 # ok 191 name.LCALTA.33
1975 12:33:00.343549 # ok 192 write_default.LCALTA.33
1976 12:33:00.344018 # ok 193 write_valid.LCALTA.33
1977 12:33:00.349425 # ok 194 write_invalid.LCALTA.33
1978 12:33:00.349855 # ok 195 event_missing.LCALTA.33
1979 12:33:00.354750 # ok 196 event_spurious.LCALTA.33
1980 12:33:00.355238 # ok 197 get_value.LCALTA.32
1981 12:33:00.360347 # # LCALTA.32 FRDDR_A SINK 3 SEL
1982 12:33:00.360812 # ok 198 name.LCALTA.32
1983 12:33:00.365763 # ok 199 write_default.LCALTA.32
1984 12:33:00.366215 # ok 200 write_valid.LCALTA.32
1985 12:33:00.371342 # ok 201 write_invalid.LCALTA.32
1986 12:33:00.371770 # ok 202 event_missing.LCALTA.32
1987 12:33:00.376889 # ok 203 event_spurious.LCALTA.32
1988 12:33:00.377309 # ok 204 get_value.LCALTA.31
1989 12:33:00.382395 # # LCALTA.31 FRDDR_A SINK 2 SEL
1990 12:33:00.382804 # ok 205 name.LCALTA.31
1991 12:33:00.388463 # ok 206 write_default.LCALTA.31
1992 12:33:00.388892 # ok 207 write_valid.LCALTA.31
1993 12:33:00.393502 # ok 208 write_invalid.LCALTA.31
1994 12:33:00.393954 # ok 209 event_missing.LCALTA.31
1995 12:33:00.399109 # ok 210 event_spurious.LCALTA.31
1996 12:33:00.401199 # ok 211 get_value.LCALTA.30
1997 12:33:00.404583 # # LCALTA.30 FRDDR_A SINK 1 SEL
1998 12:33:00.405014 # ok 212 name.LCALTA.30
1999 12:33:00.410095 # ok 213 write_default.LCALTA.30
2000 12:33:00.410473 # ok 214 write_valid.LCALTA.30
2001 12:33:00.415583 # ok 215 write_invalid.LCALTA.30
2002 12:33:00.421233 # ok 216 event_missing.LCALTA.30
2003 12:33:00.421763 # ok 217 event_spurious.LCALTA.30
2004 12:33:00.426712 # ok 218 get_value.LCALTA.29
2005 12:33:00.427120 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2006 12:33:00.432375 # ok 219 name.LCALTA.29
2007 12:33:00.432863 # ok 220 write_default.LCALTA.29
2008 12:33:00.438103 # ok 221 write_valid.LCALTA.29
2009 12:33:00.438538 # ok 222 write_invalid.LCALTA.29
2010 12:33:00.443943 # ok 223 event_missing.LCALTA.29
2011 12:33:00.444632 # ok 224 event_spurious.LCALTA.29
2012 12:33:00.448886 # ok 225 get_value.LCALTA.28
2013 12:33:00.449451 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2014 12:33:00.454837 # ok 226 name.LCALTA.28
2015 12:33:00.455407 # ok 227 write_default.LCALTA.28
2016 12:33:00.460093 # ok 228 write_valid.LCALTA.28
2017 12:33:00.460642 # ok 229 write_invalid.LCALTA.28
2018 12:33:00.465640 # ok 230 event_missing.LCALTA.28
2019 12:33:00.466201 # ok 231 event_spurious.LCALTA.28
2020 12:33:00.471213 # ok 232 get_value.LCALTA.27
2021 12:33:00.471773 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2022 12:33:00.476713 # ok 233 name.LCALTA.27
2023 12:33:00.477088 # ok 234 write_default.LCALTA.27
2024 12:33:00.482201 # ok 235 write_valid.LCALTA.27
2025 12:33:00.482541 # ok 236 write_invalid.LCALTA.27
2026 12:33:00.487837 # ok 237 event_missing.LCALTA.27
2027 12:33:00.488441 # ok 238 event_spurious.LCALTA.27
2028 12:33:00.493603 # ok 239 get_value.LCALTA.26
2029 12:33:00.494402 # # LCALTA.26 ELD
2030 12:33:00.499249 # ok 240 name.LCALTA.26
2031 12:33:00.499684 # # ELD is not writeable
2032 12:33:00.504477 # ok 241 # SKIP write_default.LCALTA.26
2033 12:33:00.504880 # # ELD is not writeable
2034 12:33:00.510247 # ok 242 # SKIP write_valid.LCALTA.26
2035 12:33:00.510684 # # ELD is not writeable
2036 12:33:00.515549 # ok 243 # SKIP write_invalid.LCALTA.26
2037 12:33:00.516676 # ok 244 event_missing.LCALTA.26
2038 12:33:00.521155 # ok 245 event_spurious.LCALTA.26
2039 12:33:00.521654 # ok 246 get_value.LCALTA.25
2040 12:33:00.526542 # # LCALTA.25 IEC958 Playback Default
2041 12:33:00.527022 # ok 247 name.LCALTA.25
2042 12:33:00.532116 # ok 248 write_default.LCALTA.25
2043 12:33:00.532613 # ok 249 # SKIP write_valid.LCALTA.25
2044 12:33:00.537651 # ok 250 # SKIP write_invalid.LCALTA.25
2045 12:33:00.543285 # ok 251 event_missing.LCALTA.25
2046 12:33:00.543711 # ok 252 event_spurious.LCALTA.25
2047 12:33:00.548729 # ok 253 get_value.LCALTA.24
2048 12:33:00.549155 # # LCALTA.24 IEC958 Playback Mask
2049 12:33:00.549451 # ok 254 name.LCALTA.24
2050 12:33:00.554312 # # IEC958 Playback Mask is not writeable
2051 12:33:00.559838 # ok 255 # SKIP write_default.LCALTA.24
2052 12:33:00.560275 # # IEC958 Playback Mask is not writeable
2053 12:33:00.565381 # ok 256 # SKIP write_valid.LCALTA.24
2054 12:33:00.570941 # # IEC958 Playback Mask is not writeable
2055 12:33:00.571387 # ok 257 # SKIP write_invalid.LCALTA.24
2056 12:33:00.576457 # ok 258 event_missing.LCALTA.24
2057 12:33:00.576872 # ok 259 event_spurious.LCALTA.24
2058 12:33:00.582008 # ok 260 get_value.LCALTA.23
2059 12:33:00.582419 # # LCALTA.23 Playback Channel Map
2060 12:33:00.587722 # ok 261 name.LCALTA.23
2061 12:33:00.593150 # # Playback Channel Map is not writeable
2062 12:33:00.593522 # ok 262 # SKIP write_default.LCALTA.23
2063 12:33:00.598821 # # Playback Channel Map is not writeable
2064 12:33:00.599518 # ok 263 # SKIP write_valid.LCALTA.23
2065 12:33:00.604394 # # Playback Channel Map is not writeable
2066 12:33:00.609880 # ok 264 # SKIP write_invalid.LCALTA.23
2067 12:33:00.610509 # ok 265 event_missing.LCALTA.23
2068 12:33:00.615441 # ok 266 event_spurious.LCALTA.23
2069 12:33:00.615851 # ok 267 get_value.LCALTA.22
2070 12:33:00.620989 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2071 12:33:00.621631 # ok 268 name.LCALTA.22
2072 12:33:00.626569 # ok 269 write_default.LCALTA.22
2073 12:33:00.627212 # ok 270 write_valid.LCALTA.22
2074 12:33:00.632156 # ok 271 write_invalid.LCALTA.22
2075 12:33:00.632800 # ok 272 event_missing.LCALTA.22
2076 12:33:00.637503 # ok 273 event_spurious.LCALTA.22
2077 12:33:00.643199 # ok 274 get_value.LCALTA.21
2078 12:33:00.643620 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2079 12:33:00.643854 # ok 275 name.LCALTA.21
2080 12:33:00.648728 # ok 276 write_default.LCALTA.21
2081 12:33:00.654135 # ok 277 write_valid.LCALTA.21
2082 12:33:00.654578 # ok 278 write_invalid.LCALTA.21
2083 12:33:00.659795 # ok 279 event_missing.LCALTA.21
2084 12:33:00.660524 # ok 280 event_spurious.LCALTA.21
2085 12:33:00.665366 # ok 281 get_value.LCALTA.20
2086 12:33:00.665999 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2087 12:33:00.671062 # ok 282 name.LCALTA.20
2088 12:33:00.671720 # ok 283 write_default.LCALTA.20
2089 12:33:00.676484 # ok 284 write_valid.LCALTA.20
2090 12:33:00.677146 # ok 285 write_invalid.LCALTA.20
2091 12:33:00.682071 # ok 286 event_missing.LCALTA.20
2092 12:33:00.682714 # ok 287 event_spurious.LCALTA.20
2093 12:33:00.688085 # ok 288 get_value.LCALTA.19
2094 12:33:00.688738 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2095 12:33:00.693193 # ok 289 name.LCALTA.19
2096 12:33:00.693849 # ok 290 write_default.LCALTA.19
2097 12:33:00.698689 # ok 291 write_valid.LCALTA.19
2098 12:33:00.699338 # ok 292 write_invalid.LCALTA.19
2099 12:33:00.704320 # ok 293 event_missing.LCALTA.19
2100 12:33:00.704995 # ok 294 event_spurious.LCALTA.19
2101 12:33:00.709770 # ok 295 get_value.LCALTA.18
2102 12:33:00.710406 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2103 12:33:00.715318 # ok 296 name.LCALTA.18
2104 12:33:00.716015 # ok 297 write_default.LCALTA.18
2105 12:33:00.720936 # ok 298 write_valid.LCALTA.18
2106 12:33:00.721596 # ok 299 write_invalid.LCALTA.18
2107 12:33:00.726333 # ok 300 event_missing.LCALTA.18
2108 12:33:00.726743 # ok 301 event_spurious.LCALTA.18
2109 12:33:00.732129 # ok 302 get_value.LCALTA.17
2110 12:33:00.737370 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2111 12:33:00.737789 # ok 303 name.LCALTA.17
2112 12:33:00.738141 # ok 304 write_default.LCALTA.17
2113 12:33:00.742957 # ok 305 write_valid.LCALTA.17
2114 12:33:00.748480 # ok 306 write_invalid.LCALTA.17
2115 12:33:00.748900 # ok 307 event_missing.LCALTA.17
2116 12:33:00.753934 # ok 308 event_spurious.LCALTA.17
2117 12:33:00.754307 # ok 309 get_value.LCALTA.16
2118 12:33:00.759554 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2119 12:33:00.760028 # ok 310 name.LCALTA.16
2120 12:33:00.765018 # ok 311 write_default.LCALTA.16
2121 12:33:00.765421 # ok 312 write_valid.LCALTA.16
2122 12:33:00.770668 # ok 313 write_invalid.LCALTA.16
2123 12:33:00.771081 # ok 314 event_missing.LCALTA.16
2124 12:33:00.776320 # ok 315 event_spurious.LCALTA.16
2125 12:33:00.777013 # ok 316 get_value.LCALTA.15
2126 12:33:00.781767 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2127 12:33:00.782262 # ok 317 name.LCALTA.15
2128 12:33:00.787569 # ok 318 write_default.LCALTA.15
2129 12:33:00.788136 # ok 319 write_valid.LCALTA.15
2130 12:33:00.793136 # ok 320 write_invalid.LCALTA.15
2131 12:33:00.793625 # ok 321 event_missing.LCALTA.15
2132 12:33:00.798440 # ok 322 event_spurious.LCALTA.15
2133 12:33:00.798933 # ok 323 get_value.LCALTA.14
2134 12:33:00.804059 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2135 12:33:00.804544 # ok 324 name.LCALTA.14
2136 12:33:00.809669 # ok 325 write_default.LCALTA.14
2137 12:33:00.810125 # ok 326 write_valid.LCALTA.14
2138 12:33:00.815126 # ok 327 write_invalid.LCALTA.14
2139 12:33:00.815559 # ok 328 event_missing.LCALTA.14
2140 12:33:00.820635 # ok 329 event_spurious.LCALTA.14
2141 12:33:00.821076 # ok 330 get_value.LCALTA.13
2142 12:33:00.826186 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2143 12:33:00.826613 # ok 331 name.LCALTA.13
2144 12:33:00.831708 # ok 332 write_default.LCALTA.13
2145 12:33:00.832171 # ok 333 write_valid.LCALTA.13
2146 12:33:00.837282 # ok 334 write_invalid.LCALTA.13
2147 12:33:00.837729 # ok 335 event_missing.LCALTA.13
2148 12:33:00.842744 # ok 336 event_spurious.LCALTA.13
2149 12:33:00.843199 # ok 337 get_value.LCALTA.12
2150 12:33:00.848354 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2151 12:33:00.848796 # ok 338 name.LCALTA.12
2152 12:33:00.853906 # ok 339 write_default.LCALTA.12
2153 12:33:00.859458 # ok 340 write_valid.LCALTA.12
2154 12:33:00.859872 # ok 341 write_invalid.LCALTA.12
2155 12:33:00.864979 # ok 342 event_missing.LCALTA.12
2156 12:33:00.865393 # ok 343 event_spurious.LCALTA.12
2157 12:33:00.870524 # ok 344 get_value.LCALTA.11
2158 12:33:00.870907 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2159 12:33:00.876067 # ok 345 name.LCALTA.11
2160 12:33:00.876445 # ok 346 write_default.LCALTA.11
2161 12:33:00.881589 # ok 347 write_valid.LCALTA.11
2162 12:33:00.881992 # ok 348 write_invalid.LCALTA.11
2163 12:33:00.887135 # ok 349 event_missing.LCALTA.11
2164 12:33:00.887526 # ok 350 event_spurious.LCALTA.11
2165 12:33:00.892669 # ok 351 get_value.LCALTA.10
2166 12:33:00.893056 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2167 12:33:00.898276 # ok 352 name.LCALTA.10
2168 12:33:00.898672 # ok 353 write_default.LCALTA.10
2169 12:33:00.903791 # ok 354 write_valid.LCALTA.10
2170 12:33:00.904213 # ok 355 write_invalid.LCALTA.10
2171 12:33:00.909319 # ok 356 event_missing.LCALTA.10
2172 12:33:00.909716 # ok 357 event_spurious.LCALTA.10
2173 12:33:00.914918 # ok 358 get_value.LCALTA.9
2174 12:33:00.915326 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2175 12:33:00.920412 # ok 359 name.LCALTA.9
2176 12:33:00.920808 # ok 360 write_default.LCALTA.9
2177 12:33:00.925959 # ok 361 write_valid.LCALTA.9
2178 12:33:00.926335 # ok 362 write_invalid.LCALTA.9
2179 12:33:00.931510 # ok 363 event_missing.LCALTA.9
2180 12:33:00.931901 # ok 364 event_spurious.LCALTA.9
2181 12:33:00.937026 # ok 365 get_value.LCALTA.8
2182 12:33:00.937406 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2183 12:33:00.942629 # ok 366 name.LCALTA.8
2184 12:33:00.943022 # ok 367 write_default.LCALTA.8
2185 12:33:00.948391 # ok 368 write_valid.LCALTA.8
2186 12:33:00.948772 # ok 369 write_invalid.LCALTA.8
2187 12:33:00.953831 # ok 370 event_missing.LCALTA.8
2188 12:33:00.954219 # ok 371 event_spurious.LCALTA.8
2189 12:33:00.959316 # ok 372 get_value.LCALTA.7
2190 12:33:00.959705 # # LCALTA.7 ACODEC Unmute Ramp Switch
2191 12:33:00.964850 # ok 373 name.LCALTA.7
2192 12:33:00.965238 # ok 374 write_default.LCALTA.7
2193 12:33:00.970338 # ok 375 write_valid.LCALTA.7
2194 12:33:00.970717 # ok 376 write_invalid.LCALTA.7
2195 12:33:00.975955 # ok 377 event_missing.LCALTA.7
2196 12:33:00.976355 # ok 378 event_spurious.LCALTA.7
2197 12:33:00.981469 # ok 379 get_value.LCALTA.6
2198 12:33:00.981857 # # LCALTA.6 ACODEC Mute Ramp Switch
2199 12:33:00.987016 # ok 380 name.LCALTA.6
2200 12:33:00.987399 # ok 381 write_default.LCALTA.6
2201 12:33:00.992531 # ok 382 write_valid.LCALTA.6
2202 12:33:00.992922 # ok 383 write_invalid.LCALTA.6
2203 12:33:00.998097 # ok 384 event_missing.LCALTA.6
2204 12:33:00.998491 # ok 385 event_spurious.LCALTA.6
2205 12:33:01.003675 # ok 386 get_value.LCALTA.5
2206 12:33:01.004110 # # LCALTA.5 ACODEC Volume Ramp Switch
2207 12:33:01.009208 # ok 387 name.LCALTA.5
2208 12:33:01.009601 # ok 388 write_default.LCALTA.5
2209 12:33:01.014705 # ok 389 write_valid.LCALTA.5
2210 12:33:01.015096 # ok 390 write_invalid.LCALTA.5
2211 12:33:01.020314 # ok 391 event_missing.LCALTA.5
2212 12:33:01.020731 # ok 392 event_spurious.LCALTA.5
2213 12:33:01.025894 # ok 393 get_value.LCALTA.4
2214 12:33:01.026283 # # LCALTA.4 ACODEC Ramp Rate
2215 12:33:01.031357 # ok 394 name.LCALTA.4
2216 12:33:01.031738 # ok 395 write_default.LCALTA.4
2217 12:33:01.037142 # ok 396 write_valid.LCALTA.4
2218 12:33:01.037548 # ok 397 write_invalid.LCALTA.4
2219 12:33:01.042456 # ok 398 event_missing.LCALTA.4
2220 12:33:01.042843 # ok 399 event_spurious.LCALTA.4
2221 12:33:01.048214 # ok 400 get_value.LCALTA.3
2222 12:33:01.048618 # # LCALTA.3 ACODEC Playback Volume
2223 12:33:01.053548 # ok 401 name.LCALTA.3
2224 12:33:01.053942 # ok 402 write_default.LCALTA.3
2225 12:33:01.059082 # ok 403 write_valid.LCALTA.3
2226 12:33:01.059473 # ok 404 write_invalid.LCALTA.3
2227 12:33:01.064563 # ok 405 event_missing.LCALTA.3
2228 12:33:01.064924 # ok 406 event_spurious.LCALTA.3
2229 12:33:01.070291 # ok 407 get_value.LCALTA.2
2230 12:33:01.070666 # # LCALTA.2 ACODEC Playback Switch
2231 12:33:01.075686 # ok 408 name.LCALTA.2
2232 12:33:01.076094 # ok 409 write_default.LCALTA.2
2233 12:33:01.081212 # ok 410 write_valid.LCALTA.2
2234 12:33:01.081583 # ok 411 write_invalid.LCALTA.2
2235 12:33:01.086766 # ok 412 event_missing.LCALTA.2
2236 12:33:01.087143 # ok 413 event_spurious.LCALTA.2
2237 12:33:01.092309 # ok 414 get_value.LCALTA.1
2238 12:33:01.092690 # # LCALTA.1 ACODEC Playback Channel Mode
2239 12:33:01.097923 # ok 415 name.LCALTA.1
2240 12:33:01.098300 # ok 416 write_default.LCALTA.1
2241 12:33:01.103429 # ok 417 write_valid.LCALTA.1
2242 12:33:01.103815 # ok 418 write_invalid.LCALTA.1
2243 12:33:01.108979 # ok 419 event_missing.LCALTA.1
2244 12:33:01.109691 # ok 420 event_spurious.LCALTA.1
2245 12:33:01.114629 # ok 421 get_value.LCALTA.0
2246 12:33:01.115321 # # LCALTA.0 TOACODEC Lane Select
2247 12:33:01.120134 # ok 422 name.LCALTA.0
2248 12:33:01.120938 # ok 423 write_default.LCALTA.0
2249 12:33:01.125626 # ok 424 write_valid.LCALTA.0
2250 12:33:01.126336 # ok 425 write_invalid.LCALTA.0
2251 12:33:01.131211 # ok 426 event_missing.LCALTA.0
2252 12:33:01.131919 # ok 427 event_spurious.LCALTA.0
2253 12:33:01.136742 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2254 12:33:01.142290 ok 1 selftests: alsa: mixer-test
2255 12:33:01.143009 # timeout set to 45
2256 12:33:01.143639 # selftests: alsa: pcm-test
2257 12:33:01.147808 # TAP version 13
2258 12:33:01.148557 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2259 12:33:01.153390 # # LCALTA.0 - fe.dai-link-0 (*)
2260 12:33:01.154093 # # LCALTA.0 - fe.dai-link-1 (*)
2261 12:33:01.158997 # # LCALTA.0 - fe.dai-link-2 (*)
2262 12:33:01.159703 # # LCALTA.0 - fe.dai-link-3 (*)
2263 12:33:01.164460 # # LCALTA.0 - fe.dai-link-4 (*)
2264 12:33:01.165158 # # LCALTA.0 - fe.dai-link-5 (*)
2265 12:33:01.170020 # 1..42
2266 12:33:01.175583 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2267 12:33:01.176334 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2268 12:33:01.181117 # # snd_pcm_hw_params: Invalid argument
2269 12:33:01.186660 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2270 12:33:01.192193 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2271 12:33:01.192903 # # snd_pcm_hw_params: Invalid argument
2272 12:33:01.197699 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2273 12:33:01.203228 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2274 12:33:01.208806 # # snd_pcm_hw_params: Invalid argument
2275 12:33:01.214340 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2276 12:33:01.220077 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2277 12:33:01.220848 # # snd_pcm_hw_params: Invalid argument
2278 12:33:01.225417 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2279 12:33:01.231003 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2280 12:33:01.236514 # # snd_pcm_hw_params: Invalid argument
2281 12:33:01.242070 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2282 12:33:01.247631 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2283 12:33:01.248296 # # snd_pcm_hw_params: Invalid argument
2284 12:33:01.253188 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2285 12:33:01.258759 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2286 12:33:01.264254 # # snd_pcm_hw_params: Invalid argument
2287 12:33:01.269828 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2288 12:33:01.270507 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2289 12:33:01.275361 # # snd_pcm_hw_params: Invalid argument
2290 12:33:01.280913 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2291 12:33:01.286445 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2292 12:33:01.287085 # # snd_pcm_hw_params: Invalid argument
2293 12:33:01.297567 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2294 12:33:01.298229 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2295 12:33:01.303070 # # snd_pcm_hw_params: Invalid argument
2296 12:33:01.308612 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2297 12:33:01.314159 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2298 12:33:01.314796 # # snd_pcm_hw_params: Invalid argument
2299 12:33:01.319776 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2300 12:33:01.325250 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2301 12:33:01.330805 # # snd_pcm_hw_params: Invalid argument
2302 12:33:01.336462 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2303 12:33:01.342002 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2304 12:33:01.342573 # # snd_pcm_hw_params: Invalid argument
2305 12:33:01.347503 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2306 12:33:01.353037 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2307 12:33:01.358572 # # snd_pcm_hw_params: Invalid argument
2308 12:33:01.364162 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2309 12:33:01.369667 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2310 12:33:01.370195 # # snd_pcm_hw_params: Invalid argument
2311 12:33:01.375309 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2312 12:33:01.380923 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2313 12:33:01.386312 # # snd_pcm_hw_params: Invalid argument
2314 12:33:01.391853 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2315 12:33:01.392540 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2316 12:33:01.397401 # # snd_pcm_hw_params: Invalid argument
2317 12:33:01.403017 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2318 12:33:01.408544 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2319 12:33:01.414074 # # snd_pcm_hw_params: Invalid argument
2320 12:33:01.419581 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2321 12:33:01.420311 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2322 12:33:01.425197 # # snd_pcm_hw_params: Invalid argument
2323 12:33:01.430687 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2324 12:33:01.436278 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2325 12:33:01.441779 # # snd_pcm_hw_params: Invalid argument
2326 12:33:01.447398 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2327 12:33:01.448117 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2328 12:33:01.452866 # # snd_pcm_hw_params: Invalid argument
2329 12:33:01.458460 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2330 12:33:01.464295 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2331 12:33:01.464984 # # snd_pcm_hw_params: Invalid argument
2332 12:33:01.469534 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2333 12:33:01.475166 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2334 12:33:01.480645 # # snd_pcm_hw_params: Invalid argument
2335 12:33:01.486179 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2336 12:33:01.491821 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2337 12:33:01.492503 # # snd_pcm_hw_params: Invalid argument
2338 12:33:01.497319 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2339 12:33:01.502901 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2340 12:33:01.508422 # # snd_pcm_hw_params: Invalid argument
2341 12:33:01.513982 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2342 12:33:01.519531 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2343 12:33:01.520290 # # snd_pcm_hw_params: Invalid argument
2344 12:33:01.525058 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2345 12:33:01.530617 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2346 12:33:01.536134 # # snd_pcm_hw_params: Invalid argument
2347 12:33:01.541672 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2348 12:33:01.547247 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2349 12:33:01.547973 # # snd_pcm_hw_params: Invalid argument
2350 12:33:01.552754 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2351 12:33:01.558315 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2352 12:33:01.563778 # # snd_pcm_hw_params: Invalid argument
2353 12:33:01.569315 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2354 12:33:01.574873 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2355 12:33:01.575482 # # snd_pcm_hw_params: Invalid argument
2356 12:33:01.580431 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2357 12:33:01.585983 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2358 12:33:01.591507 # # snd_pcm_hw_params: Invalid argument
2359 12:33:01.597059 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2360 12:33:01.602623 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2361 12:33:01.603226 # # snd_pcm_hw_params: Invalid argument
2362 12:33:01.608193 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2363 12:33:01.613728 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2364 12:33:01.619250 # # snd_pcm_hw_params: Invalid argument
2365 12:33:01.624804 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2366 12:33:01.630374 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2367 12:33:01.630985 # # snd_pcm_hw_params: Invalid argument
2368 12:33:01.635914 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2369 12:33:01.641491 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2370 12:33:01.647035 # # snd_pcm_hw_params: Invalid argument
2371 12:33:01.652581 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2372 12:33:01.658132 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2373 12:33:01.658765 # # snd_pcm_hw_params: Invalid argument
2374 12:33:01.663660 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2375 12:33:01.669187 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2376 12:33:01.674744 # # snd_pcm_hw_params: Invalid argument
2377 12:33:01.680276 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2378 12:33:01.685810 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2379 12:33:01.686393 # # snd_pcm_hw_params: Invalid argument
2380 12:33:01.691356 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2381 12:33:01.696876 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2382 12:33:01.702417 # # snd_pcm_hw_params: Invalid argument
2383 12:33:01.708084 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2384 12:33:01.713539 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2385 12:33:01.714110 # # snd_pcm_hw_params: Invalid argument
2386 12:33:01.719092 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2387 12:33:01.724658 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2388 12:33:01.730162 # # snd_pcm_hw_params: Invalid argument
2389 12:33:01.735725 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2390 12:33:01.741328 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2391 12:33:01.741951 # # snd_pcm_hw_params: Invalid argument
2392 12:33:01.746844 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2393 12:33:01.752426 ok 2 selftests: alsa: pcm-test
2394 12:33:01.753055 # timeout set to 45
2395 12:33:01.757971 # selftests: alsa: test-pcmtest-driver
2396 12:33:01.758602 # TAP version 13
2397 12:33:01.759091 # 1..5
2398 12:33:01.763491 # # Starting 5 tests from 1 test cases.
2399 12:33:01.764164 # # RUN pcmtest.playback ...
2400 12:33:01.769043 # # SKIP Can't read patterns. Probably, module isn't loaded
2401 12:33:01.774595 # # OK pcmtest.playback
2402 12:33:01.780096 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2403 12:33:01.785696 # # RUN pcmtest.capture ...
2404 12:33:01.791198 # # SKIP Can't read patterns. Probably, module isn't loaded
2405 12:33:01.796729 # # OK pcmtest.capture
2406 12:33:01.802318 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2407 12:33:01.807841 # # RUN pcmtest.ni_capture ...
2408 12:33:01.813376 # # SKIP Can't read patterns. Probably, module isn't loaded
2409 12:33:01.813971 # # OK pcmtest.ni_capture
2410 12:33:01.824548 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2411 12:33:01.825159 # # RUN pcmtest.ni_playback ...
2412 12:33:01.830093 # # SKIP Can't read patterns. Probably, module isn't loaded
2413 12:33:01.835582 # # OK pcmtest.ni_playback
2414 12:33:01.841118 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2415 12:33:01.846723 # # RUN pcmtest.reset_ioctl ...
2416 12:33:01.852223 # # SKIP Can't read patterns. Probably, module isn't loaded
2417 12:33:01.857736 # # OK pcmtest.reset_ioctl
2418 12:33:01.863283 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2419 12:33:01.868871 # # PASSED: 5 / 5 tests passed.
2420 12:33:01.874428 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2421 12:33:01.875005 ok 3 selftests: alsa: test-pcmtest-driver
2422 12:33:01.880045 # timeout set to 45
2423 12:33:01.880605 # selftests: alsa: utimer-test
2424 12:33:01.881053 # TAP version 13
2425 12:33:01.881487 # 1..2
2426 12:33:01.885481 # # Starting 2 tests from 2 test cases.
2427 12:33:01.891038 # # RUN global.wrong_timers_test ...
2428 12:33:01.896621 # # OK global.wrong_timers_test
2429 12:33:01.897179 # ok 1 global.wrong_timers_test
2430 12:33:01.902239 # # RUN timer_f.utimer ...
2431 12:33:01.907708 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2432 12:33:01.913276 # # utimer: Test terminated by assertion
2433 12:33:01.918812 # # FAIL timer_f.utimer
2434 12:33:01.919369 # not ok 2 timer_f.utimer
2435 12:33:01.924345 # # FAILED: 1 / 2 tests passed.
2436 12:33:01.931753 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2437 12:33:01.932348 not ok 4 selftests: alsa: utimer-test # exit=1
2438 12:33:02.745922 alsa_mixer-test_get_value_LCALTA_60 pass
2439 12:33:02.751321 alsa_mixer-test_name_LCALTA_60 pass
2440 12:33:02.751830 alsa_mixer-test_write_default_LCALTA_60 pass
2441 12:33:02.756828 alsa_mixer-test_write_valid_LCALTA_60 pass
2442 12:33:02.760286 alsa_mixer-test_write_invalid_LCALTA_60 pass
2443 12:33:02.765827 alsa_mixer-test_event_missing_LCALTA_60 pass
2444 12:33:02.771369 alsa_mixer-test_event_spurious_LCALTA_60 pass
2445 12:33:02.771851 alsa_mixer-test_get_value_LCALTA_59 pass
2446 12:33:02.776924 alsa_mixer-test_name_LCALTA_59 pass
2447 12:33:02.782518 alsa_mixer-test_write_default_LCALTA_59 pass
2448 12:33:02.783065 alsa_mixer-test_write_valid_LCALTA_59 pass
2449 12:33:02.788069 alsa_mixer-test_write_invalid_LCALTA_59 pass
2450 12:33:02.793596 alsa_mixer-test_event_missing_LCALTA_59 pass
2451 12:33:02.794082 alsa_mixer-test_event_spurious_LCALTA_59 pass
2452 12:33:02.799129 alsa_mixer-test_get_value_LCALTA_58 pass
2453 12:33:02.804692 alsa_mixer-test_name_LCALTA_58 pass
2454 12:33:02.805182 alsa_mixer-test_write_default_LCALTA_58 pass
2455 12:33:02.810308 alsa_mixer-test_write_valid_LCALTA_58 pass
2456 12:33:02.815831 alsa_mixer-test_write_invalid_LCALTA_58 pass
2457 12:33:02.821275 alsa_mixer-test_event_missing_LCALTA_58 pass
2458 12:33:02.821773 alsa_mixer-test_event_spurious_LCALTA_58 pass
2459 12:33:02.826844 alsa_mixer-test_get_value_LCALTA_57 pass
2460 12:33:02.832537 alsa_mixer-test_name_LCALTA_57 pass
2461 12:33:02.833079 alsa_mixer-test_write_default_LCALTA_57 pass
2462 12:33:02.838015 alsa_mixer-test_write_valid_LCALTA_57 pass
2463 12:33:02.843596 alsa_mixer-test_write_invalid_LCALTA_57 pass
2464 12:33:02.844183 alsa_mixer-test_event_missing_LCALTA_57 pass
2465 12:33:02.849162 alsa_mixer-test_event_spurious_LCALTA_57 pass
2466 12:33:02.854668 alsa_mixer-test_get_value_LCALTA_56 pass
2467 12:33:02.855213 alsa_mixer-test_name_LCALTA_56 pass
2468 12:33:02.860236 alsa_mixer-test_write_default_LCALTA_56 pass
2469 12:33:02.865760 alsa_mixer-test_write_valid_LCALTA_56 pass
2470 12:33:02.866303 alsa_mixer-test_write_invalid_LCALTA_56 pass
2471 12:33:02.871271 alsa_mixer-test_event_missing_LCALTA_56 pass
2472 12:33:02.876868 alsa_mixer-test_event_spurious_LCALTA_56 pass
2473 12:33:02.882420 alsa_mixer-test_get_value_LCALTA_55 pass
2474 12:33:02.882944 alsa_mixer-test_name_LCALTA_55 pass
2475 12:33:02.887947 alsa_mixer-test_write_default_LCALTA_55 pass
2476 12:33:02.893486 alsa_mixer-test_write_valid_LCALTA_55 pass
2477 12:33:02.894015 alsa_mixer-test_write_invalid_LCALTA_55 pass
2478 12:33:02.899038 alsa_mixer-test_event_missing_LCALTA_55 pass
2479 12:33:02.904578 alsa_mixer-test_event_spurious_LCALTA_55 pass
2480 12:33:02.905110 alsa_mixer-test_get_value_LCALTA_54 pass
2481 12:33:02.910136 alsa_mixer-test_name_LCALTA_54 pass
2482 12:33:02.915688 alsa_mixer-test_write_default_LCALTA_54 pass
2483 12:33:02.916243 alsa_mixer-test_write_valid_LCALTA_54 pass
2484 12:33:02.921203 alsa_mixer-test_write_invalid_LCALTA_54 pass
2485 12:33:02.926759 alsa_mixer-test_event_missing_LCALTA_54 pass
2486 12:33:02.932343 alsa_mixer-test_event_spurious_LCALTA_54 pass
2487 12:33:02.932909 alsa_mixer-test_get_value_LCALTA_53 pass
2488 12:33:02.937877 alsa_mixer-test_name_LCALTA_53 pass
2489 12:33:02.943341 alsa_mixer-test_write_default_LCALTA_53 pass
2490 12:33:02.943887 alsa_mixer-test_write_valid_LCALTA_53 pass
2491 12:33:02.948921 alsa_mixer-test_write_invalid_LCALTA_53 pass
2492 12:33:02.954490 alsa_mixer-test_event_missing_LCALTA_53 pass
2493 12:33:02.955038 alsa_mixer-test_event_spurious_LCALTA_53 pass
2494 12:33:02.960030 alsa_mixer-test_get_value_LCALTA_52 pass
2495 12:33:02.965539 alsa_mixer-test_name_LCALTA_52 pass
2496 12:33:02.966075 alsa_mixer-test_write_default_LCALTA_52 pass
2497 12:33:02.971101 alsa_mixer-test_write_valid_LCALTA_52 pass
2498 12:33:02.976629 alsa_mixer-test_write_invalid_LCALTA_52 pass
2499 12:33:02.977172 alsa_mixer-test_event_missing_LCALTA_52 pass
2500 12:33:02.982191 alsa_mixer-test_event_spurious_LCALTA_52 pass
2501 12:33:02.987719 alsa_mixer-test_get_value_LCALTA_51 pass
2502 12:33:02.988314 alsa_mixer-test_name_LCALTA_51 pass
2503 12:33:02.993263 alsa_mixer-test_write_default_LCALTA_51 pass
2504 12:33:02.998824 alsa_mixer-test_write_valid_LCALTA_51 pass
2505 12:33:03.004394 alsa_mixer-test_write_invalid_LCALTA_51 pass
2506 12:33:03.004927 alsa_mixer-test_event_missing_LCALTA_51 pass
2507 12:33:03.009908 alsa_mixer-test_event_spurious_LCALTA_51 pass
2508 12:33:03.015452 alsa_mixer-test_get_value_LCALTA_50 pass
2509 12:33:03.016018 alsa_mixer-test_name_LCALTA_50 pass
2510 12:33:03.020997 alsa_mixer-test_write_default_LCALTA_50 pass
2511 12:33:03.026541 alsa_mixer-test_write_valid_LCALTA_50 pass
2512 12:33:03.027076 alsa_mixer-test_write_invalid_LCALTA_50 pass
2513 12:33:03.032151 alsa_mixer-test_event_missing_LCALTA_50 pass
2514 12:33:03.037670 alsa_mixer-test_event_spurious_LCALTA_50 pass
2515 12:33:03.038221 alsa_mixer-test_get_value_LCALTA_49 pass
2516 12:33:03.043196 alsa_mixer-test_name_LCALTA_49 pass
2517 12:33:03.048773 alsa_mixer-test_write_default_LCALTA_49 pass
2518 12:33:03.049324 alsa_mixer-test_write_valid_LCALTA_49 pass
2519 12:33:03.054270 alsa_mixer-test_write_invalid_LCALTA_49 pass
2520 12:33:03.059829 alsa_mixer-test_event_missing_LCALTA_49 pass
2521 12:33:03.065411 alsa_mixer-test_event_spurious_LCALTA_49 pass
2522 12:33:03.065959 alsa_mixer-test_get_value_LCALTA_48 pass
2523 12:33:03.070921 alsa_mixer-test_name_LCALTA_48 pass
2524 12:33:03.076467 alsa_mixer-test_write_default_LCALTA_48 pass
2525 12:33:03.077005 alsa_mixer-test_write_valid_LCALTA_48 pass
2526 12:33:03.082004 alsa_mixer-test_write_invalid_LCALTA_48 pass
2527 12:33:03.087572 alsa_mixer-test_event_missing_LCALTA_48 pass
2528 12:33:03.088167 alsa_mixer-test_event_spurious_LCALTA_48 pass
2529 12:33:03.093114 alsa_mixer-test_get_value_LCALTA_47 pass
2530 12:33:03.098701 alsa_mixer-test_name_LCALTA_47 pass
2531 12:33:03.099255 alsa_mixer-test_write_default_LCALTA_47 pass
2532 12:33:03.104205 alsa_mixer-test_write_valid_LCALTA_47 pass
2533 12:33:03.109752 alsa_mixer-test_write_invalid_LCALTA_47 pass
2534 12:33:03.115320 alsa_mixer-test_event_missing_LCALTA_47 pass
2535 12:33:03.115900 alsa_mixer-test_event_spurious_LCALTA_47 pass
2536 12:33:03.120941 alsa_mixer-test_get_value_LCALTA_46 pass
2537 12:33:03.121494 alsa_mixer-test_name_LCALTA_46 pass
2538 12:33:03.126462 alsa_mixer-test_write_default_LCALTA_46 pass
2539 12:33:03.132051 alsa_mixer-test_write_valid_LCALTA_46 pass
2540 12:33:03.137558 alsa_mixer-test_write_invalid_LCALTA_46 pass
2541 12:33:03.138117 alsa_mixer-test_event_missing_LCALTA_46 pass
2542 12:33:03.143115 alsa_mixer-test_event_spurious_LCALTA_46 pass
2543 12:33:03.148680 alsa_mixer-test_get_value_LCALTA_45 pass
2544 12:33:03.149245 alsa_mixer-test_name_LCALTA_45 pass
2545 12:33:03.154211 alsa_mixer-test_write_default_LCALTA_45 pass
2546 12:33:03.159733 alsa_mixer-test_write_valid_LCALTA_45 pass
2547 12:33:03.160463 alsa_mixer-test_write_invalid_LCALTA_45 pass
2548 12:33:03.165316 alsa_mixer-test_event_missing_LCALTA_45 pass
2549 12:33:03.170862 alsa_mixer-test_event_spurious_LCALTA_45 pass
2550 12:33:03.176409 alsa_mixer-test_get_value_LCALTA_44 pass
2551 12:33:03.176962 alsa_mixer-test_name_LCALTA_44 pass
2552 12:33:03.181943 alsa_mixer-test_write_default_LCALTA_44 pass
2553 12:33:03.187498 alsa_mixer-test_write_valid_LCALTA_44 pass
2554 12:33:03.188099 alsa_mixer-test_write_invalid_LCALTA_44 pass
2555 12:33:03.193041 alsa_mixer-test_event_missing_LCALTA_44 pass
2556 12:33:03.198583 alsa_mixer-test_event_spurious_LCALTA_44 pass
2557 12:33:03.199134 alsa_mixer-test_get_value_LCALTA_43 pass
2558 12:33:03.204116 alsa_mixer-test_name_LCALTA_43 pass
2559 12:33:03.209697 alsa_mixer-test_write_default_LCALTA_43 pass
2560 12:33:03.210270 alsa_mixer-test_write_valid_LCALTA_43 pass
2561 12:33:03.215270 alsa_mixer-test_write_invalid_LCALTA_43 pass
2562 12:33:03.220754 alsa_mixer-test_event_missing_LCALTA_43 pass
2563 12:33:03.221297 alsa_mixer-test_event_spurious_LCALTA_43 pass
2564 12:33:03.226307 alsa_mixer-test_get_value_LCALTA_42 pass
2565 12:33:03.231882 alsa_mixer-test_name_LCALTA_42 pass
2566 12:33:03.232502 alsa_mixer-test_write_default_LCALTA_42 pass
2567 12:33:03.237394 alsa_mixer-test_write_valid_LCALTA_42 pass
2568 12:33:03.242961 alsa_mixer-test_write_invalid_LCALTA_42 pass
2569 12:33:03.248502 alsa_mixer-test_event_missing_LCALTA_42 pass
2570 12:33:03.249057 alsa_mixer-test_event_spurious_LCALTA_42 pass
2571 12:33:03.254032 alsa_mixer-test_get_value_LCALTA_41 pass
2572 12:33:03.259524 alsa_mixer-test_name_LCALTA_41 pass
2573 12:33:03.260100 alsa_mixer-test_write_default_LCALTA_41 pass
2574 12:33:03.265167 alsa_mixer-test_write_valid_LCALTA_41 pass
2575 12:33:03.270648 alsa_mixer-test_write_invalid_LCALTA_41 pass
2576 12:33:03.271214 alsa_mixer-test_event_missing_LCALTA_41 pass
2577 12:33:03.276207 alsa_mixer-test_event_spurious_LCALTA_41 pass
2578 12:33:03.281714 alsa_mixer-test_get_value_LCALTA_40 pass
2579 12:33:03.282252 alsa_mixer-test_name_LCALTA_40 pass
2580 12:33:03.287248 alsa_mixer-test_write_default_LCALTA_40 pass
2581 12:33:03.292822 alsa_mixer-test_write_valid_LCALTA_40 pass
2582 12:33:03.293366 alsa_mixer-test_write_invalid_LCALTA_40 pass
2583 12:33:03.298405 alsa_mixer-test_event_missing_LCALTA_40 pass
2584 12:33:03.303895 alsa_mixer-test_event_spurious_LCALTA_40 pass
2585 12:33:03.309398 alsa_mixer-test_get_value_LCALTA_39 pass
2586 12:33:03.309885 alsa_mixer-test_name_LCALTA_39 pass
2587 12:33:03.314978 alsa_mixer-test_write_default_LCALTA_39 pass
2588 12:33:03.320528 alsa_mixer-test_write_valid_LCALTA_39 pass
2589 12:33:03.321009 alsa_mixer-test_write_invalid_LCALTA_39 pass
2590 12:33:03.326129 alsa_mixer-test_event_missing_LCALTA_39 pass
2591 12:33:03.331626 alsa_mixer-test_event_spurious_LCALTA_39 pass
2592 12:33:03.332203 alsa_mixer-test_get_value_LCALTA_38 pass
2593 12:33:03.337173 alsa_mixer-test_name_LCALTA_38 pass
2594 12:33:03.342688 alsa_mixer-test_write_default_LCALTA_38 pass
2595 12:33:03.343182 alsa_mixer-test_write_valid_LCALTA_38 pass
2596 12:33:03.348264 alsa_mixer-test_write_invalid_LCALTA_38 pass
2597 12:33:03.353824 alsa_mixer-test_event_missing_LCALTA_38 pass
2598 12:33:03.359361 alsa_mixer-test_event_spurious_LCALTA_38 pass
2599 12:33:03.359844 alsa_mixer-test_get_value_LCALTA_37 pass
2600 12:33:03.364880 alsa_mixer-test_name_LCALTA_37 pass
2601 12:33:03.370455 alsa_mixer-test_write_default_LCALTA_37 pass
2602 12:33:03.370939 alsa_mixer-test_write_valid_LCALTA_37 pass
2603 12:33:03.376034 alsa_mixer-test_write_invalid_LCALTA_37 pass
2604 12:33:03.381592 alsa_mixer-test_event_missing_LCALTA_37 pass
2605 12:33:03.382208 alsa_mixer-test_event_spurious_LCALTA_37 pass
2606 12:33:03.387264 alsa_mixer-test_get_value_LCALTA_36 pass
2607 12:33:03.392683 alsa_mixer-test_name_LCALTA_36 pass
2608 12:33:03.393190 alsa_mixer-test_write_default_LCALTA_36 pass
2609 12:33:03.398189 alsa_mixer-test_write_valid_LCALTA_36 pass
2610 12:33:03.403771 alsa_mixer-test_write_invalid_LCALTA_36 pass
2611 12:33:03.404295 alsa_mixer-test_event_missing_LCALTA_36 pass
2612 12:33:03.409268 alsa_mixer-test_event_spurious_LCALTA_36 pass
2613 12:33:03.414826 alsa_mixer-test_get_value_LCALTA_35 pass
2614 12:33:03.415315 alsa_mixer-test_name_LCALTA_35 pass
2615 12:33:03.420342 alsa_mixer-test_write_default_LCALTA_35 pass
2616 12:33:03.425896 alsa_mixer-test_write_valid_LCALTA_35 pass
2617 12:33:03.431455 alsa_mixer-test_write_invalid_LCALTA_35 pass
2618 12:33:03.432018 alsa_mixer-test_event_missing_LCALTA_35 pass
2619 12:33:03.437083 alsa_mixer-test_event_spurious_LCALTA_35 pass
2620 12:33:03.442570 alsa_mixer-test_get_value_LCALTA_34 pass
2621 12:33:03.443051 alsa_mixer-test_name_LCALTA_34 pass
2622 12:33:03.448203 alsa_mixer-test_write_default_LCALTA_34 pass
2623 12:33:03.453672 alsa_mixer-test_write_valid_LCALTA_34 pass
2624 12:33:03.454151 alsa_mixer-test_write_invalid_LCALTA_34 pass
2625 12:33:03.459218 alsa_mixer-test_event_missing_LCALTA_34 pass
2626 12:33:03.464785 alsa_mixer-test_event_spurious_LCALTA_34 pass
2627 12:33:03.465283 alsa_mixer-test_get_value_LCALTA_33 pass
2628 12:33:03.470286 alsa_mixer-test_name_LCALTA_33 pass
2629 12:33:03.475833 alsa_mixer-test_write_default_LCALTA_33 pass
2630 12:33:03.476415 alsa_mixer-test_write_valid_LCALTA_33 pass
2631 12:33:03.481422 alsa_mixer-test_write_invalid_LCALTA_33 pass
2632 12:33:03.486960 alsa_mixer-test_event_missing_LCALTA_33 pass
2633 12:33:03.492473 alsa_mixer-test_event_spurious_LCALTA_33 pass
2634 12:33:03.492963 alsa_mixer-test_get_value_LCALTA_32 pass
2635 12:33:03.498035 alsa_mixer-test_name_LCALTA_32 pass
2636 12:33:03.503597 alsa_mixer-test_write_default_LCALTA_32 pass
2637 12:33:03.504108 alsa_mixer-test_write_valid_LCALTA_32 pass
2638 12:33:03.509167 alsa_mixer-test_write_invalid_LCALTA_32 pass
2639 12:33:03.514652 alsa_mixer-test_event_missing_LCALTA_32 pass
2640 12:33:03.515128 alsa_mixer-test_event_spurious_LCALTA_32 pass
2641 12:33:03.520214 alsa_mixer-test_get_value_LCALTA_31 pass
2642 12:33:03.525760 alsa_mixer-test_name_LCALTA_31 pass
2643 12:33:03.526245 alsa_mixer-test_write_default_LCALTA_31 pass
2644 12:33:03.531303 alsa_mixer-test_write_valid_LCALTA_31 pass
2645 12:33:03.536919 alsa_mixer-test_write_invalid_LCALTA_31 pass
2646 12:33:03.542420 alsa_mixer-test_event_missing_LCALTA_31 pass
2647 12:33:03.542921 alsa_mixer-test_event_spurious_LCALTA_31 pass
2648 12:33:03.547936 alsa_mixer-test_get_value_LCALTA_30 pass
2649 12:33:03.548467 alsa_mixer-test_name_LCALTA_30 pass
2650 12:33:03.553504 alsa_mixer-test_write_default_LCALTA_30 pass
2651 12:33:03.559125 alsa_mixer-test_write_valid_LCALTA_30 pass
2652 12:33:03.564649 alsa_mixer-test_write_invalid_LCALTA_30 pass
2653 12:33:03.565143 alsa_mixer-test_event_missing_LCALTA_30 pass
2654 12:33:03.570252 alsa_mixer-test_event_spurious_LCALTA_30 pass
2655 12:33:03.575751 alsa_mixer-test_get_value_LCALTA_29 pass
2656 12:33:03.576276 alsa_mixer-test_name_LCALTA_29 pass
2657 12:33:03.581294 alsa_mixer-test_write_default_LCALTA_29 pass
2658 12:33:03.586858 alsa_mixer-test_write_valid_LCALTA_29 pass
2659 12:33:03.587348 alsa_mixer-test_write_invalid_LCALTA_29 pass
2660 12:33:03.592376 alsa_mixer-test_event_missing_LCALTA_29 pass
2661 12:33:03.597913 alsa_mixer-test_event_spurious_LCALTA_29 pass
2662 12:33:03.603446 alsa_mixer-test_get_value_LCALTA_28 pass
2663 12:33:03.603929 alsa_mixer-test_name_LCALTA_28 pass
2664 12:33:03.609161 alsa_mixer-test_write_default_LCALTA_28 pass
2665 12:33:03.614586 alsa_mixer-test_write_valid_LCALTA_28 pass
2666 12:33:03.615073 alsa_mixer-test_write_invalid_LCALTA_28 pass
2667 12:33:03.620120 alsa_mixer-test_event_missing_LCALTA_28 pass
2668 12:33:03.625659 alsa_mixer-test_event_spurious_LCALTA_28 pass
2669 12:33:03.626140 alsa_mixer-test_get_value_LCALTA_27 pass
2670 12:33:03.631222 alsa_mixer-test_name_LCALTA_27 pass
2671 12:33:03.636754 alsa_mixer-test_write_default_LCALTA_27 pass
2672 12:33:03.637337 alsa_mixer-test_write_valid_LCALTA_27 pass
2673 12:33:03.642275 alsa_mixer-test_write_invalid_LCALTA_27 pass
2674 12:33:03.647843 alsa_mixer-test_event_missing_LCALTA_27 pass
2675 12:33:03.648366 alsa_mixer-test_event_spurious_LCALTA_27 pass
2676 12:33:03.653384 alsa_mixer-test_get_value_LCALTA_26 pass
2677 12:33:03.659008 alsa_mixer-test_name_LCALTA_26 pass
2678 12:33:03.659606 alsa_mixer-test_write_default_LCALTA_26 skip
2679 12:33:03.664488 alsa_mixer-test_write_valid_LCALTA_26 skip
2680 12:33:03.670028 alsa_mixer-test_write_invalid_LCALTA_26 skip
2681 12:33:03.675578 alsa_mixer-test_event_missing_LCALTA_26 pass
2682 12:33:03.676109 alsa_mixer-test_event_spurious_LCALTA_26 pass
2683 12:33:03.681142 alsa_mixer-test_get_value_LCALTA_25 pass
2684 12:33:03.686672 alsa_mixer-test_name_LCALTA_25 pass
2685 12:33:03.687160 alsa_mixer-test_write_default_LCALTA_25 pass
2686 12:33:03.692249 alsa_mixer-test_write_valid_LCALTA_25 skip
2687 12:33:03.697777 alsa_mixer-test_write_invalid_LCALTA_25 skip
2688 12:33:03.698261 alsa_mixer-test_event_missing_LCALTA_25 pass
2689 12:33:03.703288 alsa_mixer-test_event_spurious_LCALTA_25 pass
2690 12:33:03.708869 alsa_mixer-test_get_value_LCALTA_24 pass
2691 12:33:03.709354 alsa_mixer-test_name_LCALTA_24 pass
2692 12:33:03.714413 alsa_mixer-test_write_default_LCALTA_24 skip
2693 12:33:03.719940 alsa_mixer-test_write_valid_LCALTA_24 skip
2694 12:33:03.720450 alsa_mixer-test_write_invalid_LCALTA_24 skip
2695 12:33:03.725458 alsa_mixer-test_event_missing_LCALTA_24 pass
2696 12:33:03.731035 alsa_mixer-test_event_spurious_LCALTA_24 pass
2697 12:33:03.736614 alsa_mixer-test_get_value_LCALTA_23 pass
2698 12:33:03.737192 alsa_mixer-test_name_LCALTA_23 pass
2699 12:33:03.742176 alsa_mixer-test_write_default_LCALTA_23 skip
2700 12:33:03.747688 alsa_mixer-test_write_valid_LCALTA_23 skip
2701 12:33:03.748219 alsa_mixer-test_write_invalid_LCALTA_23 skip
2702 12:33:03.753258 alsa_mixer-test_event_missing_LCALTA_23 pass
2703 12:33:03.758762 alsa_mixer-test_event_spurious_LCALTA_23 pass
2704 12:33:03.759246 alsa_mixer-test_get_value_LCALTA_22 pass
2705 12:33:03.764315 alsa_mixer-test_name_LCALTA_22 pass
2706 12:33:03.769862 alsa_mixer-test_write_default_LCALTA_22 pass
2707 12:33:03.770347 alsa_mixer-test_write_valid_LCALTA_22 pass
2708 12:33:03.775397 alsa_mixer-test_write_invalid_LCALTA_22 pass
2709 12:33:03.780935 alsa_mixer-test_event_missing_LCALTA_22 pass
2710 12:33:03.786557 alsa_mixer-test_event_spurious_LCALTA_22 pass
2711 12:33:03.787037 alsa_mixer-test_get_value_LCALTA_21 pass
2712 12:33:03.792083 alsa_mixer-test_name_LCALTA_21 pass
2713 12:33:03.797590 alsa_mixer-test_write_default_LCALTA_21 pass
2714 12:33:03.798072 alsa_mixer-test_write_valid_LCALTA_21 pass
2715 12:33:03.803150 alsa_mixer-test_write_invalid_LCALTA_21 pass
2716 12:33:03.808694 alsa_mixer-test_event_missing_LCALTA_21 pass
2717 12:33:03.809186 alsa_mixer-test_event_spurious_LCALTA_21 pass
2718 12:33:03.814262 alsa_mixer-test_get_value_LCALTA_20 pass
2719 12:33:03.819730 alsa_mixer-test_name_LCALTA_20 pass
2720 12:33:03.820031 alsa_mixer-test_write_default_LCALTA_20 pass
2721 12:33:03.825292 alsa_mixer-test_write_valid_LCALTA_20 pass
2722 12:33:03.830923 alsa_mixer-test_write_invalid_LCALTA_20 pass
2723 12:33:03.831895 alsa_mixer-test_event_missing_LCALTA_20 pass
2724 12:33:03.836455 alsa_mixer-test_event_spurious_LCALTA_20 pass
2725 12:33:03.841948 alsa_mixer-test_get_value_LCALTA_19 pass
2726 12:33:03.842248 alsa_mixer-test_name_LCALTA_19 pass
2727 12:33:03.847534 alsa_mixer-test_write_default_LCALTA_19 pass
2728 12:33:03.852999 alsa_mixer-test_write_valid_LCALTA_19 pass
2729 12:33:03.858543 alsa_mixer-test_write_invalid_LCALTA_19 pass
2730 12:33:03.858805 alsa_mixer-test_event_missing_LCALTA_19 pass
2731 12:33:03.864264 alsa_mixer-test_event_spurious_LCALTA_19 pass
2732 12:33:03.869642 alsa_mixer-test_get_value_LCALTA_18 pass
2733 12:33:03.869918 alsa_mixer-test_name_LCALTA_18 pass
2734 12:33:03.875233 alsa_mixer-test_write_default_LCALTA_18 pass
2735 12:33:03.880768 alsa_mixer-test_write_valid_LCALTA_18 pass
2736 12:33:03.881041 alsa_mixer-test_write_invalid_LCALTA_18 pass
2737 12:33:03.886364 alsa_mixer-test_event_missing_LCALTA_18 pass
2738 12:33:03.891912 alsa_mixer-test_event_spurious_LCALTA_18 pass
2739 12:33:03.892516 alsa_mixer-test_get_value_LCALTA_17 pass
2740 12:33:03.897388 alsa_mixer-test_name_LCALTA_17 pass
2741 12:33:03.903026 alsa_mixer-test_write_default_LCALTA_17 pass
2742 12:33:03.904015 alsa_mixer-test_write_valid_LCALTA_17 pass
2743 12:33:03.908506 alsa_mixer-test_write_invalid_LCALTA_17 pass
2744 12:33:03.914010 alsa_mixer-test_event_missing_LCALTA_17 pass
2745 12:33:03.919669 alsa_mixer-test_event_spurious_LCALTA_17 pass
2746 12:33:03.920622 alsa_mixer-test_get_value_LCALTA_16 pass
2747 12:33:03.925203 alsa_mixer-test_name_LCALTA_16 pass
2748 12:33:03.930720 alsa_mixer-test_write_default_LCALTA_16 pass
2749 12:33:03.931379 alsa_mixer-test_write_valid_LCALTA_16 pass
2750 12:33:03.936259 alsa_mixer-test_write_invalid_LCALTA_16 pass
2751 12:33:03.941801 alsa_mixer-test_event_missing_LCALTA_16 pass
2752 12:33:03.942427 alsa_mixer-test_event_spurious_LCALTA_16 pass
2753 12:33:03.947353 alsa_mixer-test_get_value_LCALTA_15 pass
2754 12:33:03.952887 alsa_mixer-test_name_LCALTA_15 pass
2755 12:33:03.953492 alsa_mixer-test_write_default_LCALTA_15 pass
2756 12:33:03.958420 alsa_mixer-test_write_valid_LCALTA_15 pass
2757 12:33:03.964005 alsa_mixer-test_write_invalid_LCALTA_15 pass
2758 12:33:03.969539 alsa_mixer-test_event_missing_LCALTA_15 pass
2759 12:33:03.970126 alsa_mixer-test_event_spurious_LCALTA_15 pass
2760 12:33:03.975050 alsa_mixer-test_get_value_LCALTA_14 pass
2761 12:33:03.975633 alsa_mixer-test_name_LCALTA_14 pass
2762 12:33:03.980623 alsa_mixer-test_write_default_LCALTA_14 pass
2763 12:33:03.986163 alsa_mixer-test_write_valid_LCALTA_14 pass
2764 12:33:03.991747 alsa_mixer-test_write_invalid_LCALTA_14 pass
2765 12:33:03.992453 alsa_mixer-test_event_missing_LCALTA_14 pass
2766 12:33:03.997294 alsa_mixer-test_event_spurious_LCALTA_14 pass
2767 12:33:04.002845 alsa_mixer-test_get_value_LCALTA_13 pass
2768 12:33:04.003445 alsa_mixer-test_name_LCALTA_13 pass
2769 12:33:04.008367 alsa_mixer-test_write_default_LCALTA_13 pass
2770 12:33:04.013923 alsa_mixer-test_write_valid_LCALTA_13 pass
2771 12:33:04.014525 alsa_mixer-test_write_invalid_LCALTA_13 pass
2772 12:33:04.019504 alsa_mixer-test_event_missing_LCALTA_13 pass
2773 12:33:04.025010 alsa_mixer-test_event_spurious_LCALTA_13 pass
2774 12:33:04.030588 alsa_mixer-test_get_value_LCALTA_12 pass
2775 12:33:04.031204 alsa_mixer-test_name_LCALTA_12 pass
2776 12:33:04.036109 alsa_mixer-test_write_default_LCALTA_12 pass
2777 12:33:04.041662 alsa_mixer-test_write_valid_LCALTA_12 pass
2778 12:33:04.042271 alsa_mixer-test_write_invalid_LCALTA_12 pass
2779 12:33:04.047210 alsa_mixer-test_event_missing_LCALTA_12 pass
2780 12:33:04.052785 alsa_mixer-test_event_spurious_LCALTA_12 pass
2781 12:33:04.053490 alsa_mixer-test_get_value_LCALTA_11 pass
2782 12:33:04.058314 alsa_mixer-test_name_LCALTA_11 pass
2783 12:33:04.063852 alsa_mixer-test_write_default_LCALTA_11 pass
2784 12:33:04.064489 alsa_mixer-test_write_valid_LCALTA_11 pass
2785 12:33:04.069385 alsa_mixer-test_write_invalid_LCALTA_11 pass
2786 12:33:04.074901 alsa_mixer-test_event_missing_LCALTA_11 pass
2787 12:33:04.075490 alsa_mixer-test_event_spurious_LCALTA_11 pass
2788 12:33:04.080441 alsa_mixer-test_get_value_LCALTA_10 pass
2789 12:33:04.086028 alsa_mixer-test_name_LCALTA_10 pass
2790 12:33:04.086617 alsa_mixer-test_write_default_LCALTA_10 pass
2791 12:33:04.091588 alsa_mixer-test_write_valid_LCALTA_10 pass
2792 12:33:04.097139 alsa_mixer-test_write_invalid_LCALTA_10 pass
2793 12:33:04.102694 alsa_mixer-test_event_missing_LCALTA_10 pass
2794 12:33:04.103265 alsa_mixer-test_event_spurious_LCALTA_10 pass
2795 12:33:04.108240 alsa_mixer-test_get_value_LCALTA_9 pass
2796 12:33:04.113775 alsa_mixer-test_name_LCALTA_9 pass
2797 12:33:04.114406 alsa_mixer-test_write_default_LCALTA_9 pass
2798 12:33:04.119325 alsa_mixer-test_write_valid_LCALTA_9 pass
2799 12:33:04.124839 alsa_mixer-test_write_invalid_LCALTA_9 pass
2800 12:33:04.125435 alsa_mixer-test_event_missing_LCALTA_9 pass
2801 12:33:04.130384 alsa_mixer-test_event_spurious_LCALTA_9 pass
2802 12:33:04.135933 alsa_mixer-test_get_value_LCALTA_8 pass
2803 12:33:04.136561 alsa_mixer-test_name_LCALTA_8 pass
2804 12:33:04.141474 alsa_mixer-test_write_default_LCALTA_8 pass
2805 12:33:04.147048 alsa_mixer-test_write_valid_LCALTA_8 pass
2806 12:33:04.147632 alsa_mixer-test_write_invalid_LCALTA_8 pass
2807 12:33:04.152589 alsa_mixer-test_event_missing_LCALTA_8 pass
2808 12:33:04.158165 alsa_mixer-test_event_spurious_LCALTA_8 pass
2809 12:33:04.158818 alsa_mixer-test_get_value_LCALTA_7 pass
2810 12:33:04.163707 alsa_mixer-test_name_LCALTA_7 pass
2811 12:33:04.169257 alsa_mixer-test_write_default_LCALTA_7 pass
2812 12:33:04.169941 alsa_mixer-test_write_valid_LCALTA_7 pass
2813 12:33:04.174757 alsa_mixer-test_write_invalid_LCALTA_7 pass
2814 12:33:04.180321 alsa_mixer-test_event_missing_LCALTA_7 pass
2815 12:33:04.180972 alsa_mixer-test_event_spurious_LCALTA_7 pass
2816 12:33:04.185922 alsa_mixer-test_get_value_LCALTA_6 pass
2817 12:33:04.191412 alsa_mixer-test_name_LCALTA_6 pass
2818 12:33:04.192055 alsa_mixer-test_write_default_LCALTA_6 pass
2819 12:33:04.196974 alsa_mixer-test_write_valid_LCALTA_6 pass
2820 12:33:04.202504 alsa_mixer-test_write_invalid_LCALTA_6 pass
2821 12:33:04.203089 alsa_mixer-test_event_missing_LCALTA_6 pass
2822 12:33:04.208115 alsa_mixer-test_event_spurious_LCALTA_6 pass
2823 12:33:04.213640 alsa_mixer-test_get_value_LCALTA_5 pass
2824 12:33:04.214263 alsa_mixer-test_name_LCALTA_5 pass
2825 12:33:04.219161 alsa_mixer-test_write_default_LCALTA_5 pass
2826 12:33:04.224706 alsa_mixer-test_write_valid_LCALTA_5 pass
2827 12:33:04.225363 alsa_mixer-test_write_invalid_LCALTA_5 pass
2828 12:33:04.230245 alsa_mixer-test_event_missing_LCALTA_5 pass
2829 12:33:04.235764 alsa_mixer-test_event_spurious_LCALTA_5 pass
2830 12:33:04.236392 alsa_mixer-test_get_value_LCALTA_4 pass
2831 12:33:04.241318 alsa_mixer-test_name_LCALTA_4 pass
2832 12:33:04.246887 alsa_mixer-test_write_default_LCALTA_4 pass
2833 12:33:04.247484 alsa_mixer-test_write_valid_LCALTA_4 pass
2834 12:33:04.252414 alsa_mixer-test_write_invalid_LCALTA_4 pass
2835 12:33:04.257945 alsa_mixer-test_event_missing_LCALTA_4 pass
2836 12:33:04.263481 alsa_mixer-test_event_spurious_LCALTA_4 pass
2837 12:33:04.264103 alsa_mixer-test_get_value_LCALTA_3 pass
2838 12:33:04.269069 alsa_mixer-test_name_LCALTA_3 pass
2839 12:33:04.269659 alsa_mixer-test_write_default_LCALTA_3 pass
2840 12:33:04.274622 alsa_mixer-test_write_valid_LCALTA_3 pass
2841 12:33:04.280201 alsa_mixer-test_write_invalid_LCALTA_3 pass
2842 12:33:04.285676 alsa_mixer-test_event_missing_LCALTA_3 pass
2843 12:33:04.286271 alsa_mixer-test_event_spurious_LCALTA_3 pass
2844 12:33:04.291240 alsa_mixer-test_get_value_LCALTA_2 pass
2845 12:33:04.291936 alsa_mixer-test_name_LCALTA_2 pass
2846 12:33:04.296776 alsa_mixer-test_write_default_LCALTA_2 pass
2847 12:33:04.302426 alsa_mixer-test_write_valid_LCALTA_2 pass
2848 12:33:04.307922 alsa_mixer-test_write_invalid_LCALTA_2 pass
2849 12:33:04.308653 alsa_mixer-test_event_missing_LCALTA_2 pass
2850 12:33:04.313494 alsa_mixer-test_event_spurious_LCALTA_2 pass
2851 12:33:04.319010 alsa_mixer-test_get_value_LCALTA_1 pass
2852 12:33:04.319615 alsa_mixer-test_name_LCALTA_1 pass
2853 12:33:04.324548 alsa_mixer-test_write_default_LCALTA_1 pass
2854 12:33:04.330090 alsa_mixer-test_write_valid_LCALTA_1 pass
2855 12:33:04.330682 alsa_mixer-test_write_invalid_LCALTA_1 pass
2856 12:33:04.335634 alsa_mixer-test_event_missing_LCALTA_1 pass
2857 12:33:04.341176 alsa_mixer-test_event_spurious_LCALTA_1 pass
2858 12:33:04.341764 alsa_mixer-test_get_value_LCALTA_0 pass
2859 12:33:04.346713 alsa_mixer-test_name_LCALTA_0 pass
2860 12:33:04.352380 alsa_mixer-test_write_default_LCALTA_0 pass
2861 12:33:04.353056 alsa_mixer-test_write_valid_LCALTA_0 pass
2862 12:33:04.357832 alsa_mixer-test_write_invalid_LCALTA_0 pass
2863 12:33:04.363408 alsa_mixer-test_event_missing_LCALTA_0 pass
2864 12:33:04.364041 alsa_mixer-test_event_spurious_LCALTA_0 pass
2865 12:33:04.368924 alsa_mixer-test pass
2866 12:33:04.374489 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2867 12:33:04.375079 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2868 12:33:04.380034 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2869 12:33:04.385583 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2870 12:33:04.391092 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2871 12:33:04.396644 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2872 12:33:04.397237 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2873 12:33:04.402213 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2874 12:33:04.407734 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2875 12:33:04.413378 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2876 12:33:04.418835 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2877 12:33:04.424427 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2878 12:33:04.425095 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2879 12:33:04.429927 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2880 12:33:04.435490 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2881 12:33:04.441028 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2882 12:33:04.446567 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2883 12:33:04.452125 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2884 12:33:04.452983 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2885 12:33:04.457690 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2886 12:33:04.463210 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2887 12:33:04.468846 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2888 12:33:04.474423 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2889 12:33:04.479852 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2890 12:33:04.480649 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2891 12:33:04.485441 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2892 12:33:04.490931 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2893 12:33:04.496493 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2894 12:33:04.502026 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2895 12:33:04.507586 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2896 12:33:04.513162 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2897 12:33:04.513797 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2898 12:33:04.518741 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2899 12:33:04.524330 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2900 12:33:04.529848 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2901 12:33:04.535458 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2902 12:33:04.540933 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2903 12:33:04.541495 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2904 12:33:04.546519 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2905 12:33:04.552056 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2906 12:33:04.557575 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2907 12:33:04.563110 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2908 12:33:04.563657 alsa_pcm-test pass
2909 12:33:04.574174 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2910 12:33:04.579749 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2911 12:33:04.590820 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2912 12:33:04.596450 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2913 12:33:04.607449 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2914 12:33:04.608055 alsa_test-pcmtest-driver pass
2915 12:33:04.613019 alsa_utimer-test_global_wrong_timers_test pass
2916 12:33:04.618546 alsa_utimer-test_timer_f_utimer fail
2917 12:33:04.619088 alsa_utimer-test fail
2918 12:33:04.624142 + ../../utils/send-to-lava.sh ./output/result.txt
2919 12:33:04.629699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2920 12:33:04.630744 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2922 12:33:04.635245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2923 12:33:04.636083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2925 12:33:04.643069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2926 12:33:04.643893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2928 12:33:04.667833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2929 12:33:04.668738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2931 12:33:04.726916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2932 12:33:04.727789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2934 12:33:04.780861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2935 12:33:04.781725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2937 12:33:04.831892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2938 12:33:04.832817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2940 12:33:04.882839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2941 12:33:04.883699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2943 12:33:04.932600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2944 12:33:04.933480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2946 12:33:04.982823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2947 12:33:04.983740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2949 12:33:05.031479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2950 12:33:05.032381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2952 12:33:05.076644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2953 12:33:05.077496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2955 12:33:05.126496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2956 12:33:05.127342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2958 12:33:05.182487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2959 12:33:05.183362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2961 12:33:05.228912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2962 12:33:05.229791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2964 12:33:05.278787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2965 12:33:05.279685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2967 12:33:05.325564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2968 12:33:05.326452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2970 12:33:05.379722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2971 12:33:05.380662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2973 12:33:05.437566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2974 12:33:05.438673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2976 12:33:05.496556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2977 12:33:05.497411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2979 12:33:05.557743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2980 12:33:05.558591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2982 12:33:05.618246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2983 12:33:05.619097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2985 12:33:05.666935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2986 12:33:05.667779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2988 12:33:05.724242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2989 12:33:05.725069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2991 12:33:05.780531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2992 12:33:05.781379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2994 12:33:05.838209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2995 12:33:05.839056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2997 12:33:05.896330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2998 12:33:05.897149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3000 12:33:05.957189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3001 12:33:05.958247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3003 12:33:06.012188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3004 12:33:06.013077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3006 12:33:06.068622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3007 12:33:06.069459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3009 12:33:06.122350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3010 12:33:06.123171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3012 12:33:06.179402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3013 12:33:06.180283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3015 12:33:06.231552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3016 12:33:06.232477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3018 12:33:06.284277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3019 12:33:06.285133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3021 12:33:06.331421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3022 12:33:06.332304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3024 12:33:06.376145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3025 12:33:06.377001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3027 12:33:06.425171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3028 12:33:06.425996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3030 12:33:06.477185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3031 12:33:06.478020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3033 12:33:06.532220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3034 12:33:06.533045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3036 12:33:06.579266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3037 12:33:06.580094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3039 12:33:06.633438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3040 12:33:06.634296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3042 12:33:06.684292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3043 12:33:06.685121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3045 12:33:06.731265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3046 12:33:06.732093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3048 12:33:06.782323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3049 12:33:06.783211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3051 12:33:06.829432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3052 12:33:06.830349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3054 12:33:06.881793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3055 12:33:06.882721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3057 12:33:06.935127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3058 12:33:06.936054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3060 12:33:06.984895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3061 12:33:06.985844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3063 12:33:07.035594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3064 12:33:07.036643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3066 12:33:07.089381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3067 12:33:07.090321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3069 12:33:07.136292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3070 12:33:07.137255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3072 12:33:07.187957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3073 12:33:07.188953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3075 12:33:07.240322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3076 12:33:07.241253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3078 12:33:07.294229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3079 12:33:07.295165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3081 12:33:07.341280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3082 12:33:07.342108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3084 12:33:07.401465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3085 12:33:07.402327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3087 12:33:07.446635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3088 12:33:07.447426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3090 12:33:07.505432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3091 12:33:07.506211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3093 12:33:07.558404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3094 12:33:07.559203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3096 12:33:07.609370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3097 12:33:07.610152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3099 12:33:07.656391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3100 12:33:07.657261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3102 12:33:07.702627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3103 12:33:07.703214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3105 12:33:07.751532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3106 12:33:07.752149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3108 12:33:07.803280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3109 12:33:07.803938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3111 12:33:07.847210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3112 12:33:07.847860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3114 12:33:07.902384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3115 12:33:07.902984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3117 12:33:07.960470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3118 12:33:07.961051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3120 12:33:08.015908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3121 12:33:08.016518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3123 12:33:08.073123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3124 12:33:08.073728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3126 12:33:08.121263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3127 12:33:08.121841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3129 12:33:08.173061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3130 12:33:08.173626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3132 12:33:08.217641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3133 12:33:08.218199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3135 12:33:08.264767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3136 12:33:08.265332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3138 12:33:08.320059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3139 12:33:08.320675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3141 12:33:08.370134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3142 12:33:08.370709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3144 12:33:08.427164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3145 12:33:08.427789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3147 12:33:08.472960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3148 12:33:08.473839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3150 12:33:08.529272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3151 12:33:08.530120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3153 12:33:08.574795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3154 12:33:08.575402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3156 12:33:08.625234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3157 12:33:08.625865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3159 12:33:08.690435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3160 12:33:08.691046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3162 12:33:08.747017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3163 12:33:08.747601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3165 12:33:08.804395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3166 12:33:08.804996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3168 12:33:08.866032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3169 12:33:08.866655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3171 12:33:08.917909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3172 12:33:08.918521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3174 12:33:08.969754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3175 12:33:08.970622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3177 12:33:09.024955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3178 12:33:09.025823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3180 12:33:09.075062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3181 12:33:09.075954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3183 12:33:09.122377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3184 12:33:09.123266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3186 12:33:09.174650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3187 12:33:09.175532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3189 12:33:09.222061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3190 12:33:09.222963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3192 12:33:09.274766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3193 12:33:09.275638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3195 12:33:09.320572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3196 12:33:09.321416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3198 12:33:09.380020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3199 12:33:09.380866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3201 12:33:09.429914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3202 12:33:09.430761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3204 12:33:09.482489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3205 12:33:09.483338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3207 12:33:09.529530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3208 12:33:09.530388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3210 12:33:09.584545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3211 12:33:09.585391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3213 12:33:09.641449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3214 12:33:09.642309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3216 12:33:09.686626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3217 12:33:09.687478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3219 12:33:09.732115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3220 12:33:09.732947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3222 12:33:09.782265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3223 12:33:09.783106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3225 12:33:09.829680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3226 12:33:09.830507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3228 12:33:09.875008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3229 12:33:09.875839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3231 12:33:09.922630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3232 12:33:09.923460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3234 12:33:09.967412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3235 12:33:09.968265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3237 12:33:10.016568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3238 12:33:10.017482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3240 12:33:10.066990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3241 12:33:10.067613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3243 12:33:10.121947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3244 12:33:10.122854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3246 12:33:10.173477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3247 12:33:10.174335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3249 12:33:10.232977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3250 12:33:10.233824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3252 12:33:10.289215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3253 12:33:10.290043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3255 12:33:10.335482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3256 12:33:10.336334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3258 12:33:10.392161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3259 12:33:10.392992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3261 12:33:10.444480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3262 12:33:10.445293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3264 12:33:10.499067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3265 12:33:10.499897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3267 12:33:10.550373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3268 12:33:10.551197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3270 12:33:10.594971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3271 12:33:10.595785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3273 12:33:10.657792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3274 12:33:10.658343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3276 12:33:10.704062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3277 12:33:10.704909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3279 12:33:10.754310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3280 12:33:10.755186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3282 12:33:10.799493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3283 12:33:10.800404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3285 12:33:10.858064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3286 12:33:10.858673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3288 12:33:10.899297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3289 12:33:10.900144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3291 12:33:10.957829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3292 12:33:10.958672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3294 12:33:11.003236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3295 12:33:11.004087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3297 12:33:11.057044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3298 12:33:11.057767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3300 12:33:11.115570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3301 12:33:11.116569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3303 12:33:11.166909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3304 12:33:11.167574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3306 12:33:11.216138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3307 12:33:11.216780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3309 12:33:11.269946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3310 12:33:11.270808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3312 12:33:11.313175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3313 12:33:11.314020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3315 12:33:11.362867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3316 12:33:11.363687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3318 12:33:11.410574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3319 12:33:11.411429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3321 12:33:11.455855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3322 12:33:11.456726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3324 12:33:11.512233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3325 12:33:11.513087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3327 12:33:11.558901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3328 12:33:11.559710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3330 12:33:11.612561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3331 12:33:11.613408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3333 12:33:11.664855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3334 12:33:11.665709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3336 12:33:11.716307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3337 12:33:11.717144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3339 12:33:11.766336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3340 12:33:11.767169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3342 12:33:11.813321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3343 12:33:11.814151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3345 12:33:11.871499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3346 12:33:11.872378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3348 12:33:11.921184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3349 12:33:11.922043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3351 12:33:11.967217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3352 12:33:11.968079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3354 12:33:12.026832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3355 12:33:12.027677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3357 12:33:12.080684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3358 12:33:12.081536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3360 12:33:12.138361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3361 12:33:12.139200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3363 12:33:12.190919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3364 12:33:12.191740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3366 12:33:12.243106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3367 12:33:12.243929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3369 12:33:12.296988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3370 12:33:12.297744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3372 12:33:12.345909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3373 12:33:12.346561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3375 12:33:12.392478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3376 12:33:12.393167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3378 12:33:12.435141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3379 12:33:12.435801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3381 12:33:12.477876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3382 12:33:12.478524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3384 12:33:12.526621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3385 12:33:12.527573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3387 12:33:12.581775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3388 12:33:12.582729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3390 12:33:12.630202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3391 12:33:12.631111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3393 12:33:12.677117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3394 12:33:12.678001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3396 12:33:12.731768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3397 12:33:12.732732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3399 12:33:12.778363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3400 12:33:12.779233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3402 12:33:12.830273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3403 12:33:12.831157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3405 12:33:12.876805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3406 12:33:12.877788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3408 12:33:12.922375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3409 12:33:12.923402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3411 12:33:12.983190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3412 12:33:12.984100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3414 12:33:13.030540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3415 12:33:13.031430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3417 12:33:13.076789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3418 12:33:13.077607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3420 12:33:13.123060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3421 12:33:13.123813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3423 12:33:13.174506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3424 12:33:13.175343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3426 12:33:13.218230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3427 12:33:13.219077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3429 12:33:13.273123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3430 12:33:13.273981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3432 12:33:13.321887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3433 12:33:13.322759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3435 12:33:13.374040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3436 12:33:13.375039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3438 12:33:13.426931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3439 12:33:13.427854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3441 12:33:13.481891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3442 12:33:13.482732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3444 12:33:13.535097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3445 12:33:13.535928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3447 12:33:13.587670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3448 12:33:13.588525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3450 12:33:13.639957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3451 12:33:13.640798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3453 12:33:13.698402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3454 12:33:13.699181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3456 12:33:13.754830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3457 12:33:13.755590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3459 12:33:13.803582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3460 12:33:13.804394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3462 12:33:13.853506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3463 12:33:13.854639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3465 12:33:13.904820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3466 12:33:13.905989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3468 12:33:13.957618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3469 12:33:13.958696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3471 12:33:14.009545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3472 12:33:14.010703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3474 12:33:14.063464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3475 12:33:14.064558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3477 12:33:14.116334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3478 12:33:14.117389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3480 12:33:14.169598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3481 12:33:14.170767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3483 12:33:14.216345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3484 12:33:14.217620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3486 12:33:14.265357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3487 12:33:14.266578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3489 12:33:14.321764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3490 12:33:14.322955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3492 12:33:14.373094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3493 12:33:14.373730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3495 12:33:14.429565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3496 12:33:14.430532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3498 12:33:14.478644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3499 12:33:14.479298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3501 12:33:14.535113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3502 12:33:14.535755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3504 12:33:14.594183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3505 12:33:14.594828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3507 12:33:14.642592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3508 12:33:14.643228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3510 12:33:14.693664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3511 12:33:14.694287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3513 12:33:14.751037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3514 12:33:14.751658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3516 12:33:14.803533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3517 12:33:14.804168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3519 12:33:14.853774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3520 12:33:14.854442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3522 12:33:14.907016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3523 12:33:14.908334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3525 12:33:14.961049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3526 12:33:14.961713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3528 12:33:15.015586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3529 12:33:15.016257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3531 12:33:15.070499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3532 12:33:15.071125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3534 12:33:15.120650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3535 12:33:15.121281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3537 12:33:15.167714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3538 12:33:15.168550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3540 12:33:15.223940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3541 12:33:15.224715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3543 12:33:15.273441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3544 12:33:15.274088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3546 12:33:15.325247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3547 12:33:15.325920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3549 12:33:15.368959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3550 12:33:15.369801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3552 12:33:15.413636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3553 12:33:15.414350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3555 12:33:15.462072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3556 12:33:15.462973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3558 12:33:15.509753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3559 12:33:15.510650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3561 12:33:15.569620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3562 12:33:15.570508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3564 12:33:15.622143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3565 12:33:15.622975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3567 12:33:15.675114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3568 12:33:15.676306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3570 12:33:15.729217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3571 12:33:15.730059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3573 12:33:15.783630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3574 12:33:15.784515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3576 12:33:15.843135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3577 12:33:15.844040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3579 12:33:15.898796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3580 12:33:15.899411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3582 12:33:15.944063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3583 12:33:15.944663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3585 12:33:15.999540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3586 12:33:16.000153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3588 12:33:16.045043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3589 12:33:16.045646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3591 12:33:16.094585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3592 12:33:16.095211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3594 12:33:16.148939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3595 12:33:16.149573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3597 12:33:16.205160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3598 12:33:16.205793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3600 12:33:16.255745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3601 12:33:16.256413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3603 12:33:16.303191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3604 12:33:16.303857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3606 12:33:16.348737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3607 12:33:16.349367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3609 12:33:16.393441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3610 12:33:16.394070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3612 12:33:16.439338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3613 12:33:16.440202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3615 12:33:16.496782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3616 12:33:16.497601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3618 12:33:16.550744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3619 12:33:16.551494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3621 12:33:16.597721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3622 12:33:16.598449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3624 12:33:16.648429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3625 12:33:16.649136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3627 12:33:16.700300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3628 12:33:16.700999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3630 12:33:16.752170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3631 12:33:16.752875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3633 12:33:16.804183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3634 12:33:16.805006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3636 12:33:16.848805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3637 12:33:16.849529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3639 12:33:16.902936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3640 12:33:16.903647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3642 12:33:16.947492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3643 12:33:16.948206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3645 12:33:16.995817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3646 12:33:16.996593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3648 12:33:17.041537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3649 12:33:17.042254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3651 12:33:17.091582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3652 12:33:17.092332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3654 12:33:17.143191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3655 12:33:17.143896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3657 12:33:17.188680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3658 12:33:17.189380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3660 12:33:17.235481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3661 12:33:17.236193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3663 12:33:17.287008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3664 12:33:17.287696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3666 12:33:17.331784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3667 12:33:17.332500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3669 12:33:17.386079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3670 12:33:17.386769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3672 12:33:17.432268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3673 12:33:17.432967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3675 12:33:17.487501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3676 12:33:17.488259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3678 12:33:17.535718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3679 12:33:17.536426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3681 12:33:17.589583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3682 12:33:17.590256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3684 12:33:17.643585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3685 12:33:17.644299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3687 12:33:17.691914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3688 12:33:17.692640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3690 12:33:17.738918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3691 12:33:17.739608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3693 12:33:17.786750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3694 12:33:17.787448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3696 12:33:17.842415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3697 12:33:17.843156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3699 12:33:17.901880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3700 12:33:17.902578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3702 12:33:17.946805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3703 12:33:17.947379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3705 12:33:18.007065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3706 12:33:18.007913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3708 12:33:18.065183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3709 12:33:18.066145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3711 12:33:18.115064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3712 12:33:18.115736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3714 12:33:18.181365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3715 12:33:18.182259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3717 12:33:18.233450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3718 12:33:18.234319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3720 12:33:18.289714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3721 12:33:18.290583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3723 12:33:18.336845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3724 12:33:18.337515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3726 12:33:18.396411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3727 12:33:18.397348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3729 12:33:18.449211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3730 12:33:18.450083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3732 12:33:18.496837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3733 12:33:18.497756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3735 12:33:18.547974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3736 12:33:18.548896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3738 12:33:18.591106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3739 12:33:18.591975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3741 12:33:18.640924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3742 12:33:18.641787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3744 12:33:18.690121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3745 12:33:18.690968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3747 12:33:18.742054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3748 12:33:18.742906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3750 12:33:18.793804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3751 12:33:18.796164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3753 12:33:18.853725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3754 12:33:18.854959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3756 12:33:18.907065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3757 12:33:18.908354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3759 12:33:18.961322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3760 12:33:18.962466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3762 12:33:19.017578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3763 12:33:19.018674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3765 12:33:19.068956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3766 12:33:19.070109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3768 12:33:19.122745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3769 12:33:19.123923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3771 12:33:19.180747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3772 12:33:19.181877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3774 12:33:19.230392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3775 12:33:19.231501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3777 12:33:19.282406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3778 12:33:19.283584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3780 12:33:19.339680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3781 12:33:19.340884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3783 12:33:19.391378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3784 12:33:19.392584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3786 12:33:19.442557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3787 12:33:19.443790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3789 12:33:19.497384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3790 12:33:19.498568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3792 12:33:19.544845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3793 12:33:19.545976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3795 12:33:19.597561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3796 12:33:19.598693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3798 12:33:19.654837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3799 12:33:19.656015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3801 12:33:19.713794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3802 12:33:19.714922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3804 12:33:19.767783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3805 12:33:19.768850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3807 12:33:19.822828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3808 12:33:19.823630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3810 12:33:19.873980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3811 12:33:19.874800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3813 12:33:19.925555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3814 12:33:19.926381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3816 12:33:19.979004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3817 12:33:19.979824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3819 12:33:20.038769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3820 12:33:20.039686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3822 12:33:20.095094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3823 12:33:20.096026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3825 12:33:20.155890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3826 12:33:20.156797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3828 12:33:20.208583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3829 12:33:20.209439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3831 12:33:20.262284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3832 12:33:20.263170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3834 12:33:20.317139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3835 12:33:20.318270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3837 12:33:20.375623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3838 12:33:20.376487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3840 12:33:20.434727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3841 12:33:20.435554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3843 12:33:20.491375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3844 12:33:20.492205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3846 12:33:20.535572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3847 12:33:20.536458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3849 12:33:20.590932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3850 12:33:20.591742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3852 12:33:20.644711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3853 12:33:20.645558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3855 12:33:20.691534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3856 12:33:20.692378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3858 12:33:20.742021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3859 12:33:20.742877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3861 12:33:20.802163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3862 12:33:20.802994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3864 12:33:20.854847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3865 12:33:20.856174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3867 12:33:20.906297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3868 12:33:20.907207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3870 12:33:20.963672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3871 12:33:20.964618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3873 12:33:21.020867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3874 12:33:21.021779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3876 12:33:21.085019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3877 12:33:21.085975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3879 12:33:21.139768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3880 12:33:21.140743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3882 12:33:21.204406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3883 12:33:21.205355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3885 12:33:21.262750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3886 12:33:21.263543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3888 12:33:21.316124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3889 12:33:21.316895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3891 12:33:21.367483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3892 12:33:21.368316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3894 12:33:21.426896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3895 12:33:21.427671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3897 12:33:21.471385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3898 12:33:21.472147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3900 12:33:21.525271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3901 12:33:21.526070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3903 12:33:21.595724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3904 12:33:21.596607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3906 12:33:21.648632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3907 12:33:21.649417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3909 12:33:21.699721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3910 12:33:21.700598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3912 12:33:21.760908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3913 12:33:21.761693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3915 12:33:21.826484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3916 12:33:21.827292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3918 12:33:21.877773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3919 12:33:21.878575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3921 12:33:21.927827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3922 12:33:21.928643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3924 12:33:21.979417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3925 12:33:21.980184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3927 12:33:22.038042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3928 12:33:22.038817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3930 12:33:22.097624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3931 12:33:22.098395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3933 12:33:22.147912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3934 12:33:22.148786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3936 12:33:22.203436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3937 12:33:22.204318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3939 12:33:22.261082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3940 12:33:22.261865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3942 12:33:22.320942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3943 12:33:22.321714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3945 12:33:22.377587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3946 12:33:22.378375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3948 12:33:22.429380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3949 12:33:22.430143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3951 12:33:22.487721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3952 12:33:22.488561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3954 12:33:22.533242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3955 12:33:22.534114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3957 12:33:22.591685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3958 12:33:22.592688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3960 12:33:22.641159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3961 12:33:22.642001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3963 12:33:22.691777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3964 12:33:22.692677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3966 12:33:22.750320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3967 12:33:22.751121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3969 12:33:22.809645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3970 12:33:22.810435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3972 12:33:22.861514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3973 12:33:22.862285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3975 12:33:22.917137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3976 12:33:22.917911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3978 12:33:22.971557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3979 12:33:22.972370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3981 12:33:23.028435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3982 12:33:23.029189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3984 12:33:23.079261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3985 12:33:23.080140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3987 12:33:23.140672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3988 12:33:23.141498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3990 12:33:23.192793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3991 12:33:23.193615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3993 12:33:23.248312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3994 12:33:23.249246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3996 12:33:23.300799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3997 12:33:23.301651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
3999 12:33:23.367526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4000 12:33:23.368419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4002 12:33:23.421650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4003 12:33:23.422492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4005 12:33:23.482504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4006 12:33:23.483363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4008 12:33:23.535799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4009 12:33:23.536655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4011 12:33:23.588485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4012 12:33:23.589397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4014 12:33:23.636516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4015 12:33:23.637105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4017 12:33:23.694810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4018 12:33:23.695708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4020 12:33:23.748507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4021 12:33:23.749117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4023 12:33:23.798107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4024 12:33:23.798742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4026 12:33:23.847671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4027 12:33:23.848348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4029 12:33:23.892937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4030 12:33:23.893561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4032 12:33:23.951074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4033 12:33:23.951732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4035 12:33:23.999809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4036 12:33:24.000455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4038 12:33:24.051213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4039 12:33:24.051839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4041 12:33:24.109854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4042 12:33:24.110467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4044 12:33:24.168064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4045 12:33:24.168673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4047 12:33:24.222467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4048 12:33:24.223060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4050 12:33:24.276443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4051 12:33:24.277036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4053 12:33:24.321967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4054 12:33:24.322539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4056 12:33:24.375118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4057 12:33:24.375671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4059 12:33:24.426137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4060 12:33:24.426699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4062 12:33:24.491380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4063 12:33:24.492005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4065 12:33:24.543171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4066 12:33:24.543830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4068 12:33:24.603501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4069 12:33:24.604525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4071 12:33:24.656790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4072 12:33:24.658608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4074 12:33:24.709949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4075 12:33:24.710719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4077 12:33:24.781029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4078 12:33:24.781755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4080 12:33:24.840754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4081 12:33:24.841417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4083 12:33:24.898509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4084 12:33:24.899174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4086 12:33:24.954560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4087 12:33:24.955475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4089 12:33:25.052388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4090 12:33:25.053038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4092 12:33:25.126696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4093 12:33:25.127312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4095 12:33:25.185919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4096 12:33:25.186607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4098 12:33:25.264381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4099 12:33:25.265204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4101 12:33:25.335288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4102 12:33:25.335948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4104 12:33:25.383590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4105 12:33:25.384301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4107 12:33:25.441255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4108 12:33:25.441942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4110 12:33:25.508862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4111 12:33:25.509679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4113 12:33:25.565813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4114 12:33:25.566665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4116 12:33:25.619461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4117 12:33:25.620120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4119 12:33:25.678843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4120 12:33:25.679494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4122 12:33:25.736814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4123 12:33:25.738056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4125 12:33:25.795743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4126 12:33:25.796485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4128 12:33:25.851254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4129 12:33:25.851947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4131 12:33:25.904544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4132 12:33:25.905807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4134 12:33:25.974860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4135 12:33:25.976050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4137 12:33:26.161940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4138 12:33:26.162885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4140 12:33:26.227224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4141 12:33:26.227902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4143 12:33:26.285518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4144 12:33:26.286204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4146 12:33:26.342400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4147 12:33:26.343077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4149 12:33:26.405886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4150 12:33:26.406520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4152 12:33:26.474806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4153 12:33:26.475432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4155 12:33:26.538166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4156 12:33:26.538865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4158 12:33:26.595182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4159 12:33:26.595881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4161 12:33:26.661418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4162 12:33:26.662082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4164 12:33:26.718027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4165 12:33:26.718718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4167 12:33:26.780787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4168 12:33:26.781471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4170 12:33:26.842042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4171 12:33:26.842764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4173 12:33:26.895715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4174 12:33:26.896725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4176 12:33:26.948758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4177 12:33:26.949749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4179 12:33:27.003007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4180 12:33:27.003886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4182 12:33:27.052815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4183 12:33:27.053680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4185 12:33:27.105015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4186 12:33:27.105901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4188 12:33:27.161069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4189 12:33:27.161946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4191 12:33:27.217002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4192 12:33:27.217915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4194 12:33:27.279667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4195 12:33:27.280319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4197 12:33:27.331594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4198 12:33:27.332212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4200 12:33:27.387840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4201 12:33:27.388470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4203 12:33:27.440530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4205 12:33:27.443471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4206 12:33:27.498122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4207 12:33:27.498773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4209 12:33:27.543285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4210 12:33:27.543924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4212 12:33:27.600395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4213 12:33:27.600977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4215 12:33:27.651776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4216 12:33:27.652377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4218 12:33:27.701502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4219 12:33:27.702111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4221 12:33:27.750777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4222 12:33:27.751390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4224 12:33:27.802757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4225 12:33:27.803377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4227 12:33:27.848904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4228 12:33:27.849530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4230 12:33:27.896219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4231 12:33:27.896783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4233 12:33:27.950366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4234 12:33:27.950982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4236 12:33:28.003153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4237 12:33:28.003763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4239 12:33:28.054269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4240 12:33:28.054863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4242 12:33:28.115367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4243 12:33:28.116014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4245 12:33:28.160122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4246 12:33:28.160713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4248 12:33:28.206006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4249 12:33:28.206583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4251 12:33:28.257866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4252 12:33:28.258443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4254 12:33:28.302633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4255 12:33:28.303186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4257 12:33:28.354494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4258 12:33:28.355127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4260 12:33:28.400883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4261 12:33:28.401540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4263 12:33:28.449245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4264 12:33:28.449902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4266 12:33:28.496450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4267 12:33:28.497106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4269 12:33:28.550361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4270 12:33:28.550942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4272 12:33:28.605135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4273 12:33:28.605720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4275 12:33:28.651104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4276 12:33:28.651705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4278 12:33:28.701893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4279 12:33:28.702494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4281 12:33:28.760989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4282 12:33:28.761676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4284 12:33:28.813551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4285 12:33:28.814310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4287 12:33:28.861811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4288 12:33:28.862529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4290 12:33:28.910547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4291 12:33:28.911234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4293 12:33:28.961700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4294 12:33:28.962363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4296 12:33:29.015859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4297 12:33:29.016499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4299 12:33:29.061500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4300 12:33:29.062101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4302 12:33:29.123833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4303 12:33:29.124424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4305 12:33:29.178488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4306 12:33:29.179098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4308 12:33:29.242555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4309 12:33:29.243140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4311 12:33:29.300093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4312 12:33:29.300677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4314 12:33:29.344913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4315 12:33:29.345496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4317 12:33:29.409877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4318 12:33:29.410408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4320 12:33:29.456849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4321 12:33:29.457399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4323 12:33:29.507279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4324 12:33:29.507816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4326 12:33:29.566927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4327 12:33:29.567477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4329 12:33:29.630659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4330 12:33:29.631218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4332 12:33:29.680121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4333 12:33:29.680655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4335 12:33:29.748153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4336 12:33:29.748688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4338 12:33:29.794411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4339 12:33:29.794956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4341 12:33:29.845306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4342 12:33:29.845863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4344 12:33:29.888400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4345 12:33:29.888934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4347 12:33:29.946379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4348 12:33:29.946902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4350 12:33:29.991485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4351 12:33:29.992024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4353 12:33:30.048260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4354 12:33:30.048782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4356 12:33:30.100235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4357 12:33:30.100771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4359 12:33:30.142732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4361 12:33:30.147942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4362 12:33:30.148216 + set +x
4363 12:33:30.156215 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 826935_1.6.2.4.5>
4364 12:33:30.156588 <LAVA_TEST_RUNNER EXIT>
4365 12:33:30.157110 Received signal: <ENDRUN> 1_kselftest-alsa 826935_1.6.2.4.5
4366 12:33:30.157460 Ending use of test pattern.
4367 12:33:30.157687 Ending test lava.1_kselftest-alsa (826935_1.6.2.4.5), duration 41.10
4369 12:33:30.158469 ok: lava_test_shell seems to have completed
4370 12:33:30.170043 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4371 12:33:30.171147 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4372 12:33:30.171595 end: 3 lava-test-retry (duration 00:00:42) [common]
4373 12:33:30.172069 start: 4 finalize (timeout 00:06:03) [common]
4374 12:33:30.172515 start: 4.1 power-off (timeout 00:00:30) [common]
4375 12:33:30.173148 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4376 12:33:30.205464 >> OK - accepted request
4377 12:33:30.207299 Returned 0 in 0 seconds
4378 12:33:30.308260 end: 4.1 power-off (duration 00:00:00) [common]
4380 12:33:30.309541 start: 4.2 read-feedback (timeout 00:06:03) [common]
4381 12:33:30.310331 Listened to connection for namespace 'common' for up to 1s
4382 12:33:31.311245 Finalising connection for namespace 'common'
4383 12:33:31.316235 Disconnecting from shell: Finalise
4384 12:33:31.316834 / #
4385 12:33:31.417760 end: 4.2 read-feedback (duration 00:00:01) [common]
4386 12:33:31.418498 end: 4 finalize (duration 00:00:01) [common]
4387 12:33:31.419146 Cleaning after the job
4388 12:33:31.419724 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/ramdisk
4389 12:33:31.423177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/kernel
4390 12:33:31.430535 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/dtb
4391 12:33:31.431813 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/nfsrootfs
4392 12:33:31.484619 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826935/tftp-deploy-xv3srcgq/modules
4393 12:33:31.491697 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/826935
4394 12:33:34.531177 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/826935
4395 12:33:34.531732 Job finished correctly