Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 12:25:12.983481 lava-dispatcher, installed at version: 2024.01
2 12:25:12.984329 start: 0 validate
3 12:25:12.984830 Start time: 2024-10-09 12:25:12.984799+00:00 (UTC)
4 12:25:12.985373 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 12:25:12.985916 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 12:25:13.027836 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 12:25:13.028407 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-7-g556be13a9b36%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 12:25:13.060632 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 12:25:13.061272 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-7-g556be13a9b36%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 12:25:13.089465 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 12:25:13.089974 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:25:13.125254 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 12:25:13.125768 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-7-g556be13a9b36%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 12:25:13.165516 validate duration: 0.18
16 12:25:13.166987 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:25:13.167588 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:25:13.168209 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:25:13.169279 Not decompressing ramdisk as can be used compressed.
20 12:25:13.170046 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 12:25:13.170563 saving as /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/ramdisk/initrd.cpio.gz
22 12:25:13.171078 total size: 5628169 (5 MB)
23 12:25:13.217840 progress 0 % (0 MB)
24 12:25:13.225942 progress 5 % (0 MB)
25 12:25:13.233387 progress 10 % (0 MB)
26 12:25:13.237714 progress 15 % (0 MB)
27 12:25:13.242258 progress 20 % (1 MB)
28 12:25:13.246358 progress 25 % (1 MB)
29 12:25:13.250882 progress 30 % (1 MB)
30 12:25:13.255307 progress 35 % (1 MB)
31 12:25:13.259341 progress 40 % (2 MB)
32 12:25:13.263876 progress 45 % (2 MB)
33 12:25:13.268064 progress 50 % (2 MB)
34 12:25:13.272584 progress 55 % (2 MB)
35 12:25:13.277074 progress 60 % (3 MB)
36 12:25:13.281096 progress 65 % (3 MB)
37 12:25:13.285631 progress 70 % (3 MB)
38 12:25:13.291372 progress 75 % (4 MB)
39 12:25:13.295502 progress 80 % (4 MB)
40 12:25:13.299142 progress 85 % (4 MB)
41 12:25:13.303252 progress 90 % (4 MB)
42 12:25:13.307293 progress 95 % (5 MB)
43 12:25:13.310680 progress 100 % (5 MB)
44 12:25:13.311365 5 MB downloaded in 0.14 s (38.26 MB/s)
45 12:25:13.311915 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:25:13.312950 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:25:13.313251 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:25:13.313526 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:25:13.314009 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/kernel/Image
51 12:25:13.314264 saving as /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/kernel/Image
52 12:25:13.314476 total size: 45713920 (43 MB)
53 12:25:13.314689 No compression specified
54 12:25:13.348189 progress 0 % (0 MB)
55 12:25:13.377186 progress 5 % (2 MB)
56 12:25:13.405764 progress 10 % (4 MB)
57 12:25:13.434987 progress 15 % (6 MB)
58 12:25:13.464162 progress 20 % (8 MB)
59 12:25:13.493200 progress 25 % (10 MB)
60 12:25:13.522425 progress 30 % (13 MB)
61 12:25:13.551533 progress 35 % (15 MB)
62 12:25:13.580500 progress 40 % (17 MB)
63 12:25:13.609345 progress 45 % (19 MB)
64 12:25:13.638704 progress 50 % (21 MB)
65 12:25:13.667896 progress 55 % (24 MB)
66 12:25:13.697279 progress 60 % (26 MB)
67 12:25:13.725982 progress 65 % (28 MB)
68 12:25:13.755093 progress 70 % (30 MB)
69 12:25:13.784091 progress 75 % (32 MB)
70 12:25:13.817242 progress 80 % (34 MB)
71 12:25:13.846331 progress 85 % (37 MB)
72 12:25:13.876425 progress 90 % (39 MB)
73 12:25:13.905902 progress 95 % (41 MB)
74 12:25:13.934991 progress 100 % (43 MB)
75 12:25:13.935532 43 MB downloaded in 0.62 s (70.20 MB/s)
76 12:25:13.936023 end: 1.2.1 http-download (duration 00:00:01) [common]
78 12:25:13.936858 end: 1.2 download-retry (duration 00:00:01) [common]
79 12:25:13.937135 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:25:13.937402 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:25:13.937873 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 12:25:13.938143 saving as /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/dtb/meson-g12b-a311d-libretech-cc.dtb
83 12:25:13.938351 total size: 54703 (0 MB)
84 12:25:13.938560 No compression specified
85 12:25:13.975907 progress 59 % (0 MB)
86 12:25:13.976825 progress 100 % (0 MB)
87 12:25:13.977451 0 MB downloaded in 0.04 s (1.33 MB/s)
88 12:25:13.978067 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:25:13.978977 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:25:13.979251 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:25:13.979517 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:25:13.980036 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 12:25:13.980348 saving as /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/nfsrootfs/full.rootfs.tar
95 12:25:13.980575 total size: 120894716 (115 MB)
96 12:25:13.980791 Using unxz to decompress xz
97 12:25:14.019582 progress 0 % (0 MB)
98 12:25:14.818477 progress 5 % (5 MB)
99 12:25:15.659721 progress 10 % (11 MB)
100 12:25:16.455972 progress 15 % (17 MB)
101 12:25:17.195082 progress 20 % (23 MB)
102 12:25:17.784964 progress 25 % (28 MB)
103 12:25:18.612863 progress 30 % (34 MB)
104 12:25:19.428601 progress 35 % (40 MB)
105 12:25:19.777887 progress 40 % (46 MB)
106 12:25:20.158742 progress 45 % (51 MB)
107 12:25:20.902897 progress 50 % (57 MB)
108 12:25:21.787900 progress 55 % (63 MB)
109 12:25:22.570082 progress 60 % (69 MB)
110 12:25:23.332335 progress 65 % (74 MB)
111 12:25:24.112609 progress 70 % (80 MB)
112 12:25:24.945244 progress 75 % (86 MB)
113 12:25:25.738209 progress 80 % (92 MB)
114 12:25:26.504597 progress 85 % (98 MB)
115 12:25:27.362700 progress 90 % (103 MB)
116 12:25:28.148530 progress 95 % (109 MB)
117 12:25:28.985742 progress 100 % (115 MB)
118 12:25:28.998278 115 MB downloaded in 15.02 s (7.68 MB/s)
119 12:25:28.999042 end: 1.4.1 http-download (duration 00:00:15) [common]
121 12:25:29.000908 end: 1.4 download-retry (duration 00:00:15) [common]
122 12:25:29.001499 start: 1.5 download-retry (timeout 00:09:44) [common]
123 12:25:29.002078 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 12:25:29.002962 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/modules.tar.xz
125 12:25:29.003475 saving as /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/modules/modules.tar
126 12:25:29.003935 total size: 11609636 (11 MB)
127 12:25:29.004445 Using unxz to decompress xz
128 12:25:29.050611 progress 0 % (0 MB)
129 12:25:29.112727 progress 5 % (0 MB)
130 12:25:29.191369 progress 10 % (1 MB)
131 12:25:29.279230 progress 15 % (1 MB)
132 12:25:29.371630 progress 20 % (2 MB)
133 12:25:29.454895 progress 25 % (2 MB)
134 12:25:29.533409 progress 30 % (3 MB)
135 12:25:29.617008 progress 35 % (3 MB)
136 12:25:29.694323 progress 40 % (4 MB)
137 12:25:29.772807 progress 45 % (5 MB)
138 12:25:29.855856 progress 50 % (5 MB)
139 12:25:29.933495 progress 55 % (6 MB)
140 12:25:30.017943 progress 60 % (6 MB)
141 12:25:30.093102 progress 65 % (7 MB)
142 12:25:30.173412 progress 70 % (7 MB)
143 12:25:30.247116 progress 75 % (8 MB)
144 12:25:30.324588 progress 80 % (8 MB)
145 12:25:30.409696 progress 85 % (9 MB)
146 12:25:30.489590 progress 90 % (9 MB)
147 12:25:30.571102 progress 95 % (10 MB)
148 12:25:30.651223 progress 100 % (11 MB)
149 12:25:30.662803 11 MB downloaded in 1.66 s (6.67 MB/s)
150 12:25:30.663415 end: 1.5.1 http-download (duration 00:00:02) [common]
152 12:25:30.664631 end: 1.5 download-retry (duration 00:00:02) [common]
153 12:25:30.665163 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 12:25:30.665682 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 12:25:46.994235 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/826934/extract-nfsrootfs-p_bkrn9h
156 12:25:46.994837 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 12:25:46.995163 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 12:25:46.995911 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7
159 12:25:46.996474 makedir: /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin
160 12:25:46.996988 makedir: /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/tests
161 12:25:46.997419 makedir: /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/results
162 12:25:46.997789 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-add-keys
163 12:25:46.998402 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-add-sources
164 12:25:46.998978 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-background-process-start
165 12:25:46.999484 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-background-process-stop
166 12:25:47.000044 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-common-functions
167 12:25:47.000649 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-echo-ipv4
168 12:25:47.001154 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-install-packages
169 12:25:47.001645 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-installed-packages
170 12:25:47.002128 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-os-build
171 12:25:47.002628 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-probe-channel
172 12:25:47.003132 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-probe-ip
173 12:25:47.003644 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-target-ip
174 12:25:47.004143 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-target-mac
175 12:25:47.004653 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-target-storage
176 12:25:47.005154 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-test-case
177 12:25:47.005642 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-test-event
178 12:25:47.006121 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-test-feedback
179 12:25:47.006611 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-test-raise
180 12:25:47.007099 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-test-reference
181 12:25:47.007590 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-test-runner
182 12:25:47.008098 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-test-set
183 12:25:47.008617 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-test-shell
184 12:25:47.009122 Updating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-add-keys (debian)
185 12:25:47.009682 Updating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-add-sources (debian)
186 12:25:47.010219 Updating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-install-packages (debian)
187 12:25:47.010756 Updating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-installed-packages (debian)
188 12:25:47.011270 Updating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/bin/lava-os-build (debian)
189 12:25:47.011720 Creating /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/environment
190 12:25:47.012124 LAVA metadata
191 12:25:47.012396 - LAVA_JOB_ID=826934
192 12:25:47.012609 - LAVA_DISPATCHER_IP=192.168.6.2
193 12:25:47.012974 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 12:25:47.013988 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 12:25:47.014307 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 12:25:47.014514 skipped lava-vland-overlay
197 12:25:47.014754 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 12:25:47.015008 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 12:25:47.015227 skipped lava-multinode-overlay
200 12:25:47.015468 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 12:25:47.015716 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 12:25:47.015963 Loading test definitions
203 12:25:47.016288 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 12:25:47.016508 Using /lava-826934 at stage 0
205 12:25:47.017664 uuid=826934_1.6.2.4.1 testdef=None
206 12:25:47.017969 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 12:25:47.018229 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 12:25:47.019819 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 12:25:47.020632 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 12:25:47.022585 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 12:25:47.023405 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 12:25:47.025318 runner path: /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/0/tests/0_timesync-off test_uuid 826934_1.6.2.4.1
215 12:25:47.025875 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 12:25:47.026688 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 12:25:47.026910 Using /lava-826934 at stage 0
219 12:25:47.027265 Fetching tests from https://github.com/kernelci/test-definitions.git
220 12:25:47.027554 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/0/tests/1_kselftest-dt'
221 12:25:50.711176 Running '/usr/bin/git checkout kernelci.org
222 12:25:51.166008 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 12:25:51.167480 uuid=826934_1.6.2.4.5 testdef=None
224 12:25:51.167841 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 12:25:51.169356 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 12:25:51.175447 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 12:25:51.177279 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 12:25:51.185794 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 12:25:51.187692 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 12:25:51.196074 runner path: /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/0/tests/1_kselftest-dt test_uuid 826934_1.6.2.4.5
234 12:25:51.196705 BOARD='meson-g12b-a311d-libretech-cc'
235 12:25:51.197161 BRANCH='lee-mfd'
236 12:25:51.197598 SKIPFILE='/dev/null'
237 12:25:51.198032 SKIP_INSTALL='True'
238 12:25:51.198458 TESTPROG_URL='http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 12:25:51.198897 TST_CASENAME=''
240 12:25:51.199328 TST_CMDFILES='dt'
241 12:25:51.200497 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 12:25:51.202219 Creating lava-test-runner.conf files
244 12:25:51.202659 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/826934/lava-overlay-lu2a_oe7/lava-826934/0 for stage 0
245 12:25:51.203517 - 0_timesync-off
246 12:25:51.204067 - 1_kselftest-dt
247 12:25:51.204779 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 12:25:51.205370 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 12:26:16.432309 end: 1.6.2.5 compress-overlay (duration 00:00:25) [common]
250 12:26:16.432770 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 12:26:16.433068 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 12:26:16.433380 end: 1.6.2 lava-overlay (duration 00:00:29) [common]
253 12:26:16.433677 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 12:26:17.057890 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 12:26:17.058368 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
256 12:26:17.058640 extracting modules file /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/modules/modules.tar to /var/lib/lava/dispatcher/tmp/826934/extract-nfsrootfs-p_bkrn9h
257 12:26:18.457716 extracting modules file /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/modules/modules.tar to /var/lib/lava/dispatcher/tmp/826934/extract-overlay-ramdisk-9ax7zgg3/ramdisk
258 12:26:19.885571 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 12:26:19.886062 start: 1.6.5 apply-overlay-tftp (timeout 00:08:53) [common]
260 12:26:19.886360 [common] Applying overlay to NFS
261 12:26:19.886592 [common] Applying overlay /var/lib/lava/dispatcher/tmp/826934/compress-overlay-buyd7d_1/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/826934/extract-nfsrootfs-p_bkrn9h
262 12:26:22.668534 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 12:26:22.669025 start: 1.6.6 prepare-kernel (timeout 00:08:50) [common]
264 12:26:22.669333 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:50) [common]
265 12:26:22.669599 Converting downloaded kernel to a uImage
266 12:26:22.669931 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/kernel/Image /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/kernel/uImage
267 12:26:23.253442 output: Image Name:
268 12:26:23.253963 output: Created: Wed Oct 9 12:26:22 2024
269 12:26:23.254211 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 12:26:23.254522 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 12:26:23.254878 output: Load Address: 01080000
272 12:26:23.255140 output: Entry Point: 01080000
273 12:26:23.255365 output:
274 12:26:23.255749 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 12:26:23.256116 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 12:26:23.256439 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 12:26:23.257095 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 12:26:23.257735 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 12:26:23.258162 Building ramdisk /var/lib/lava/dispatcher/tmp/826934/extract-overlay-ramdisk-9ax7zgg3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/826934/extract-overlay-ramdisk-9ax7zgg3/ramdisk
280 12:26:26.431094 >> 166772 blocks
281 12:26:34.194861 Adding RAMdisk u-boot header.
282 12:26:34.196490 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/826934/extract-overlay-ramdisk-9ax7zgg3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/826934/extract-overlay-ramdisk-9ax7zgg3/ramdisk.cpio.gz.uboot
283 12:26:34.441209 output: Image Name:
284 12:26:34.441634 output: Created: Wed Oct 9 12:26:34 2024
285 12:26:34.443078 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 12:26:34.443548 output: Data Size: 23425087 Bytes = 22876.06 KiB = 22.34 MiB
287 12:26:34.443966 output: Load Address: 00000000
288 12:26:34.444425 output: Entry Point: 00000000
289 12:26:34.444838 output:
290 12:26:34.445925 rename /var/lib/lava/dispatcher/tmp/826934/extract-overlay-ramdisk-9ax7zgg3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/ramdisk/ramdisk.cpio.gz.uboot
291 12:26:34.446659 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 12:26:34.447219 end: 1.6 prepare-tftp-overlay (duration 00:01:04) [common]
293 12:26:34.447757 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:39) [common]
294 12:26:34.448251 No LXC device requested
295 12:26:34.448772 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 12:26:34.449298 start: 1.8 deploy-device-env (timeout 00:08:39) [common]
297 12:26:34.449804 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 12:26:34.450226 Checking files for TFTP limit of 4294967296 bytes.
299 12:26:34.453006 end: 1 tftp-deploy (duration 00:01:21) [common]
300 12:26:34.453626 start: 2 uboot-action (timeout 00:05:00) [common]
301 12:26:34.454172 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 12:26:34.458297 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 12:26:34.458962 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 12:26:34.459523 Using kernel file from prepare-kernel: 826934/tftp-deploy-7kw3hh21/kernel/uImage
305 12:26:34.460196 substitutions:
306 12:26:34.462453 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 12:26:34.462894 - {DTB_ADDR}: 0x01070000
308 12:26:34.463311 - {DTB}: 826934/tftp-deploy-7kw3hh21/dtb/meson-g12b-a311d-libretech-cc.dtb
309 12:26:34.463928 - {INITRD}: 826934/tftp-deploy-7kw3hh21/ramdisk/ramdisk.cpio.gz.uboot
310 12:26:34.464401 - {KERNEL_ADDR}: 0x01080000
311 12:26:34.464817 - {KERNEL}: 826934/tftp-deploy-7kw3hh21/kernel/uImage
312 12:26:34.465224 - {LAVA_MAC}: None
313 12:26:34.465678 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/826934/extract-nfsrootfs-p_bkrn9h
314 12:26:34.466093 - {NFS_SERVER_IP}: 192.168.6.2
315 12:26:34.467443 - {PRESEED_CONFIG}: None
316 12:26:34.467867 - {PRESEED_LOCAL}: None
317 12:26:34.468313 - {RAMDISK_ADDR}: 0x08000000
318 12:26:34.468720 - {RAMDISK}: 826934/tftp-deploy-7kw3hh21/ramdisk/ramdisk.cpio.gz.uboot
319 12:26:34.470606 - {ROOT_PART}: None
320 12:26:34.471083 - {ROOT}: None
321 12:26:34.471494 - {SERVER_IP}: 192.168.6.2
322 12:26:34.471896 - {TEE_ADDR}: 0x83000000
323 12:26:34.472330 - {TEE}: None
324 12:26:34.472735 Parsed boot commands:
325 12:26:34.473125 - setenv autoload no
326 12:26:34.473519 - setenv initrd_high 0xffffffff
327 12:26:34.473914 - setenv fdt_high 0xffffffff
328 12:26:34.474309 - dhcp
329 12:26:34.474705 - setenv serverip 192.168.6.2
330 12:26:34.475103 - tftpboot 0x01080000 826934/tftp-deploy-7kw3hh21/kernel/uImage
331 12:26:34.475507 - tftpboot 0x08000000 826934/tftp-deploy-7kw3hh21/ramdisk/ramdisk.cpio.gz.uboot
332 12:26:34.475908 - tftpboot 0x01070000 826934/tftp-deploy-7kw3hh21/dtb/meson-g12b-a311d-libretech-cc.dtb
333 12:26:34.476337 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/826934/extract-nfsrootfs-p_bkrn9h,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 12:26:34.476751 - bootm 0x01080000 0x08000000 0x01070000
335 12:26:34.477290 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 12:26:34.478833 start: 2.3 connect-device (timeout 00:05:00) [common]
338 12:26:34.479092 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 12:26:34.497021 Setting prompt string to ['lava-test: # ']
340 12:26:34.498020 end: 2.3 connect-device (duration 00:00:00) [common]
341 12:26:34.498414 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 12:26:34.498771 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 12:26:34.499102 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 12:26:34.499762 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 12:26:34.540672 >> OK - accepted request
346 12:26:34.543099 Returned 0 in 0 seconds
347 12:26:34.646755 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 12:26:34.649357 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 12:26:34.650711 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 12:26:34.651267 Setting prompt string to ['Hit any key to stop autoboot']
352 12:26:34.652269 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 12:26:34.653915 Trying 192.168.56.21...
354 12:26:34.654205 Connected to conserv1.
355 12:26:34.654642 Escape character is '^]'.
356 12:26:34.655083
357 12:26:34.655562 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 12:26:34.655801
359 12:26:45.814093 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 12:26:45.814519 bl2_stage_init 0x01
361 12:26:45.814752 bl2_stage_init 0x81
362 12:26:45.819561 hw id: 0x0000 - pwm id 0x01
363 12:26:45.819843 bl2_stage_init 0xc1
364 12:26:45.820089 bl2_stage_init 0x02
365 12:26:45.820305
366 12:26:45.825049 L0:00000000
367 12:26:45.825336 L1:20000703
368 12:26:45.825555 L2:00008067
369 12:26:45.825766 L3:14000000
370 12:26:45.828034 B2:00402000
371 12:26:45.828306 B1:e0f83180
372 12:26:45.828523
373 12:26:45.828727 TE: 58124
374 12:26:45.828930
375 12:26:45.839057 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 12:26:45.839329
377 12:26:45.839535 Board ID = 1
378 12:26:45.839735 Set A53 clk to 24M
379 12:26:45.839933 Set A73 clk to 24M
380 12:26:45.844781 Set clk81 to 24M
381 12:26:45.845052 A53 clk: 1200 MHz
382 12:26:45.845257 A73 clk: 1200 MHz
383 12:26:45.848218 CLK81: 166.6M
384 12:26:45.848463 smccc: 00012a91
385 12:26:45.853757 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 12:26:45.859410 board id: 1
387 12:26:45.864713 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 12:26:45.875058 fw parse done
389 12:26:45.880984 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 12:26:45.923585 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 12:26:45.934541 PIEI prepare done
392 12:26:45.934919 fastboot data load
393 12:26:45.935138 fastboot data verify
394 12:26:45.940088 verify result: 266
395 12:26:45.945715 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 12:26:45.946090 LPDDR4 probe
397 12:26:45.946310 ddr clk to 1584MHz
398 12:26:45.953647 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 12:26:45.990925
400 12:26:45.991321 dmc_version 0001
401 12:26:45.997535 Check phy result
402 12:26:46.003435 INFO : End of CA training
403 12:26:46.003704 INFO : End of initialization
404 12:26:46.009049 INFO : Training has run successfully!
405 12:26:46.009304 Check phy result
406 12:26:46.014616 INFO : End of initialization
407 12:26:46.014856 INFO : End of read enable training
408 12:26:46.020281 INFO : End of fine write leveling
409 12:26:46.025831 INFO : End of Write leveling coarse delay
410 12:26:46.026111 INFO : Training has run successfully!
411 12:26:46.026317 Check phy result
412 12:26:46.031443 INFO : End of initialization
413 12:26:46.031687 INFO : End of read dq deskew training
414 12:26:46.037015 INFO : End of MPR read delay center optimization
415 12:26:46.042608 INFO : End of write delay center optimization
416 12:26:46.048270 INFO : End of read delay center optimization
417 12:26:46.048527 INFO : End of max read latency training
418 12:26:46.053822 INFO : Training has run successfully!
419 12:26:46.054073 1D training succeed
420 12:26:46.063009 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 12:26:46.110656 Check phy result
422 12:26:46.111047 INFO : End of initialization
423 12:26:46.133319 INFO : End of 2D read delay Voltage center optimization
424 12:26:46.153545 INFO : End of 2D read delay Voltage center optimization
425 12:26:46.205635 INFO : End of 2D write delay Voltage center optimization
426 12:26:46.254951 INFO : End of 2D write delay Voltage center optimization
427 12:26:46.260465 INFO : Training has run successfully!
428 12:26:46.260771
429 12:26:46.260989 channel==0
430 12:26:46.266060 RxClkDly_Margin_A0==88 ps 9
431 12:26:46.266338 TxDqDly_Margin_A0==98 ps 10
432 12:26:46.269456 RxClkDly_Margin_A1==88 ps 9
433 12:26:46.269695 TxDqDly_Margin_A1==98 ps 10
434 12:26:46.274960 TrainedVREFDQ_A0==74
435 12:26:46.275226 TrainedVREFDQ_A1==75
436 12:26:46.275437 VrefDac_Margin_A0==25
437 12:26:46.280570 DeviceVref_Margin_A0==40
438 12:26:46.280829 VrefDac_Margin_A1==24
439 12:26:46.286181 DeviceVref_Margin_A1==39
440 12:26:46.286418
441 12:26:46.286621
442 12:26:46.286821 channel==1
443 12:26:46.287018 RxClkDly_Margin_A0==98 ps 10
444 12:26:46.291754 TxDqDly_Margin_A0==98 ps 10
445 12:26:46.292020 RxClkDly_Margin_A1==98 ps 10
446 12:26:46.297440 TxDqDly_Margin_A1==88 ps 9
447 12:26:46.297702 TrainedVREFDQ_A0==77
448 12:26:46.297906 TrainedVREFDQ_A1==77
449 12:26:46.302970 VrefDac_Margin_A0==22
450 12:26:46.303231 DeviceVref_Margin_A0==37
451 12:26:46.308571 VrefDac_Margin_A1==22
452 12:26:46.308825 DeviceVref_Margin_A1==37
453 12:26:46.309026
454 12:26:46.314173 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 12:26:46.314424
456 12:26:46.342162 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 12:26:46.347755 2D training succeed
458 12:26:46.353448 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 12:26:46.353702 auto size-- 65535DDR cs0 size: 2048MB
460 12:26:46.358958 DDR cs1 size: 2048MB
461 12:26:46.359220 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 12:26:46.364583 cs0 DataBus test pass
463 12:26:46.364836 cs1 DataBus test pass
464 12:26:46.365043 cs0 AddrBus test pass
465 12:26:46.370170 cs1 AddrBus test pass
466 12:26:46.370444
467 12:26:46.370654 100bdlr_step_size ps== 420
468 12:26:46.370862 result report
469 12:26:46.375751 boot times 0Enable ddr reg access
470 12:26:46.383533 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 12:26:46.396964 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 12:26:46.969989 0.0;M3 CHK:0;cm4_sp_mode 0
473 12:26:46.970428 MVN_1=0x00000000
474 12:26:46.975534 MVN_2=0x00000000
475 12:26:46.981284 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 12:26:46.981604 OPS=0x10
477 12:26:46.981814 ring efuse init
478 12:26:46.982014 chipver efuse init
479 12:26:46.986874 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 12:26:46.992525 [0.018961 Inits done]
481 12:26:46.992977 secure task start!
482 12:26:46.993320 high task start!
483 12:26:46.996594 low task start!
484 12:26:46.996966 run into bl31
485 12:26:47.003710 NOTICE: BL31: v1.3(release):4fc40b1
486 12:26:47.010657 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 12:26:47.010967 NOTICE: BL31: G12A normal boot!
488 12:26:47.036930 NOTICE: BL31: BL33 decompress pass
489 12:26:47.041774 ERROR: Error initializing runtime service opteed_fast
490 12:26:48.275472
491 12:26:48.275886
492 12:26:48.283914 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 12:26:48.284217
494 12:26:48.284427 Model: Libre Computer AML-A311D-CC Alta
495 12:26:48.491783 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 12:26:48.515223 DRAM: 2 GiB (effective 3.8 GiB)
497 12:26:48.658933 Core: 408 devices, 31 uclasses, devicetree: separate
498 12:26:48.664046 WDT: Not starting watchdog@f0d0
499 12:26:48.696879 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 12:26:48.710254 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 12:26:48.714070 ** Bad device specification mmc 0 **
502 12:26:48.724653 Card did not respond to voltage select! : -110
503 12:26:48.731891 ** Bad device specification mmc 0 **
504 12:26:48.732226 Couldn't find partition mmc 0
505 12:26:48.740670 Card did not respond to voltage select! : -110
506 12:26:48.746174 ** Bad device specification mmc 0 **
507 12:26:48.746752 Couldn't find partition mmc 0
508 12:26:48.750388 Error: could not access storage.
509 12:26:50.014488 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 12:26:50.015157 bl2_stage_init 0x01
511 12:26:50.015635 bl2_stage_init 0x81
512 12:26:50.020032 hw id: 0x0000 - pwm id 0x01
513 12:26:50.020541 bl2_stage_init 0xc1
514 12:26:50.020999 bl2_stage_init 0x02
515 12:26:50.021447
516 12:26:50.025591 L0:00000000
517 12:26:50.026066 L1:20000703
518 12:26:50.026510 L2:00008067
519 12:26:50.026949 L3:14000000
520 12:26:50.031189 B2:00402000
521 12:26:50.031670 B1:e0f83180
522 12:26:50.032146
523 12:26:50.032591 TE: 58159
524 12:26:50.033033
525 12:26:50.036842 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 12:26:50.037561
527 12:26:50.037845 Board ID = 1
528 12:26:50.042397 Set A53 clk to 24M
529 12:26:50.042883 Set A73 clk to 24M
530 12:26:50.043272 Set clk81 to 24M
531 12:26:50.048139 A53 clk: 1200 MHz
532 12:26:50.048533 A73 clk: 1200 MHz
533 12:26:50.048736 CLK81: 166.6M
534 12:26:50.048936 smccc: 00012ab5
535 12:26:50.053569 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 12:26:50.059175 board id: 1
537 12:26:50.064969 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 12:26:50.075760 fw parse done
539 12:26:50.081051 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 12:26:50.124371 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 12:26:50.135270 PIEI prepare done
542 12:26:50.135778 fastboot data load
543 12:26:50.136363 fastboot data verify
544 12:26:50.140897 verify result: 266
545 12:26:50.146468 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 12:26:50.146992 LPDDR4 probe
547 12:26:50.147452 ddr clk to 1584MHz
548 12:26:50.153516 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 12:26:50.191139
550 12:26:50.191726 dmc_version 0001
551 12:26:50.198204 Check phy result
552 12:26:50.204277 INFO : End of CA training
553 12:26:50.204831 INFO : End of initialization
554 12:26:50.209929 INFO : Training has run successfully!
555 12:26:50.210702 Check phy result
556 12:26:50.215458 INFO : End of initialization
557 12:26:50.216140 INFO : End of read enable training
558 12:26:50.221080 INFO : End of fine write leveling
559 12:26:50.226700 INFO : End of Write leveling coarse delay
560 12:26:50.227277 INFO : Training has run successfully!
561 12:26:50.227771 Check phy result
562 12:26:50.232294 INFO : End of initialization
563 12:26:50.232844 INFO : End of read dq deskew training
564 12:26:50.237910 INFO : End of MPR read delay center optimization
565 12:26:50.243473 INFO : End of write delay center optimization
566 12:26:50.249127 INFO : End of read delay center optimization
567 12:26:50.249679 INFO : End of max read latency training
568 12:26:50.254687 INFO : Training has run successfully!
569 12:26:50.255240 1D training succeed
570 12:26:50.263436 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 12:26:50.311472 Check phy result
572 12:26:50.312130 INFO : End of initialization
573 12:26:50.333045 INFO : End of 2D read delay Voltage center optimization
574 12:26:50.353302 INFO : End of 2D read delay Voltage center optimization
575 12:26:50.405341 INFO : End of 2D write delay Voltage center optimization
576 12:26:50.454812 INFO : End of 2D write delay Voltage center optimization
577 12:26:50.460402 INFO : Training has run successfully!
578 12:26:50.460966
579 12:26:50.461429 channel==0
580 12:26:50.466071 RxClkDly_Margin_A0==88 ps 9
581 12:26:50.466583 TxDqDly_Margin_A0==98 ps 10
582 12:26:50.471577 RxClkDly_Margin_A1==88 ps 9
583 12:26:50.472134 TxDqDly_Margin_A1==98 ps 10
584 12:26:50.472595 TrainedVREFDQ_A0==74
585 12:26:50.477237 TrainedVREFDQ_A1==74
586 12:26:50.477738 VrefDac_Margin_A0==25
587 12:26:50.478164 DeviceVref_Margin_A0==40
588 12:26:50.482782 VrefDac_Margin_A1==25
589 12:26:50.483287 DeviceVref_Margin_A1==40
590 12:26:50.483698
591 12:26:50.484155
592 12:26:50.488364 channel==1
593 12:26:50.488861 RxClkDly_Margin_A0==88 ps 9
594 12:26:50.489299 TxDqDly_Margin_A0==88 ps 9
595 12:26:50.494059 RxClkDly_Margin_A1==98 ps 10
596 12:26:50.494566 TxDqDly_Margin_A1==88 ps 9
597 12:26:50.499594 TrainedVREFDQ_A0==77
598 12:26:50.500150 TrainedVREFDQ_A1==77
599 12:26:50.500608 VrefDac_Margin_A0==22
600 12:26:50.505247 DeviceVref_Margin_A0==37
601 12:26:50.505755 VrefDac_Margin_A1==22
602 12:26:50.510790 DeviceVref_Margin_A1==37
603 12:26:50.511302
604 12:26:50.511741 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 12:26:50.512227
606 12:26:50.544381 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 12:26:50.544968 2D training succeed
608 12:26:50.550092 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 12:26:50.555575 auto size-- 65535DDR cs0 size: 2048MB
610 12:26:50.556123 DDR cs1 size: 2048MB
611 12:26:50.561198 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 12:26:50.561713 cs0 DataBus test pass
613 12:26:50.566792 cs1 DataBus test pass
614 12:26:50.567309 cs0 AddrBus test pass
615 12:26:50.567750 cs1 AddrBus test pass
616 12:26:50.568222
617 12:26:50.572382 100bdlr_step_size ps== 420
618 12:26:50.572893 result report
619 12:26:50.578098 boot times 0Enable ddr reg access
620 12:26:50.582356 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 12:26:50.596544 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 12:26:51.170410 0.0;M3 CHK:0;cm4_sp_mode 0
623 12:26:51.170841 MVN_1=0x00000000
624 12:26:51.176056 MVN_2=0x00000000
625 12:26:51.181896 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 12:26:51.182233 OPS=0x10
627 12:26:51.182458 ring efuse init
628 12:26:51.182666 chipver efuse init
629 12:26:51.187428 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 12:26:51.193005 [0.018960 Inits done]
631 12:26:51.193334 secure task start!
632 12:26:51.193544 high task start!
633 12:26:51.196913 low task start!
634 12:26:51.197466 run into bl31
635 12:26:51.204241 NOTICE: BL31: v1.3(release):4fc40b1
636 12:26:51.211436 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 12:26:51.211945 NOTICE: BL31: G12A normal boot!
638 12:26:51.237264 NOTICE: BL31: BL33 decompress pass
639 12:26:51.242559 ERROR: Error initializing runtime service opteed_fast
640 12:26:52.476100
641 12:26:52.477564
642 12:26:52.484311 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 12:26:52.485423
644 12:26:52.486202 Model: Libre Computer AML-A311D-CC Alta
645 12:26:52.692152 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 12:26:52.715442 DRAM: 2 GiB (effective 3.8 GiB)
647 12:26:52.859121 Core: 408 devices, 31 uclasses, devicetree: separate
648 12:26:52.864626 WDT: Not starting watchdog@f0d0
649 12:26:52.899682 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 12:26:52.909793 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 12:26:52.914805 ** Bad device specification mmc 0 **
652 12:26:52.925210 Card did not respond to voltage select! : -110
653 12:26:52.931836 ** Bad device specification mmc 0 **
654 12:26:52.932263 Couldn't find partition mmc 0
655 12:26:52.940925 Card did not respond to voltage select! : -110
656 12:26:52.946471 ** Bad device specification mmc 0 **
657 12:26:52.946849 Couldn't find partition mmc 0
658 12:26:52.950845 Error: could not access storage.
659 12:26:53.295034 Net: eth0: ethernet@ff3f0000
660 12:26:53.295428 starting USB...
661 12:26:53.546859 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 12:26:53.547271 Starting the controller
663 12:26:53.552800 USB XHCI 1.10
664 12:26:55.263236 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 12:26:55.263705 bl2_stage_init 0x01
666 12:26:55.263956 bl2_stage_init 0x81
667 12:26:55.268771 hw id: 0x0000 - pwm id 0x01
668 12:26:55.269341 bl2_stage_init 0xc1
669 12:26:55.269720 bl2_stage_init 0x02
670 12:26:55.270071
671 12:26:55.274354 L0:00000000
672 12:26:55.274909 L1:20000703
673 12:26:55.275184 L2:00008067
674 12:26:55.275414 L3:14000000
675 12:26:55.279940 B2:00402000
676 12:26:55.280508 B1:e0f83180
677 12:26:55.280886
678 12:26:55.281243 TE: 58167
679 12:26:55.281516
680 12:26:55.285628 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 12:26:55.286198
682 12:26:55.286588 Board ID = 1
683 12:26:55.291180 Set A53 clk to 24M
684 12:26:55.291586 Set A73 clk to 24M
685 12:26:55.291822 Set clk81 to 24M
686 12:26:55.296757 A53 clk: 1200 MHz
687 12:26:55.297217 A73 clk: 1200 MHz
688 12:26:55.297573 CLK81: 166.6M
689 12:26:55.297916 smccc: 00012abd
690 12:26:55.302327 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 12:26:55.307819 board id: 1
692 12:26:55.313543 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 12:26:55.324495 fw parse done
694 12:26:55.330480 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 12:26:55.372594 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 12:26:55.383930 PIEI prepare done
697 12:26:55.384336 fastboot data load
698 12:26:55.384591 fastboot data verify
699 12:26:55.389553 verify result: 266
700 12:26:55.395138 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 12:26:55.395455 LPDDR4 probe
702 12:26:55.395676 ddr clk to 1584MHz
703 12:26:55.403141 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 12:26:55.439462
705 12:26:55.440018 dmc_version 0001
706 12:26:55.446315 Check phy result
707 12:26:55.452962 INFO : End of CA training
708 12:26:55.453354 INFO : End of initialization
709 12:26:55.458593 INFO : Training has run successfully!
710 12:26:55.459159 Check phy result
711 12:26:55.464224 INFO : End of initialization
712 12:26:55.464691 INFO : End of read enable training
713 12:26:55.469808 INFO : End of fine write leveling
714 12:26:55.475380 INFO : End of Write leveling coarse delay
715 12:26:55.475741 INFO : Training has run successfully!
716 12:26:55.476057 Check phy result
717 12:26:55.480965 INFO : End of initialization
718 12:26:55.481508 INFO : End of read dq deskew training
719 12:26:55.486558 INFO : End of MPR read delay center optimization
720 12:26:55.492215 INFO : End of write delay center optimization
721 12:26:55.497781 INFO : End of read delay center optimization
722 12:26:55.498317 INFO : End of max read latency training
723 12:26:55.503428 INFO : Training has run successfully!
724 12:26:55.503784 1D training succeed
725 12:26:55.511654 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 12:26:55.559969 Check phy result
727 12:26:55.560471 INFO : End of initialization
728 12:26:55.582039 INFO : End of 2D read delay Voltage center optimization
729 12:26:55.600434 INFO : End of 2D read delay Voltage center optimization
730 12:26:55.653394 INFO : End of 2D write delay Voltage center optimization
731 12:26:55.702839 INFO : End of 2D write delay Voltage center optimization
732 12:26:55.708309 INFO : Training has run successfully!
733 12:26:55.708659
734 12:26:55.708920 channel==0
735 12:26:55.714000 RxClkDly_Margin_A0==88 ps 9
736 12:26:55.714335 TxDqDly_Margin_A0==98 ps 10
737 12:26:55.717157 RxClkDly_Margin_A1==88 ps 9
738 12:26:55.717586 TxDqDly_Margin_A1==98 ps 10
739 12:26:55.722718 TrainedVREFDQ_A0==74
740 12:26:55.723042 TrainedVREFDQ_A1==74
741 12:26:55.728353 VrefDac_Margin_A0==25
742 12:26:55.728815 DeviceVref_Margin_A0==40
743 12:26:55.729483 VrefDac_Margin_A1==25
744 12:26:55.734010 DeviceVref_Margin_A1==40
745 12:26:55.734318
746 12:26:55.734539
747 12:26:55.734751 channel==1
748 12:26:55.734961 RxClkDly_Margin_A0==88 ps 9
749 12:26:55.737351 TxDqDly_Margin_A0==88 ps 9
750 12:26:55.743002 RxClkDly_Margin_A1==88 ps 9
751 12:26:55.743457 TxDqDly_Margin_A1==88 ps 9
752 12:26:55.743820 TrainedVREFDQ_A0==76
753 12:26:55.748539 TrainedVREFDQ_A1==77
754 12:26:55.748984 VrefDac_Margin_A0==23
755 12:26:55.754165 DeviceVref_Margin_A0==38
756 12:26:55.754620 VrefDac_Margin_A1==24
757 12:26:55.754877 DeviceVref_Margin_A1==37
758 12:26:55.755091
759 12:26:55.759787 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 12:26:55.760242
761 12:26:55.793213 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 12:26:55.793771 2D training succeed
763 12:26:55.798871 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 12:26:55.804427 auto size-- 65535DDR cs0 size: 2048MB
765 12:26:55.804756 DDR cs1 size: 2048MB
766 12:26:55.810028 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 12:26:55.810484 cs0 DataBus test pass
768 12:26:55.810871 cs1 DataBus test pass
769 12:26:55.815615 cs0 AddrBus test pass
770 12:26:55.815926 cs1 AddrBus test pass
771 12:26:55.816183
772 12:26:55.821219 100bdlr_step_size ps== 420
773 12:26:55.821679 result report
774 12:26:55.822063 boot times 0Enable ddr reg access
775 12:26:55.830941 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 12:26:55.843527 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 12:26:56.418059 0.0;M3 CHK:0;cm4_sp_mode 0
778 12:26:56.418500 MVN_1=0x00000000
779 12:26:56.423632 MVN_2=0x00000000
780 12:26:56.429333 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 12:26:56.429685 OPS=0x10
782 12:26:56.429918 ring efuse init
783 12:26:56.430133 chipver efuse init
784 12:26:56.434931 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 12:26:56.440534 [0.018960 Inits done]
786 12:26:56.440875 secure task start!
787 12:26:56.441097 high task start!
788 12:26:56.444184 low task start!
789 12:26:56.444518 run into bl31
790 12:26:56.452199 NOTICE: BL31: v1.3(release):4fc40b1
791 12:26:56.458811 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 12:26:56.459257 NOTICE: BL31: G12A normal boot!
793 12:26:56.485100 NOTICE: BL31: BL33 decompress pass
794 12:26:56.494622 ERROR: Error initializing runtime service opteed_fast
795 12:26:57.723593
796 12:26:57.724185
797 12:26:57.732068 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 12:26:57.732571
799 12:26:57.732842 Model: Libre Computer AML-A311D-CC Alta
800 12:26:57.939970 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 12:26:57.963030 DRAM: 2 GiB (effective 3.8 GiB)
802 12:26:58.106852 Core: 408 devices, 31 uclasses, devicetree: separate
803 12:26:58.111785 WDT: Not starting watchdog@f0d0
804 12:26:58.145076 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 12:26:58.157451 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 12:26:58.161379 ** Bad device specification mmc 0 **
807 12:26:58.172859 Card did not respond to voltage select! : -110
808 12:26:58.179497 ** Bad device specification mmc 0 **
809 12:26:58.180222 Couldn't find partition mmc 0
810 12:26:58.189042 Card did not respond to voltage select! : -110
811 12:26:58.195247 ** Bad device specification mmc 0 **
812 12:26:58.195718 Couldn't find partition mmc 0
813 12:26:58.198527 Error: could not access storage.
814 12:26:58.540716 Net: eth0: ethernet@ff3f0000
815 12:26:58.541276 starting USB...
816 12:26:58.793505 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 12:26:58.793925 Starting the controller
818 12:26:58.799608 USB XHCI 1.10
819 12:27:00.963532 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 12:27:00.963966 bl2_stage_init 0x01
821 12:27:00.964216 bl2_stage_init 0x81
822 12:27:00.968898 hw id: 0x0000 - pwm id 0x01
823 12:27:00.969238 bl2_stage_init 0xc1
824 12:27:00.969466 bl2_stage_init 0x02
825 12:27:00.969677
826 12:27:00.974598 L0:00000000
827 12:27:00.974915 L1:20000703
828 12:27:00.975141 L2:00008067
829 12:27:00.975356 L3:14000000
830 12:27:00.977435 B2:00402000
831 12:27:00.977736 B1:e0f83180
832 12:27:00.977954
833 12:27:00.978167 TE: 58159
834 12:27:00.978413
835 12:27:00.988674 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 12:27:00.989019
837 12:27:00.989243 Board ID = 1
838 12:27:00.989452 Set A53 clk to 24M
839 12:27:00.989686 Set A73 clk to 24M
840 12:27:00.994217 Set clk81 to 24M
841 12:27:00.994557 A53 clk: 1200 MHz
842 12:27:00.994812 A73 clk: 1200 MHz
843 12:27:00.999901 CLK81: 166.6M
844 12:27:01.000278 smccc: 00012ab5
845 12:27:01.005486 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 12:27:01.005839 board id: 1
847 12:27:01.014174 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 12:27:01.024581 fw parse done
849 12:27:01.030586 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 12:27:01.073192 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 12:27:01.084057 PIEI prepare done
852 12:27:01.084472 fastboot data load
853 12:27:01.084708 fastboot data verify
854 12:27:01.089647 verify result: 266
855 12:27:01.095272 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 12:27:01.095629 LPDDR4 probe
857 12:27:01.095864 ddr clk to 1584MHz
858 12:27:01.103175 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 12:27:01.140501
860 12:27:01.140908 dmc_version 0001
861 12:27:01.147186 Check phy result
862 12:27:01.153016 INFO : End of CA training
863 12:27:01.153363 INFO : End of initialization
864 12:27:01.158584 INFO : Training has run successfully!
865 12:27:01.158930 Check phy result
866 12:27:01.164464 INFO : End of initialization
867 12:27:01.164866 INFO : End of read enable training
868 12:27:01.167700 INFO : End of fine write leveling
869 12:27:01.173272 INFO : End of Write leveling coarse delay
870 12:27:01.178996 INFO : Training has run successfully!
871 12:27:01.179379 Check phy result
872 12:27:01.179597 INFO : End of initialization
873 12:27:01.184542 INFO : End of read dq deskew training
874 12:27:01.190203 INFO : End of MPR read delay center optimization
875 12:27:01.190609 INFO : End of write delay center optimization
876 12:27:01.195746 INFO : End of read delay center optimization
877 12:27:01.201376 INFO : End of max read latency training
878 12:27:01.201751 INFO : Training has run successfully!
879 12:27:01.206765 1D training succeed
880 12:27:01.212870 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 12:27:01.260555 Check phy result
882 12:27:01.260985 INFO : End of initialization
883 12:27:01.281893 INFO : End of 2D read delay Voltage center optimization
884 12:27:01.302077 INFO : End of 2D read delay Voltage center optimization
885 12:27:01.353892 INFO : End of 2D write delay Voltage center optimization
886 12:27:01.403021 INFO : End of 2D write delay Voltage center optimization
887 12:27:01.408671 INFO : Training has run successfully!
888 12:27:01.409177
889 12:27:01.409481 channel==0
890 12:27:01.414199 RxClkDly_Margin_A0==88 ps 9
891 12:27:01.414660 TxDqDly_Margin_A0==98 ps 10
892 12:27:01.417540 RxClkDly_Margin_A1==88 ps 9
893 12:27:01.418019 TxDqDly_Margin_A1==98 ps 10
894 12:27:01.423223 TrainedVREFDQ_A0==74
895 12:27:01.423698 TrainedVREFDQ_A1==74
896 12:27:01.423946 VrefDac_Margin_A0==25
897 12:27:01.428792 DeviceVref_Margin_A0==40
898 12:27:01.429161 VrefDac_Margin_A1==25
899 12:27:01.434430 DeviceVref_Margin_A1==40
900 12:27:01.434798
901 12:27:01.435013
902 12:27:01.435216 channel==1
903 12:27:01.435415 RxClkDly_Margin_A0==98 ps 10
904 12:27:01.437665 TxDqDly_Margin_A0==88 ps 9
905 12:27:01.443487 RxClkDly_Margin_A1==98 ps 10
906 12:27:01.443872 TxDqDly_Margin_A1==88 ps 9
907 12:27:01.444116 TrainedVREFDQ_A0==76
908 12:27:01.448976 TrainedVREFDQ_A1==77
909 12:27:01.449330 VrefDac_Margin_A0==22
910 12:27:01.454491 DeviceVref_Margin_A0==38
911 12:27:01.454854 VrefDac_Margin_A1==22
912 12:27:01.455061 DeviceVref_Margin_A1==37
913 12:27:01.455264
914 12:27:01.460062 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 12:27:01.460434
916 12:27:01.493696 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
917 12:27:01.494115 2D training succeed
918 12:27:01.499334 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 12:27:01.504857 auto size-- 65535DDR cs0 size: 2048MB
920 12:27:01.505154 DDR cs1 size: 2048MB
921 12:27:01.510471 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 12:27:01.510808 cs0 DataBus test pass
923 12:27:01.511016 cs1 DataBus test pass
924 12:27:01.516063 cs0 AddrBus test pass
925 12:27:01.516378 cs1 AddrBus test pass
926 12:27:01.516584
927 12:27:01.521846 100bdlr_step_size ps== 420
928 12:27:01.522187 result report
929 12:27:01.522398 boot times 0Enable ddr reg access
930 12:27:01.531520 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 12:27:01.544979 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 12:27:02.117022 0.0;M3 CHK:0;cm4_sp_mode 0
933 12:27:02.117451 MVN_1=0x00000000
934 12:27:02.122462 MVN_2=0x00000000
935 12:27:02.128215 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 12:27:02.128506 OPS=0x10
937 12:27:02.128719 ring efuse init
938 12:27:02.128921 chipver efuse init
939 12:27:02.133822 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 12:27:02.139410 [0.018961 Inits done]
941 12:27:02.139678 secure task start!
942 12:27:02.139882 high task start!
943 12:27:02.143990 low task start!
944 12:27:02.144242 run into bl31
945 12:27:02.150647 NOTICE: BL31: v1.3(release):4fc40b1
946 12:27:02.158419 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 12:27:02.158698 NOTICE: BL31: G12A normal boot!
948 12:27:02.183770 NOTICE: BL31: BL33 decompress pass
949 12:27:02.189427 ERROR: Error initializing runtime service opteed_fast
950 12:27:03.422355
951 12:27:03.422768
952 12:27:03.430717 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 12:27:03.431098
954 12:27:03.431407 Model: Libre Computer AML-A311D-CC Alta
955 12:27:03.639194 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 12:27:03.662549 DRAM: 2 GiB (effective 3.8 GiB)
957 12:27:03.805544 Core: 408 devices, 31 uclasses, devicetree: separate
958 12:27:03.811398 WDT: Not starting watchdog@f0d0
959 12:27:03.843672 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 12:27:03.856103 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 12:27:03.861031 ** Bad device specification mmc 0 **
962 12:27:03.871400 Card did not respond to voltage select! : -110
963 12:27:03.879021 ** Bad device specification mmc 0 **
964 12:27:03.879359 Couldn't find partition mmc 0
965 12:27:03.887420 Card did not respond to voltage select! : -110
966 12:27:03.892935 ** Bad device specification mmc 0 **
967 12:27:03.893265 Couldn't find partition mmc 0
968 12:27:03.898024 Error: could not access storage.
969 12:27:04.240456 Net: eth0: ethernet@ff3f0000
970 12:27:04.241019 starting USB...
971 12:27:04.492277 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 12:27:04.492689 Starting the controller
973 12:27:04.499147 USB XHCI 1.10
974 12:27:06.363203 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 12:27:06.363786 bl2_stage_init 0x01
976 12:27:06.364071 bl2_stage_init 0x81
977 12:27:06.368691 hw id: 0x0000 - pwm id 0x01
978 12:27:06.368994 bl2_stage_init 0xc1
979 12:27:06.369206 bl2_stage_init 0x02
980 12:27:06.369409
981 12:27:06.374475 L0:00000000
982 12:27:06.374876 L1:20000703
983 12:27:06.375203 L2:00008067
984 12:27:06.375532 L3:14000000
985 12:27:06.379936 B2:00402000
986 12:27:06.380364 B1:e0f83180
987 12:27:06.380703
988 12:27:06.381013 TE: 58167
989 12:27:06.381246
990 12:27:06.385535 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 12:27:06.385837
992 12:27:06.386059 Board ID = 1
993 12:27:06.391106 Set A53 clk to 24M
994 12:27:06.391502 Set A73 clk to 24M
995 12:27:06.391836 Set clk81 to 24M
996 12:27:06.396733 A53 clk: 1200 MHz
997 12:27:06.397137 A73 clk: 1200 MHz
998 12:27:06.397462 CLK81: 166.6M
999 12:27:06.397694 smccc: 00012abe
1000 12:27:06.402369 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 12:27:06.407933 board id: 1
1002 12:27:06.413962 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 12:27:06.424367 fw parse done
1004 12:27:06.430367 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 12:27:06.472972 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 12:27:06.483866 PIEI prepare done
1007 12:27:06.484451 fastboot data load
1008 12:27:06.484903 fastboot data verify
1009 12:27:06.489500 verify result: 266
1010 12:27:06.495102 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 12:27:06.495588 LPDDR4 probe
1012 12:27:06.496061 ddr clk to 1584MHz
1013 12:27:06.503095 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 12:27:06.540458
1015 12:27:06.540955 dmc_version 0001
1016 12:27:06.546990 Check phy result
1017 12:27:06.552888 INFO : End of CA training
1018 12:27:06.553364 INFO : End of initialization
1019 12:27:06.558482 INFO : Training has run successfully!
1020 12:27:06.558970 Check phy result
1021 12:27:06.564093 INFO : End of initialization
1022 12:27:06.564602 INFO : End of read enable training
1023 12:27:06.569677 INFO : End of fine write leveling
1024 12:27:06.575350 INFO : End of Write leveling coarse delay
1025 12:27:06.575847 INFO : Training has run successfully!
1026 12:27:06.576343 Check phy result
1027 12:27:06.580898 INFO : End of initialization
1028 12:27:06.581393 INFO : End of read dq deskew training
1029 12:27:06.586487 INFO : End of MPR read delay center optimization
1030 12:27:06.592115 INFO : End of write delay center optimization
1031 12:27:06.597687 INFO : End of read delay center optimization
1032 12:27:06.598183 INFO : End of max read latency training
1033 12:27:06.603335 INFO : Training has run successfully!
1034 12:27:06.603826 1D training succeed
1035 12:27:06.612442 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 12:27:06.660118 Check phy result
1037 12:27:06.660630 INFO : End of initialization
1038 12:27:06.681816 INFO : End of 2D read delay Voltage center optimization
1039 12:27:06.701973 INFO : End of 2D read delay Voltage center optimization
1040 12:27:06.754132 INFO : End of 2D write delay Voltage center optimization
1041 12:27:06.804075 INFO : End of 2D write delay Voltage center optimization
1042 12:27:06.808969 INFO : Training has run successfully!
1043 12:27:06.809350
1044 12:27:06.809636 channel==0
1045 12:27:06.814531 RxClkDly_Margin_A0==88 ps 9
1046 12:27:06.814888 TxDqDly_Margin_A0==98 ps 10
1047 12:27:06.820213 RxClkDly_Margin_A1==88 ps 9
1048 12:27:06.820586 TxDqDly_Margin_A1==88 ps 9
1049 12:27:06.820863 TrainedVREFDQ_A0==74
1050 12:27:06.825719 TrainedVREFDQ_A1==74
1051 12:27:06.826071 VrefDac_Margin_A0==25
1052 12:27:06.826333 DeviceVref_Margin_A0==40
1053 12:27:06.831363 VrefDac_Margin_A1==25
1054 12:27:06.831729 DeviceVref_Margin_A1==40
1055 12:27:06.832008
1056 12:27:06.832272
1057 12:27:06.832536 channel==1
1058 12:27:06.836948 RxClkDly_Margin_A0==88 ps 9
1059 12:27:06.837292 TxDqDly_Margin_A0==88 ps 9
1060 12:27:06.842531 RxClkDly_Margin_A1==88 ps 9
1061 12:27:06.842872 TxDqDly_Margin_A1==88 ps 9
1062 12:27:06.848224 TrainedVREFDQ_A0==77
1063 12:27:06.848572 TrainedVREFDQ_A1==77
1064 12:27:06.848836 VrefDac_Margin_A0==22
1065 12:27:06.853720 DeviceVref_Margin_A0==37
1066 12:27:06.854055 VrefDac_Margin_A1==24
1067 12:27:06.854313 DeviceVref_Margin_A1==37
1068 12:27:06.859318
1069 12:27:06.859663 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 12:27:06.859926
1071 12:27:06.893074 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 12:27:06.893468 2D training succeed
1073 12:27:06.898603 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 12:27:06.904192 auto size-- 65535DDR cs0 size: 2048MB
1075 12:27:06.904668 DDR cs1 size: 2048MB
1076 12:27:06.909791 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 12:27:06.910132 cs0 DataBus test pass
1078 12:27:06.915417 cs1 DataBus test pass
1079 12:27:06.915896 cs0 AddrBus test pass
1080 12:27:06.916323 cs1 AddrBus test pass
1081 12:27:06.916697
1082 12:27:06.921003 100bdlr_step_size ps== 420
1083 12:27:06.921342 result report
1084 12:27:06.926618 boot times 0Enable ddr reg access
1085 12:27:06.931701 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 12:27:06.945168 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 12:27:07.518308 0.0;M3 CHK:0;cm4_sp_mode 0
1088 12:27:07.518743 MVN_1=0x00000000
1089 12:27:07.524202 MVN_2=0x00000000
1090 12:27:07.529456 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 12:27:07.529875 OPS=0x10
1092 12:27:07.530159 ring efuse init
1093 12:27:07.530402 chipver efuse init
1094 12:27:07.535071 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 12:27:07.540712 [0.018961 Inits done]
1096 12:27:07.541257 secure task start!
1097 12:27:07.541686 high task start!
1098 12:27:07.545161 low task start!
1099 12:27:07.545640 run into bl31
1100 12:27:07.551900 NOTICE: BL31: v1.3(release):4fc40b1
1101 12:27:07.559677 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 12:27:07.560095 NOTICE: BL31: G12A normal boot!
1103 12:27:07.585539 NOTICE: BL31: BL33 decompress pass
1104 12:27:07.591197 ERROR: Error initializing runtime service opteed_fast
1105 12:27:08.824139
1106 12:27:08.824566
1107 12:27:08.832466 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 12:27:08.832919
1109 12:27:08.833325 Model: Libre Computer AML-A311D-CC Alta
1110 12:27:09.040956 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 12:27:09.064302 DRAM: 2 GiB (effective 3.8 GiB)
1112 12:27:09.207296 Core: 408 devices, 31 uclasses, devicetree: separate
1113 12:27:09.213086 WDT: Not starting watchdog@f0d0
1114 12:27:09.245403 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 12:27:09.257816 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 12:27:09.262768 ** Bad device specification mmc 0 **
1117 12:27:09.273123 Card did not respond to voltage select! : -110
1118 12:27:09.280795 ** Bad device specification mmc 0 **
1119 12:27:09.281131 Couldn't find partition mmc 0
1120 12:27:09.289118 Card did not respond to voltage select! : -110
1121 12:27:09.294607 ** Bad device specification mmc 0 **
1122 12:27:09.295027 Couldn't find partition mmc 0
1123 12:27:09.299689 Error: could not access storage.
1124 12:27:09.643303 Net: eth0: ethernet@ff3f0000
1125 12:27:09.643744 starting USB...
1126 12:27:09.895159 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 12:27:09.895747 Starting the controller
1128 12:27:09.901949 USB XHCI 1.10
1129 12:27:11.459309 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 12:27:11.467509 scanning usb for storage devices... 0 Storage Device(s) found
1132 12:27:11.518583 Hit any key to stop autoboot: 1
1133 12:27:11.519188 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 12:27:11.519539 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 12:27:11.519792 Setting prompt string to ['=>']
1136 12:27:11.520078 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 12:27:11.524926 0
1138 12:27:11.525504 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 12:27:11.525777 Sending with 10 millisecond of delay
1141 12:27:12.659963 => setenv autoload no
1142 12:27:12.670807 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 12:27:12.673476 setenv autoload no
1144 12:27:12.674177 Sending with 10 millisecond of delay
1146 12:27:14.470309 => setenv initrd_high 0xffffffff
1147 12:27:14.481040 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 12:27:14.481567 setenv initrd_high 0xffffffff
1149 12:27:14.482062 Sending with 10 millisecond of delay
1151 12:27:16.098447 => setenv fdt_high 0xffffffff
1152 12:27:16.109261 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 12:27:16.110134 setenv fdt_high 0xffffffff
1154 12:27:16.110907 Sending with 10 millisecond of delay
1156 12:27:16.402791 => dhcp
1157 12:27:16.413485 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 12:27:16.414324 dhcp
1159 12:27:16.414803 Speed: 1000, full duplex
1160 12:27:16.415259 BOOTP broadcast 1
1161 12:27:16.661488 BOOTP broadcast 2
1162 12:27:16.837927 DHCP client bound to address 192.168.6.33 (425 ms)
1163 12:27:16.838800 Sending with 10 millisecond of delay
1165 12:27:18.515234 => setenv serverip 192.168.6.2
1166 12:27:18.525744 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1167 12:27:18.526237 setenv serverip 192.168.6.2
1168 12:27:18.527239 Sending with 10 millisecond of delay
1170 12:27:22.251478 => tftpboot 0x01080000 826934/tftp-deploy-7kw3hh21/kernel/uImage
1171 12:27:22.262375 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1172 12:27:22.263323 tftpboot 0x01080000 826934/tftp-deploy-7kw3hh21/kernel/uImage
1173 12:27:22.263794 Speed: 1000, full duplex
1174 12:27:22.264277 Using ethernet@ff3f0000 device
1175 12:27:22.265069 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1176 12:27:22.270549 Filename '826934/tftp-deploy-7kw3hh21/kernel/uImage'.
1177 12:27:22.274445 Load address: 0x1080000
1178 12:27:32.951606 Loading: *###########################################T ####### 43.6 MiB
1179 12:27:32.952485 4.1 MiB/s
1180 12:27:32.953105 done
1181 12:27:32.955770 Bytes transferred = 45713984 (2b98a40 hex)
1182 12:27:32.956963 Sending with 10 millisecond of delay
1184 12:27:37.646912 => tftpboot 0x08000000 826934/tftp-deploy-7kw3hh21/ramdisk/ramdisk.cpio.gz.uboot
1185 12:27:37.657625 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:57)
1186 12:27:37.658157 tftpboot 0x08000000 826934/tftp-deploy-7kw3hh21/ramdisk/ramdisk.cpio.gz.uboot
1187 12:27:37.658402 Speed: 1000, full duplex
1188 12:27:37.658615 Using ethernet@ff3f0000 device
1189 12:27:37.660113 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1190 12:27:37.671855 Filename '826934/tftp-deploy-7kw3hh21/ramdisk/ramdisk.cpio.gz.uboot'.
1191 12:27:37.672346 Load address: 0x8000000
1192 12:27:39.661074 Loading: *################################################# UDP wrong checksum 00000005 00006c00
1193 12:27:44.662999 T UDP wrong checksum 00000005 00006c00
1194 12:27:54.664571 T T UDP wrong checksum 00000005 00006c00
1195 12:28:05.096497 T T UDP wrong checksum 000000ff 000007c8
1196 12:28:05.116463 UDP wrong checksum 000000ff 0000a4ba
1197 12:28:14.669087 T T UDP wrong checksum 00000005 00006c00
1198 12:28:26.007490 T T UDP wrong checksum 000000ff 0000120d
1199 12:28:26.017666 UDP wrong checksum 000000ff 0000f8ed
1200 12:28:26.037455 UDP wrong checksum 000000ff 00006a93
1201 12:28:26.047721 UDP wrong checksum 000000ff 00005176
1202 12:28:34.673209 T
1203 12:28:34.673905 Retry count exceeded; starting again
1205 12:28:34.675489 end: 2.4.3 bootloader-commands (duration 00:01:23) [common]
1208 12:28:34.677608 end: 2.4 uboot-commands (duration 00:02:00) [common]
1210 12:28:34.679141 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1212 12:28:34.680324 end: 2 uboot-action (duration 00:02:00) [common]
1214 12:28:34.682061 Cleaning after the job
1215 12:28:34.682715 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/ramdisk
1216 12:28:34.684236 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/kernel
1217 12:28:34.732786 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/dtb
1218 12:28:34.733707 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/nfsrootfs
1219 12:28:34.760048 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826934/tftp-deploy-7kw3hh21/modules
1220 12:28:34.767507 start: 4.1 power-off (timeout 00:00:30) [common]
1221 12:28:34.768184 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1222 12:28:34.811918 >> OK - accepted request
1223 12:28:34.813705 Returned 0 in 0 seconds
1224 12:28:34.914424 end: 4.1 power-off (duration 00:00:00) [common]
1226 12:28:34.915366 start: 4.2 read-feedback (timeout 00:10:00) [common]
1227 12:28:34.916032 Listened to connection for namespace 'common' for up to 1s
1228 12:28:35.917024 Finalising connection for namespace 'common'
1229 12:28:35.917844 Disconnecting from shell: Finalise
1230 12:28:35.918523 =>
1231 12:28:36.020205 end: 4.2 read-feedback (duration 00:00:01) [common]
1232 12:28:36.020974 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/826934
1233 12:28:39.204760 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/826934
1234 12:28:39.205393 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.