Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 12:41:53.286757 lava-dispatcher, installed at version: 2024.01
2 12:41:53.287611 start: 0 validate
3 12:41:53.288151 Start time: 2024-10-09 12:41:53.288118+00:00 (UTC)
4 12:41:53.288719 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 12:41:53.289264 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 12:41:53.331315 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 12:41:53.331861 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-7-g556be13a9b36%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 12:41:53.361096 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 12:41:53.361722 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-7-g556be13a9b36%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 12:41:53.392592 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 12:41:53.393088 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:41:53.424453 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 12:41:53.424958 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Flee-mfd%2Ffor-mfd-next%2Fv6.12-rc1-7-g556be13a9b36%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 12:41:53.461741 validate duration: 0.17
16 12:41:53.462647 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:41:53.462988 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:41:53.463320 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:41:53.463907 Not decompressing ramdisk as can be used compressed.
20 12:41:53.464406 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 12:41:53.464712 saving as /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/ramdisk/initrd.cpio.gz
22 12:41:53.464999 total size: 5628140 (5 MB)
23 12:41:53.498923 progress 0 % (0 MB)
24 12:41:53.502896 progress 5 % (0 MB)
25 12:41:53.507060 progress 10 % (0 MB)
26 12:41:53.510760 progress 15 % (0 MB)
27 12:41:53.514833 progress 20 % (1 MB)
28 12:41:53.518469 progress 25 % (1 MB)
29 12:41:53.522457 progress 30 % (1 MB)
30 12:41:53.526584 progress 35 % (1 MB)
31 12:41:53.530244 progress 40 % (2 MB)
32 12:41:53.534286 progress 45 % (2 MB)
33 12:41:53.537905 progress 50 % (2 MB)
34 12:41:53.541890 progress 55 % (2 MB)
35 12:41:53.545876 progress 60 % (3 MB)
36 12:41:53.549493 progress 65 % (3 MB)
37 12:41:53.553690 progress 70 % (3 MB)
38 12:41:53.557297 progress 75 % (4 MB)
39 12:41:53.561270 progress 80 % (4 MB)
40 12:41:53.564854 progress 85 % (4 MB)
41 12:41:53.568880 progress 90 % (4 MB)
42 12:41:53.572702 progress 95 % (5 MB)
43 12:41:53.575999 progress 100 % (5 MB)
44 12:41:53.576669 5 MB downloaded in 0.11 s (48.07 MB/s)
45 12:41:53.577246 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:41:53.578164 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:41:53.578475 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:41:53.578761 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:41:53.579246 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/kernel/Image
51 12:41:53.579502 saving as /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/kernel/Image
52 12:41:53.579721 total size: 45713920 (43 MB)
53 12:41:53.580020 No compression specified
54 12:41:53.613941 progress 0 % (0 MB)
55 12:41:53.642682 progress 5 % (2 MB)
56 12:41:53.671308 progress 10 % (4 MB)
57 12:41:53.699906 progress 15 % (6 MB)
58 12:41:53.728791 progress 20 % (8 MB)
59 12:41:53.756897 progress 25 % (10 MB)
60 12:41:53.785960 progress 30 % (13 MB)
61 12:41:53.814613 progress 35 % (15 MB)
62 12:41:53.843870 progress 40 % (17 MB)
63 12:41:53.873651 progress 45 % (19 MB)
64 12:41:53.905551 progress 50 % (21 MB)
65 12:41:53.935435 progress 55 % (24 MB)
66 12:41:53.965070 progress 60 % (26 MB)
67 12:41:53.994183 progress 65 % (28 MB)
68 12:41:54.023789 progress 70 % (30 MB)
69 12:41:54.053490 progress 75 % (32 MB)
70 12:41:54.082984 progress 80 % (34 MB)
71 12:41:54.111428 progress 85 % (37 MB)
72 12:41:54.140190 progress 90 % (39 MB)
73 12:41:54.169201 progress 95 % (41 MB)
74 12:41:54.197686 progress 100 % (43 MB)
75 12:41:54.198255 43 MB downloaded in 0.62 s (70.48 MB/s)
76 12:41:54.198760 end: 1.2.1 http-download (duration 00:00:01) [common]
78 12:41:54.199611 end: 1.2 download-retry (duration 00:00:01) [common]
79 12:41:54.199912 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:41:54.200269 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:41:54.201119 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 12:41:54.201427 saving as /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/dtb/meson-g12b-a311d-libretech-cc.dtb
83 12:41:54.201649 total size: 54703 (0 MB)
84 12:41:54.201867 No compression specified
85 12:41:54.243085 progress 59 % (0 MB)
86 12:41:54.243950 progress 100 % (0 MB)
87 12:41:54.244551 0 MB downloaded in 0.04 s (1.22 MB/s)
88 12:41:54.245019 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:41:54.245830 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:41:54.246088 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:41:54.246348 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:41:54.246814 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 12:41:54.247059 saving as /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/nfsrootfs/full.rootfs.tar
95 12:41:54.247261 total size: 474398908 (452 MB)
96 12:41:54.247468 Using unxz to decompress xz
97 12:41:54.285557 progress 0 % (0 MB)
98 12:41:55.383686 progress 5 % (22 MB)
99 12:41:56.829687 progress 10 % (45 MB)
100 12:41:57.273045 progress 15 % (67 MB)
101 12:41:58.040134 progress 20 % (90 MB)
102 12:41:58.563754 progress 25 % (113 MB)
103 12:41:58.908797 progress 30 % (135 MB)
104 12:41:59.520781 progress 35 % (158 MB)
105 12:42:00.440900 progress 40 % (181 MB)
106 12:42:01.348800 progress 45 % (203 MB)
107 12:42:02.105408 progress 50 % (226 MB)
108 12:42:02.753658 progress 55 % (248 MB)
109 12:42:03.969335 progress 60 % (271 MB)
110 12:42:05.409562 progress 65 % (294 MB)
111 12:42:07.083300 progress 70 % (316 MB)
112 12:42:10.181909 progress 75 % (339 MB)
113 12:42:12.644275 progress 80 % (361 MB)
114 12:42:15.562337 progress 85 % (384 MB)
115 12:42:18.744329 progress 90 % (407 MB)
116 12:42:21.958049 progress 95 % (429 MB)
117 12:42:25.142123 progress 100 % (452 MB)
118 12:42:25.156342 452 MB downloaded in 30.91 s (14.64 MB/s)
119 12:42:25.156987 end: 1.4.1 http-download (duration 00:00:31) [common]
121 12:42:25.157816 end: 1.4 download-retry (duration 00:00:31) [common]
122 12:42:25.158075 start: 1.5 download-retry (timeout 00:09:28) [common]
123 12:42:25.158330 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 12:42:25.158972 downloading http://storage.kernelci.org/lee-mfd/for-mfd-next/v6.12-rc1-7-g556be13a9b36/arm64/defconfig/gcc-12/modules.tar.xz
125 12:42:25.159244 saving as /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/modules/modules.tar
126 12:42:25.159447 total size: 11609636 (11 MB)
127 12:42:25.159656 Using unxz to decompress xz
128 12:42:25.202624 progress 0 % (0 MB)
129 12:42:25.265903 progress 5 % (0 MB)
130 12:42:25.345000 progress 10 % (1 MB)
131 12:42:25.433216 progress 15 % (1 MB)
132 12:42:25.524099 progress 20 % (2 MB)
133 12:42:25.606068 progress 25 % (2 MB)
134 12:42:25.682799 progress 30 % (3 MB)
135 12:42:25.764658 progress 35 % (3 MB)
136 12:42:25.839424 progress 40 % (4 MB)
137 12:42:25.915886 progress 45 % (5 MB)
138 12:42:25.997444 progress 50 % (5 MB)
139 12:42:26.074348 progress 55 % (6 MB)
140 12:42:26.157764 progress 60 % (6 MB)
141 12:42:26.232213 progress 65 % (7 MB)
142 12:42:26.311547 progress 70 % (7 MB)
143 12:42:26.384323 progress 75 % (8 MB)
144 12:42:26.462930 progress 80 % (8 MB)
145 12:42:26.548809 progress 85 % (9 MB)
146 12:42:26.628915 progress 90 % (9 MB)
147 12:42:26.711836 progress 95 % (10 MB)
148 12:42:26.793575 progress 100 % (11 MB)
149 12:42:26.806094 11 MB downloaded in 1.65 s (6.72 MB/s)
150 12:42:26.807310 end: 1.5.1 http-download (duration 00:00:02) [common]
152 12:42:26.809528 end: 1.5 download-retry (duration 00:00:02) [common]
153 12:42:26.810223 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 12:42:26.810883 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 12:42:44.227333 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/826964/extract-nfsrootfs-d1sy6lir
156 12:42:44.227953 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 12:42:44.228270 start: 1.6.2 lava-overlay (timeout 00:09:09) [common]
158 12:42:44.229056 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr
159 12:42:44.229532 makedir: /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin
160 12:42:44.229868 makedir: /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/tests
161 12:42:44.230188 makedir: /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/results
162 12:42:44.230540 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-add-keys
163 12:42:44.231108 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-add-sources
164 12:42:44.231658 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-background-process-start
165 12:42:44.232228 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-background-process-stop
166 12:42:44.232815 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-common-functions
167 12:42:44.233353 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-echo-ipv4
168 12:42:44.233863 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-install-packages
169 12:42:44.234398 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-installed-packages
170 12:42:44.234911 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-os-build
171 12:42:44.235429 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-probe-channel
172 12:42:44.236040 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-probe-ip
173 12:42:44.236606 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-target-ip
174 12:42:44.237116 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-target-mac
175 12:42:44.237624 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-target-storage
176 12:42:44.238145 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-test-case
177 12:42:44.238695 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-test-event
178 12:42:44.239206 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-test-feedback
179 12:42:44.239709 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-test-raise
180 12:42:44.240262 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-test-reference
181 12:42:44.240788 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-test-runner
182 12:42:44.241299 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-test-set
183 12:42:44.241801 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-test-shell
184 12:42:44.242373 Updating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-install-packages (oe)
185 12:42:44.242968 Updating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/bin/lava-installed-packages (oe)
186 12:42:44.243447 Creating /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/environment
187 12:42:44.243855 LAVA metadata
188 12:42:44.244168 - LAVA_JOB_ID=826964
189 12:42:44.244387 - LAVA_DISPATCHER_IP=192.168.6.2
190 12:42:44.244781 start: 1.6.2.1 ssh-authorize (timeout 00:09:09) [common]
191 12:42:44.245828 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 12:42:44.246177 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:09) [common]
193 12:42:44.246386 skipped lava-vland-overlay
194 12:42:44.246627 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 12:42:44.246880 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:09) [common]
196 12:42:44.247102 skipped lava-multinode-overlay
197 12:42:44.247340 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 12:42:44.247590 start: 1.6.2.4 test-definition (timeout 00:09:09) [common]
199 12:42:44.247838 Loading test definitions
200 12:42:44.248152 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:09) [common]
201 12:42:44.248376 Using /lava-826964 at stage 0
202 12:42:44.249574 uuid=826964_1.6.2.4.1 testdef=None
203 12:42:44.249889 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 12:42:44.250149 start: 1.6.2.4.2 test-overlay (timeout 00:09:09) [common]
205 12:42:44.251870 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 12:42:44.252680 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:09) [common]
208 12:42:44.254849 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 12:42:44.255671 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:09) [common]
211 12:42:44.257761 runner path: /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 826964_1.6.2.4.1
212 12:42:44.258335 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 12:42:44.259082 Creating lava-test-runner.conf files
215 12:42:44.259280 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/826964/lava-overlay-ss50y_qr/lava-826964/0 for stage 0
216 12:42:44.259612 - 0_v4l2-decoder-conformance-vp9
217 12:42:44.259942 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 12:42:44.260233 start: 1.6.2.5 compress-overlay (timeout 00:09:09) [common]
219 12:42:44.281985 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 12:42:44.282348 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:09) [common]
221 12:42:44.282604 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 12:42:44.282868 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 12:42:44.283128 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:09) [common]
224 12:42:44.934818 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 12:42:44.935281 start: 1.6.4 extract-modules (timeout 00:09:09) [common]
226 12:42:44.935523 extracting modules file /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/modules/modules.tar to /var/lib/lava/dispatcher/tmp/826964/extract-nfsrootfs-d1sy6lir
227 12:42:46.318606 extracting modules file /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/modules/modules.tar to /var/lib/lava/dispatcher/tmp/826964/extract-overlay-ramdisk-g6vtyhd6/ramdisk
228 12:42:47.710685 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 12:42:47.711148 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
230 12:42:47.711424 [common] Applying overlay to NFS
231 12:42:47.711635 [common] Applying overlay /var/lib/lava/dispatcher/tmp/826964/compress-overlay-yb95kwyu/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/826964/extract-nfsrootfs-d1sy6lir
232 12:42:47.740705 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 12:42:47.741104 start: 1.6.6 prepare-kernel (timeout 00:09:06) [common]
234 12:42:47.741373 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:06) [common]
235 12:42:47.741598 Converting downloaded kernel to a uImage
236 12:42:47.741905 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/kernel/Image /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/kernel/uImage
237 12:42:48.203828 output: Image Name:
238 12:42:48.204276 output: Created: Wed Oct 9 12:42:47 2024
239 12:42:48.204488 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 12:42:48.204689 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 12:42:48.204888 output: Load Address: 01080000
242 12:42:48.205086 output: Entry Point: 01080000
243 12:42:48.205279 output:
244 12:42:48.205609 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 12:42:48.205872 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 12:42:48.206137 start: 1.6.7 configure-preseed-file (timeout 00:09:05) [common]
247 12:42:48.206383 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 12:42:48.206637 start: 1.6.8 compress-ramdisk (timeout 00:09:05) [common]
249 12:42:48.206888 Building ramdisk /var/lib/lava/dispatcher/tmp/826964/extract-overlay-ramdisk-g6vtyhd6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/826964/extract-overlay-ramdisk-g6vtyhd6/ramdisk
250 12:42:50.440688 >> 166772 blocks
251 12:42:58.210659 Adding RAMdisk u-boot header.
252 12:42:58.211111 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/826964/extract-overlay-ramdisk-g6vtyhd6/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/826964/extract-overlay-ramdisk-g6vtyhd6/ramdisk.cpio.gz.uboot
253 12:42:58.456456 output: Image Name:
254 12:42:58.456885 output: Created: Wed Oct 9 12:42:58 2024
255 12:42:58.457095 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 12:42:58.457299 output: Data Size: 23425157 Bytes = 22876.13 KiB = 22.34 MiB
257 12:42:58.457499 output: Load Address: 00000000
258 12:42:58.457696 output: Entry Point: 00000000
259 12:42:58.457890 output:
260 12:42:58.458491 rename /var/lib/lava/dispatcher/tmp/826964/extract-overlay-ramdisk-g6vtyhd6/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/ramdisk/ramdisk.cpio.gz.uboot
261 12:42:58.458898 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 12:42:58.459182 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
263 12:42:58.459455 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:55) [common]
264 12:42:58.459697 No LXC device requested
265 12:42:58.459951 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 12:42:58.460533 start: 1.8 deploy-device-env (timeout 00:08:55) [common]
267 12:42:58.461080 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 12:42:58.461531 Checking files for TFTP limit of 4294967296 bytes.
269 12:42:58.464484 end: 1 tftp-deploy (duration 00:01:05) [common]
270 12:42:58.465106 start: 2 uboot-action (timeout 00:05:00) [common]
271 12:42:58.465677 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 12:42:58.466216 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 12:42:58.466765 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 12:42:58.467337 Using kernel file from prepare-kernel: 826964/tftp-deploy-4eirm310/kernel/uImage
275 12:42:58.468047 substitutions:
276 12:42:58.468498 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 12:42:58.468936 - {DTB_ADDR}: 0x01070000
278 12:42:58.469371 - {DTB}: 826964/tftp-deploy-4eirm310/dtb/meson-g12b-a311d-libretech-cc.dtb
279 12:42:58.469804 - {INITRD}: 826964/tftp-deploy-4eirm310/ramdisk/ramdisk.cpio.gz.uboot
280 12:42:58.470235 - {KERNEL_ADDR}: 0x01080000
281 12:42:58.470662 - {KERNEL}: 826964/tftp-deploy-4eirm310/kernel/uImage
282 12:42:58.471087 - {LAVA_MAC}: None
283 12:42:58.471552 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/826964/extract-nfsrootfs-d1sy6lir
284 12:42:58.472006 - {NFS_SERVER_IP}: 192.168.6.2
285 12:42:58.472442 - {PRESEED_CONFIG}: None
286 12:42:58.472865 - {PRESEED_LOCAL}: None
287 12:42:58.473288 - {RAMDISK_ADDR}: 0x08000000
288 12:42:58.473705 - {RAMDISK}: 826964/tftp-deploy-4eirm310/ramdisk/ramdisk.cpio.gz.uboot
289 12:42:58.474127 - {ROOT_PART}: None
290 12:42:58.474551 - {ROOT}: None
291 12:42:58.474972 - {SERVER_IP}: 192.168.6.2
292 12:42:58.475392 - {TEE_ADDR}: 0x83000000
293 12:42:58.475810 - {TEE}: None
294 12:42:58.476259 Parsed boot commands:
295 12:42:58.476671 - setenv autoload no
296 12:42:58.477092 - setenv initrd_high 0xffffffff
297 12:42:58.477511 - setenv fdt_high 0xffffffff
298 12:42:58.477929 - dhcp
299 12:42:58.478349 - setenv serverip 192.168.6.2
300 12:42:58.478768 - tftpboot 0x01080000 826964/tftp-deploy-4eirm310/kernel/uImage
301 12:42:58.479189 - tftpboot 0x08000000 826964/tftp-deploy-4eirm310/ramdisk/ramdisk.cpio.gz.uboot
302 12:42:58.479605 - tftpboot 0x01070000 826964/tftp-deploy-4eirm310/dtb/meson-g12b-a311d-libretech-cc.dtb
303 12:42:58.480046 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/826964/extract-nfsrootfs-d1sy6lir,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 12:42:58.480488 - bootm 0x01080000 0x08000000 0x01070000
305 12:42:58.481026 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 12:42:58.482634 start: 2.3 connect-device (timeout 00:05:00) [common]
308 12:42:58.483084 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 12:42:58.498528 Setting prompt string to ['lava-test: # ']
310 12:42:58.500185 end: 2.3 connect-device (duration 00:00:00) [common]
311 12:42:58.500855 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 12:42:58.501446 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 12:42:58.502017 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 12:42:58.503224 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 12:42:58.540514 >> OK - accepted request
316 12:42:58.542665 Returned 0 in 0 seconds
317 12:42:58.643834 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 12:42:58.645606 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 12:42:58.646223 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 12:42:58.646785 Setting prompt string to ['Hit any key to stop autoboot']
322 12:42:58.647292 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 12:42:58.649007 Trying 192.168.56.21...
324 12:42:58.649538 Connected to conserv1.
325 12:42:58.649996 Escape character is '^]'.
326 12:42:58.650449
327 12:42:58.650911 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 12:42:58.651378
329 12:43:10.048887 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 12:43:10.049590 bl2_stage_init 0x01
331 12:43:10.050098 bl2_stage_init 0x81
332 12:43:10.054704 hw id: 0x0000 - pwm id 0x01
333 12:43:10.055342 bl2_stage_init 0xc1
334 12:43:10.055799 bl2_stage_init 0x02
335 12:43:10.056308
336 12:43:10.060073 L0:00000000
337 12:43:10.060648 L1:20000703
338 12:43:10.061081 L2:00008067
339 12:43:10.061518 L3:14000000
340 12:43:10.065719 B2:00402000
341 12:43:10.066249 B1:e0f83180
342 12:43:10.066678
343 12:43:10.067112 TE: 58167
344 12:43:10.067542
345 12:43:10.071228 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 12:43:10.071772
347 12:43:10.072248 Board ID = 1
348 12:43:10.076789 Set A53 clk to 24M
349 12:43:10.077308 Set A73 clk to 24M
350 12:43:10.077738 Set clk81 to 24M
351 12:43:10.082314 A53 clk: 1200 MHz
352 12:43:10.082858 A73 clk: 1200 MHz
353 12:43:10.083285 CLK81: 166.6M
354 12:43:10.083708 smccc: 00012abd
355 12:43:10.087933 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 12:43:10.093493 board id: 1
357 12:43:10.099116 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 12:43:10.110215 fw parse done
359 12:43:10.116076 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 12:43:10.158677 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 12:43:10.169542 PIEI prepare done
362 12:43:10.170042 fastboot data load
363 12:43:10.170481 fastboot data verify
364 12:43:10.175204 verify result: 266
365 12:43:10.180766 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 12:43:10.181265 LPDDR4 probe
367 12:43:10.181692 ddr clk to 1584MHz
368 12:43:10.188222 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 12:43:10.226078
370 12:43:10.226592 dmc_version 0001
371 12:43:10.231915 Check phy result
372 12:43:10.238620 INFO : End of CA training
373 12:43:10.239113 INFO : End of initialization
374 12:43:10.244259 INFO : Training has run successfully!
375 12:43:10.244773 Check phy result
376 12:43:10.249782 INFO : End of initialization
377 12:43:10.250274 INFO : End of read enable training
378 12:43:10.255399 INFO : End of fine write leveling
379 12:43:10.260998 INFO : End of Write leveling coarse delay
380 12:43:10.261494 INFO : Training has run successfully!
381 12:43:10.261922 Check phy result
382 12:43:10.266615 INFO : End of initialization
383 12:43:10.267106 INFO : End of read dq deskew training
384 12:43:10.272277 INFO : End of MPR read delay center optimization
385 12:43:10.277733 INFO : End of write delay center optimization
386 12:43:10.283356 INFO : End of read delay center optimization
387 12:43:10.283849 INFO : End of max read latency training
388 12:43:10.289003 INFO : Training has run successfully!
389 12:43:10.289490 1D training succeed
390 12:43:10.297889 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 12:43:10.345324 Check phy result
392 12:43:10.345944 INFO : End of initialization
393 12:43:10.368429 INFO : End of 2D read delay Voltage center optimization
394 12:43:10.388392 INFO : End of 2D read delay Voltage center optimization
395 12:43:10.440701 INFO : End of 2D write delay Voltage center optimization
396 12:43:10.490128 INFO : End of 2D write delay Voltage center optimization
397 12:43:10.495713 INFO : Training has run successfully!
398 12:43:10.496307
399 12:43:10.496774 channel==0
400 12:43:10.501344 RxClkDly_Margin_A0==88 ps 9
401 12:43:10.501853 TxDqDly_Margin_A0==98 ps 10
402 12:43:10.504720 RxClkDly_Margin_A1==88 ps 9
403 12:43:10.505241 TxDqDly_Margin_A1==98 ps 10
404 12:43:10.510336 TrainedVREFDQ_A0==74
405 12:43:10.510842 TrainedVREFDQ_A1==74
406 12:43:10.511294 VrefDac_Margin_A0==25
407 12:43:10.515782 DeviceVref_Margin_A0==40
408 12:43:10.516315 VrefDac_Margin_A1==24
409 12:43:10.521478 DeviceVref_Margin_A1==40
410 12:43:10.521981
411 12:43:10.522428
412 12:43:10.522870 channel==1
413 12:43:10.523304 RxClkDly_Margin_A0==98 ps 10
414 12:43:10.526969 TxDqDly_Margin_A0==88 ps 9
415 12:43:10.527479 RxClkDly_Margin_A1==98 ps 10
416 12:43:10.532606 TxDqDly_Margin_A1==88 ps 9
417 12:43:10.533114 TrainedVREFDQ_A0==77
418 12:43:10.533568 TrainedVREFDQ_A1==77
419 12:43:10.538355 VrefDac_Margin_A0==22
420 12:43:10.538867 DeviceVref_Margin_A0==37
421 12:43:10.543868 VrefDac_Margin_A1==22
422 12:43:10.544405 DeviceVref_Margin_A1==37
423 12:43:10.544852
424 12:43:10.549455 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 12:43:10.549965
426 12:43:10.577408 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000018 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 12:43:10.583037 2D training succeed
428 12:43:10.588631 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 12:43:10.589156 auto size-- 65535DDR cs0 size: 2048MB
430 12:43:10.594125 DDR cs1 size: 2048MB
431 12:43:10.594633 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 12:43:10.599730 cs0 DataBus test pass
433 12:43:10.600280 cs1 DataBus test pass
434 12:43:10.600736 cs0 AddrBus test pass
435 12:43:10.605337 cs1 AddrBus test pass
436 12:43:10.605845
437 12:43:10.606296 100bdlr_step_size ps== 420
438 12:43:10.606748 result report
439 12:43:10.610928 boot times 0Enable ddr reg access
440 12:43:10.618533 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 12:43:10.631858 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 12:43:11.205516 0.0;M3 CHK:0;cm4_sp_mode 0
443 12:43:11.206118 MVN_1=0x00000000
444 12:43:11.211119 MVN_2=0x00000000
445 12:43:11.216868 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 12:43:11.217366 OPS=0x10
447 12:43:11.217817 ring efuse init
448 12:43:11.218257 chipver efuse init
449 12:43:11.222481 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 12:43:11.228086 [0.018961 Inits done]
451 12:43:11.228584 secure task start!
452 12:43:11.229032 high task start!
453 12:43:11.232633 low task start!
454 12:43:11.233127 run into bl31
455 12:43:11.239391 NOTICE: BL31: v1.3(release):4fc40b1
456 12:43:11.247171 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 12:43:11.247677 NOTICE: BL31: G12A normal boot!
458 12:43:11.272486 NOTICE: BL31: BL33 decompress pass
459 12:43:11.278143 ERROR: Error initializing runtime service opteed_fast
460 12:43:12.510959
461 12:43:12.511320
462 12:43:12.519476 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 12:43:12.520055
464 12:43:12.520524 Model: Libre Computer AML-A311D-CC Alta
465 12:43:12.727786 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 12:43:12.751193 DRAM: 2 GiB (effective 3.8 GiB)
467 12:43:12.894744 Core: 408 devices, 31 uclasses, devicetree: separate
468 12:43:12.900679 WDT: Not starting watchdog@f0d0
469 12:43:12.933333 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 12:43:12.946386 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 12:43:12.949731 ** Bad device specification mmc 0 **
472 12:43:12.960086 Card did not respond to voltage select! : -110
473 12:43:12.967736 ** Bad device specification mmc 0 **
474 12:43:12.968271 Couldn't find partition mmc 0
475 12:43:12.976106 Card did not respond to voltage select! : -110
476 12:43:12.981572 ** Bad device specification mmc 0 **
477 12:43:12.982066 Couldn't find partition mmc 0
478 12:43:12.986652 Error: could not access storage.
479 12:43:14.249918 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 12:43:14.250600 bl2_stage_init 0x01
481 12:43:14.251081 bl2_stage_init 0x81
482 12:43:14.255508 hw id: 0x0000 - pwm id 0x01
483 12:43:14.256135 bl2_stage_init 0xc1
484 12:43:14.256602 bl2_stage_init 0x02
485 12:43:14.257045
486 12:43:14.261101 L0:00000000
487 12:43:14.261655 L1:20000703
488 12:43:14.262133 L2:00008067
489 12:43:14.262590 L3:14000000
490 12:43:14.263968 B2:00402000
491 12:43:14.264521 B1:e0f83180
492 12:43:14.264971
493 12:43:14.265415 TE: 58124
494 12:43:14.265853
495 12:43:14.275177 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 12:43:14.275776
497 12:43:14.276245 Board ID = 1
498 12:43:14.276676 Set A53 clk to 24M
499 12:43:14.277109 Set A73 clk to 24M
500 12:43:14.280799 Set clk81 to 24M
501 12:43:14.281351 A53 clk: 1200 MHz
502 12:43:14.281822 A73 clk: 1200 MHz
503 12:43:14.287732 CLK81: 166.6M
504 12:43:14.288470 smccc: 00012a92
505 12:43:14.292024 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 12:43:14.292566 board id: 1
507 12:43:14.300773 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 12:43:14.311806 fw parse done
509 12:43:14.317979 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 12:43:14.360743 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 12:43:14.370712 PIEI prepare done
512 12:43:14.371296 fastboot data load
513 12:43:14.371763 fastboot data verify
514 12:43:14.376487 verify result: 266
515 12:43:14.382108 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 12:43:14.382500 LPDDR4 probe
517 12:43:14.382858 ddr clk to 1584MHz
518 12:43:14.389865 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 12:43:14.427326
520 12:43:14.428024 dmc_version 0001
521 12:43:14.435340 Check phy result
522 12:43:14.439848 INFO : End of CA training
523 12:43:14.440444 INFO : End of initialization
524 12:43:14.445124 INFO : Training has run successfully!
525 12:43:14.445631 Check phy result
526 12:43:14.450800 INFO : End of initialization
527 12:43:14.451333 INFO : End of read enable training
528 12:43:14.456424 INFO : End of fine write leveling
529 12:43:14.461982 INFO : End of Write leveling coarse delay
530 12:43:14.462449 INFO : Training has run successfully!
531 12:43:14.462859 Check phy result
532 12:43:14.467597 INFO : End of initialization
533 12:43:14.468081 INFO : End of read dq deskew training
534 12:43:14.473174 INFO : End of MPR read delay center optimization
535 12:43:14.478770 INFO : End of write delay center optimization
536 12:43:14.484417 INFO : End of read delay center optimization
537 12:43:14.484878 INFO : End of max read latency training
538 12:43:14.489977 INFO : Training has run successfully!
539 12:43:14.490430 1D training succeed
540 12:43:14.499183 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 12:43:14.546813 Check phy result
542 12:43:14.547405 INFO : End of initialization
543 12:43:14.568575 INFO : End of 2D read delay Voltage center optimization
544 12:43:14.589009 INFO : End of 2D read delay Voltage center optimization
545 12:43:14.641268 INFO : End of 2D write delay Voltage center optimization
546 12:43:14.690312 INFO : End of 2D write delay Voltage center optimization
547 12:43:14.695882 INFO : Training has run successfully!
548 12:43:14.696471
549 12:43:14.696918 channel==0
550 12:43:14.701434 RxClkDly_Margin_A0==88 ps 9
551 12:43:14.701913 TxDqDly_Margin_A0==98 ps 10
552 12:43:14.706962 RxClkDly_Margin_A1==88 ps 9
553 12:43:14.707543 TxDqDly_Margin_A1==88 ps 9
554 12:43:14.708007 TrainedVREFDQ_A0==74
555 12:43:14.712814 TrainedVREFDQ_A1==74
556 12:43:14.713288 VrefDac_Margin_A0==25
557 12:43:14.713706 DeviceVref_Margin_A0==40
558 12:43:14.718298 VrefDac_Margin_A1==25
559 12:43:14.718761 DeviceVref_Margin_A1==40
560 12:43:14.719172
561 12:43:14.719657
562 12:43:14.720178 channel==1
563 12:43:14.723824 RxClkDly_Margin_A0==98 ps 10
564 12:43:14.724372 TxDqDly_Margin_A0==88 ps 9
565 12:43:14.729314 RxClkDly_Margin_A1==88 ps 9
566 12:43:14.729755 TxDqDly_Margin_A1==88 ps 9
567 12:43:14.735010 TrainedVREFDQ_A0==77
568 12:43:14.735465 TrainedVREFDQ_A1==77
569 12:43:14.735864 VrefDac_Margin_A0==22
570 12:43:14.741101 DeviceVref_Margin_A0==37
571 12:43:14.741594 VrefDac_Margin_A1==24
572 12:43:14.751042 DeviceVref_Margin_A1==37
573 12:43:14.751673
574 12:43:14.752114 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 12:43:14.752514
576 12:43:14.780165 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 12:43:14.780776 2D training succeed
578 12:43:14.785388 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 12:43:14.791066 auto size-- 65535DDR cs0 size: 2048MB
580 12:43:14.791523 DDR cs1 size: 2048MB
581 12:43:14.797960 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 12:43:14.798411 cs0 DataBus test pass
583 12:43:14.815165 cs1 DataBus test pass
584 12:43:14.815599 cs0 AddrBus test pass
585 12:43:14.816032 cs1 AddrBus test pass
586 12:43:14.816439
587 12:43:14.816833 100bdlr_step_size ps== 420
588 12:43:14.817236 result report
589 12:43:14.817621 boot times 0Enable ddr reg access
590 12:43:14.818600 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 12:43:14.831897 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 12:43:15.405080 0.0;M3 CHK:0;cm4_sp_mode 0
593 12:43:15.405664 MVN_1=0x00000000
594 12:43:15.410594 MVN_2=0x00000000
595 12:43:15.416315 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 12:43:15.416804 OPS=0x10
597 12:43:15.417245 ring efuse init
598 12:43:15.417638 chipver efuse init
599 12:43:15.421921 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 12:43:15.427526 [0.018961 Inits done]
601 12:43:15.427955 secure task start!
602 12:43:15.428383 high task start!
603 12:43:15.432070 low task start!
604 12:43:15.432490 run into bl31
605 12:43:15.438789 NOTICE: BL31: v1.3(release):4fc40b1
606 12:43:15.446546 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 12:43:15.446976 NOTICE: BL31: G12A normal boot!
608 12:43:15.471899 NOTICE: BL31: BL33 decompress pass
609 12:43:15.477612 ERROR: Error initializing runtime service opteed_fast
610 12:43:16.710685
611 12:43:16.711283
612 12:43:16.719012 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 12:43:16.719459
614 12:43:16.719866 Model: Libre Computer AML-A311D-CC Alta
615 12:43:16.927441 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 12:43:16.950762 DRAM: 2 GiB (effective 3.8 GiB)
617 12:43:17.093701 Core: 408 devices, 31 uclasses, devicetree: separate
618 12:43:17.099631 WDT: Not starting watchdog@f0d0
619 12:43:17.131928 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 12:43:17.144381 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 12:43:17.149384 ** Bad device specification mmc 0 **
622 12:43:17.159638 Card did not respond to voltage select! : -110
623 12:43:17.167260 ** Bad device specification mmc 0 **
624 12:43:17.167693 Couldn't find partition mmc 0
625 12:43:17.175702 Card did not respond to voltage select! : -110
626 12:43:17.181121 ** Bad device specification mmc 0 **
627 12:43:17.181558 Couldn't find partition mmc 0
628 12:43:17.185332 Error: could not access storage.
629 12:43:17.528821 Net: eth0: ethernet@ff3f0000
630 12:43:17.529350 starting USB...
631 12:43:17.781757 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 12:43:17.782245 Starting the controller
633 12:43:17.787695 USB XHCI 1.10
634 12:43:19.501117 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 12:43:19.501784 bl2_stage_init 0x01
636 12:43:19.502252 bl2_stage_init 0x81
637 12:43:19.506800 hw id: 0x0000 - pwm id 0x01
638 12:43:19.507322 bl2_stage_init 0xc1
639 12:43:19.507781 bl2_stage_init 0x02
640 12:43:19.508283
641 12:43:19.512256 L0:00000000
642 12:43:19.512771 L1:20000703
643 12:43:19.513223 L2:00008067
644 12:43:19.513674 L3:14000000
645 12:43:19.515222 B2:00402000
646 12:43:19.515727 B1:e0f83180
647 12:43:19.516214
648 12:43:19.516666 TE: 58167
649 12:43:19.517111
650 12:43:19.526379 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 12:43:19.526915
652 12:43:19.527374 Board ID = 1
653 12:43:19.527820 Set A53 clk to 24M
654 12:43:19.528296 Set A73 clk to 24M
655 12:43:19.531911 Set clk81 to 24M
656 12:43:19.532446 A53 clk: 1200 MHz
657 12:43:19.532899 A73 clk: 1200 MHz
658 12:43:19.535541 CLK81: 166.6M
659 12:43:19.536074 smccc: 00012abd
660 12:43:19.541325 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 12:43:19.546583 board id: 1
662 12:43:19.551841 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 12:43:19.562419 fw parse done
664 12:43:19.568422 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 12:43:19.610887 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 12:43:19.621802 PIEI prepare done
667 12:43:19.622310 fastboot data load
668 12:43:19.622766 fastboot data verify
669 12:43:19.627514 verify result: 266
670 12:43:19.633021 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 12:43:19.633530 LPDDR4 probe
672 12:43:19.633985 ddr clk to 1584MHz
673 12:43:19.641010 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 12:43:19.678247
675 12:43:19.678765 dmc_version 0001
676 12:43:19.684916 Check phy result
677 12:43:19.690802 INFO : End of CA training
678 12:43:19.691314 INFO : End of initialization
679 12:43:19.696538 INFO : Training has run successfully!
680 12:43:19.697044 Check phy result
681 12:43:19.702025 INFO : End of initialization
682 12:43:19.702533 INFO : End of read enable training
683 12:43:19.707649 INFO : End of fine write leveling
684 12:43:19.713256 INFO : End of Write leveling coarse delay
685 12:43:19.713763 INFO : Training has run successfully!
686 12:43:19.714217 Check phy result
687 12:43:19.718835 INFO : End of initialization
688 12:43:19.719337 INFO : End of read dq deskew training
689 12:43:19.724408 INFO : End of MPR read delay center optimization
690 12:43:19.730045 INFO : End of write delay center optimization
691 12:43:19.735563 INFO : End of read delay center optimization
692 12:43:19.736101 INFO : End of max read latency training
693 12:43:19.741209 INFO : Training has run successfully!
694 12:43:19.741715 1D training succeed
695 12:43:19.750352 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 12:43:19.797996 Check phy result
697 12:43:19.798526 INFO : End of initialization
698 12:43:19.819725 INFO : End of 2D read delay Voltage center optimization
699 12:43:19.840039 INFO : End of 2D read delay Voltage center optimization
700 12:43:19.892288 INFO : End of 2D write delay Voltage center optimization
701 12:43:19.942349 INFO : End of 2D write delay Voltage center optimization
702 12:43:19.947156 INFO : Training has run successfully!
703 12:43:19.947574
704 12:43:19.947812 channel==0
705 12:43:19.952960 RxClkDly_Margin_A0==88 ps 9
706 12:43:19.953754 TxDqDly_Margin_A0==98 ps 10
707 12:43:19.958315 RxClkDly_Margin_A1==88 ps 9
708 12:43:19.959500 TxDqDly_Margin_A1==88 ps 9
709 12:43:19.959833 TrainedVREFDQ_A0==74
710 12:43:19.964017 TrainedVREFDQ_A1==74
711 12:43:19.964673 VrefDac_Margin_A0==25
712 12:43:19.964931 DeviceVref_Margin_A0==40
713 12:43:19.969451 VrefDac_Margin_A1==25
714 12:43:19.969892 DeviceVref_Margin_A1==40
715 12:43:19.970123
716 12:43:19.970335
717 12:43:19.970540 channel==1
718 12:43:19.975578 RxClkDly_Margin_A0==88 ps 9
719 12:43:19.976201 TxDqDly_Margin_A0==88 ps 9
720 12:43:19.980801 RxClkDly_Margin_A1==88 ps 9
721 12:43:19.981222 TxDqDly_Margin_A1==88 ps 9
722 12:43:19.986127 TrainedVREFDQ_A0==77
723 12:43:19.986494 TrainedVREFDQ_A1==77
724 12:43:19.986726 VrefDac_Margin_A0==22
725 12:43:19.991745 DeviceVref_Margin_A0==37
726 12:43:19.992148 VrefDac_Margin_A1==24
727 12:43:19.992379 DeviceVref_Margin_A1==37
728 12:43:19.997488
729 12:43:19.997857 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 12:43:19.998105
731 12:43:20.031008 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
732 12:43:20.031687 2D training succeed
733 12:43:20.036668 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 12:43:20.042144 auto size-- 65535DDR cs0 size: 2048MB
735 12:43:20.042748 DDR cs1 size: 2048MB
736 12:43:20.047640 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 12:43:20.048234 cs0 DataBus test pass
738 12:43:20.053240 cs1 DataBus test pass
739 12:43:20.053779 cs0 AddrBus test pass
740 12:43:20.054238 cs1 AddrBus test pass
741 12:43:20.054688
742 12:43:20.058881 100bdlr_step_size ps== 420
743 12:43:20.059436 result report
744 12:43:20.064481 boot times 0Enable ddr reg access
745 12:43:20.069587 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 12:43:20.083041 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 12:43:20.656543 0.0;M3 CHK:0;cm4_sp_mode 0
748 12:43:20.657150 MVN_1=0x00000000
749 12:43:20.662144 MVN_2=0x00000000
750 12:43:20.667935 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 12:43:20.668594 OPS=0x10
752 12:43:20.669034 ring efuse init
753 12:43:20.669457 chipver efuse init
754 12:43:20.676214 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 12:43:20.676831 [0.018961 Inits done]
756 12:43:20.677283 secure task start!
757 12:43:20.683632 high task start!
758 12:43:20.684235 low task start!
759 12:43:20.684679 run into bl31
760 12:43:20.690279 NOTICE: BL31: v1.3(release):4fc40b1
761 12:43:20.698104 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 12:43:20.698632 NOTICE: BL31: G12A normal boot!
763 12:43:20.723485 NOTICE: BL31: BL33 decompress pass
764 12:43:20.729191 ERROR: Error initializing runtime service opteed_fast
765 12:43:21.961942
766 12:43:21.962308
767 12:43:21.970402 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 12:43:21.970932
769 12:43:21.971405 Model: Libre Computer AML-A311D-CC Alta
770 12:43:22.178778 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 12:43:22.202200 DRAM: 2 GiB (effective 3.8 GiB)
772 12:43:22.345190 Core: 408 devices, 31 uclasses, devicetree: separate
773 12:43:22.350302 WDT: Not starting watchdog@f0d0
774 12:43:22.383283 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 12:43:22.395779 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 12:43:22.399901 ** Bad device specification mmc 0 **
777 12:43:22.411147 Card did not respond to voltage select! : -110
778 12:43:22.418516 ** Bad device specification mmc 0 **
779 12:43:22.419019 Couldn't find partition mmc 0
780 12:43:22.427072 Card did not respond to voltage select! : -110
781 12:43:22.432688 ** Bad device specification mmc 0 **
782 12:43:22.433206 Couldn't find partition mmc 0
783 12:43:22.437742 Error: could not access storage.
784 12:43:22.780200 Net: eth0: ethernet@ff3f0000
785 12:43:22.780728 starting USB...
786 12:43:23.032064 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 12:43:23.032683 Starting the controller
788 12:43:23.039148 USB XHCI 1.10
789 12:43:25.199651 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 12:43:25.200109 bl2_stage_init 0x01
791 12:43:25.200341 bl2_stage_init 0x81
792 12:43:25.205050 hw id: 0x0000 - pwm id 0x01
793 12:43:25.205557 bl2_stage_init 0xc1
794 12:43:25.205977 bl2_stage_init 0x02
795 12:43:25.206400
796 12:43:25.210717 L0:00000000
797 12:43:25.211206 L1:20000703
798 12:43:25.211623 L2:00008067
799 12:43:25.212056 L3:14000000
800 12:43:25.213474 B2:00402000
801 12:43:25.213946 B1:e0f83180
802 12:43:25.214356
803 12:43:25.214759 TE: 58124
804 12:43:25.215327
805 12:43:25.224735 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 12:43:25.225241
807 12:43:25.225666 Board ID = 1
808 12:43:25.226290 Set A53 clk to 24M
809 12:43:25.226743 Set A73 clk to 24M
810 12:43:25.230290 Set clk81 to 24M
811 12:43:25.230926 A53 clk: 1200 MHz
812 12:43:25.231527 A73 clk: 1200 MHz
813 12:43:25.235834 CLK81: 166.6M
814 12:43:25.236496 smccc: 00012a91
815 12:43:25.241635 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 12:43:25.242383 board id: 1
817 12:43:25.249258 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 12:43:25.262274 fw parse done
819 12:43:25.266609 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 12:43:25.308690 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 12:43:25.320176 PIEI prepare done
822 12:43:25.320782 fastboot data load
823 12:43:25.321222 fastboot data verify
824 12:43:25.325954 verify result: 266
825 12:43:25.331436 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 12:43:25.332238 LPDDR4 probe
827 12:43:25.332827 ddr clk to 1584MHz
828 12:43:25.338786 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 12:43:25.376329
830 12:43:25.377020 dmc_version 0001
831 12:43:25.383222 Check phy result
832 12:43:25.389244 INFO : End of CA training
833 12:43:25.389899 INFO : End of initialization
834 12:43:25.394865 INFO : Training has run successfully!
835 12:43:25.395510 Check phy result
836 12:43:25.400424 INFO : End of initialization
837 12:43:25.401098 INFO : End of read enable training
838 12:43:25.403740 INFO : End of fine write leveling
839 12:43:25.409388 INFO : End of Write leveling coarse delay
840 12:43:25.414982 INFO : Training has run successfully!
841 12:43:25.415504 Check phy result
842 12:43:25.416112 INFO : End of initialization
843 12:43:25.420572 INFO : End of read dq deskew training
844 12:43:25.426251 INFO : End of MPR read delay center optimization
845 12:43:25.426754 INFO : End of write delay center optimization
846 12:43:25.431727 INFO : End of read delay center optimization
847 12:43:25.437360 INFO : End of max read latency training
848 12:43:25.437856 INFO : Training has run successfully!
849 12:43:25.442850 1D training succeed
850 12:43:25.448441 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 12:43:25.495496 Check phy result
852 12:43:25.496069 INFO : End of initialization
853 12:43:25.517791 INFO : End of 2D read delay Voltage center optimization
854 12:43:25.537279 INFO : End of 2D read delay Voltage center optimization
855 12:43:25.588146 INFO : End of 2D write delay Voltage center optimization
856 12:43:25.638412 INFO : End of 2D write delay Voltage center optimization
857 12:43:25.643898 INFO : Training has run successfully!
858 12:43:25.644520
859 12:43:25.644954 channel==0
860 12:43:25.649475 RxClkDly_Margin_A0==88 ps 9
861 12:43:25.650049 TxDqDly_Margin_A0==98 ps 10
862 12:43:25.655135 RxClkDly_Margin_A1==88 ps 9
863 12:43:25.655607 TxDqDly_Margin_A1==98 ps 10
864 12:43:25.656170 TrainedVREFDQ_A0==74
865 12:43:25.660676 TrainedVREFDQ_A1==74
866 12:43:25.661154 VrefDac_Margin_A0==25
867 12:43:25.661574 DeviceVref_Margin_A0==40
868 12:43:25.666299 VrefDac_Margin_A1==25
869 12:43:25.666796 DeviceVref_Margin_A1==40
870 12:43:25.667198
871 12:43:25.667733
872 12:43:25.671919 channel==1
873 12:43:25.672449 RxClkDly_Margin_A0==88 ps 9
874 12:43:25.672843 TxDqDly_Margin_A0==98 ps 10
875 12:43:25.677475 RxClkDly_Margin_A1==88 ps 9
876 12:43:25.677936 TxDqDly_Margin_A1==88 ps 9
877 12:43:25.683182 TrainedVREFDQ_A0==77
878 12:43:25.683647 TrainedVREFDQ_A1==77
879 12:43:25.684073 VrefDac_Margin_A0==23
880 12:43:25.688699 DeviceVref_Margin_A0==37
881 12:43:25.689156 VrefDac_Margin_A1==24
882 12:43:25.694302 DeviceVref_Margin_A1==37
883 12:43:25.694756
884 12:43:25.695142 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 12:43:25.695530
886 12:43:25.727912 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000019 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 12:43:25.728431 2D training succeed
888 12:43:25.733501 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 12:43:25.739155 auto size-- 65535DDR cs0 size: 2048MB
890 12:43:25.739616 DDR cs1 size: 2048MB
891 12:43:25.744650 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 12:43:25.745103 cs0 DataBus test pass
893 12:43:25.750270 cs1 DataBus test pass
894 12:43:25.750723 cs0 AddrBus test pass
895 12:43:25.751112 cs1 AddrBus test pass
896 12:43:25.751493
897 12:43:25.755840 100bdlr_step_size ps== 420
898 12:43:25.756339 result report
899 12:43:25.761508 boot times 0Enable ddr reg access
900 12:43:25.766342 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 12:43:25.779294 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 12:43:26.352294 0.0;M3 CHK:0;cm4_sp_mode 0
903 12:43:26.352704 MVN_1=0x00000000
904 12:43:26.357702 MVN_2=0x00000000
905 12:43:26.363466 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 12:43:26.363772 OPS=0x10
907 12:43:26.364023 ring efuse init
908 12:43:26.364245 chipver efuse init
909 12:43:26.371851 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 12:43:26.372158 [0.018961 Inits done]
911 12:43:26.372381 secure task start!
912 12:43:26.379275 high task start!
913 12:43:26.379554 low task start!
914 12:43:26.379768 run into bl31
915 12:43:26.385989 NOTICE: BL31: v1.3(release):4fc40b1
916 12:43:26.393660 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 12:43:26.393952 NOTICE: BL31: G12A normal boot!
918 12:43:26.419347 NOTICE: BL31: BL33 decompress pass
919 12:43:26.423944 ERROR: Error initializing runtime service opteed_fast
920 12:43:27.657764
921 12:43:27.658177
922 12:43:27.665420 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 12:43:27.665726
924 12:43:27.665947 Model: Libre Computer AML-A311D-CC Alta
925 12:43:27.873902 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 12:43:27.898036 DRAM: 2 GiB (effective 3.8 GiB)
927 12:43:28.041011 Core: 408 devices, 31 uclasses, devicetree: separate
928 12:43:28.045871 WDT: Not starting watchdog@f0d0
929 12:43:28.079015 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 12:43:28.091497 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 12:43:28.096156 ** Bad device specification mmc 0 **
932 12:43:28.106820 Card did not respond to voltage select! : -110
933 12:43:28.114538 ** Bad device specification mmc 0 **
934 12:43:28.114997 Couldn't find partition mmc 0
935 12:43:28.122789 Card did not respond to voltage select! : -110
936 12:43:28.128322 ** Bad device specification mmc 0 **
937 12:43:28.128777 Couldn't find partition mmc 0
938 12:43:28.132482 Error: could not access storage.
939 12:43:28.475785 Net: eth0: ethernet@ff3f0000
940 12:43:28.476212 starting USB...
941 12:43:28.727636 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 12:43:28.728180 Starting the controller
943 12:43:28.734626 USB XHCI 1.10
944 12:43:30.599433 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 12:43:30.600054 bl2_stage_init 0x01
946 12:43:30.600485 bl2_stage_init 0x81
947 12:43:30.604922 hw id: 0x0000 - pwm id 0x01
948 12:43:30.605362 bl2_stage_init 0xc1
949 12:43:30.605770 bl2_stage_init 0x02
950 12:43:30.606173
951 12:43:30.610598 L0:00000000
952 12:43:30.611027 L1:20000703
953 12:43:30.611433 L2:00008067
954 12:43:30.611827 L3:14000000
955 12:43:30.616274 B2:00402000
956 12:43:30.616717 B1:e0f83180
957 12:43:30.617118
958 12:43:30.617514 TE: 58124
959 12:43:30.617913
960 12:43:30.621701 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 12:43:30.622128
962 12:43:30.622531 Board ID = 1
963 12:43:30.627509 Set A53 clk to 24M
964 12:43:30.627935 Set A73 clk to 24M
965 12:43:30.628370 Set clk81 to 24M
966 12:43:30.632970 A53 clk: 1200 MHz
967 12:43:30.633403 A73 clk: 1200 MHz
968 12:43:30.633800 CLK81: 166.6M
969 12:43:30.634191 smccc: 00012a92
970 12:43:30.638665 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 12:43:30.644185 board id: 1
972 12:43:30.650083 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 12:43:30.660765 fw parse done
974 12:43:30.666767 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 12:43:30.709191 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 12:43:30.720095 PIEI prepare done
977 12:43:30.720517 fastboot data load
978 12:43:30.720908 fastboot data verify
979 12:43:30.725700 verify result: 266
980 12:43:30.731441 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 12:43:30.732368 LPDDR4 probe
982 12:43:30.732873 ddr clk to 1584MHz
983 12:43:30.739253 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 12:43:30.776499
985 12:43:30.776749 dmc_version 0001
986 12:43:30.783265 Check phy result
987 12:43:30.789049 INFO : End of CA training
988 12:43:30.789282 INFO : End of initialization
989 12:43:30.794679 INFO : Training has run successfully!
990 12:43:30.794913 Check phy result
991 12:43:30.800356 INFO : End of initialization
992 12:43:30.801258 INFO : End of read enable training
993 12:43:30.805947 INFO : End of fine write leveling
994 12:43:30.811427 INFO : End of Write leveling coarse delay
995 12:43:30.811654 INFO : Training has run successfully!
996 12:43:30.811856 Check phy result
997 12:43:30.817074 INFO : End of initialization
998 12:43:30.817300 INFO : End of read dq deskew training
999 12:43:30.822770 INFO : End of MPR read delay center optimization
1000 12:43:30.828364 INFO : End of write delay center optimization
1001 12:43:30.833875 INFO : End of read delay center optimization
1002 12:43:30.834103 INFO : End of max read latency training
1003 12:43:30.839515 INFO : Training has run successfully!
1004 12:43:30.840441 1D training succeed
1005 12:43:30.848724 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 12:43:30.896309 Check phy result
1007 12:43:30.896896 INFO : End of initialization
1008 12:43:30.918158 INFO : End of 2D read delay Voltage center optimization
1009 12:43:30.938374 INFO : End of 2D read delay Voltage center optimization
1010 12:43:30.990446 INFO : End of 2D write delay Voltage center optimization
1011 12:43:31.039865 INFO : End of 2D write delay Voltage center optimization
1012 12:43:31.045350 INFO : Training has run successfully!
1013 12:43:31.045907
1014 12:43:31.046361 channel==0
1015 12:43:31.051006 RxClkDly_Margin_A0==88 ps 9
1016 12:43:31.051560 TxDqDly_Margin_A0==98 ps 10
1017 12:43:31.056538 RxClkDly_Margin_A1==88 ps 9
1018 12:43:31.057059 TxDqDly_Margin_A1==88 ps 9
1019 12:43:31.057504 TrainedVREFDQ_A0==74
1020 12:43:31.062139 TrainedVREFDQ_A1==74
1021 12:43:31.062705 VrefDac_Margin_A0==24
1022 12:43:31.063164 DeviceVref_Margin_A0==40
1023 12:43:31.067802 VrefDac_Margin_A1==25
1024 12:43:31.068394 DeviceVref_Margin_A1==40
1025 12:43:31.068838
1026 12:43:31.069275
1027 12:43:31.069705 channel==1
1028 12:43:31.073331 RxClkDly_Margin_A0==98 ps 10
1029 12:43:31.073862 TxDqDly_Margin_A0==98 ps 10
1030 12:43:31.078991 RxClkDly_Margin_A1==98 ps 10
1031 12:43:31.079514 TxDqDly_Margin_A1==88 ps 9
1032 12:43:31.084526 TrainedVREFDQ_A0==77
1033 12:43:31.085052 TrainedVREFDQ_A1==77
1034 12:43:31.085493 VrefDac_Margin_A0==22
1035 12:43:31.090141 DeviceVref_Margin_A0==37
1036 12:43:31.090662 VrefDac_Margin_A1==22
1037 12:43:31.095760 DeviceVref_Margin_A1==37
1038 12:43:31.096316
1039 12:43:31.096755 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 12:43:31.097185
1041 12:43:31.129328 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
1042 12:43:31.129911 2D training succeed
1043 12:43:31.135018 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 12:43:31.140567 auto size-- 65535DDR cs0 size: 2048MB
1045 12:43:31.141103 DDR cs1 size: 2048MB
1046 12:43:31.146153 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 12:43:31.146691 cs0 DataBus test pass
1048 12:43:31.151764 cs1 DataBus test pass
1049 12:43:31.152348 cs0 AddrBus test pass
1050 12:43:31.152791 cs1 AddrBus test pass
1051 12:43:31.153224
1052 12:43:31.157382 100bdlr_step_size ps== 420
1053 12:43:31.157929 result report
1054 12:43:31.163063 boot times 0Enable ddr reg access
1055 12:43:31.168306 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 12:43:31.181783 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 12:43:31.755366 0.0;M3 CHK:0;cm4_sp_mode 0
1058 12:43:31.756034 MVN_1=0x00000000
1059 12:43:31.760933 MVN_2=0x00000000
1060 12:43:31.766679 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 12:43:31.767231 OPS=0x10
1062 12:43:31.767701 ring efuse init
1063 12:43:31.768186 chipver efuse init
1064 12:43:31.774830 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 12:43:31.775402 [0.018961 Inits done]
1066 12:43:31.782453 secure task start!
1067 12:43:31.782999 high task start!
1068 12:43:31.783459 low task start!
1069 12:43:31.783901 run into bl31
1070 12:43:31.789110 NOTICE: BL31: v1.3(release):4fc40b1
1071 12:43:31.796033 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 12:43:31.796591 NOTICE: BL31: G12A normal boot!
1073 12:43:31.822249 NOTICE: BL31: BL33 decompress pass
1074 12:43:31.827117 ERROR: Error initializing runtime service opteed_fast
1075 12:43:33.060821
1076 12:43:33.061482
1077 12:43:33.069329 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 12:43:33.069894
1079 12:43:33.070366 Model: Libre Computer AML-A311D-CC Alta
1080 12:43:33.277673 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 12:43:33.301055 DRAM: 2 GiB (effective 3.8 GiB)
1082 12:43:33.444240 Core: 408 devices, 31 uclasses, devicetree: separate
1083 12:43:33.449977 WDT: Not starting watchdog@f0d0
1084 12:43:33.482103 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 12:43:33.494593 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 12:43:33.499091 ** Bad device specification mmc 0 **
1087 12:43:33.509991 Card did not respond to voltage select! : -110
1088 12:43:33.516863 ** Bad device specification mmc 0 **
1089 12:43:33.517477 Couldn't find partition mmc 0
1090 12:43:33.526106 Card did not respond to voltage select! : -110
1091 12:43:33.531418 ** Bad device specification mmc 0 **
1092 12:43:33.532072 Couldn't find partition mmc 0
1093 12:43:33.535500 Error: could not access storage.
1094 12:43:33.878567 Net: eth0: ethernet@ff3f0000
1095 12:43:33.879197 starting USB...
1096 12:43:34.130705 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 12:43:34.131329 Starting the controller
1098 12:43:34.137096 USB XHCI 1.10
1099 12:43:35.691968 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 12:43:35.699394 scanning usb for storage devices... 0 Storage Device(s) found
1102 12:43:35.751171 Hit any key to stop autoboot: 1
1103 12:43:35.752110 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 12:43:35.752525 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 12:43:35.752818 Setting prompt string to ['=>']
1106 12:43:35.753107 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 12:43:35.767229 0
1108 12:43:35.768071 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 12:43:35.768410 Sending with 10 millisecond of delay
1111 12:43:36.902805 => setenv autoload no
1112 12:43:36.913346 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 12:43:36.915849 setenv autoload no
1114 12:43:36.916540 Sending with 10 millisecond of delay
1116 12:43:38.715079 => setenv initrd_high 0xffffffff
1117 12:43:38.725668 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 12:43:38.726219 setenv initrd_high 0xffffffff
1119 12:43:38.726702 Sending with 10 millisecond of delay
1121 12:43:40.342950 => setenv fdt_high 0xffffffff
1122 12:43:40.353762 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 12:43:40.354635 setenv fdt_high 0xffffffff
1124 12:43:40.355395 Sending with 10 millisecond of delay
1126 12:43:40.647346 => dhcp
1127 12:43:40.658181 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 12:43:40.659083 dhcp
1129 12:43:40.659559 Speed: 1000, full duplex
1130 12:43:40.660048 BOOTP broadcast 1
1131 12:43:40.905456 BOOTP broadcast 2
1132 12:43:41.103425 DHCP client bound to address 192.168.6.33 (446 ms)
1133 12:43:41.104673 Sending with 10 millisecond of delay
1135 12:43:42.782341 => setenv serverip 192.168.6.2
1136 12:43:42.793130 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1137 12:43:42.794025 setenv serverip 192.168.6.2
1138 12:43:42.794774 Sending with 10 millisecond of delay
1140 12:43:46.518238 => tftpboot 0x01080000 826964/tftp-deploy-4eirm310/kernel/uImage
1141 12:43:46.529046 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1142 12:43:46.529913 tftpboot 0x01080000 826964/tftp-deploy-4eirm310/kernel/uImage
1143 12:43:46.530339 Speed: 1000, full duplex
1144 12:43:46.530733 Using ethernet@ff3f0000 device
1145 12:43:46.531704 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1146 12:43:46.537201 Filename '826964/tftp-deploy-4eirm310/kernel/uImage'.
1147 12:43:46.541067 Load address: 0x1080000
1148 12:43:50.658555 Loading: *################################################## 43.6 MiB
1149 12:43:50.659232 10.6 MiB/s
1150 12:43:50.659703 done
1151 12:43:50.663056 Bytes transferred = 45713984 (2b98a40 hex)
1152 12:43:50.663874 Sending with 10 millisecond of delay
1154 12:43:55.350263 => tftpboot 0x08000000 826964/tftp-deploy-4eirm310/ramdisk/ramdisk.cpio.gz.uboot
1155 12:43:55.363485 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
1156 12:43:55.364050 tftpboot 0x08000000 826964/tftp-deploy-4eirm310/ramdisk/ramdisk.cpio.gz.uboot
1157 12:43:55.364298 Speed: 1000, full duplex
1158 12:43:55.364509 Using ethernet@ff3f0000 device
1159 12:43:55.364756 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1160 12:43:55.375957 Filename '826964/tftp-deploy-4eirm310/ramdisk/ramdisk.cpio.gz.uboot'.
1161 12:43:55.376270 Load address: 0x8000000
1162 12:43:57.975263 Loading: *################################################# UDP wrong checksum 00000005 0000e891
1163 12:44:02.977829 T UDP wrong checksum 00000005 0000e891
1164 12:44:12.979594 T T UDP wrong checksum 00000005 0000e891
1165 12:44:19.247612 T UDP wrong checksum 000000ff 0000eb45
1166 12:44:19.260942 UDP wrong checksum 000000ff 000043be
1167 12:44:23.160379 T UDP wrong checksum 000000ff 00003f50
1168 12:44:23.172411 UDP wrong checksum 000000ff 0000c242
1169 12:44:32.983901 T T UDP wrong checksum 00000005 0000e891
1170 12:44:52.988908 T T T
1171 12:44:52.989517 Retry count exceeded; starting again
1173 12:44:52.990939 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1176 12:44:52.992882 end: 2.4 uboot-commands (duration 00:01:54) [common]
1178 12:44:52.994330 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1180 12:44:52.995311 end: 2 uboot-action (duration 00:01:55) [common]
1182 12:44:52.996829 Cleaning after the job
1183 12:44:52.997367 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/ramdisk
1184 12:44:52.998669 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/kernel
1185 12:44:53.044735 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/dtb
1186 12:44:53.045595 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/nfsrootfs
1187 12:44:53.356261 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/826964/tftp-deploy-4eirm310/modules
1188 12:44:53.376788 start: 4.1 power-off (timeout 00:00:30) [common]
1189 12:44:53.377448 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1190 12:44:53.412612 >> OK - accepted request
1191 12:44:53.414854 Returned 0 in 0 seconds
1192 12:44:53.515571 end: 4.1 power-off (duration 00:00:00) [common]
1194 12:44:53.516535 start: 4.2 read-feedback (timeout 00:10:00) [common]
1195 12:44:53.517201 Listened to connection for namespace 'common' for up to 1s
1196 12:44:54.518075 Finalising connection for namespace 'common'
1197 12:44:54.518516 Disconnecting from shell: Finalise
1198 12:44:54.518778 =>
1199 12:44:54.619418 end: 4.2 read-feedback (duration 00:00:01) [common]
1200 12:44:54.619855 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/826964
1201 12:44:57.204994 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/826964
1202 12:44:57.205619 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.