Boot log: beaglebone-black
- Warnings: 3
- Kernel Warnings: 100
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 09:32:43.680405 lava-dispatcher, installed at version: 2024.01
2 09:32:43.680731 start: 0 validate
3 09:32:43.680883 Start time: 2024-09-19 09:32:43.680875+00:00 (UTC)
4 09:32:43.681062 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 09:32:43.982518 Validating that http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 09:32:44.127104 Validating that http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 09:32:44.274315 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 09:32:44.418153 Validating that http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 09:32:44.565443 validate duration: 0.88
11 09:32:44.566143 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 09:32:44.566383 start: 1.1 download-retry (timeout 00:10:00) [common]
13 09:32:44.566604 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 09:32:44.567070 Not decompressing ramdisk as can be used compressed.
15 09:32:44.567366 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 09:32:44.567563 saving as /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/ramdisk/initrd.cpio.gz
17 09:32:44.567723 total size: 4775763 (4 MB)
18 09:32:44.852024 progress 0 % (0 MB)
19 09:32:45.274248 progress 5 % (0 MB)
20 09:32:45.415150 progress 10 % (0 MB)
21 09:32:45.420523 progress 15 % (0 MB)
22 09:32:45.556008 progress 20 % (0 MB)
23 09:32:45.560788 progress 25 % (1 MB)
24 09:32:45.564785 progress 30 % (1 MB)
25 09:32:45.569079 progress 35 % (1 MB)
26 09:32:45.697577 progress 40 % (1 MB)
27 09:32:45.701321 progress 45 % (2 MB)
28 09:32:45.705088 progress 50 % (2 MB)
29 09:32:45.709198 progress 55 % (2 MB)
30 09:32:45.712858 progress 60 % (2 MB)
31 09:32:45.716496 progress 65 % (2 MB)
32 09:32:45.720483 progress 70 % (3 MB)
33 09:32:45.723752 progress 75 % (3 MB)
34 09:32:45.839188 progress 80 % (3 MB)
35 09:32:45.842827 progress 85 % (3 MB)
36 09:32:45.846867 progress 90 % (4 MB)
37 09:32:45.850466 progress 95 % (4 MB)
38 09:32:45.853853 progress 100 % (4 MB)
39 09:32:45.854425 4 MB downloaded in 1.29 s (3.54 MB/s)
40 09:32:45.854832 end: 1.1.1 http-download (duration 00:00:01) [common]
42 09:32:45.855460 end: 1.1 download-retry (duration 00:00:01) [common]
43 09:32:45.855716 start: 1.2 download-retry (timeout 00:09:59) [common]
44 09:32:45.855922 start: 1.2.1 http-download (timeout 00:09:59) [common]
45 09:32:45.856334 downloading http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 09:32:45.856531 saving as /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/kernel/zImage
47 09:32:45.856682 total size: 11403776 (10 MB)
48 09:32:45.856841 No compression specified
49 09:32:46.001029 progress 0 % (0 MB)
50 09:32:46.009561 progress 5 % (0 MB)
51 09:32:46.017974 progress 10 % (1 MB)
52 09:32:46.026877 progress 15 % (1 MB)
53 09:32:46.035205 progress 20 % (2 MB)
54 09:32:46.043264 progress 25 % (2 MB)
55 09:32:46.148546 progress 30 % (3 MB)
56 09:32:46.156980 progress 35 % (3 MB)
57 09:32:46.165825 progress 40 % (4 MB)
58 09:32:46.174170 progress 45 % (4 MB)
59 09:32:46.182404 progress 50 % (5 MB)
60 09:32:46.287097 progress 55 % (6 MB)
61 09:32:46.295516 progress 60 % (6 MB)
62 09:32:46.304457 progress 65 % (7 MB)
63 09:32:46.312802 progress 70 % (7 MB)
64 09:32:46.321528 progress 75 % (8 MB)
65 09:32:46.328918 progress 80 % (8 MB)
66 09:32:46.434322 progress 85 % (9 MB)
67 09:32:46.444737 progress 90 % (9 MB)
68 09:32:46.453108 progress 95 % (10 MB)
69 09:32:46.577066 progress 100 % (10 MB)
70 09:32:46.577356 10 MB downloaded in 0.72 s (15.09 MB/s)
71 09:32:46.577657 end: 1.2.1 http-download (duration 00:00:01) [common]
73 09:32:46.578118 end: 1.2 download-retry (duration 00:00:01) [common]
74 09:32:46.578289 start: 1.3 download-retry (timeout 00:09:58) [common]
75 09:32:46.578447 start: 1.3.1 http-download (timeout 00:09:58) [common]
76 09:32:46.578753 downloading http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 09:32:46.578887 saving as /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/dtb/am335x-boneblack.dtb
78 09:32:46.579003 total size: 70568 (0 MB)
79 09:32:46.579120 No compression specified
80 09:32:46.722436 progress 46 % (0 MB)
81 09:32:46.723244 progress 92 % (0 MB)
82 09:32:46.723943 progress 100 % (0 MB)
83 09:32:46.724255 0 MB downloaded in 0.15 s (0.46 MB/s)
84 09:32:46.724631 end: 1.3.1 http-download (duration 00:00:00) [common]
86 09:32:46.725214 end: 1.3 download-retry (duration 00:00:00) [common]
87 09:32:46.725417 start: 1.4 download-retry (timeout 00:09:58) [common]
88 09:32:46.725625 start: 1.4.1 http-download (timeout 00:09:58) [common]
89 09:32:46.726020 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 09:32:46.726189 saving as /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/nfsrootfs/full.rootfs.tar
91 09:32:46.726339 total size: 117747780 (112 MB)
92 09:32:46.726494 Using unxz to decompress xz
93 09:32:46.869861 progress 0 % (0 MB)
94 09:32:47.239546 progress 5 % (5 MB)
95 09:32:47.625419 progress 10 % (11 MB)
96 09:32:48.004385 progress 15 % (16 MB)
97 09:32:48.371561 progress 20 % (22 MB)
98 09:32:48.730583 progress 25 % (28 MB)
99 09:32:49.113714 progress 30 % (33 MB)
100 09:32:49.485527 progress 35 % (39 MB)
101 09:32:49.772681 progress 40 % (44 MB)
102 09:32:50.109050 progress 45 % (50 MB)
103 09:32:50.422049 progress 50 % (56 MB)
104 09:32:50.805033 progress 55 % (61 MB)
105 09:32:51.166792 progress 60 % (67 MB)
106 09:32:51.527174 progress 65 % (73 MB)
107 09:32:51.898211 progress 70 % (78 MB)
108 09:32:52.272251 progress 75 % (84 MB)
109 09:32:52.631578 progress 80 % (89 MB)
110 09:32:52.993290 progress 85 % (95 MB)
111 09:32:53.425915 progress 90 % (101 MB)
112 09:32:53.801890 progress 95 % (106 MB)
113 09:32:54.173123 progress 100 % (112 MB)
114 09:32:54.179076 112 MB downloaded in 7.45 s (15.07 MB/s)
115 09:32:54.179457 end: 1.4.1 http-download (duration 00:00:07) [common]
117 09:32:54.179960 end: 1.4 download-retry (duration 00:00:07) [common]
118 09:32:54.180126 start: 1.5 download-retry (timeout 00:09:50) [common]
119 09:32:54.180287 start: 1.5.1 http-download (timeout 00:09:50) [common]
120 09:32:54.180610 downloading http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 09:32:54.180743 saving as /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/modules/modules.tar
122 09:32:54.180859 total size: 6613592 (6 MB)
123 09:32:54.180979 Using unxz to decompress xz
124 09:32:54.325193 progress 0 % (0 MB)
125 09:32:54.344498 progress 5 % (0 MB)
126 09:32:54.364650 progress 10 % (0 MB)
127 09:32:54.385465 progress 15 % (0 MB)
128 09:32:54.408358 progress 20 % (1 MB)
129 09:32:54.429497 progress 25 % (1 MB)
130 09:32:54.452086 progress 30 % (1 MB)
131 09:32:54.473107 progress 35 % (2 MB)
132 09:32:54.494026 progress 40 % (2 MB)
133 09:32:54.514612 progress 45 % (2 MB)
134 09:32:54.535569 progress 50 % (3 MB)
135 09:32:54.557786 progress 55 % (3 MB)
136 09:32:54.578653 progress 60 % (3 MB)
137 09:32:54.599765 progress 65 % (4 MB)
138 09:32:54.620976 progress 70 % (4 MB)
139 09:32:54.642117 progress 75 % (4 MB)
140 09:32:54.663966 progress 80 % (5 MB)
141 09:32:54.685702 progress 85 % (5 MB)
142 09:32:54.706315 progress 90 % (5 MB)
143 09:32:54.726852 progress 95 % (6 MB)
144 09:32:54.890418 progress 100 % (6 MB)
145 09:32:54.894511 6 MB downloaded in 0.71 s (8.84 MB/s)
146 09:32:54.894943 end: 1.5.1 http-download (duration 00:00:01) [common]
148 09:32:54.895643 end: 1.5 download-retry (duration 00:00:01) [common]
149 09:32:54.895901 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
150 09:32:54.896153 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
151 09:33:00.317050 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/743617/extract-nfsrootfs-k28ofhyi
152 09:33:00.317354 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
153 09:33:00.317449 start: 1.6.2 lava-overlay (timeout 00:09:44) [common]
154 09:33:00.317745 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79
155 09:33:00.317894 makedir: /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin
156 09:33:00.318005 makedir: /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/tests
157 09:33:00.318109 makedir: /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/results
158 09:33:00.318223 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-add-keys
159 09:33:00.318406 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-add-sources
160 09:33:00.318558 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-background-process-start
161 09:33:00.318713 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-background-process-stop
162 09:33:00.318877 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-common-functions
163 09:33:00.319028 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-echo-ipv4
164 09:33:00.319181 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-install-packages
165 09:33:00.319328 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-installed-packages
166 09:33:00.319502 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-os-build
167 09:33:00.319705 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-probe-channel
168 09:33:00.319856 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-probe-ip
169 09:33:00.320015 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-target-ip
170 09:33:00.320161 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-target-mac
171 09:33:00.320308 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-target-storage
172 09:33:00.320459 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-test-case
173 09:33:00.320606 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-test-event
174 09:33:00.320753 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-test-feedback
175 09:33:00.320900 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-test-raise
176 09:33:00.321046 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-test-reference
177 09:33:00.321194 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-test-runner
178 09:33:00.321342 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-test-set
179 09:33:00.321489 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-test-shell
180 09:33:00.321644 Updating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-add-keys (debian)
181 09:33:00.321838 Updating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-add-sources (debian)
182 09:33:00.322024 Updating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-install-packages (debian)
183 09:33:00.322202 Updating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-installed-packages (debian)
184 09:33:00.322382 Updating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/bin/lava-os-build (debian)
185 09:33:00.322534 Creating /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/environment
186 09:33:00.322648 LAVA metadata
187 09:33:00.322719 - LAVA_JOB_ID=743617
188 09:33:00.322778 - LAVA_DISPATCHER_IP=192.168.56.76
189 09:33:00.322901 start: 1.6.2.1 ssh-authorize (timeout 00:09:44) [common]
190 09:33:00.323221 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 09:33:00.323312 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:44) [common]
192 09:33:00.323376 skipped lava-vland-overlay
193 09:33:00.323448 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 09:33:00.323540 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:44) [common]
195 09:33:00.323606 skipped lava-multinode-overlay
196 09:33:00.323678 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 09:33:00.323754 start: 1.6.2.4 test-definition (timeout 00:09:44) [common]
198 09:33:00.323825 Loading test definitions
199 09:33:00.323907 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:44) [common]
200 09:33:00.323971 Using /lava-743617 at stage 0
201 09:33:00.324353 uuid=743617_1.6.2.4.1 testdef=None
202 09:33:00.324444 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 09:33:00.324524 start: 1.6.2.4.2 test-overlay (timeout 00:09:44) [common]
204 09:33:00.325011 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 09:33:00.325225 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:44) [common]
207 09:33:00.325868 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 09:33:00.326107 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:44) [common]
210 09:33:00.326761 runner path: /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/0/tests/0_timesync-off test_uuid 743617_1.6.2.4.1
211 09:33:00.326954 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 09:33:00.327180 start: 1.6.2.4.5 git-repo-action (timeout 00:09:44) [common]
214 09:33:00.327249 Using /lava-743617 at stage 0
215 09:33:00.327351 Fetching tests from https://github.com/kernelci/test-definitions.git
216 09:33:00.327447 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/0/tests/1_kselftest-dt'
217 09:33:02.171815 Running '/usr/bin/git checkout kernelci.org
218 09:33:02.292057 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 09:33:02.292927 uuid=743617_1.6.2.4.5 testdef=None
220 09:33:02.293063 end: 1.6.2.4.5 git-repo-action (duration 00:00:02) [common]
222 09:33:02.293271 start: 1.6.2.4.6 test-overlay (timeout 00:09:42) [common]
223 09:33:02.294165 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 09:33:02.294388 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:42) [common]
226 09:33:02.295614 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 09:33:02.295873 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:42) [common]
229 09:33:02.297018 runner path: /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/0/tests/1_kselftest-dt test_uuid 743617_1.6.2.4.5
230 09:33:02.297110 BOARD='beaglebone-black'
231 09:33:02.297172 BRANCH='mainline'
232 09:33:02.297240 SKIPFILE='/dev/null'
233 09:33:02.297295 SKIP_INSTALL='True'
234 09:33:02.297347 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 09:33:02.297402 TST_CASENAME=''
236 09:33:02.297455 TST_CMDFILES='dt'
237 09:33:02.297666 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 09:33:02.297879 Creating lava-test-runner.conf files
240 09:33:02.297954 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/743617/lava-overlay-p24lfj79/lava-743617/0 for stage 0
241 09:33:02.298067 - 0_timesync-off
242 09:33:02.298132 - 1_kselftest-dt
243 09:33:02.298242 end: 1.6.2.4 test-definition (duration 00:00:02) [common]
244 09:33:02.298343 start: 1.6.2.5 compress-overlay (timeout 00:09:42) [common]
245 09:33:10.660700 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 09:33:10.660874 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
247 09:33:10.660958 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 09:33:10.661050 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
249 09:33:10.661150 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
250 09:33:10.786931 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 09:33:10.787254 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
252 09:33:10.787419 extracting modules file /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/743617/extract-nfsrootfs-k28ofhyi
253 09:33:11.105451 extracting modules file /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/743617/extract-overlay-ramdisk-ibl76lvh/ramdisk
254 09:33:11.435350 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 09:33:11.435572 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
256 09:33:11.435665 [common] Applying overlay to NFS
257 09:33:11.435727 [common] Applying overlay /var/lib/lava/dispatcher/tmp/743617/compress-overlay-e8nrslf9/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/743617/extract-nfsrootfs-k28ofhyi
258 09:33:12.559460 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 09:33:12.559661 start: 1.6.6 prepare-kernel (timeout 00:09:32) [common]
260 09:33:12.559748 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:32) [common]
261 09:33:12.559839 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 09:33:12.559916 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 09:33:12.560004 start: 1.6.7 configure-preseed-file (timeout 00:09:32) [common]
264 09:33:12.560081 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 09:33:12.560157 start: 1.6.8 compress-ramdisk (timeout 00:09:32) [common]
266 09:33:12.560227 Building ramdisk /var/lib/lava/dispatcher/tmp/743617/extract-overlay-ramdisk-ibl76lvh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/743617/extract-overlay-ramdisk-ibl76lvh/ramdisk
267 09:33:12.840929 >> 74838 blocks
268 09:33:14.632863 Adding RAMdisk u-boot header.
269 09:33:14.633080 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/743617/extract-overlay-ramdisk-ibl76lvh/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/743617/extract-overlay-ramdisk-ibl76lvh/ramdisk.cpio.gz.uboot
270 09:33:14.737975 output: Image Name:
271 09:33:14.738146 output: Created: Thu Sep 19 09:33:14 2024
272 09:33:14.738215 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 09:33:14.738285 output: Data Size: 14802836 Bytes = 14455.89 KiB = 14.12 MiB
274 09:33:14.738349 output: Load Address: 00000000
275 09:33:14.738411 output: Entry Point: 00000000
276 09:33:14.738480 output:
277 09:33:14.738623 rename /var/lib/lava/dispatcher/tmp/743617/extract-overlay-ramdisk-ibl76lvh/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/ramdisk/ramdisk.cpio.gz.uboot
278 09:33:14.738766 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 09:33:14.738861 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
280 09:33:14.738943 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:30) [common]
281 09:33:14.739027 No LXC device requested
282 09:33:14.739120 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 09:33:14.739204 start: 1.8 deploy-device-env (timeout 00:09:30) [common]
284 09:33:14.739280 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 09:33:14.739347 Checking files for TFTP limit of 4294967296 bytes.
286 09:33:14.739868 end: 1 tftp-deploy (duration 00:00:30) [common]
287 09:33:14.739975 start: 2 uboot-action (timeout 00:05:00) [common]
288 09:33:14.740057 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 09:33:14.740142 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 09:33:14.740229 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 09:33:14.740359 substitutions:
292 09:33:14.740421 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 09:33:14.740478 - {DTB_ADDR}: 0x88000000
294 09:33:14.740532 - {DTB}: 743617/tftp-deploy-s_g8aco4/dtb/am335x-boneblack.dtb
295 09:33:14.740592 - {INITRD}: 743617/tftp-deploy-s_g8aco4/ramdisk/ramdisk.cpio.gz.uboot
296 09:33:14.740666 - {KERNEL_ADDR}: 0x82000000
297 09:33:14.740721 - {KERNEL}: 743617/tftp-deploy-s_g8aco4/kernel/zImage
298 09:33:14.740776 - {LAVA_MAC}: None
299 09:33:14.740840 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/743617/extract-nfsrootfs-k28ofhyi
300 09:33:14.740897 - {NFS_SERVER_IP}: 192.168.56.76
301 09:33:14.740951 - {PRESEED_CONFIG}: None
302 09:33:14.741016 - {PRESEED_LOCAL}: None
303 09:33:14.741083 - {RAMDISK_ADDR}: 0x83000000
304 09:33:14.741139 - {RAMDISK}: 743617/tftp-deploy-s_g8aco4/ramdisk/ramdisk.cpio.gz.uboot
305 09:33:14.741195 - {ROOT_PART}: None
306 09:33:14.741248 - {ROOT}: None
307 09:33:14.741302 - {SERVER_IP}: 192.168.56.76
308 09:33:14.741356 - {TEE_ADDR}: 0x83000000
309 09:33:14.741425 - {TEE}: None
310 09:33:14.741484 Parsed boot commands:
311 09:33:14.741538 - setenv autoload no
312 09:33:14.741590 - setenv initrd_high 0xffffffff
313 09:33:14.741643 - setenv fdt_high 0xffffffff
314 09:33:14.741695 - dhcp
315 09:33:14.741750 - setenv serverip 192.168.56.76
316 09:33:14.741820 - tftp 0x82000000 743617/tftp-deploy-s_g8aco4/kernel/zImage
317 09:33:14.741877 - tftp 0x83000000 743617/tftp-deploy-s_g8aco4/ramdisk/ramdisk.cpio.gz.uboot
318 09:33:14.741930 - setenv initrd_size ${filesize}
319 09:33:14.741993 - tftp 0x88000000 743617/tftp-deploy-s_g8aco4/dtb/am335x-boneblack.dtb
320 09:33:14.742047 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/743617/extract-nfsrootfs-k28ofhyi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 09:33:14.742105 - bootz 0x82000000 0x83000000 0x88000000
322 09:33:14.742198 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 09:33:14.742424 start: 2.3 connect-device (timeout 00:05:00) [common]
325 09:33:14.742488 [common] connect-device Connecting to device using 'telnet conserv3 3000'
326 09:33:14.748943 Setting prompt string to ['lava-test: # ']
327 09:33:14.749725 end: 2.3 connect-device (duration 00:00:00) [common]
328 09:33:14.749994 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 09:33:14.750210 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 09:33:14.750447 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 09:33:14.750783 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
332 09:33:14.769715 >> OK - accepted request
333 09:33:14.770929 Returned 0 in 0 seconds
334 09:33:14.871696 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
336 09:33:14.872384 end: 2.4.1 reset-device (duration 00:00:00) [common]
337 09:33:14.872618 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
338 09:33:14.872820 Setting prompt string to ['Hit any key to stop autoboot']
339 09:33:14.872994 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
340 09:33:14.873668 Trying 192.168.56.22...
341 09:33:14.873839 Connected to conserv3.
342 09:33:14.874002 Escape character is '^]'.
343 09:33:14.874170
344 09:33:14.874329 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
345 09:33:14.874486
346 09:33:23.191471
347 09:33:23.198565 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
348 09:33:23.198872 Trying to boot from MMC1
349 09:33:23.779429
350 09:33:23.779707
351 09:33:23.784833 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
352 09:33:23.785108
353 09:33:23.785356 CPU : AM335X-GP rev 2.0
354 09:33:23.789291 Model: TI AM335x BeagleBone Black
355 09:33:23.789485 DRAM: 512 MiB
356 09:33:27.246779
357 09:33:27.254199 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
358 09:33:27.254600 Trying to boot from MMC1
359 09:33:27.831783
360 09:33:27.832090
361 09:33:27.837368 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
362 09:33:27.837695
363 09:33:27.837867 CPU : AM335X-GP rev 2.0
364 09:33:27.842576 Model: TI AM335x BeagleBone Black
365 09:33:27.842887 DRAM: 512 MiB
366 09:33:29.940605
367 09:33:29.947692 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
368 09:33:29.948087 Trying to boot from MMC1
369 09:33:30.525625
370 09:33:30.525930
371 09:33:30.531016 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
372 09:33:30.531325
373 09:33:30.531507 CPU : AM335X-GP rev 2.0
374 09:33:30.536190 Model: TI AM335x BeagleBone Black
375 09:33:30.536545 DRAM: 512 MiB
376 09:33:30.620893 Core: 160 devices, 18 uclasses, devicetree: separate
377 09:33:30.634749 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
378 09:33:31.035528 NAND: 0 MiB
379 09:33:31.045576 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
380 09:33:31.119972 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
381 09:33:31.141637 <ethaddr> not set. Validating first E-fuse MAC
382 09:33:31.171430 Net: eth2: ethernet@4a100000, eth3: usb_ether
384 09:33:31.229696 Hit any key to stop autoboot: 2
385 09:33:31.230222 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
386 09:33:31.230490 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
387 09:33:31.230692 Setting prompt string to ['=>']
388 09:33:31.230875 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
389 09:33:31.239455 0
390 09:33:31.240199 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
391 09:33:31.240431 Sending with 10 millisecond of delay
393 09:33:32.379634 => setenv autoload no
394 09:33:32.390235 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
395 09:33:32.392258 setenv autoload no
396 09:33:32.392674 Sending with 10 millisecond of delay
398 09:33:34.194567 => setenv initrd_high 0xffffffff
399 09:33:34.205236 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
400 09:33:34.205738 setenv initrd_high 0xffffffff
401 09:33:34.206156 Sending with 10 millisecond of delay
403 09:33:35.830782 => setenv fdt_high 0xffffffff
404 09:33:35.841252 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
405 09:33:35.841763 setenv fdt_high 0xffffffff
406 09:33:35.842165 Sending with 10 millisecond of delay
408 09:33:36.134655 => dhcp
409 09:33:36.145164 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 09:33:36.145667 dhcp
411 09:33:36.147789 link up on port 0, speed 100, full duplex
412 09:33:36.148013 BOOTP broadcast 1
413 09:33:36.399448 BOOTP broadcast 2
414 09:33:36.901700 BOOTP broadcast 3
415 09:33:37.903346 BOOTP broadcast 4
416 09:33:39.905281 BOOTP broadcast 5
417 09:33:39.929158 *** Unhandled DHCP Option in OFFER/ACK: 42
418 09:33:39.957777 *** Unhandled DHCP Option in OFFER/ACK: 42
419 09:33:39.963920 DHCP client bound to address 192.168.56.9 (3813 ms)
420 09:33:39.964459 Sending with 10 millisecond of delay
422 09:33:41.771107 => setenv serverip 192.168.56.76
423 09:33:41.781716 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
424 09:33:41.782226 setenv serverip 192.168.56.76
425 09:33:41.782630 Sending with 10 millisecond of delay
427 09:33:45.273247 => tftp 0x82000000 743617/tftp-deploy-s_g8aco4/kernel/zImage
428 09:33:45.283718 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
429 09:33:45.284217 tftp 0x82000000 743617/tftp-deploy-s_g8aco4/kernel/zImage
430 09:33:45.284399 link up on port 0, speed 100, full duplex
431 09:33:45.288537 Using ethernet@4a100000 device
432 09:33:45.294245 TFTP from server 192.168.56.76; our IP address is 192.168.56.9
433 09:33:45.301614 Filename '743617/tftp-deploy-s_g8aco4/kernel/zImage'.
434 09:33:45.301874 Load address: 0x82000000
435 09:33:47.533354 Loading: *################################################## 10.9 MiB
436 09:33:47.533643 4.9 MiB/s
437 09:33:47.533828 done
438 09:33:47.537389 Bytes transferred = 11403776 (ae0200 hex)
439 09:33:47.537834 Sending with 10 millisecond of delay
441 09:33:51.991446 => tftp 0x83000000 743617/tftp-deploy-s_g8aco4/ramdisk/ramdisk.cpio.gz.uboot
442 09:33:52.001988 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
443 09:33:52.002491 tftp 0x83000000 743617/tftp-deploy-s_g8aco4/ramdisk/ramdisk.cpio.gz.uboot
444 09:33:52.002695 link up on port 0, speed 100, full duplex
445 09:33:52.007049 Using ethernet@4a100000 device
446 09:33:52.012474 TFTP from server 192.168.56.76; our IP address is 192.168.56.9
447 09:33:52.021044 Filename '743617/tftp-deploy-s_g8aco4/ramdisk/ramdisk.cpio.gz.uboot'.
448 09:33:52.021283 Load address: 0x83000000
449 09:33:54.850435 Loading: *################################################## 14.1 MiB
450 09:33:54.850730 5 MiB/s
451 09:33:54.850897 done
452 09:33:54.854191 Bytes transferred = 14802900 (e1dfd4 hex)
453 09:33:54.854668 Sending with 10 millisecond of delay
455 09:33:56.718739 => setenv initrd_size ${filesize}
456 09:33:56.729275 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
457 09:33:56.729757 setenv initrd_size ${filesize}
458 09:33:56.730180 Sending with 10 millisecond of delay
460 09:34:00.893841 => tftp 0x88000000 743617/tftp-deploy-s_g8aco4/dtb/am335x-boneblack.dtb
461 09:34:00.904398 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
462 09:34:00.904868 tftp 0x88000000 743617/tftp-deploy-s_g8aco4/dtb/am335x-boneblack.dtb
463 09:34:00.905047 link up on port 0, speed 100, full duplex
464 09:34:00.909475 Using ethernet@4a100000 device
465 09:34:00.915056 TFTP from server 192.168.56.76; our IP address is 192.168.56.9
466 09:34:00.925263 Filename '743617/tftp-deploy-s_g8aco4/dtb/am335x-boneblack.dtb'.
467 09:34:00.925507 Load address: 0x88000000
468 09:34:00.936517 Loading: *################################################## 68.9 KiB
469 09:34:00.936751 4.5 MiB/s
470 09:34:00.945782 done
471 09:34:00.946102 Bytes transferred = 70568 (113a8 hex)
472 09:34:00.946492 Sending with 10 millisecond of delay
474 09:34:14.261985 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/743617/extract-nfsrootfs-k28ofhyi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
475 09:34:14.272404 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
476 09:34:14.272869 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/743617/extract-nfsrootfs-k28ofhyi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
477 09:34:14.273275 Sending with 10 millisecond of delay
479 09:34:16.614767 => bootz 0x82000000 0x83000000 0x88000000
480 09:34:16.625360 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
481 09:34:16.625701 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
482 09:34:16.626271 bootz 0x82000000 0x83000000 0x88000000
483 09:34:16.626505 Kernel image @ 0x82000000 [ 0x000000 - 0xae0200 ]
484 09:34:16.627426 ## Loading init Ramdisk from Legacy Image at 83000000 ...
485 09:34:16.633003 Image Name:
486 09:34:16.633265 Created: 2024-09-19 9:33:14 UTC
487 09:34:16.641993 Image Type: ARM Linux RAMDisk Image (uncompressed)
488 09:34:16.642295 Data Size: 14802836 Bytes = 14.1 MiB
489 09:34:16.650357 Load Address: 00000000
490 09:34:16.650611 Entry Point: 00000000
491 09:34:16.819293 Verifying Checksum ... OK
492 09:34:16.819701 ## Flattened Device Tree blob at 88000000
493 09:34:16.825166 Booting using the fdt blob at 0x88000000
494 09:34:16.825459 Working FDT set to 88000000
495 09:34:16.830957 Using Device Tree in place at 88000000, end 880143a7
496 09:34:16.835066 Working FDT set to 88000000
497 09:34:16.848378
498 09:34:16.848633 Starting kernel ...
499 09:34:16.848803
500 09:34:16.849283 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
501 09:34:16.849515 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
502 09:34:16.849695 Setting prompt string to ['Linux version [0-9]']
503 09:34:16.849874 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
504 09:34:16.850054 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
505 09:34:17.686003 [ 0.000000] Booting Linux on physical CPU 0x0
506 09:34:17.691428 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
507 09:34:17.691721 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
508 09:34:17.691946 Setting prompt string to []
509 09:34:17.692153 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
510 09:34:17.692340 Using line separator: #'\n'#
511 09:34:17.692497 No login prompt set.
512 09:34:17.692709 Parsing kernel messages
513 09:34:17.692897 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
514 09:34:17.693246 [login-action] Waiting for messages, (timeout 00:03:57)
515 09:34:17.693448 Waiting using forced prompt support (timeout 00:01:59)
516 09:34:17.705800 [ 0.000000] Linux version 6.11.0 (KernelCI@build-j314580-arm-gcc-12-multi-v7-defconfig-jpmwj) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Sep 19 08:53:27 UTC 2024
517 09:34:17.711461 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
518 09:34:17.722832 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
519 09:34:17.728459 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
520 09:34:17.734281 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
521 09:34:17.740071 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
522 09:34:17.746721 [ 0.000000] Memory policy: Data cache writeback
523 09:34:17.746973 [ 0.000000] efi: UEFI not found.
524 09:34:17.755560 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
525 09:34:17.761160 [ 0.000000] Zone ranges:
526 09:34:17.766837 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
527 09:34:17.767073 [ 0.000000] Normal empty
528 09:34:17.772935 [ 0.000000] HighMem empty
529 09:34:17.778375 [ 0.000000] Movable zone start for each node
530 09:34:17.778611 [ 0.000000] Early memory node ranges
531 09:34:17.784944 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
532 09:34:17.794202 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
533 09:34:17.818813 [ 0.000000] CPU: All CPU(s) started in SVC mode.
534 09:34:17.824384 [ 0.000000] AM335X ES2.0 (sgx neon)
535 09:34:17.836111 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
536 09:34:17.853762 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/743617/extract-nfsrootfs-k28ofhyi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
537 09:34:17.865598 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
538 09:34:17.871070 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
539 09:34:17.876849 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
540 09:34:17.887001 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
541 09:34:17.915994 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
542 09:34:17.921869 <6>[ 0.000000] trace event string verifier disabled
543 09:34:17.922156 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
544 09:34:17.929973 <6>[ 0.000000] rcu: RCU event tracing is enabled.
545 09:34:17.935671 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
546 09:34:17.947076 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
547 09:34:17.952024 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
548 09:34:17.967005 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
549 09:34:17.984225 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
550 09:34:17.990882 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
551 09:34:18.083977 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
552 09:34:18.095517 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
553 09:34:18.102142 <6>[ 0.008335] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
554 09:34:18.115404 <6>[ 0.019161] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
555 09:34:18.122750 <6>[ 0.034040] Console: colour dummy device 80x30
556 09:34:18.128692 Matched prompt #6: WARNING:
557 09:34:18.128972 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
558 09:34:18.134259 <3>[ 0.038935] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
559 09:34:18.139949 <3>[ 0.046000] This ensures that you still see kernel messages. Please
560 09:34:18.143320 <3>[ 0.052725] update your kernel commandline.
561 09:34:18.184097 <6>[ 0.057337] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
562 09:34:18.189567 <6>[ 0.096163] CPU: Testing write buffer coherency: ok
563 09:34:18.195538 <6>[ 0.101531] CPU0: Spectre v2: using BPIALL workaround
564 09:34:18.195768 <6>[ 0.106998] pid_max: default: 32768 minimum: 301
565 09:34:18.206951 <6>[ 0.112199] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 09:34:18.213760 <6>[ 0.120018] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 09:34:18.221227 <6>[ 0.129321] CPU0: thread -1, cpu 0, socket -1, mpidr 0
568 09:34:18.229161 <6>[ 0.136173] Setting up static identity map for 0x80300000 - 0x803000ac
569 09:34:18.235141 <6>[ 0.145781] rcu: Hierarchical SRCU implementation.
570 09:34:18.242771 <6>[ 0.151063] rcu: Max phase no-delay instances is 1000.
571 09:34:18.251129 <6>[ 0.162156] EFI services will not be available.
572 09:34:18.257029 <6>[ 0.167413] smp: Bringing up secondary CPUs ...
573 09:34:18.262694 <6>[ 0.172457] smp: Brought up 1 node, 1 CPU
574 09:34:18.269093 <6>[ 0.176856] SMP: Total of 1 processors activated (996.14 BogoMIPS).
575 09:34:18.274529 <6>[ 0.183608] CPU: All CPU(s) started in SVC mode.
576 09:34:18.294731 <6>[ 0.188789] Memory: 407012K/522240K available (16384K kernel code, 2545K rwdata, 6752K rodata, 2048K init, 432K bss, 48040K reserved, 65536K cma-reserved, 0K highmem)
577 09:34:18.295042 <6>[ 0.205043] devtmpfs: initialized
578 09:34:18.316877 <6>[ 0.222014] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
579 09:34:18.328675 <6>[ 0.230596] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
580 09:34:18.334295 <6>[ 0.241039] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
581 09:34:18.345151 <6>[ 0.253376] pinctrl core: initialized pinctrl subsystem
582 09:34:18.354341 <6>[ 0.264061] DMI not present or invalid.
583 09:34:18.362722 <6>[ 0.269887] NET: Registered PF_NETLINK/PF_ROUTE protocol family
584 09:34:18.372145 <6>[ 0.278781] DMA: preallocated 256 KiB pool for atomic coherent allocations
585 09:34:18.387324 <6>[ 0.290382] thermal_sys: Registered thermal governor 'step_wise'
586 09:34:18.387617 <6>[ 0.290527] cpuidle: using governor menu
587 09:34:18.415113 <6>[ 0.326474] No ATAGs?
588 09:34:18.421348 <6>[ 0.329116] hw-breakpoint: debug architecture 0x4 unsupported.
589 09:34:18.431580 <6>[ 0.341118] Serial: AMBA PL011 UART driver
590 09:34:18.471649 <6>[ 0.382925] iommu: Default domain type: Translated
591 09:34:18.480855 <6>[ 0.388154] iommu: DMA domain TLB invalidation policy: strict mode
592 09:34:18.490631 <5>[ 0.400442] SCSI subsystem initialized
593 09:34:18.514644 <6>[ 0.420265] usbcore: registered new interface driver usbfs
594 09:34:18.521849 <6>[ 0.426232] usbcore: registered new interface driver hub
595 09:34:18.522162 <6>[ 0.432059] usbcore: registered new device driver usb
596 09:34:18.527582 <6>[ 0.438525] pps_core: LinuxPPS API ver. 1 registered
597 09:34:18.538951 <6>[ 0.443958] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
598 09:34:18.547451 <6>[ 0.453658] PTP clock support registered
599 09:34:18.547734 <6>[ 0.458098] EDAC MC: Ver: 3.0.0
600 09:34:18.590455 <6>[ 0.498976] scmi_core: SCMI protocol bus registered
601 09:34:18.596441 <6>[ 0.507080] vgaarb: loaded
602 09:34:18.609246 <6>[ 0.520124] clocksource: Switched to clocksource dmtimer
603 09:34:18.654220 <6>[ 0.565224] NET: Registered PF_INET protocol family
604 09:34:18.666976 <6>[ 0.570894] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
605 09:34:18.672698 <6>[ 0.579704] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
606 09:34:18.684189 <6>[ 0.588634] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
607 09:34:18.690145 <6>[ 0.596893] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
608 09:34:18.701709 <6>[ 0.605184] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
609 09:34:18.707162 <6>[ 0.612901] TCP: Hash tables configured (established 4096 bind 4096)
610 09:34:18.713075 <6>[ 0.619803] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
611 09:34:18.718912 <6>[ 0.626841] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
612 09:34:18.726786 <6>[ 0.634445] NET: Registered PF_UNIX/PF_LOCAL protocol family
613 09:34:18.772453 <6>[ 0.678053] RPC: Registered named UNIX socket transport module.
614 09:34:18.772786 <6>[ 0.684503] RPC: Registered udp transport module.
615 09:34:18.778298 <6>[ 0.689611] RPC: Registered tcp transport module.
616 09:34:18.784548 <6>[ 0.694733] RPC: Registered tcp-with-tls transport module.
617 09:34:18.796963 <6>[ 0.700656] RPC: Registered tcp NFSv4.1 backchannel transport module.
618 09:34:18.797237 <6>[ 0.707562] PCI: CLS 0 bytes, default 64
619 09:34:18.803397 <5>[ 0.713338] Initialise system trusted keyrings
620 09:34:18.811119 <6>[ 0.718959] Trying to unpack rootfs image as initramfs...
621 09:34:18.845459 <6>[ 0.750519] workingset: timestamp_bits=30 max_order=17 bucket_order=0
622 09:34:18.850339 <6>[ 0.758005] squashfs: version 4.0 (2009/01/31) Phillip Lougher
623 09:34:18.890078 <5>[ 0.801347] NFS: Registering the id_resolver key type
624 09:34:18.895906 <5>[ 0.806972] Key type id_resolver registered
625 09:34:18.901641 <5>[ 0.811613] Key type id_legacy registered
626 09:34:18.910242 <6>[ 0.816048] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
627 09:34:18.917093 <6>[ 0.823241] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
628 09:34:18.969449 <5>[ 0.880690] Key type asymmetric registered
629 09:34:18.975348 <5>[ 0.885214] Asymmetric key parser 'x509' registered
630 09:34:18.987171 <6>[ 0.890739] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
631 09:34:18.987548 <6>[ 0.898629] io scheduler mq-deadline registered
632 09:34:18.992723 <6>[ 0.903606] io scheduler kyber registered
633 09:34:18.998478 <6>[ 0.908063] io scheduler bfq registered
634 09:34:19.331893 <6>[ 1.239172] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
635 09:34:19.364536 <6>[ 1.275427] msm_serial: driver initialized
636 09:34:19.370392 <6>[ 1.280402] SuperH (H)SCI(F) driver initialized
637 09:34:19.376401 <6>[ 1.285529] STMicroelectronics ASC driver initialized
638 09:34:19.381543 <6>[ 1.291194] STM32 USART driver initialized
639 09:34:19.496867 <6>[ 1.408493] brd: module loaded
640 09:34:19.534639 <6>[ 1.445242] loop: module loaded
641 09:34:19.587157 <6>[ 1.497509] CAN device driver interface
642 09:34:19.593791 <6>[ 1.502811] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
643 09:34:19.599453 <6>[ 1.509717] e1000e: Intel(R) PRO/1000 Network Driver
644 09:34:19.605493 <6>[ 1.515169] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
645 09:34:19.611046 <6>[ 1.521620] igb: Intel(R) Gigabit Ethernet Network Driver
646 09:34:19.619285 <6>[ 1.527441] igb: Copyright (c) 2007-2014 Intel Corporation.
647 09:34:19.630995 <6>[ 1.536659] pegasus: Pegasus/Pegasus II USB Ethernet driver
648 09:34:19.636860 <6>[ 1.542811] usbcore: registered new interface driver pegasus
649 09:34:19.642770 <6>[ 1.548950] usbcore: registered new interface driver asix
650 09:34:19.648430 <6>[ 1.554835] usbcore: registered new interface driver ax88179_178a
651 09:34:19.654336 <6>[ 1.561445] usbcore: registered new interface driver cdc_ether
652 09:34:19.660040 <6>[ 1.567743] usbcore: registered new interface driver smsc75xx
653 09:34:19.665743 <6>[ 1.573974] usbcore: registered new interface driver smsc95xx
654 09:34:19.671575 <6>[ 1.580203] usbcore: registered new interface driver net1080
655 09:34:19.677455 <6>[ 1.586319] usbcore: registered new interface driver cdc_subset
656 09:34:19.683178 <6>[ 1.592728] usbcore: registered new interface driver zaurus
657 09:34:19.690983 <6>[ 1.598781] usbcore: registered new interface driver cdc_ncm
658 09:34:19.700709 <6>[ 1.608268] usbcore: registered new interface driver usb-storage
659 09:34:19.803428 <6>[ 1.712624] i2c_dev: i2c /dev entries driver
660 09:34:19.863317 <5>[ 1.766561] cpuidle: enable-method property 'ti,am3352' found operations
661 09:34:19.869108 <6>[ 1.776100] sdhci: Secure Digital Host Controller Interface driver
662 09:34:19.876612 <6>[ 1.782880] sdhci: Copyright(c) Pierre Ossman
663 09:34:19.883907 <6>[ 1.789329] Synopsys Designware Multimedia Card Interface Driver
664 09:34:19.889506 <6>[ 1.797270] sdhci-pltfm: SDHCI platform and OF driver helper
665 09:34:19.963325 <6>[ 1.870812] ledtrig-cpu: registered to indicate activity on CPUs
666 09:34:20.027874 <6>[ 1.931475] usbcore: registered new interface driver usbhid
667 09:34:20.028182 <6>[ 1.937515] usbhid: USB HID core driver
668 09:34:20.048366 <6>[ 1.956984] NET: Registered PF_INET6 protocol family
669 09:34:20.099867 <6>[ 2.010933] Segment Routing with IPv6
670 09:34:20.105837 <6>[ 2.015083] In-situ OAM (IOAM) with IPv6
671 09:34:20.112713 <6>[ 2.019477] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
672 09:34:20.119734 <6>[ 2.026874] NET: Registered PF_PACKET protocol family
673 09:34:20.125473 <6>[ 2.032429] can: controller area network core
674 09:34:20.125713 <6>[ 2.037251] NET: Registered PF_CAN protocol family
675 09:34:20.131423 <6>[ 2.042478] can: raw protocol
676 09:34:20.137070 <6>[ 2.045805] can: broadcast manager protocol
677 09:34:20.143992 <6>[ 2.050398] can: netlink gateway - max_hops=1
678 09:34:20.144297 <5>[ 2.055917] Key type dns_resolver registered
679 09:34:20.149783 <6>[ 2.060989] ThumbEE CPU extension supported.
680 09:34:20.155920 <5>[ 2.065682] Registering SWP/SWPB emulation handler
681 09:34:20.164587 <3>[ 2.071372] omap_voltage_late_init: Voltage driver support not added
682 09:34:20.236526 <5>[ 2.145276] Loading compiled-in X.509 certificates
683 09:34:20.373949 <6>[ 2.272403] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
684 09:34:20.381189 <6>[ 2.289007] pinctrl-single 44e10800.pinmux: 142 pins, size 568
685 09:34:20.407690 <3>[ 2.312693] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
686 09:34:20.494147 <3>[ 2.399404] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
687 09:34:20.601363 <6>[ 2.510904] OMAP GPIO hardware version 0.1
688 09:34:20.622045 <6>[ 2.529440] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
689 09:34:20.685024 <4>[ 2.591883] at24 2-0054: supply vcc not found, using dummy regulator
690 09:34:20.738778 <4>[ 2.646122] at24 2-0055: supply vcc not found, using dummy regulator
691 09:34:20.778960 <4>[ 2.686116] at24 2-0056: supply vcc not found, using dummy regulator
692 09:34:20.831235 <4>[ 2.738431] at24 2-0057: supply vcc not found, using dummy regulator
693 09:34:20.876678 <6>[ 2.784763] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
694 09:34:20.951828 <3>[ 2.855937] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
695 09:34:20.976367 <6>[ 2.876783] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
696 09:34:20.997426 <4>[ 2.903264] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
697 09:34:21.034881 <4>[ 2.940796] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
698 09:34:21.102892 <6>[ 3.010441] omap_rng 48310000.rng: Random Number Generator ver. 20
699 09:34:21.126082 <5>[ 3.036506] random: crng init done
700 09:34:21.224677 <6>[ 3.130722] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
701 09:34:21.880187 <6>[ 3.789881] Freeing initrd memory: 14456K
702 09:34:21.927346 <6>[ 3.832532] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
703 09:34:21.933080 <4>[ 3.842841] ------------[ cut here ]------------
704 09:34:21.944635 <4>[ 3.847873] WARNING: CPU: 0 PID: 38 at drivers/base/regmap/regmap.c:1208 devm_regmap_field_alloc+0xb8/0xc4
705 09:34:21.950426 <4>[ 3.858191] invalid empty mask defined
706 09:34:21.950682 <4>[ 3.862352] Modules linked in:
707 09:34:21.956363 <4>[ 3.865775] CPU: 0 UID: 0 PID: 38 Comm: kworker/u4:4 Not tainted 6.11.0 #1
708 09:34:21.967622 <4>[ 3.873119] Hardware name: Generic AM33XX (Flattened Device Tree)
709 09:34:21.973495 <4>[ 3.879658] Workqueue: events_unbound deferred_probe_work_func
710 09:34:21.973789 <4>[ 3.885937] Call trace:
711 09:34:21.979323 <4>[ 3.885955] unwind_backtrace from show_stack+0x10/0x14
712 09:34:21.985006 <4>[ 3.894490] show_stack from dump_stack_lvl+0x68/0x74
713 09:34:21.990756 <4>[ 3.899976] dump_stack_lvl from __warn+0x7c/0x12c
714 09:34:21.996582 <4>[ 3.905191] __warn from warn_slowpath_fmt+0x124/0x190
715 09:34:22.002208 <4>[ 3.910758] warn_slowpath_fmt from devm_regmap_field_alloc+0xb8/0xc4
716 09:34:22.008168 <4>[ 3.917658] devm_regmap_field_alloc from cpsw_ale_create+0x124/0x368
717 09:34:22.013728 <4>[ 3.924576] cpsw_ale_create from cpsw_init_common+0x238/0x37c
718 09:34:22.019519 <4>[ 3.930860] cpsw_init_common from cpsw_probe+0x530/0xc60
719 09:34:22.025176 <4>[ 3.936696] cpsw_probe from platform_probe+0x5c/0xb0
720 09:34:22.030884 <4>[ 3.942176] platform_probe from really_probe+0xc8/0x2c8
721 09:34:22.042438 <4>[ 3.947920] really_probe from __driver_probe_device+0x88/0x19c
722 09:34:22.048168 <4>[ 3.954285] __driver_probe_device from driver_probe_device+0x30/0x104
723 09:34:22.053879 <4>[ 3.961273] driver_probe_device from __device_attach_driver+0x94/0x108
724 09:34:22.059667 <4>[ 3.968355] __device_attach_driver from bus_for_each_drv+0x90/0xe4
725 09:34:22.065425 <4>[ 3.975076] bus_for_each_drv from __device_attach+0xa8/0x1a4
726 09:34:22.071188 <4>[ 3.981261] __device_attach from bus_probe_device+0x88/0x8c
727 09:34:22.076935 <4>[ 3.987357] bus_probe_device from device_add+0x5a8/0x77c
728 09:34:22.088501 <4>[ 3.993185] device_add from of_platform_device_create_pdata+0x90/0xbc
729 09:34:22.094289 <4>[ 4.000190] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
730 09:34:22.099898 <4>[ 4.008440] of_platform_bus_create from of_platform_populate+0x70/0xd4
731 09:34:22.105727 <4>[ 4.015527] of_platform_populate from sysc_probe+0x100c/0x1418
732 09:34:22.111351 <4>[ 4.021911] sysc_probe from platform_probe+0x5c/0xb0
733 09:34:22.117196 <4>[ 4.027389] platform_probe from really_probe+0xc8/0x2c8
734 09:34:22.122776 <4>[ 4.033129] really_probe from __driver_probe_device+0x88/0x19c
735 09:34:22.134438 <4>[ 4.039494] __driver_probe_device from driver_probe_device+0x30/0x104
736 09:34:22.140002 <4>[ 4.046484] driver_probe_device from __device_attach_driver+0x94/0x108
737 09:34:22.145724 <4>[ 4.053565] __device_attach_driver from bus_for_each_drv+0x90/0xe4
738 09:34:22.151474 <4>[ 4.060285] bus_for_each_drv from __device_attach+0xa8/0x1a4
739 09:34:22.157227 <4>[ 4.066470] __device_attach from bus_probe_device+0x88/0x8c
740 09:34:22.162992 <4>[ 4.072566] bus_probe_device from device_add+0x5a8/0x77c
741 09:34:22.168724 <4>[ 4.078392] device_add from of_platform_device_create_pdata+0x90/0xbc
742 09:34:22.180163 <4>[ 4.085385] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
743 09:34:22.185956 <4>[ 4.093634] of_platform_bus_create from of_platform_populate+0x70/0xd4
744 09:34:22.191661 <4>[ 4.100719] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
745 09:34:22.197568 <4>[ 4.107536] simple_pm_bus_probe from platform_probe+0x5c/0xb0
746 09:34:22.203451 <4>[ 4.113816] platform_probe from really_probe+0xc8/0x2c8
747 09:34:22.208924 <4>[ 4.119557] really_probe from __driver_probe_device+0x88/0x19c
748 09:34:22.220424 <4>[ 4.125922] __driver_probe_device from driver_probe_device+0x30/0x104
749 09:34:22.226036 <4>[ 4.132913] driver_probe_device from __device_attach_driver+0x94/0x108
750 09:34:22.231827 <4>[ 4.139995] __device_attach_driver from bus_for_each_drv+0x90/0xe4
751 09:34:22.237560 <4>[ 4.146717] bus_for_each_drv from __device_attach+0xa8/0x1a4
752 09:34:22.243542 <4>[ 4.152902] __device_attach from bus_probe_device+0x88/0x8c
753 09:34:22.249077 <4>[ 4.158997] bus_probe_device from device_add+0x5a8/0x77c
754 09:34:22.254891 <4>[ 4.164823] device_add from of_platform_device_create_pdata+0x90/0xbc
755 09:34:22.266251 <4>[ 4.171818] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
756 09:34:22.272082 <4>[ 4.180065] of_platform_bus_create from of_platform_populate+0x70/0xd4
757 09:34:22.277763 <4>[ 4.187152] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
758 09:34:22.283436 <4>[ 4.193970] simple_pm_bus_probe from platform_probe+0x5c/0xb0
759 09:34:22.289200 <4>[ 4.200249] platform_probe from really_probe+0xc8/0x2c8
760 09:34:22.300690 <4>[ 4.205990] really_probe from __driver_probe_device+0x88/0x19c
761 09:34:22.306423 <4>[ 4.212352] __driver_probe_device from driver_probe_device+0x30/0x104
762 09:34:22.312169 <4>[ 4.219343] driver_probe_device from __device_attach_driver+0x94/0x108
763 09:34:22.317880 <4>[ 4.226421] __device_attach_driver from bus_for_each_drv+0x90/0xe4
764 09:34:22.323724 <4>[ 4.233142] bus_for_each_drv from __device_attach+0xa8/0x1a4
765 09:34:22.329437 <4>[ 4.239328] __device_attach from bus_probe_device+0x88/0x8c
766 09:34:22.335227 <4>[ 4.245425] bus_probe_device from device_add+0x5a8/0x77c
767 09:34:22.346586 <4>[ 4.251252] device_add from of_platform_device_create_pdata+0x90/0xbc
768 09:34:22.352484 <4>[ 4.258244] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
769 09:34:22.358092 <4>[ 4.266493] of_platform_bus_create from of_platform_populate+0x70/0xd4
770 09:34:22.363913 <4>[ 4.273580] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
771 09:34:22.369605 <4>[ 4.280396] simple_pm_bus_probe from platform_probe+0x5c/0xb0
772 09:34:22.375312 <4>[ 4.286676] platform_probe from really_probe+0xc8/0x2c8
773 09:34:22.386690 <4>[ 4.292414] really_probe from __driver_probe_device+0x88/0x19c
774 09:34:22.392481 <4>[ 4.298778] __driver_probe_device from driver_probe_device+0x30/0x104
775 09:34:22.398261 <4>[ 4.305769] driver_probe_device from __device_attach_driver+0x94/0x108
776 09:34:22.404031 <4>[ 4.312849] __device_attach_driver from bus_for_each_drv+0x90/0xe4
777 09:34:22.409741 <4>[ 4.319571] bus_for_each_drv from __device_attach+0xa8/0x1a4
778 09:34:22.415520 <4>[ 4.325753] __device_attach from bus_probe_device+0x88/0x8c
779 09:34:22.426967 <4>[ 4.331847] bus_probe_device from deferred_probe_work_func+0x78/0xa4
780 09:34:22.432710 <4>[ 4.338748] deferred_probe_work_func from process_one_work+0x178/0x3c0
781 09:34:22.438531 <4>[ 4.345844] process_one_work from worker_thread+0x264/0x42c
782 09:34:22.444332 <4>[ 4.351949] worker_thread from kthread+0xe0/0xfc
783 09:34:22.450209 <4>[ 4.357076] kthread from ret_from_fork+0x14/0x28
784 09:34:22.455702 <4>[ 4.362195] Exception stack(0xe0131fb0 to 0xe0131ff8)
785 09:34:22.461504 <4>[ 4.367661] 1fa0: 00000000 00000000 00000000 00000000
786 09:34:22.472800 <4>[ 4.376342] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
787 09:34:22.478642 <4>[ 4.385019] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
788 09:34:22.484477 <4>[ 4.392219] ---[ end trace 0000000000000000 ]---
789 09:34:22.485128 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
790 09:34:22.485368 login-action: kernel 'warning'
791 09:34:22.485579 [login-action] Waiting for messages, (timeout 00:03:52)
792 09:34:22.485762 Waiting using forced prompt support (timeout 00:01:56)
793 09:34:22.490238 <6>[ 4.397315] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
794 09:34:22.496497 <6>[ 4.404606] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
795 09:34:22.508089 <6>[ 4.412294] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
796 09:34:22.519689 <6>[ 4.420447] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
797 09:34:22.527082 <6>[ 4.432082] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
798 09:34:22.537705 <5>[ 4.441202] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
799 09:34:22.565054 <3>[ 4.470853] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
800 09:34:22.570775 <6>[ 4.479317] edma 49000000.dma: TI EDMA DMA engine driver
801 09:34:22.641641 <3>[ 4.546634] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
802 09:34:22.655818 <6>[ 4.561004] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
803 09:34:22.674404 <3>[ 4.583402] l3-aon-clkctrl:0000:0: failed to disable
804 09:34:22.725667 <6>[ 4.631233] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
805 09:34:22.731224 <6>[ 4.640695] printk: legacy console [ttyS0] enabled
806 09:34:22.737012 <6>[ 4.640695] printk: legacy console [ttyS0] enabled
807 09:34:22.742656 <6>[ 4.651018] printk: legacy bootconsole [omap8250] disabled
808 09:34:22.747866 <6>[ 4.651018] printk: legacy bootconsole [omap8250] disabled
809 09:34:22.776295 <4>[ 4.680887] tps65217-pmic: Failed to locate of_node [id: -1]
810 09:34:22.778920 <4>[ 4.688257] tps65217-bl: Failed to locate of_node [id: -1]
811 09:34:22.796063 <6>[ 4.707625] tps65217 0-0024: TPS65217 ID 0xe version 1.2
812 09:34:22.816660 <6>[ 4.714594] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
813 09:34:22.828210 <6>[ 4.728295] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
814 09:34:22.831432 <6>[ 4.740182] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
815 09:34:22.854398 <6>[ 4.760361] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
816 09:34:22.860382 <6>[ 4.769414] sdhci-omap 48060000.mmc: Got CD GPIO
817 09:34:22.868169 <4>[ 4.774586] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
818 09:34:22.883062 <4>[ 4.787944] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
819 09:34:22.889680 <4>[ 4.796845] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
820 09:34:22.898687 <4>[ 4.805681] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
821 09:34:22.943670 <6>[ 4.850812] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
822 09:34:22.991663 <6>[ 4.896934] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
823 09:34:22.998175 <6>[ 4.905591] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
824 09:34:23.007125 <6>[ 4.914572] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
825 09:34:23.056291 <6>[ 4.959356] mmc0: new high speed SDHC card at address 0001
826 09:34:23.056657 <6>[ 4.966682] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
827 09:34:23.063515 <6>[ 4.975005] mmcblk0: p1
828 09:34:23.086333 <6>[ 4.989159] mmc1: new high speed MMC card at address 0001
829 09:34:23.086649 <6>[ 4.996177] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
830 09:34:23.098216 <6>[ 5.003883] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
831 09:34:23.104425 <6>[ 5.015074] mmcblk1:
832 09:34:23.107180 <6>[ 5.018290] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
833 09:34:23.122626 <6>[ 5.032356] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
834 09:34:23.130670 <6>[ 5.039490] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
835 09:34:25.255052 <6>[ 7.161116] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
836 09:34:32.598606 <5>[ 7.200116] Sending DHCP requests ..., OK
837 09:34:32.610247 <6>[ 14.514697] IP-Config: Got DHCP answer from 192.168.56.254, my address is 192.168.56.9
838 09:34:32.610489 <6>[ 14.523104] IP-Config: Complete:
839 09:34:32.624036 <6>[ 14.526642] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.56.9, mask=255.255.255.0, gw=192.168.56.254
840 09:34:32.629710 <6>[ 14.537410] host=192.168.56.9, domain=mayfield.sirena.org.uk, nis-domain=(none)
841 09:34:32.641485 <6>[ 14.545539] bootserver=192.168.56.254, rootserver=192.168.56.76, rootpath=
842 09:34:32.641790 <6>[ 14.545575] nameserver0=192.168.56.254
843 09:34:32.653851 <6>[ 14.557750] ntpserver0=50.205.244.22, ntpserver1=85.199.214.99
844 09:34:32.654207 <6>[ 14.565389] clk: Disabling unused clocks
845 09:34:32.661154 <6>[ 14.569997] PM: genpd: Disabling unused power domains
846 09:34:32.680218 <6>[ 14.589292] Freeing unused kernel image (initmem) memory: 2048K
847 09:34:32.688412 <6>[ 14.598947] Run /init as init process
848 09:34:32.709929 Loading, please wait...
849 09:34:32.785637 Starting systemd-udevd version 252.22-1~deb12u1
850 09:34:35.795808 <4>[ 17.700928] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
851 09:34:35.977635 <4>[ 17.882525] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
852 09:34:36.173144 <6>[ 18.084940] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
853 09:34:36.183157 <6>[ 18.090761] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
854 09:34:36.347966 <6>[ 18.259090] hub 1-0:1.0: USB hub found
855 09:34:36.389459 <6>[ 18.300369] hub 1-0:1.0: 1 port detected
856 09:34:36.643610 <6>[ 18.554551] tda998x 0-0070: found TDA19988
857 09:34:39.312192 Begin: Loading essential drivers ... done.
858 09:34:39.317464 Begin: Running /scripts/init-premount ... done.
859 09:34:39.323630 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
860 09:34:39.332776 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
861 09:34:39.339802 Device /sys/class/net/eth0 found
862 09:34:39.340105 done.
863 09:34:39.399690 Begin: Waiting up to 180 secs for any network device to become available ... done.
864 09:34:39.480917 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
865 09:34:39.580440 IP-Config: eth0 complete (dhcp from 192.168.56.254):
866 09:34:39.592206 address: 192.168.56.9 broadcast: 192.168.56.255 netmask: 255.255.255.0
867 09:34:39.595293 gateway: 192.168.56.254 dns0 : 192.168.56.254 dns1 : 0.0.0.0
868 09:34:39.600843 domain : mayfield.sirena.org.uk
869 09:34:39.609006 rootserver: 192.168.56.254 rootpath:
870 09:34:39.609391 filename :
871 09:34:39.704578 done.
872 09:34:39.714276 Begin: Running /scripts/nfs-bottom ... done.
873 09:34:39.781950 Begin: Running /scripts/init-bottom ... done.
874 09:34:40.928991 <30>[ 22.837456] systemd[1]: System time before build time, advancing clock.
875 09:34:41.075876 <30>[ 22.957075] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
876 09:34:41.144900 <30>[ 23.054340] systemd[1]: Detected architecture arm.
877 09:34:41.158830
878 09:34:41.159141 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
879 09:34:41.159311
880 09:34:41.181663 <30>[ 23.089925] systemd[1]: Hostname set to <debian-bookworm-armhf>.
881 09:34:43.457046 <30>[ 25.363774] systemd[1]: Queued start job for default target graphical.target.
882 09:34:43.473428 <30>[ 25.378286] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
883 09:34:43.480251 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
884 09:34:43.511449 <30>[ 25.416105] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
885 09:34:43.519309 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
886 09:34:43.548930 <30>[ 25.453129] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
887 09:34:43.556487 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
888 09:34:43.589395 <30>[ 25.493867] systemd[1]: Created slice user.slice - User and Session Slice.
889 09:34:43.596026 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
890 09:34:43.621667 <30>[ 25.521347] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
891 09:34:43.627669 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
892 09:34:43.645537 <30>[ 25.551187] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
893 09:34:43.654762 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
894 09:34:43.686752 <30>[ 25.581247] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
895 09:34:43.693101 <30>[ 25.601674] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
896 09:34:43.701392 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
897 09:34:43.724878 <30>[ 25.630608] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
898 09:34:43.732673 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
899 09:34:43.755717 <30>[ 25.661066] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
900 09:34:43.763861 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
901 09:34:43.785466 <30>[ 25.691098] systemd[1]: Reached target paths.target - Path Units.
902 09:34:43.790552 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
903 09:34:43.814647 <30>[ 25.720712] systemd[1]: Reached target remote-fs.target - Remote File Systems.
904 09:34:43.822390 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
905 09:34:43.845140 <30>[ 25.750767] systemd[1]: Reached target slices.target - Slice Units.
906 09:34:43.850647 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
907 09:34:43.875200 <30>[ 25.780906] systemd[1]: Reached target swap.target - Swaps.
908 09:34:43.879359 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
909 09:34:43.905112 <30>[ 25.810840] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
910 09:34:43.913508 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
911 09:34:43.936103 <30>[ 25.841640] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
912 09:34:43.944593 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
913 09:34:44.032943 <30>[ 25.934373] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
914 09:34:44.046359 <30>[ 25.952194] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
915 09:34:44.054833 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
916 09:34:44.078266 <30>[ 25.982881] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
917 09:34:44.085626 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
918 09:34:44.108080 <30>[ 26.013480] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
919 09:34:44.116142 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
920 09:34:44.141398 <30>[ 26.045817] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
921 09:34:44.146980 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
922 09:34:44.177796 <30>[ 26.081896] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
923 09:34:44.185211 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
924 09:34:44.212113 <30>[ 26.111934] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
925 09:34:44.231320 <30>[ 26.130709] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
926 09:34:44.284412 <30>[ 26.190946] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
927 09:34:44.308541 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
928 09:34:44.367186 <30>[ 26.273663] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
929 09:34:44.389050 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
930 09:34:44.466307 <30>[ 26.371501] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
931 09:34:44.476923 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
932 09:34:44.545762 <30>[ 26.451618] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
933 09:34:44.564050 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
934 09:34:44.600469 <30>[ 26.506721] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
935 09:34:44.632993 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
936 09:34:44.685450 <30>[ 26.592868] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
937 09:34:44.711521 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
938 09:34:44.766769 <30>[ 26.672529] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
939 09:34:44.779728 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
940 09:34:44.814883 <30>[ 26.722235] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
941 09:34:44.846008 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
942 09:34:44.895038 <30>[ 26.801452] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
943 09:34:44.912625 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
944 09:34:44.944927 <28>[ 26.844512] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
945 09:34:44.952645 <28>[ 26.859091] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
946 09:34:44.995623 <30>[ 26.903448] systemd[1]: Starting systemd-journald.service - Journal Service...
947 09:34:45.013014 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
948 09:34:45.085739 <30>[ 26.992335] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
949 09:34:45.102366 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
950 09:34:45.146804 <30>[ 27.053249] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
951 09:34:45.206453 Starting [0;1;39msystemd-network-g… units from Kernel command line...
952 09:34:45.281478 <30>[ 27.186772] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
953 09:34:45.333064 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
954 09:34:45.392523 <30>[ 27.299171] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
955 09:34:45.444519 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
956 09:34:45.490545 <30>[ 27.398156] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
957 09:34:45.545229 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
958 09:34:45.564959 <30>[ 27.472359] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
959 09:34:45.602346 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
960 09:34:45.625220 <30>[ 27.530662] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
961 09:34:45.651908 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
962 09:34:45.806716 <30>[ 27.714415] systemd[1]: modprobe@configfs.service: Deactivated successfully.
963 09:34:45.845096 <30>[ 27.751922] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
964 09:34:45.874235 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
965 09:34:45.894871 <30>[ 27.802970] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
966 09:34:45.931364 <30>[ 27.838610] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
967 09:34:45.945001 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
968 09:34:45.966038 <30>[ 27.871820] systemd[1]: Started systemd-journald.service - Journal Service.
969 09:34:45.972635 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
970 09:34:46.014379 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
971 09:34:46.047305 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
972 09:34:46.068790 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
973 09:34:46.089543 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
974 09:34:46.124326 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
975 09:34:46.148213 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
976 09:34:46.176852 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
977 09:34:46.204199 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
978 09:34:46.264586 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
979 09:34:46.307837 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
980 09:34:46.375437 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
981 09:34:46.471247 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
982 09:34:46.544484 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
983 09:34:46.683600 <46>[ 28.591149] systemd-journald[164]: Received client request to flush runtime journal.
984 09:34:46.695146 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
985 09:34:46.800601 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
986 09:34:47.505999 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
987 09:34:48.046947 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
988 09:34:48.107177 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
989 09:34:48.520945 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
990 09:34:48.686762 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
991 09:34:48.714729 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
992 09:34:48.733651 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
993 09:34:48.784653 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
994 09:34:48.838878 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
995 09:34:49.721946 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
996 09:34:49.787879 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
997 09:34:50.185983 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
998 09:34:50.317201 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
999 09:34:50.417723 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1000 09:34:52.141487 <5>[ 34.049125] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1001 09:34:52.319466 [[0m[0;31m* [0m] (1 of 5) Job systemd-networkd.service/start running (8s / 1min 36s)
1002 09:34:52.500752 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1003 09:34:52.739514 [K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1004 09:34:53.586168 <5>[ 35.495065] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1005 09:34:53.680582 <5>[ 35.587963] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1006 09:34:53.713106 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m -<4>[ 35.617401] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1007 09:34:53.713493 /dev/ttyS0.
1008 09:34:53.720155 <6>[ 35.628943] cfg80211: failed to load regulatory.db
1009 09:34:55.153872 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1010 09:34:55.189622 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1011 09:35:02.791230 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1012 09:35:02.815080 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1013 09:35:02.839209 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1014 09:35:02.871723 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1015 09:35:02.951022 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1016 09:35:02.990592 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1017 09:35:03.056595 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1018 09:35:03.103614 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1019 09:35:03.154554 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1020 09:35:03.179194 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1021 09:35:03.211141 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1022 09:35:03.251617 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1023 09:35:03.288958 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1024 09:35:03.352034 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1025 09:35:03.392009 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1026 09:35:03.414595 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1027 09:35:03.446713 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1028 09:35:03.476878 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1029 09:35:03.509482 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1030 09:35:03.533844 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1031 09:35:03.560710 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1032 09:35:03.583772 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1033 09:35:03.609669 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1034 09:35:03.721432 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1035 09:35:03.783440 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1036 09:35:03.894250 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1037 09:35:03.987793 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1038 09:35:04.041844 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1039 09:35:04.085639 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1040 09:35:04.108426 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1041 09:35:04.305448 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1042 09:35:04.365337 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1043 09:35:04.437570 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1044 09:35:04.466749 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1045 09:35:04.511779 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1046 09:35:04.683896 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
1047 09:35:04.784842 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1048 09:35:05.232510 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
1049 09:35:05.278821 <46>[ 47.175808] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1050 09:35:05.327015 <46>[ 47.227272] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
1051 09:35:05.356808 Starting [0;1;39mdpkg-db-backup.se…ly dpkg database backup service...
1052 09:35:05.434685 Starting [0;1;39me2scrub_all.servi…adata Check for All Filesystems...
1053 09:35:07.468073 [[0;32m OK [0m] Finished [0;1;39me2scrub_all.servi…etadata Check for All Filesystems.
1054 09:35:08.443958 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1055 09:35:08.487452 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1056 09:35:08.516365 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1057 09:35:08.651190 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1058 09:35:08.930438 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1059 09:35:09.509326
1060 09:35:09.509643 Dworm-armhf login: root (automatic login)
1061 09:35:09.509825
1062 09:35:09.986689 Linux debian-bookworm-armhf 6.11.0 #1 SMP Thu Sep 19 08:53:27 UTC 2024 armv7l
1063 09:35:09.987005
1064 09:35:09.992445 The programs included with the Debian GNU/Linux system are free software;
1065 09:35:09.997657 the exact distribution terms for each program are described in the
1066 09:35:10.003247 individual files in /usr/share/doc/*/copyright.
1067 09:35:10.003521
1068 09:35:10.011074 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1069 09:35:10.011330 permitted by applicable law.
1070 09:35:14.627092 Matched prompt #10: / #
1072 09:35:14.628013 Kernel warnings or errors detected.
1073 09:35:14.628148 Setting prompt string to ['/ #']
1074 09:35:14.628325 end: 2.4.4.1 login-action (duration 00:00:57) [common]
1076 09:35:14.629106 end: 2.4.4 auto-login-action (duration 00:00:58) [common]
1077 09:35:14.629286 start: 2.4.5 expect-shell-connection (timeout 00:03:00) [common]
1078 09:35:14.629427 Setting prompt string to ['/ #']
1079 09:35:14.629555 Forcing a shell prompt, looking for ['/ #']
1081 09:35:14.679942 / #
1082 09:35:14.680390 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1083 09:35:14.680583 Waiting using forced prompt support (timeout 00:02:30)
1084 09:35:14.684739
1085 09:35:14.690519 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1086 09:35:14.690808 start: 2.4.6 export-device-env (timeout 00:03:00) [common]
1087 09:35:14.690975 Sending with 10 millisecond of delay
1089 09:35:19.680857 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/743617/extract-nfsrootfs-k28ofhyi'
1090 09:35:19.691371 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/743617/extract-nfsrootfs-k28ofhyi'
1091 09:35:19.691938 Sending with 10 millisecond of delay
1093 09:35:21.909952 / # export NFS_SERVER_IP='192.168.56.76'
1094 09:35:21.920370 export NFS_SERVER_IP='192.168.56.76'
1095 09:35:21.920897 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1096 09:35:21.921111 end: 2.4 uboot-commands (duration 00:02:07) [common]
1097 09:35:21.921311 end: 2 uboot-action (duration 00:02:07) [common]
1098 09:35:21.921495 start: 3 lava-test-retry (timeout 00:07:23) [common]
1099 09:35:21.921678 start: 3.1 lava-test-shell (timeout 00:07:23) [common]
1100 09:35:21.921828 Using namespace: common
1102 09:35:22.022301 / # #
1103 09:35:22.022670 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1104 09:35:22.026257 #
1105 09:35:22.032888 Using /lava-743617
1107 09:35:22.133436 / # export SHELL=/bin/bash
1108 09:35:22.137413 export SHELL=/bin/bash
1110 09:35:22.244470 / # . /lava-743617/environment
1111 09:35:22.249708 . /lava-743617/environment
1113 09:35:22.361675 / # /lava-743617/bin/lava-test-runner /lava-743617/0
1114 09:35:22.361975 Test shell timeout: 10s (minimum of the action and connection timeout)
1115 09:35:22.366800 /lava-743617/bin/lava-test-runner /lava-743617/0
1116 09:35:22.765233 + export TESTRUN_ID=0_timesync-off
1117 09:35:22.773213 + TESTRUN_ID=0_timesync-off
1118 09:35:22.773517 + cd /lava-743617/0/tests/0_timesync-off
1119 09:35:22.773686 ++ cat uuid
1120 09:35:22.796064 + UUID=743617_1.6.2.4.1
1121 09:35:22.796368 + set +x
1122 09:35:22.804933 <LAVA_SIGNAL_STARTRUN 0_timesync-off 743617_1.6.2.4.1>
1123 09:35:22.805243 + systemctl stop systemd-timesyncd
1124 09:35:22.805651 Received signal: <STARTRUN> 0_timesync-off 743617_1.6.2.4.1
1125 09:35:22.805811 Starting test lava.0_timesync-off (743617_1.6.2.4.1)
1126 09:35:22.806019 Skipping test definition patterns.
1127 09:35:23.128864 + set +x
1128 09:35:23.129107 <LAVA_SIGNAL_ENDRUN 0_timesync-off 743617_1.6.2.4.1>
1129 09:35:23.129490 Received signal: <ENDRUN> 0_timesync-off 743617_1.6.2.4.1
1130 09:35:23.129669 Ending use of test pattern.
1131 09:35:23.129812 Ending test lava.0_timesync-off (743617_1.6.2.4.1), duration 0.32
1133 09:35:23.279572 + export TESTRUN_ID=1_kselftest-dt
1134 09:35:23.287461 + TESTRUN_ID=1_kselftest-dt
1135 09:35:23.287686 + cd /lava-743617/0/tests/1_kselftest-dt
1136 09:35:23.287857 ++ cat uuid
1137 09:35:23.301897 + UUID=743617_1.6.2.4.5
1138 09:35:23.302079 + set +x
1139 09:35:23.307461 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 743617_1.6.2.4.5>
1140 09:35:23.307666 + cd ./automated/linux/kselftest/
1141 09:35:23.308041 Received signal: <STARTRUN> 1_kselftest-dt 743617_1.6.2.4.5
1142 09:35:23.308188 Starting test lava.1_kselftest-dt (743617_1.6.2.4.5)
1143 09:35:23.308385 Skipping test definition patterns.
1144 09:35:23.335765 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1145 09:35:23.427758 INFO: install_deps skipped
1146 09:35:23.985628 --2024-09-19 09:35:23-- http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1147 09:35:24.010151 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1148 09:35:24.158029 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1149 09:35:24.305160 HTTP request sent, awaiting response... 200 OK
1150 09:35:24.305413 Length: 4076804 (3.9M) [application/octet-stream]
1151 09:35:24.310711 Saving to: 'kselftest_armhf.tar.gz'
1152 09:35:24.310889
1153 09:35:26.070669
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kselftest_armhf.tar 28%[====> ] 1.10M 930KB/s
kselftest_armhf.tar 77%[==============> ] 3.00M 1.95MB/s
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kselftest_armhf.tar 100%[===================>] 3.89M 2.22MB/s in 1.8s
1154 09:35:26.070910
1155 09:35:26.776451 2024-09-19 09:35:26 (2.22 MB/s) - 'kselftest_armhf.tar.gz' saved [4076804/4076804]
1156 09:35:26.776711
1157 09:35:48.875510 skiplist:
1158 09:35:48.875832 ========================================
1159 09:35:48.880086 ========================================
1160 09:35:48.988613 dt:test_unprobed_devices.sh
1161 09:35:49.038504 ============== Tests to run ===============
1162 09:35:49.048117 dt:test_unprobed_devices.sh
1163 09:35:49.051973 ===========End Tests to run ===============
1164 09:35:49.062277 shardfile-dt pass
1165 09:35:49.310484 <12>[ 91.223597] kselftest: Running tests in dt
1166 09:35:49.340997 TAP version 13
1167 09:35:49.367458 1..1
1168 09:35:49.423864 # timeout set to 45
1169 09:35:49.424174 # selftests: dt: test_unprobed_devices.sh
1170 09:35:50.182791 # TAP version 13
1171 09:36:15.963358 # 1..257
1172 09:36:16.185726 # ok 1 / # SKIP
1173 09:36:16.205745 # ok 2 /clk_mcasp0
1174 09:36:16.274425 # ok 3 /clk_mcasp0_fixed # SKIP
1175 09:36:16.340369 # ok 4 /cpus/cpu@0 # SKIP
1176 09:36:16.410637 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1177 09:36:16.429583 # ok 6 /fixedregulator0
1178 09:36:16.453088 # ok 7 /leds
1179 09:36:16.468712 # ok 8 /ocp
1180 09:36:16.492009 # ok 9 /ocp/interconnect@44c00000
1181 09:36:16.521174 # ok 10 /ocp/interconnect@44c00000/segment@0
1182 09:36:16.543204 # ok 11 /ocp/interconnect@44c00000/segment@100000
1183 09:36:16.566570 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1184 09:36:16.637484 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1185 09:36:16.656416 # ok 14 /ocp/interconnect@44c00000/segment@200000
1186 09:36:16.673070 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1187 09:36:16.772972 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1188 09:36:16.847126 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1189 09:36:16.917871 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1190 09:36:16.984188 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1191 09:36:17.054269 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1192 09:36:17.122687 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1193 09:36:17.193073 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1194 09:36:17.258492 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1195 09:36:17.327562 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1196 09:36:17.398037 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1197 09:36:17.463408 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1198 09:36:17.531060 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1199 09:36:17.610687 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1200 09:36:17.682583 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1201 09:36:17.753271 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1202 09:36:17.840372 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1203 09:36:17.920895 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1204 09:36:17.991186 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1205 09:36:18.073441 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1206 09:36:18.152503 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1207 09:36:18.230717 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1208 09:36:18.312908 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1209 09:36:18.389956 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1210 09:36:18.470227 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1211 09:36:18.549446 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1212 09:36:18.629283 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1213 09:36:18.704713 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1214 09:36:18.792409 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1215 09:36:18.866855 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1216 09:36:18.956109 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1217 09:36:19.025346 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1218 09:36:19.113518 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1219 09:36:19.192153 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1220 09:36:19.264986 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1221 09:36:19.345348 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1222 09:36:19.416851 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1223 09:36:19.505853 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1224 09:36:19.581332 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1225 09:36:19.654447 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1226 09:36:19.740199 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1227 09:36:19.819836 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1228 09:36:19.897806 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1229 09:36:19.974694 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1230 09:36:20.048767 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1231 09:36:20.132284 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1232 09:36:20.203552 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1233 09:36:20.282626 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1234 09:36:20.370368 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1235 09:36:20.454977 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1236 09:36:20.526617 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1237 09:36:20.613252 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1238 09:36:20.684571 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1239 09:36:20.771622 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1240 09:36:20.850802 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1241 09:36:20.936706 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1242 09:36:21.007002 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1243 09:36:21.090612 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1244 09:36:21.163008 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1245 09:36:21.254160 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1246 09:36:21.333866 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1247 09:36:21.416139 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1248 09:36:21.494444 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1249 09:36:21.581464 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1250 09:36:21.653594 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1251 09:36:21.729495 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1252 09:36:21.821585 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1253 09:36:21.891420 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1254 09:36:21.971725 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1255 09:36:22.054179 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1256 09:36:22.123590 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1257 09:36:22.201274 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1258 09:36:22.281268 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1259 09:36:22.357251 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1260 09:36:22.441761 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1261 09:36:22.515119 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1262 09:36:22.588579 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1263 09:36:22.660826 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1264 09:36:22.732249 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1265 09:36:22.796066 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1266 09:36:22.822473 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1267 09:36:22.840188 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1268 09:36:22.866538 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1269 09:36:22.892532 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1270 09:36:22.916649 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1271 09:36:22.941338 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1272 09:36:22.956684 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1273 09:36:22.979176 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1274 09:36:23.088886 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1275 09:36:23.112667 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1276 09:36:23.130153 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1277 09:36:23.160508 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1278 09:36:23.255730 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1279 09:36:23.335000 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1280 09:36:23.396221 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1281 09:36:23.471336 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1282 09:36:23.542542 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1283 09:36:23.604415 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1284 09:36:23.680822 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1285 09:36:23.743189 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1286 09:36:23.817954 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1287 09:36:23.887579 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1288 09:36:23.955545 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1289 09:36:24.025626 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1290 09:36:24.099439 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1291 09:36:24.164865 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1292 09:36:24.241849 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1293 09:36:24.310216 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1294 09:36:24.332968 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1295 09:36:24.401020 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1296 09:36:24.465720 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1297 09:36:24.539374 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1298 09:36:24.553309 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1299 09:36:24.631761 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1300 09:36:24.650957 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1301 09:36:24.718038 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1302 09:36:24.744593 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1303 09:36:24.767717 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1304 09:36:24.791257 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1305 09:36:24.808979 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1306 09:36:24.834397 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1307 09:36:24.857721 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1308 09:36:24.883555 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1309 09:36:24.950877 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1310 09:36:24.978841 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1311 09:36:24.995665 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1312 09:36:25.074237 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1313 09:36:25.142964 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1314 09:36:25.155841 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1315 09:36:25.261170 # not ok 144 /ocp/interconnect@47c00000
1316 09:36:25.325252 # not ok 145 /ocp/interconnect@47c00000/segment@0
1317 09:36:25.349835 # ok 146 /ocp/interconnect@48000000
1318 09:36:25.371319 # ok 147 /ocp/interconnect@48000000/segment@0
1319 09:36:25.396952 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1320 09:36:25.421025 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1321 09:36:25.438338 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1322 09:36:25.465300 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1323 09:36:25.489808 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1324 09:36:25.505538 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1325 09:36:25.533155 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1326 09:36:25.599292 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1327 09:36:25.669100 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1328 09:36:25.696865 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1329 09:36:25.713466 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1330 09:36:25.734630 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1331 09:36:25.763249 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1332 09:36:25.785463 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1333 09:36:25.811189 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1334 09:36:25.830311 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1335 09:36:25.852196 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1336 09:36:25.877642 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1337 09:36:25.903911 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1338 09:36:25.925828 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1339 09:36:25.948424 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1340 09:36:25.968701 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1341 09:36:25.997847 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1342 09:36:26.013440 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1343 09:36:26.040358 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1344 09:36:26.060391 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1345 09:36:26.089436 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1346 09:36:26.103607 # ok 175 /ocp/interconnect@48000000/segment@100000
1347 09:36:26.131411 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1348 09:36:26.151790 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1349 09:36:26.230700 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1350 09:36:26.301868 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1351 09:36:26.369960 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1352 09:36:26.434462 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1353 09:36:26.502167 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1354 09:36:26.581776 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1355 09:36:26.643546 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1356 09:36:26.721910 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1357 09:36:26.741039 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1358 09:36:26.755459 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1359 09:36:26.785364 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1360 09:36:26.809900 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1361 09:36:26.827941 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1362 09:36:26.849740 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1363 09:36:26.878008 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1364 09:36:26.905473 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1365 09:36:26.931316 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1366 09:36:26.953913 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1367 09:36:26.977528 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1368 09:36:27.000563 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1369 09:36:27.016295 # ok 198 /ocp/interconnect@48000000/segment@200000
1370 09:36:27.039404 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1371 09:36:27.113829 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1372 09:36:27.128836 # ok 201 /ocp/interconnect@48000000/segment@300000
1373 09:36:27.157261 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1374 09:36:27.181510 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1375 09:36:27.198667 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1376 09:36:27.225622 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1377 09:36:27.248139 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1378 09:36:27.264597 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1379 09:36:27.335217 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1380 09:36:27.355714 # ok 209 /ocp/interconnect@4a000000
1381 09:36:27.375749 # ok 210 /ocp/interconnect@4a000000/segment@0
1382 09:36:27.402250 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1383 09:36:27.431889 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1384 09:36:27.451151 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1385 09:36:27.471209 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1386 09:36:27.544952 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1387 09:36:27.660132 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1388 09:36:27.722366 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1389 09:36:27.830103 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1390 09:36:27.889720 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1391 09:36:27.960293 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1392 09:36:28.058397 # not ok 221 /ocp/interconnect@4b140000
1393 09:36:28.125545 # not ok 222 /ocp/interconnect@4b140000/segment@0
1394 09:36:28.197960 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1395 09:36:28.214503 # ok 224 /ocp/target-module@40300000
1396 09:36:28.237421 # ok 225 /ocp/target-module@40300000/sram@0
1397 09:36:28.313526 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1398 09:36:28.383217 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1399 09:36:28.402409 # ok 228 /ocp/target-module@47400000
1400 09:36:28.425234 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1401 09:36:28.449546 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1402 09:36:28.463966 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1403 09:36:28.491186 # ok 232 /ocp/target-module@47400000/usb@1400
1404 09:36:28.512770 # ok 233 /ocp/target-module@47400000/usb@1800
1405 09:36:28.533945 # ok 234 /ocp/target-module@47810000
1406 09:36:28.555593 # ok 235 /ocp/target-module@49000000
1407 09:36:28.572319 # ok 236 /ocp/target-module@49000000/dma@0
1408 09:36:28.596110 # ok 237 /ocp/target-module@49800000
1409 09:36:28.617100 # ok 238 /ocp/target-module@49800000/dma@0
1410 09:36:28.642143 # ok 239 /ocp/target-module@49900000
1411 09:36:28.665247 # ok 240 /ocp/target-module@49900000/dma@0
1412 09:36:28.686108 # ok 241 /ocp/target-module@49a00000
1413 09:36:28.705053 # ok 242 /ocp/target-module@49a00000/dma@0
1414 09:36:28.730208 # ok 243 /ocp/target-module@4c000000
1415 09:36:28.795013 # not ok 244 /ocp/target-module@4c000000/emif@0
1416 09:36:28.819841 # ok 245 /ocp/target-module@50000000
1417 09:36:28.842161 # ok 246 /ocp/target-module@53100000
1418 09:36:28.906947 # not ok 247 /ocp/target-module@53100000/sham@0
1419 09:36:28.933171 # ok 248 /ocp/target-module@53500000
1420 09:36:29.000861 # not ok 249 /ocp/target-module@53500000/aes@0
1421 09:36:29.024309 # ok 250 /ocp/target-module@56000000
1422 09:36:29.118235 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1423 09:36:29.188981 # ok 252 /opp-table # SKIP
1424 09:36:29.253278 # ok 253 /soc # SKIP
1425 09:36:29.271786 # ok 254 /sound
1426 09:36:29.295271 # ok 255 /target-module@4b000000
1427 09:36:29.319069 # ok 256 /target-module@4b000000/target-module@140000
1428 09:36:29.341902 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1429 09:36:29.347779 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1430 09:36:29.354495 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1431 09:36:31.444614 dt_test_unprobed_devices_sh_ skip
1432 09:36:31.450015 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1433 09:36:31.455717 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1434 09:36:31.455969 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1435 09:36:31.461460 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1436 09:36:31.466835 dt_test_unprobed_devices_sh_fixedregulator0 pass
1437 09:36:31.472496 dt_test_unprobed_devices_sh_leds pass
1438 09:36:31.472745 dt_test_unprobed_devices_sh_ocp pass
1439 09:36:31.478147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1440 09:36:31.483715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1441 09:36:31.489486 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1442 09:36:31.500538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1443 09:36:31.506190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1444 09:36:31.511773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1445 09:36:31.522856 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1446 09:36:31.528522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1447 09:36:31.539942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1448 09:36:31.550893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1449 09:36:31.562063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1450 09:36:31.567829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1451 09:36:31.579063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1452 09:36:31.590200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1453 09:36:31.601347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1454 09:36:31.612600 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1455 09:36:31.618188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1456 09:36:31.629331 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1457 09:36:31.640506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1458 09:36:31.651926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1459 09:36:31.662956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1460 09:36:31.668542 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1461 09:36:31.679869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1462 09:36:31.691016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1463 09:36:31.702246 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1464 09:36:31.707792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1465 09:36:31.719042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1466 09:36:31.730213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1467 09:36:31.741357 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1468 09:36:31.752474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1469 09:36:31.758184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1470 09:36:31.769367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1471 09:36:31.780400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1472 09:36:31.791758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1473 09:36:31.802913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1474 09:36:31.813955 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1475 09:36:31.825329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1476 09:36:31.836364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1477 09:36:31.847701 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1478 09:36:31.858732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1479 09:36:31.870063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1480 09:36:31.881204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1481 09:36:31.893402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1482 09:36:31.903749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1483 09:36:31.914898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1484 09:36:31.926136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1485 09:36:31.937459 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1486 09:36:31.948374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1487 09:36:31.959676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1488 09:36:31.970885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1489 09:36:31.982096 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1490 09:36:31.993133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1491 09:36:32.004471 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1492 09:36:32.015680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1493 09:36:32.026830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1494 09:36:32.038056 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1495 09:36:32.043669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1496 09:36:32.054858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1497 09:36:32.066030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1498 09:36:32.077048 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1499 09:36:32.088212 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1500 09:36:32.099412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1501 09:36:32.110767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1502 09:36:32.121777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1503 09:36:32.132993 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1504 09:36:32.144218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1505 09:36:32.155549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1506 09:36:32.166908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1507 09:36:32.177956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1508 09:36:32.189066 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1509 09:36:32.200179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1510 09:36:32.211567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1511 09:36:32.222738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1512 09:36:32.234051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1513 09:36:32.239576 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1514 09:36:32.250694 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1515 09:36:32.261820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1516 09:36:32.273129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1517 09:36:32.284259 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1518 09:36:32.290005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1519 09:36:32.306766 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1520 09:36:32.317847 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1521 09:36:32.323458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1522 09:36:32.340416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1523 09:36:32.351716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1524 09:36:32.362908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1525 09:36:32.368436 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1526 09:36:32.379552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1527 09:36:32.390837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1528 09:36:32.396415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1529 09:36:32.407729 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1530 09:36:32.419032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1531 09:36:32.424523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1532 09:36:32.435740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1533 09:36:32.441324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1534 09:36:32.452668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1535 09:36:32.463792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1536 09:36:32.475068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1537 09:36:32.486090 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1538 09:36:32.497279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1539 09:36:32.508414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1540 09:36:32.519643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1541 09:36:32.530803 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1542 09:36:32.542159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1543 09:36:32.553309 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1544 09:36:32.564411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1545 09:36:32.575608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1546 09:36:32.592444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1547 09:36:32.603573 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1548 09:36:32.614765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1549 09:36:32.626008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1550 09:36:32.637164 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1551 09:36:32.654011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1552 09:36:32.665331 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1553 09:36:32.676495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1554 09:36:32.687871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1555 09:36:32.693297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1556 09:36:32.704530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1557 09:36:32.716017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1558 09:36:32.721307 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1559 09:36:32.732464 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1560 09:36:32.738077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1561 09:36:32.749365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1562 09:36:32.754866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1563 09:36:32.766116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1564 09:36:32.771714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1565 09:36:32.782870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1566 09:36:32.788441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1567 09:36:32.799654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1568 09:36:32.810834 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1569 09:36:32.822022 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1570 09:36:32.833211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1571 09:36:32.844469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1572 09:36:32.850043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1573 09:36:32.861194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1574 09:36:32.866765 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1575 09:36:32.872457 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1576 09:36:32.878014 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1577 09:36:32.883659 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1578 09:36:32.889238 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1579 09:36:32.900486 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1580 09:36:32.906028 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1581 09:36:32.911608 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1582 09:36:32.922786 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1583 09:36:32.928383 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1584 09:36:32.939703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1585 09:36:32.945159 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1586 09:36:32.956363 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1587 09:36:32.961966 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1588 09:36:32.973140 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1589 09:36:32.978914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1590 09:36:32.989947 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1591 09:36:32.995555 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1592 09:36:33.006762 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1593 09:36:33.012400 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1594 09:36:33.023505 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1595 09:36:33.029193 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1596 09:36:33.034795 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1597 09:36:33.045992 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1598 09:36:33.051599 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1599 09:36:33.062790 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1600 09:36:33.068532 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1601 09:36:33.079682 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1602 09:36:33.085321 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1603 09:36:33.096520 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1604 09:36:33.102110 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1605 09:36:33.107709 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1606 09:36:33.118907 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1607 09:36:33.124507 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1608 09:36:33.135831 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1609 09:36:33.147059 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1610 09:36:33.158232 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1611 09:36:33.170378 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1612 09:36:33.180691 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1613 09:36:33.191848 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1614 09:36:33.203021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1615 09:36:33.214227 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1616 09:36:33.219803 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1617 09:36:33.231015 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1618 09:36:33.236576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1619 09:36:33.247860 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1620 09:36:33.253365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1621 09:36:33.264557 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1622 09:36:33.270161 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1623 09:36:33.281386 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1624 09:36:33.287195 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1625 09:36:33.298173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1626 09:36:33.303819 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1627 09:36:33.315107 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1628 09:36:33.320536 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1629 09:36:33.331777 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1630 09:36:33.337408 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1631 09:36:33.343007 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1632 09:36:33.354195 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1633 09:36:33.359797 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1634 09:36:33.371043 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1635 09:36:33.376614 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1636 09:36:33.387847 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1637 09:36:33.393505 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1638 09:36:33.404634 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1639 09:36:33.410201 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1640 09:36:33.415807 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1641 09:36:33.421477 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1642 09:36:33.432615 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1643 09:36:33.443868 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1644 09:36:33.449538 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1645 09:36:33.455150 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1646 09:36:33.466502 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1647 09:36:33.477789 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1648 09:36:33.488728 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1649 09:36:33.499910 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1650 09:36:33.505618 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1651 09:36:33.511055 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1652 09:36:33.516785 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1653 09:36:33.522363 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1654 09:36:33.527911 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1655 09:36:33.533747 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1656 09:36:33.544744 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1657 09:36:33.550291 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1658 09:36:33.555921 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1659 09:36:33.561643 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1660 09:36:33.567219 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1661 09:36:33.578327 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1662 09:36:33.583932 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1663 09:36:33.589590 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1664 09:36:33.595133 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1665 09:36:33.600775 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1666 09:36:33.606383 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1667 09:36:33.611939 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1668 09:36:33.617555 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1669 09:36:33.623142 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1670 09:36:33.628772 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1671 09:36:33.634375 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1672 09:36:33.639948 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1673 09:36:33.645651 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1674 09:36:33.651113 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1675 09:36:33.657591 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1676 09:36:33.662385 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1677 09:36:33.667962 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1678 09:36:33.673606 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1679 09:36:33.679132 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1680 09:36:33.684752 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1681 09:36:33.690341 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1682 09:36:33.690581 dt_test_unprobed_devices_sh_opp-table skip
1683 09:36:33.695925 dt_test_unprobed_devices_sh_soc skip
1684 09:36:33.701586 dt_test_unprobed_devices_sh_sound pass
1685 09:36:33.707138 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1686 09:36:33.712748 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1687 09:36:33.718338 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1688 09:36:33.723918 dt_test_unprobed_devices_sh fail
1689 09:36:33.724147 + ../../utils/send-to-lava.sh ./output/result.txt
1690 09:36:33.731815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1691 09:36:33.732322 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1693 09:36:33.764480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1694 09:36:33.765006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1696 09:36:33.864151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1697 09:36:33.864681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1699 09:36:33.962133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1700 09:36:33.962661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1702 09:36:34.055610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1703 09:36:34.056115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1705 09:36:34.153746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1706 09:36:34.154242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1708 09:36:34.250290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1709 09:36:34.250795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1711 09:36:34.343537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1712 09:36:34.344042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1714 09:36:34.440915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1715 09:36:34.441427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1717 09:36:34.534892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1718 09:36:34.535362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1720 09:36:34.629768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1721 09:36:34.630208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1723 09:36:34.724214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1724 09:36:34.724744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1726 09:36:34.818816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1727 09:36:34.819301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1729 09:36:34.912021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1730 09:36:34.912483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1732 09:36:35.004569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1733 09:36:35.005085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1735 09:36:35.097938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1736 09:36:35.098379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1738 09:36:35.194864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1739 09:36:35.195313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1741 09:36:35.287327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1742 09:36:35.287850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1744 09:36:35.383994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1745 09:36:35.384468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1747 09:36:35.478153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1748 09:36:35.478602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1750 09:36:35.572019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1751 09:36:35.572518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1753 09:36:35.664622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1754 09:36:35.665113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1756 09:36:35.761800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1757 09:36:35.762279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1759 09:36:35.856372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1760 09:36:35.856842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1762 09:36:35.949209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1763 09:36:35.949669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1765 09:36:36.046140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1766 09:36:36.046587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1768 09:36:36.139969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1769 09:36:36.140415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1771 09:36:36.237268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1772 09:36:36.237710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1774 09:36:36.330405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1775 09:36:36.330885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1777 09:36:36.427896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1778 09:36:36.428372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1780 09:36:36.520183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1781 09:36:36.520656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1783 09:36:36.618164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1784 09:36:36.618626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1786 09:36:36.711910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1787 09:36:36.712372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1789 09:36:36.806834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1790 09:36:36.807280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1792 09:36:36.902463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1793 09:36:36.902957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1795 09:36:36.998343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1796 09:36:36.998792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1798 09:36:37.092102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1799 09:36:37.092612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1801 09:36:37.189619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1802 09:36:37.190075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1804 09:36:37.284818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1805 09:36:37.285276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1807 09:36:37.386765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1808 09:36:37.387233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1810 09:36:37.480391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1811 09:36:37.480839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1813 09:36:37.574457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1814 09:36:37.574929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1816 09:36:37.672004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1817 09:36:37.672464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1819 09:36:37.770754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1820 09:36:37.771222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1822 09:36:37.861260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1823 09:36:37.862077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1825 09:36:37.958390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1826 09:36:37.958841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1828 09:36:38.052497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1829 09:36:38.052950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1831 09:36:38.145823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1832 09:36:38.146294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1834 09:36:38.241043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1835 09:36:38.241532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1837 09:36:38.338205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1838 09:36:38.338693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1840 09:36:38.433784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1841 09:36:38.434266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1843 09:36:38.532042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1844 09:36:38.532544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1846 09:36:38.629293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1847 09:36:38.629740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1849 09:36:38.722293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1850 09:36:38.722749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1852 09:36:38.821542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1853 09:36:38.822000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1855 09:36:38.919479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1856 09:36:38.919960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1858 09:36:39.015893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1859 09:36:39.016390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1861 09:36:39.110946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1862 09:36:39.111400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1864 09:36:39.207372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1865 09:36:39.207858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1867 09:36:39.306667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1868 09:36:39.307134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1870 09:36:39.404183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1871 09:36:39.404638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1873 09:36:39.502177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1874 09:36:39.502629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1876 09:36:39.597037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1877 09:36:39.597499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1879 09:36:39.689842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1880 09:36:39.690301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1882 09:36:39.790233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1883 09:36:39.790693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1885 09:36:39.887537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1886 09:36:39.887984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1888 09:36:39.988989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1889 09:36:39.989435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1891 09:36:40.085730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1892 09:36:40.086174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1894 09:36:40.182961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1895 09:36:40.183422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1897 09:36:40.278935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1898 09:36:40.279398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1900 09:36:40.374207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1901 09:36:40.374674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1903 09:36:40.473109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1904 09:36:40.473562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1906 09:36:40.569658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1907 09:36:40.570134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1909 09:36:40.663300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1910 09:36:40.663800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1912 09:36:40.761364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1913 09:36:40.761828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1915 09:36:40.859045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1916 09:36:40.859558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1918 09:36:40.952505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1919 09:36:40.952960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1921 09:36:41.045749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1922 09:36:41.046214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1924 09:36:41.144651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1925 09:36:41.145081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1927 09:36:41.239822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1928 09:36:41.240316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1930 09:36:41.336582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1931 09:36:41.337034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1933 09:36:41.429093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1934 09:36:41.429619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1936 09:36:41.619213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1937 09:36:41.619665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1939 09:36:41.716984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1940 09:36:41.717441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1942 09:36:41.810320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1943 09:36:41.810773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1945 09:36:41.903365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1946 09:36:41.903844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1948 09:36:41.998948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1949 09:36:41.999419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1951 09:36:42.093070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1952 09:36:42.093525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1954 09:36:42.190306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1955 09:36:42.190796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1957 09:36:42.288841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1958 09:36:42.289309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1960 09:36:42.399950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1961 09:36:42.400416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1963 09:36:42.489042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1964 09:36:42.489517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1966 09:36:42.590234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1967 09:36:42.590704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1969 09:36:42.685967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1970 09:36:42.686433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1972 09:36:42.784885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1973 09:36:42.785352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1975 09:36:42.878219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1976 09:36:42.878685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1978 09:36:42.972644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1979 09:36:42.973105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1981 09:36:43.068510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1982 09:36:43.068973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1984 09:36:43.186209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1985 09:36:43.186665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1987 09:36:43.280261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1988 09:36:43.280712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1990 09:36:43.367084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1991 09:36:43.367546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1993 09:36:43.455698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1994 09:36:43.456153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1996 09:36:43.544038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1997 09:36:43.544482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1999 09:36:43.633663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
2000 09:36:43.634097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
2002 09:36:43.719867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
2003 09:36:43.720309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
2005 09:36:43.808518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
2006 09:36:43.808957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
2008 09:36:43.896514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
2009 09:36:43.896959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
2011 09:36:43.982922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
2012 09:36:43.983361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
2014 09:36:44.076309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
2015 09:36:44.076744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
2017 09:36:44.173120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
2018 09:36:44.173553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
2020 09:36:44.265290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
2021 09:36:44.265761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
2023 09:36:44.353670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
2024 09:36:44.354113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
2026 09:36:44.446159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
2027 09:36:44.446606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
2029 09:36:44.536012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
2030 09:36:44.536454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
2032 09:36:44.624655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2033 09:36:44.625117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2035 09:36:44.714339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2036 09:36:44.714789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2038 09:36:44.809374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2039 09:36:44.809860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2041 09:36:44.897665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2042 09:36:44.898124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2044 09:36:44.989093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2045 09:36:44.989586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2047 09:36:45.078441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2048 09:36:45.078916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2050 09:36:45.165731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2052 09:36:45.168866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2053 09:36:45.262774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2055 09:36:45.265869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2056 09:36:45.351782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2058 09:36:45.354870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2059 09:36:45.443130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2060 09:36:45.443553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2062 09:36:45.535952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2063 09:36:45.536399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2065 09:36:45.623978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2066 09:36:45.624470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2068 09:36:45.795725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2069 09:36:45.796220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2071 09:36:45.896767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2072 09:36:45.897226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2074 09:36:45.992662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2075 09:36:45.993113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2077 09:36:46.091969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2078 09:36:46.092500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2080 09:36:46.186972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2081 09:36:46.187426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2083 09:36:46.278707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2084 09:36:46.279157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2086 09:36:46.375821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2087 09:36:46.376278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2089 09:36:46.468389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2090 09:36:46.468844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2092 09:36:46.566023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2093 09:36:46.566514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2095 09:36:46.662072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2096 09:36:46.662528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2098 09:36:46.760630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2099 09:36:46.761082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2101 09:36:46.860286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2102 09:36:46.860803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2104 09:36:46.959224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2105 09:36:46.959707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2107 09:36:47.055833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2108 09:36:47.056327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2110 09:36:47.148801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2111 09:36:47.149255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2113 09:36:47.244987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2114 09:36:47.245397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2116 09:36:47.344607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2117 09:36:47.345045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2119 09:36:47.436664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2120 09:36:47.437107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2122 09:36:47.526330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2123 09:36:47.526852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2125 09:36:47.668499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2126 09:36:47.669002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2128 09:36:47.763529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2129 09:36:47.764016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2131 09:36:47.864284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2132 09:36:47.864843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2134 09:36:48.000006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2135 09:36:48.000444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2137 09:36:48.094630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2138 09:36:48.095073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2140 09:36:48.184509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2141 09:36:48.184950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2143 09:36:48.279851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2144 09:36:48.280327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2146 09:36:48.375866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2147 09:36:48.376364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2149 09:36:48.498027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2150 09:36:48.498497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2152 09:36:48.613186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2153 09:36:48.613707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2155 09:36:48.712398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2156 09:36:48.712836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2158 09:36:48.808586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2159 09:36:48.809062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2161 09:36:48.905926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2162 09:36:48.906381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2164 09:36:49.004297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2165 09:36:49.004744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2167 09:36:49.096768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2168 09:36:49.097222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2170 09:36:49.312519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2171 09:36:49.312999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2173 09:36:49.415285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2174 09:36:49.415777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2176 09:36:49.511419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2177 09:36:49.511907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2179 09:36:49.605211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2180 09:36:49.605667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2182 09:36:49.713926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2183 09:36:49.714389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2185 09:36:49.807713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2186 09:36:49.808173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2188 09:36:49.904040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2189 09:36:49.904503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2191 09:36:49.994825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2192 09:36:49.995285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2194 09:36:50.090777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2195 09:36:50.091238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2197 09:36:50.299206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2198 09:36:50.299654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2200 09:36:50.397613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2201 09:36:50.398058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2203 09:36:50.492814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2204 09:36:50.493249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2206 09:36:50.585281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2207 09:36:50.585719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2209 09:36:50.674709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2210 09:36:50.675148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2212 09:36:50.765937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2213 09:36:50.766387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2215 09:36:50.855640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2216 09:36:50.856074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2218 09:36:50.952343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2219 09:36:50.952684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2221 09:36:51.044316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2222 09:36:51.044753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2224 09:36:51.142985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2225 09:36:51.143411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2227 09:36:51.238886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2228 09:36:51.239321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2230 09:36:51.330477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2231 09:36:51.330909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2233 09:36:51.426452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2234 09:36:51.426926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2236 09:36:51.517104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2237 09:36:51.517542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2239 09:36:51.610644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2240 09:36:51.611103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2242 09:36:51.703110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2243 09:36:51.703547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2245 09:36:51.798670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2246 09:36:51.799094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2248 09:36:51.883592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2249 09:36:51.884023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2251 09:36:51.975539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2252 09:36:51.975962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2254 09:36:52.065795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2255 09:36:52.066236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2257 09:36:52.155050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2258 09:36:52.155469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2260 09:36:52.247483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2261 09:36:52.247950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2263 09:36:52.340291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2264 09:36:52.340729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2266 09:36:52.426507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2267 09:36:52.426971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2269 09:36:52.518617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2270 09:36:52.519047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2272 09:36:52.609312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2273 09:36:52.609751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2275 09:36:52.701452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2276 09:36:52.701887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2278 09:36:52.796020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2279 09:36:52.796463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2281 09:36:52.890141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2282 09:36:52.890576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2284 09:36:52.978283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2285 09:36:52.978723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2287 09:36:53.074884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2288 09:36:53.075327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2290 09:36:53.227388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2291 09:36:53.227869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2293 09:36:53.321221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2294 09:36:53.321671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2296 09:36:53.414318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2297 09:36:53.414768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2299 09:36:53.506674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2300 09:36:53.507125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2302 09:36:53.599638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2303 09:36:53.600085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2305 09:36:53.690802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2306 09:36:53.691254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2308 09:36:53.786366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2309 09:36:53.786804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2311 09:36:53.878344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2312 09:36:53.878786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2314 09:36:53.970611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2315 09:36:53.971038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2317 09:36:54.061579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2318 09:36:54.062025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2320 09:36:54.156518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2321 09:36:54.156978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2323 09:36:54.252967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2324 09:36:54.253410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2326 09:36:54.348275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2327 09:36:54.348757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2329 09:36:54.440580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2330 09:36:54.441051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2332 09:36:54.531968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2333 09:36:54.532435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2335 09:36:54.628536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2336 09:36:54.628992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2338 09:36:54.719985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2339 09:36:54.720444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2341 09:36:54.817996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2342 09:36:54.818430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2344 09:36:54.910556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2345 09:36:54.911026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2347 09:36:55.006683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2348 09:36:55.007133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2350 09:36:55.100649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2351 09:36:55.101084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2353 09:36:55.193719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2354 09:36:55.194156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2356 09:36:55.286523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2357 09:36:55.286964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2359 09:36:55.378217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2360 09:36:55.378665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2362 09:36:55.473922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2363 09:36:55.474357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2365 09:36:55.571689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2366 09:36:55.572133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2368 09:36:55.667914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2369 09:36:55.668347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2371 09:36:55.755400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2373 09:36:55.757722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2374 09:36:55.852454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2375 09:36:55.852892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2377 09:36:55.943432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2378 09:36:55.943916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2380 09:36:56.033317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2381 09:36:56.033762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2383 09:36:56.124695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2384 09:36:56.125134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2386 09:36:56.214822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2387 09:36:56.215255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2389 09:36:56.310076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2390 09:36:56.310508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2392 09:36:56.403657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2393 09:36:56.404103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2395 09:36:56.495291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2396 09:36:56.495756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2398 09:36:56.587221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2399 09:36:56.587661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2401 09:36:56.681547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2402 09:36:56.682010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2404 09:36:56.773302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2405 09:36:56.773770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2407 09:36:56.874685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2408 09:36:56.875052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2410 09:36:56.968222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2411 09:36:56.968664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2413 09:36:57.059508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2414 09:36:57.059936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2416 09:36:57.154337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2417 09:36:57.154771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2419 09:36:57.246786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2420 09:36:57.247284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2422 09:36:57.341284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2423 09:36:57.341777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2425 09:36:57.437005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2426 09:36:57.437506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2428 09:36:57.531747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2429 09:36:57.532244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2431 09:36:57.627194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2432 09:36:57.627682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2434 09:36:57.722279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2435 09:36:57.722800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2437 09:36:58.079137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2438 09:36:58.079477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2439 09:36:58.079935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2441 09:36:58.080488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2443 09:36:58.081689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2444 09:36:58.082100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2446 09:36:58.109586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2447 09:36:58.110087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2449 09:36:58.205100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2450 09:36:58.205639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2452 09:36:58.302288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2453 09:36:58.302778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2455 09:36:58.399732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2456 09:36:58.400247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2458 09:36:58.497579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2459 09:36:58.498072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2461 09:36:58.594973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2462 09:36:58.595472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2464 09:36:58.686724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2465 09:36:58.687008 + set +x
2466 09:36:58.687387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2468 09:36:58.689851 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 743617_1.6.2.4.5>
2469 09:36:58.690295 Received signal: <ENDRUN> 1_kselftest-dt 743617_1.6.2.4.5
2470 09:36:58.690485 Ending use of test pattern.
2471 09:36:58.690646 Ending test lava.1_kselftest-dt (743617_1.6.2.4.5), duration 95.38
2473 09:36:58.700409 <LAVA_TEST_RUNNER EXIT>
2474 09:36:58.700844 ok: lava_test_shell seems to have completed
2475 09:36:58.704839 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2476 09:36:58.705621 end: 3.1 lava-test-shell (duration 00:01:37) [common]
2477 09:36:58.705836 end: 3 lava-test-retry (duration 00:01:37) [common]
2478 09:36:58.706066 start: 4 finalize (timeout 00:05:46) [common]
2479 09:36:58.706287 start: 4.1 power-off (timeout 00:00:30) [common]
2480 09:36:58.706661 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2481 09:36:58.726674 >> OK - accepted request
2482 09:36:58.728465 Returned 0 in 0 seconds
2483 09:36:58.829152 end: 4.1 power-off (duration 00:00:00) [common]
2485 09:36:58.829887 start: 4.2 read-feedback (timeout 00:05:46) [common]
2486 09:36:58.830464 Listened to connection for namespace 'common' for up to 1s
2487 09:36:58.830936 Listened to connection for namespace 'common' for up to 1s
2488 09:36:59.831357 Finalising connection for namespace 'common'
2489 09:36:59.831848 Disconnecting from shell: Finalise
2490 09:36:59.832070 / #
2491 09:36:59.932709 end: 4.2 read-feedback (duration 00:00:01) [common]
2492 09:36:59.933134 end: 4 finalize (duration 00:00:01) [common]
2493 09:36:59.933430 Cleaning after the job
2494 09:36:59.933695 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/ramdisk
2495 09:36:59.941691 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/kernel
2496 09:36:59.947757 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/dtb
2497 09:36:59.948264 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/nfsrootfs
2498 09:37:00.061248 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/743617/tftp-deploy-s_g8aco4/modules
2499 09:37:00.067597 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/743617
2500 09:37:01.022290 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/743617
2501 09:37:01.022527 Job finished correctly