Boot log: beaglebone-black
- Warnings: 3
- Kernel Warnings: 101
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 20:52:03.426738 lava-dispatcher, installed at version: 2023.08
2 20:52:03.427050 start: 0 validate
3 20:52:03.427231 Start time: 2024-09-19 20:52:03.427220+00:00 (UTC)
4 20:52:03.427455 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 20:52:03.918574 Validating that http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 20:52:04.032866 Validating that http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 20:52:04.146621 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 20:52:04.260054 Validating that http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 20:52:04.378396 validate duration: 0.95
11 20:52:04.379180 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 20:52:04.379517 start: 1.1 download-retry (timeout 00:10:00) [common]
13 20:52:04.379832 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 20:52:04.380314 Not decompressing ramdisk as can be used compressed.
15 20:52:04.380614 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 20:52:04.380855 saving as /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/ramdisk/initrd.cpio.gz
17 20:52:04.381100 total size: 4775763 (4 MB)
18 20:52:04.608138 progress 0 % (0 MB)
19 20:52:04.943599 progress 5 % (0 MB)
20 20:52:05.054140 progress 10 % (0 MB)
21 20:52:05.338187 progress 15 % (0 MB)
22 20:52:05.343548 progress 20 % (0 MB)
23 20:52:05.387859 progress 25 % (1 MB)
24 20:52:05.399431 progress 30 % (1 MB)
25 20:52:05.406736 progress 35 % (1 MB)
26 20:52:05.454807 progress 40 % (1 MB)
27 20:52:05.515467 progress 45 % (2 MB)
28 20:52:05.564483 progress 50 % (2 MB)
29 20:52:05.628156 progress 55 % (2 MB)
30 20:52:05.675283 progress 60 % (2 MB)
31 20:52:05.737474 progress 65 % (2 MB)
32 20:52:05.785743 progress 70 % (3 MB)
33 20:52:05.848351 progress 75 % (3 MB)
34 20:52:05.892067 progress 80 % (3 MB)
35 20:52:05.950456 progress 85 % (3 MB)
36 20:52:05.986101 progress 90 % (4 MB)
37 20:52:06.058873 progress 95 % (4 MB)
38 20:52:06.085032 progress 100 % (4 MB)
39 20:52:06.085760 4 MB downloaded in 1.70 s (2.67 MB/s)
40 20:52:06.086223 end: 1.1.1 http-download (duration 00:00:02) [common]
42 20:52:06.087014 end: 1.1 download-retry (duration 00:00:02) [common]
43 20:52:06.087294 start: 1.2 download-retry (timeout 00:09:58) [common]
44 20:52:06.087567 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 20:52:06.087959 downloading http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 20:52:06.088175 saving as /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/kernel/zImage
47 20:52:06.088379 total size: 11403776 (10 MB)
48 20:52:06.088522 No compression specified
49 20:52:06.203311 progress 0 % (0 MB)
50 20:52:06.546535 progress 5 % (0 MB)
51 20:52:06.769949 progress 10 % (1 MB)
52 20:52:06.984459 progress 15 % (1 MB)
53 20:52:07.208566 progress 20 % (2 MB)
54 20:52:07.434226 progress 25 % (2 MB)
55 20:52:07.656123 progress 30 % (3 MB)
56 20:52:07.876110 progress 35 % (3 MB)
57 20:52:08.098125 progress 40 % (4 MB)
58 20:52:08.315334 progress 45 % (4 MB)
59 20:52:08.535118 progress 50 % (5 MB)
60 20:52:08.675975 progress 55 % (6 MB)
61 20:52:08.891659 progress 60 % (6 MB)
62 20:52:09.110934 progress 65 % (7 MB)
63 20:52:09.327289 progress 70 % (7 MB)
64 20:52:09.545287 progress 75 % (8 MB)
65 20:52:09.759932 progress 80 % (8 MB)
66 20:52:09.896057 progress 85 % (9 MB)
67 20:52:10.114858 progress 90 % (9 MB)
68 20:52:10.330997 progress 95 % (10 MB)
69 20:52:10.552490 progress 100 % (10 MB)
70 20:52:10.552864 10 MB downloaded in 4.46 s (2.44 MB/s)
71 20:52:10.553241 end: 1.2.1 http-download (duration 00:00:04) [common]
73 20:52:10.553907 end: 1.2 download-retry (duration 00:00:04) [common]
74 20:52:10.554146 start: 1.3 download-retry (timeout 00:09:54) [common]
75 20:52:10.554373 start: 1.3.1 http-download (timeout 00:09:54) [common]
76 20:52:10.554740 downloading http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 20:52:10.554929 saving as /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/dtb/am335x-boneblack.dtb
78 20:52:10.555099 total size: 70568 (0 MB)
79 20:52:10.555271 No compression specified
80 20:52:10.671112 progress 46 % (0 MB)
81 20:52:10.673914 progress 92 % (0 MB)
82 20:52:10.674901 progress 100 % (0 MB)
83 20:52:10.675302 0 MB downloaded in 0.12 s (0.56 MB/s)
84 20:52:10.675737 end: 1.3.1 http-download (duration 00:00:00) [common]
86 20:52:10.676559 end: 1.3 download-retry (duration 00:00:00) [common]
87 20:52:10.676841 start: 1.4 download-retry (timeout 00:09:54) [common]
88 20:52:10.677123 start: 1.4.1 http-download (timeout 00:09:54) [common]
89 20:52:10.677512 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 20:52:10.677737 saving as /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/nfsrootfs/full.rootfs.tar
91 20:52:10.677947 total size: 117747780 (112 MB)
92 20:52:10.678165 Using unxz to decompress xz
93 20:52:10.794554 progress 0 % (0 MB)
94 20:52:13.266583 progress 5 % (5 MB)
95 20:52:15.399685 progress 10 % (11 MB)
96 20:52:17.516433 progress 15 % (16 MB)
97 20:52:19.541517 progress 20 % (22 MB)
98 20:52:21.442246 progress 25 % (28 MB)
99 20:52:23.013585 progress 30 % (33 MB)
100 20:52:24.256871 progress 35 % (39 MB)
101 20:52:25.284835 progress 40 % (44 MB)
102 20:52:26.175824 progress 45 % (50 MB)
103 20:52:26.934549 progress 50 % (56 MB)
104 20:52:27.591847 progress 55 % (61 MB)
105 20:52:28.169128 progress 60 % (67 MB)
106 20:52:28.689015 progress 65 % (73 MB)
107 20:52:29.317548 progress 70 % (78 MB)
108 20:52:29.832796 progress 75 % (84 MB)
109 20:52:30.423700 progress 80 % (89 MB)
110 20:52:30.987338 progress 85 % (95 MB)
111 20:52:31.526589 progress 90 % (101 MB)
112 20:52:32.042745 progress 95 % (106 MB)
113 20:52:32.552501 progress 100 % (112 MB)
114 20:52:32.555997 112 MB downloaded in 21.88 s (5.13 MB/s)
115 20:52:32.556347 end: 1.4.1 http-download (duration 00:00:22) [common]
117 20:52:32.556914 end: 1.4 download-retry (duration 00:00:22) [common]
118 20:52:32.557112 start: 1.5 download-retry (timeout 00:09:32) [common]
119 20:52:32.557305 start: 1.5.1 http-download (timeout 00:09:32) [common]
120 20:52:32.557597 downloading http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 20:52:32.557750 saving as /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/modules/modules.tar
122 20:52:32.557893 total size: 6613592 (6 MB)
123 20:52:32.558040 Using unxz to decompress xz
124 20:52:32.673320 progress 0 % (0 MB)
125 20:52:32.916042 progress 5 % (0 MB)
126 20:52:33.177266 progress 10 % (0 MB)
127 20:52:33.253144 progress 15 % (0 MB)
128 20:52:33.344770 progress 20 % (1 MB)
129 20:52:33.371607 progress 25 % (1 MB)
130 20:52:33.397235 progress 30 % (1 MB)
131 20:52:33.562040 progress 35 % (2 MB)
132 20:52:33.588012 progress 40 % (2 MB)
133 20:52:33.612145 progress 45 % (2 MB)
134 20:52:33.779014 progress 50 % (3 MB)
135 20:52:33.805226 progress 55 % (3 MB)
136 20:52:33.829673 progress 60 % (3 MB)
137 20:52:33.853915 progress 65 % (4 MB)
138 20:52:33.877909 progress 70 % (4 MB)
139 20:52:33.901637 progress 75 % (4 MB)
140 20:52:33.940435 progress 80 % (5 MB)
141 20:52:34.029884 progress 85 % (5 MB)
142 20:52:34.101310 progress 90 % (5 MB)
143 20:52:34.171389 progress 95 % (6 MB)
144 20:52:34.257942 progress 100 % (6 MB)
145 20:52:34.261651 6 MB downloaded in 1.70 s (3.70 MB/s)
146 20:52:34.262068 end: 1.5.1 http-download (duration 00:00:02) [common]
148 20:52:34.262807 end: 1.5 download-retry (duration 00:00:02) [common]
149 20:52:34.263076 start: 1.6 prepare-tftp-overlay (timeout 00:09:30) [common]
150 20:52:34.263333 start: 1.6.1 extract-nfsrootfs (timeout 00:09:30) [common]
151 20:52:39.812965 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1193790/extract-nfsrootfs-m1ujbv4e
152 20:52:39.813252 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 20:52:39.813381 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
154 20:52:39.813651 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z
155 20:52:39.813819 makedir: /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin
156 20:52:39.813951 makedir: /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/tests
157 20:52:39.814079 makedir: /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/results
158 20:52:39.814221 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-add-keys
159 20:52:39.814424 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-add-sources
160 20:52:39.814598 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-background-process-start
161 20:52:39.814768 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-background-process-stop
162 20:52:39.814952 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-common-functions
163 20:52:39.815121 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-echo-ipv4
164 20:52:39.815288 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-install-packages
165 20:52:39.815451 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-installed-packages
166 20:52:39.815614 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-os-build
167 20:52:39.815778 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-probe-channel
168 20:52:39.815941 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-probe-ip
169 20:52:39.816106 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-target-ip
170 20:52:39.816294 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-target-mac
171 20:52:39.816456 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-target-storage
172 20:52:39.816622 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-test-case
173 20:52:39.816785 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-test-event
174 20:52:39.816947 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-test-feedback
175 20:52:39.817109 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-test-raise
176 20:52:39.817271 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-test-reference
177 20:52:39.817434 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-test-runner
178 20:52:39.817597 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-test-set
179 20:52:39.817759 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-test-shell
180 20:52:39.817924 Updating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-add-keys (debian)
181 20:52:39.818140 Updating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-add-sources (debian)
182 20:52:39.818327 Updating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-install-packages (debian)
183 20:52:39.818512 Updating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-installed-packages (debian)
184 20:52:39.818697 Updating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/bin/lava-os-build (debian)
185 20:52:39.818860 Creating /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/environment
186 20:52:39.818984 LAVA metadata
187 20:52:39.819079 - LAVA_JOB_ID=1193790
188 20:52:39.819171 - LAVA_DISPATCHER_IP=192.168.11.5
189 20:52:39.819307 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
190 20:52:39.819623 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 20:52:39.819768 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
192 20:52:39.819859 skipped lava-vland-overlay
193 20:52:39.819967 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 20:52:39.820080 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
195 20:52:39.820172 skipped lava-multinode-overlay
196 20:52:39.820417 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 20:52:39.820529 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
198 20:52:39.820627 Loading test definitions
199 20:52:39.820745 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
200 20:52:39.820841 Using /lava-1193790 at stage 0
201 20:52:39.821231 uuid=1193790_1.6.2.4.1 testdef=None
202 20:52:39.821348 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 20:52:39.821461 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
204 20:52:39.822053 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 20:52:39.822375 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
207 20:52:39.823138 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 20:52:39.823466 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
210 20:52:39.824218 runner path: /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/0/tests/0_timesync-off test_uuid 1193790_1.6.2.4.1
211 20:52:39.824418 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 20:52:39.824740 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
214 20:52:39.824839 Using /lava-1193790 at stage 0
215 20:52:39.824971 Fetching tests from https://github.com/kernelci/test-definitions.git
216 20:52:39.825070 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/0/tests/1_kselftest-dt'
217 20:52:44.878582 Running '/usr/bin/git checkout kernelci.org
218 20:52:45.099374 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 20:52:45.100251 uuid=1193790_1.6.2.4.5 testdef=None
220 20:52:45.100560 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 20:52:45.101069 start: 1.6.2.4.6 test-overlay (timeout 00:09:19) [common]
223 20:52:45.102950 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 20:52:45.103588 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:19) [common]
226 20:52:45.106326 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 20:52:45.106959 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:19) [common]
229 20:52:45.109542 runner path: /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/0/tests/1_kselftest-dt test_uuid 1193790_1.6.2.4.5
230 20:52:45.109747 BOARD='beaglebone-black'
231 20:52:45.109911 BRANCH='mainline'
232 20:52:45.110069 SKIPFILE='/dev/null'
233 20:52:45.110225 SKIP_INSTALL='True'
234 20:52:45.110381 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 20:52:45.110539 TST_CASENAME=''
236 20:52:45.110691 TST_CMDFILES='dt'
237 20:52:45.111031 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 20:52:45.111579 Creating lava-test-runner.conf files
240 20:52:45.111738 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1193790/lava-overlay-zk9w9u0z/lava-1193790/0 for stage 0
241 20:52:45.111960 - 0_timesync-off
242 20:52:45.112127 - 1_kselftest-dt
243 20:52:45.112346 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 20:52:45.112463 start: 1.6.2.5 compress-overlay (timeout 00:09:19) [common]
245 20:52:53.626375 end: 1.6.2.5 compress-overlay (duration 00:00:09) [common]
246 20:52:53.626586 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
247 20:52:53.626732 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 20:52:53.626878 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 20:52:53.627022 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
250 20:52:53.750946 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 20:52:53.751236 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
252 20:52:53.751399 extracting modules file /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1193790/extract-nfsrootfs-m1ujbv4e
253 20:52:54.050414 extracting modules file /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1193790/extract-overlay-ramdisk-aec2grzl/ramdisk
254 20:52:54.358779 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 20:52:54.359000 start: 1.6.5 apply-overlay-tftp (timeout 00:09:10) [common]
256 20:52:54.359134 [common] Applying overlay to NFS
257 20:52:54.359242 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1193790/compress-overlay-n8u7ekeg/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1193790/extract-nfsrootfs-m1ujbv4e
258 20:52:55.538775 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 20:52:55.538987 start: 1.6.6 prepare-kernel (timeout 00:09:09) [common]
260 20:52:55.539132 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:09) [common]
261 20:52:55.539278 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 20:52:55.539414 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 20:52:55.539552 start: 1.6.7 configure-preseed-file (timeout 00:09:09) [common]
264 20:52:55.539684 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 20:52:55.539819 start: 1.6.8 compress-ramdisk (timeout 00:09:09) [common]
266 20:52:55.539923 Building ramdisk /var/lib/lava/dispatcher/tmp/1193790/extract-overlay-ramdisk-aec2grzl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1193790/extract-overlay-ramdisk-aec2grzl/ramdisk
267 20:52:55.852770 >> 74838 blocks
268 20:52:57.787577 Adding RAMdisk u-boot header.
269 20:52:57.787861 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1193790/extract-overlay-ramdisk-aec2grzl/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1193790/extract-overlay-ramdisk-aec2grzl/ramdisk.cpio.gz.uboot
270 20:52:57.940070 output: Image Name:
271 20:52:57.940457 output: Created: Thu Sep 19 20:52:57 2024
272 20:52:57.940687 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 20:52:57.940908 output: Data Size: 14806030 Bytes = 14459.01 KiB = 14.12 MiB
274 20:52:57.941124 output: Load Address: 00000000
275 20:52:57.941335 output: Entry Point: 00000000
276 20:52:57.941546 output:
277 20:52:57.941879 rename /var/lib/lava/dispatcher/tmp/1193790/extract-overlay-ramdisk-aec2grzl/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/ramdisk/ramdisk.cpio.gz.uboot
278 20:52:57.942237 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 20:52:57.942508 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
280 20:52:57.942775 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:06) [common]
281 20:52:57.942984 No LXC device requested
282 20:52:57.943236 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 20:52:57.943495 start: 1.8 deploy-device-env (timeout 00:09:06) [common]
284 20:52:57.943744 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 20:52:57.943944 Checking files for TFTP limit of 4294967296 bytes.
286 20:52:57.945202 end: 1 tftp-deploy (duration 00:00:54) [common]
287 20:52:57.945478 start: 2 uboot-action (timeout 00:05:00) [common]
288 20:52:57.945744 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 20:52:57.945996 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 20:52:57.946254 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 20:52:57.946633 substitutions:
292 20:52:57.946838 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 20:52:57.947039 - {DTB_ADDR}: 0x88000000
294 20:52:57.947235 - {DTB}: 1193790/tftp-deploy-wiehv_vq/dtb/am335x-boneblack.dtb
295 20:52:57.947432 - {INITRD}: 1193790/tftp-deploy-wiehv_vq/ramdisk/ramdisk.cpio.gz.uboot
296 20:52:57.947627 - {KERNEL_ADDR}: 0x82000000
297 20:52:57.947821 - {KERNEL}: 1193790/tftp-deploy-wiehv_vq/kernel/zImage
298 20:52:57.948014 - {LAVA_MAC}: None
299 20:52:57.948227 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1193790/extract-nfsrootfs-m1ujbv4e
300 20:52:57.948443 - {NFS_SERVER_IP}: 192.168.11.5
301 20:52:57.948632 - {PRESEED_CONFIG}: None
302 20:52:57.948821 - {PRESEED_LOCAL}: None
303 20:52:57.949010 - {RAMDISK_ADDR}: 0x83000000
304 20:52:57.949198 - {RAMDISK}: 1193790/tftp-deploy-wiehv_vq/ramdisk/ramdisk.cpio.gz.uboot
305 20:52:57.949388 - {ROOT_PART}: None
306 20:52:57.949574 - {ROOT}: None
307 20:52:57.949759 - {SERVER_IP}: 192.168.11.5
308 20:52:57.949945 - {TEE_ADDR}: 0x83000000
309 20:52:57.950129 - {TEE}: None
310 20:52:57.950315 Parsed boot commands:
311 20:52:57.950497 - setenv autoload no
312 20:52:57.950683 - setenv initrd_high 0xffffffff
313 20:52:57.950867 - setenv fdt_high 0xffffffff
314 20:52:57.951051 - dhcp
315 20:52:57.951235 - setenv serverip 192.168.11.5
316 20:52:57.951419 - tftp 0x82000000 1193790/tftp-deploy-wiehv_vq/kernel/zImage
317 20:52:57.951606 - tftp 0x83000000 1193790/tftp-deploy-wiehv_vq/ramdisk/ramdisk.cpio.gz.uboot
318 20:52:57.951794 - setenv initrd_size ${filesize}
319 20:52:57.951979 - tftp 0x88000000 1193790/tftp-deploy-wiehv_vq/dtb/am335x-boneblack.dtb
320 20:52:57.952164 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1193790/extract-nfsrootfs-m1ujbv4e,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 20:52:57.952351 - bootz 0x82000000 0x83000000 0x88000000
322 20:52:57.952462 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 20:52:57.952779 start: 2.3 connect-device (timeout 00:05:00) [common]
325 20:52:57.952872 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 20:52:58.311692 Setting prompt string to ['lava-test: # ']
327 20:52:58.312152 end: 2.3 connect-device (duration 00:00:00) [common]
328 20:52:58.312366 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 20:52:58.312536 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 20:52:58.312686 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 20:52:58.313018 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 20:52:58.679523 Returned 0 in 0 seconds
333 20:52:58.780607 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 20:52:58.781492 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 20:52:58.781814 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 20:52:58.782094 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 20:52:58.782343 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 20:52:58.783073 Trying 127.0.0.1...
340 20:52:58.783306 Connected to 127.0.0.1.
341 20:52:58.783520 Escape character is '^]'.
342 20:53:03.598192
343 20:53:03.601975 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 20:53:03.658528 Trying to boot from MMC2
345 20:53:03.707004 Loading Environment from EXT4... Card did not respond to voltage select!
346 20:53:03.774398
347 20:53:03.774739
348 20:53:03.779959 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 20:53:03.780261
350 20:53:03.784863 CPU : AM335X-GP rev 2.1
351 20:53:03.838729 I2C: ready
352 20:53:03.839006 DRAM: 512 MiB
353 20:53:03.893411 No match for driver 'omap_hsmmc'
354 20:53:03.898942 No match for driver 'omap_hsmmc'
355 20:53:03.899221 Some drivers were not found
356 20:53:03.905272 Reset Source: Power-on reset has occurred.
357 20:53:03.905553 RTC 32KCLK Source: External.
358 20:53:03.912686 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 20:53:03.926070 Loading Environment from EXT4... Card did not respond to voltage select!
360 20:53:03.990530 Board: BeagleBone Black
361 20:53:03.994461 <ethaddr> not set. Validating first E-fuse MAC
362 20:53:04.051063 BeagleBone Black:
363 20:53:04.051332 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 20:53:04.056659 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 20:53:04.062635 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 20:53:04.062903 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 20:53:04.067580 Net: eth0: MII MODE
368 20:53:04.076997 cpsw, usb_ether
369 20:53:04.077264 Press SPACE to abort autoboot in 2 seconds
370 20:53:04.128032 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 20:53:04.128393 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 20:53:04.128655 Setting prompt string to ['=> ']
373 20:53:04.128907 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 20:53:04.132308 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 20:53:04.132567 Sending with 10 millisecond of delay
377 20:53:05.267247 => setenv autoload no
378 20:53:05.277728 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 20:53:05.280070 setenv autoload no
380 20:53:05.280573 Sending with 10 millisecond of delay
382 20:53:07.077522 => setenv initrd_high 0xffffffff
383 20:53:07.088041 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 20:53:07.088548 setenv initrd_high 0xffffffff
385 20:53:07.088998 Sending with 10 millisecond of delay
387 20:53:08.705126 => setenv fdt_high 0xffffffff
388 20:53:08.715622 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 20:53:08.716087 setenv fdt_high 0xffffffff
390 20:53:08.716550 Sending with 10 millisecond of delay
392 20:53:09.008025 => dhcp
393 20:53:09.018509 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 20:53:09.018964 dhcp
395 20:53:09.019192 link up on port 0, speed 100, full duplex
396 20:53:09.019409 BOOTP broadcast 1
397 20:53:09.027051 DHCP client bound to address 192.168.11.7 (4 ms)
398 20:53:09.027533 Sending with 10 millisecond of delay
400 20:53:10.764434 => setenv serverip 192.168.11.5
401 20:53:10.775015 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 20:53:10.775638 setenv serverip 192.168.11.5
403 20:53:10.776109 Sending with 10 millisecond of delay
405 20:53:14.319328 => tftp 0x82000000 1193790/tftp-deploy-wiehv_vq/kernel/zImage
406 20:53:14.329839 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 20:53:14.330303 tftp 0x82000000 1193790/tftp-deploy-wiehv_vq/kernel/zImage
408 20:53:14.330534 link up on port 0, speed 100, full duplex
409 20:53:14.330747 Using cpsw device
410 20:53:14.334061 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
411 20:53:14.339685 Filename '1193790/tftp-deploy-wiehv_vq/kernel/zImage'.
412 20:53:14.370858 Load address: 0x82000000
413 20:53:14.525541 Loading: *#################################################################
414 20:53:14.696639 #################################################################
415 20:53:14.883872 #################################################################
416 20:53:15.058372 #################################################################
417 20:53:15.233999 #################################################################
418 20:53:15.409243 #################################################################
419 20:53:15.584122 #################################################################
420 20:53:15.759126 #################################################################
421 20:53:15.933701 #################################################################
422 20:53:16.107926 #################################################################
423 20:53:16.303909 #################################################################
424 20:53:16.457594 ##############################################################
425 20:53:16.457912 5.2 MiB/s
426 20:53:16.458156 done
427 20:53:16.461517 Bytes transferred = 11403776 (ae0200 hex)
428 20:53:16.461992 Sending with 10 millisecond of delay
430 20:53:20.968751 => tftp 0x83000000 1193790/tftp-deploy-wiehv_vq/ramdisk/ramdisk.cpio.gz.uboot
431 20:53:20.979231 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
432 20:53:20.979697 tftp 0x83000000 1193790/tftp-deploy-wiehv_vq/ramdisk/ramdisk.cpio.gz.uboot
433 20:53:20.979928 link up on port 0, speed 100, full duplex
434 20:53:20.980141 Using cpsw device
435 20:53:20.983438 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
436 20:53:21.043650 Filename '1193790/tftp-deploy-wiehv_vq/ramdisk/ramdisk.cpio.gz.uboot'.
437 20:53:21.043930 Load address: 0x83000000
438 20:53:21.169471 Loading: *#################################################################
439 20:53:21.425889 #################################################################
440 20:53:21.510313 #################################################################
441 20:53:21.678465 #################################################################
442 20:53:21.852573 #################################################################
443 20:53:22.025507 #################################################################
444 20:53:22.198804 #################################################################
445 20:53:22.394318 #################################################################
446 20:53:22.565616 #################################################################
447 20:53:22.731854 #################################################################
448 20:53:22.905354 #################################################################
449 20:53:23.079959 #################################################################
450 20:53:23.254882 #################################################################
451 20:53:23.429179 #################################################################
452 20:53:23.614878 #################################################################
453 20:53:23.696649 ##################################
454 20:53:23.696937 5.2 MiB/s
455 20:53:23.697168 done
456 20:53:23.700337 Bytes transferred = 14806094 (e1ec4e hex)
457 20:53:23.700829 Sending with 10 millisecond of delay
459 20:53:25.558035 => setenv initrd_size ${filesize}
460 20:53:25.568544 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
461 20:53:25.569010 setenv initrd_size ${filesize}
462 20:53:25.569456 Sending with 10 millisecond of delay
464 20:53:29.774878 => tftp 0x88000000 1193790/tftp-deploy-wiehv_vq/dtb/am335x-boneblack.dtb
465 20:53:29.785365 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
466 20:53:29.785820 tftp 0x88000000 1193790/tftp-deploy-wiehv_vq/dtb/am335x-boneblack.dtb
467 20:53:29.786076 link up on port 0, speed 100, full duplex
468 20:53:29.786317 Using cpsw device
469 20:53:29.789657 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
470 20:53:29.814834 Filename '1193790/tftp-deploy-wiehv_vq/dtb/am335x-boneblack.dtb'.
471 20:53:29.815089 Load address: 0x88000000
472 20:53:29.815322 Loading: *#####
473 20:53:29.815552 4.8 MiB/s
474 20:53:29.821629 done
475 20:53:29.821898 Bytes transferred = 70568 (113a8 hex)
476 20:53:29.822336 Sending with 10 millisecond of delay
478 20:53:43.121553 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1193790/extract-nfsrootfs-m1ujbv4e,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 20:53:43.132067 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
480 20:53:43.132540 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1193790/extract-nfsrootfs-m1ujbv4e,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 20:53:43.132997 Sending with 10 millisecond of delay
483 20:53:45.472132 => bootz 0x82000000 0x83000000 0x88000000
484 20:53:45.482679 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
485 20:53:45.483002 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
486 20:53:45.483546 bootz 0x82000000 0x83000000 0x88000000
487 20:53:45.483777 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 20:53:45.484257 Image Name:
489 20:53:45.484485 Created: 2024-09-19 20:52:57 UTC
490 20:53:45.489891 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 20:53:45.495515 Data Size: 14806030 Bytes = 14.1 MiB
492 20:53:45.495790 Load Address: 00000000
493 20:53:45.502691 Entry Point: 00000000
494 20:53:45.640149 Verifying Checksum ... OK
495 20:53:45.640443 ## Flattened Device Tree blob at 88000000
496 20:53:45.646630 Booting using the fdt blob at 0x88000000
497 20:53:45.651586 Using Device Tree in place at 88000000, end 880143a7
498 20:53:45.659204
499 20:53:45.659483 Starting kernel ...
500 20:53:45.659709
501 20:53:45.660254 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 20:53:45.660566 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
503 20:53:45.660819 Setting prompt string to ['Linux version [0-9]']
504 20:53:45.661061 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
505 20:53:45.661305 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
506 20:53:46.498997 [ 0.000000] Booting Linux on physical CPU 0x0
507 20:53:46.505010 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
508 20:53:46.505298 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 20:53:46.505548 Setting prompt string to []
510 20:53:46.505807 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 20:53:46.506060 Using line separator: #'\n'#
512 20:53:46.506279 No login prompt set.
513 20:53:46.506508 Parsing kernel messages
514 20:53:46.506717 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 20:53:46.507099 [login-action] Waiting for messages, (timeout 00:04:11)
516 20:53:46.521842 [ 0.000000] Linux version 6.11.0 (KernelCI@build-j314580-arm-gcc-12-multi-v7-defconfig-jpmwj) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Sep 19 08:53:27 UTC 2024
517 20:53:46.527592 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
518 20:53:46.533343 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
519 20:53:46.538968 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
520 20:53:46.550467 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
521 20:53:46.550742 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
522 20:53:46.556235 [ 0.000000] Memory policy: Data cache writeback
523 20:53:46.562838 [ 0.000000] efi: UEFI not found.
524 20:53:46.568007 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
525 20:53:46.573714 [ 0.000000] Zone ranges:
526 20:53:46.579456 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
527 20:53:46.585207 [ 0.000000] Normal empty
528 20:53:46.585481 [ 0.000000] HighMem empty
529 20:53:46.590849 [ 0.000000] Movable zone start for each node
530 20:53:46.591125 [ 0.000000] Early memory node ranges
531 20:53:46.602470 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
532 20:53:46.607732 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
533 20:53:46.632519 [ 0.000000] CPU: All CPU(s) started in SVC mode.
534 20:53:46.638028 [ 0.000000] AM335X ES2.1 (sgx neon)
535 20:53:46.649843 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
536 20:53:46.667469 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1193790/extract-nfsrootfs-m1ujbv4e,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
537 20:53:46.678967 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
538 20:53:46.684738 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
539 20:53:46.690470 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
540 20:53:46.700651 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
541 20:53:46.729843 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
542 20:53:46.735721 <6>[ 0.000000] trace event string verifier disabled
543 20:53:46.735998 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
544 20:53:46.741477 <6>[ 0.000000] rcu: RCU event tracing is enabled.
545 20:53:46.752980 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
546 20:53:46.758717 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
547 20:53:46.765894 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
548 20:53:46.780791 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
549 20:53:46.798087 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
550 20:53:46.804769 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
551 20:53:46.897960 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
552 20:53:46.909459 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
553 20:53:46.916306 <6>[ 0.008340] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
554 20:53:46.929266 <6>[ 0.019168] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
555 20:53:46.936724 <6>[ 0.034068] Console: colour dummy device 80x30
556 20:53:46.942777 Matched prompt #6: WARNING:
557 20:53:46.943068 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
558 20:53:46.948221 <3>[ 0.038971] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
559 20:53:46.950949 <3>[ 0.046041] This ensures that you still see kernel messages. Please
560 20:53:46.957132 <3>[ 0.052769] update your kernel commandline.
561 20:53:46.997831 <6>[ 0.057381] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
562 20:53:47.003579 <6>[ 0.096182] CPU: Testing write buffer coherency: ok
563 20:53:47.009457 <6>[ 0.101551] CPU0: Spectre v2: using BPIALL workaround
564 20:53:47.009733 <6>[ 0.107018] pid_max: default: 32768 minimum: 301
565 20:53:47.020956 <6>[ 0.112218] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 20:53:47.027830 <6>[ 0.120039] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 20:53:47.034831 <6>[ 0.129346] CPU0: thread -1, cpu 0, socket -1, mpidr 0
568 20:53:47.043201 <6>[ 0.136203] Setting up static identity map for 0x80300000 - 0x803000ac
569 20:53:47.048954 <6>[ 0.145802] rcu: Hierarchical SRCU implementation.
570 20:53:47.056656 <6>[ 0.151080] rcu: Max phase no-delay instances is 1000.
571 20:53:47.065096 <6>[ 0.162201] EFI services will not be available.
572 20:53:47.070954 <6>[ 0.167454] smp: Bringing up secondary CPUs ...
573 20:53:47.076723 <6>[ 0.172497] smp: Brought up 1 node, 1 CPU
574 20:53:47.082457 <6>[ 0.176895] SMP: Total of 1 processors activated (996.14 BogoMIPS).
575 20:53:47.088470 <6>[ 0.183648] CPU: All CPU(s) started in SVC mode.
576 20:53:47.108648 <6>[ 0.188830] Memory: 407008K/522240K available (16384K kernel code, 2545K rwdata, 6752K rodata, 2048K init, 432K bss, 48044K reserved, 65536K cma-reserved, 0K highmem)
577 20:53:47.108937 <6>[ 0.205092] devtmpfs: initialized
578 20:53:47.130828 <6>[ 0.222086] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
579 20:53:47.142326 <6>[ 0.230665] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
580 20:53:47.148263 <6>[ 0.241106] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
581 20:53:47.159043 <6>[ 0.253492] pinctrl core: initialized pinctrl subsystem
582 20:53:47.168504 <6>[ 0.264179] DMI not present or invalid.
583 20:53:47.176651 <6>[ 0.269995] NET: Registered PF_NETLINK/PF_ROUTE protocol family
584 20:53:47.186122 <6>[ 0.278884] DMA: preallocated 256 KiB pool for atomic coherent allocations
585 20:53:47.201252 <6>[ 0.290503] thermal_sys: Registered thermal governor 'step_wise'
586 20:53:47.201527 <6>[ 0.290653] cpuidle: using governor menu
587 20:53:47.229340 <6>[ 0.326690] No ATAGs?
588 20:53:47.235531 <6>[ 0.329334] hw-breakpoint: debug architecture 0x4 unsupported.
589 20:53:47.245640 <6>[ 0.341331] Serial: AMBA PL011 UART driver
590 20:53:47.285468 <6>[ 0.382853] iommu: Default domain type: Translated
591 20:53:47.294618 <6>[ 0.388085] iommu: DMA domain TLB invalidation policy: strict mode
592 20:53:47.304516 <5>[ 0.400544] SCSI subsystem initialized
593 20:53:47.328814 <6>[ 0.420539] usbcore: registered new interface driver usbfs
594 20:53:47.335712 <6>[ 0.426496] usbcore: registered new interface driver hub
595 20:53:47.335989 <6>[ 0.432335] usbcore: registered new device driver usb
596 20:53:47.341589 <6>[ 0.438826] pps_core: LinuxPPS API ver. 1 registered
597 20:53:47.352967 <6>[ 0.444263] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
598 20:53:47.361745 <6>[ 0.453966] PTP clock support registered
599 20:53:47.362021 <6>[ 0.458411] EDAC MC: Ver: 3.0.0
600 20:53:47.384893 <6>[ 0.479699] scmi_core: SCMI protocol bus registered
601 20:53:47.410835 <6>[ 0.507473] vgaarb: loaded
602 20:53:47.416893 <6>[ 0.511345] clocksource: Switched to clocksource dmtimer
603 20:53:47.459489 <6>[ 0.556481] NET: Registered PF_INET protocol family
604 20:53:47.471940 <6>[ 0.562147] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
605 20:53:47.477813 <6>[ 0.570960] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
606 20:53:47.489189 <6>[ 0.579884] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
607 20:53:47.495067 <6>[ 0.588144] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
608 20:53:47.506561 <6>[ 0.596430] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
609 20:53:47.512441 <6>[ 0.604143] TCP: Hash tables configured (established 4096 bind 4096)
610 20:53:47.518206 <6>[ 0.611049] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
611 20:53:47.524065 <6>[ 0.618088] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
612 20:53:47.531661 <6>[ 0.625694] NET: Registered PF_UNIX/PF_LOCAL protocol family
613 20:53:47.577692 <6>[ 0.669308] RPC: Registered named UNIX socket transport module.
614 20:53:47.577973 <6>[ 0.675758] RPC: Registered udp transport module.
615 20:53:47.583437 <6>[ 0.680866] RPC: Registered tcp transport module.
616 20:53:47.589157 <6>[ 0.685986] RPC: Registered tcp-with-tls transport module.
617 20:53:47.602184 <6>[ 0.691909] RPC: Registered tcp NFSv4.1 backchannel transport module.
618 20:53:47.602464 <6>[ 0.698814] PCI: CLS 0 bytes, default 64
619 20:53:47.609383 <5>[ 0.704609] Initialise system trusted keyrings
620 20:53:47.625178 <6>[ 0.719475] Trying to unpack rootfs image as initramfs...
621 20:53:47.659382 <6>[ 0.750403] workingset: timestamp_bits=30 max_order=17 bucket_order=0
622 20:53:47.664022 <6>[ 0.757939] squashfs: version 4.0 (2009/01/31) Phillip Lougher
623 20:53:47.719410 <5>[ 0.816552] NFS: Registering the id_resolver key type
624 20:53:47.725079 <5>[ 0.822276] Key type id_resolver registered
625 20:53:47.730957 <5>[ 0.826855] Key type id_legacy registered
626 20:53:47.736581 <6>[ 0.831284] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
627 20:53:47.746231 <6>[ 0.838493] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
628 20:53:47.774449 <5>[ 0.871864] Key type asymmetric registered
629 20:53:47.780434 <5>[ 0.876389] Asymmetric key parser 'x509' registered
630 20:53:47.791932 <6>[ 0.881934] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
631 20:53:47.792224 <6>[ 0.889821] io scheduler mq-deadline registered
632 20:53:47.797809 <6>[ 0.894809] io scheduler kyber registered
633 20:53:47.803362 <6>[ 0.899265] io scheduler bfq registered
634 20:53:48.161466 <6>[ 1.254830] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
635 20:53:48.182165 <6>[ 1.279155] msm_serial: driver initialized
636 20:53:48.188025 <6>[ 1.284130] SuperH (H)SCI(F) driver initialized
637 20:53:48.194024 <6>[ 1.289241] STMicroelectronics ASC driver initialized
638 20:53:48.199202 <6>[ 1.294915] STM32 USART driver initialized
639 20:53:48.307340 <6>[ 1.404078] brd: module loaded
640 20:53:48.332239 <6>[ 1.428691] loop: module loaded
641 20:53:48.382499 <6>[ 1.479059] CAN device driver interface
642 20:53:48.389163 <6>[ 1.484280] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
643 20:53:48.394891 <6>[ 1.491192] e1000e: Intel(R) PRO/1000 Network Driver
644 20:53:48.400766 <6>[ 1.496645] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
645 20:53:48.406625 <6>[ 1.503093] igb: Intel(R) Gigabit Ethernet Network Driver
646 20:53:48.414695 <6>[ 1.508915] igb: Copyright (c) 2007-2014 Intel Corporation.
647 20:53:48.426529 <6>[ 1.518141] pegasus: Pegasus/Pegasus II USB Ethernet driver
648 20:53:48.432295 <6>[ 1.524298] usbcore: registered new interface driver pegasus
649 20:53:48.438032 <6>[ 1.530424] usbcore: registered new interface driver asix
650 20:53:48.443932 <6>[ 1.536319] usbcore: registered new interface driver ax88179_178a
651 20:53:48.449664 <6>[ 1.542914] usbcore: registered new interface driver cdc_ether
652 20:53:48.455414 <6>[ 1.549212] usbcore: registered new interface driver smsc75xx
653 20:53:48.461289 <6>[ 1.555460] usbcore: registered new interface driver smsc95xx
654 20:53:48.467042 <6>[ 1.561693] usbcore: registered new interface driver net1080
655 20:53:48.472799 <6>[ 1.567813] usbcore: registered new interface driver cdc_subset
656 20:53:48.478543 <6>[ 1.574222] usbcore: registered new interface driver zaurus
657 20:53:48.486217 <6>[ 1.580270] usbcore: registered new interface driver cdc_ncm
658 20:53:48.496155 <6>[ 1.589809] usbcore: registered new interface driver usb-storage
659 20:53:48.618613 <6>[ 1.714136] i2c_dev: i2c /dev entries driver
660 20:53:48.669166 <5>[ 1.758482] cpuidle: enable-method property 'ti,am3352' found operations
661 20:53:48.675033 <6>[ 1.768131] sdhci: Secure Digital Host Controller Interface driver
662 20:53:48.682532 <6>[ 1.774906] sdhci: Copyright(c) Pierre Ossman
663 20:53:48.689780 <6>[ 1.781432] Synopsys Designware Multimedia Card Interface Driver
664 20:53:48.695205 <6>[ 1.789336] sdhci-pltfm: SDHCI platform and OF driver helper
665 20:53:48.761207 <6>[ 1.854869] ledtrig-cpu: registered to indicate activity on CPUs
666 20:53:48.792832 <6>[ 1.882760] usbcore: registered new interface driver usbhid
667 20:53:48.793112 <6>[ 1.888802] usbhid: USB HID core driver
668 20:53:48.842462 <6>[ 1.937205] NET: Registered PF_INET6 protocol family
669 20:53:48.895289 <6>[ 1.992621] Segment Routing with IPv6
670 20:53:48.901024 <6>[ 1.996773] In-situ OAM (IOAM) with IPv6
671 20:53:48.907770 <6>[ 2.001160] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
672 20:53:48.913518 <6>[ 2.008495] NET: Registered PF_PACKET protocol family
673 20:53:48.919399 <6>[ 2.014061] can: controller area network core
674 20:53:48.925266 <6>[ 2.018885] NET: Registered PF_CAN protocol family
675 20:53:48.925640 <6>[ 2.024114] can: raw protocol
676 20:53:48.930987 <6>[ 2.027437] can: broadcast manager protocol
677 20:53:48.937400 <6>[ 2.032031] can: netlink gateway - max_hops=1
678 20:53:48.943521 <5>[ 2.037509] Key type dns_resolver registered
679 20:53:48.949899 <6>[ 2.042582] ThumbEE CPU extension supported.
680 20:53:48.950169 <5>[ 2.047276] Registering SWP/SWPB emulation handler
681 20:53:48.959570 <3>[ 2.052976] omap_voltage_late_init: Voltage driver support not added
682 20:53:49.016908 <5>[ 2.111857] Loading compiled-in X.509 certificates
683 20:53:49.195640 <6>[ 2.280026] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
684 20:53:49.202815 <6>[ 2.296689] pinctrl-single 44e10800.pinmux: 142 pins, size 568
685 20:53:49.229136 <3>[ 2.320373] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
686 20:53:49.319571 <3>[ 2.410891] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
687 20:53:49.406496 <6>[ 2.502190] OMAP GPIO hardware version 0.1
688 20:53:49.427248 <6>[ 2.520816] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
689 20:53:49.490180 <4>[ 2.583536] at24 2-0054: supply vcc not found, using dummy regulator
690 20:53:49.542059 <4>[ 2.635465] at24 2-0055: supply vcc not found, using dummy regulator
691 20:53:49.580999 <4>[ 2.674333] at24 2-0056: supply vcc not found, using dummy regulator
692 20:53:49.631668 <4>[ 2.725029] at24 2-0057: supply vcc not found, using dummy regulator
693 20:53:49.679570 <6>[ 2.773780] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
694 20:53:49.757553 <3>[ 2.847707] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
695 20:53:49.782054 <6>[ 2.868595] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
696 20:53:49.803021 <4>[ 2.895239] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
697 20:53:49.849892 <4>[ 2.942101] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
698 20:53:49.908375 <6>[ 3.001910] omap_rng 48310000.rng: Random Number Generator ver. 20
699 20:53:49.931741 <5>[ 3.028013] random: crng init done
700 20:53:50.013455 <6>[ 3.105467] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
701 20:53:50.700174 <6>[ 3.795936] Freeing initrd memory: 14460K
702 20:53:50.752444 <6>[ 3.843745] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
703 20:53:50.758316 <4>[ 3.854040] ------------[ cut here ]------------
704 20:53:50.769834 <4>[ 3.859070] WARNING: CPU: 0 PID: 38 at drivers/base/regmap/regmap.c:1208 devm_regmap_field_alloc+0xb8/0xc4
705 20:53:50.775588 <4>[ 3.869363] invalid empty mask defined
706 20:53:50.775878 <4>[ 3.873518] Modules linked in:
707 20:53:50.781314 <4>[ 3.876946] CPU: 0 UID: 0 PID: 38 Comm: kworker/u4:4 Not tainted 6.11.0 #1
708 20:53:50.792781 <4>[ 3.884289] Hardware name: Generic AM33XX (Flattened Device Tree)
709 20:53:50.798590 <4>[ 3.890825] Workqueue: events_unbound deferred_probe_work_func
710 20:53:50.798869 <4>[ 3.897106] Call trace:
711 20:53:50.804341 <4>[ 3.897125] unwind_backtrace from show_stack+0x10/0x14
712 20:53:50.810090 <4>[ 3.905660] show_stack from dump_stack_lvl+0x68/0x74
713 20:53:50.815841 <4>[ 3.911146] dump_stack_lvl from __warn+0x7c/0x12c
714 20:53:50.821589 <4>[ 3.916362] __warn from warn_slowpath_fmt+0x124/0x190
715 20:53:50.827338 <4>[ 3.921927] warn_slowpath_fmt from devm_regmap_field_alloc+0xb8/0xc4
716 20:53:50.833127 <4>[ 3.928834] devm_regmap_field_alloc from cpsw_ale_create+0x124/0x368
717 20:53:50.838860 <4>[ 3.935755] cpsw_ale_create from cpsw_init_common+0x238/0x37c
718 20:53:50.844628 <4>[ 3.942041] cpsw_init_common from cpsw_probe+0x530/0xc60
719 20:53:50.850359 <4>[ 3.947878] cpsw_probe from platform_probe+0x5c/0xb0
720 20:53:50.856108 <4>[ 3.953359] platform_probe from really_probe+0xc8/0x2c8
721 20:53:50.867481 <4>[ 3.959101] really_probe from __driver_probe_device+0x88/0x19c
722 20:53:50.873361 <4>[ 3.965465] __driver_probe_device from driver_probe_device+0x30/0x104
723 20:53:50.878983 <4>[ 3.972457] driver_probe_device from __device_attach_driver+0x94/0x108
724 20:53:50.884732 <4>[ 3.979539] __device_attach_driver from bus_for_each_drv+0x90/0xe4
725 20:53:50.890485 <4>[ 3.986260] bus_for_each_drv from __device_attach+0xa8/0x1a4
726 20:53:50.896246 <4>[ 3.992443] __device_attach from bus_probe_device+0x88/0x8c
727 20:53:50.901984 <4>[ 3.998538] bus_probe_device from device_add+0x5a8/0x77c
728 20:53:50.913484 <4>[ 4.004365] device_add from of_platform_device_create_pdata+0x90/0xbc
729 20:53:50.919233 <4>[ 4.011369] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
730 20:53:50.925000 <4>[ 4.019620] of_platform_bus_create from of_platform_populate+0x70/0xd4
731 20:53:50.930717 <4>[ 4.026707] of_platform_populate from sysc_probe+0x100c/0x1418
732 20:53:50.936603 <4>[ 4.033090] sysc_probe from platform_probe+0x5c/0xb0
733 20:53:50.942234 <4>[ 4.038566] platform_probe from really_probe+0xc8/0x2c8
734 20:53:50.947856 <4>[ 4.044308] really_probe from __driver_probe_device+0x88/0x19c
735 20:53:50.959352 <4>[ 4.050673] __driver_probe_device from driver_probe_device+0x30/0x104
736 20:53:50.965107 <4>[ 4.057664] driver_probe_device from __device_attach_driver+0x94/0x108
737 20:53:50.970857 <4>[ 4.064743] __device_attach_driver from bus_for_each_drv+0x90/0xe4
738 20:53:50.976602 <4>[ 4.071465] bus_for_each_drv from __device_attach+0xa8/0x1a4
739 20:53:50.982352 <4>[ 4.077650] __device_attach from bus_probe_device+0x88/0x8c
740 20:53:50.988103 <4>[ 4.083747] bus_probe_device from device_add+0x5a8/0x77c
741 20:53:50.993853 <4>[ 4.089572] device_add from of_platform_device_create_pdata+0x90/0xbc
742 20:53:51.005353 <4>[ 4.096566] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
743 20:53:51.010977 <4>[ 4.104815] of_platform_bus_create from of_platform_populate+0x70/0xd4
744 20:53:51.016726 <4>[ 4.111902] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
745 20:53:51.022475 <4>[ 4.118720] simple_pm_bus_probe from platform_probe+0x5c/0xb0
746 20:53:51.028374 <4>[ 4.125000] platform_probe from really_probe+0xc8/0x2c8
747 20:53:51.033980 <4>[ 4.130743] really_probe from __driver_probe_device+0x88/0x19c
748 20:53:51.045477 <4>[ 4.137107] __driver_probe_device from driver_probe_device+0x30/0x104
749 20:53:51.051230 <4>[ 4.144096] driver_probe_device from __device_attach_driver+0x94/0x108
750 20:53:51.056868 <4>[ 4.151177] __device_attach_driver from bus_for_each_drv+0x90/0xe4
751 20:53:51.062602 <4>[ 4.157898] bus_for_each_drv from __device_attach+0xa8/0x1a4
752 20:53:51.068361 <4>[ 4.164084] __device_attach from bus_probe_device+0x88/0x8c
753 20:53:51.074104 <4>[ 4.170181] bus_probe_device from device_add+0x5a8/0x77c
754 20:53:51.079851 <4>[ 4.176005] device_add from of_platform_device_create_pdata+0x90/0xbc
755 20:53:51.091338 <4>[ 4.182997] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
756 20:53:51.097087 <4>[ 4.191247] of_platform_bus_create from of_platform_populate+0x70/0xd4
757 20:53:51.102822 <4>[ 4.198332] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
758 20:53:51.108566 <4>[ 4.205146] simple_pm_bus_probe from platform_probe+0x5c/0xb0
759 20:53:51.114330 <4>[ 4.211426] platform_probe from really_probe+0xc8/0x2c8
760 20:53:51.125685 <4>[ 4.217167] really_probe from __driver_probe_device+0x88/0x19c
761 20:53:51.131452 <4>[ 4.223530] __driver_probe_device from driver_probe_device+0x30/0x104
762 20:53:51.137315 <4>[ 4.230521] driver_probe_device from __device_attach_driver+0x94/0x108
763 20:53:51.142939 <4>[ 4.237603] __device_attach_driver from bus_for_each_drv+0x90/0xe4
764 20:53:51.148708 <4>[ 4.244327] bus_for_each_drv from __device_attach+0xa8/0x1a4
765 20:53:51.154456 <4>[ 4.250511] __device_attach from bus_probe_device+0x88/0x8c
766 20:53:51.160190 <4>[ 4.256609] bus_probe_device from device_add+0x5a8/0x77c
767 20:53:51.171563 <4>[ 4.262435] device_add from of_platform_device_create_pdata+0x90/0xbc
768 20:53:51.177436 <4>[ 4.269427] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
769 20:53:51.183060 <4>[ 4.277675] of_platform_bus_create from of_platform_populate+0x70/0xd4
770 20:53:51.188829 <4>[ 4.284763] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
771 20:53:51.194559 <4>[ 4.291580] simple_pm_bus_probe from platform_probe+0x5c/0xb0
772 20:53:51.200327 <4>[ 4.297859] platform_probe from really_probe+0xc8/0x2c8
773 20:53:51.211812 <4>[ 4.303601] really_probe from __driver_probe_device+0x88/0x19c
774 20:53:51.217561 <4>[ 4.309966] __driver_probe_device from driver_probe_device+0x30/0x104
775 20:53:51.223325 <4>[ 4.316956] driver_probe_device from __device_attach_driver+0x94/0x108
776 20:53:51.229059 <4>[ 4.324036] __device_attach_driver from bus_for_each_drv+0x90/0xe4
777 20:53:51.234810 <4>[ 4.330759] bus_for_each_drv from __device_attach+0xa8/0x1a4
778 20:53:51.240464 <4>[ 4.336944] __device_attach from bus_probe_device+0x88/0x8c
779 20:53:51.251933 <4>[ 4.343040] bus_probe_device from deferred_probe_work_func+0x78/0xa4
780 20:53:51.257707 <4>[ 4.349941] deferred_probe_work_func from process_one_work+0x178/0x3c0
781 20:53:51.263437 <4>[ 4.357037] process_one_work from worker_thread+0x264/0x42c
782 20:53:51.269314 <4>[ 4.363143] worker_thread from kthread+0xe0/0xfc
783 20:53:51.274937 <4>[ 4.368274] kthread from ret_from_fork+0x14/0x28
784 20:53:51.280716 <4>[ 4.373390] Exception stack(0xe0131fb0 to 0xe0131ff8)
785 20:53:51.286438 <4>[ 4.378856] 1fa0: 00000000 00000000 00000000 00000000
786 20:53:51.297807 <4>[ 4.387540] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
787 20:53:51.303681 <4>[ 4.396220] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
788 20:53:51.309558 <4>[ 4.403418] ---[ end trace 0000000000000000 ]---
789 20:53:51.310177 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
790 20:53:51.310435 login-action: kernel 'warning'
791 20:53:51.310677 [login-action] Waiting for messages, (timeout 00:04:07)
792 20:53:51.315307 <6>[ 4.408515] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
793 20:53:51.321686 <6>[ 4.415804] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
794 20:53:51.333181 <6>[ 4.423529] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
795 20:53:51.344708 <6>[ 4.431681] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
796 20:53:51.352214 <6>[ 4.443319] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
797 20:53:51.362730 <5>[ 4.452439] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
798 20:53:51.390324 <3>[ 4.482192] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
799 20:53:51.396124 <6>[ 4.490667] edma 49000000.dma: TI EDMA DMA engine driver
800 20:53:51.467231 <3>[ 4.558282] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
801 20:53:51.481980 <6>[ 4.572705] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
802 20:53:51.500617 <3>[ 4.595528] l3-aon-clkctrl:0000:0: failed to disable
803 20:53:51.551305 <6>[ 4.642900] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
804 20:53:51.556820 <6>[ 4.652366] printk: legacy console [ttyS0] enabled
805 20:53:51.562547 <6>[ 4.652366] printk: legacy console [ttyS0] enabled
806 20:53:51.568333 <6>[ 4.662681] printk: legacy bootconsole [omap8250] disabled
807 20:53:51.574025 <6>[ 4.662681] printk: legacy bootconsole [omap8250] disabled
808 20:53:51.601443 <4>[ 4.692126] tps65217-pmic: Failed to locate of_node [id: -1]
809 20:53:51.605030 <4>[ 4.699512] tps65217-bl: Failed to locate of_node [id: -1]
810 20:53:51.621152 <6>[ 4.718908] tps65217 0-0024: TPS65217 ID 0xe version 1.2
811 20:53:51.639670 <6>[ 4.725888] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
812 20:53:51.651421 <6>[ 4.739569] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
813 20:53:51.657013 <6>[ 4.751479] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
814 20:53:51.679671 <6>[ 4.771769] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
815 20:53:51.685550 <6>[ 4.780824] sdhci-omap 48060000.mmc: Got CD GPIO
816 20:53:51.693616 <4>[ 4.786016] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
817 20:53:51.708321 <4>[ 4.799408] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
818 20:53:51.714968 <4>[ 4.808329] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
819 20:53:51.724703 <4>[ 4.817174] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
820 20:53:51.829412 <6>[ 4.922585] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
821 20:53:51.862272 <6>[ 4.954589] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
822 20:53:51.885616 <6>[ 4.976550] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
823 20:53:51.892284 <6>[ 4.985874] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
824 20:53:51.940459 <6>[ 5.028653] mmc1: new high speed MMC card at address 0001
825 20:53:51.940816 <6>[ 5.035964] mmcblk1: mmc1:0001 M62704 3.56 GiB
826 20:53:51.948262 <6>[ 5.044425] mmcblk1: p1
827 20:53:51.953644 <6>[ 5.048862] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
828 20:53:51.962437 <6>[ 5.057176] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
829 20:53:51.974630 <6>[ 5.065207] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
830 20:53:51.983322 <6>[ 5.072864] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
831 20:53:55.110429 <6>[ 8.202317] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
832 20:53:55.183786 <5>[ 8.241411] Sending DHCP requests ., OK
833 20:53:55.195220 <6>[ 8.285835] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.7
834 20:53:55.195502 <6>[ 8.294066] IP-Config: Complete:
835 20:53:55.206466 <6>[ 8.297605] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.7, mask=255.255.255.0, gw=192.168.11.1
836 20:53:55.212256 <6>[ 8.308230] host=192.168.11.7, domain=usen.ad.jp, nis-domain=(none)
837 20:53:55.224602 <6>[ 8.315314] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
838 20:53:55.224873 <6>[ 8.315348] nameserver0=192.168.11.1
839 20:53:55.230693 <6>[ 8.327632] clk: Disabling unused clocks
840 20:53:55.237292 <6>[ 8.332348] PM: genpd: Disabling unused power domains
841 20:53:55.256270 <6>[ 8.350313] Freeing unused kernel image (initmem) memory: 2048K
842 20:53:55.263530 <6>[ 8.359942] Run /init as init process
843 20:53:55.286255 Loading, please wait...
844 20:53:55.360621 Starting systemd-udevd version 252.22-1~deb12u1
845 20:53:58.369095 <4>[ 11.459503] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
846 20:53:58.532064 <4>[ 11.622545] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
847 20:53:58.632527 <6>[ 11.730641] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
848 20:53:58.643643 <6>[ 11.736549] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
849 20:53:58.845357 <6>[ 11.941947] hub 1-0:1.0: USB hub found
850 20:53:58.859354 <6>[ 11.955721] hub 1-0:1.0: 1 port detected
851 20:53:59.117775 <6>[ 12.213951] tda998x 0-0070: found TDA19988
852 20:54:01.867120 Begin: Loading essential drivers ... done.
853 20:54:01.872757 Begin: Running /scripts/init-premount ... done.
854 20:54:01.878182 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
855 20:54:01.894129 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
856 20:54:01.894402 Device /sys/class/net/eth0 found
857 20:54:01.894622 done.
858 20:54:01.954911 Begin: Waiting up to 180 secs for any network device to become available ... done.
859 20:54:02.038937 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
860 20:54:02.039285 IP-Config: eth0 guessed broadcast address 192.168.11.255
861 20:54:02.044583 IP-Config: eth0 complete (dhcp from 192.168.11.1):
862 20:54:02.055803 address: 192.168.11.7 broadcast: 192.168.11.255 netmask: 255.255.255.0
863 20:54:02.061428 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
864 20:54:02.067050 domain : usen.ad.jp
865 20:54:02.071989 rootserver: 192.168.11.1 rootpath:
866 20:54:02.072273 filename :
867 20:54:02.144540 done.
868 20:54:02.156266 Begin: Running /scripts/nfs-bottom ... done.
869 20:54:02.234662 Begin: Running /scripts/init-bottom ... done.
870 20:54:03.372068 <30>[ 16.465779] systemd[1]: System time before build time, advancing clock.
871 20:54:03.576106 <30>[ 16.643629] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
872 20:54:03.585072 <30>[ 16.680720] systemd[1]: Detected architecture arm.
873 20:54:03.596954
874 20:54:03.597231 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
875 20:54:03.597458
876 20:54:03.627185 <30>[ 16.721536] systemd[1]: Hostname set to <debian-bookworm-armhf>.
877 20:54:05.779227 <30>[ 18.872646] systemd[1]: Queued start job for default target graphical.target.
878 20:54:05.796171 <30>[ 18.887431] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
879 20:54:05.803764 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
880 20:54:05.833856 <30>[ 18.924143] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
881 20:54:05.841138 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
882 20:54:05.865978 <30>[ 18.957658] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
883 20:54:05.878976 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
884 20:54:05.901203 <30>[ 18.993202] systemd[1]: Created slice user.slice - User and Session Slice.
885 20:54:05.907879 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
886 20:54:05.936857 <30>[ 19.022698] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
887 20:54:05.942877 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
888 20:54:05.960583 <30>[ 19.052444] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
889 20:54:05.969651 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
890 20:54:06.001573 <30>[ 19.082434] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
891 20:54:06.008081 <30>[ 19.102917] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
892 20:54:06.016524 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
893 20:54:06.039797 <30>[ 19.131875] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
894 20:54:06.048146 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
895 20:54:06.070448 <30>[ 19.162162] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
896 20:54:06.079004 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
897 20:54:06.100454 <30>[ 19.192349] systemd[1]: Reached target paths.target - Path Units.
898 20:54:06.105487 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
899 20:54:06.130147 <30>[ 19.222029] systemd[1]: Reached target remote-fs.target - Remote File Systems.
900 20:54:06.137392 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
901 20:54:06.159951 <30>[ 19.251870] systemd[1]: Reached target slices.target - Slice Units.
902 20:54:06.165383 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
903 20:54:06.190190 <30>[ 19.282113] systemd[1]: Reached target swap.target - Swaps.
904 20:54:06.194182 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
905 20:54:06.220386 <30>[ 19.312107] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
906 20:54:06.229242 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
907 20:54:06.251223 <30>[ 19.342883] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
908 20:54:06.259602 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
909 20:54:06.338436 <30>[ 19.425256] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
910 20:54:06.351222 <30>[ 19.442972] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
911 20:54:06.359645 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
912 20:54:06.383223 <30>[ 19.474076] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
913 20:54:06.390631 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
914 20:54:06.412850 <30>[ 19.504490] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
915 20:54:06.420925 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
916 20:54:06.445096 <30>[ 19.536309] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
917 20:54:06.450721 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
918 20:54:06.482593 <30>[ 19.573083] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
919 20:54:06.490152 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
920 20:54:06.517394 <30>[ 19.603187] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
921 20:54:06.536050 <30>[ 19.621731] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
922 20:54:06.583142 <30>[ 19.675691] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
923 20:54:06.602875 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
924 20:54:06.662046 <30>[ 19.754402] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
925 20:54:06.679300 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
926 20:54:06.763260 <30>[ 19.854788] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
927 20:54:06.780789 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
928 20:54:06.808861 <30>[ 19.901003] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
929 20:54:06.830249 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
930 20:54:06.872150 <30>[ 19.964785] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
931 20:54:06.890769 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
932 20:54:06.940509 <30>[ 20.032594] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
933 20:54:06.947451 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
934 20:54:06.989490 <30>[ 20.081228] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
935 20:54:07.019052 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
936 20:54:07.072946 <30>[ 20.165813] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
937 20:54:07.092467 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
938 20:54:07.117472 <30>[ 20.210355] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
939 20:54:07.139438 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
940 20:54:07.156013 <28>[ 20.243775] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
941 20:54:07.175126 <28>[ 20.267212] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
942 20:54:07.220373 <30>[ 20.312419] systemd[1]: Starting systemd-journald.service - Journal Service...
943 20:54:07.226766 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
944 20:54:07.273015 <30>[ 20.365633] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
945 20:54:07.290667 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
946 20:54:07.342270 <30>[ 20.435090] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
947 20:54:07.400514 Starting [0;1;39msystemd-network-g… units from Kernel command line...
948 20:54:07.453085 <30>[ 20.544347] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
949 20:54:07.498961 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
950 20:54:07.542449 <30>[ 20.634600] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
951 20:54:07.601036 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
952 20:54:07.661792 <30>[ 20.754850] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
953 20:54:07.722368 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
954 20:54:07.728785 <30>[ 20.823520] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
955 20:54:07.771380 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
956 20:54:07.803131 <30>[ 20.895002] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
957 20:54:07.849379 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
958 20:54:07.972360 <30>[ 21.066006] systemd[1]: modprobe@configfs.service: Deactivated successfully.
959 20:54:08.010799 <30>[ 21.103159] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
960 20:54:08.039788 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
961 20:54:08.060430 <30>[ 21.154107] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
962 20:54:08.089868 <30>[ 21.181973] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
963 20:54:08.098280 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
964 20:54:08.130337 <30>[ 21.224232] systemd[1]: modprobe@drm.service: Deactivated successfully.
965 20:54:08.159987 <30>[ 21.253145] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
966 20:54:08.188669 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
967 20:54:08.210790 <30>[ 21.304177] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
968 20:54:08.239903 <30>[ 21.331911] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
969 20:54:08.269024 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
970 20:54:08.290838 <30>[ 21.382951] systemd[1]: Started systemd-journald.service - Journal Service.
971 20:54:08.297832 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
972 20:54:08.330391 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
973 20:54:08.361895 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
974 20:54:08.390041 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
975 20:54:08.412149 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
976 20:54:08.432357 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
977 20:54:08.459974 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
978 20:54:08.519434 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
979 20:54:08.553290 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
980 20:54:08.644530 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
981 20:54:08.734621 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
982 20:54:08.858929 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
983 20:54:08.910152 <46>[ 22.002995] systemd-journald[163]: Received client request to flush runtime journal.
984 20:54:08.968389 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
985 20:54:09.109925 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
986 20:54:09.220089 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
987 20:54:10.128753 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
988 20:54:10.181285 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
989 20:54:10.749909 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
990 20:54:10.881801 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
991 20:54:10.901653 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
992 20:54:10.929648 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
993 20:54:11.000008 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
994 20:54:11.049215 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
995 20:54:11.962665 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
996 20:54:12.031770 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
997 20:54:12.307203 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
998 20:54:12.400008 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
999 20:54:12.460636 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1000 20:54:14.141786 <5>[ 27.234946] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1001 20:54:14.467910 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1002 20:54:14.938764 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1003 20:54:15.657989 <5>[ 28.753375] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1004 20:54:15.781167 <5>[ 28.871863] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1005 20:54:15.786682 <4>[ 28.881828] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1006 20:54:15.794464 <6>[ 28.890801] cfg80211: failed to load regulatory.db
1007 20:54:15.994498 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
1008 20:54:16.977668 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1009 20:54:16.993071 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1010 20:54:17.174653 <46>[ 30.257887] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1011 20:54:17.301651 <46>[ 30.388105] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
1012 20:54:25.933680 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1013 20:54:25.960433 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1014 20:54:25.979956 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1015 20:54:26.003966 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1016 20:54:26.085183 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1017 20:54:26.122438 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1018 20:54:26.181400 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1019 20:54:26.249184 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1020 20:54:26.306157 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1021 20:54:26.322575 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1022 20:54:26.364790 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1023 20:54:26.393582 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1024 20:54:26.433925 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1025 20:54:26.475931 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1026 20:54:26.509908 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1027 20:54:26.533186 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1028 20:54:26.571006 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1029 20:54:26.601554 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1030 20:54:26.621182 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1031 20:54:26.638550 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1032 20:54:26.676802 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1033 20:54:26.698549 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1034 20:54:26.720802 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1035 20:54:26.792548 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1036 20:54:26.828461 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1037 20:54:26.943689 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1038 20:54:27.051285 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1039 20:54:27.122566 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1040 20:54:27.179156 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1041 20:54:27.196257 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1042 20:54:27.390025 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1043 20:54:27.443420 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1044 20:54:27.502215 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1045 20:54:27.529717 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1046 20:54:27.601804 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1047 20:54:27.790902 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1048 20:54:28.076680 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1049 20:54:28.116352 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1050 20:54:28.140782 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1051 20:54:28.223487 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1052 20:54:28.379275 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1053 20:54:28.485450
1054 20:54:28.485814 Debian GNU/Linux worm-armhf login: root (automatic login)
1055 20:54:28.488533
1056 20:54:28.834649 Linux debian-bookworm-armhf 6.11.0 #1 SMP Thu Sep 19 08:53:27 UTC 2024 armv7l
1057 20:54:28.834932
1058 20:54:28.840273 The programs included with the Debian GNU/Linux system are free software;
1059 20:54:28.845897 the exact distribution terms for each program are described in the
1060 20:54:28.851387 individual files in /usr/share/doc/*/copyright.
1061 20:54:28.851680
1062 20:54:28.859091 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1063 20:54:28.859366 permitted by applicable law.
1064 20:54:33.469874 Matched prompt #10: / #
1066 20:54:33.471284 Kernel warnings or errors detected.
1067 20:54:33.471521 Setting prompt string to ['/ #']
1068 20:54:33.471818 end: 2.4.4.1 login-action (duration 00:00:47) [common]
1070 20:54:33.473114 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
1071 20:54:33.473425 start: 2.4.5 expect-shell-connection (timeout 00:03:24) [common]
1072 20:54:33.473667 Setting prompt string to ['/ #']
1073 20:54:33.473879 Forcing a shell prompt, looking for ['/ #']
1075 20:54:33.524436 / #
1076 20:54:33.524936 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1077 20:54:33.525196 Waiting using forced prompt support (timeout 00:02:30)
1078 20:54:33.529431
1079 20:54:33.535453 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1080 20:54:33.535794 start: 2.4.6 export-device-env (timeout 00:03:24) [common]
1081 20:54:33.536060 Sending with 10 millisecond of delay
1083 20:54:38.585088 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1193790/extract-nfsrootfs-m1ujbv4e'
1084 20:54:38.595664 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1193790/extract-nfsrootfs-m1ujbv4e'
1085 20:54:38.596174 Sending with 10 millisecond of delay
1087 20:54:40.754486 / # export NFS_SERVER_IP='192.168.11.5'
1088 20:54:40.765086 export NFS_SERVER_IP='192.168.11.5'
1089 20:54:40.765651 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1090 20:54:40.765968 end: 2.4 uboot-commands (duration 00:01:42) [common]
1091 20:54:40.766278 end: 2 uboot-action (duration 00:01:43) [common]
1092 20:54:40.766581 start: 3 lava-test-retry (timeout 00:07:24) [common]
1093 20:54:40.766891 start: 3.1 lava-test-shell (timeout 00:07:24) [common]
1094 20:54:40.767138 Using namespace: common
1096 20:54:40.867869 / # #
1097 20:54:40.868245 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1098 20:54:40.872596 #
1099 20:54:40.878271 Using /lava-1193790
1101 20:54:40.979051 / # export SHELL=/bin/bash
1102 20:54:40.983786 export SHELL=/bin/bash
1104 20:54:41.090118 / # . /lava-1193790/environment
1105 20:54:41.094961 . /lava-1193790/environment
1107 20:54:41.207274 / # /lava-1193790/bin/lava-test-runner /lava-1193790/0
1108 20:54:41.207756 Test shell timeout: 10s (minimum of the action and connection timeout)
1109 20:54:41.212101 /lava-1193790/bin/lava-test-runner /lava-1193790/0
1110 20:54:41.668072 + export TESTRUN_ID=0_timesync-off
1111 20:54:41.676096 + TESTRUN_ID=0_timesync-off
1112 20:54:41.676431 + cd /lava-1193790/0/tests/0_timesync-off
1113 20:54:41.676669 ++ cat uuid
1114 20:54:41.691977 + UUID=1193790_1.6.2.4.1
1115 20:54:41.692281 + set +x
1116 20:54:41.697579 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1193790_1.6.2.4.1>
1117 20:54:41.698091 Received signal: <STARTRUN> 0_timesync-off 1193790_1.6.2.4.1
1118 20:54:41.698335 Starting test lava.0_timesync-off (1193790_1.6.2.4.1)
1119 20:54:41.698616 Skipping test definition patterns.
1120 20:54:41.700807 + systemctl stop systemd-timesyncd
1121 20:54:41.989809 + set +x
1122 20:54:41.999844 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1193790_1.6.2.4.1>
1123 20:54:42.000334 Received signal: <ENDRUN> 0_timesync-off 1193790_1.6.2.4.1
1124 20:54:42.000605 Ending use of test pattern.
1125 20:54:42.000831 Ending test lava.0_timesync-off (1193790_1.6.2.4.1), duration 0.30
1127 20:54:42.179285 + export TESTRUN_ID=1_kselftest-dt
1128 20:54:42.187290 + TESTRUN_ID=1_kselftest-dt
1129 20:54:42.187571 + cd /lava-1193790/0/tests/1_kselftest-dt
1130 20:54:42.187843 ++ cat uuid
1131 20:54:42.204260 + UUID=1193790_1.6.2.4.5
1132 20:54:42.204541 + set +x
1133 20:54:42.209861 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1193790_1.6.2.4.5>
1134 20:54:42.210142 + cd ./automated/linux/kselftest/
1135 20:54:42.210589 Received signal: <STARTRUN> 1_kselftest-dt 1193790_1.6.2.4.5
1136 20:54:42.210822 Starting test lava.1_kselftest-dt (1193790_1.6.2.4.5)
1137 20:54:42.211097 Skipping test definition patterns.
1138 20:54:42.237903 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1139 20:54:42.346822 INFO: install_deps skipped
1140 20:54:42.962729 --2024-09-19 20:54:42-- http://storage.kernelci.org/mainline/master/v6.11-5778-g176000734ee29/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1141 20:54:42.972920 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1142 20:54:43.087645 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1143 20:54:43.202262 HTTP request sent, awaiting response... 200 OK
1144 20:54:43.202660 Length: 4076804 (3.9M) [application/octet-stream]
1145 20:54:43.207742 Saving to: 'kselftest_armhf.tar.gz'
1146 20:54:43.208017
1147 20:54:44.858923 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 1%[ ] 49.92K 223KB/s kselftest_armhf.tar 5%[> ] 218.67K 491KB/s kselftest_armhf.tar 16%[==> ] 674.29K 796KB/s kselftest_armhf.tar 56%[==========> ] 2.20M 2.04MB/s kselftest_armhf.tar 66%[============> ] 2.60M 2.01MB/s kselftest_armhf.tar 89%[================> ] 3.47M 2.26MB/s kselftest_armhf.tar 100%[===================>] 3.89M 2.36MB/s in 1.7s
1148 20:54:44.859297
1149 20:54:45.533189 2024-09-19 20:54:44 (2.36 MB/s) - 'kselftest_armhf.tar.gz' saved [4076804/4076804]
1150 20:54:45.533571
1151 20:55:06.974545 skiplist:
1152 20:55:06.974905 ========================================
1153 20:55:06.980113 ========================================
1154 20:55:07.081795 dt:test_unprobed_devices.sh
1155 20:55:07.113798 ============== Tests to run ===============
1156 20:55:07.122373 dt:test_unprobed_devices.sh
1157 20:55:07.126281 ===========End Tests to run ===============
1158 20:55:07.136833 shardfile-dt pass
1159 20:55:07.364428 <12>[ 80.463361] kselftest: Running tests in dt
1160 20:55:07.392416 TAP version 13
1161 20:55:07.420147 1..1
1162 20:55:07.476469 # timeout set to 45
1163 20:55:07.476752 # selftests: dt: test_unprobed_devices.sh
1164 20:55:08.312301 # TAP version 13
1165 20:55:33.188253 # 1..257
1166 20:55:33.385268 # ok 1 / # SKIP
1167 20:55:33.402649 # ok 2 /clk_mcasp0
1168 20:55:33.473457 # ok 3 /clk_mcasp0_fixed # SKIP
1169 20:55:33.542632 # ok 4 /cpus/cpu@0 # SKIP
1170 20:55:33.617399 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1171 20:55:33.637199 # ok 6 /fixedregulator0
1172 20:55:33.652962 # ok 7 /leds
1173 20:55:33.673921 # ok 8 /ocp
1174 20:55:33.697319 # ok 9 /ocp/interconnect@44c00000
1175 20:55:33.721265 # ok 10 /ocp/interconnect@44c00000/segment@0
1176 20:55:33.743448 # ok 11 /ocp/interconnect@44c00000/segment@100000
1177 20:55:33.772483 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1178 20:55:33.844019 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1179 20:55:33.864177 # ok 14 /ocp/interconnect@44c00000/segment@200000
1180 20:55:33.882272 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1181 20:55:33.992033 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1182 20:55:34.066986 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1183 20:55:34.131232 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1184 20:55:34.209123 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1185 20:55:34.273001 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1186 20:55:34.346914 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1187 20:55:34.422984 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1188 20:55:34.490952 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1189 20:55:34.564341 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1190 20:55:34.629984 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1191 20:55:34.700159 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1192 20:55:34.774801 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1193 20:55:34.837860 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1194 20:55:34.912574 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1195 20:55:34.984620 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1196 20:55:35.049312 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1197 20:55:35.126066 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1198 20:55:35.191074 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1199 20:55:35.268192 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1200 20:55:35.338813 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1201 20:55:35.402811 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1202 20:55:35.476841 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1203 20:55:35.554553 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1204 20:55:35.622299 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1205 20:55:35.696062 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1206 20:55:35.767554 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1207 20:55:35.840350 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1208 20:55:35.903924 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1209 20:55:35.980157 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1210 20:55:36.050285 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1211 20:55:36.125406 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1212 20:55:36.195793 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1213 20:55:36.266027 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1214 20:55:36.335900 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1215 20:55:36.402036 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1216 20:55:36.478520 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1217 20:55:36.545251 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1218 20:55:36.620150 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1219 20:55:36.691274 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1220 20:55:36.764869 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1221 20:55:36.836397 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1222 20:55:36.901154 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1223 20:55:36.975903 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1224 20:55:37.041762 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1225 20:55:37.117757 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1226 20:55:37.191398 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1227 20:55:37.265127 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1228 20:55:37.336510 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1229 20:55:37.408385 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1230 20:55:37.471978 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1231 20:55:37.552287 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1232 20:55:37.616755 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1233 20:55:37.689111 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1234 20:55:37.766995 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1235 20:55:37.838731 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1236 20:55:37.902855 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1237 20:55:37.979887 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1238 20:55:38.054726 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1239 20:55:38.128846 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1240 20:55:38.192489 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1241 20:55:38.270217 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1242 20:55:38.338232 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1243 20:55:38.414595 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1244 20:55:38.485175 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1245 20:55:38.557205 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1246 20:55:38.627496 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1247 20:55:38.693109 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1248 20:55:38.768707 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1249 20:55:38.837213 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1250 20:55:38.914194 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1251 20:55:38.983693 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1252 20:55:39.057438 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1253 20:55:39.121688 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1254 20:55:39.200706 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1255 20:55:39.275439 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1256 20:55:39.345035 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1257 20:55:39.417131 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1258 20:55:39.486762 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1259 20:55:39.553994 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1260 20:55:39.581488 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1261 20:55:39.596630 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1262 20:55:39.627261 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1263 20:55:39.648818 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1264 20:55:39.676126 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1265 20:55:39.695127 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1266 20:55:39.724015 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1267 20:55:39.749368 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1268 20:55:39.850675 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1269 20:55:39.876290 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1270 20:55:39.905172 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1271 20:55:39.924152 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1272 20:55:40.032643 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1273 20:55:40.107367 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1274 20:55:40.177860 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1275 20:55:40.244367 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1276 20:55:40.321008 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1277 20:55:40.392902 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1278 20:55:40.465014 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1279 20:55:40.537353 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1280 20:55:40.606983 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1281 20:55:40.681260 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1282 20:55:40.751609 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1283 20:55:40.819149 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1284 20:55:40.895093 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1285 20:55:40.959870 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1286 20:55:41.039656 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1287 20:55:41.103200 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1288 20:55:41.129370 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1289 20:55:41.196640 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1290 20:55:41.266661 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1291 20:55:41.332611 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1292 20:55:41.361860 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1293 20:55:41.423882 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1294 20:55:41.451747 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1295 20:55:41.522604 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1296 20:55:41.546144 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1297 20:55:41.563816 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1298 20:55:41.592976 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1299 20:55:41.610608 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1300 20:55:41.633851 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1301 20:55:41.660943 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1302 20:55:41.689107 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1303 20:55:41.753210 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1304 20:55:41.782411 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1305 20:55:41.805144 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1306 20:55:41.870372 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1307 20:55:41.947276 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1308 20:55:41.960456 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1309 20:55:42.060953 # not ok 144 /ocp/interconnect@47c00000
1310 20:55:42.132250 # not ok 145 /ocp/interconnect@47c00000/segment@0
1311 20:55:42.155531 # ok 146 /ocp/interconnect@48000000
1312 20:55:42.177394 # ok 147 /ocp/interconnect@48000000/segment@0
1313 20:55:42.202382 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1314 20:55:42.225923 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1315 20:55:42.248141 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1316 20:55:42.270647 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1317 20:55:42.295608 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1318 20:55:42.311302 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1319 20:55:42.342542 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1320 20:55:42.412107 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1321 20:55:42.482900 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1322 20:55:42.505590 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1323 20:55:42.523032 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1324 20:55:42.552162 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1325 20:55:42.573370 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1326 20:55:42.595911 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1327 20:55:42.614316 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1328 20:55:42.641014 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1329 20:55:42.666579 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1330 20:55:42.681054 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1331 20:55:42.711255 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1332 20:55:42.735071 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1333 20:55:42.754083 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1334 20:55:42.774394 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1335 20:55:42.805608 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1336 20:55:42.822837 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1337 20:55:42.850709 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1338 20:55:42.872598 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1339 20:55:42.895335 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1340 20:55:42.916084 # ok 175 /ocp/interconnect@48000000/segment@100000
1341 20:55:42.942895 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1342 20:55:42.965181 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1343 20:55:43.033534 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1344 20:55:43.114505 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1345 20:55:43.184167 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1346 20:55:43.249547 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1347 20:55:43.326009 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1348 20:55:43.396131 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1349 20:55:43.459264 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1350 20:55:43.538731 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1351 20:55:43.559797 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1352 20:55:43.582433 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1353 20:55:43.605626 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1354 20:55:43.621272 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1355 20:55:43.651995 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1356 20:55:43.674370 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1357 20:55:43.693746 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1358 20:55:43.722866 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1359 20:55:43.737012 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1360 20:55:43.765895 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1361 20:55:43.782261 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1362 20:55:43.807770 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1363 20:55:43.833203 # ok 198 /ocp/interconnect@48000000/segment@200000
1364 20:55:43.851357 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1365 20:55:43.924923 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1366 20:55:43.951581 # ok 201 /ocp/interconnect@48000000/segment@300000
1367 20:55:43.972511 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1368 20:55:43.993882 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1369 20:55:44.020753 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1370 20:55:44.045369 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1371 20:55:44.060500 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1372 20:55:44.089126 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1373 20:55:44.159713 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1374 20:55:44.179876 # ok 209 /ocp/interconnect@4a000000
1375 20:55:44.196236 # ok 210 /ocp/interconnect@4a000000/segment@0
1376 20:55:44.224236 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1377 20:55:44.250621 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1378 20:55:44.275121 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1379 20:55:44.295763 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1380 20:55:44.362493 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1381 20:55:44.472099 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1382 20:55:44.546575 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1383 20:55:44.646701 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1384 20:55:44.713468 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1385 20:55:44.789601 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1386 20:55:44.889508 # not ok 221 /ocp/interconnect@4b140000
1387 20:55:44.952595 # not ok 222 /ocp/interconnect@4b140000/segment@0
1388 20:55:45.030884 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1389 20:55:45.044355 # ok 224 /ocp/target-module@40300000
1390 20:55:45.070378 # ok 225 /ocp/target-module@40300000/sram@0
1391 20:55:45.143933 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1392 20:55:45.213307 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1393 20:55:45.236375 # ok 228 /ocp/target-module@47400000
1394 20:55:45.260132 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1395 20:55:45.281121 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1396 20:55:45.301532 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1397 20:55:45.322500 # ok 232 /ocp/target-module@47400000/usb@1400
1398 20:55:45.349746 # ok 233 /ocp/target-module@47400000/usb@1800
1399 20:55:45.369995 # ok 234 /ocp/target-module@47810000
1400 20:55:45.391170 # ok 235 /ocp/target-module@49000000
1401 20:55:45.410547 # ok 236 /ocp/target-module@49000000/dma@0
1402 20:55:45.436750 # ok 237 /ocp/target-module@49800000
1403 20:55:45.458999 # ok 238 /ocp/target-module@49800000/dma@0
1404 20:55:45.480011 # ok 239 /ocp/target-module@49900000
1405 20:55:45.500152 # ok 240 /ocp/target-module@49900000/dma@0
1406 20:55:45.521328 # ok 241 /ocp/target-module@49a00000
1407 20:55:45.543792 # ok 242 /ocp/target-module@49a00000/dma@0
1408 20:55:45.569253 # ok 243 /ocp/target-module@4c000000
1409 20:55:45.639539 # not ok 244 /ocp/target-module@4c000000/emif@0
1410 20:55:45.660024 # ok 245 /ocp/target-module@50000000
1411 20:55:45.680531 # ok 246 /ocp/target-module@53100000
1412 20:55:45.752487 # not ok 247 /ocp/target-module@53100000/sham@0
1413 20:55:45.772215 # ok 248 /ocp/target-module@53500000
1414 20:55:45.846899 # not ok 249 /ocp/target-module@53500000/aes@0
1415 20:55:45.867775 # ok 250 /ocp/target-module@56000000
1416 20:55:45.970985 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1417 20:55:46.034105 # ok 252 /opp-table # SKIP
1418 20:55:46.107687 # ok 253 /soc # SKIP
1419 20:55:46.124316 # ok 254 /sound
1420 20:55:46.147721 # ok 255 /target-module@4b000000
1421 20:55:46.172241 # ok 256 /target-module@4b000000/target-module@140000
1422 20:55:46.192921 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1423 20:55:46.200803 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1424 20:55:46.207791 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1425 20:55:48.389473 dt_test_unprobed_devices_sh_ skip
1426 20:55:48.395011 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1427 20:55:48.400670 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1428 20:55:48.401019 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1429 20:55:48.406282 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1430 20:55:48.411739 dt_test_unprobed_devices_sh_fixedregulator0 pass
1431 20:55:48.417368 dt_test_unprobed_devices_sh_leds pass
1432 20:55:48.417610 dt_test_unprobed_devices_sh_ocp pass
1433 20:55:48.422990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1434 20:55:48.428557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1435 20:55:48.434242 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1436 20:55:48.445380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1437 20:55:48.451041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1438 20:55:48.456659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1439 20:55:48.467736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1440 20:55:48.473360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1441 20:55:48.484659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1442 20:55:48.495890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1443 20:55:48.506990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1444 20:55:48.512645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1445 20:55:48.523865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1446 20:55:48.535172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1447 20:55:48.546391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1448 20:55:48.557509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1449 20:55:48.563169 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1450 20:55:48.574263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1451 20:55:48.585511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1452 20:55:48.596642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1453 20:55:48.607888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1454 20:55:48.613515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1455 20:55:48.624699 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1456 20:55:48.635887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1457 20:55:48.647031 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1458 20:55:48.652711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1459 20:55:48.663918 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1460 20:55:48.675043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1461 20:55:48.686293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1462 20:55:48.697404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1463 20:55:48.703041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1464 20:55:48.714288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1465 20:55:48.725415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1466 20:55:48.736666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1467 20:55:48.747787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1468 20:55:48.759043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1469 20:55:48.770456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1470 20:55:48.781448 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1471 20:55:48.792566 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1472 20:55:48.803792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1473 20:55:48.814913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1474 20:55:48.826167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1475 20:55:48.837411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1476 20:55:48.848559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1477 20:55:48.859788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1478 20:55:48.870929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1479 20:55:48.882159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1480 20:55:48.893283 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1481 20:55:48.904559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1482 20:55:48.915659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1483 20:55:48.926908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1484 20:55:48.938161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1485 20:55:48.949410 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1486 20:55:48.960679 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1487 20:55:48.971908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1488 20:55:48.983035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1489 20:55:48.988662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1490 20:55:48.999906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1491 20:55:49.011281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1492 20:55:49.022405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1493 20:55:49.033546 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1494 20:55:49.044800 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1495 20:55:49.055906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1496 20:55:49.067152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1497 20:55:49.078276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1498 20:55:49.089527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1499 20:55:49.100676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1500 20:55:49.111905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1501 20:55:49.123151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1502 20:55:49.134403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1503 20:55:49.145532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1504 20:55:49.156795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1505 20:55:49.168054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1506 20:55:49.179274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1507 20:55:49.184797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1508 20:55:49.196022 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1509 20:55:49.207275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1510 20:55:49.218401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1511 20:55:49.229542 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1512 20:55:49.235276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1513 20:55:49.252021 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1514 20:55:49.263291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1515 20:55:49.268785 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1516 20:55:49.285491 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1517 20:55:49.296753 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1518 20:55:49.307896 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1519 20:55:49.313524 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1520 20:55:49.324677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1521 20:55:49.335893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1522 20:55:49.341522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1523 20:55:49.352676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1524 20:55:49.363923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1525 20:55:49.369533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1526 20:55:49.380660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1527 20:55:49.386314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1528 20:55:49.397587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1529 20:55:49.408720 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1530 20:55:49.419919 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1531 20:55:49.431083 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1532 20:55:49.442334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1533 20:55:49.453472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1534 20:55:49.464748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1535 20:55:49.475827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1536 20:55:49.487072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1537 20:55:49.498323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1538 20:55:49.509447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1539 20:55:49.520717 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1540 20:55:49.537452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1541 20:55:49.548590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1542 20:55:49.559825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1543 20:55:49.570948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1544 20:55:49.582299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1545 20:55:49.598899 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1546 20:55:49.610143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1547 20:55:49.621455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1548 20:55:49.632579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1549 20:55:49.638199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1550 20:55:49.649452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1551 20:55:49.660698 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1552 20:55:49.666326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1553 20:55:49.677452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1554 20:55:49.683075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1555 20:55:49.694325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1556 20:55:49.699944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1557 20:55:49.711200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1558 20:55:49.716824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1559 20:55:49.727947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1560 20:55:49.733575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1561 20:55:49.744833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1562 20:55:49.755921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1563 20:55:49.767194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1564 20:55:49.778538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1565 20:55:49.789568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1566 20:55:49.795196 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1567 20:55:49.806321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1568 20:55:49.811941 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1569 20:55:49.817572 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1570 20:55:49.823188 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1571 20:55:49.828698 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1572 20:55:49.834323 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1573 20:55:49.845560 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1574 20:55:49.851192 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1575 20:55:49.856695 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1576 20:55:49.867941 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1577 20:55:49.873570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1578 20:55:49.884695 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1579 20:55:49.890319 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1580 20:55:49.901445 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1581 20:55:49.907067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1582 20:55:49.918318 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1583 20:55:49.923941 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1584 20:55:49.935067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1585 20:55:49.940727 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1586 20:55:49.951820 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1587 20:55:49.957444 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1588 20:55:49.968691 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1589 20:55:49.974317 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1590 20:55:49.979816 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1591 20:55:49.991062 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1592 20:55:49.996691 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1593 20:55:50.007810 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1594 20:55:50.013433 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1595 20:55:50.024574 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1596 20:55:50.030320 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1597 20:55:50.041438 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1598 20:55:50.046940 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1599 20:55:50.052564 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1600 20:55:50.063808 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1601 20:55:50.069437 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1602 20:55:50.080565 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1603 20:55:50.091822 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1604 20:55:50.102937 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1605 20:55:50.114184 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1606 20:55:50.125312 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1607 20:55:50.136597 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1608 20:55:50.147685 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1609 20:55:50.158931 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1610 20:55:50.164564 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1611 20:55:50.175690 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1612 20:55:50.181306 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1613 20:55:50.192421 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1614 20:55:50.198056 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1615 20:55:50.209308 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1616 20:55:50.214808 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1617 20:55:50.226057 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1618 20:55:50.231677 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1619 20:55:50.242809 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1620 20:55:50.248423 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1621 20:55:50.259683 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1622 20:55:50.265306 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1623 20:55:50.276425 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1624 20:55:50.282050 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1625 20:55:50.287557 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1626 20:55:50.298803 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1627 20:55:50.304423 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1628 20:55:50.315557 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1629 20:55:50.321307 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1630 20:55:50.332421 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1631 20:55:50.337929 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1632 20:55:50.349177 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1633 20:55:50.354798 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1634 20:55:50.360420 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1635 20:55:50.365931 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1636 20:55:50.377156 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1637 20:55:50.388262 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1638 20:55:50.393874 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1639 20:55:50.399499 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1640 20:55:50.410639 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1641 20:55:50.421922 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1642 20:55:50.432993 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1643 20:55:50.444383 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1644 20:55:50.449994 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1645 20:55:50.455619 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1646 20:55:50.461245 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1647 20:55:50.466870 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1648 20:55:50.472383 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1649 20:55:50.478009 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1650 20:55:50.489243 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1651 20:55:50.494866 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1652 20:55:50.500378 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1653 20:55:50.505991 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1654 20:55:50.511617 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1655 20:55:50.522866 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1656 20:55:50.528384 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1657 20:55:50.533990 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1658 20:55:50.539620 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1659 20:55:50.545251 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1660 20:55:50.550865 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1661 20:55:50.556365 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1662 20:55:50.561957 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1663 20:55:50.567586 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1664 20:55:50.573288 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1665 20:55:50.578834 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1666 20:55:50.584374 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1667 20:55:50.589986 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1668 20:55:50.595606 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1669 20:55:50.601211 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1670 20:55:50.606856 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1671 20:55:50.612606 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1672 20:55:50.618317 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1673 20:55:50.623752 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1674 20:55:50.629374 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1675 20:55:50.635000 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1676 20:55:50.635277 dt_test_unprobed_devices_sh_opp-table skip
1677 20:55:50.640573 dt_test_unprobed_devices_sh_soc skip
1678 20:55:50.646233 dt_test_unprobed_devices_sh_sound pass
1679 20:55:50.651867 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1680 20:55:50.657349 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1681 20:55:50.662991 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1682 20:55:50.668732 dt_test_unprobed_devices_sh fail
1683 20:55:50.669007 + ../../utils/send-to-lava.sh ./output/result.txt
1684 20:55:50.674354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1685 20:55:50.674972 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1687 20:55:50.683390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1688 20:55:50.683874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1690 20:55:50.766338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1691 20:55:50.766825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1693 20:55:50.861269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1694 20:55:50.861832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1696 20:55:50.954915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1697 20:55:50.955406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1699 20:55:51.052943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1700 20:55:51.053429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1702 20:55:51.151709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1703 20:55:51.152211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1705 20:55:51.245440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1706 20:55:51.245947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1708 20:55:51.341720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1709 20:55:51.342230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1711 20:55:51.437404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1712 20:55:51.437969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1714 20:55:51.532896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1715 20:55:51.533380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1717 20:55:51.625626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1718 20:55:51.626113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1720 20:55:51.719660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1721 20:55:51.720149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1723 20:55:51.810670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1724 20:55:51.811248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1726 20:55:51.904262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1727 20:55:51.904767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1729 20:55:52.002673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1730 20:55:52.003166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1732 20:55:52.097890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1733 20:55:52.098377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1735 20:55:52.193648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1736 20:55:52.194137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1738 20:55:52.290616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1739 20:55:52.291128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1741 20:55:52.385735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1742 20:55:52.386228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1744 20:55:52.481466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1745 20:55:52.482050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1747 20:55:52.575082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1748 20:55:52.575567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1750 20:55:52.668178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1751 20:55:52.668685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1753 20:55:52.763708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1754 20:55:52.764192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1756 20:55:52.856411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1757 20:55:52.856980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1759 20:55:52.955403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1760 20:55:52.955718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1762 20:55:53.048321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1763 20:55:53.048811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1765 20:55:53.143438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1766 20:55:53.143914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1768 20:55:53.237519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1769 20:55:53.237995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1771 20:55:53.334910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1772 20:55:53.335392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1774 20:55:53.428220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1775 20:55:53.428804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1777 20:55:53.524929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1778 20:55:53.525421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1780 20:55:53.617190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1781 20:55:53.617663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1783 20:55:53.712180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1784 20:55:53.712678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1786 20:55:53.802435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1787 20:55:53.802984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1789 20:55:53.898879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1790 20:55:53.899361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1792 20:55:53.991674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1793 20:55:53.992154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1795 20:55:54.088423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1796 20:55:54.088912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1798 20:55:54.181758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1799 20:55:54.182246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1801 20:55:54.281390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1802 20:55:54.281875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1804 20:55:54.375269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1805 20:55:54.375754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1807 20:55:54.468168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1808 20:55:54.468773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1810 20:55:54.565195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1811 20:55:54.565681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1813 20:55:54.658773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1814 20:55:54.659234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1816 20:55:54.754049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1817 20:55:54.754544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1819 20:55:54.849181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1820 20:55:54.849748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1822 20:55:54.946291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1823 20:55:54.946776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1825 20:55:55.041791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1826 20:55:55.042277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1828 20:55:55.136912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1829 20:55:55.137404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1831 20:55:55.235181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1832 20:55:55.235669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1834 20:55:55.329781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1835 20:55:55.330269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1837 20:55:55.425251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1838 20:55:55.425839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1840 20:55:55.518798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1841 20:55:55.519281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1843 20:55:55.614159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1844 20:55:55.614647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1846 20:55:55.710147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1847 20:55:55.710631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1849 20:55:55.803221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1850 20:55:55.803804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1852 20:55:55.899783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1853 20:55:55.900261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1855 20:55:55.995933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1856 20:55:55.996451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1858 20:55:56.092409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1859 20:55:56.092895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1861 20:55:56.186933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1862 20:55:56.187409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1864 20:55:56.282183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1865 20:55:56.282658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1867 20:55:56.376431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1868 20:55:56.376915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1870 20:55:56.471162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1871 20:55:56.471707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1873 20:55:56.565728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1874 20:55:56.566205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1876 20:55:56.662122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1877 20:55:56.662625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1879 20:55:56.753216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1880 20:55:56.753724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1882 20:55:56.849820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1883 20:55:56.850363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1885 20:55:56.943033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1886 20:55:56.943508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1888 20:55:57.040028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1889 20:55:57.040537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1891 20:55:57.135891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1892 20:55:57.136366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1894 20:55:57.233346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1895 20:55:57.233831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1897 20:55:57.323799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1898 20:55:57.324256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1900 20:55:57.415292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1901 20:55:57.415769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1903 20:55:57.507086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1904 20:55:57.507639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1906 20:55:57.602062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1907 20:55:57.602545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1909 20:55:57.695050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1910 20:55:57.695526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1912 20:55:57.791080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1913 20:55:57.791556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1915 20:55:57.884293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1916 20:55:57.884842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1918 20:55:57.979293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1919 20:55:57.979781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1921 20:55:58.074421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1922 20:55:58.074906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1924 20:55:58.169187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1925 20:55:58.169680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1927 20:55:58.262905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1928 20:55:58.263392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1930 20:55:58.357418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1931 20:55:58.357906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1933 20:55:58.450540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1934 20:55:58.451091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1936 20:55:58.544240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1937 20:55:58.544722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1939 20:55:58.641576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1940 20:55:58.642073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1942 20:55:58.735258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1943 20:55:58.735738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1945 20:55:58.832043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1946 20:55:58.832654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1948 20:55:58.925561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1949 20:55:58.926045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1951 20:55:59.023128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1952 20:55:59.023676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1954 20:55:59.119143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1955 20:55:59.119641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1957 20:55:59.209004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1958 20:55:59.209545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1960 20:55:59.305027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1961 20:55:59.305517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1963 20:55:59.397943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1964 20:55:59.398476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1966 20:55:59.493864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1967 20:55:59.494415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1969 20:55:59.584985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1970 20:55:59.585473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1972 20:55:59.680853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1973 20:55:59.681342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1975 20:55:59.772333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1976 20:55:59.772825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1978 20:55:59.866735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1979 20:55:59.867300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1981 20:55:59.961716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1982 20:55:59.962202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1984 20:56:00.054979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1985 20:56:00.055524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1987 20:56:00.163664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1988 20:56:00.164152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1990 20:56:00.264236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1991 20:56:00.264725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1993 20:56:00.357584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1994 20:56:00.358074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1996 20:56:00.454284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1997 20:56:00.454855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1999 20:56:00.551497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
2000 20:56:00.551980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
2002 20:56:00.644598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
2003 20:56:00.645111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
2005 20:56:00.740620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
2006 20:56:00.741122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
2008 20:56:00.837923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
2009 20:56:00.838494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
2011 20:56:00.936264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
2012 20:56:00.936756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
2014 20:56:01.030561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
2015 20:56:01.031073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
2017 20:56:01.126787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
2018 20:56:01.127285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
2020 20:56:01.223611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
2021 20:56:01.224111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
2023 20:56:01.320017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
2024 20:56:01.320545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
2026 20:56:01.414606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2027 20:56:01.415110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2029 20:56:01.508768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2030 20:56:01.509342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2032 20:56:01.603194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2033 20:56:01.603681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2035 20:56:01.696055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2036 20:56:01.696566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2038 20:56:01.790217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2039 20:56:01.790706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2041 20:56:01.882134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2042 20:56:01.882704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2044 20:56:01.977802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2046 20:56:01.980921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2047 20:56:02.072043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2049 20:56:02.075038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2050 20:56:02.166668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2052 20:56:02.169681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2053 20:56:02.261681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2054 20:56:02.262157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2056 20:56:02.355175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2057 20:56:02.355653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2059 20:56:02.449175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2060 20:56:02.449804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2062 20:56:02.543883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2063 20:56:02.544430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2065 20:56:02.639174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2066 20:56:02.639662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2068 20:56:02.732756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2069 20:56:02.733248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2071 20:56:02.826585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2072 20:56:02.827169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2074 20:56:02.921169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2075 20:56:02.921656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2077 20:56:03.013678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2078 20:56:03.014169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2080 20:56:03.106811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2081 20:56:03.107299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2083 20:56:03.232330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2084 20:56:03.232816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2086 20:56:03.339929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2087 20:56:03.340441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2089 20:56:03.432306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2090 20:56:03.432793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2092 20:56:03.526609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2093 20:56:03.527165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2095 20:56:03.620974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2096 20:56:03.621455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2098 20:56:03.719099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2099 20:56:03.719574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2101 20:56:03.810340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2102 20:56:03.810814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2104 20:56:03.905219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2105 20:56:03.905769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2107 20:56:03.997155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2108 20:56:03.997639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2110 20:56:04.094000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2111 20:56:04.094493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2113 20:56:04.185846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2114 20:56:04.186332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2116 20:56:04.277961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2117 20:56:04.278451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2119 20:56:04.374114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2120 20:56:04.374607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2122 20:56:04.466854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2123 20:56:04.467422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2125 20:56:04.560965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2126 20:56:04.561451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2128 20:56:04.656476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2129 20:56:04.656970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2131 20:56:04.751974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2132 20:56:04.752522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2134 20:56:04.849202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2135 20:56:04.849789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2137 20:56:04.944043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2138 20:56:04.944557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2140 20:56:05.041396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2141 20:56:05.041896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2143 20:56:05.140283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2144 20:56:05.140806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2146 20:56:05.234073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2147 20:56:05.234560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2149 20:56:05.330249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2150 20:56:05.330761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2152 20:56:05.425815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2153 20:56:05.426298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2155 20:56:05.520174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2156 20:56:05.520756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2158 20:56:05.616075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2159 20:56:05.616586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2161 20:56:05.709117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2162 20:56:05.709608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2164 20:56:05.806454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2165 20:56:05.806985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2167 20:56:05.900509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2168 20:56:05.901075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2170 20:56:05.994881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2171 20:56:05.995371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2173 20:56:06.089461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2174 20:56:06.089949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2176 20:56:06.185087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2177 20:56:06.185575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2179 20:56:06.282684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2180 20:56:06.283226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2182 20:56:06.376740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2183 20:56:06.377226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2185 20:56:06.470993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2186 20:56:06.471597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2188 20:56:06.565640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2189 20:56:06.566125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2191 20:56:06.660519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2192 20:56:06.661013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2194 20:56:06.753757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2195 20:56:06.754247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2197 20:56:06.850271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2198 20:56:06.850841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2200 20:56:06.947174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2201 20:56:06.947660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2203 20:56:07.042386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2204 20:56:07.042873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2206 20:56:07.143501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2207 20:56:07.143989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2209 20:56:07.234765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2210 20:56:07.235256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2212 20:56:07.332878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2213 20:56:07.333402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2215 20:56:07.427026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2216 20:56:07.427521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2218 20:56:07.527030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2219 20:56:07.527600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2221 20:56:07.625857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2222 20:56:07.626387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2224 20:56:07.716913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2225 20:56:07.717403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2227 20:56:07.813992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2228 20:56:07.814524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2230 20:56:07.907521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2231 20:56:07.908116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2233 20:56:08.005839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2234 20:56:08.006326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2236 20:56:08.098211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2237 20:56:08.098698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2239 20:56:08.194944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2240 20:56:08.195428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2242 20:56:08.286085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2243 20:56:08.286572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2245 20:56:08.380810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2246 20:56:08.381301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2248 20:56:08.476040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2249 20:56:08.476697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2251 20:56:08.571954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2252 20:56:08.572466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2254 20:56:08.669961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2255 20:56:08.670446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2257 20:56:08.765668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2258 20:56:08.766160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2260 20:56:08.860719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2261 20:56:08.861284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2263 20:56:08.956914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2264 20:56:08.957386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2266 20:56:09.052975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2267 20:56:09.053457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2269 20:56:09.149120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2270 20:56:09.149611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2272 20:56:09.244558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2273 20:56:09.245037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2275 20:56:09.341509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2276 20:56:09.341996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2278 20:56:09.432351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2279 20:56:09.432838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2281 20:56:09.529357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2282 20:56:09.529923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2284 20:56:09.624822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2285 20:56:09.625311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2287 20:56:09.720697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2288 20:56:09.721223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2290 20:56:09.818091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2291 20:56:09.818584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2293 20:56:09.915424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2294 20:56:09.915982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2296 20:56:10.011581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2297 20:56:10.012071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2299 20:56:10.106690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2300 20:56:10.107175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2302 20:56:10.201347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2303 20:56:10.201839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2305 20:56:10.295144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2306 20:56:10.295635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2308 20:56:10.387688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2309 20:56:10.388305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2311 20:56:10.481851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2312 20:56:10.482477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2314 20:56:10.578044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2315 20:56:10.578602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2317 20:56:10.674821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2318 20:56:10.675377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2320 20:56:10.768976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2321 20:56:10.769453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2323 20:56:10.862873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2324 20:56:10.863442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2326 20:56:10.955821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2327 20:56:10.956307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2329 20:56:11.050865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2330 20:56:11.051352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2332 20:56:11.145802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2333 20:56:11.146278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2335 20:56:11.242268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2336 20:56:11.242753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2338 20:56:11.334279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2339 20:56:11.334768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2341 20:56:11.427255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2342 20:56:11.427739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2344 20:56:11.521323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2345 20:56:11.521889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2347 20:56:11.615229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2348 20:56:11.615711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2350 20:56:11.708077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2351 20:56:11.708575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2353 20:56:11.800214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2354 20:56:11.800697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2356 20:56:11.890703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2357 20:56:11.891248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2359 20:56:11.986745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2360 20:56:11.987229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2362 20:56:12.081191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2363 20:56:12.081672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2365 20:56:12.172333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2367 20:56:12.175335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2368 20:56:12.265811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2369 20:56:12.266286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2371 20:56:12.361557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2372 20:56:12.362033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2374 20:56:12.451559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2375 20:56:12.452036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2377 20:56:12.547309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2378 20:56:12.547863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2380 20:56:12.640669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2381 20:56:12.641145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2383 20:56:12.736794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2384 20:56:12.737271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2386 20:56:12.827302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2387 20:56:12.827781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2389 20:56:12.921055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2390 20:56:12.921607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2392 20:56:13.013345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2393 20:56:13.013828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2395 20:56:13.108093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2396 20:56:13.108589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2398 20:56:13.200483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2399 20:56:13.200955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2401 20:56:13.292604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2402 20:56:13.293082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2404 20:56:13.386087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2405 20:56:13.386559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2407 20:56:13.474767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2408 20:56:13.475241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2410 20:56:13.568498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2411 20:56:13.569056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2413 20:56:13.659753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2414 20:56:13.660249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2416 20:56:13.755734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2417 20:56:13.756227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2419 20:56:13.846832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2420 20:56:13.847301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2422 20:56:13.940234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2423 20:56:13.940782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2425 20:56:14.031723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2426 20:56:14.032192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2428 20:56:14.126451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2429 20:56:14.126918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2431 20:56:14.220842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2432 20:56:14.221319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2434 20:56:14.314942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2435 20:56:14.315419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2437 20:56:14.410679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2438 20:56:14.411153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2440 20:56:14.503569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2441 20:56:14.504141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2443 20:56:14.596235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2444 20:56:14.596710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2446 20:56:14.692479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2447 20:56:14.692953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2449 20:56:14.786233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2450 20:56:14.786708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2452 20:56:14.878797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2453 20:56:14.879352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2455 20:56:14.973914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2456 20:56:14.974396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2458 20:56:15.061777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2459 20:56:15.062071 + set +x
2460 20:56:15.062522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2462 20:56:15.066055 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1193790_1.6.2.4.5>
2463 20:56:15.066488 Received signal: <ENDRUN> 1_kselftest-dt 1193790_1.6.2.4.5
2464 20:56:15.066728 Ending use of test pattern.
2465 20:56:15.066946 Ending test lava.1_kselftest-dt (1193790_1.6.2.4.5), duration 92.86
2467 20:56:15.072614 <LAVA_TEST_RUNNER EXIT>
2468 20:56:15.073092 ok: lava_test_shell seems to have completed
2469 20:56:15.078867 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2470 20:56:15.079923 end: 3.1 lava-test-shell (duration 00:01:34) [common]
2471 20:56:15.080237 end: 3 lava-test-retry (duration 00:01:34) [common]
2472 20:56:15.080436 start: 4 finalize (timeout 00:05:49) [common]
2473 20:56:15.080611 start: 4.1 power-off (timeout 00:00:30) [common]
2474 20:56:15.080837 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2475 20:56:15.449723 Returned 0 in 0 seconds
2476 20:56:15.550667 end: 4.1 power-off (duration 00:00:00) [common]
2478 20:56:15.551636 start: 4.2 read-feedback (timeout 00:05:49) [common]
2479 20:56:15.552265 Listened to connection for namespace 'common' for up to 1s
2480 20:56:15.552816 Listened to connection for namespace 'common' for up to 1s
2481 20:56:16.553159 Finalising connection for namespace 'common'
2482 20:56:16.553622 Disconnecting from shell: Finalise
2483 20:56:16.553896 / #
2484 20:56:16.654448 end: 4.2 read-feedback (duration 00:00:01) [common]
2485 20:56:16.654814 end: 4 finalize (duration 00:00:02) [common]
2486 20:56:16.655164 Cleaning after the job
2487 20:56:16.655473 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/ramdisk
2488 20:56:16.659161 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/kernel
2489 20:56:16.662081 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/dtb
2490 20:56:16.662543 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/nfsrootfs
2491 20:56:16.716844 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1193790/tftp-deploy-wiehv_vq/modules
2492 20:56:16.720435 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1193790
2493 20:56:17.361718 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1193790
2494 20:56:17.361993 Job finished correctly