Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 12:41:39.783684 lava-dispatcher, installed at version: 2024.01
2 12:41:39.784542 start: 0 validate
3 12:41:39.785051 Start time: 2024-09-19 12:41:39.785022+00:00 (UTC)
4 12:41:39.785631 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 12:41:39.786190 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 12:41:39.828529 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 12:41:39.829142 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 12:41:39.865902 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 12:41:39.866576 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 12:41:40.913798 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 12:41:40.914335 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
12 12:41:40.957965 validate duration: 1.17
14 12:41:40.959460 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:41:40.960250 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:41:40.960645 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:41:40.961275 Not decompressing ramdisk as can be used compressed.
18 12:41:40.961712 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 12:41:40.961950 saving as /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/ramdisk/rootfs.cpio.gz
20 12:41:40.962202 total size: 8181887 (7 MB)
21 12:41:41.004233 progress 0 % (0 MB)
22 12:41:41.016594 progress 5 % (0 MB)
23 12:41:41.028322 progress 10 % (0 MB)
24 12:41:41.040227 progress 15 % (1 MB)
25 12:41:41.045732 progress 20 % (1 MB)
26 12:41:41.051621 progress 25 % (1 MB)
27 12:41:41.057131 progress 30 % (2 MB)
28 12:41:41.063104 progress 35 % (2 MB)
29 12:41:41.068569 progress 40 % (3 MB)
30 12:41:41.074484 progress 45 % (3 MB)
31 12:41:41.079906 progress 50 % (3 MB)
32 12:41:41.085734 progress 55 % (4 MB)
33 12:41:41.091061 progress 60 % (4 MB)
34 12:41:41.096889 progress 65 % (5 MB)
35 12:41:41.102449 progress 70 % (5 MB)
36 12:41:41.108240 progress 75 % (5 MB)
37 12:41:41.113641 progress 80 % (6 MB)
38 12:41:41.119425 progress 85 % (6 MB)
39 12:41:41.124768 progress 90 % (7 MB)
40 12:41:41.130537 progress 95 % (7 MB)
41 12:41:41.135569 progress 100 % (7 MB)
42 12:41:41.136264 7 MB downloaded in 0.17 s (44.83 MB/s)
43 12:41:41.136844 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:41:41.137807 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:41:41.138129 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:41:41.138419 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:41:41.138918 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
49 12:41:41.139199 saving as /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/kernel/Image
50 12:41:41.139423 total size: 39127552 (37 MB)
51 12:41:41.139648 No compression specified
52 12:41:41.180243 progress 0 % (0 MB)
53 12:41:41.205052 progress 5 % (1 MB)
54 12:41:41.229957 progress 10 % (3 MB)
55 12:41:41.254598 progress 15 % (5 MB)
56 12:41:41.279590 progress 20 % (7 MB)
57 12:41:41.304737 progress 25 % (9 MB)
58 12:41:41.330247 progress 30 % (11 MB)
59 12:41:41.354583 progress 35 % (13 MB)
60 12:41:41.379077 progress 40 % (14 MB)
61 12:41:41.403450 progress 45 % (16 MB)
62 12:41:41.428405 progress 50 % (18 MB)
63 12:41:41.452354 progress 55 % (20 MB)
64 12:41:41.476996 progress 60 % (22 MB)
65 12:41:41.501357 progress 65 % (24 MB)
66 12:41:41.525730 progress 70 % (26 MB)
67 12:41:41.549988 progress 75 % (28 MB)
68 12:41:41.574111 progress 80 % (29 MB)
69 12:41:41.597883 progress 85 % (31 MB)
70 12:41:41.622038 progress 90 % (33 MB)
71 12:41:41.646474 progress 95 % (35 MB)
72 12:41:41.670119 progress 100 % (37 MB)
73 12:41:41.670663 37 MB downloaded in 0.53 s (70.24 MB/s)
74 12:41:41.671155 end: 1.2.1 http-download (duration 00:00:01) [common]
76 12:41:41.672012 end: 1.2 download-retry (duration 00:00:01) [common]
77 12:41:41.672301 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:41:41.672570 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:41:41.673057 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 12:41:41.673346 saving as /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/dtb/meson-g12b-a311d-libretech-cc.dtb
81 12:41:41.673557 total size: 54703 (0 MB)
82 12:41:41.673768 No compression specified
83 12:41:41.717225 progress 59 % (0 MB)
84 12:41:41.718097 progress 100 % (0 MB)
85 12:41:41.718657 0 MB downloaded in 0.05 s (1.16 MB/s)
86 12:41:41.719166 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:41:41.720040 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:41:41.720329 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:41:41.720603 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:41:41.721111 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
92 12:41:41.721366 saving as /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/modules/modules.tar
93 12:41:41.721575 total size: 11720432 (11 MB)
94 12:41:41.721787 Using unxz to decompress xz
95 12:41:41.763316 progress 0 % (0 MB)
96 12:41:41.833212 progress 5 % (0 MB)
97 12:41:41.915212 progress 10 % (1 MB)
98 12:41:42.007269 progress 15 % (1 MB)
99 12:41:42.090634 progress 20 % (2 MB)
100 12:41:42.175645 progress 25 % (2 MB)
101 12:41:42.258635 progress 30 % (3 MB)
102 12:41:42.340423 progress 35 % (3 MB)
103 12:41:42.420800 progress 40 % (4 MB)
104 12:41:42.494804 progress 45 % (5 MB)
105 12:41:42.575569 progress 50 % (5 MB)
106 12:41:42.654360 progress 55 % (6 MB)
107 12:41:42.740610 progress 60 % (6 MB)
108 12:41:42.828514 progress 65 % (7 MB)
109 12:41:42.912351 progress 70 % (7 MB)
110 12:41:43.007494 progress 75 % (8 MB)
111 12:41:43.103841 progress 80 % (8 MB)
112 12:41:43.186994 progress 85 % (9 MB)
113 12:41:43.259500 progress 90 % (10 MB)
114 12:41:43.339807 progress 95 % (10 MB)
115 12:41:43.417911 progress 100 % (11 MB)
116 12:41:43.431492 11 MB downloaded in 1.71 s (6.54 MB/s)
117 12:41:43.432235 end: 1.4.1 http-download (duration 00:00:02) [common]
119 12:41:43.433864 end: 1.4 download-retry (duration 00:00:02) [common]
120 12:41:43.434390 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 12:41:43.434908 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 12:41:43.435397 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:41:43.435892 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 12:41:43.436930 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta
125 12:41:43.437740 makedir: /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin
126 12:41:43.438364 makedir: /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/tests
127 12:41:43.438971 makedir: /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/results
128 12:41:43.439574 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-add-keys
129 12:41:43.440550 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-add-sources
130 12:41:43.441486 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-background-process-start
131 12:41:43.442421 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-background-process-stop
132 12:41:43.443376 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-common-functions
133 12:41:43.444336 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-echo-ipv4
134 12:41:43.445238 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-install-packages
135 12:41:43.446135 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-installed-packages
136 12:41:43.447017 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-os-build
137 12:41:43.447915 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-probe-channel
138 12:41:43.448856 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-probe-ip
139 12:41:43.449756 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-target-ip
140 12:41:43.450647 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-target-mac
141 12:41:43.451541 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-target-storage
142 12:41:43.452507 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-test-case
143 12:41:43.453425 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-test-event
144 12:41:43.454312 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-test-feedback
145 12:41:43.455236 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-test-raise
146 12:41:43.456149 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-test-reference
147 12:41:43.457054 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-test-runner
148 12:41:43.457939 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-test-set
149 12:41:43.458826 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-test-shell
150 12:41:43.459760 Updating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-install-packages (oe)
151 12:41:43.460796 Updating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/bin/lava-installed-packages (oe)
152 12:41:43.461627 Creating /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/environment
153 12:41:43.462337 LAVA metadata
154 12:41:43.462815 - LAVA_JOB_ID=745160
155 12:41:43.463243 - LAVA_DISPATCHER_IP=192.168.6.2
156 12:41:43.463906 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 12:41:43.465790 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 12:41:43.466374 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 12:41:43.466788 skipped lava-vland-overlay
160 12:41:43.467271 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 12:41:43.467771 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 12:41:43.468235 skipped lava-multinode-overlay
163 12:41:43.468721 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 12:41:43.469220 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 12:41:43.469700 Loading test definitions
166 12:41:43.470246 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 12:41:43.470685 Using /lava-745160 at stage 0
168 12:41:43.472592 uuid=745160_1.5.2.4.1 testdef=None
169 12:41:43.472924 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 12:41:43.473222 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 12:41:43.475161 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 12:41:43.476000 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 12:41:43.478315 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 12:41:43.479158 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 12:41:43.481409 runner path: /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/0/tests/0_dmesg test_uuid 745160_1.5.2.4.1
178 12:41:43.481982 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 12:41:43.482763 Creating lava-test-runner.conf files
181 12:41:43.482969 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/745160/lava-overlay-mscyclta/lava-745160/0 for stage 0
182 12:41:43.483316 - 0_dmesg
183 12:41:43.483668 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 12:41:43.483951 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 12:41:43.507940 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 12:41:43.508392 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 12:41:43.508660 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 12:41:43.508930 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 12:41:43.509195 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 12:41:44.440892 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 12:41:44.441370 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 12:41:44.441615 extracting modules file /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/745160/extract-overlay-ramdisk-nj5chtq3/ramdisk
193 12:41:45.835577 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 12:41:45.836066 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 12:41:45.836343 [common] Applying overlay /var/lib/lava/dispatcher/tmp/745160/compress-overlay-294wjerp/overlay-1.5.2.5.tar.gz to ramdisk
196 12:41:45.836555 [common] Applying overlay /var/lib/lava/dispatcher/tmp/745160/compress-overlay-294wjerp/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/745160/extract-overlay-ramdisk-nj5chtq3/ramdisk
197 12:41:45.866813 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 12:41:45.867242 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 12:41:45.867512 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 12:41:45.867742 Converting downloaded kernel to a uImage
201 12:41:45.868077 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/kernel/Image /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/kernel/uImage
202 12:41:46.267760 output: Image Name:
203 12:41:46.268198 output: Created: Thu Sep 19 12:41:45 2024
204 12:41:46.268410 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 12:41:46.268616 output: Data Size: 39127552 Bytes = 38210.50 KiB = 37.31 MiB
206 12:41:46.268818 output: Load Address: 01080000
207 12:41:46.269015 output: Entry Point: 01080000
208 12:41:46.269211 output:
209 12:41:46.269544 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 12:41:46.269810 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 12:41:46.270083 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 12:41:46.270338 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 12:41:46.270597 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 12:41:46.270850 Building ramdisk /var/lib/lava/dispatcher/tmp/745160/extract-overlay-ramdisk-nj5chtq3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/745160/extract-overlay-ramdisk-nj5chtq3/ramdisk
215 12:41:48.908430 >> 187623 blocks
216 12:41:57.268229 Adding RAMdisk u-boot header.
217 12:41:57.268660 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/745160/extract-overlay-ramdisk-nj5chtq3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/745160/extract-overlay-ramdisk-nj5chtq3/ramdisk.cpio.gz.uboot
218 12:41:57.545475 output: Image Name:
219 12:41:57.545890 output: Created: Thu Sep 19 12:41:57 2024
220 12:41:57.546098 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 12:41:57.546302 output: Data Size: 26696441 Bytes = 26070.74 KiB = 25.46 MiB
222 12:41:57.546502 output: Load Address: 00000000
223 12:41:57.546700 output: Entry Point: 00000000
224 12:41:57.546897 output:
225 12:41:57.547535 rename /var/lib/lava/dispatcher/tmp/745160/extract-overlay-ramdisk-nj5chtq3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/ramdisk/ramdisk.cpio.gz.uboot
226 12:41:57.547953 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 12:41:57.548616 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 12:41:57.549221 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 12:41:57.549722 No LXC device requested
230 12:41:57.550269 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 12:41:57.550824 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 12:41:57.551367 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 12:41:57.551821 Checking files for TFTP limit of 4294967296 bytes.
234 12:41:57.554787 end: 1 tftp-deploy (duration 00:00:17) [common]
235 12:41:57.555406 start: 2 uboot-action (timeout 00:05:00) [common]
236 12:41:57.555975 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 12:41:57.556555 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 12:41:57.557122 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 12:41:57.557704 Using kernel file from prepare-kernel: 745160/tftp-deploy-1f36vw0e/kernel/uImage
240 12:41:57.558367 substitutions:
241 12:41:57.558815 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 12:41:57.559259 - {DTB_ADDR}: 0x01070000
243 12:41:57.559694 - {DTB}: 745160/tftp-deploy-1f36vw0e/dtb/meson-g12b-a311d-libretech-cc.dtb
244 12:41:57.560167 - {INITRD}: 745160/tftp-deploy-1f36vw0e/ramdisk/ramdisk.cpio.gz.uboot
245 12:41:57.560611 - {KERNEL_ADDR}: 0x01080000
246 12:41:57.561045 - {KERNEL}: 745160/tftp-deploy-1f36vw0e/kernel/uImage
247 12:41:57.561479 - {LAVA_MAC}: None
248 12:41:57.561952 - {PRESEED_CONFIG}: None
249 12:41:57.562385 - {PRESEED_LOCAL}: None
250 12:41:57.562813 - {RAMDISK_ADDR}: 0x08000000
251 12:41:57.563238 - {RAMDISK}: 745160/tftp-deploy-1f36vw0e/ramdisk/ramdisk.cpio.gz.uboot
252 12:41:57.563671 - {ROOT_PART}: None
253 12:41:57.564127 - {ROOT}: None
254 12:41:57.564563 - {SERVER_IP}: 192.168.6.2
255 12:41:57.564998 - {TEE_ADDR}: 0x83000000
256 12:41:57.565426 - {TEE}: None
257 12:41:57.565851 Parsed boot commands:
258 12:41:57.566265 - setenv autoload no
259 12:41:57.566687 - setenv initrd_high 0xffffffff
260 12:41:57.567114 - setenv fdt_high 0xffffffff
261 12:41:57.567538 - dhcp
262 12:41:57.567963 - setenv serverip 192.168.6.2
263 12:41:57.568420 - tftpboot 0x01080000 745160/tftp-deploy-1f36vw0e/kernel/uImage
264 12:41:57.568848 - tftpboot 0x08000000 745160/tftp-deploy-1f36vw0e/ramdisk/ramdisk.cpio.gz.uboot
265 12:41:57.569277 - tftpboot 0x01070000 745160/tftp-deploy-1f36vw0e/dtb/meson-g12b-a311d-libretech-cc.dtb
266 12:41:57.569703 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 12:41:57.570133 - bootm 0x01080000 0x08000000 0x01070000
268 12:41:57.570670 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 12:41:57.572327 start: 2.3 connect-device (timeout 00:05:00) [common]
271 12:41:57.572811 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 12:41:57.588091 Setting prompt string to ['lava-test: # ']
273 12:41:57.589693 end: 2.3 connect-device (duration 00:00:00) [common]
274 12:41:57.590344 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 12:41:57.590942 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 12:41:57.591500 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 12:41:57.592745 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 12:41:57.629795 >> OK - accepted request
279 12:41:57.632333 Returned 0 in 0 seconds
280 12:41:57.733601 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 12:41:57.735356 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 12:41:57.735968 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 12:41:57.736576 Setting prompt string to ['Hit any key to stop autoboot']
285 12:41:57.737061 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 12:41:57.738754 Trying 192.168.56.21...
287 12:41:57.739255 Connected to conserv1.
288 12:41:57.739719 Escape character is '^]'.
289 12:41:57.740212
290 12:41:57.740678 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 12:41:57.741151
292 12:42:09.663385 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 12:42:09.664115 bl2_stage_init 0x01
294 12:42:09.664585 bl2_stage_init 0x81
295 12:42:09.665049 hw id: 0x0000 - pwm id 0x01
296 12:42:09.665496 bl2_stage_init 0xc1
297 12:42:09.665938 bl2_stage_init 0x02
298 12:42:09.666386
299 12:42:09.666841 L0:00000000
300 12:42:09.667289 L1:20000703
301 12:42:09.667731 L2:00008067
302 12:42:09.668197 L3:14000000
303 12:42:09.668633 B2:00402000
304 12:42:09.669069 B1:e0f83180
305 12:42:09.669489
306 12:42:09.669910 TE: 58159
307 12:42:09.670332
308 12:42:09.671162 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 12:42:09.671617
310 12:42:09.672082 Board ID = 1
311 12:42:09.672512 Set A53 clk to 24M
312 12:42:09.672935 Set A73 clk to 24M
313 12:42:09.673355 Set clk81 to 24M
314 12:42:09.673774 A53 clk: 1200 MHz
315 12:42:09.674192 A73 clk: 1200 MHz
316 12:42:09.674610 CLK81: 166.6M
317 12:42:09.675030 smccc: 00012ab5
318 12:42:09.675447 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 12:42:09.675870 board id: 1
320 12:42:09.676318 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 12:42:09.676742 fw parse done
322 12:42:09.677163 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 12:42:09.677585 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 12:42:09.678006 PIEI prepare done
325 12:42:09.678421 fastboot data load
326 12:42:09.678840 fastboot data verify
327 12:42:09.679256 verify result: 266
328 12:42:09.679670 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 12:42:09.680110 LPDDR4 probe
330 12:42:09.680527 ddr clk to 1584MHz
331 12:42:09.680948 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 12:42:09.681369
333 12:42:09.681788 dmc_version 0001
334 12:42:09.682203 Check phy result
335 12:42:09.682618 INFO : End of CA training
336 12:42:09.683036 INFO : End of initialization
337 12:42:09.683452 INFO : Training has run successfully!
338 12:42:09.683901 Check phy result
339 12:42:09.684347 INFO : End of initialization
340 12:42:09.684874 INFO : End of read enable training
341 12:42:09.685306 INFO : End of fine write leveling
342 12:42:09.685731 INFO : End of Write leveling coarse delay
343 12:42:09.686151 INFO : Training has run successfully!
344 12:42:09.686569 Check phy result
345 12:42:09.689623 INFO : End of initialization
346 12:42:09.690116 INFO : End of read dq deskew training
347 12:42:09.695237 INFO : End of MPR read delay center optimization
348 12:42:09.700936 INFO : End of write delay center optimization
349 12:42:09.701476 INFO : End of read delay center optimization
350 12:42:09.706615 INFO : End of max read latency training
351 12:42:09.712079 INFO : Training has run successfully!
352 12:42:09.712560 1D training succeed
353 12:42:09.719166 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 12:42:09.766746 Check phy result
355 12:42:09.767241 INFO : End of initialization
356 12:42:09.788426 INFO : End of 2D read delay Voltage center optimization
357 12:42:09.807928 INFO : End of 2D read delay Voltage center optimization
358 12:42:09.859868 INFO : End of 2D write delay Voltage center optimization
359 12:42:09.909401 INFO : End of 2D write delay Voltage center optimization
360 12:42:09.914803 INFO : Training has run successfully!
361 12:42:09.915308
362 12:42:09.915754 channel==0
363 12:42:09.920656 RxClkDly_Margin_A0==88 ps 9
364 12:42:09.921149 TxDqDly_Margin_A0==98 ps 10
365 12:42:09.923739 RxClkDly_Margin_A1==88 ps 9
366 12:42:09.924471 TxDqDly_Margin_A1==98 ps 10
367 12:42:09.929409 TrainedVREFDQ_A0==74
368 12:42:09.929969 TrainedVREFDQ_A1==76
369 12:42:09.934996 VrefDac_Margin_A0==25
370 12:42:09.935547 DeviceVref_Margin_A0==40
371 12:42:09.935957 VrefDac_Margin_A1==25
372 12:42:09.943192 DeviceVref_Margin_A1==38
373 12:42:09.943783
374 12:42:09.944247
375 12:42:09.944655 channel==1
376 12:42:09.945599 RxClkDly_Margin_A0==88 ps 9
377 12:42:09.946130 TxDqDly_Margin_A0==88 ps 9
378 12:42:09.946546 RxClkDly_Margin_A1==88 ps 9
379 12:42:09.951331 TxDqDly_Margin_A1==88 ps 9
380 12:42:09.951854 TrainedVREFDQ_A0==77
381 12:42:09.956827 TrainedVREFDQ_A1==77
382 12:42:09.957350 VrefDac_Margin_A0==23
383 12:42:09.957753 DeviceVref_Margin_A0==37
384 12:42:09.962453 VrefDac_Margin_A1==24
385 12:42:09.962973 DeviceVref_Margin_A1==37
386 12:42:09.963377
387 12:42:09.968079 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 12:42:09.968611
389 12:42:09.995893 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 12:42:10.001607 2D training succeed
391 12:42:10.007167 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 12:42:10.007701 auto size-- 65535DDR cs0 size: 2048MB
393 12:42:10.012598 DDR cs1 size: 2048MB
394 12:42:10.013121 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 12:42:10.018200 cs0 DataBus test pass
396 12:42:10.018711 cs1 DataBus test pass
397 12:42:10.019116 cs0 AddrBus test pass
398 12:42:10.023731 cs1 AddrBus test pass
399 12:42:10.024292
400 12:42:10.024704 100bdlr_step_size ps== 420
401 12:42:10.029398 result report
402 12:42:10.029902 boot times 0Enable ddr reg access
403 12:42:10.037627 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 12:42:10.051066 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 12:42:10.624726 0.0;M3 CHK:0;cm4_sp_mode 0
406 12:42:10.625308 MVN_1=0x00000000
407 12:42:10.630216 MVN_2=0x00000000
408 12:42:10.635941 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 12:42:10.636498 OPS=0x10
410 12:42:10.636908 ring efuse init
411 12:42:10.637301 chipver efuse init
412 12:42:10.644325 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 12:42:10.644864 [0.018960 Inits done]
414 12:42:10.645269 secure task start!
415 12:42:10.651770 high task start!
416 12:42:10.652308 low task start!
417 12:42:10.652714 run into bl31
418 12:42:10.658355 NOTICE: BL31: v1.3(release):4fc40b1
419 12:42:10.666194 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 12:42:10.666714 NOTICE: BL31: G12A normal boot!
421 12:42:10.691645 NOTICE: BL31: BL33 decompress pass
422 12:42:10.697268 ERROR: Error initializing runtime service opteed_fast
423 12:42:11.930041
424 12:42:11.930630
425 12:42:11.938483 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 12:42:11.938983
427 12:42:11.939386 Model: Libre Computer AML-A311D-CC Alta
428 12:42:12.146891 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 12:42:12.170260 DRAM: 2 GiB (effective 3.8 GiB)
430 12:42:12.313290 Core: 408 devices, 31 uclasses, devicetree: separate
431 12:42:12.319157 WDT: Not starting watchdog@f0d0
432 12:42:12.351440 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 12:42:12.363839 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 12:42:12.368867 ** Bad device specification mmc 0 **
435 12:42:12.379195 Card did not respond to voltage select! : -110
436 12:42:12.386898 ** Bad device specification mmc 0 **
437 12:42:12.387381 Couldn't find partition mmc 0
438 12:42:12.395207 Card did not respond to voltage select! : -110
439 12:42:12.400810 ** Bad device specification mmc 0 **
440 12:42:12.401286 Couldn't find partition mmc 0
441 12:42:12.405871 Error: could not access storage.
442 12:42:13.669046 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 12:42:13.669653 bl2_stage_init 0x01
444 12:42:13.670081 bl2_stage_init 0x81
445 12:42:13.674685 hw id: 0x0000 - pwm id 0x01
446 12:42:13.675164 bl2_stage_init 0xc1
447 12:42:13.675579 bl2_stage_init 0x02
448 12:42:13.676049
449 12:42:13.680228 L0:00000000
450 12:42:13.680701 L1:20000703
451 12:42:13.681115 L2:00008067
452 12:42:13.681516 L3:14000000
453 12:42:13.685824 B2:00402000
454 12:42:13.686291 B1:e0f83180
455 12:42:13.686701
456 12:42:13.687111 TE: 58124
457 12:42:13.687517
458 12:42:13.691443 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 12:42:13.691917
460 12:42:13.692366 Board ID = 1
461 12:42:13.697154 Set A53 clk to 24M
462 12:42:13.697628 Set A73 clk to 24M
463 12:42:13.698040 Set clk81 to 24M
464 12:42:13.702640 A53 clk: 1200 MHz
465 12:42:13.703111 A73 clk: 1200 MHz
466 12:42:13.703523 CLK81: 166.6M
467 12:42:13.703921 smccc: 00012a92
468 12:42:13.708281 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 12:42:13.713802 board id: 1
470 12:42:13.719699 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 12:42:13.730351 fw parse done
472 12:42:13.735387 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 12:42:13.778112 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 12:42:13.789844 PIEI prepare done
475 12:42:13.790317 fastboot data load
476 12:42:13.790728 fastboot data verify
477 12:42:13.795469 verify result: 266
478 12:42:13.801091 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 12:42:13.801556 LPDDR4 probe
480 12:42:13.801966 ddr clk to 1584MHz
481 12:42:13.808152 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 12:42:13.846295
483 12:42:13.846791 dmc_version 0001
484 12:42:13.852164 Check phy result
485 12:42:13.858868 INFO : End of CA training
486 12:42:13.859339 INFO : End of initialization
487 12:42:13.864464 INFO : Training has run successfully!
488 12:42:13.864933 Check phy result
489 12:42:13.870073 INFO : End of initialization
490 12:42:13.870540 INFO : End of read enable training
491 12:42:13.875662 INFO : End of fine write leveling
492 12:42:13.881247 INFO : End of Write leveling coarse delay
493 12:42:13.881714 INFO : Training has run successfully!
494 12:42:13.882122 Check phy result
495 12:42:13.886866 INFO : End of initialization
496 12:42:13.887331 INFO : End of read dq deskew training
497 12:42:13.892436 INFO : End of MPR read delay center optimization
498 12:42:13.898068 INFO : End of write delay center optimization
499 12:42:13.903646 INFO : End of read delay center optimization
500 12:42:13.904156 INFO : End of max read latency training
501 12:42:13.909245 INFO : Training has run successfully!
502 12:42:13.909710 1D training succeed
503 12:42:13.918397 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 12:42:13.966054 Check phy result
505 12:42:13.966574 INFO : End of initialization
506 12:42:13.986859 INFO : End of 2D read delay Voltage center optimization
507 12:42:14.008197 INFO : End of 2D read delay Voltage center optimization
508 12:42:14.059253 INFO : End of 2D write delay Voltage center optimization
509 12:42:14.109415 INFO : End of 2D write delay Voltage center optimization
510 12:42:14.115108 INFO : Training has run successfully!
511 12:42:14.115589
512 12:42:14.116050 channel==0
513 12:42:14.120594 RxClkDly_Margin_A0==88 ps 9
514 12:42:14.121066 TxDqDly_Margin_A0==98 ps 10
515 12:42:14.126199 RxClkDly_Margin_A1==88 ps 9
516 12:42:14.126672 TxDqDly_Margin_A1==98 ps 10
517 12:42:14.127083 TrainedVREFDQ_A0==74
518 12:42:14.131803 TrainedVREFDQ_A1==75
519 12:42:14.132311 VrefDac_Margin_A0==25
520 12:42:14.132721 DeviceVref_Margin_A0==40
521 12:42:14.137385 VrefDac_Margin_A1==25
522 12:42:14.137854 DeviceVref_Margin_A1==39
523 12:42:14.138260
524 12:42:14.138658
525 12:42:14.143072 channel==1
526 12:42:14.143535 RxClkDly_Margin_A0==98 ps 10
527 12:42:14.143945 TxDqDly_Margin_A0==98 ps 10
528 12:42:14.148607 RxClkDly_Margin_A1==98 ps 10
529 12:42:14.149071 TxDqDly_Margin_A1==88 ps 9
530 12:42:14.154180 TrainedVREFDQ_A0==77
531 12:42:14.154652 TrainedVREFDQ_A1==77
532 12:42:14.155066 VrefDac_Margin_A0==22
533 12:42:14.159842 DeviceVref_Margin_A0==37
534 12:42:14.160358 VrefDac_Margin_A1==22
535 12:42:14.165334 DeviceVref_Margin_A1==37
536 12:42:14.165841
537 12:42:14.166256 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 12:42:14.171072
539 12:42:14.199030 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
540 12:42:14.199577 2D training succeed
541 12:42:14.204601 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 12:42:14.210181 auto size-- 65535DDR cs0 size: 2048MB
543 12:42:14.210656 DDR cs1 size: 2048MB
544 12:42:14.215811 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 12:42:14.216356 cs0 DataBus test pass
546 12:42:14.221506 cs1 DataBus test pass
547 12:42:14.221980 cs0 AddrBus test pass
548 12:42:14.222392 cs1 AddrBus test pass
549 12:42:14.222794
550 12:42:14.227096 100bdlr_step_size ps== 420
551 12:42:14.227576 result report
552 12:42:14.232609 boot times 0Enable ddr reg access
553 12:42:14.238054 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 12:42:14.251461 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 12:42:14.825273 0.0;M3 CHK:0;cm4_sp_mode 0
556 12:42:14.825860 MVN_1=0x00000000
557 12:42:14.830721 MVN_2=0x00000000
558 12:42:14.836513 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 12:42:14.837046 OPS=0x10
560 12:42:14.837493 ring efuse init
561 12:42:14.837917 chipver efuse init
562 12:42:14.842035 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 12:42:14.847609 [0.018961 Inits done]
564 12:42:14.848134 secure task start!
565 12:42:14.848531 high task start!
566 12:42:14.852225 low task start!
567 12:42:14.852691 run into bl31
568 12:42:14.858820 NOTICE: BL31: v1.3(release):4fc40b1
569 12:42:14.866607 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 12:42:14.867088 NOTICE: BL31: G12A normal boot!
571 12:42:14.892015 NOTICE: BL31: BL33 decompress pass
572 12:42:14.897692 ERROR: Error initializing runtime service opteed_fast
573 12:42:16.130732
574 12:42:16.131284
575 12:42:16.139087 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 12:42:16.139510
577 12:42:16.139727 Model: Libre Computer AML-A311D-CC Alta
578 12:42:16.349082 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 12:42:16.371432 DRAM: 2 GiB (effective 3.8 GiB)
580 12:42:16.513968 Core: 408 devices, 31 uclasses, devicetree: separate
581 12:42:16.520019 WDT: Not starting watchdog@f0d0
582 12:42:16.552027 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 12:42:16.564539 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 12:42:16.569504 ** Bad device specification mmc 0 **
585 12:42:16.579891 Card did not respond to voltage select! : -110
586 12:42:16.587446 ** Bad device specification mmc 0 **
587 12:42:16.587966 Couldn't find partition mmc 0
588 12:42:16.595725 Card did not respond to voltage select! : -110
589 12:42:16.601599 ** Bad device specification mmc 0 **
590 12:42:16.602122 Couldn't find partition mmc 0
591 12:42:16.605742 Error: could not access storage.
592 12:42:16.950061 Net: eth0: ethernet@ff3f0000
593 12:42:16.950520 starting USB...
594 12:42:17.201960 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 12:42:17.202500 Starting the controller
596 12:42:17.208983 USB XHCI 1.10
597 12:42:18.920834 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 12:42:18.921256 bl2_stage_init 0x01
599 12:42:18.921496 bl2_stage_init 0x81
600 12:42:18.926456 hw id: 0x0000 - pwm id 0x01
601 12:42:18.926761 bl2_stage_init 0xc1
602 12:42:18.926987 bl2_stage_init 0x02
603 12:42:18.927198
604 12:42:18.931906 L0:00000000
605 12:42:18.932236 L1:20000703
606 12:42:18.932463 L2:00008067
607 12:42:18.932681 L3:14000000
608 12:42:18.934977 B2:00402000
609 12:42:18.935302 B1:e0f83180
610 12:42:18.935526
611 12:42:18.935876 TE: 58124
612 12:42:18.936333
613 12:42:18.946190 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 12:42:18.946785
615 12:42:18.947213 Board ID = 1
616 12:42:18.947625 Set A53 clk to 24M
617 12:42:18.948074 Set A73 clk to 24M
618 12:42:18.951904 Set clk81 to 24M
619 12:42:18.952471 A53 clk: 1200 MHz
620 12:42:18.952892 A73 clk: 1200 MHz
621 12:42:18.955278 CLK81: 166.6M
622 12:42:18.955760 smccc: 00012a92
623 12:42:18.960735 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 12:42:18.966440 board id: 1
625 12:42:18.971685 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 12:42:18.982215 fw parse done
627 12:42:18.988186 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 12:42:19.030775 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 12:42:19.041771 PIEI prepare done
630 12:42:19.042340 fastboot data load
631 12:42:19.042764 fastboot data verify
632 12:42:19.047449 verify result: 266
633 12:42:19.053031 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 12:42:19.053584 LPDDR4 probe
635 12:42:19.054007 ddr clk to 1584MHz
636 12:42:19.060891 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 12:42:19.098203
638 12:42:19.098765 dmc_version 0001
639 12:42:19.104094 Check phy result
640 12:42:19.110844 INFO : End of CA training
641 12:42:19.111321 INFO : End of initialization
642 12:42:19.116378 INFO : Training has run successfully!
643 12:42:19.116854 Check phy result
644 12:42:19.122056 INFO : End of initialization
645 12:42:19.122527 INFO : End of read enable training
646 12:42:19.125438 INFO : End of fine write leveling
647 12:42:19.130964 INFO : End of Write leveling coarse delay
648 12:42:19.136437 INFO : Training has run successfully!
649 12:42:19.136923 Check phy result
650 12:42:19.137339 INFO : End of initialization
651 12:42:19.142082 INFO : End of read dq deskew training
652 12:42:19.147806 INFO : End of MPR read delay center optimization
653 12:42:19.148357 INFO : End of write delay center optimization
654 12:42:19.153536 INFO : End of read delay center optimization
655 12:42:19.159040 INFO : End of max read latency training
656 12:42:19.159599 INFO : Training has run successfully!
657 12:42:19.164677 1D training succeed
658 12:42:19.170447 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 12:42:19.216938 Check phy result
660 12:42:19.217535 INFO : End of initialization
661 12:42:19.238630 INFO : End of 2D read delay Voltage center optimization
662 12:42:19.258074 INFO : End of 2D read delay Voltage center optimization
663 12:42:19.310468 INFO : End of 2D write delay Voltage center optimization
664 12:42:19.360313 INFO : End of 2D write delay Voltage center optimization
665 12:42:19.365965 INFO : Training has run successfully!
666 12:42:19.366454
667 12:42:19.366889 channel==0
668 12:42:19.371612 RxClkDly_Margin_A0==88 ps 9
669 12:42:19.372127 TxDqDly_Margin_A0==98 ps 10
670 12:42:19.377092 RxClkDly_Margin_A1==88 ps 9
671 12:42:19.377552 TxDqDly_Margin_A1==98 ps 10
672 12:42:19.377975 TrainedVREFDQ_A0==74
673 12:42:19.382804 TrainedVREFDQ_A1==74
674 12:42:19.383268 VrefDac_Margin_A0==25
675 12:42:19.383679 DeviceVref_Margin_A0==40
676 12:42:19.388285 VrefDac_Margin_A1==25
677 12:42:19.388769 DeviceVref_Margin_A1==40
678 12:42:19.389182
679 12:42:19.389583
680 12:42:19.393911 channel==1
681 12:42:19.394382 RxClkDly_Margin_A0==98 ps 10
682 12:42:19.394800 TxDqDly_Margin_A0==88 ps 9
683 12:42:19.399576 RxClkDly_Margin_A1==88 ps 9
684 12:42:19.400085 TxDqDly_Margin_A1==98 ps 10
685 12:42:19.405072 TrainedVREFDQ_A0==77
686 12:42:19.405547 TrainedVREFDQ_A1==77
687 12:42:19.405962 VrefDac_Margin_A0==23
688 12:42:19.410836 DeviceVref_Margin_A0==37
689 12:42:19.411301 VrefDac_Margin_A1==24
690 12:42:19.416316 DeviceVref_Margin_A1==37
691 12:42:19.416776
692 12:42:19.417181 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 12:42:19.417582
694 12:42:19.449845 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 12:42:19.450420 2D training succeed
696 12:42:19.455579 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 12:42:19.461109 auto size-- 65535DDR cs0 size: 2048MB
698 12:42:19.461572 DDR cs1 size: 2048MB
699 12:42:19.466854 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 12:42:19.467315 cs0 DataBus test pass
701 12:42:19.472333 cs1 DataBus test pass
702 12:42:19.472800 cs0 AddrBus test pass
703 12:42:19.473214 cs1 AddrBus test pass
704 12:42:19.473613
705 12:42:19.477916 100bdlr_step_size ps== 420
706 12:42:19.478408 result report
707 12:42:19.483508 boot times 0Enable ddr reg access
708 12:42:19.488925 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 12:42:19.502296 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 12:42:20.075908 0.0;M3 CHK:0;cm4_sp_mode 0
711 12:42:20.076569 MVN_1=0x00000000
712 12:42:20.081481 MVN_2=0x00000000
713 12:42:20.087178 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 12:42:20.087498 OPS=0x10
715 12:42:20.087737 ring efuse init
716 12:42:20.087961 chipver efuse init
717 12:42:20.092706 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 12:42:20.098351 [0.018961 Inits done]
719 12:42:20.098780 secure task start!
720 12:42:20.099110 high task start!
721 12:42:20.102917 low task start!
722 12:42:20.103298 run into bl31
723 12:42:20.109540 NOTICE: BL31: v1.3(release):4fc40b1
724 12:42:20.117338 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 12:42:20.117650 NOTICE: BL31: G12A normal boot!
726 12:42:20.142754 NOTICE: BL31: BL33 decompress pass
727 12:42:20.148389 ERROR: Error initializing runtime service opteed_fast
728 12:42:21.381277
729 12:42:21.381684
730 12:42:21.389732 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 12:42:21.390178
732 12:42:21.390497 Model: Libre Computer AML-A311D-CC Alta
733 12:42:21.598234 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 12:42:21.621544 DRAM: 2 GiB (effective 3.8 GiB)
735 12:42:21.764516 Core: 408 devices, 31 uclasses, devicetree: separate
736 12:42:21.770357 WDT: Not starting watchdog@f0d0
737 12:42:21.802649 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 12:42:21.815101 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 12:42:21.820102 ** Bad device specification mmc 0 **
740 12:42:21.830379 Card did not respond to voltage select! : -110
741 12:42:21.838078 ** Bad device specification mmc 0 **
742 12:42:21.838554 Couldn't find partition mmc 0
743 12:42:21.846408 Card did not respond to voltage select! : -110
744 12:42:21.851972 ** Bad device specification mmc 0 **
745 12:42:21.852494 Couldn't find partition mmc 0
746 12:42:21.857070 Error: could not access storage.
747 12:42:22.199449 Net: eth0: ethernet@ff3f0000
748 12:42:22.200073 starting USB...
749 12:42:22.451252 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 12:42:22.451835 Starting the controller
751 12:42:22.458217 USB XHCI 1.10
752 12:42:24.619587 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 12:42:24.620260 bl2_stage_init 0x01
754 12:42:24.620690 bl2_stage_init 0x81
755 12:42:24.625196 hw id: 0x0000 - pwm id 0x01
756 12:42:24.625659 bl2_stage_init 0xc1
757 12:42:24.626073 bl2_stage_init 0x02
758 12:42:24.626479
759 12:42:24.630672 L0:00000000
760 12:42:24.631118 L1:20000703
761 12:42:24.631528 L2:00008067
762 12:42:24.631929 L3:14000000
763 12:42:24.636351 B2:00402000
764 12:42:24.636795 B1:e0f83180
765 12:42:24.637204
766 12:42:24.637606 TE: 58159
767 12:42:24.638006
768 12:42:24.641854 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 12:42:24.642299
770 12:42:24.642709 Board ID = 1
771 12:42:24.647591 Set A53 clk to 24M
772 12:42:24.648083 Set A73 clk to 24M
773 12:42:24.648508 Set clk81 to 24M
774 12:42:24.653243 A53 clk: 1200 MHz
775 12:42:24.653694 A73 clk: 1200 MHz
776 12:42:24.654103 CLK81: 166.6M
777 12:42:24.654500 smccc: 00012ab5
778 12:42:24.658750 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 12:42:24.664281 board id: 1
780 12:42:24.670310 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 12:42:24.680870 fw parse done
782 12:42:24.686872 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 12:42:24.729436 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 12:42:24.740223 PIEI prepare done
785 12:42:24.740695 fastboot data load
786 12:42:24.741111 fastboot data verify
787 12:42:24.745936 verify result: 266
788 12:42:24.751526 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 12:42:24.752011 LPDDR4 probe
790 12:42:24.752427 ddr clk to 1584MHz
791 12:42:24.759554 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 12:42:24.796786
793 12:42:24.797334 dmc_version 0001
794 12:42:24.803510 Check phy result
795 12:42:24.809301 INFO : End of CA training
796 12:42:24.809754 INFO : End of initialization
797 12:42:24.814904 INFO : Training has run successfully!
798 12:42:24.815361 Check phy result
799 12:42:24.820516 INFO : End of initialization
800 12:42:24.820969 INFO : End of read enable training
801 12:42:24.826106 INFO : End of fine write leveling
802 12:42:24.831709 INFO : End of Write leveling coarse delay
803 12:42:24.832193 INFO : Training has run successfully!
804 12:42:24.832604 Check phy result
805 12:42:24.837203 INFO : End of initialization
806 12:42:24.837511 INFO : End of read dq deskew training
807 12:42:24.842852 INFO : End of MPR read delay center optimization
808 12:42:24.848441 INFO : End of write delay center optimization
809 12:42:24.853991 INFO : End of read delay center optimization
810 12:42:24.854278 INFO : End of max read latency training
811 12:42:24.859641 INFO : Training has run successfully!
812 12:42:24.860083 1D training succeed
813 12:42:24.868802 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 12:42:24.916413 Check phy result
815 12:42:24.916771 INFO : End of initialization
816 12:42:24.938107 INFO : End of 2D read delay Voltage center optimization
817 12:42:24.957559 INFO : End of 2D read delay Voltage center optimization
818 12:42:25.009558 INFO : End of 2D write delay Voltage center optimization
819 12:42:25.058876 INFO : End of 2D write delay Voltage center optimization
820 12:42:25.064482 INFO : Training has run successfully!
821 12:42:25.064832
822 12:42:25.065052 channel==0
823 12:42:25.070084 RxClkDly_Margin_A0==88 ps 9
824 12:42:25.070536 TxDqDly_Margin_A0==98 ps 10
825 12:42:25.073488 RxClkDly_Margin_A1==88 ps 9
826 12:42:25.073956 TxDqDly_Margin_A1==88 ps 9
827 12:42:25.078991 TrainedVREFDQ_A0==74
828 12:42:25.079320 TrainedVREFDQ_A1==74
829 12:42:25.079545 VrefDac_Margin_A0==25
830 12:42:25.084839 DeviceVref_Margin_A0==40
831 12:42:25.085416 VrefDac_Margin_A1==25
832 12:42:25.090296 DeviceVref_Margin_A1==40
833 12:42:25.090787
834 12:42:25.091229
835 12:42:25.091667 channel==1
836 12:42:25.092141 RxClkDly_Margin_A0==88 ps 9
837 12:42:25.095821 TxDqDly_Margin_A0==88 ps 9
838 12:42:25.096329 RxClkDly_Margin_A1==88 ps 9
839 12:42:25.101516 TxDqDly_Margin_A1==88 ps 9
840 12:42:25.102026 TrainedVREFDQ_A0==77
841 12:42:25.102470 TrainedVREFDQ_A1==77
842 12:42:25.107027 VrefDac_Margin_A0==23
843 12:42:25.107507 DeviceVref_Margin_A0==37
844 12:42:25.107942 VrefDac_Margin_A1==24
845 12:42:25.112644 DeviceVref_Margin_A1==37
846 12:42:25.113121
847 12:42:25.118269 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 12:42:25.118750
849 12:42:25.146261 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000019 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 12:42:25.151847 2D training succeed
851 12:42:25.157533 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 12:42:25.158024 auto size-- 65535DDR cs0 size: 2048MB
853 12:42:25.163050 DDR cs1 size: 2048MB
854 12:42:25.163539 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 12:42:25.168661 cs0 DataBus test pass
856 12:42:25.169148 cs1 DataBus test pass
857 12:42:25.169583 cs0 AddrBus test pass
858 12:42:25.174395 cs1 AddrBus test pass
859 12:42:25.174894
860 12:42:25.175335 100bdlr_step_size ps== 420
861 12:42:25.175781 result report
862 12:42:25.179894 boot times 0Enable ddr reg access
863 12:42:25.187186 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 12:42:25.200761 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 12:42:25.774420 0.0;M3 CHK:0;cm4_sp_mode 0
866 12:42:25.775078 MVN_1=0x00000000
867 12:42:25.779779 MVN_2=0x00000000
868 12:42:25.785566 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 12:42:25.786086 OPS=0x10
870 12:42:25.786556 ring efuse init
871 12:42:25.787011 chipver efuse init
872 12:42:25.793781 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 12:42:25.794306 [0.018961 Inits done]
874 12:42:25.801381 secure task start!
875 12:42:25.801885 high task start!
876 12:42:25.802342 low task start!
877 12:42:25.802799 run into bl31
878 12:42:25.808048 NOTICE: BL31: v1.3(release):4fc40b1
879 12:42:25.814922 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 12:42:25.815461 NOTICE: BL31: G12A normal boot!
881 12:42:25.841188 NOTICE: BL31: BL33 decompress pass
882 12:42:25.846871 ERROR: Error initializing runtime service opteed_fast
883 12:42:27.079945
884 12:42:27.080419
885 12:42:27.087258 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 12:42:27.087753
887 12:42:27.088127 Model: Libre Computer AML-A311D-CC Alta
888 12:42:27.296639 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 12:42:27.320137 DRAM: 2 GiB (effective 3.8 GiB)
890 12:42:27.463148 Core: 408 devices, 31 uclasses, devicetree: separate
891 12:42:27.469041 WDT: Not starting watchdog@f0d0
892 12:42:27.501257 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 12:42:27.513742 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 12:42:27.518639 ** Bad device specification mmc 0 **
895 12:42:27.528943 Card did not respond to voltage select! : -110
896 12:42:27.536664 ** Bad device specification mmc 0 **
897 12:42:27.537159 Couldn't find partition mmc 0
898 12:42:27.545038 Card did not respond to voltage select! : -110
899 12:42:27.550465 ** Bad device specification mmc 0 **
900 12:42:27.550954 Couldn't find partition mmc 0
901 12:42:27.555515 Error: could not access storage.
902 12:42:27.897998 Net: eth0: ethernet@ff3f0000
903 12:42:27.898645 starting USB...
904 12:42:28.149927 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 12:42:28.150555 Starting the controller
906 12:42:28.156820 USB XHCI 1.10
907 12:42:29.710931 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 12:42:29.719386 scanning usb for storage devices... 0 Storage Device(s) found
910 12:42:29.770983 Hit any key to stop autoboot: 1
911 12:42:29.771841 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 12:42:29.772517 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 12:42:29.773043 Setting prompt string to ['=>']
914 12:42:29.773578 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 12:42:29.786789 0
916 12:42:29.787715 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 12:42:29.788295 Sending with 10 millisecond of delay
919 12:42:30.923416 => setenv autoload no
920 12:42:30.933989 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 12:42:30.936560 setenv autoload no
922 12:42:30.937034 Sending with 10 millisecond of delay
924 12:42:32.733516 => setenv initrd_high 0xffffffff
925 12:42:32.744354 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 12:42:32.745286 setenv initrd_high 0xffffffff
927 12:42:32.746049 Sending with 10 millisecond of delay
929 12:42:34.362515 => setenv fdt_high 0xffffffff
930 12:42:34.373181 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 12:42:34.373739 setenv fdt_high 0xffffffff
932 12:42:34.374235 Sending with 10 millisecond of delay
934 12:42:34.665802 => dhcp
935 12:42:34.676616 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 12:42:34.677533 dhcp
937 12:42:34.677984 Speed: 1000, full duplex
938 12:42:34.678504 BOOTP broadcast 1
939 12:42:34.924580 BOOTP broadcast 2
940 12:42:34.945365 DHCP client bound to address 192.168.6.33 (268 ms)
941 12:42:34.946168 Sending with 10 millisecond of delay
943 12:42:36.623007 => setenv serverip 192.168.6.2
944 12:42:36.633777 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
945 12:42:36.634685 setenv serverip 192.168.6.2
946 12:42:36.635411 Sending with 10 millisecond of delay
948 12:42:40.360061 => tftpboot 0x01080000 745160/tftp-deploy-1f36vw0e/kernel/uImage
949 12:42:40.371045 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
950 12:42:40.372024 tftpboot 0x01080000 745160/tftp-deploy-1f36vw0e/kernel/uImage
951 12:42:40.372530 Speed: 1000, full duplex
952 12:42:40.373006 Using ethernet@ff3f0000 device
953 12:42:40.373828 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
954 12:42:40.379437 Filename '745160/tftp-deploy-1f36vw0e/kernel/uImage'.
955 12:42:40.383276 Load address: 0x1080000
956 12:42:43.754364 Loading: *################################################## 37.3 MiB
957 12:42:43.755129 11.1 MiB/s
958 12:42:43.755670 done
959 12:42:43.758639 Bytes transferred = 39127616 (2550a40 hex)
960 12:42:43.759510 Sending with 10 millisecond of delay
962 12:42:48.448062 => tftpboot 0x08000000 745160/tftp-deploy-1f36vw0e/ramdisk/ramdisk.cpio.gz.uboot
963 12:42:48.458811 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
964 12:42:48.459363 tftpboot 0x08000000 745160/tftp-deploy-1f36vw0e/ramdisk/ramdisk.cpio.gz.uboot
965 12:42:48.459645 Speed: 1000, full duplex
966 12:42:48.459878 Using ethernet@ff3f0000 device
967 12:42:48.461502 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
968 12:42:48.470295 Filename '745160/tftp-deploy-1f36vw0e/ramdisk/ramdisk.cpio.gz.uboot'.
969 12:42:48.470675 Load address: 0x8000000
970 12:42:56.343106 Loading: *###T ############################################## UDP wrong checksum 00000005 00005005
971 12:43:01.344941 T UDP wrong checksum 00000005 00005005
972 12:43:11.346375 T T UDP wrong checksum 00000005 00005005
973 12:43:31.351050 T T T T UDP wrong checksum 00000005 00005005
974 12:43:46.354986 T T
975 12:43:46.355431 Retry count exceeded; starting again
977 12:43:46.356340 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
980 12:43:46.357266 end: 2.4 uboot-commands (duration 00:01:49) [common]
982 12:43:46.358096 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
984 12:43:46.358686 end: 2 uboot-action (duration 00:01:49) [common]
986 12:43:46.360643 Cleaning after the job
987 12:43:46.361025 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/ramdisk
988 12:43:46.361961 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/kernel
989 12:43:46.385557 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/dtb
990 12:43:46.386477 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745160/tftp-deploy-1f36vw0e/modules
991 12:43:46.409030 start: 4.1 power-off (timeout 00:00:30) [common]
992 12:43:46.409756 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
993 12:43:46.443451 >> OK - accepted request
994 12:43:46.445561 Returned 0 in 0 seconds
995 12:43:46.546430 end: 4.1 power-off (duration 00:00:00) [common]
997 12:43:46.547500 start: 4.2 read-feedback (timeout 00:10:00) [common]
998 12:43:46.548284 Listened to connection for namespace 'common' for up to 1s
999 12:43:47.549207 Finalising connection for namespace 'common'
1000 12:43:47.549713 Disconnecting from shell: Finalise
1001 12:43:47.550023 =>
1002 12:43:47.650838 end: 4.2 read-feedback (duration 00:00:01) [common]
1003 12:43:47.651611 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/745160
1004 12:43:47.937804 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/745160
1005 12:43:47.938409 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.