Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 12:38:19.286209 lava-dispatcher, installed at version: 2024.01
2 12:38:19.286990 start: 0 validate
3 12:38:19.287482 Start time: 2024-09-19 12:38:19.287451+00:00 (UTC)
4 12:38:19.288083 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 12:38:19.288640 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 12:38:19.331257 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 12:38:19.331817 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 12:38:19.360729 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 12:38:19.361491 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 12:38:20.410594 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 12:38:20.411094 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 12:38:20.446342 validate duration: 1.16
14 12:38:20.447212 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:38:20.447567 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:38:20.447878 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:38:20.448586 Not decompressing ramdisk as can be used compressed.
18 12:38:20.449018 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 12:38:20.449312 saving as /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/ramdisk/rootfs.cpio.gz
20 12:38:20.449594 total size: 8181887 (7 MB)
21 12:38:20.486389 progress 0 % (0 MB)
22 12:38:20.497339 progress 5 % (0 MB)
23 12:38:20.507739 progress 10 % (0 MB)
24 12:38:20.519202 progress 15 % (1 MB)
25 12:38:20.525114 progress 20 % (1 MB)
26 12:38:20.531040 progress 25 % (1 MB)
27 12:38:20.536345 progress 30 % (2 MB)
28 12:38:20.542092 progress 35 % (2 MB)
29 12:38:20.547361 progress 40 % (3 MB)
30 12:38:20.553145 progress 45 % (3 MB)
31 12:38:20.558730 progress 50 % (3 MB)
32 12:38:20.564494 progress 55 % (4 MB)
33 12:38:20.569817 progress 60 % (4 MB)
34 12:38:20.575525 progress 65 % (5 MB)
35 12:38:20.580925 progress 70 % (5 MB)
36 12:38:20.586594 progress 75 % (5 MB)
37 12:38:20.591845 progress 80 % (6 MB)
38 12:38:20.597562 progress 85 % (6 MB)
39 12:38:20.602886 progress 90 % (7 MB)
40 12:38:20.608659 progress 95 % (7 MB)
41 12:38:20.613965 progress 100 % (7 MB)
42 12:38:20.614623 7 MB downloaded in 0.17 s (47.29 MB/s)
43 12:38:20.615151 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:38:20.616050 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:38:20.616352 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:38:20.616623 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:38:20.617088 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/kernel/Image
49 12:38:20.617353 saving as /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/kernel/Image
50 12:38:20.617568 total size: 45482496 (43 MB)
51 12:38:20.617781 No compression specified
52 12:38:20.657933 progress 0 % (0 MB)
53 12:38:20.685857 progress 5 % (2 MB)
54 12:38:20.713963 progress 10 % (4 MB)
55 12:38:20.741917 progress 15 % (6 MB)
56 12:38:20.770056 progress 20 % (8 MB)
57 12:38:20.798014 progress 25 % (10 MB)
58 12:38:20.825449 progress 30 % (13 MB)
59 12:38:20.853133 progress 35 % (15 MB)
60 12:38:20.881299 progress 40 % (17 MB)
61 12:38:20.909012 progress 45 % (19 MB)
62 12:38:20.936715 progress 50 % (21 MB)
63 12:38:20.963794 progress 55 % (23 MB)
64 12:38:20.990926 progress 60 % (26 MB)
65 12:38:21.018718 progress 65 % (28 MB)
66 12:38:21.045935 progress 70 % (30 MB)
67 12:38:21.073614 progress 75 % (32 MB)
68 12:38:21.101046 progress 80 % (34 MB)
69 12:38:21.128882 progress 85 % (36 MB)
70 12:38:21.156728 progress 90 % (39 MB)
71 12:38:21.183889 progress 95 % (41 MB)
72 12:38:21.210931 progress 100 % (43 MB)
73 12:38:21.211448 43 MB downloaded in 0.59 s (73.04 MB/s)
74 12:38:21.211939 end: 1.2.1 http-download (duration 00:00:01) [common]
76 12:38:21.212796 end: 1.2 download-retry (duration 00:00:01) [common]
77 12:38:21.213074 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:38:21.213339 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:38:21.213810 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 12:38:21.214079 saving as /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 12:38:21.214290 total size: 53209 (0 MB)
82 12:38:21.214500 No compression specified
83 12:38:21.257933 progress 61 % (0 MB)
84 12:38:21.258786 progress 100 % (0 MB)
85 12:38:21.259357 0 MB downloaded in 0.05 s (1.13 MB/s)
86 12:38:21.259854 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:38:21.260743 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:38:21.261012 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:38:21.261312 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:38:21.261803 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/modules.tar.xz
92 12:38:21.262059 saving as /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/modules/modules.tar
93 12:38:21.262282 total size: 11582224 (11 MB)
94 12:38:21.262496 Using unxz to decompress xz
95 12:38:21.300117 progress 0 % (0 MB)
96 12:38:21.367379 progress 5 % (0 MB)
97 12:38:21.453222 progress 10 % (1 MB)
98 12:38:21.539150 progress 15 % (1 MB)
99 12:38:21.620706 progress 20 % (2 MB)
100 12:38:21.698044 progress 25 % (2 MB)
101 12:38:21.776653 progress 30 % (3 MB)
102 12:38:21.848416 progress 35 % (3 MB)
103 12:38:21.928948 progress 40 % (4 MB)
104 12:38:22.012465 progress 45 % (5 MB)
105 12:38:22.094774 progress 50 % (5 MB)
106 12:38:22.183315 progress 55 % (6 MB)
107 12:38:22.262272 progress 60 % (6 MB)
108 12:38:22.342736 progress 65 % (7 MB)
109 12:38:22.423881 progress 70 % (7 MB)
110 12:38:22.506302 progress 75 % (8 MB)
111 12:38:22.597827 progress 80 % (8 MB)
112 12:38:22.696995 progress 85 % (9 MB)
113 12:38:22.771812 progress 90 % (9 MB)
114 12:38:22.845272 progress 95 % (10 MB)
115 12:38:22.920824 progress 100 % (11 MB)
116 12:38:22.934255 11 MB downloaded in 1.67 s (6.61 MB/s)
117 12:38:22.934857 end: 1.4.1 http-download (duration 00:00:02) [common]
119 12:38:22.935684 end: 1.4 download-retry (duration 00:00:02) [common]
120 12:38:22.935954 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 12:38:22.936603 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 12:38:22.937185 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:38:22.937746 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 12:38:22.938779 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv
125 12:38:22.939686 makedir: /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin
126 12:38:22.940446 makedir: /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/tests
127 12:38:22.941179 makedir: /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/results
128 12:38:22.941855 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-add-keys
129 12:38:22.942870 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-add-sources
130 12:38:22.943873 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-background-process-start
131 12:38:22.945009 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-background-process-stop
132 12:38:22.946150 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-common-functions
133 12:38:22.947223 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-echo-ipv4
134 12:38:22.948298 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-install-packages
135 12:38:22.951742 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-installed-packages
136 12:38:22.952816 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-os-build
137 12:38:22.953809 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-probe-channel
138 12:38:22.954793 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-probe-ip
139 12:38:22.955775 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-target-ip
140 12:38:22.956808 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-target-mac
141 12:38:22.957833 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-target-storage
142 12:38:22.958879 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-test-case
143 12:38:22.959871 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-test-event
144 12:38:22.960904 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-test-feedback
145 12:38:22.961930 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-test-raise
146 12:38:22.962903 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-test-reference
147 12:38:22.963879 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-test-runner
148 12:38:22.964902 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-test-set
149 12:38:22.965881 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-test-shell
150 12:38:22.966879 Updating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-install-packages (oe)
151 12:38:22.967928 Updating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/bin/lava-installed-packages (oe)
152 12:38:22.968892 Creating /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/environment
153 12:38:22.969671 LAVA metadata
154 12:38:22.970202 - LAVA_JOB_ID=745004
155 12:38:22.970673 - LAVA_DISPATCHER_IP=192.168.6.2
156 12:38:22.971412 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 12:38:22.973399 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 12:38:22.974007 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 12:38:22.974421 skipped lava-vland-overlay
160 12:38:22.974909 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 12:38:22.975417 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 12:38:22.975844 skipped lava-multinode-overlay
163 12:38:22.976238 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 12:38:22.976500 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 12:38:22.976759 Loading test definitions
166 12:38:22.977061 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 12:38:22.977293 Using /lava-745004 at stage 0
168 12:38:22.978555 uuid=745004_1.5.2.4.1 testdef=None
169 12:38:22.978879 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 12:38:22.979152 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 12:38:22.981113 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 12:38:22.981937 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 12:38:22.984315 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 12:38:22.985161 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 12:38:22.987432 runner path: /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/0/tests/0_dmesg test_uuid 745004_1.5.2.4.1
178 12:38:22.988033 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 12:38:22.988824 Creating lava-test-runner.conf files
181 12:38:22.989033 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/745004/lava-overlay-sjhld5sv/lava-745004/0 for stage 0
182 12:38:22.989390 - 0_dmesg
183 12:38:22.989746 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 12:38:22.990029 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 12:38:23.015096 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 12:38:23.015538 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 12:38:23.015810 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 12:38:23.016112 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 12:38:23.016385 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 12:38:24.039305 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 12:38:24.039830 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 12:38:24.040413 extracting modules file /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/modules/modules.tar to /var/lib/lava/dispatcher/tmp/745004/extract-overlay-ramdisk-kabq5h7j/ramdisk
193 12:38:25.392752 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 12:38:25.393239 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 12:38:25.393527 [common] Applying overlay /var/lib/lava/dispatcher/tmp/745004/compress-overlay-qa1wtic8/overlay-1.5.2.5.tar.gz to ramdisk
196 12:38:25.393760 [common] Applying overlay /var/lib/lava/dispatcher/tmp/745004/compress-overlay-qa1wtic8/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/745004/extract-overlay-ramdisk-kabq5h7j/ramdisk
197 12:38:25.424488 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 12:38:25.424932 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 12:38:25.425202 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 12:38:25.425431 Converting downloaded kernel to a uImage
201 12:38:25.425740 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/kernel/Image /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/kernel/uImage
202 12:38:25.895388 output: Image Name:
203 12:38:25.895802 output: Created: Thu Sep 19 12:38:25 2024
204 12:38:25.896044 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 12:38:25.896254 output: Data Size: 45482496 Bytes = 44416.50 KiB = 43.38 MiB
206 12:38:25.896457 output: Load Address: 01080000
207 12:38:25.896657 output: Entry Point: 01080000
208 12:38:25.896854 output:
209 12:38:25.897189 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 12:38:25.897455 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 12:38:25.897726 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 12:38:25.897979 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 12:38:25.898235 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 12:38:25.898488 Building ramdisk /var/lib/lava/dispatcher/tmp/745004/extract-overlay-ramdisk-kabq5h7j/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/745004/extract-overlay-ramdisk-kabq5h7j/ramdisk
215 12:38:28.348277 >> 180988 blocks
216 12:38:36.872679 Adding RAMdisk u-boot header.
217 12:38:36.873105 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/745004/extract-overlay-ramdisk-kabq5h7j/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/745004/extract-overlay-ramdisk-kabq5h7j/ramdisk.cpio.gz.uboot
218 12:38:37.143946 output: Image Name:
219 12:38:37.144602 output: Created: Thu Sep 19 12:38:36 2024
220 12:38:37.145023 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 12:38:37.145427 output: Data Size: 26021287 Bytes = 25411.41 KiB = 24.82 MiB
222 12:38:37.145825 output: Load Address: 00000000
223 12:38:37.146223 output: Entry Point: 00000000
224 12:38:37.146615 output:
225 12:38:37.147676 rename /var/lib/lava/dispatcher/tmp/745004/extract-overlay-ramdisk-kabq5h7j/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/ramdisk/ramdisk.cpio.gz.uboot
226 12:38:37.148458 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 12:38:37.149006 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 12:38:37.149534 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 12:38:37.149992 No LXC device requested
230 12:38:37.150497 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 12:38:37.151001 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 12:38:37.151487 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 12:38:37.151899 Checking files for TFTP limit of 4294967296 bytes.
234 12:38:37.154675 end: 1 tftp-deploy (duration 00:00:17) [common]
235 12:38:37.155282 start: 2 uboot-action (timeout 00:05:00) [common]
236 12:38:37.155807 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 12:38:37.156346 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 12:38:37.156862 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 12:38:37.157395 Using kernel file from prepare-kernel: 745004/tftp-deploy-5oark332/kernel/uImage
240 12:38:37.158012 substitutions:
241 12:38:37.158427 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 12:38:37.158834 - {DTB_ADDR}: 0x01070000
243 12:38:37.159233 - {DTB}: 745004/tftp-deploy-5oark332/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 12:38:37.159636 - {INITRD}: 745004/tftp-deploy-5oark332/ramdisk/ramdisk.cpio.gz.uboot
245 12:38:37.160068 - {KERNEL_ADDR}: 0x01080000
246 12:38:37.160471 - {KERNEL}: 745004/tftp-deploy-5oark332/kernel/uImage
247 12:38:37.160874 - {LAVA_MAC}: None
248 12:38:37.161308 - {PRESEED_CONFIG}: None
249 12:38:37.161711 - {PRESEED_LOCAL}: None
250 12:38:37.162102 - {RAMDISK_ADDR}: 0x08000000
251 12:38:37.162496 - {RAMDISK}: 745004/tftp-deploy-5oark332/ramdisk/ramdisk.cpio.gz.uboot
252 12:38:37.162896 - {ROOT_PART}: None
253 12:38:37.163286 - {ROOT}: None
254 12:38:37.163674 - {SERVER_IP}: 192.168.6.2
255 12:38:37.164103 - {TEE_ADDR}: 0x83000000
256 12:38:37.164503 - {TEE}: None
257 12:38:37.164894 Parsed boot commands:
258 12:38:37.165274 - setenv autoload no
259 12:38:37.165664 - setenv initrd_high 0xffffffff
260 12:38:37.166050 - setenv fdt_high 0xffffffff
261 12:38:37.166434 - dhcp
262 12:38:37.166819 - setenv serverip 192.168.6.2
263 12:38:37.167203 - tftpboot 0x01080000 745004/tftp-deploy-5oark332/kernel/uImage
264 12:38:37.167592 - tftpboot 0x08000000 745004/tftp-deploy-5oark332/ramdisk/ramdisk.cpio.gz.uboot
265 12:38:37.168014 - tftpboot 0x01070000 745004/tftp-deploy-5oark332/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 12:38:37.168479 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 12:38:37.168888 - bootm 0x01080000 0x08000000 0x01070000
268 12:38:37.169408 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 12:38:37.170897 start: 2.3 connect-device (timeout 00:05:00) [common]
271 12:38:37.171347 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 12:38:37.186388 Setting prompt string to ['lava-test: # ']
273 12:38:37.187864 end: 2.3 connect-device (duration 00:00:00) [common]
274 12:38:37.188549 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 12:38:37.189090 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 12:38:37.189722 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 12:38:37.190853 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 12:38:37.224552 >> OK - accepted request
279 12:38:37.226598 Returned 0 in 0 seconds
280 12:38:37.327747 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 12:38:37.329425 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 12:38:37.329981 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 12:38:37.330486 Setting prompt string to ['Hit any key to stop autoboot']
285 12:38:37.330920 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 12:38:37.332524 Trying 192.168.56.21...
287 12:38:37.333010 Connected to conserv1.
288 12:38:37.333425 Escape character is '^]'.
289 12:38:37.333842
290 12:38:37.334259 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 12:38:37.334677
292 12:38:45.221965 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 12:38:45.222592 bl2_stage_init 0x01
294 12:38:45.223025 bl2_stage_init 0x81
295 12:38:45.227523 hw id: 0x0000 - pwm id 0x01
296 12:38:45.228045 bl2_stage_init 0xc1
297 12:38:45.228476 bl2_stage_init 0x02
298 12:38:45.228889
299 12:38:45.233205 L0:00000000
300 12:38:45.233635 L1:00000703
301 12:38:45.234030 L2:00008067
302 12:38:45.234421 L3:15000000
303 12:38:45.234814 S1:00000000
304 12:38:45.235492 B2:20282000
305 12:38:45.239967 B1:a0f83180
306 12:38:45.240423
307 12:38:45.240822 TE: 67969
308 12:38:45.241214
309 12:38:45.245581 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 12:38:45.246010
311 12:38:45.246404 Board ID = 1
312 12:38:45.251169 Set cpu clk to 24M
313 12:38:45.251645 Set clk81 to 24M
314 12:38:45.252090 Use GP1_pll as DSU clk.
315 12:38:45.256726 DSU clk: 1200 Mhz
316 12:38:45.257154 CPU clk: 1200 MHz
317 12:38:45.257547 Set clk81 to 166.6M
318 12:38:45.262325 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 12:38:45.267913 board id: 1
320 12:38:45.273250 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 12:38:45.283822 fw parse done
322 12:38:45.289768 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 12:38:45.332481 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 12:38:45.343363 PIEI prepare done
325 12:38:45.343800 fastboot data load
326 12:38:45.344232 fastboot data verify
327 12:38:45.349031 verify result: 266
328 12:38:45.354546 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 12:38:45.354846 LPDDR4 probe
330 12:38:45.355060 ddr clk to 1584MHz
331 12:38:45.362525 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 12:38:45.399837
333 12:38:45.400242 dmc_version 0001
334 12:38:45.406449 Check phy result
335 12:38:45.412368 INFO : End of CA training
336 12:38:45.412665 INFO : End of initialization
337 12:38:45.418000 INFO : Training has run successfully!
338 12:38:45.418295 Check phy result
339 12:38:45.423544 INFO : End of initialization
340 12:38:45.423841 INFO : End of read enable training
341 12:38:45.429241 INFO : End of fine write leveling
342 12:38:45.434771 INFO : End of Write leveling coarse delay
343 12:38:45.435062 INFO : Training has run successfully!
344 12:38:45.435276 Check phy result
345 12:38:45.440358 INFO : End of initialization
346 12:38:45.440659 INFO : End of read dq deskew training
347 12:38:45.445985 INFO : End of MPR read delay center optimization
348 12:38:45.451678 INFO : End of write delay center optimization
349 12:38:45.457333 INFO : End of read delay center optimization
350 12:38:45.457627 INFO : End of max read latency training
351 12:38:45.462770 INFO : Training has run successfully!
352 12:38:45.463065 1D training succeed
353 12:38:45.471950 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 12:38:45.518793 Check phy result
355 12:38:45.519160 INFO : End of initialization
356 12:38:45.541097 INFO : End of 2D read delay Voltage center optimization
357 12:38:45.561183 INFO : End of 2D read delay Voltage center optimization
358 12:38:45.612977 INFO : End of 2D write delay Voltage center optimization
359 12:38:45.662284 INFO : End of 2D write delay Voltage center optimization
360 12:38:45.667669 INFO : Training has run successfully!
361 12:38:45.667967
362 12:38:45.668236 channel==0
363 12:38:45.673321 RxClkDly_Margin_A0==78 ps 8
364 12:38:45.673651 TxDqDly_Margin_A0==98 ps 10
365 12:38:45.678892 RxClkDly_Margin_A1==88 ps 9
366 12:38:45.679184 TxDqDly_Margin_A1==98 ps 10
367 12:38:45.679399 TrainedVREFDQ_A0==74
368 12:38:45.684470 TrainedVREFDQ_A1==74
369 12:38:45.684772 VrefDac_Margin_A0==24
370 12:38:45.684989 DeviceVref_Margin_A0==40
371 12:38:45.690073 VrefDac_Margin_A1==23
372 12:38:45.690363 DeviceVref_Margin_A1==40
373 12:38:45.690580
374 12:38:45.690795
375 12:38:45.695687 channel==1
376 12:38:45.695975 RxClkDly_Margin_A0==88 ps 9
377 12:38:45.696363 TxDqDly_Margin_A0==88 ps 9
378 12:38:45.701351 RxClkDly_Margin_A1==78 ps 8
379 12:38:45.701783 TxDqDly_Margin_A1==78 ps 8
380 12:38:45.706866 TrainedVREFDQ_A0==75
381 12:38:45.707295 TrainedVREFDQ_A1==75
382 12:38:45.707688 VrefDac_Margin_A0==20
383 12:38:45.712693 DeviceVref_Margin_A0==39
384 12:38:45.713121 VrefDac_Margin_A1==22
385 12:38:45.718264 DeviceVref_Margin_A1==39
386 12:38:45.718683
387 12:38:45.719082 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 12:38:45.719471
389 12:38:45.751699 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 12:38:45.752276 2D training succeed
391 12:38:45.757338 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 12:38:45.762883 auto size-- 65535DDR cs0 size: 2048MB
393 12:38:45.763312 DDR cs1 size: 2048MB
394 12:38:45.768473 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 12:38:45.768903 cs0 DataBus test pass
396 12:38:45.774120 cs1 DataBus test pass
397 12:38:45.774538 cs0 AddrBus test pass
398 12:38:45.774926 cs1 AddrBus test pass
399 12:38:45.775316
400 12:38:45.779714 100bdlr_step_size ps== 478
401 12:38:45.780177 result report
402 12:38:45.785280 boot times 0Enable ddr reg access
403 12:38:45.791036 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 12:38:45.804459 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 12:38:46.458852 bl2z: ptr: 05129330, size: 00001e40
406 12:38:46.464941 0.0;M3 CHK:0;cm4_sp_mode 0
407 12:38:46.465406 MVN_1=0x00000000
408 12:38:46.465813 MVN_2=0x00000000
409 12:38:46.476455 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 12:38:46.476914 OPS=0x04
411 12:38:46.477316 ring efuse init
412 12:38:46.482050 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 12:38:46.482496 [0.017319 Inits done]
414 12:38:46.482891 secure task start!
415 12:38:46.489981 high task start!
416 12:38:46.490418 low task start!
417 12:38:46.490812 run into bl31
418 12:38:46.498603 NOTICE: BL31: v1.3(release):4fc40b1
419 12:38:46.506510 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 12:38:46.506949 NOTICE: BL31: G12A normal boot!
421 12:38:46.521906 NOTICE: BL31: BL33 decompress pass
422 12:38:46.527611 ERROR: Error initializing runtime service opteed_fast
423 12:38:47.773875 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 12:38:47.774471 bl2_stage_init 0x01
425 12:38:47.774901 bl2_stage_init 0x81
426 12:38:47.779463 hw id: 0x0000 - pwm id 0x01
427 12:38:47.779941 bl2_stage_init 0xc1
428 12:38:47.785055 bl2_stage_init 0x02
429 12:38:47.785570
430 12:38:47.785969 L0:00000000
431 12:38:47.786356 L1:00000703
432 12:38:47.786741 L2:00008067
433 12:38:47.787123 L3:15000000
434 12:38:47.790578 S1:00000000
435 12:38:47.791000 B2:20282000
436 12:38:47.791388 B1:a0f83180
437 12:38:47.791769
438 12:38:47.792198 TE: 68791
439 12:38:47.792587
440 12:38:47.796284 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 12:38:47.796722
442 12:38:47.801978 Board ID = 1
443 12:38:47.802403 Set cpu clk to 24M
444 12:38:47.802793 Set clk81 to 24M
445 12:38:47.807394 Use GP1_pll as DSU clk.
446 12:38:47.807812 DSU clk: 1200 Mhz
447 12:38:47.808238 CPU clk: 1200 MHz
448 12:38:47.813200 Set clk81 to 166.6M
449 12:38:47.818655 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 12:38:47.819076 board id: 1
451 12:38:47.825825 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 12:38:47.836647 fw parse done
453 12:38:47.842461 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 12:38:47.885092 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 12:38:47.896026 PIEI prepare done
456 12:38:47.896484 fastboot data load
457 12:38:47.896878 fastboot data verify
458 12:38:47.901608 verify result: 266
459 12:38:47.907587 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 12:38:47.908053 LPDDR4 probe
461 12:38:47.908447 ddr clk to 1584MHz
462 12:38:49.273330 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, par SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 12:38:49.274017 bl2_stage_init 0x01
464 12:38:49.274476 bl2_stage_init 0x81
465 12:38:49.278896 hw id: 0x0000 - pwm id 0x01
466 12:38:49.279434 bl2_stage_init 0xc1
467 12:38:49.284524 bl2_stage_init 0x02
468 12:38:49.285021
469 12:38:49.285477 L0:00000000
470 12:38:49.285889 L1:00000703
471 12:38:49.286321 L2:00008067
472 12:38:49.286757 L3:15000000
473 12:38:49.290050 S1:00000000
474 12:38:49.290551 B2:20282000
475 12:38:49.290973 B1:a0f83180
476 12:38:49.291385
477 12:38:49.291826 TE: 70009
478 12:38:49.292296
479 12:38:49.295725 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 12:38:49.296452
481 12:38:49.301232 Board ID = 1
482 12:38:49.301755 Set cpu clk to 24M
483 12:38:49.302188 Set clk81 to 24M
484 12:38:49.306916 Use GP1_pll as DSU clk.
485 12:38:49.307586 DSU clk: 1200 Mhz
486 12:38:49.308194 CPU clk: 1200 MHz
487 12:38:49.312613 Set clk81 to 166.6M
488 12:38:49.318127 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 12:38:49.318630 board id: 1
490 12:38:49.325319 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 12:38:49.336019 fw parse done
492 12:38:49.341951 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 12:38:49.384642 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 12:38:49.395563 PIEI prepare done
495 12:38:49.396121 fastboot data load
496 12:38:49.396564 fastboot data verify
497 12:38:49.401216 verify result: 266
498 12:38:49.406829 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 12:38:49.407348 LPDDR4 probe
500 12:38:49.407774 ddr clk to 1584MHz
501 12:38:49.413787 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 12:38:49.452021
503 12:38:49.452573 dmc_version 0001
504 12:38:49.457681 Check phy result
505 12:38:49.464606 INFO : End of CA training
506 12:38:49.465153 INFO : End of initialization
507 12:38:49.470161 INFO : Training has run successfully!
508 12:38:49.470676 Check phy result
509 12:38:49.475925 INFO : End of initialization
510 12:38:49.476504 INFO : End of read enable training
511 12:38:49.479075 INFO : End of fine write leveling
512 12:38:49.484677 INFO : End of Write leveling coarse delay
513 12:38:49.490350 INFO : Training has run successfully!
514 12:38:49.490895 Check phy result
515 12:38:49.491327 INFO : End of initialization
516 12:38:49.495925 INFO : End of read dq deskew training
517 12:38:49.501525 INFO : End of MPR read delay center optimization
518 12:38:49.502038 INFO : End of write delay center optimization
519 12:38:49.507108 INFO : End of read delay center optimization
520 12:38:49.512720 INFO : End of max read latency training
521 12:38:49.513236 INFO : Training has run successfully!
522 12:38:49.518334 1D training succeed
523 12:38:49.524274 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 12:38:49.571955 Check phy result
525 12:38:49.572433 INFO : End of initialization
526 12:38:49.594214 INFO : End of 2D read delay Voltage center optimization
527 12:38:49.613299 INFO : End of 2D read delay Voltage center optimization
528 12:38:49.665185 INFO : End of 2D write delay Voltage center optimization
529 12:38:49.714357 INFO : End of 2D write delay Voltage center optimization
530 12:38:49.719967 INFO : Training has run successfully!
531 12:38:49.720542
532 12:38:49.721017 channel==0
533 12:38:49.725535 RxClkDly_Margin_A0==78 ps 8
534 12:38:49.726047 TxDqDly_Margin_A0==98 ps 10
535 12:38:49.731118 RxClkDly_Margin_A1==88 ps 9
536 12:38:49.731637 TxDqDly_Margin_A1==98 ps 10
537 12:38:49.732098 TrainedVREFDQ_A0==74
538 12:38:49.736699 TrainedVREFDQ_A1==74
539 12:38:49.737192 VrefDac_Margin_A0==23
540 12:38:49.737609 DeviceVref_Margin_A0==40
541 12:38:49.742293 VrefDac_Margin_A1==23
542 12:38:49.742780 DeviceVref_Margin_A1==40
543 12:38:49.743191
544 12:38:49.743599
545 12:38:49.747958 channel==1
546 12:38:49.748478 RxClkDly_Margin_A0==88 ps 9
547 12:38:49.748893 TxDqDly_Margin_A0==98 ps 10
548 12:38:49.753577 RxClkDly_Margin_A1==78 ps 8
549 12:38:49.754137 TxDqDly_Margin_A1==88 ps 9
550 12:38:49.759115 TrainedVREFDQ_A0==78
551 12:38:49.759651 TrainedVREFDQ_A1==75
552 12:38:49.760133 VrefDac_Margin_A0==23
553 12:38:49.764710 DeviceVref_Margin_A0==36
554 12:38:49.765215 VrefDac_Margin_A1==20
555 12:38:49.770299 DeviceVref_Margin_A1==38
556 12:38:49.770806
557 12:38:49.771265 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 12:38:49.771708
559 12:38:49.804047 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000016 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
560 12:38:49.804832 2D training succeed
561 12:38:49.809618 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 12:38:49.815110 auto size-- 65535DDR cs0 size: 2048MB
563 12:38:49.815644 DDR cs1 size: 2048MB
564 12:38:49.820743 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 12:38:49.821253 cs0 DataBus test pass
566 12:38:49.826369 cs1 DataBus test pass
567 12:38:49.827040 cs0 AddrBus test pass
568 12:38:49.827612 cs1 AddrBus test pass
569 12:38:49.828203
570 12:38:49.832081 100bdlr_step_size ps== 478
571 12:38:49.832744 result report
572 12:38:49.837543 boot times 0Enable ddr reg access
573 12:38:49.842808 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 12:38:49.856645 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 12:38:50.511882 bl2z: ptr: 05129330, size: 00001e40
576 12:38:50.518899 0.0;M3 CHK:0;cm4_sp_mode 0
577 12:38:50.519583 MVN_1=0x00000000
578 12:38:50.520190 MVN_2=0x00000000
579 12:38:50.530384 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 12:38:50.531077 OPS=0x04
581 12:38:50.531652 ring efuse init
582 12:38:50.536045 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 12:38:50.536573 [0.017310 Inits done]
584 12:38:50.537018 secure task start!
585 12:38:50.543680 high task start!
586 12:38:50.544195 low task start!
587 12:38:50.544646 run into bl31
588 12:38:50.552372 NOTICE: BL31: v1.3(release):4fc40b1
589 12:38:50.560182 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 12:38:50.560683 NOTICE: BL31: G12A normal boot!
591 12:38:50.575613 NOTICE: BL31: BL33 decompress pass
592 12:38:50.581316 ERROR: Error initializing runtime service opteed_fast
593 12:38:51.825627 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 12:38:51.826420 bl2_stage_init 0x01
595 12:38:51.826979 bl2_stage_init 0x81
596 12:38:51.831303 hw id: 0x0000 - pwm id 0x01
597 12:38:51.831969 bl2_stage_init 0xc1
598 12:38:51.832611 bl2_stage_init 0x02
599 12:38:51.833171
600 12:38:51.836838 L0:00000000
601 12:38:51.837486 L1:00000703
602 12:38:51.838307 L2:00008067
603 12:38:51.838898 L3:15000000
604 12:38:51.839457 S1:00000000
605 12:38:51.840449 B2:20282000
606 12:38:51.843527 B1:a0f83180
607 12:38:51.844062
608 12:38:51.844511 TE: 71123
609 12:38:51.844955
610 12:38:51.849144 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 12:38:51.849649
612 12:38:51.850076 Board ID = 1
613 12:38:51.854708 Set cpu clk to 24M
614 12:38:51.855204 Set clk81 to 24M
615 12:38:51.855619 Use GP1_pll as DSU clk.
616 12:38:51.860309 DSU clk: 1200 Mhz
617 12:38:51.860805 CPU clk: 1200 MHz
618 12:38:51.861227 Set clk81 to 166.6M
619 12:38:51.865934 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 12:38:51.871507 board id: 1
621 12:38:51.876666 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 12:38:51.887571 fw parse done
623 12:38:51.893549 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 12:38:51.936821 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 12:38:51.948017 PIEI prepare done
626 12:38:51.948643 fastboot data load
627 12:38:51.949102 fastboot data verify
628 12:38:51.953536 verify result: 266
629 12:38:51.959091 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 12:38:51.959631 LPDDR4 probe
631 12:38:51.960090 ddr clk to 1584MHz
632 12:38:51.967110 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 12:38:52.004831
634 12:38:52.005424 dmc_version 0001
635 12:38:52.011816 Check phy result
636 12:38:52.017796 INFO : End of CA training
637 12:38:52.018266 INFO : End of initialization
638 12:38:52.023401 INFO : Training has run successfully!
639 12:38:52.023933 Check phy result
640 12:38:52.029072 INFO : End of initialization
641 12:38:52.029615 INFO : End of read enable training
642 12:38:52.034599 INFO : End of fine write leveling
643 12:38:52.040350 INFO : End of Write leveling coarse delay
644 12:38:52.041018 INFO : Training has run successfully!
645 12:38:52.041634 Check phy result
646 12:38:52.045813 INFO : End of initialization
647 12:38:52.046312 INFO : End of read dq deskew training
648 12:38:52.051383 INFO : End of MPR read delay center optimization
649 12:38:52.056988 INFO : End of write delay center optimization
650 12:38:52.062617 INFO : End of read delay center optimization
651 12:38:52.063128 INFO : End of max read latency training
652 12:38:52.068274 INFO : Training has run successfully!
653 12:38:52.068779 1D training succeed
654 12:38:52.077342 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 12:38:52.126228 Check phy result
656 12:38:52.126820 INFO : End of initialization
657 12:38:52.153151 INFO : End of 2D read delay Voltage center optimization
658 12:38:52.177274 INFO : End of 2D read delay Voltage center optimization
659 12:38:52.233979 INFO : End of 2D write delay Voltage center optimization
660 12:38:52.287886 INFO : End of 2D write delay Voltage center optimization
661 12:38:52.293424 INFO : Training has run successfully!
662 12:38:52.294062
663 12:38:52.294647 channel==0
664 12:38:52.298951 RxClkDly_Margin_A0==78 ps 8
665 12:38:52.299461 TxDqDly_Margin_A0==98 ps 10
666 12:38:52.302279 RxClkDly_Margin_A1==88 ps 9
667 12:38:52.302761 TxDqDly_Margin_A1==88 ps 9
668 12:38:52.307851 TrainedVREFDQ_A0==76
669 12:38:52.308462 TrainedVREFDQ_A1==74
670 12:38:52.308894 VrefDac_Margin_A0==22
671 12:38:52.313446 DeviceVref_Margin_A0==38
672 12:38:52.313938 VrefDac_Margin_A1==23
673 12:38:52.319075 DeviceVref_Margin_A1==40
674 12:38:52.319559
675 12:38:52.319976
676 12:38:52.320416 channel==1
677 12:38:52.320811 RxClkDly_Margin_A0==78 ps 8
678 12:38:52.324659 TxDqDly_Margin_A0==88 ps 9
679 12:38:52.325131 RxClkDly_Margin_A1==78 ps 8
680 12:38:52.330341 TxDqDly_Margin_A1==98 ps 10
681 12:38:52.330851 TrainedVREFDQ_A0==75
682 12:38:52.331268 TrainedVREFDQ_A1==78
683 12:38:52.335887 VrefDac_Margin_A0==22
684 12:38:52.336385 DeviceVref_Margin_A0==39
685 12:38:52.341564 VrefDac_Margin_A1==22
686 12:38:52.342095 DeviceVref_Margin_A1==36
687 12:38:52.342517
688 12:38:52.347086 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 12:38:52.347580
690 12:38:52.375054 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
691 12:38:52.380656 2D training succeed
692 12:38:52.386343 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 12:38:52.386821 auto size-- 65535DDR cs0 size: 2048MB
694 12:38:52.391846 DDR cs1 size: 2048MB
695 12:38:52.392361 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 12:38:52.397449 cs0 DataBus test pass
697 12:38:52.397935 cs1 DataBus test pass
698 12:38:52.398337 cs0 AddrBus test pass
699 12:38:52.403085 cs1 AddrBus test pass
700 12:38:52.403561
701 12:38:52.404019 100bdlr_step_size ps== 471
702 12:38:52.404434 result report
703 12:38:52.408638 boot times 0Enable ddr reg access
704 12:38:52.416135 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 12:38:52.429936 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 12:38:53.088968 bl2z: ptr: 05129330, size: 00001e40
707 12:38:53.096912 0.0;M3 CHK:0;cm4_sp_mode 0
708 12:38:53.097424 MVN_1=0x00000000
709 12:38:53.097944 MVN_2=0x00000000
710 12:38:53.108367 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 12:38:53.108708 OPS=0x04
712 12:38:53.108931 ring efuse init
713 12:38:53.111258 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 12:38:53.117656 [0.017354 Inits done]
715 12:38:53.117944 secure task start!
716 12:38:53.118159 high task start!
717 12:38:53.118368 low task start!
718 12:38:53.121964 run into bl31
719 12:38:53.130549 NOTICE: BL31: v1.3(release):4fc40b1
720 12:38:53.138548 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 12:38:53.138862 NOTICE: BL31: G12A normal boot!
722 12:38:53.153994 NOTICE: BL31: BL33 decompress pass
723 12:38:53.159693 ERROR: Error initializing runtime service opteed_fast
724 12:38:53.954007
725 12:38:53.954425
726 12:38:53.959358 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 12:38:53.959795
728 12:38:53.962917 Model: Libre Computer AML-S905D3-CC Solitude
729 12:38:54.109845 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 12:38:54.124221 DRAM: 2 GiB (effective 3.8 GiB)
731 12:38:54.226113 Core: 406 devices, 33 uclasses, devicetree: separate
732 12:38:54.231850 WDT: Not starting watchdog@f0d0
733 12:38:54.256847 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 12:38:54.269145 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 12:38:54.274053 ** Bad device specification mmc 0 **
736 12:38:54.284095 Card did not respond to voltage select! : -110
737 12:38:54.291791 ** Bad device specification mmc 0 **
738 12:38:54.292112 Couldn't find partition mmc 0
739 12:38:54.300148 Card did not respond to voltage select! : -110
740 12:38:54.305618 ** Bad device specification mmc 0 **
741 12:38:54.305919 Couldn't find partition mmc 0
742 12:38:54.309938 Error: could not access storage.
743 12:38:54.607259 Net: eth0: ethernet@ff3f0000
744 12:38:54.607657 starting USB...
745 12:38:54.873992 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 12:38:54.875677 Starting the controller
747 12:38:54.876075 USB XHCI 1.10
748 12:38:56.412372 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 12:38:56.420565 scanning usb for storage devices... 0 Storage Device(s) found
751 12:38:56.472083 Hit any key to stop autoboot: 1
752 12:38:56.472992 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 12:38:56.473585 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 12:38:56.474068 Setting prompt string to ['=>']
755 12:38:56.474552 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 12:38:56.486457 0
757 12:38:56.487339 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 12:38:56.588608 => setenv autoload no
760 12:38:56.589365 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 12:38:56.594156 setenv autoload no
763 12:38:56.695641 => setenv initrd_high 0xffffffff
764 12:38:56.696424 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
765 12:38:56.700344 setenv initrd_high 0xffffffff
767 12:38:56.801773 => setenv fdt_high 0xffffffff
768 12:38:56.802497 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
769 12:38:56.806431 setenv fdt_high 0xffffffff
771 12:38:56.907890 => dhcp
772 12:38:56.908646 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
773 12:38:56.912555 dhcp
774 12:38:57.467420 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 12:38:57.468089 Speed: 1000, full duplex
776 12:38:57.468519 BOOTP broadcast 1
777 12:38:57.716262 BOOTP broadcast 2
778 12:38:58.217709 BOOTP broadcast 3
779 12:38:59.218132 BOOTP broadcast 4
780 12:39:01.219811 BOOTP broadcast 5
781 12:39:01.232062 DHCP client bound to address 192.168.6.12 (3763 ms)
783 12:39:01.333478 => setenv serverip 192.168.6.2
784 12:39:01.334130 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
785 12:39:01.338125 setenv serverip 192.168.6.2
787 12:39:01.439526 => tftpboot 0x01080000 745004/tftp-deploy-5oark332/kernel/uImage
788 12:39:01.440230 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
789 12:39:01.446951 tftpboot 0x01080000 745004/tftp-deploy-5oark332/kernel/uImage
790 12:39:01.447400 Speed: 1000, full duplex
791 12:39:01.447811 Using ethernet@ff3f0000 device
792 12:39:01.452585 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 12:39:01.457982 Filename '745004/tftp-deploy-5oark332/kernel/uImage'.
794 12:39:01.461942 Load address: 0x1080000
795 12:39:05.516551 Loading: *################################################## 43.4 MiB
796 12:39:05.517400 10.7 MiB/s
797 12:39:05.518004 done
798 12:39:05.521098 Bytes transferred = 45482560 (2b60240 hex)
800 12:39:05.623303 => tftpboot 0x08000000 745004/tftp-deploy-5oark332/ramdisk/ramdisk.cpio.gz.uboot
801 12:39:05.624377 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
802 12:39:05.631313 tftpboot 0x08000000 745004/tftp-deploy-5oark332/ramdisk/ramdisk.cpio.gz.uboot
803 12:39:05.631852 Speed: 1000, full duplex
804 12:39:05.632297 Using ethernet@ff3f0000 device
805 12:39:05.636803 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
806 12:39:05.646552 Filename '745004/tftp-deploy-5oark332/ramdisk/ramdisk.cpio.gz.uboot'.
807 12:39:05.647072 Load address: 0x8000000
808 12:39:12.821837 Loading: *##########################T ####################### UDP wrong checksum 00000005 00006cc5
809 12:39:17.821916 T UDP wrong checksum 00000005 00006cc5
810 12:39:27.823976 T T UDP wrong checksum 00000005 00006cc5
811 12:39:47.827597 T T T T UDP wrong checksum 00000005 00006cc5
812 12:40:02.830864 T T
813 12:40:02.831473 Retry count exceeded; starting again
815 12:40:02.832888 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
818 12:40:02.834747 end: 2.4 uboot-commands (duration 00:01:26) [common]
820 12:40:02.836258 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
822 12:40:02.837254 end: 2 uboot-action (duration 00:01:26) [common]
824 12:40:02.838756 Cleaning after the job
825 12:40:02.839287 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/ramdisk
826 12:40:02.840582 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/kernel
827 12:40:02.887064 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/dtb
828 12:40:02.887842 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745004/tftp-deploy-5oark332/modules
829 12:40:02.910112 start: 4.1 power-off (timeout 00:00:30) [common]
830 12:40:02.910775 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
831 12:40:02.943292 >> OK - accepted request
832 12:40:02.945302 Returned 0 in 0 seconds
833 12:40:03.046125 end: 4.1 power-off (duration 00:00:00) [common]
835 12:40:03.047141 start: 4.2 read-feedback (timeout 00:10:00) [common]
836 12:40:03.047804 Listened to connection for namespace 'common' for up to 1s
837 12:40:04.048247 Finalising connection for namespace 'common'
838 12:40:04.049000 Disconnecting from shell: Finalise
839 12:40:04.049536 =>
840 12:40:04.150549 end: 4.2 read-feedback (duration 00:00:01) [common]
841 12:40:04.151263 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/745004
842 12:40:04.450194 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/745004
843 12:40:04.450789 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.