Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 14:21:03.120951 lava-dispatcher, installed at version: 2024.01
2 14:21:03.121856 start: 0 validate
3 14:21:03.122431 Start time: 2024-09-19 14:21:03.122339+00:00 (UTC)
4 14:21:03.123004 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:21:03.123635 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 14:21:03.169830 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:21:03.170390 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 14:21:03.203762 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:21:03.204556 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 14:21:03.236146 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:21:03.236655 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 14:21:03.277540 validate duration: 0.16
14 14:21:03.278337 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:21:03.278655 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:21:03.278942 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:21:03.279522 Not decompressing ramdisk as can be used compressed.
18 14:21:03.279939 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 14:21:03.280194 saving as /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/ramdisk/rootfs.cpio.gz
20 14:21:03.280443 total size: 47897469 (45 MB)
21 14:21:03.322289 progress 0 % (0 MB)
22 14:21:03.352464 progress 5 % (2 MB)
23 14:21:03.382220 progress 10 % (4 MB)
24 14:21:03.411776 progress 15 % (6 MB)
25 14:21:03.441410 progress 20 % (9 MB)
26 14:21:03.471133 progress 25 % (11 MB)
27 14:21:03.500711 progress 30 % (13 MB)
28 14:21:03.530421 progress 35 % (16 MB)
29 14:21:03.559928 progress 40 % (18 MB)
30 14:21:03.589277 progress 45 % (20 MB)
31 14:21:03.618858 progress 50 % (22 MB)
32 14:21:03.649075 progress 55 % (25 MB)
33 14:21:03.678755 progress 60 % (27 MB)
34 14:21:03.708248 progress 65 % (29 MB)
35 14:21:03.737887 progress 70 % (32 MB)
36 14:21:03.767154 progress 75 % (34 MB)
37 14:21:03.796355 progress 80 % (36 MB)
38 14:21:03.826043 progress 85 % (38 MB)
39 14:21:03.855523 progress 90 % (41 MB)
40 14:21:03.884659 progress 95 % (43 MB)
41 14:21:03.913555 progress 100 % (45 MB)
42 14:21:03.914283 45 MB downloaded in 0.63 s (72.07 MB/s)
43 14:21:03.914821 end: 1.1.1 http-download (duration 00:00:01) [common]
45 14:21:03.915692 end: 1.1 download-retry (duration 00:00:01) [common]
46 14:21:03.916000 start: 1.2 download-retry (timeout 00:09:59) [common]
47 14:21:03.916274 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 14:21:03.916801 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/kernel/Image
49 14:21:03.917051 saving as /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/kernel/Image
50 14:21:03.917259 total size: 45482496 (43 MB)
51 14:21:03.917469 No compression specified
52 14:21:03.959528 progress 0 % (0 MB)
53 14:21:03.987554 progress 5 % (2 MB)
54 14:21:04.015434 progress 10 % (4 MB)
55 14:21:04.043844 progress 15 % (6 MB)
56 14:21:04.071621 progress 20 % (8 MB)
57 14:21:04.100349 progress 25 % (10 MB)
58 14:21:04.128613 progress 30 % (13 MB)
59 14:21:04.156219 progress 35 % (15 MB)
60 14:21:04.184141 progress 40 % (17 MB)
61 14:21:04.211949 progress 45 % (19 MB)
62 14:21:04.239597 progress 50 % (21 MB)
63 14:21:04.267404 progress 55 % (23 MB)
64 14:21:04.295172 progress 60 % (26 MB)
65 14:21:04.323322 progress 65 % (28 MB)
66 14:21:04.351227 progress 70 % (30 MB)
67 14:21:04.379501 progress 75 % (32 MB)
68 14:21:04.407812 progress 80 % (34 MB)
69 14:21:04.435580 progress 85 % (36 MB)
70 14:21:04.463476 progress 90 % (39 MB)
71 14:21:04.491201 progress 95 % (41 MB)
72 14:21:04.518484 progress 100 % (43 MB)
73 14:21:04.519003 43 MB downloaded in 0.60 s (72.08 MB/s)
74 14:21:04.519504 end: 1.2.1 http-download (duration 00:00:01) [common]
76 14:21:04.520378 end: 1.2 download-retry (duration 00:00:01) [common]
77 14:21:04.520680 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:21:04.520962 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:21:04.521517 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 14:21:04.521810 saving as /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/dtb/meson-g12b-a311d-libretech-cc.dtb
81 14:21:04.522031 total size: 54703 (0 MB)
82 14:21:04.522249 No compression specified
83 14:21:04.568760 progress 59 % (0 MB)
84 14:21:04.569614 progress 100 % (0 MB)
85 14:21:04.570188 0 MB downloaded in 0.05 s (1.08 MB/s)
86 14:21:04.570691 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:21:04.571546 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:21:04.571827 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:21:04.572136 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:21:04.572597 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/modules.tar.xz
92 14:21:04.572848 saving as /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/modules/modules.tar
93 14:21:04.573060 total size: 11582224 (11 MB)
94 14:21:04.573276 Using unxz to decompress xz
95 14:21:04.611643 progress 0 % (0 MB)
96 14:21:04.677375 progress 5 % (0 MB)
97 14:21:04.760731 progress 10 % (1 MB)
98 14:21:04.853034 progress 15 % (1 MB)
99 14:21:04.939514 progress 20 % (2 MB)
100 14:21:05.019828 progress 25 % (2 MB)
101 14:21:05.097827 progress 30 % (3 MB)
102 14:21:05.169407 progress 35 % (3 MB)
103 14:21:05.249219 progress 40 % (4 MB)
104 14:21:05.331475 progress 45 % (5 MB)
105 14:21:05.406767 progress 50 % (5 MB)
106 14:21:05.490349 progress 55 % (6 MB)
107 14:21:05.568240 progress 60 % (6 MB)
108 14:21:05.647704 progress 65 % (7 MB)
109 14:21:05.727785 progress 70 % (7 MB)
110 14:21:05.810454 progress 75 % (8 MB)
111 14:21:05.902306 progress 80 % (8 MB)
112 14:21:06.001347 progress 85 % (9 MB)
113 14:21:06.077101 progress 90 % (9 MB)
114 14:21:06.151808 progress 95 % (10 MB)
115 14:21:06.229010 progress 100 % (11 MB)
116 14:21:06.241598 11 MB downloaded in 1.67 s (6.62 MB/s)
117 14:21:06.242213 end: 1.4.1 http-download (duration 00:00:02) [common]
119 14:21:06.243037 end: 1.4 download-retry (duration 00:00:02) [common]
120 14:21:06.243311 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 14:21:06.243578 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 14:21:06.243829 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:21:06.244262 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 14:21:06.245249 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g
125 14:21:06.246100 makedir: /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin
126 14:21:06.246745 makedir: /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/tests
127 14:21:06.247363 makedir: /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/results
128 14:21:06.247970 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-add-keys
129 14:21:06.248979 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-add-sources
130 14:21:06.249915 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-background-process-start
131 14:21:06.250857 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-background-process-stop
132 14:21:06.251843 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-common-functions
133 14:21:06.252847 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-echo-ipv4
134 14:21:06.253764 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-install-packages
135 14:21:06.254666 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-installed-packages
136 14:21:06.255573 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-os-build
137 14:21:06.256547 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-probe-channel
138 14:21:06.257453 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-probe-ip
139 14:21:06.258358 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-target-ip
140 14:21:06.259266 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-target-mac
141 14:21:06.260481 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-target-storage
142 14:21:06.261513 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-test-case
143 14:21:06.262448 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-test-event
144 14:21:06.263373 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-test-feedback
145 14:21:06.264362 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-test-raise
146 14:21:06.265297 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-test-reference
147 14:21:06.266261 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-test-runner
148 14:21:06.267218 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-test-set
149 14:21:06.268213 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-test-shell
150 14:21:06.269157 Updating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-install-packages (oe)
151 14:21:06.270147 Updating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/bin/lava-installed-packages (oe)
152 14:21:06.270999 Creating /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/environment
153 14:21:06.271751 LAVA metadata
154 14:21:06.272230 - LAVA_JOB_ID=745049
155 14:21:06.272461 - LAVA_DISPATCHER_IP=192.168.6.2
156 14:21:06.272865 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 14:21:06.273982 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 14:21:06.274345 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 14:21:06.274563 skipped lava-vland-overlay
160 14:21:06.274815 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 14:21:06.275081 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 14:21:06.275306 skipped lava-multinode-overlay
163 14:21:06.275555 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 14:21:06.275816 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 14:21:06.276106 Loading test definitions
166 14:21:06.276411 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 14:21:06.276644 Using /lava-745049 at stage 0
168 14:21:06.277948 uuid=745049_1.5.2.4.1 testdef=None
169 14:21:06.278309 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 14:21:06.278587 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 14:21:06.280510 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 14:21:06.281382 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 14:21:06.283645 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 14:21:06.284567 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 14:21:06.286712 runner path: /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/0/tests/0_igt-gpu-panfrost test_uuid 745049_1.5.2.4.1
178 14:21:06.287308 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 14:21:06.288170 Creating lava-test-runner.conf files
181 14:21:06.288385 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/745049/lava-overlay-3_jzoc5g/lava-745049/0 for stage 0
182 14:21:06.288747 - 0_igt-gpu-panfrost
183 14:21:06.289109 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 14:21:06.289399 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 14:21:06.313518 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 14:21:06.313960 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 14:21:06.314227 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 14:21:06.314499 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 14:21:06.314765 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 14:21:13.584524 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 14:21:13.585003 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 14:21:13.585478 extracting modules file /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/745049/extract-overlay-ramdisk-5gea467z/ramdisk
193 14:21:15.022545 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 14:21:15.023009 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 14:21:15.023299 [common] Applying overlay /var/lib/lava/dispatcher/tmp/745049/compress-overlay-07i5r4qg/overlay-1.5.2.5.tar.gz to ramdisk
196 14:21:15.023523 [common] Applying overlay /var/lib/lava/dispatcher/tmp/745049/compress-overlay-07i5r4qg/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/745049/extract-overlay-ramdisk-5gea467z/ramdisk
197 14:21:15.053459 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 14:21:15.053845 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 14:21:15.054130 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 14:21:15.054369 Converting downloaded kernel to a uImage
201 14:21:15.054675 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/kernel/Image /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/kernel/uImage
202 14:21:15.506127 output: Image Name:
203 14:21:15.506520 output: Created: Thu Sep 19 14:21:15 2024
204 14:21:15.506739 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 14:21:15.506943 output: Data Size: 45482496 Bytes = 44416.50 KiB = 43.38 MiB
206 14:21:15.507147 output: Load Address: 01080000
207 14:21:15.507347 output: Entry Point: 01080000
208 14:21:15.507546 output:
209 14:21:15.507876 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 14:21:15.508187 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 14:21:15.508460 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 14:21:15.508713 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 14:21:15.508968 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 14:21:15.509219 Building ramdisk /var/lib/lava/dispatcher/tmp/745049/extract-overlay-ramdisk-5gea467z/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/745049/extract-overlay-ramdisk-5gea467z/ramdisk
215 14:21:22.092679 >> 501793 blocks
216 14:21:42.674001 Adding RAMdisk u-boot header.
217 14:21:42.674489 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/745049/extract-overlay-ramdisk-5gea467z/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/745049/extract-overlay-ramdisk-5gea467z/ramdisk.cpio.gz.uboot
218 14:21:43.353643 output: Image Name:
219 14:21:43.354272 output: Created: Thu Sep 19 14:21:42 2024
220 14:21:43.354684 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 14:21:43.355087 output: Data Size: 65678619 Bytes = 64139.28 KiB = 62.64 MiB
222 14:21:43.355484 output: Load Address: 00000000
223 14:21:43.355881 output: Entry Point: 00000000
224 14:21:43.356329 output:
225 14:21:43.357277 rename /var/lib/lava/dispatcher/tmp/745049/extract-overlay-ramdisk-5gea467z/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/ramdisk/ramdisk.cpio.gz.uboot
226 14:21:43.358009 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 14:21:43.358573 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 14:21:43.359106 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 14:21:43.359565 No LXC device requested
230 14:21:43.360107 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 14:21:43.360657 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 14:21:43.361186 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 14:21:43.361624 Checking files for TFTP limit of 4294967296 bytes.
234 14:21:43.364341 end: 1 tftp-deploy (duration 00:00:40) [common]
235 14:21:43.364947 start: 2 uboot-action (timeout 00:05:00) [common]
236 14:21:43.365492 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 14:21:43.366004 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 14:21:43.366514 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 14:21:43.367051 Using kernel file from prepare-kernel: 745049/tftp-deploy-t9w3g4cu/kernel/uImage
240 14:21:43.367690 substitutions:
241 14:21:43.368146 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 14:21:43.368570 - {DTB_ADDR}: 0x01070000
243 14:21:43.368979 - {DTB}: 745049/tftp-deploy-t9w3g4cu/dtb/meson-g12b-a311d-libretech-cc.dtb
244 14:21:43.369392 - {INITRD}: 745049/tftp-deploy-t9w3g4cu/ramdisk/ramdisk.cpio.gz.uboot
245 14:21:43.369796 - {KERNEL_ADDR}: 0x01080000
246 14:21:43.370196 - {KERNEL}: 745049/tftp-deploy-t9w3g4cu/kernel/uImage
247 14:21:43.370619 - {LAVA_MAC}: None
248 14:21:43.371317 - {PRESEED_CONFIG}: None
249 14:21:43.371792 - {PRESEED_LOCAL}: None
250 14:21:43.372235 - {RAMDISK_ADDR}: 0x08000000
251 14:21:43.372643 - {RAMDISK}: 745049/tftp-deploy-t9w3g4cu/ramdisk/ramdisk.cpio.gz.uboot
252 14:21:43.373053 - {ROOT_PART}: None
253 14:21:43.373457 - {ROOT}: None
254 14:21:43.373859 - {SERVER_IP}: 192.168.6.2
255 14:21:43.374260 - {TEE_ADDR}: 0x83000000
256 14:21:43.374660 - {TEE}: None
257 14:21:43.375057 Parsed boot commands:
258 14:21:43.375444 - setenv autoload no
259 14:21:43.375841 - setenv initrd_high 0xffffffff
260 14:21:43.376270 - setenv fdt_high 0xffffffff
261 14:21:43.376673 - dhcp
262 14:21:43.377072 - setenv serverip 192.168.6.2
263 14:21:43.377470 - tftpboot 0x01080000 745049/tftp-deploy-t9w3g4cu/kernel/uImage
264 14:21:43.377868 - tftpboot 0x08000000 745049/tftp-deploy-t9w3g4cu/ramdisk/ramdisk.cpio.gz.uboot
265 14:21:43.378264 - tftpboot 0x01070000 745049/tftp-deploy-t9w3g4cu/dtb/meson-g12b-a311d-libretech-cc.dtb
266 14:21:43.378662 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 14:21:43.379060 - bootm 0x01080000 0x08000000 0x01070000
268 14:21:43.379587 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 14:21:43.381138 start: 2.3 connect-device (timeout 00:05:00) [common]
271 14:21:43.381600 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 14:21:43.396324 Setting prompt string to ['lava-test: # ']
273 14:21:43.397847 end: 2.3 connect-device (duration 00:00:00) [common]
274 14:21:43.398517 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 14:21:43.399104 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 14:21:43.399661 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 14:21:43.400897 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 14:21:43.437629 >> OK - accepted request
279 14:21:43.439621 Returned 0 in 0 seconds
280 14:21:43.540751 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 14:21:43.541751 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 14:21:43.542086 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 14:21:43.542421 Setting prompt string to ['Hit any key to stop autoboot']
285 14:21:43.542707 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 14:21:43.543668 Trying 192.168.56.21...
287 14:21:43.543951 Connected to conserv1.
288 14:21:43.544454 Escape character is '^]'.
289 14:21:43.544906
290 14:21:43.545384 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 14:21:43.545825
292 14:21:54.837080 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 14:21:54.837699 bl2_stage_init 0x01
294 14:21:54.838164 bl2_stage_init 0x81
295 14:21:54.842635 hw id: 0x0000 - pwm id 0x01
296 14:21:54.843157 bl2_stage_init 0xc1
297 14:21:54.843565 bl2_stage_init 0x02
298 14:21:54.843977
299 14:21:54.848239 L0:00000000
300 14:21:54.848720 L1:20000703
301 14:21:54.849154 L2:00008067
302 14:21:54.849555 L3:14000000
303 14:21:54.853899 B2:00402000
304 14:21:54.854380 B1:e0f83180
305 14:21:54.854771
306 14:21:54.855160 TE: 58124
307 14:21:54.855547
308 14:21:54.859480 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 14:21:54.859939
310 14:21:54.860370 Board ID = 1
311 14:21:54.864998 Set A53 clk to 24M
312 14:21:54.865472 Set A73 clk to 24M
313 14:21:54.865870 Set clk81 to 24M
314 14:21:54.870659 A53 clk: 1200 MHz
315 14:21:54.871122 A73 clk: 1200 MHz
316 14:21:54.871514 CLK81: 166.6M
317 14:21:54.871897 smccc: 00012a92
318 14:21:54.876355 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 14:21:54.881952 board id: 1
320 14:21:54.887670 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 14:21:54.898516 fw parse done
322 14:21:54.904352 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 14:21:54.946819 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 14:21:54.957883 PIEI prepare done
325 14:21:54.958408 fastboot data load
326 14:21:54.958808 fastboot data verify
327 14:21:54.963392 verify result: 266
328 14:21:54.968971 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 14:21:54.969284 LPDDR4 probe
330 14:21:54.969517 ddr clk to 1584MHz
331 14:21:54.976971 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 14:21:55.014410
333 14:21:55.015027 dmc_version 0001
334 14:21:55.020971 Check phy result
335 14:21:55.026899 INFO : End of CA training
336 14:21:55.027431 INFO : End of initialization
337 14:21:55.032507 INFO : Training has run successfully!
338 14:21:55.033056 Check phy result
339 14:21:55.038091 INFO : End of initialization
340 14:21:55.038632 INFO : End of read enable training
341 14:21:55.043650 INFO : End of fine write leveling
342 14:21:55.049231 INFO : End of Write leveling coarse delay
343 14:21:55.049756 INFO : Training has run successfully!
344 14:21:55.050179 Check phy result
345 14:21:55.054842 INFO : End of initialization
346 14:21:55.055360 INFO : End of read dq deskew training
347 14:21:55.060370 INFO : End of MPR read delay center optimization
348 14:21:55.066045 INFO : End of write delay center optimization
349 14:21:55.071629 INFO : End of read delay center optimization
350 14:21:55.072227 INFO : End of max read latency training
351 14:21:55.077245 INFO : Training has run successfully!
352 14:21:55.077765 1D training succeed
353 14:21:55.086316 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 14:21:55.134026 Check phy result
355 14:21:55.134592 INFO : End of initialization
356 14:21:55.155693 INFO : End of 2D read delay Voltage center optimization
357 14:21:55.176085 INFO : End of 2D read delay Voltage center optimization
358 14:21:55.227891 INFO : End of 2D write delay Voltage center optimization
359 14:21:55.277314 INFO : End of 2D write delay Voltage center optimization
360 14:21:55.282898 INFO : Training has run successfully!
361 14:21:55.283252
362 14:21:55.283490 channel==0
363 14:21:55.288407 RxClkDly_Margin_A0==88 ps 9
364 14:21:55.288746 TxDqDly_Margin_A0==98 ps 10
365 14:21:55.294018 RxClkDly_Margin_A1==88 ps 9
366 14:21:55.294368 TxDqDly_Margin_A1==98 ps 10
367 14:21:55.294594 TrainedVREFDQ_A0==74
368 14:21:55.299584 TrainedVREFDQ_A1==74
369 14:21:55.299933 VrefDac_Margin_A0==25
370 14:21:55.300192 DeviceVref_Margin_A0==40
371 14:21:55.305148 VrefDac_Margin_A1==25
372 14:21:55.305492 DeviceVref_Margin_A1==40
373 14:21:55.305708
374 14:21:55.305924
375 14:21:55.311054 channel==1
376 14:21:55.311714 RxClkDly_Margin_A0==98 ps 10
377 14:21:55.312440 TxDqDly_Margin_A0==98 ps 10
378 14:21:55.316352 RxClkDly_Margin_A1==98 ps 10
379 14:21:55.316883 TxDqDly_Margin_A1==88 ps 9
380 14:21:55.322180 TrainedVREFDQ_A0==77
381 14:21:55.322847 TrainedVREFDQ_A1==77
382 14:21:55.323391 VrefDac_Margin_A0==22
383 14:21:55.327547 DeviceVref_Margin_A0==37
384 14:21:55.328077 VrefDac_Margin_A1==22
385 14:21:55.333235 DeviceVref_Margin_A1==37
386 14:21:55.333915
387 14:21:55.334500 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 14:21:55.338710
389 14:21:55.366850 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 14:21:55.367504 2D training succeed
391 14:21:55.372419 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 14:21:55.378208 auto size-- 65535DDR cs0 size: 2048MB
393 14:21:55.378806 DDR cs1 size: 2048MB
394 14:21:55.383602 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 14:21:55.384199 cs0 DataBus test pass
396 14:21:55.389197 cs1 DataBus test pass
397 14:21:55.389769 cs0 AddrBus test pass
398 14:21:55.390228 cs1 AddrBus test pass
399 14:21:55.390629
400 14:21:55.394822 100bdlr_step_size ps== 420
401 14:21:55.395318 result report
402 14:21:55.400435 boot times 0Enable ddr reg access
403 14:21:55.405876 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 14:21:55.418425 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 14:21:55.993069 0.0;M3 CHK:0;cm4_sp_mode 0
406 14:21:55.993500 MVN_1=0x00000000
407 14:21:55.998592 MVN_2=0x00000000
408 14:21:56.004340 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 14:21:56.004823 OPS=0x10
410 14:21:56.005254 ring efuse init
411 14:21:56.005660 chipver efuse init
412 14:21:56.009912 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 14:21:56.015570 [0.018961 Inits done]
414 14:21:56.015862 secure task start!
415 14:21:56.016095 high task start!
416 14:21:56.020173 low task start!
417 14:21:56.020657 run into bl31
418 14:21:56.026751 NOTICE: BL31: v1.3(release):4fc40b1
419 14:21:56.034544 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 14:21:56.035051 NOTICE: BL31: G12A normal boot!
421 14:21:56.059977 NOTICE: BL31: BL33 decompress pass
422 14:21:56.065623 ERROR: Error initializing runtime service opteed_fast
423 14:21:57.298556
424 14:21:57.299212
425 14:21:57.306770 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 14:21:57.307301
427 14:21:57.307736 Model: Libre Computer AML-A311D-CC Alta
428 14:21:57.515319 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 14:21:57.539615 DRAM: 2 GiB (effective 3.8 GiB)
430 14:21:57.684280 Core: 408 devices, 31 uclasses, devicetree: separate
431 14:21:57.687472 WDT: Not starting watchdog@f0d0
432 14:21:57.720054 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 14:21:57.732263 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 14:21:57.737270 ** Bad device specification mmc 0 **
435 14:21:57.747499 Card did not respond to voltage select! : -110
436 14:21:57.755138 ** Bad device specification mmc 0 **
437 14:21:57.755481 Couldn't find partition mmc 0
438 14:21:57.763660 Card did not respond to voltage select! : -110
439 14:21:57.769022 ** Bad device specification mmc 0 **
440 14:21:57.769360 Couldn't find partition mmc 0
441 14:21:57.774060 Error: could not access storage.
442 14:21:59.037362 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 14:21:59.038019 bl2_stage_init 0x01
444 14:21:59.038473 bl2_stage_init 0x81
445 14:21:59.042837 hw id: 0x0000 - pwm id 0x01
446 14:21:59.043325 bl2_stage_init 0xc1
447 14:21:59.043767 bl2_stage_init 0x02
448 14:21:59.044269
449 14:21:59.048422 L0:00000000
450 14:21:59.048911 L1:20000703
451 14:21:59.049349 L2:00008067
452 14:21:59.049781 L3:14000000
453 14:21:59.054036 B2:00402000
454 14:21:59.054537 B1:e0f83180
455 14:21:59.054973
456 14:21:59.055411 TE: 58124
457 14:21:59.055841
458 14:21:59.059641 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 14:21:59.060156
460 14:21:59.060600 Board ID = 1
461 14:21:59.065298 Set A53 clk to 24M
462 14:21:59.065777 Set A73 clk to 24M
463 14:21:59.066213 Set clk81 to 24M
464 14:21:59.070901 A53 clk: 1200 MHz
465 14:21:59.071371 A73 clk: 1200 MHz
466 14:21:59.071804 CLK81: 166.6M
467 14:21:59.072272 smccc: 00012a92
468 14:21:59.076624 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 14:21:59.082010 board id: 1
470 14:21:59.087894 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 14:21:59.098623 fw parse done
472 14:21:59.104518 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 14:21:59.147134 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 14:21:59.158044 PIEI prepare done
475 14:21:59.158357 fastboot data load
476 14:21:59.158575 fastboot data verify
477 14:21:59.163772 verify result: 266
478 14:21:59.169274 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 14:21:59.169568 LPDDR4 probe
480 14:21:59.169779 ddr clk to 1584MHz
481 14:21:59.177301 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 14:21:59.214593
483 14:21:59.214979 dmc_version 0001
484 14:21:59.221173 Check phy result
485 14:21:59.227039 INFO : End of CA training
486 14:21:59.227329 INFO : End of initialization
487 14:21:59.232678 INFO : Training has run successfully!
488 14:21:59.232965 Check phy result
489 14:21:59.238295 INFO : End of initialization
490 14:21:59.238589 INFO : End of read enable training
491 14:21:59.241723 INFO : End of fine write leveling
492 14:21:59.247285 INFO : End of Write leveling coarse delay
493 14:21:59.252880 INFO : Training has run successfully!
494 14:21:59.253105 Check phy result
495 14:21:59.253305 INFO : End of initialization
496 14:21:59.258541 INFO : End of read dq deskew training
497 14:21:59.264138 INFO : End of MPR read delay center optimization
498 14:21:59.264428 INFO : End of write delay center optimization
499 14:21:59.269662 INFO : End of read delay center optimization
500 14:21:59.275331 INFO : End of max read latency training
501 14:21:59.275563 INFO : Training has run successfully!
502 14:21:59.280865 1D training succeed
503 14:21:59.285856 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 14:21:59.334376 Check phy result
505 14:21:59.334878 INFO : End of initialization
506 14:21:59.355976 INFO : End of 2D read delay Voltage center optimization
507 14:21:59.375137 INFO : End of 2D read delay Voltage center optimization
508 14:21:59.426991 INFO : End of 2D write delay Voltage center optimization
509 14:21:59.476277 INFO : End of 2D write delay Voltage center optimization
510 14:21:59.481801 INFO : Training has run successfully!
511 14:21:59.482092
512 14:21:59.482313 channel==0
513 14:21:59.487410 RxClkDly_Margin_A0==88 ps 9
514 14:21:59.487960 TxDqDly_Margin_A0==98 ps 10
515 14:21:59.493038 RxClkDly_Margin_A1==88 ps 9
516 14:21:59.493578 TxDqDly_Margin_A1==98 ps 10
517 14:21:59.494045 TrainedVREFDQ_A0==74
518 14:21:59.498748 TrainedVREFDQ_A1==74
519 14:21:59.499266 VrefDac_Margin_A0==25
520 14:21:59.499711 DeviceVref_Margin_A0==40
521 14:21:59.504267 VrefDac_Margin_A1==25
522 14:21:59.504808 DeviceVref_Margin_A1==40
523 14:21:59.505260
524 14:21:59.505735
525 14:21:59.509814 channel==1
526 14:21:59.510307 RxClkDly_Margin_A0==88 ps 9
527 14:21:59.510740 TxDqDly_Margin_A0==88 ps 9
528 14:21:59.515354 RxClkDly_Margin_A1==88 ps 9
529 14:21:59.515811 TxDqDly_Margin_A1==88 ps 9
530 14:21:59.520978 TrainedVREFDQ_A0==77
531 14:21:59.521466 TrainedVREFDQ_A1==77
532 14:21:59.521906 VrefDac_Margin_A0==23
533 14:21:59.526702 DeviceVref_Margin_A0==37
534 14:21:59.527153 VrefDac_Margin_A1==24
535 14:21:59.532205 DeviceVref_Margin_A1==37
536 14:21:59.532661
537 14:21:59.533094 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 14:21:59.533520
539 14:21:59.565794 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000019 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 14:21:59.566331 2D training succeed
541 14:21:59.571366 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 14:21:59.577005 auto size-- 65535DDR cs0 size: 2048MB
543 14:21:59.577487 DDR cs1 size: 2048MB
544 14:21:59.582603 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 14:21:59.583070 cs0 DataBus test pass
546 14:21:59.588219 cs1 DataBus test pass
547 14:21:59.588684 cs0 AddrBus test pass
548 14:21:59.589120 cs1 AddrBus test pass
549 14:21:59.589553
550 14:21:59.593818 100bdlr_step_size ps== 420
551 14:21:59.594295 result report
552 14:21:59.599370 boot times 0Enable ddr reg access
553 14:21:59.604590 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 14:21:59.618019 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 14:22:00.190507 0.0;M3 CHK:0;cm4_sp_mode 0
556 14:22:00.191134 MVN_1=0x00000000
557 14:22:00.195749 MVN_2=0x00000000
558 14:22:00.201510 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 14:22:00.202031 OPS=0x10
560 14:22:00.202430 ring efuse init
561 14:22:00.202818 chipver efuse init
562 14:22:00.207110 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 14:22:00.212714 [0.018961 Inits done]
564 14:22:00.213170 secure task start!
565 14:22:00.213560 high task start!
566 14:22:00.217238 low task start!
567 14:22:00.217687 run into bl31
568 14:22:00.224024 NOTICE: BL31: v1.3(release):4fc40b1
569 14:22:00.231713 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 14:22:00.232213 NOTICE: BL31: G12A normal boot!
571 14:22:00.257002 NOTICE: BL31: BL33 decompress pass
572 14:22:00.262792 ERROR: Error initializing runtime service opteed_fast
573 14:22:01.495841
574 14:22:01.496310
575 14:22:01.504175 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 14:22:01.504684
577 14:22:01.505039 Model: Libre Computer AML-A311D-CC Alta
578 14:22:01.712528 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 14:22:01.736091 DRAM: 2 GiB (effective 3.8 GiB)
580 14:22:01.878983 Core: 408 devices, 31 uclasses, devicetree: separate
581 14:22:01.884812 WDT: Not starting watchdog@f0d0
582 14:22:01.916947 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 14:22:01.929469 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 14:22:01.934387 ** Bad device specification mmc 0 **
585 14:22:01.944774 Card did not respond to voltage select! : -110
586 14:22:01.952314 ** Bad device specification mmc 0 **
587 14:22:01.952623 Couldn't find partition mmc 0
588 14:22:01.960751 Card did not respond to voltage select! : -110
589 14:22:01.966236 ** Bad device specification mmc 0 **
590 14:22:01.966643 Couldn't find partition mmc 0
591 14:22:01.971258 Error: could not access storage.
592 14:22:02.313803 Net: eth0: ethernet@ff3f0000
593 14:22:02.314217 starting USB...
594 14:22:02.565767 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 14:22:02.566366 Starting the controller
596 14:22:02.572655 USB XHCI 1.10
597 14:22:04.286271 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 14:22:04.286897 bl2_stage_init 0x01
599 14:22:04.287322 bl2_stage_init 0x81
600 14:22:04.291976 hw id: 0x0000 - pwm id 0x01
601 14:22:04.292469 bl2_stage_init 0xc1
602 14:22:04.292890 bl2_stage_init 0x02
603 14:22:04.293297
604 14:22:04.297681 L0:00000000
605 14:22:04.298149 L1:20000703
606 14:22:04.298561 L2:00008067
607 14:22:04.298958 L3:14000000
608 14:22:04.300524 B2:00402000
609 14:22:04.300978 B1:e0f83180
610 14:22:04.301381
611 14:22:04.301778 TE: 58167
612 14:22:04.302175
613 14:22:04.311560 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 14:22:04.312063
615 14:22:04.312478 Board ID = 1
616 14:22:04.312873 Set A53 clk to 24M
617 14:22:04.313261 Set A73 clk to 24M
618 14:22:04.317266 Set clk81 to 24M
619 14:22:04.317725 A53 clk: 1200 MHz
620 14:22:04.318132 A73 clk: 1200 MHz
621 14:22:04.320941 CLK81: 166.6M
622 14:22:04.321393 smccc: 00012abe
623 14:22:04.326584 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 14:22:04.327046 board id: 1
625 14:22:04.336920 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 14:22:04.347638 fw parse done
627 14:22:04.353723 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 14:22:04.396084 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 14:22:04.407115 PIEI prepare done
630 14:22:04.407600 fastboot data load
631 14:22:04.408045 fastboot data verify
632 14:22:04.412723 verify result: 266
633 14:22:04.418287 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 14:22:04.418748 LPDDR4 probe
635 14:22:04.419158 ddr clk to 1584MHz
636 14:22:04.426308 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 14:22:04.463587
638 14:22:04.464106 dmc_version 0001
639 14:22:04.470193 Check phy result
640 14:22:04.476164 INFO : End of CA training
641 14:22:04.476630 INFO : End of initialization
642 14:22:04.481652 INFO : Training has run successfully!
643 14:22:04.482118 Check phy result
644 14:22:04.487261 INFO : End of initialization
645 14:22:04.487718 INFO : End of read enable training
646 14:22:04.492846 INFO : End of fine write leveling
647 14:22:04.498510 INFO : End of Write leveling coarse delay
648 14:22:04.498974 INFO : Training has run successfully!
649 14:22:04.499382 Check phy result
650 14:22:04.504049 INFO : End of initialization
651 14:22:04.504507 INFO : End of read dq deskew training
652 14:22:04.509657 INFO : End of MPR read delay center optimization
653 14:22:04.515293 INFO : End of write delay center optimization
654 14:22:04.520897 INFO : End of read delay center optimization
655 14:22:04.521360 INFO : End of max read latency training
656 14:22:04.526516 INFO : Training has run successfully!
657 14:22:04.526973 1D training succeed
658 14:22:04.535703 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 14:22:04.583242 Check phy result
660 14:22:04.583755 INFO : End of initialization
661 14:22:04.604829 INFO : End of 2D read delay Voltage center optimization
662 14:22:04.624138 INFO : End of 2D read delay Voltage center optimization
663 14:22:04.676013 INFO : End of 2D write delay Voltage center optimization
664 14:22:04.725194 INFO : End of 2D write delay Voltage center optimization
665 14:22:04.730792 INFO : Training has run successfully!
666 14:22:04.731258
667 14:22:04.731668 channel==0
668 14:22:04.736572 RxClkDly_Margin_A0==88 ps 9
669 14:22:04.737053 TxDqDly_Margin_A0==98 ps 10
670 14:22:04.741981 RxClkDly_Margin_A1==88 ps 9
671 14:22:04.742438 TxDqDly_Margin_A1==98 ps 10
672 14:22:04.742855 TrainedVREFDQ_A0==74
673 14:22:04.747593 TrainedVREFDQ_A1==74
674 14:22:04.748085 VrefDac_Margin_A0==25
675 14:22:04.748495 DeviceVref_Margin_A0==40
676 14:22:04.753192 VrefDac_Margin_A1==25
677 14:22:04.753643 DeviceVref_Margin_A1==40
678 14:22:04.754047
679 14:22:04.754446
680 14:22:04.758795 channel==1
681 14:22:04.759252 RxClkDly_Margin_A0==88 ps 9
682 14:22:04.759658 TxDqDly_Margin_A0==98 ps 10
683 14:22:04.764571 RxClkDly_Margin_A1==88 ps 9
684 14:22:04.765046 TxDqDly_Margin_A1==98 ps 10
685 14:22:04.770020 TrainedVREFDQ_A0==77
686 14:22:04.770483 TrainedVREFDQ_A1==78
687 14:22:04.770892 VrefDac_Margin_A0==23
688 14:22:04.775575 DeviceVref_Margin_A0==37
689 14:22:04.776055 VrefDac_Margin_A1==24
690 14:22:04.781205 DeviceVref_Margin_A1==36
691 14:22:04.781660
692 14:22:04.782067 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 14:22:04.782465
694 14:22:04.814740 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000019 0000001a 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
695 14:22:04.815272 2D training succeed
696 14:22:04.820373 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 14:22:04.826022 auto size-- 65535DDR cs0 size: 2048MB
698 14:22:04.826486 DDR cs1 size: 2048MB
699 14:22:04.831606 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 14:22:04.832104 cs0 DataBus test pass
701 14:22:04.837183 cs1 DataBus test pass
702 14:22:04.837642 cs0 AddrBus test pass
703 14:22:04.838044 cs1 AddrBus test pass
704 14:22:04.838437
705 14:22:04.842805 100bdlr_step_size ps== 420
706 14:22:04.843272 result report
707 14:22:04.848378 boot times 0Enable ddr reg access
708 14:22:04.853757 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 14:22:04.867185 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 14:22:05.439152 0.0;M3 CHK:0;cm4_sp_mode 0
711 14:22:05.439581 MVN_1=0x00000000
712 14:22:05.444638 MVN_2=0x00000000
713 14:22:05.450535 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 14:22:05.450845 OPS=0x10
715 14:22:05.451053 ring efuse init
716 14:22:05.451254 chipver efuse init
717 14:22:05.455992 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 14:22:05.461633 [0.018961 Inits done]
719 14:22:05.461923 secure task start!
720 14:22:05.462134 high task start!
721 14:22:05.466234 low task start!
722 14:22:05.466526 run into bl31
723 14:22:05.473016 NOTICE: BL31: v1.3(release):4fc40b1
724 14:22:05.480665 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 14:22:05.481017 NOTICE: BL31: G12A normal boot!
726 14:22:05.506309 NOTICE: BL31: BL33 decompress pass
727 14:22:05.511902 ERROR: Error initializing runtime service opteed_fast
728 14:22:06.745127
729 14:22:06.745790
730 14:22:06.753076 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 14:22:06.753689
732 14:22:06.754124 Model: Libre Computer AML-A311D-CC Alta
733 14:22:06.961480 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 14:22:06.985003 DRAM: 2 GiB (effective 3.8 GiB)
735 14:22:07.127924 Core: 408 devices, 31 uclasses, devicetree: separate
736 14:22:07.133666 WDT: Not starting watchdog@f0d0
737 14:22:07.165847 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 14:22:07.178375 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 14:22:07.182626 ** Bad device specification mmc 0 **
740 14:22:07.193826 Card did not respond to voltage select! : -110
741 14:22:07.201325 ** Bad device specification mmc 0 **
742 14:22:07.201815 Couldn't find partition mmc 0
743 14:22:07.209831 Card did not respond to voltage select! : -110
744 14:22:07.215148 ** Bad device specification mmc 0 **
745 14:22:07.215619 Couldn't find partition mmc 0
746 14:22:07.220243 Error: could not access storage.
747 14:22:07.562658 Net: eth0: ethernet@ff3f0000
748 14:22:07.563258 starting USB...
749 14:22:07.814439 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 14:22:07.814967 Starting the controller
751 14:22:07.821418 USB XHCI 1.10
752 14:22:09.986591 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 14:22:09.987185 bl2_stage_init 0x01
754 14:22:09.987606 bl2_stage_init 0x81
755 14:22:09.992244 hw id: 0x0000 - pwm id 0x01
756 14:22:09.992741 bl2_stage_init 0xc1
757 14:22:09.993158 bl2_stage_init 0x02
758 14:22:09.993563
759 14:22:09.997844 L0:00000000
760 14:22:09.998303 L1:20000703
761 14:22:09.998708 L2:00008067
762 14:22:09.999102 L3:14000000
763 14:22:10.003580 B2:00402000
764 14:22:10.004072 B1:e0f83180
765 14:22:10.004484
766 14:22:10.004883 TE: 58159
767 14:22:10.005282
768 14:22:10.008911 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 14:22:10.009375
770 14:22:10.009781 Board ID = 1
771 14:22:10.014569 Set A53 clk to 24M
772 14:22:10.015042 Set A73 clk to 24M
773 14:22:10.015454 Set clk81 to 24M
774 14:22:10.020187 A53 clk: 1200 MHz
775 14:22:10.020670 A73 clk: 1200 MHz
776 14:22:10.021082 CLK81: 166.6M
777 14:22:10.021481 smccc: 00012ab5
778 14:22:10.025918 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 14:22:10.031915 board id: 1
780 14:22:10.037176 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 14:22:10.047551 fw parse done
782 14:22:10.053509 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 14:22:10.096138 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 14:22:10.107078 PIEI prepare done
785 14:22:10.107567 fastboot data load
786 14:22:10.108012 fastboot data verify
787 14:22:10.112746 verify result: 266
788 14:22:10.118350 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 14:22:10.118829 LPDDR4 probe
790 14:22:10.119236 ddr clk to 1584MHz
791 14:22:10.126303 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 14:22:10.163570
793 14:22:10.164108 dmc_version 0001
794 14:22:10.170270 Check phy result
795 14:22:10.176260 INFO : End of CA training
796 14:22:10.176758 INFO : End of initialization
797 14:22:10.181737 INFO : Training has run successfully!
798 14:22:10.182207 Check phy result
799 14:22:10.187297 INFO : End of initialization
800 14:22:10.187761 INFO : End of read enable training
801 14:22:10.192918 INFO : End of fine write leveling
802 14:22:10.198513 INFO : End of Write leveling coarse delay
803 14:22:10.198989 INFO : Training has run successfully!
804 14:22:10.199397 Check phy result
805 14:22:10.204250 INFO : End of initialization
806 14:22:10.204726 INFO : End of read dq deskew training
807 14:22:10.209750 INFO : End of MPR read delay center optimization
808 14:22:10.215292 INFO : End of write delay center optimization
809 14:22:10.220919 INFO : End of read delay center optimization
810 14:22:10.221399 INFO : End of max read latency training
811 14:22:10.226587 INFO : Training has run successfully!
812 14:22:10.227063 1D training succeed
813 14:22:10.235644 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 14:22:10.283315 Check phy result
815 14:22:10.283833 INFO : End of initialization
816 14:22:10.305051 INFO : End of 2D read delay Voltage center optimization
817 14:22:10.324412 INFO : End of 2D read delay Voltage center optimization
818 14:22:10.376472 INFO : End of 2D write delay Voltage center optimization
819 14:22:10.425843 INFO : End of 2D write delay Voltage center optimization
820 14:22:10.431376 INFO : Training has run successfully!
821 14:22:10.431837
822 14:22:10.432304 channel==0
823 14:22:10.436985 RxClkDly_Margin_A0==88 ps 9
824 14:22:10.437461 TxDqDly_Margin_A0==98 ps 10
825 14:22:10.442578 RxClkDly_Margin_A1==88 ps 9
826 14:22:10.443038 TxDqDly_Margin_A1==88 ps 9
827 14:22:10.443456 TrainedVREFDQ_A0==74
828 14:22:10.448343 TrainedVREFDQ_A1==74
829 14:22:10.448851 VrefDac_Margin_A0==24
830 14:22:10.449260 DeviceVref_Margin_A0==40
831 14:22:10.453771 VrefDac_Margin_A1==25
832 14:22:10.454258 DeviceVref_Margin_A1==40
833 14:22:10.454643
834 14:22:10.455025
835 14:22:10.455405 channel==1
836 14:22:10.459398 RxClkDly_Margin_A0==88 ps 9
837 14:22:10.459852 TxDqDly_Margin_A0==88 ps 9
838 14:22:10.464965 RxClkDly_Margin_A1==88 ps 9
839 14:22:10.465417 TxDqDly_Margin_A1==88 ps 9
840 14:22:10.470584 TrainedVREFDQ_A0==77
841 14:22:10.471044 TrainedVREFDQ_A1==77
842 14:22:10.471434 VrefDac_Margin_A0==23
843 14:22:10.476226 DeviceVref_Margin_A0==37
844 14:22:10.476682 VrefDac_Margin_A1==24
845 14:22:10.477069 DeviceVref_Margin_A1==37
846 14:22:10.481806
847 14:22:10.482261 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 14:22:10.482652
849 14:22:10.515294 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 14:22:10.515835 2D training succeed
851 14:22:10.520965 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 14:22:10.526602 auto size-- 65535DDR cs0 size: 2048MB
853 14:22:10.527048 DDR cs1 size: 2048MB
854 14:22:10.532234 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 14:22:10.532683 cs0 DataBus test pass
856 14:22:10.537805 cs1 DataBus test pass
857 14:22:10.538256 cs0 AddrBus test pass
858 14:22:10.538642 cs1 AddrBus test pass
859 14:22:10.539025
860 14:22:10.543369 100bdlr_step_size ps== 420
861 14:22:10.543834 result report
862 14:22:10.548963 boot times 0Enable ddr reg access
863 14:22:10.554023 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 14:22:10.567508 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 14:22:11.140559 0.0;M3 CHK:0;cm4_sp_mode 0
866 14:22:11.141161 MVN_1=0x00000000
867 14:22:11.146046 MVN_2=0x00000000
868 14:22:11.151823 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 14:22:11.152373 OPS=0x10
870 14:22:11.152793 ring efuse init
871 14:22:11.153198 chipver efuse init
872 14:22:11.157407 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 14:22:11.163008 [0.018960 Inits done]
874 14:22:11.163484 secure task start!
875 14:22:11.163890 high task start!
876 14:22:11.167618 low task start!
877 14:22:11.168117 run into bl31
878 14:22:11.174279 NOTICE: BL31: v1.3(release):4fc40b1
879 14:22:11.182034 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 14:22:11.182506 NOTICE: BL31: G12A normal boot!
881 14:22:11.207386 NOTICE: BL31: BL33 decompress pass
882 14:22:11.212095 ERROR: Error initializing runtime service opteed_fast
883 14:22:12.445961
884 14:22:12.446575
885 14:22:12.454361 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 14:22:12.454842
887 14:22:12.455263 Model: Libre Computer AML-A311D-CC Alta
888 14:22:12.662721 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 14:22:12.686145 DRAM: 2 GiB (effective 3.8 GiB)
890 14:22:12.829161 Core: 408 devices, 31 uclasses, devicetree: separate
891 14:22:12.835019 WDT: Not starting watchdog@f0d0
892 14:22:12.867307 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 14:22:12.879705 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 14:22:12.883824 ** Bad device specification mmc 0 **
895 14:22:12.895305 Card did not respond to voltage select! : -110
896 14:22:12.902648 ** Bad device specification mmc 0 **
897 14:22:12.903110 Couldn't find partition mmc 0
898 14:22:12.911040 Card did not respond to voltage select! : -110
899 14:22:12.916548 ** Bad device specification mmc 0 **
900 14:22:12.917007 Couldn't find partition mmc 0
901 14:22:12.921581 Error: could not access storage.
902 14:22:13.265106 Net: eth0: ethernet@ff3f0000
903 14:22:13.265700 starting USB...
904 14:22:13.516944 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 14:22:13.517516 Starting the controller
906 14:22:13.523898 USB XHCI 1.10
907 14:22:15.078079 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 14:22:15.086530 scanning usb for storage devices... 0 Storage Device(s) found
910 14:22:15.138017 Hit any key to stop autoboot: 1
911 14:22:15.138866 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 14:22:15.139617 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 14:22:15.140156 Setting prompt string to ['=>']
914 14:22:15.140656 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 14:22:15.153331 0
916 14:22:15.154204 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 14:22:15.154704 Sending with 10 millisecond of delay
919 14:22:16.289418 => setenv autoload no
920 14:22:16.300235 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 14:22:16.305205 setenv autoload no
922 14:22:16.305926 Sending with 10 millisecond of delay
924 14:22:18.103354 => setenv initrd_high 0xffffffff
925 14:22:18.114250 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 14:22:18.115222 setenv initrd_high 0xffffffff
927 14:22:18.116036 Sending with 10 millisecond of delay
929 14:22:19.733364 => setenv fdt_high 0xffffffff
930 14:22:19.744297 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
931 14:22:19.745271 setenv fdt_high 0xffffffff
932 14:22:19.746019 Sending with 10 millisecond of delay
934 14:22:20.037992 => dhcp
935 14:22:20.048530 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 14:22:20.049076 dhcp
937 14:22:20.049321 Speed: 1000, full duplex
938 14:22:20.049537 BOOTP broadcast 1
939 14:22:20.295830 BOOTP broadcast 2
940 14:22:20.797706 BOOTP broadcast 3
941 14:22:20.817831 DHCP client bound to address 192.168.6.33 (769 ms)
942 14:22:20.818623 Sending with 10 millisecond of delay
944 14:22:22.495839 => setenv serverip 192.168.6.2
945 14:22:22.506711 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
946 14:22:22.507578 setenv serverip 192.168.6.2
947 14:22:22.508319 Sending with 10 millisecond of delay
949 14:22:26.233241 => tftpboot 0x01080000 745049/tftp-deploy-t9w3g4cu/kernel/uImage
950 14:22:26.244005 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
951 14:22:26.244700 tftpboot 0x01080000 745049/tftp-deploy-t9w3g4cu/kernel/uImage
952 14:22:26.244961 Speed: 1000, full duplex
953 14:22:26.245179 Using ethernet@ff3f0000 device
954 14:22:26.246741 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
955 14:22:26.252405 Filename '745049/tftp-deploy-t9w3g4cu/kernel/uImage'.
956 14:22:26.255548 Load address: 0x1080000
957 14:22:31.291408 Loading: *################################################## 43.4 MiB
958 14:22:31.292037 8.6 MiB/s
959 14:22:31.292446 done
960 14:22:31.294969 Bytes transferred = 45482560 (2b60240 hex)
961 14:22:31.295670 Sending with 10 millisecond of delay
963 14:22:35.981760 => tftpboot 0x08000000 745049/tftp-deploy-t9w3g4cu/ramdisk/ramdisk.cpio.gz.uboot
964 14:22:35.992729 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:07)
965 14:22:35.993715 tftpboot 0x08000000 745049/tftp-deploy-t9w3g4cu/ramdisk/ramdisk.cpio.gz.uboot
966 14:22:35.994292 Speed: 1000, full duplex
967 14:22:35.994830 Using ethernet@ff3f0000 device
968 14:22:35.995444 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
969 14:22:36.006258 Filename '745049/tftp-deploy-t9w3g4cu/ramdisk/ramdisk.cpio.gz.uboot'.
970 14:22:36.006791 Load address: 0x8000000
971 14:22:38.970978 Loading: *########################## UDP wrong checksum 000000ff 0000ee87
972 14:22:38.989603 UDP wrong checksum 000000ff 0000817a
973 14:22:47.063379 ##############T ######### UDP wrong checksum 0000000f 00008585
974 14:22:52.064160 T UDP wrong checksum 0000000f 00008585
975 14:22:54.387820 UDP wrong checksum 000000ff 0000394a
976 14:22:54.398702 UDP wrong checksum 000000ff 0000bc3c
977 14:23:02.066317 T T UDP wrong checksum 0000000f 00008585
978 14:23:22.069100 T T T UDP wrong checksum 0000000f 00008585
979 14:23:33.984426 T T T UDP wrong checksum 000000ff 000094f4
980 14:23:34.011077 UDP wrong checksum 000000ff 000029e7
981 14:23:37.075202
982 14:23:37.075642 Retry count exceeded; starting again
984 14:23:37.076541 end: 2.4.3 bootloader-commands (duration 00:01:22) [common]
987 14:23:37.077502 end: 2.4 uboot-commands (duration 00:01:54) [common]
989 14:23:37.078210 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
991 14:23:37.078768 end: 2 uboot-action (duration 00:01:54) [common]
993 14:23:37.079766 Cleaning after the job
994 14:23:37.080189 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/ramdisk
995 14:23:37.081121 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/kernel
996 14:23:37.095751 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/dtb
997 14:23:37.096766 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745049/tftp-deploy-t9w3g4cu/modules
998 14:23:37.100599 start: 4.1 power-off (timeout 00:00:30) [common]
999 14:23:37.101262 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1000 14:23:37.135054 >> OK - accepted request
1001 14:23:37.137264 Returned 0 in 0 seconds
1002 14:23:37.238138 end: 4.1 power-off (duration 00:00:00) [common]
1004 14:23:37.239183 start: 4.2 read-feedback (timeout 00:10:00) [common]
1005 14:23:37.239904 Listened to connection for namespace 'common' for up to 1s
1006 14:23:38.240778 Finalising connection for namespace 'common'
1007 14:23:38.241252 Disconnecting from shell: Finalise
1008 14:23:38.241536 =>
1009 14:23:38.342155 end: 4.2 read-feedback (duration 00:00:01) [common]
1010 14:23:38.342744 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/745049
1011 14:23:38.997379 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/745049
1012 14:23:38.998004 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.