Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 15:08:04.921246 lava-dispatcher, installed at version: 2024.01
2 15:08:04.922050 start: 0 validate
3 15:08:04.922552 Start time: 2024-09-19 15:08:04.922501+00:00 (UTC)
4 15:08:04.923132 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 15:08:04.923681 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 15:08:04.978843 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 15:08:04.979423 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 15:08:05.018915 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 15:08:05.019545 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 15:08:05.052844 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 15:08:05.053321 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 15:08:05.098267 validate duration: 0.18
14 15:08:05.099845 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 15:08:05.100544 start: 1.1 download-retry (timeout 00:10:00) [common]
16 15:08:05.101164 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 15:08:05.102158 Not decompressing ramdisk as can be used compressed.
18 15:08:05.102925 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 15:08:05.103235 saving as /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/ramdisk/rootfs.cpio.gz
20 15:08:05.103547 total size: 47897469 (45 MB)
21 15:08:05.144457 progress 0 % (0 MB)
22 15:08:05.192783 progress 5 % (2 MB)
23 15:08:05.223458 progress 10 % (4 MB)
24 15:08:05.253994 progress 15 % (6 MB)
25 15:08:05.284175 progress 20 % (9 MB)
26 15:08:05.314691 progress 25 % (11 MB)
27 15:08:05.344758 progress 30 % (13 MB)
28 15:08:05.374814 progress 35 % (16 MB)
29 15:08:05.405380 progress 40 % (18 MB)
30 15:08:05.435191 progress 45 % (20 MB)
31 15:08:05.465196 progress 50 % (22 MB)
32 15:08:05.500689 progress 55 % (25 MB)
33 15:08:05.532063 progress 60 % (27 MB)
34 15:08:05.562583 progress 65 % (29 MB)
35 15:08:05.592834 progress 70 % (32 MB)
36 15:08:05.623082 progress 75 % (34 MB)
37 15:08:05.653402 progress 80 % (36 MB)
38 15:08:05.683642 progress 85 % (38 MB)
39 15:08:05.714000 progress 90 % (41 MB)
40 15:08:05.744088 progress 95 % (43 MB)
41 15:08:05.773827 progress 100 % (45 MB)
42 15:08:05.774600 45 MB downloaded in 0.67 s (68.07 MB/s)
43 15:08:05.775169 end: 1.1.1 http-download (duration 00:00:01) [common]
45 15:08:05.776100 end: 1.1 download-retry (duration 00:00:01) [common]
46 15:08:05.776418 start: 1.2 download-retry (timeout 00:09:59) [common]
47 15:08:05.776708 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 15:08:05.777206 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/kernel/Image
49 15:08:05.777464 saving as /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/kernel/Image
50 15:08:05.777680 total size: 45482496 (43 MB)
51 15:08:05.777899 No compression specified
52 15:08:05.821687 progress 0 % (0 MB)
53 15:08:05.849874 progress 5 % (2 MB)
54 15:08:05.878176 progress 10 % (4 MB)
55 15:08:05.906652 progress 15 % (6 MB)
56 15:08:05.934622 progress 20 % (8 MB)
57 15:08:05.963319 progress 25 % (10 MB)
58 15:08:05.991623 progress 30 % (13 MB)
59 15:08:06.019469 progress 35 % (15 MB)
60 15:08:06.047777 progress 40 % (17 MB)
61 15:08:06.077587 progress 45 % (19 MB)
62 15:08:06.107089 progress 50 % (21 MB)
63 15:08:06.134712 progress 55 % (23 MB)
64 15:08:06.162380 progress 60 % (26 MB)
65 15:08:06.190378 progress 65 % (28 MB)
66 15:08:06.218135 progress 70 % (30 MB)
67 15:08:06.246235 progress 75 % (32 MB)
68 15:08:06.274252 progress 80 % (34 MB)
69 15:08:06.301981 progress 85 % (36 MB)
70 15:08:06.329926 progress 90 % (39 MB)
71 15:08:06.357421 progress 95 % (41 MB)
72 15:08:06.384918 progress 100 % (43 MB)
73 15:08:06.385427 43 MB downloaded in 0.61 s (71.37 MB/s)
74 15:08:06.385925 end: 1.2.1 http-download (duration 00:00:01) [common]
76 15:08:06.386758 end: 1.2 download-retry (duration 00:00:01) [common]
77 15:08:06.387051 start: 1.3 download-retry (timeout 00:09:59) [common]
78 15:08:06.387327 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 15:08:06.387811 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 15:08:06.388114 saving as /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 15:08:06.388335 total size: 53209 (0 MB)
82 15:08:06.388559 No compression specified
83 15:08:06.433493 progress 61 % (0 MB)
84 15:08:06.434638 progress 100 % (0 MB)
85 15:08:06.435200 0 MB downloaded in 0.05 s (1.08 MB/s)
86 15:08:06.435696 end: 1.3.1 http-download (duration 00:00:00) [common]
88 15:08:06.436571 end: 1.3 download-retry (duration 00:00:00) [common]
89 15:08:06.436847 start: 1.4 download-retry (timeout 00:09:59) [common]
90 15:08:06.437119 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 15:08:06.437599 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/modules.tar.xz
92 15:08:06.437846 saving as /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/modules/modules.tar
93 15:08:06.438057 total size: 11582224 (11 MB)
94 15:08:06.438275 Using unxz to decompress xz
95 15:08:06.479920 progress 0 % (0 MB)
96 15:08:06.548069 progress 5 % (0 MB)
97 15:08:06.638280 progress 10 % (1 MB)
98 15:08:06.726170 progress 15 % (1 MB)
99 15:08:06.815414 progress 20 % (2 MB)
100 15:08:06.898100 progress 25 % (2 MB)
101 15:08:06.987172 progress 30 % (3 MB)
102 15:08:07.063207 progress 35 % (3 MB)
103 15:08:07.149070 progress 40 % (4 MB)
104 15:08:07.246972 progress 45 % (5 MB)
105 15:08:07.322343 progress 50 % (5 MB)
106 15:08:07.406377 progress 55 % (6 MB)
107 15:08:07.484741 progress 60 % (6 MB)
108 15:08:07.564984 progress 65 % (7 MB)
109 15:08:07.645127 progress 70 % (7 MB)
110 15:08:07.728031 progress 75 % (8 MB)
111 15:08:07.820049 progress 80 % (8 MB)
112 15:08:07.919394 progress 85 % (9 MB)
113 15:08:07.994963 progress 90 % (9 MB)
114 15:08:08.069588 progress 95 % (10 MB)
115 15:08:08.145893 progress 100 % (11 MB)
116 15:08:08.159586 11 MB downloaded in 1.72 s (6.42 MB/s)
117 15:08:08.160417 end: 1.4.1 http-download (duration 00:00:02) [common]
119 15:08:08.162256 end: 1.4 download-retry (duration 00:00:02) [common]
120 15:08:08.162783 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 15:08:08.163299 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 15:08:08.163784 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 15:08:08.164409 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 15:08:08.165524 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101
125 15:08:08.166445 makedir: /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin
126 15:08:08.167112 makedir: /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/tests
127 15:08:08.167724 makedir: /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/results
128 15:08:08.168382 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-add-keys
129 15:08:08.169505 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-add-sources
130 15:08:08.170587 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-background-process-start
131 15:08:08.171612 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-background-process-stop
132 15:08:08.172769 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-common-functions
133 15:08:08.173712 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-echo-ipv4
134 15:08:08.174771 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-install-packages
135 15:08:08.175842 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-installed-packages
136 15:08:08.176945 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-os-build
137 15:08:08.177962 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-probe-channel
138 15:08:08.178998 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-probe-ip
139 15:08:08.179971 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-target-ip
140 15:08:08.181332 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-target-mac
141 15:08:08.182415 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-target-storage
142 15:08:08.183472 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-test-case
143 15:08:08.184600 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-test-event
144 15:08:08.185628 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-test-feedback
145 15:08:08.186658 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-test-raise
146 15:08:08.187633 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-test-reference
147 15:08:08.188697 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-test-runner
148 15:08:08.189775 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-test-set
149 15:08:08.190767 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-test-shell
150 15:08:08.191731 Updating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-install-packages (oe)
151 15:08:08.192730 Updating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/bin/lava-installed-packages (oe)
152 15:08:08.193553 Creating /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/environment
153 15:08:08.194353 LAVA metadata
154 15:08:08.194916 - LAVA_JOB_ID=745017
155 15:08:08.195356 - LAVA_DISPATCHER_IP=192.168.6.2
156 15:08:08.196205 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 15:08:08.198257 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 15:08:08.198913 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 15:08:08.199329 skipped lava-vland-overlay
160 15:08:08.199892 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 15:08:08.200308 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 15:08:08.200538 skipped lava-multinode-overlay
163 15:08:08.200845 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 15:08:08.201123 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 15:08:08.201422 Loading test definitions
166 15:08:08.201716 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 15:08:08.201984 Using /lava-745017 at stage 0
168 15:08:08.203243 uuid=745017_1.5.2.4.1 testdef=None
169 15:08:08.203565 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 15:08:08.203905 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 15:08:08.206132 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 15:08:08.207047 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 15:08:08.209732 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 15:08:08.210709 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 15:08:08.213138 runner path: /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/0/tests/0_igt-gpu-panfrost test_uuid 745017_1.5.2.4.1
178 15:08:08.213736 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 15:08:08.214553 Creating lava-test-runner.conf files
181 15:08:08.214761 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/745017/lava-overlay-t5v_h101/lava-745017/0 for stage 0
182 15:08:08.215103 - 0_igt-gpu-panfrost
183 15:08:08.215525 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 15:08:08.215858 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 15:08:08.242337 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 15:08:08.242769 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 15:08:08.243036 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 15:08:08.243305 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 15:08:08.243569 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 15:08:15.457776 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 15:08:15.458260 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 15:08:15.458623 extracting modules file /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/modules/modules.tar to /var/lib/lava/dispatcher/tmp/745017/extract-overlay-ramdisk-8a6f8i2g/ramdisk
193 15:08:16.921217 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 15:08:16.921666 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 15:08:16.921942 [common] Applying overlay /var/lib/lava/dispatcher/tmp/745017/compress-overlay-8lcwnuky/overlay-1.5.2.5.tar.gz to ramdisk
196 15:08:16.922155 [common] Applying overlay /var/lib/lava/dispatcher/tmp/745017/compress-overlay-8lcwnuky/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/745017/extract-overlay-ramdisk-8a6f8i2g/ramdisk
197 15:08:16.952264 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 15:08:16.952700 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 15:08:16.952971 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 15:08:16.953198 Converting downloaded kernel to a uImage
201 15:08:16.953503 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/kernel/Image /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/kernel/uImage
202 15:08:17.441002 output: Image Name:
203 15:08:17.441409 output: Created: Thu Sep 19 15:08:16 2024
204 15:08:17.441618 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 15:08:17.441819 output: Data Size: 45482496 Bytes = 44416.50 KiB = 43.38 MiB
206 15:08:17.442016 output: Load Address: 01080000
207 15:08:17.442214 output: Entry Point: 01080000
208 15:08:17.442410 output:
209 15:08:17.442737 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 15:08:17.443002 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 15:08:17.443266 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 15:08:17.443517 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 15:08:17.443769 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 15:08:17.444048 Building ramdisk /var/lib/lava/dispatcher/tmp/745017/extract-overlay-ramdisk-8a6f8i2g/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/745017/extract-overlay-ramdisk-8a6f8i2g/ramdisk
215 15:08:24.502321 >> 501793 blocks
216 15:08:45.127863 Adding RAMdisk u-boot header.
217 15:08:45.128549 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/745017/extract-overlay-ramdisk-8a6f8i2g/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/745017/extract-overlay-ramdisk-8a6f8i2g/ramdisk.cpio.gz.uboot
218 15:08:45.808653 output: Image Name:
219 15:08:45.809078 output: Created: Thu Sep 19 15:08:45 2024
220 15:08:45.809284 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 15:08:45.809487 output: Data Size: 65677445 Bytes = 64138.13 KiB = 62.63 MiB
222 15:08:45.809686 output: Load Address: 00000000
223 15:08:45.809882 output: Entry Point: 00000000
224 15:08:45.810077 output:
225 15:08:45.810704 rename /var/lib/lava/dispatcher/tmp/745017/extract-overlay-ramdisk-8a6f8i2g/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/ramdisk/ramdisk.cpio.gz.uboot
226 15:08:45.811122 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 15:08:45.811403 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 15:08:45.811672 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 15:08:45.811911 No LXC device requested
230 15:08:45.812429 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 15:08:45.812935 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 15:08:45.813435 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 15:08:45.813839 Checking files for TFTP limit of 4294967296 bytes.
234 15:08:45.816503 end: 1 tftp-deploy (duration 00:00:41) [common]
235 15:08:45.817096 start: 2 uboot-action (timeout 00:05:00) [common]
236 15:08:45.817614 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 15:08:45.818099 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 15:08:45.818590 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 15:08:45.819107 Using kernel file from prepare-kernel: 745017/tftp-deploy-h7rkxj72/kernel/uImage
240 15:08:45.819727 substitutions:
241 15:08:45.820171 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 15:08:45.820569 - {DTB_ADDR}: 0x01070000
243 15:08:45.820966 - {DTB}: 745017/tftp-deploy-h7rkxj72/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 15:08:45.821364 - {INITRD}: 745017/tftp-deploy-h7rkxj72/ramdisk/ramdisk.cpio.gz.uboot
245 15:08:45.821755 - {KERNEL_ADDR}: 0x01080000
246 15:08:45.822141 - {KERNEL}: 745017/tftp-deploy-h7rkxj72/kernel/uImage
247 15:08:45.822530 - {LAVA_MAC}: None
248 15:08:45.822953 - {PRESEED_CONFIG}: None
249 15:08:45.823347 - {PRESEED_LOCAL}: None
250 15:08:45.823732 - {RAMDISK_ADDR}: 0x08000000
251 15:08:45.824144 - {RAMDISK}: 745017/tftp-deploy-h7rkxj72/ramdisk/ramdisk.cpio.gz.uboot
252 15:08:45.824536 - {ROOT_PART}: None
253 15:08:45.824920 - {ROOT}: None
254 15:08:45.825304 - {SERVER_IP}: 192.168.6.2
255 15:08:45.825690 - {TEE_ADDR}: 0x83000000
256 15:08:45.826073 - {TEE}: None
257 15:08:45.826455 Parsed boot commands:
258 15:08:45.826829 - setenv autoload no
259 15:08:45.827210 - setenv initrd_high 0xffffffff
260 15:08:45.827591 - setenv fdt_high 0xffffffff
261 15:08:45.827968 - dhcp
262 15:08:45.828375 - setenv serverip 192.168.6.2
263 15:08:45.828756 - tftpboot 0x01080000 745017/tftp-deploy-h7rkxj72/kernel/uImage
264 15:08:45.829140 - tftpboot 0x08000000 745017/tftp-deploy-h7rkxj72/ramdisk/ramdisk.cpio.gz.uboot
265 15:08:45.829521 - tftpboot 0x01070000 745017/tftp-deploy-h7rkxj72/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 15:08:45.829903 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 15:08:45.830288 - bootm 0x01080000 0x08000000 0x01070000
268 15:08:45.830774 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 15:08:45.832263 start: 2.3 connect-device (timeout 00:05:00) [common]
271 15:08:45.832697 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 15:08:45.848612 Setting prompt string to ['lava-test: # ']
273 15:08:45.850094 end: 2.3 connect-device (duration 00:00:00) [common]
274 15:08:45.850684 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 15:08:45.851213 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 15:08:45.851712 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 15:08:45.853182 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 15:08:45.890122 >> OK - accepted request
279 15:08:45.892752 Returned 0 in 0 seconds
280 15:08:45.993860 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 15:08:45.995459 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 15:08:45.996063 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 15:08:45.996573 Setting prompt string to ['Hit any key to stop autoboot']
285 15:08:45.997020 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 15:08:45.998592 Trying 192.168.56.21...
287 15:08:45.999050 Connected to conserv1.
288 15:08:45.999458 Escape character is '^]'.
289 15:08:45.999862
290 15:08:46.000310 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 15:08:46.000726
292 15:08:53.315881 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 15:08:53.316548 bl2_stage_init 0x01
294 15:08:53.316976 bl2_stage_init 0x81
295 15:08:53.321470 hw id: 0x0000 - pwm id 0x01
296 15:08:53.321964 bl2_stage_init 0xc1
297 15:08:53.326612 bl2_stage_init 0x02
298 15:08:53.327078
299 15:08:53.327486 L0:00000000
300 15:08:53.327882 L1:00000703
301 15:08:53.328316 L2:00008067
302 15:08:53.332182 L3:15000000
303 15:08:53.332637 S1:00000000
304 15:08:53.333031 B2:20282000
305 15:08:53.333416 B1:a0f83180
306 15:08:53.333799
307 15:08:53.334183 TE: 68914
308 15:08:53.334565
309 15:08:53.337719 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 15:08:53.343392
311 15:08:53.343839 Board ID = 1
312 15:08:53.344268 Set cpu clk to 24M
313 15:08:53.344654 Set clk81 to 24M
314 15:08:53.346807 Use GP1_pll as DSU clk.
315 15:08:53.347242 DSU clk: 1200 Mhz
316 15:08:53.352282 CPU clk: 1200 MHz
317 15:08:53.352721 Set clk81 to 166.6M
318 15:08:53.358162 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 15:08:53.358629 board id: 1
320 15:08:53.367661 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 15:08:53.378339 fw parse done
322 15:08:53.384334 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 15:08:53.427037 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 15:08:53.437903 PIEI prepare done
325 15:08:53.438332 fastboot data load
326 15:08:53.438728 fastboot data verify
327 15:08:53.443501 verify result: 266
328 15:08:53.449105 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 15:08:53.449542 LPDDR4 probe
330 15:08:53.449929 ddr clk to 1584MHz
331 15:08:53.457187 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 15:08:53.494340
333 15:08:53.494778 dmc_version 0001
334 15:08:53.501141 Check phy result
335 15:08:53.506996 INFO : End of CA training
336 15:08:53.507430 INFO : End of initialization
337 15:08:53.512581 INFO : Training has run successfully!
338 15:08:53.513011 Check phy result
339 15:08:53.518152 INFO : End of initialization
340 15:08:53.518585 INFO : End of read enable training
341 15:08:53.521554 INFO : End of fine write leveling
342 15:08:53.527162 INFO : End of Write leveling coarse delay
343 15:08:53.532723 INFO : Training has run successfully!
344 15:08:53.533154 Check phy result
345 15:08:53.533543 INFO : End of initialization
346 15:08:53.538294 INFO : End of read dq deskew training
347 15:08:53.541695 INFO : End of MPR read delay center optimization
348 15:08:53.547283 INFO : End of write delay center optimization
349 15:08:53.552843 INFO : End of read delay center optimization
350 15:08:53.553289 INFO : End of max read latency training
351 15:08:53.558427 INFO : Training has run successfully!
352 15:08:53.558861 1D training succeed
353 15:08:53.566564 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 15:08:53.614246 Check phy result
355 15:08:53.614690 INFO : End of initialization
356 15:08:53.635516 INFO : End of 2D read delay Voltage center optimization
357 15:08:53.655664 INFO : End of 2D read delay Voltage center optimization
358 15:08:53.707560 INFO : End of 2D write delay Voltage center optimization
359 15:08:53.756809 INFO : End of 2D write delay Voltage center optimization
360 15:08:53.762350 INFO : Training has run successfully!
361 15:08:53.762778
362 15:08:53.763170 channel==0
363 15:08:53.767961 RxClkDly_Margin_A0==78 ps 8
364 15:08:53.768435 TxDqDly_Margin_A0==98 ps 10
365 15:08:53.773594 RxClkDly_Margin_A1==88 ps 9
366 15:08:53.774019 TxDqDly_Margin_A1==98 ps 10
367 15:08:53.774411 TrainedVREFDQ_A0==74
368 15:08:53.779204 TrainedVREFDQ_A1==74
369 15:08:53.779631 VrefDac_Margin_A0==24
370 15:08:53.780059 DeviceVref_Margin_A0==40
371 15:08:53.784765 VrefDac_Margin_A1==23
372 15:08:53.785201 DeviceVref_Margin_A1==40
373 15:08:53.785588
374 15:08:53.785977
375 15:08:53.790387 channel==1
376 15:08:53.790816 RxClkDly_Margin_A0==78 ps 8
377 15:08:53.791209 TxDqDly_Margin_A0==98 ps 10
378 15:08:53.796007 RxClkDly_Margin_A1==88 ps 9
379 15:08:53.796447 TxDqDly_Margin_A1==78 ps 8
380 15:08:53.801476 TrainedVREFDQ_A0==75
381 15:08:53.801915 TrainedVREFDQ_A1==75
382 15:08:53.802305 VrefDac_Margin_A0==22
383 15:08:53.807187 DeviceVref_Margin_A0==39
384 15:08:53.807613 VrefDac_Margin_A1==22
385 15:08:53.812686 DeviceVref_Margin_A1==39
386 15:08:53.813114
387 15:08:53.813508 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 15:08:53.813894
389 15:08:53.846246 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 15:08:53.846756 2D training succeed
391 15:08:53.851875 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 15:08:53.857500 auto size-- 65535DDR cs0 size: 2048MB
393 15:08:53.857931 DDR cs1 size: 2048MB
394 15:08:53.863166 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 15:08:53.863595 cs0 DataBus test pass
396 15:08:53.868702 cs1 DataBus test pass
397 15:08:53.869129 cs0 AddrBus test pass
398 15:08:53.869513 cs1 AddrBus test pass
399 15:08:53.869893
400 15:08:53.874289 100bdlr_step_size ps== 478
401 15:08:53.874729 result report
402 15:08:53.879921 boot times 0Enable ddr reg access
403 15:08:53.885276 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 15:08:53.898975 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 15:08:54.554089 bl2z: ptr: 05129330, size: 00001e40
406 15:08:54.562442 0.0;M3 CHK:0;cm4_sp_mode 0
407 15:08:54.562927 MVN_1=0x00000000
408 15:08:54.563336 MVN_2=0x00000000
409 15:08:54.573979 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 15:08:54.574438 OPS=0x04
411 15:08:54.574848 ring efuse init
412 15:08:54.579415 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 15:08:54.579875 [0.017319 Inits done]
414 15:08:54.580318 secure task start!
415 15:08:54.587439 high task start!
416 15:08:54.587918 low task start!
417 15:08:54.588354 run into bl31
418 15:08:54.595845 NOTICE: BL31: v1.3(release):4fc40b1
419 15:08:54.603741 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 15:08:54.604253 NOTICE: BL31: G12A normal boot!
421 15:08:54.619241 NOTICE: BL31: BL33 decompress pass
422 15:08:54.624961 ERROR: Error initializing runtime service opteed_fast
423 15:08:55.870506 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 15:08:55.871083 bl2_stage_init 0x01
425 15:08:55.871494 bl2_stage_init 0x81
426 15:08:55.876182 hw id: 0x0000 - pwm id 0x01
427 15:08:55.876634 bl2_stage_init 0xc1
428 15:08:55.881678 bl2_stage_init 0x02
429 15:08:55.882119
430 15:08:55.882524 L0:00000000
431 15:08:55.882918 L1:00000703
432 15:08:55.883310 L2:00008067
433 15:08:55.883700 L3:15000000
434 15:08:55.887326 S1:00000000
435 15:08:55.887772 B2:20282000
436 15:08:55.888216 B1:a0f83180
437 15:08:55.888619
438 15:08:55.889016 TE: 71884
439 15:08:55.889411
440 15:08:55.892899 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 15:08:55.893350
442 15:08:55.898594 Board ID = 1
443 15:08:55.899033 Set cpu clk to 24M
444 15:08:55.899434 Set clk81 to 24M
445 15:08:55.904156 Use GP1_pll as DSU clk.
446 15:08:55.904615 DSU clk: 1200 Mhz
447 15:08:55.905018 CPU clk: 1200 MHz
448 15:08:55.909737 Set clk81 to 166.6M
449 15:08:55.915302 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 15:08:55.915751 board id: 1
451 15:08:55.922612 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 15:08:55.933503 fw parse done
453 15:08:55.939459 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 15:08:55.982434 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 15:08:55.993618 PIEI prepare done
456 15:08:55.994056 fastboot data load
457 15:08:55.994460 fastboot data verify
458 15:08:55.999207 verify result: 266
459 15:08:56.007539 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 15:08:56.007977 LPDDR4 probe
461 15:08:56.008431 ddr clk to 1584MHz
462 15:08:57.364997 Load ddrfw from SPI, s SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 15:08:57.365585 bl2_stage_init 0x01
464 15:08:57.366000 bl2_stage_init 0x81
465 15:08:57.370473 hw id: 0x0000 - pwm id 0x01
466 15:08:57.370924 bl2_stage_init 0xc1
467 15:08:57.376200 bl2_stage_init 0x02
468 15:08:57.376643
469 15:08:57.377048 L0:00000000
470 15:08:57.377441 L1:00000703
471 15:08:57.377836 L2:00008067
472 15:08:57.378222 L3:15000000
473 15:08:57.381749 S1:00000000
474 15:08:57.382192 B2:20282000
475 15:08:57.382593 B1:a0f83180
476 15:08:57.382987
477 15:08:57.383380 TE: 68128
478 15:08:57.383772
479 15:08:57.387421 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 15:08:57.387869
481 15:08:57.392904 Board ID = 1
482 15:08:57.393351 Set cpu clk to 24M
483 15:08:57.393753 Set clk81 to 24M
484 15:08:57.398414 Use GP1_pll as DSU clk.
485 15:08:57.398858 DSU clk: 1200 Mhz
486 15:08:57.399262 CPU clk: 1200 MHz
487 15:08:57.404114 Set clk81 to 166.6M
488 15:08:57.409684 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 15:08:57.410129 board id: 1
490 15:08:57.417122 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 15:08:57.427595 fw parse done
492 15:08:57.433443 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 15:08:57.476071 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 15:08:57.487084 PIEI prepare done
495 15:08:57.487529 fastboot data load
496 15:08:57.487934 fastboot data verify
497 15:08:57.492711 verify result: 266
498 15:08:57.498241 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 15:08:57.498679 LPDDR4 probe
500 15:08:57.499081 ddr clk to 1584MHz
501 15:08:57.506210 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 15:08:57.543428
503 15:08:57.543867 dmc_version 0001
504 15:08:57.550186 Check phy result
505 15:08:57.556088 INFO : End of CA training
506 15:08:57.556533 INFO : End of initialization
507 15:08:57.561733 INFO : Training has run successfully!
508 15:08:57.562169 Check phy result
509 15:08:57.567291 INFO : End of initialization
510 15:08:57.567747 INFO : End of read enable training
511 15:08:57.572895 INFO : End of fine write leveling
512 15:08:57.578478 INFO : End of Write leveling coarse delay
513 15:08:57.578913 INFO : Training has run successfully!
514 15:08:57.579319 Check phy result
515 15:08:57.584120 INFO : End of initialization
516 15:08:57.584558 INFO : End of read dq deskew training
517 15:08:57.589735 INFO : End of MPR read delay center optimization
518 15:08:57.595269 INFO : End of write delay center optimization
519 15:08:57.600885 INFO : End of read delay center optimization
520 15:08:57.601327 INFO : End of max read latency training
521 15:08:57.606468 INFO : Training has run successfully!
522 15:08:57.606905 1D training succeed
523 15:08:57.615638 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 15:08:57.663181 Check phy result
525 15:08:57.663637 INFO : End of initialization
526 15:08:57.685547 INFO : End of 2D read delay Voltage center optimization
527 15:08:57.704800 INFO : End of 2D read delay Voltage center optimization
528 15:08:57.756676 INFO : End of 2D write delay Voltage center optimization
529 15:08:57.805844 INFO : End of 2D write delay Voltage center optimization
530 15:08:57.811422 INFO : Training has run successfully!
531 15:08:57.811879
532 15:08:57.812343 channel==0
533 15:08:57.817035 RxClkDly_Margin_A0==88 ps 9
534 15:08:57.817473 TxDqDly_Margin_A0==88 ps 9
535 15:08:57.821215 RxClkDly_Margin_A1==88 ps 9
536 15:08:57.825080 TxDqDly_Margin_A1==98 ps 10
537 15:08:57.825522 TrainedVREFDQ_A0==75
538 15:08:57.825926 TrainedVREFDQ_A1==74
539 15:08:57.830868 VrefDac_Margin_A0==24
540 15:08:57.831304 DeviceVref_Margin_A0==39
541 15:08:57.831703 VrefDac_Margin_A1==22
542 15:08:57.836217 DeviceVref_Margin_A1==40
543 15:08:57.836648
544 15:08:57.837051
545 15:08:57.837448 channel==1
546 15:08:57.841944 RxClkDly_Margin_A0==78 ps 8
547 15:08:57.842380 TxDqDly_Margin_A0==88 ps 9
548 15:08:57.842783 RxClkDly_Margin_A1==88 ps 9
549 15:08:57.847469 TxDqDly_Margin_A1==78 ps 8
550 15:08:57.847903 TrainedVREFDQ_A0==76
551 15:08:57.852960 TrainedVREFDQ_A1==77
552 15:08:57.853396 VrefDac_Margin_A0==22
553 15:08:57.853791 DeviceVref_Margin_A0==38
554 15:08:57.858699 VrefDac_Margin_A1==22
555 15:08:57.859136 DeviceVref_Margin_A1==37
556 15:08:57.859537
557 15:08:57.864241 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 15:08:57.864682
559 15:08:57.892181 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
560 15:08:57.897821 2D training succeed
561 15:08:57.903380 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 15:08:57.903827 auto size-- 65535DDR cs0 size: 2048MB
563 15:08:57.908997 DDR cs1 size: 2048MB
564 15:08:57.909459 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 15:08:57.914609 cs0 DataBus test pass
566 15:08:57.915054 cs1 DataBus test pass
567 15:08:57.915454 cs0 AddrBus test pass
568 15:08:57.920214 cs1 AddrBus test pass
569 15:08:57.920653
570 15:08:57.921053 100bdlr_step_size ps== 478
571 15:08:57.925854 result report
572 15:08:57.926293 boot times 0Enable ddr reg access
573 15:08:57.934058 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 15:08:57.947870 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 15:08:58.602089 bl2z: ptr: 05129330, size: 00001e40
576 15:08:58.609158 0.0;M3 CHK:0;cm4_sp_mode 0
577 15:08:58.609643 MVN_1=0x00000000
578 15:08:58.610053 MVN_2=0x00000000
579 15:08:58.620683 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 15:08:58.621140 OPS=0x04
581 15:08:58.621548 ring efuse init
582 15:08:58.626228 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 15:08:58.626679 [0.017319 Inits done]
584 15:08:58.627083 secure task start!
585 15:08:58.633984 high task start!
586 15:08:58.634436 low task start!
587 15:08:58.634836 run into bl31
588 15:08:58.642594 NOTICE: BL31: v1.3(release):4fc40b1
589 15:08:58.650360 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 15:08:58.650811 NOTICE: BL31: G12A normal boot!
591 15:08:58.665803 NOTICE: BL31: BL33 decompress pass
592 15:08:58.671535 ERROR: Error initializing runtime service opteed_fast
593 15:08:59.918440 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 15:08:59.918858 bl2_stage_init 0x01
595 15:08:59.919072 bl2_stage_init 0x81
596 15:08:59.924069 hw id: 0x0000 - pwm id 0x01
597 15:08:59.924554 bl2_stage_init 0xc1
598 15:08:59.924969 bl2_stage_init 0x02
599 15:08:59.925369
600 15:08:59.929761 L0:00000000
601 15:08:59.930222 L1:00000703
602 15:08:59.930627 L2:00008067
603 15:08:59.931023 L3:15000000
604 15:08:59.931415 S1:00000000
605 15:08:59.935361 B2:20282000
606 15:08:59.935822 B1:a0f83180
607 15:08:59.936267
608 15:08:59.936667 TE: 70859
609 15:08:59.937065
610 15:08:59.940969 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 15:08:59.941423
612 15:08:59.946573 Board ID = 1
613 15:08:59.947027 Set cpu clk to 24M
614 15:08:59.947434 Set clk81 to 24M
615 15:08:59.952193 Use GP1_pll as DSU clk.
616 15:08:59.952674 DSU clk: 1200 Mhz
617 15:08:59.953076 CPU clk: 1200 MHz
618 15:08:59.953469 Set clk81 to 166.6M
619 15:08:59.963317 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 15:08:59.963807 board id: 1
621 15:08:59.969738 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 15:08:59.980453 fw parse done
623 15:08:59.986392 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 15:09:00.029075 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 15:09:00.040070 PIEI prepare done
626 15:09:00.040560 fastboot data load
627 15:09:00.040973 fastboot data verify
628 15:09:00.045653 verify result: 266
629 15:09:00.051206 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 15:09:00.051665 LPDDR4 probe
631 15:09:00.052109 ddr clk to 1584MHz
632 15:09:00.059209 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 15:09:00.096468
634 15:09:00.096982 dmc_version 0001
635 15:09:00.103166 Check phy result
636 15:09:00.109084 INFO : End of CA training
637 15:09:00.109580 INFO : End of initialization
638 15:09:00.114659 INFO : Training has run successfully!
639 15:09:00.115140 Check phy result
640 15:09:00.120270 INFO : End of initialization
641 15:09:00.120747 INFO : End of read enable training
642 15:09:00.125828 INFO : End of fine write leveling
643 15:09:00.131438 INFO : End of Write leveling coarse delay
644 15:09:00.131909 INFO : Training has run successfully!
645 15:09:00.132353 Check phy result
646 15:09:00.137081 INFO : End of initialization
647 15:09:00.137558 INFO : End of read dq deskew training
648 15:09:00.142679 INFO : End of MPR read delay center optimization
649 15:09:00.148269 INFO : End of write delay center optimization
650 15:09:00.153834 INFO : End of read delay center optimization
651 15:09:00.154309 INFO : End of max read latency training
652 15:09:00.159412 INFO : Training has run successfully!
653 15:09:00.159868 1D training succeed
654 15:09:00.168576 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 15:09:00.216220 Check phy result
656 15:09:00.216718 INFO : End of initialization
657 15:09:00.238579 INFO : End of 2D read delay Voltage center optimization
658 15:09:00.257747 INFO : End of 2D read delay Voltage center optimization
659 15:09:00.309605 INFO : End of 2D write delay Voltage center optimization
660 15:09:00.358808 INFO : End of 2D write delay Voltage center optimization
661 15:09:00.364396 INFO : Training has run successfully!
662 15:09:00.364872
663 15:09:00.365285 channel==0
664 15:09:00.370061 RxClkDly_Margin_A0==78 ps 8
665 15:09:00.370510 TxDqDly_Margin_A0==98 ps 10
666 15:09:00.375579 RxClkDly_Margin_A1==88 ps 9
667 15:09:00.376078 TxDqDly_Margin_A1==88 ps 9
668 15:09:00.376497 TrainedVREFDQ_A0==75
669 15:09:00.381184 TrainedVREFDQ_A1==74
670 15:09:00.381635 VrefDac_Margin_A0==24
671 15:09:00.382033 DeviceVref_Margin_A0==39
672 15:09:00.386812 VrefDac_Margin_A1==22
673 15:09:00.387264 DeviceVref_Margin_A1==40
674 15:09:00.387666
675 15:09:00.388096
676 15:09:00.388494 channel==1
677 15:09:00.392361 RxClkDly_Margin_A0==78 ps 8
678 15:09:00.392809 TxDqDly_Margin_A0==98 ps 10
679 15:09:00.398071 RxClkDly_Margin_A1==78 ps 8
680 15:09:00.398521 TxDqDly_Margin_A1==88 ps 9
681 15:09:00.403544 TrainedVREFDQ_A0==78
682 15:09:00.404045 TrainedVREFDQ_A1==78
683 15:09:00.404458 VrefDac_Margin_A0==22
684 15:09:00.409218 DeviceVref_Margin_A0==36
685 15:09:00.409664 VrefDac_Margin_A1==20
686 15:09:00.414819 DeviceVref_Margin_A1==36
687 15:09:00.415269
688 15:09:00.415672 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 15:09:00.416103
690 15:09:00.448298 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000062
691 15:09:00.448783 2D training succeed
692 15:09:00.454067 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 15:09:00.459592 auto size-- 65535DDR cs0 size: 2048MB
694 15:09:00.460066 DDR cs1 size: 2048MB
695 15:09:00.465148 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 15:09:00.465595 cs0 DataBus test pass
697 15:09:00.470844 cs1 DataBus test pass
698 15:09:00.471290 cs0 AddrBus test pass
699 15:09:00.471694 cs1 AddrBus test pass
700 15:09:00.472126
701 15:09:00.476384 100bdlr_step_size ps== 478
702 15:09:00.476842 result report
703 15:09:00.482054 boot times 0Enable ddr reg access
704 15:09:00.487140 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 15:09:00.500919 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 15:09:01.155910 bl2z: ptr: 05129330, size: 00001e40
707 15:09:01.163763 0.0;M3 CHK:0;cm4_sp_mode 0
708 15:09:01.164471 MVN_1=0x00000000
709 15:09:01.164959 MVN_2=0x00000000
710 15:09:01.175183 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 15:09:01.175675 OPS=0x04
712 15:09:01.176168 ring efuse init
713 15:09:01.180825 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 15:09:01.181313 [0.017310 Inits done]
715 15:09:01.181744 secure task start!
716 15:09:01.188105 high task start!
717 15:09:01.188569 low task start!
718 15:09:01.188997 run into bl31
719 15:09:01.196670 NOTICE: BL31: v1.3(release):4fc40b1
720 15:09:01.204452 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 15:09:01.204917 NOTICE: BL31: G12A normal boot!
722 15:09:01.220038 NOTICE: BL31: BL33 decompress pass
723 15:09:01.225738 ERROR: Error initializing runtime service opteed_fast
724 15:09:02.021108
725 15:09:02.021661
726 15:09:02.026554 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 15:09:02.027078
728 15:09:02.030005 Model: Libre Computer AML-S905D3-CC Solitude
729 15:09:02.177032 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 15:09:02.192455 DRAM: 2 GiB (effective 3.8 GiB)
731 15:09:02.293423 Core: 406 devices, 33 uclasses, devicetree: separate
732 15:09:02.299375 WDT: Not starting watchdog@f0d0
733 15:09:02.324345 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 15:09:02.336680 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 15:09:02.341598 ** Bad device specification mmc 0 **
736 15:09:02.351700 Card did not respond to voltage select! : -110
737 15:09:02.359285 ** Bad device specification mmc 0 **
738 15:09:02.359824 Couldn't find partition mmc 0
739 15:09:02.367656 Card did not respond to voltage select! : -110
740 15:09:02.373210 ** Bad device specification mmc 0 **
741 15:09:02.373748 Couldn't find partition mmc 0
742 15:09:02.378291 Error: could not access storage.
743 15:09:02.674730 Net: eth0: ethernet@ff3f0000
744 15:09:02.675403 starting USB...
745 15:09:02.919442 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 15:09:02.919893 Starting the controller
747 15:09:02.926414 USB XHCI 1.10
748 15:09:04.480820 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 15:09:04.489160 scanning usb for storage devices... 0 Storage Device(s) found
751 15:09:04.540426 Hit any key to stop autoboot: 1
752 15:09:04.541218 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 15:09:04.541901 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 15:09:04.542426 Setting prompt string to ['=>']
755 15:09:04.542951 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 15:09:04.554963 0
757 15:09:04.555939 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 15:09:04.657298 => setenv autoload no
760 15:09:04.658030 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 15:09:04.663356 setenv autoload no
763 15:09:04.764909 => setenv initrd_high 0xffffffff
764 15:09:04.765616 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 15:09:04.770389 setenv initrd_high 0xffffffff
767 15:09:04.871921 => setenv fdt_high 0xffffffff
768 15:09:04.872718 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 15:09:04.877422 setenv fdt_high 0xffffffff
771 15:09:04.979011 => dhcp
772 15:09:04.979791 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 15:09:04.984282 dhcp
774 15:09:05.990219 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 15:09:05.990881 Speed: 1000, full duplex
776 15:09:05.991351 BOOTP broadcast 1
777 15:09:06.238159 BOOTP broadcast 2
778 15:09:06.739370 BOOTP broadcast 3
779 15:09:07.740349 BOOTP broadcast 4
780 15:09:09.741234 BOOTP broadcast 5
781 15:09:09.752684 DHCP client bound to address 192.168.6.12 (3762 ms)
783 15:09:09.854337 => setenv serverip 192.168.6.2
784 15:09:09.855148 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
785 15:09:09.859832 setenv serverip 192.168.6.2
787 15:09:09.961557 => tftpboot 0x01080000 745017/tftp-deploy-h7rkxj72/kernel/uImage
788 15:09:09.962398 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
789 15:09:09.969153 tftpboot 0x01080000 745017/tftp-deploy-h7rkxj72/kernel/uImage
790 15:09:09.969670 Speed: 1000, full duplex
791 15:09:09.970128 Using ethernet@ff3f0000 device
792 15:09:09.974635 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 15:09:09.980230 Filename '745017/tftp-deploy-h7rkxj72/kernel/uImage'.
794 15:09:09.984114 Load address: 0x1080000
795 15:09:13.559084 Loading: *################################################## 43.4 MiB
796 15:09:13.559744 12.1 MiB/s
797 15:09:13.560279 done
798 15:09:13.563503 Bytes transferred = 45482560 (2b60240 hex)
800 15:09:13.665237 => tftpboot 0x08000000 745017/tftp-deploy-h7rkxj72/ramdisk/ramdisk.cpio.gz.uboot
801 15:09:13.666024 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
802 15:09:13.672818 tftpboot 0x08000000 745017/tftp-deploy-h7rkxj72/ramdisk/ramdisk.cpio.gz.uboot
803 15:09:13.673313 Speed: 1000, full duplex
804 15:09:13.673746 Using ethernet@ff3f0000 device
805 15:09:13.678228 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
806 15:09:13.691544 Filename '745017/tftp-deploy-h7rkxj72/ramdisk/ramdisk.cpio.gz.uboot'.
807 15:09:13.692188 Load address: 0x8000000
808 15:09:23.920852 Loading: *#############T #################################### UDP wrong checksum 0000000f 0000752b
809 15:09:28.921294 T UDP wrong checksum 0000000f 0000752b
810 15:09:38.921915 T T UDP wrong checksum 0000000f 0000752b
811 15:09:58.927340 T T T T UDP wrong checksum 0000000f 0000752b
812 15:10:13.931067 T T
813 15:10:13.931691 Retry count exceeded; starting again
815 15:10:13.933169 end: 2.4.3 bootloader-commands (duration 00:01:09) [common]
818 15:10:13.935044 end: 2.4 uboot-commands (duration 00:01:28) [common]
820 15:10:13.937302 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
822 15:10:13.938475 end: 2 uboot-action (duration 00:01:28) [common]
824 15:10:13.940188 Cleaning after the job
825 15:10:13.940763 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/ramdisk
826 15:10:13.942208 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/kernel
827 15:10:13.987768 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/dtb
828 15:10:13.988691 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745017/tftp-deploy-h7rkxj72/modules
829 15:10:14.010771 start: 4.1 power-off (timeout 00:00:30) [common]
830 15:10:14.011497 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
831 15:10:14.045859 >> OK - accepted request
832 15:10:14.047630 Returned 0 in 0 seconds
833 15:10:14.148591 end: 4.1 power-off (duration 00:00:00) [common]
835 15:10:14.149973 start: 4.2 read-feedback (timeout 00:10:00) [common]
836 15:10:14.150699 Listened to connection for namespace 'common' for up to 1s
837 15:10:15.151650 Finalising connection for namespace 'common'
838 15:10:15.152553 Disconnecting from shell: Finalise
839 15:10:15.153158 =>
840 15:10:15.254300 end: 4.2 read-feedback (duration 00:00:01) [common]
841 15:10:15.255163 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/745017
842 15:10:15.890735 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/745017
843 15:10:15.891354 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.