Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 14:24:23.245821 lava-dispatcher, installed at version: 2024.01
2 14:24:23.246558 start: 0 validate
3 14:24:23.247036 Start time: 2024-09-19 14:24:23.247006+00:00 (UTC)
4 14:24:23.247617 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:24:23.248185 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:24:23.290799 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:24:23.291351 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 14:24:23.326910 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:24:23.327546 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 14:24:23.362512 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:24:23.363033 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:24:23.394424 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 14:24:23.394930 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 14:24:23.438876 validate duration: 0.19
16 14:24:23.440352 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:24:23.440942 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:24:23.441513 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:24:23.442448 Not decompressing ramdisk as can be used compressed.
20 14:24:23.443194 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 14:24:23.443698 saving as /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/ramdisk/initrd.cpio.gz
22 14:24:23.444236 total size: 5628169 (5 MB)
23 14:24:23.486819 progress 0 % (0 MB)
24 14:24:23.495383 progress 5 % (0 MB)
25 14:24:23.504423 progress 10 % (0 MB)
26 14:24:23.512423 progress 15 % (0 MB)
27 14:24:23.520791 progress 20 % (1 MB)
28 14:24:23.526016 progress 25 % (1 MB)
29 14:24:23.530119 progress 30 % (1 MB)
30 14:24:23.534204 progress 35 % (1 MB)
31 14:24:23.537798 progress 40 % (2 MB)
32 14:24:23.542911 progress 45 % (2 MB)
33 14:24:23.546627 progress 50 % (2 MB)
34 14:24:23.550722 progress 55 % (2 MB)
35 14:24:23.554910 progress 60 % (3 MB)
36 14:24:23.558662 progress 65 % (3 MB)
37 14:24:23.562739 progress 70 % (3 MB)
38 14:24:23.566316 progress 75 % (4 MB)
39 14:24:23.570339 progress 80 % (4 MB)
40 14:24:23.574029 progress 85 % (4 MB)
41 14:24:23.578051 progress 90 % (4 MB)
42 14:24:23.581932 progress 95 % (5 MB)
43 14:24:23.585214 progress 100 % (5 MB)
44 14:24:23.585850 5 MB downloaded in 0.14 s (37.90 MB/s)
45 14:24:23.586380 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:24:23.587284 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:24:23.587580 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:24:23.587852 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:24:23.588359 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/kernel/Image
51 14:24:23.588607 saving as /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/kernel/Image
52 14:24:23.588816 total size: 45482496 (43 MB)
53 14:24:23.589026 No compression specified
54 14:24:23.628454 progress 0 % (0 MB)
55 14:24:23.656620 progress 5 % (2 MB)
56 14:24:23.684354 progress 10 % (4 MB)
57 14:24:23.712277 progress 15 % (6 MB)
58 14:24:23.740038 progress 20 % (8 MB)
59 14:24:23.768548 progress 25 % (10 MB)
60 14:24:23.796206 progress 30 % (13 MB)
61 14:24:23.823587 progress 35 % (15 MB)
62 14:24:23.851845 progress 40 % (17 MB)
63 14:24:23.879457 progress 45 % (19 MB)
64 14:24:23.907261 progress 50 % (21 MB)
65 14:24:23.934807 progress 55 % (23 MB)
66 14:24:23.962353 progress 60 % (26 MB)
67 14:24:23.990488 progress 65 % (28 MB)
68 14:24:24.018916 progress 70 % (30 MB)
69 14:24:24.047150 progress 75 % (32 MB)
70 14:24:24.074951 progress 80 % (34 MB)
71 14:24:24.102136 progress 85 % (36 MB)
72 14:24:24.130239 progress 90 % (39 MB)
73 14:24:24.157624 progress 95 % (41 MB)
74 14:24:24.184893 progress 100 % (43 MB)
75 14:24:24.185392 43 MB downloaded in 0.60 s (72.71 MB/s)
76 14:24:24.185959 end: 1.2.1 http-download (duration 00:00:01) [common]
78 14:24:24.186838 end: 1.2 download-retry (duration 00:00:01) [common]
79 14:24:24.187118 start: 1.3 download-retry (timeout 00:09:59) [common]
80 14:24:24.187385 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 14:24:24.187852 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 14:24:24.188153 saving as /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/dtb/meson-g12b-a311d-libretech-cc.dtb
83 14:24:24.188364 total size: 54703 (0 MB)
84 14:24:24.188571 No compression specified
85 14:24:24.227286 progress 59 % (0 MB)
86 14:24:24.228134 progress 100 % (0 MB)
87 14:24:24.228680 0 MB downloaded in 0.04 s (1.29 MB/s)
88 14:24:24.229155 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:24:24.229962 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:24:24.230366 start: 1.4 download-retry (timeout 00:09:59) [common]
92 14:24:24.230662 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 14:24:24.231122 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 14:24:24.231359 saving as /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/nfsrootfs/full.rootfs.tar
95 14:24:24.231563 total size: 120894716 (115 MB)
96 14:24:24.231773 Using unxz to decompress xz
97 14:24:24.268138 progress 0 % (0 MB)
98 14:24:25.052786 progress 5 % (5 MB)
99 14:24:25.883608 progress 10 % (11 MB)
100 14:24:26.672344 progress 15 % (17 MB)
101 14:24:27.403195 progress 20 % (23 MB)
102 14:24:27.991602 progress 25 % (28 MB)
103 14:24:28.809597 progress 30 % (34 MB)
104 14:24:29.603780 progress 35 % (40 MB)
105 14:24:29.949701 progress 40 % (46 MB)
106 14:24:30.323521 progress 45 % (51 MB)
107 14:24:31.038738 progress 50 % (57 MB)
108 14:24:31.916846 progress 55 % (63 MB)
109 14:24:32.699370 progress 60 % (69 MB)
110 14:24:33.453550 progress 65 % (74 MB)
111 14:24:34.233240 progress 70 % (80 MB)
112 14:24:35.061506 progress 75 % (86 MB)
113 14:24:35.849116 progress 80 % (92 MB)
114 14:24:36.612899 progress 85 % (98 MB)
115 14:24:37.469520 progress 90 % (103 MB)
116 14:24:38.240957 progress 95 % (109 MB)
117 14:24:39.072636 progress 100 % (115 MB)
118 14:24:39.085732 115 MB downloaded in 14.85 s (7.76 MB/s)
119 14:24:39.086380 end: 1.4.1 http-download (duration 00:00:15) [common]
121 14:24:39.087774 end: 1.4 download-retry (duration 00:00:15) [common]
122 14:24:39.088221 start: 1.5 download-retry (timeout 00:09:44) [common]
123 14:24:39.088526 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 14:24:39.089043 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/modules.tar.xz
125 14:24:39.089321 saving as /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/modules/modules.tar
126 14:24:39.089538 total size: 11582224 (11 MB)
127 14:24:39.089764 Using unxz to decompress xz
128 14:24:39.134367 progress 0 % (0 MB)
129 14:24:39.199843 progress 5 % (0 MB)
130 14:24:39.281242 progress 10 % (1 MB)
131 14:24:39.364165 progress 15 % (1 MB)
132 14:24:39.448469 progress 20 % (2 MB)
133 14:24:39.527845 progress 25 % (2 MB)
134 14:24:39.612499 progress 30 % (3 MB)
135 14:24:39.687481 progress 35 % (3 MB)
136 14:24:39.767216 progress 40 % (4 MB)
137 14:24:39.848028 progress 45 % (5 MB)
138 14:24:39.921612 progress 50 % (5 MB)
139 14:24:40.004373 progress 55 % (6 MB)
140 14:24:40.080907 progress 60 % (6 MB)
141 14:24:40.159732 progress 65 % (7 MB)
142 14:24:40.238274 progress 70 % (7 MB)
143 14:24:40.319143 progress 75 % (8 MB)
144 14:24:40.408435 progress 80 % (8 MB)
145 14:24:40.505876 progress 85 % (9 MB)
146 14:24:40.579739 progress 90 % (9 MB)
147 14:24:40.652004 progress 95 % (10 MB)
148 14:24:40.725906 progress 100 % (11 MB)
149 14:24:40.738067 11 MB downloaded in 1.65 s (6.70 MB/s)
150 14:24:40.738622 end: 1.5.1 http-download (duration 00:00:02) [common]
152 14:24:40.739436 end: 1.5 download-retry (duration 00:00:02) [common]
153 14:24:40.739704 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 14:24:40.739968 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 14:24:57.272915 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/745056/extract-nfsrootfs-a_7i071f
156 14:24:57.273520 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 14:24:57.273807 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 14:24:57.274496 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc
159 14:24:57.274942 makedir: /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin
160 14:24:57.275269 makedir: /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/tests
161 14:24:57.275584 makedir: /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/results
162 14:24:57.275916 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-add-keys
163 14:24:57.276490 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-add-sources
164 14:24:57.277000 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-background-process-start
165 14:24:57.277497 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-background-process-stop
166 14:24:57.278047 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-common-functions
167 14:24:57.278561 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-echo-ipv4
168 14:24:57.279049 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-install-packages
169 14:24:57.279536 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-installed-packages
170 14:24:57.280040 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-os-build
171 14:24:57.280539 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-probe-channel
172 14:24:57.281025 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-probe-ip
173 14:24:57.281504 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-target-ip
174 14:24:57.281984 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-target-mac
175 14:24:57.282460 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-target-storage
176 14:24:57.282949 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-test-case
177 14:24:57.283433 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-test-event
178 14:24:57.283909 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-test-feedback
179 14:24:57.284443 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-test-raise
180 14:24:57.284926 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-test-reference
181 14:24:57.285407 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-test-runner
182 14:24:57.285897 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-test-set
183 14:24:57.286378 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-test-shell
184 14:24:57.286869 Updating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-add-keys (debian)
185 14:24:57.287410 Updating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-add-sources (debian)
186 14:24:57.288018 Updating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-install-packages (debian)
187 14:24:57.288590 Updating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-installed-packages (debian)
188 14:24:57.289146 Updating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/bin/lava-os-build (debian)
189 14:24:57.289597 Creating /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/environment
190 14:24:57.289974 LAVA metadata
191 14:24:57.290235 - LAVA_JOB_ID=745056
192 14:24:57.290448 - LAVA_DISPATCHER_IP=192.168.6.2
193 14:24:57.290817 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 14:24:57.291785 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 14:24:57.292149 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 14:24:57.292359 skipped lava-vland-overlay
197 14:24:57.292600 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 14:24:57.292871 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 14:24:57.293084 skipped lava-multinode-overlay
200 14:24:57.293323 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 14:24:57.293572 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 14:24:57.293825 Loading test definitions
203 14:24:57.294130 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 14:24:57.294367 Using /lava-745056 at stage 0
205 14:24:57.295543 uuid=745056_1.6.2.4.1 testdef=None
206 14:24:57.295855 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 14:24:57.296156 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 14:24:57.297760 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 14:24:57.298549 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 14:24:57.300591 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 14:24:57.301424 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 14:24:57.303323 runner path: /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/0/tests/0_timesync-off test_uuid 745056_1.6.2.4.1
215 14:24:57.303914 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 14:24:57.304759 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 14:24:57.304983 Using /lava-745056 at stage 0
219 14:24:57.305352 Fetching tests from https://github.com/kernelci/test-definitions.git
220 14:24:57.305668 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/0/tests/1_kselftest-alsa'
221 14:25:02.990623 Running '/usr/bin/git checkout kernelci.org
222 14:25:03.498498 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 14:25:03.500063 uuid=745056_1.6.2.4.5 testdef=None
224 14:25:03.500473 end: 1.6.2.4.5 git-repo-action (duration 00:00:06) [common]
226 14:25:03.501254 start: 1.6.2.4.6 test-overlay (timeout 00:09:20) [common]
227 14:25:03.506870 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 14:25:03.509051 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:20) [common]
230 14:25:03.515368 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 14:25:03.516382 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:20) [common]
233 14:25:03.520643 runner path: /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/0/tests/1_kselftest-alsa test_uuid 745056_1.6.2.4.5
234 14:25:03.521028 BOARD='meson-g12b-a311d-libretech-cc'
235 14:25:03.521280 BRANCH='mainline'
236 14:25:03.521482 SKIPFILE='/dev/null'
237 14:25:03.521680 SKIP_INSTALL='True'
238 14:25:03.521876 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 14:25:03.522076 TST_CASENAME=''
240 14:25:03.522273 TST_CMDFILES='alsa'
241 14:25:03.523203 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 14:25:03.524152 Creating lava-test-runner.conf files
244 14:25:03.524375 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/745056/lava-overlay-8ndcqikc/lava-745056/0 for stage 0
245 14:25:03.524843 - 0_timesync-off
246 14:25:03.525160 - 1_kselftest-alsa
247 14:25:03.525552 end: 1.6.2.4 test-definition (duration 00:00:06) [common]
248 14:25:03.525899 start: 1.6.2.5 compress-overlay (timeout 00:09:20) [common]
249 14:25:27.002781 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 14:25:27.003225 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:56) [common]
251 14:25:27.003489 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 14:25:27.003759 end: 1.6.2 lava-overlay (duration 00:00:30) [common]
253 14:25:27.004044 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:56) [common]
254 14:25:27.673124 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 14:25:27.673917 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
256 14:25:27.674435 extracting modules file /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/745056/extract-nfsrootfs-a_7i071f
257 14:25:29.052850 extracting modules file /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/745056/extract-overlay-ramdisk-srlnnt63/ramdisk
258 14:25:30.461023 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 14:25:30.461499 start: 1.6.5 apply-overlay-tftp (timeout 00:08:53) [common]
260 14:25:30.461778 [common] Applying overlay to NFS
261 14:25:30.461992 [common] Applying overlay /var/lib/lava/dispatcher/tmp/745056/compress-overlay-mbx14m42/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/745056/extract-nfsrootfs-a_7i071f
262 14:25:33.507435 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 14:25:33.507904 start: 1.6.6 prepare-kernel (timeout 00:08:50) [common]
264 14:25:33.508215 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:50) [common]
265 14:25:33.508448 Converting downloaded kernel to a uImage
266 14:25:33.508762 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/kernel/Image /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/kernel/uImage
267 14:25:34.010582 output: Image Name:
268 14:25:34.011008 output: Created: Thu Sep 19 14:25:33 2024
269 14:25:34.011242 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 14:25:34.011465 output: Data Size: 45482496 Bytes = 44416.50 KiB = 43.38 MiB
271 14:25:34.011672 output: Load Address: 01080000
272 14:25:34.011875 output: Entry Point: 01080000
273 14:25:34.012118 output:
274 14:25:34.012473 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 14:25:34.012786 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 14:25:34.013085 start: 1.6.7 configure-preseed-file (timeout 00:08:49) [common]
277 14:25:34.013376 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 14:25:34.013658 start: 1.6.8 compress-ramdisk (timeout 00:08:49) [common]
279 14:25:34.013962 Building ramdisk /var/lib/lava/dispatcher/tmp/745056/extract-overlay-ramdisk-srlnnt63/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/745056/extract-overlay-ramdisk-srlnnt63/ramdisk
280 14:25:36.205243 >> 166205 blocks
281 14:25:44.027093 Adding RAMdisk u-boot header.
282 14:25:44.027547 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/745056/extract-overlay-ramdisk-srlnnt63/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/745056/extract-overlay-ramdisk-srlnnt63/ramdisk.cpio.gz.uboot
283 14:25:44.306739 output: Image Name:
284 14:25:44.307181 output: Created: Thu Sep 19 14:25:44 2024
285 14:25:44.307671 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 14:25:44.308305 output: Data Size: 23391631 Bytes = 22843.39 KiB = 22.31 MiB
287 14:25:44.308777 output: Load Address: 00000000
288 14:25:44.309227 output: Entry Point: 00000000
289 14:25:44.309673 output:
290 14:25:44.310872 rename /var/lib/lava/dispatcher/tmp/745056/extract-overlay-ramdisk-srlnnt63/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/ramdisk/ramdisk.cpio.gz.uboot
291 14:25:44.311667 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 14:25:44.312332 end: 1.6 prepare-tftp-overlay (duration 00:01:04) [common]
293 14:25:44.312931 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:39) [common]
294 14:25:44.313452 No LXC device requested
295 14:25:44.314018 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 14:25:44.314595 start: 1.8 deploy-device-env (timeout 00:08:39) [common]
297 14:25:44.315151 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 14:25:44.315615 Checking files for TFTP limit of 4294967296 bytes.
299 14:25:44.318577 end: 1 tftp-deploy (duration 00:01:21) [common]
300 14:25:44.319220 start: 2 uboot-action (timeout 00:05:00) [common]
301 14:25:44.319806 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 14:25:44.320402 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 14:25:44.320971 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 14:25:44.321556 Using kernel file from prepare-kernel: 745056/tftp-deploy-uwaxng3u/kernel/uImage
305 14:25:44.322253 substitutions:
306 14:25:44.322712 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 14:25:44.323165 - {DTB_ADDR}: 0x01070000
308 14:25:44.323613 - {DTB}: 745056/tftp-deploy-uwaxng3u/dtb/meson-g12b-a311d-libretech-cc.dtb
309 14:25:44.324090 - {INITRD}: 745056/tftp-deploy-uwaxng3u/ramdisk/ramdisk.cpio.gz.uboot
310 14:25:44.324538 - {KERNEL_ADDR}: 0x01080000
311 14:25:44.324976 - {KERNEL}: 745056/tftp-deploy-uwaxng3u/kernel/uImage
312 14:25:44.325417 - {LAVA_MAC}: None
313 14:25:44.325898 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/745056/extract-nfsrootfs-a_7i071f
314 14:25:44.326346 - {NFS_SERVER_IP}: 192.168.6.2
315 14:25:44.326783 - {PRESEED_CONFIG}: None
316 14:25:44.327214 - {PRESEED_LOCAL}: None
317 14:25:44.327645 - {RAMDISK_ADDR}: 0x08000000
318 14:25:44.328119 - {RAMDISK}: 745056/tftp-deploy-uwaxng3u/ramdisk/ramdisk.cpio.gz.uboot
319 14:25:44.328563 - {ROOT_PART}: None
320 14:25:44.328999 - {ROOT}: None
321 14:25:44.329431 - {SERVER_IP}: 192.168.6.2
322 14:25:44.329859 - {TEE_ADDR}: 0x83000000
323 14:25:44.330286 - {TEE}: None
324 14:25:44.330713 Parsed boot commands:
325 14:25:44.331131 - setenv autoload no
326 14:25:44.331559 - setenv initrd_high 0xffffffff
327 14:25:44.332010 - setenv fdt_high 0xffffffff
328 14:25:44.332445 - dhcp
329 14:25:44.332873 - setenv serverip 192.168.6.2
330 14:25:44.333302 - tftpboot 0x01080000 745056/tftp-deploy-uwaxng3u/kernel/uImage
331 14:25:44.333736 - tftpboot 0x08000000 745056/tftp-deploy-uwaxng3u/ramdisk/ramdisk.cpio.gz.uboot
332 14:25:44.334170 - tftpboot 0x01070000 745056/tftp-deploy-uwaxng3u/dtb/meson-g12b-a311d-libretech-cc.dtb
333 14:25:44.334603 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/745056/extract-nfsrootfs-a_7i071f,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 14:25:44.335043 - bootm 0x01080000 0x08000000 0x01070000
335 14:25:44.335606 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 14:25:44.337271 start: 2.3 connect-device (timeout 00:05:00) [common]
338 14:25:44.337738 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 14:25:44.353272 Setting prompt string to ['lava-test: # ']
340 14:25:44.354933 end: 2.3 connect-device (duration 00:00:00) [common]
341 14:25:44.355621 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 14:25:44.356516 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 14:25:44.356983 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 14:25:44.357616 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 14:25:44.399390 >> OK - accepted request
346 14:25:44.401429 Returned 0 in 0 seconds
347 14:25:44.502688 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 14:25:44.504526 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 14:25:44.505145 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 14:25:44.505684 Setting prompt string to ['Hit any key to stop autoboot']
352 14:25:44.506175 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 14:25:44.507871 Trying 192.168.56.21...
354 14:25:44.508424 Connected to conserv1.
355 14:25:44.508864 Escape character is '^]'.
356 14:25:44.509320
357 14:25:44.509767 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 14:25:44.510236
359 14:25:56.056861 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
360 14:25:56.057263 bl2_stage_init 0x81
361 14:25:56.062653 hw id: 0x0000 - pwm id 0x01
362 14:25:56.062993 bl2_stage_init 0xc1
363 14:25:56.063248 bl2_stage_init 0x02
364 14:25:56.063487
365 14:25:56.067974 L0:00000000
366 14:25:56.068304 L1:20000703
367 14:25:56.068548 L2:00008067
368 14:25:56.068794 L3:14000000
369 14:25:56.069025 B2:00402000
370 14:25:56.070834 B1:e0f83180
371 14:25:56.071112
372 14:25:56.071346 TE: 58150
373 14:25:56.071573
374 14:25:56.081963 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
375 14:25:56.082291
376 14:25:56.082531 Board ID = 1
377 14:25:56.082754 Set A53 clk to 24M
378 14:25:56.082975 Set A73 clk to 24M
379 14:25:56.087581 Set clk81 to 24M
380 14:25:56.087870 A53 clk: 1200 MHz
381 14:25:56.088128 A73 clk: 1200 MHz
382 14:25:56.090914 CLK81: 166.6M
383 14:25:56.091189 smccc: 00012aac
384 14:25:56.096410 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
385 14:25:56.102160 board id: 1
386 14:25:56.106520 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
387 14:25:56.118123 fw parse done
388 14:25:56.123063 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
389 14:25:56.165770 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
390 14:25:56.177805 PIEI prepare done
391 14:25:56.178391 fastboot data load
392 14:25:56.178841 fastboot data verify
393 14:25:56.183338 verify result: 266
394 14:25:56.188846 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
395 14:25:56.189520 LPDDR4 probe
396 14:25:56.190075 ddr clk to 1584MHz
397 14:25:56.195824 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
398 14:25:56.233144
399 14:25:56.233828 dmc_version 0001
400 14:25:56.239685 Check phy result
401 14:25:56.246677 INFO : End of CA training
402 14:25:56.247242 INFO : End of initialization
403 14:25:56.252324 INFO : Training has run successfully!
404 14:25:56.252827 Check phy result
405 14:25:56.257763 INFO : End of initialization
406 14:25:56.258269 INFO : End of read enable training
407 14:25:56.261094 INFO : End of fine write leveling
408 14:25:56.266712 INFO : End of Write leveling coarse delay
409 14:25:56.272242 INFO : Training has run successfully!
410 14:25:56.272867 Check phy result
411 14:25:56.273362 INFO : End of initialization
412 14:25:56.277914 INFO : End of read dq deskew training
413 14:25:56.281290 INFO : End of MPR read delay center optimization
414 14:25:56.286782 INFO : End of write delay center optimization
415 14:25:56.292472 INFO : End of read delay center optimization
416 14:25:56.292988 INFO : End of max read latency training
417 14:25:56.298012 INFO : Training has run successfully!
418 14:25:56.298590 1D training succeed
419 14:25:56.305311 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
420 14:25:56.353076 Check phy result
421 14:25:56.353809 INFO : End of initialization
422 14:25:56.374662 INFO : End of 2D read delay Voltage center optimization
423 14:25:56.394878 INFO : End of 2D read delay Voltage center optimization
424 14:25:56.447155 INFO : End of 2D write delay Voltage center optimization
425 14:25:56.497235 INFO : End of 2D write delay Voltage center optimization
426 14:25:56.502754 INFO : Training has run successfully!
427 14:25:56.503371
428 14:25:56.503844 channel==0
429 14:25:56.508365 RxClkDly_Margin_A0==88 ps 9
430 14:25:56.508890 TxDqDly_Margin_A0==98 ps 10
431 14:25:56.513990 RxClkDly_Margin_A1==88 ps 9
432 14:25:56.514495 TxDqDly_Margin_A1==88 ps 9
433 14:25:56.514940 TrainedVREFDQ_A0==74
434 14:25:56.519622 TrainedVREFDQ_A1==74
435 14:25:56.520147 VrefDac_Margin_A0==25
436 14:25:56.520600 DeviceVref_Margin_A0==40
437 14:25:56.525135 VrefDac_Margin_A1==25
438 14:25:56.525623 DeviceVref_Margin_A1==40
439 14:25:56.526078
440 14:25:56.526536
441 14:25:56.526982 channel==1
442 14:25:56.530757 RxClkDly_Margin_A0==98 ps 10
443 14:25:56.531322 TxDqDly_Margin_A0==98 ps 10
444 14:25:56.536466 RxClkDly_Margin_A1==98 ps 10
445 14:25:56.537022 TxDqDly_Margin_A1==88 ps 9
446 14:25:56.542122 TrainedVREFDQ_A0==77
447 14:25:56.542654 TrainedVREFDQ_A1==77
448 14:25:56.543122 VrefDac_Margin_A0==22
449 14:25:56.547729 DeviceVref_Margin_A0==37
450 14:25:56.548296 VrefDac_Margin_A1==22
451 14:25:56.553182 DeviceVref_Margin_A1==37
452 14:25:56.553733
453 14:25:56.554200 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
454 14:25:56.554667
455 14:25:56.586908 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
456 14:25:56.587359 2D training succeed
457 14:25:56.592287 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
458 14:25:56.597878 auto size-- 65535DDR cs0 size: 2048MB
459 14:25:56.598185 DDR cs1 size: 2048MB
460 14:25:56.603714 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
461 14:25:56.604058 cs0 DataBus test pass
462 14:25:56.609143 cs1 DataBus test pass
463 14:25:56.609444 cs0 AddrBus test pass
464 14:25:56.609659 cs1 AddrBus test pass
465 14:25:56.609873
466 14:25:56.620754 100bdlr_step_size ps== 420
467 14:25:56.621116 result report
468 14:25:56.621329 boot times 0Enable ddr reg access
469 14:25:56.624764 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
470 14:25:56.638175 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
471 14:25:57.212299 0.0;M3 CHK:0;cm4_sp_mode 0
472 14:25:57.212683 MVN_1=0x00000000
473 14:25:57.217745 MVN_2=0x00000000
474 14:25:57.223442 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
475 14:25:57.223718 OPS=0x10
476 14:25:57.223929 ring efuse init
477 14:25:57.224165 chipver efuse init
478 14:25:57.231714 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
479 14:25:57.232027 [0.018961 Inits done]
480 14:25:57.232244 secure task start!
481 14:25:57.238260 high task start!
482 14:25:57.238524 low task start!
483 14:25:57.238732 run into bl31
484 14:25:57.245846 NOTICE: BL31: v1.3(release):4fc40b1
485 14:25:57.252727 NOTICE: BL31: Built : 15:58:17, May 22 2019
486 14:25:57.252998 NOTICE: BL31: G12A normal boot!
487 14:25:57.279114 NOTICE: BL31: BL33 decompress pass
488 14:25:57.283812 ERROR: Error initializing runtime service opteed_fast
489 14:25:58.517823
490 14:25:58.518223
491 14:25:58.525178 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
492 14:25:58.525457
493 14:25:58.525667 Model: Libre Computer AML-A311D-CC Alta
494 14:25:58.733785 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
495 14:25:58.757046 DRAM: 2 GiB (effective 3.8 GiB)
496 14:25:58.901060 Core: 408 devices, 31 uclasses, devicetree: separate
497 14:25:58.905938 WDT: Not starting watchdog@f0d0
498 14:25:58.939140 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
499 14:25:58.951600 Loading Environment from FAT... Card did not respond to voltage select! : -110
500 14:25:58.955507 ** Bad device specification mmc 0 **
501 14:25:58.966991 Card did not respond to voltage select! : -110
502 14:25:58.973568 ** Bad device specification mmc 0 **
503 14:25:58.974105 Couldn't find partition mmc 0
504 14:25:58.982992 Card did not respond to voltage select! : -110
505 14:25:58.988401 ** Bad device specification mmc 0 **
506 14:25:58.988958 Couldn't find partition mmc 0
507 14:25:58.992573 Error: could not access storage.
508 14:26:00.257133 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
509 14:26:00.257667 bl2_stage_init 0x01
510 14:26:00.257949 bl2_stage_init 0x81
511 14:26:00.262668 hw id: 0x0000 - pwm id 0x01
512 14:26:00.263240 bl2_stage_init 0xc1
513 14:26:00.263719 bl2_stage_init 0x02
514 14:26:00.264240
515 14:26:00.268188 L0:00000000
516 14:26:00.268732 L1:20000703
517 14:26:00.269188 L2:00008067
518 14:26:00.269630 L3:14000000
519 14:26:00.273812 B2:00402000
520 14:26:00.274327 B1:e0f83180
521 14:26:00.274781
522 14:26:00.275224 TE: 58124
523 14:26:00.275660
524 14:26:00.279409 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 14:26:00.280097
526 14:26:00.280601 Board ID = 1
527 14:26:00.285001 Set A53 clk to 24M
528 14:26:00.285505 Set A73 clk to 24M
529 14:26:00.285954 Set clk81 to 24M
530 14:26:00.290616 A53 clk: 1200 MHz
531 14:26:00.291147 A73 clk: 1200 MHz
532 14:26:00.291595 CLK81: 166.6M
533 14:26:00.292097 smccc: 00012a92
534 14:26:00.296278 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 14:26:00.301977 board id: 1
536 14:26:00.307001 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 14:26:00.318442 fw parse done
538 14:26:00.323433 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 14:26:00.366245 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 14:26:00.378053 PIEI prepare done
541 14:26:00.378688 fastboot data load
542 14:26:00.379304 fastboot data verify
543 14:26:00.383692 verify result: 266
544 14:26:00.389313 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 14:26:00.389821 LPDDR4 probe
546 14:26:00.390309 ddr clk to 1584MHz
547 14:26:00.396515 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 14:26:00.433418
549 14:26:00.434126 dmc_version 0001
550 14:26:00.440145 Check phy result
551 14:26:00.447022 INFO : End of CA training
552 14:26:00.447691 INFO : End of initialization
553 14:26:00.452464 INFO : Training has run successfully!
554 14:26:00.453044 Check phy result
555 14:26:00.458130 INFO : End of initialization
556 14:26:00.458670 INFO : End of read enable training
557 14:26:00.463757 INFO : End of fine write leveling
558 14:26:00.469441 INFO : End of Write leveling coarse delay
559 14:26:00.470098 INFO : Training has run successfully!
560 14:26:00.470625 Check phy result
561 14:26:00.474845 INFO : End of initialization
562 14:26:00.475160 INFO : End of read dq deskew training
563 14:26:00.480529 INFO : End of MPR read delay center optimization
564 14:26:00.486152 INFO : End of write delay center optimization
565 14:26:00.491657 INFO : End of read delay center optimization
566 14:26:00.492212 INFO : End of max read latency training
567 14:26:00.497351 INFO : Training has run successfully!
568 14:26:00.497903 1D training succeed
569 14:26:00.505562 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 14:26:00.553213 Check phy result
571 14:26:00.553840 INFO : End of initialization
572 14:26:00.574853 INFO : End of 2D read delay Voltage center optimization
573 14:26:00.593942 INFO : End of 2D read delay Voltage center optimization
574 14:26:00.645902 INFO : End of 2D write delay Voltage center optimization
575 14:26:00.696223 INFO : End of 2D write delay Voltage center optimization
576 14:26:00.701598 INFO : Training has run successfully!
577 14:26:00.702051
578 14:26:00.702364 channel==0
579 14:26:00.707348 RxClkDly_Margin_A0==88 ps 9
580 14:26:00.707691 TxDqDly_Margin_A0==98 ps 10
581 14:26:00.710545 RxClkDly_Margin_A1==88 ps 9
582 14:26:00.711023 TxDqDly_Margin_A1==88 ps 9
583 14:26:00.716179 TrainedVREFDQ_A0==74
584 14:26:00.716643 TrainedVREFDQ_A1==74
585 14:26:00.717050 VrefDac_Margin_A0==25
586 14:26:00.721643 DeviceVref_Margin_A0==40
587 14:26:00.722093 VrefDac_Margin_A1==25
588 14:26:00.727217 DeviceVref_Margin_A1==40
589 14:26:00.727713
590 14:26:00.728174
591 14:26:00.728586 channel==1
592 14:26:00.728976 RxClkDly_Margin_A0==98 ps 10
593 14:26:00.730522 TxDqDly_Margin_A0==88 ps 9
594 14:26:00.736145 RxClkDly_Margin_A1==88 ps 9
595 14:26:00.736520 TxDqDly_Margin_A1==88 ps 9
596 14:26:00.736732 TrainedVREFDQ_A0==77
597 14:26:00.741632 TrainedVREFDQ_A1==77
598 14:26:00.742138 VrefDac_Margin_A0==23
599 14:26:00.747232 DeviceVref_Margin_A0==37
600 14:26:00.747710 VrefDac_Margin_A1==24
601 14:26:00.748143 DeviceVref_Margin_A1==37
602 14:26:00.748532
603 14:26:00.752911 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 14:26:00.753387
605 14:26:00.786597 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
606 14:26:00.787226 2D training succeed
607 14:26:00.792265 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 14:26:00.797842 auto size-- 65535DDR cs0 size: 2048MB
609 14:26:00.798319 DDR cs1 size: 2048MB
610 14:26:00.803441 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 14:26:00.803922 cs0 DataBus test pass
612 14:26:00.804366 cs1 DataBus test pass
613 14:26:00.809050 cs0 AddrBus test pass
614 14:26:00.809512 cs1 AddrBus test pass
615 14:26:00.809911
616 14:26:00.814684 100bdlr_step_size ps== 420
617 14:26:00.815143 result report
618 14:26:00.815545 boot times 0Enable ddr reg access
619 14:26:00.823532 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 14:26:00.836972 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 14:26:01.409929 0.0;M3 CHK:0;cm4_sp_mode 0
622 14:26:01.410563 MVN_1=0x00000000
623 14:26:01.415356 MVN_2=0x00000000
624 14:26:01.421207 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 14:26:01.421686 OPS=0x10
626 14:26:01.422086 ring efuse init
627 14:26:01.422476 chipver efuse init
628 14:26:01.429422 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 14:26:01.430053 [0.018961 Inits done]
630 14:26:01.436050 secure task start!
631 14:26:01.436529 high task start!
632 14:26:01.436936 low task start!
633 14:26:01.437334 run into bl31
634 14:26:01.443551 NOTICE: BL31: v1.3(release):4fc40b1
635 14:26:01.450471 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 14:26:01.450953 NOTICE: BL31: G12A normal boot!
637 14:26:01.477317 NOTICE: BL31: BL33 decompress pass
638 14:26:01.481993 ERROR: Error initializing runtime service opteed_fast
639 14:26:02.715976
640 14:26:02.716428
641 14:26:02.723355 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 14:26:02.723659
643 14:26:02.723894 Model: Libre Computer AML-A311D-CC Alta
644 14:26:02.931768 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 14:26:02.955155 DRAM: 2 GiB (effective 3.8 GiB)
646 14:26:03.099076 Core: 408 devices, 31 uclasses, devicetree: separate
647 14:26:03.104091 WDT: Not starting watchdog@f0d0
648 14:26:03.137221 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 14:26:03.149681 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 14:26:03.153741 ** Bad device specification mmc 0 **
651 14:26:03.165007 Card did not respond to voltage select! : -110
652 14:26:03.171713 ** Bad device specification mmc 0 **
653 14:26:03.172256 Couldn't find partition mmc 0
654 14:26:03.180990 Card did not respond to voltage select! : -110
655 14:26:03.186523 ** Bad device specification mmc 0 **
656 14:26:03.186959 Couldn't find partition mmc 0
657 14:26:03.190572 Error: could not access storage.
658 14:26:03.533078 Net: eth0: ethernet@ff3f0000
659 14:26:03.533683 starting USB...
660 14:26:03.785864 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 14:26:03.786520 Starting the controller
662 14:26:03.791899 USB XHCI 1.10
663 14:26:05.507460 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 14:26:05.508152 bl2_stage_init 0x01
665 14:26:05.508633 bl2_stage_init 0x81
666 14:26:05.513119 hw id: 0x0000 - pwm id 0x01
667 14:26:05.513636 bl2_stage_init 0xc1
668 14:26:05.514097 bl2_stage_init 0x02
669 14:26:05.514546
670 14:26:05.518525 L0:00000000
671 14:26:05.519051 L1:20000703
672 14:26:05.519517 L2:00008067
673 14:26:05.519966 L3:14000000
674 14:26:05.524156 B2:00402000
675 14:26:05.524674 B1:e0f83180
676 14:26:05.525127
677 14:26:05.525572 TE: 58159
678 14:26:05.526013
679 14:26:05.529829 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 14:26:05.530345
681 14:26:05.530813 Board ID = 1
682 14:26:05.535350 Set A53 clk to 24M
683 14:26:05.535853 Set A73 clk to 24M
684 14:26:05.536346 Set clk81 to 24M
685 14:26:05.540987 A53 clk: 1200 MHz
686 14:26:05.541506 A73 clk: 1200 MHz
687 14:26:05.541959 CLK81: 166.6M
688 14:26:05.542402 smccc: 00012ab5
689 14:26:05.546519 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 14:26:05.552114 board id: 1
691 14:26:05.557090 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 14:26:05.568646 fw parse done
693 14:26:05.573807 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 14:26:05.616308 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 14:26:05.628124 PIEI prepare done
696 14:26:05.628682 fastboot data load
697 14:26:05.629164 fastboot data verify
698 14:26:05.634003 verify result: 266
699 14:26:05.639425 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 14:26:05.639947 LPDDR4 probe
701 14:26:05.640453 ddr clk to 1584MHz
702 14:26:05.646489 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 14:26:05.683795
704 14:26:05.684351 dmc_version 0001
705 14:26:05.690438 Check phy result
706 14:26:05.697195 INFO : End of CA training
707 14:26:05.697713 INFO : End of initialization
708 14:26:05.702942 INFO : Training has run successfully!
709 14:26:05.703440 Check phy result
710 14:26:05.708461 INFO : End of initialization
711 14:26:05.708961 INFO : End of read enable training
712 14:26:05.711697 INFO : End of fine write leveling
713 14:26:05.717307 INFO : End of Write leveling coarse delay
714 14:26:05.723082 INFO : Training has run successfully!
715 14:26:05.723584 Check phy result
716 14:26:05.724051 INFO : End of initialization
717 14:26:05.728498 INFO : End of read dq deskew training
718 14:26:05.731794 INFO : End of MPR read delay center optimization
719 14:26:05.737478 INFO : End of write delay center optimization
720 14:26:05.743086 INFO : End of read delay center optimization
721 14:26:05.743582 INFO : End of max read latency training
722 14:26:05.748573 INFO : Training has run successfully!
723 14:26:05.749074 1D training succeed
724 14:26:05.755807 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 14:26:05.803420 Check phy result
726 14:26:05.804296 INFO : End of initialization
727 14:26:05.825231 INFO : End of 2D read delay Voltage center optimization
728 14:26:05.845287 INFO : End of 2D read delay Voltage center optimization
729 14:26:05.897106 INFO : End of 2D write delay Voltage center optimization
730 14:26:05.947415 INFO : End of 2D write delay Voltage center optimization
731 14:26:05.952775 INFO : Training has run successfully!
732 14:26:05.953299
733 14:26:05.953739 channel==0
734 14:26:05.958484 RxClkDly_Margin_A0==88 ps 9
735 14:26:05.959021 TxDqDly_Margin_A0==98 ps 10
736 14:26:05.964116 RxClkDly_Margin_A1==88 ps 9
737 14:26:05.964645 TxDqDly_Margin_A1==98 ps 10
738 14:26:05.965121 TrainedVREFDQ_A0==74
739 14:26:05.969756 TrainedVREFDQ_A1==74
740 14:26:05.970619 VrefDac_Margin_A0==25
741 14:26:05.971286 DeviceVref_Margin_A0==40
742 14:26:05.975319 VrefDac_Margin_A1==25
743 14:26:05.976098 DeviceVref_Margin_A1==40
744 14:26:05.976760
745 14:26:05.977471
746 14:26:05.980889 channel==1
747 14:26:05.981635 RxClkDly_Margin_A0==98 ps 10
748 14:26:05.982293 TxDqDly_Margin_A0==98 ps 10
749 14:26:05.986558 RxClkDly_Margin_A1==98 ps 10
750 14:26:05.987101 TxDqDly_Margin_A1==88 ps 9
751 14:26:05.992055 TrainedVREFDQ_A0==77
752 14:26:05.992583 TrainedVREFDQ_A1==77
753 14:26:05.993059 VrefDac_Margin_A0==22
754 14:26:05.997652 DeviceVref_Margin_A0==37
755 14:26:05.998174 VrefDac_Margin_A1==22
756 14:26:06.003264 DeviceVref_Margin_A1==37
757 14:26:06.004094
758 14:26:06.004784 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 14:26:06.008894
760 14:26:06.036937 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000018 dram_vref_reg_value 0x 0000005f
761 14:26:06.037800 2D training succeed
762 14:26:06.042477 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 14:26:06.048155 auto size-- 65535DDR cs0 size: 2048MB
764 14:26:06.048904 DDR cs1 size: 2048MB
765 14:26:06.053723 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 14:26:06.054465 cs0 DataBus test pass
767 14:26:06.059358 cs1 DataBus test pass
768 14:26:06.060150 cs0 AddrBus test pass
769 14:26:06.060854 cs1 AddrBus test pass
770 14:26:06.061499
771 14:26:06.064883 100bdlr_step_size ps== 420
772 14:26:06.065635 result report
773 14:26:06.070465 boot times 0Enable ddr reg access
774 14:26:06.074952 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 14:26:06.088376 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 14:26:06.661276 0.0;M3 CHK:0;cm4_sp_mode 0
777 14:26:06.662054 MVN_1=0x00000000
778 14:26:06.666871 MVN_2=0x00000000
779 14:26:06.672633 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 14:26:06.673305 OPS=0x10
781 14:26:06.674181 ring efuse init
782 14:26:06.674715 chipver efuse init
783 14:26:06.680655 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 14:26:06.681328 [0.018961 Inits done]
785 14:26:06.687322 secure task start!
786 14:26:06.687925 high task start!
787 14:26:06.688506 low task start!
788 14:26:06.689066 run into bl31
789 14:26:06.694920 NOTICE: BL31: v1.3(release):4fc40b1
790 14:26:06.701875 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 14:26:06.702469 NOTICE: BL31: G12A normal boot!
792 14:26:06.728679 NOTICE: BL31: BL33 decompress pass
793 14:26:06.733384 ERROR: Error initializing runtime service opteed_fast
794 14:26:07.967389
795 14:26:07.968168
796 14:26:07.974694 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 14:26:07.975239
798 14:26:07.975684 Model: Libre Computer AML-A311D-CC Alta
799 14:26:08.183151 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 14:26:08.206407 DRAM: 2 GiB (effective 3.8 GiB)
801 14:26:08.350439 Core: 408 devices, 31 uclasses, devicetree: separate
802 14:26:08.355429 WDT: Not starting watchdog@f0d0
803 14:26:08.388647 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 14:26:08.401069 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 14:26:08.405119 ** Bad device specification mmc 0 **
806 14:26:08.416388 Card did not respond to voltage select! : -110
807 14:26:08.422999 ** Bad device specification mmc 0 **
808 14:26:08.423581 Couldn't find partition mmc 0
809 14:26:08.432325 Card did not respond to voltage select! : -110
810 14:26:08.437837 ** Bad device specification mmc 0 **
811 14:26:08.438421 Couldn't find partition mmc 0
812 14:26:08.441942 Error: could not access storage.
813 14:26:08.785434 Net: eth0: ethernet@ff3f0000
814 14:26:08.786061 starting USB...
815 14:26:09.038213 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 14:26:09.038832 Starting the controller
817 14:26:09.044192 USB XHCI 1.10
818 14:26:11.207491 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 14:26:11.208238 bl2_stage_init 0x01
820 14:26:11.208710 bl2_stage_init 0x81
821 14:26:11.213076 hw id: 0x0000 - pwm id 0x01
822 14:26:11.213592 bl2_stage_init 0xc1
823 14:26:11.214026 bl2_stage_init 0x02
824 14:26:11.214455
825 14:26:11.218632 L0:00000000
826 14:26:11.219108 L1:20000703
827 14:26:11.219536 L2:00008067
828 14:26:11.219959 L3:14000000
829 14:26:11.221583 B2:00402000
830 14:26:11.222075 B1:e0f83180
831 14:26:11.222507
832 14:26:11.222935 TE: 58124
833 14:26:11.223364
834 14:26:11.232657 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 14:26:11.233165
836 14:26:11.233602 Board ID = 1
837 14:26:11.234030 Set A53 clk to 24M
838 14:26:11.234456 Set A73 clk to 24M
839 14:26:11.238320 Set clk81 to 24M
840 14:26:11.238775 A53 clk: 1200 MHz
841 14:26:11.239204 A73 clk: 1200 MHz
842 14:26:11.243832 CLK81: 166.6M
843 14:26:11.244349 smccc: 00012a92
844 14:26:11.249514 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 14:26:11.249985 board id: 1
846 14:26:11.257144 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 14:26:11.268735 fw parse done
848 14:26:11.273761 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 14:26:11.316449 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 14:26:11.328368 PIEI prepare done
851 14:26:11.328893 fastboot data load
852 14:26:11.329332 fastboot data verify
853 14:26:11.334046 verify result: 266
854 14:26:11.339536 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 14:26:11.340099 LPDDR4 probe
856 14:26:11.340536 ddr clk to 1584MHz
857 14:26:11.346701 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 14:26:11.383820
859 14:26:11.384406 dmc_version 0001
860 14:26:11.390543 Check phy result
861 14:26:11.397280 INFO : End of CA training
862 14:26:11.397754 INFO : End of initialization
863 14:26:11.402893 INFO : Training has run successfully!
864 14:26:11.403363 Check phy result
865 14:26:11.408496 INFO : End of initialization
866 14:26:11.408968 INFO : End of read enable training
867 14:26:11.414042 INFO : End of fine write leveling
868 14:26:11.419740 INFO : End of Write leveling coarse delay
869 14:26:11.420346 INFO : Training has run successfully!
870 14:26:11.420788 Check phy result
871 14:26:11.425333 INFO : End of initialization
872 14:26:11.425804 INFO : End of read dq deskew training
873 14:26:11.430996 INFO : End of MPR read delay center optimization
874 14:26:11.436503 INFO : End of write delay center optimization
875 14:26:11.442047 INFO : End of read delay center optimization
876 14:26:11.442526 INFO : End of max read latency training
877 14:26:11.447712 INFO : Training has run successfully!
878 14:26:11.448222 1D training succeed
879 14:26:11.455910 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 14:26:11.503510 Check phy result
881 14:26:11.504079 INFO : End of initialization
882 14:26:11.526098 INFO : End of 2D read delay Voltage center optimization
883 14:26:11.546371 INFO : End of 2D read delay Voltage center optimization
884 14:26:11.598463 INFO : End of 2D write delay Voltage center optimization
885 14:26:11.648696 INFO : End of 2D write delay Voltage center optimization
886 14:26:11.654319 INFO : Training has run successfully!
887 14:26:11.654828
888 14:26:11.655266 channel==0
889 14:26:11.659842 RxClkDly_Margin_A0==88 ps 9
890 14:26:11.660351 TxDqDly_Margin_A0==98 ps 10
891 14:26:11.663173 RxClkDly_Margin_A1==88 ps 9
892 14:26:11.663632 TxDqDly_Margin_A1==98 ps 10
893 14:26:11.668818 TrainedVREFDQ_A0==74
894 14:26:11.669275 TrainedVREFDQ_A1==74
895 14:26:11.669702 VrefDac_Margin_A0==24
896 14:26:11.674490 DeviceVref_Margin_A0==40
897 14:26:11.674950 VrefDac_Margin_A1==24
898 14:26:11.680048 DeviceVref_Margin_A1==40
899 14:26:11.680621
900 14:26:11.681070
901 14:26:11.681506 channel==1
902 14:26:11.681935 RxClkDly_Margin_A0==98 ps 10
903 14:26:11.683429 TxDqDly_Margin_A0==88 ps 9
904 14:26:11.688911 RxClkDly_Margin_A1==88 ps 9
905 14:26:11.689424 TxDqDly_Margin_A1==88 ps 9
906 14:26:11.689860 TrainedVREFDQ_A0==77
907 14:26:11.694521 TrainedVREFDQ_A1==77
908 14:26:11.695032 VrefDac_Margin_A0==22
909 14:26:11.700108 DeviceVref_Margin_A0==37
910 14:26:11.700611 VrefDac_Margin_A1==24
911 14:26:11.701037 DeviceVref_Margin_A1==37
912 14:26:11.701460
913 14:26:11.705747 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 14:26:11.706255
915 14:26:11.739346 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
916 14:26:11.739905 2D training succeed
917 14:26:11.744979 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 14:26:11.750524 auto size-- 65535DDR cs0 size: 2048MB
919 14:26:11.751037 DDR cs1 size: 2048MB
920 14:26:11.756125 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 14:26:11.756648 cs0 DataBus test pass
922 14:26:11.757077 cs1 DataBus test pass
923 14:26:11.761788 cs0 AddrBus test pass
924 14:26:11.762298 cs1 AddrBus test pass
925 14:26:11.762729
926 14:26:11.767339 100bdlr_step_size ps== 420
927 14:26:11.767868 result report
928 14:26:11.768356 boot times 0Enable ddr reg access
929 14:26:11.776259 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 14:26:11.789758 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 14:26:12.364199 0.0;M3 CHK:0;cm4_sp_mode 0
932 14:26:12.364795 MVN_1=0x00000000
933 14:26:12.369776 MVN_2=0x00000000
934 14:26:12.375463 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 14:26:12.375947 OPS=0x10
936 14:26:12.376415 ring efuse init
937 14:26:12.376825 chipver efuse init
938 14:26:12.381108 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 14:26:12.386714 [0.018961 Inits done]
940 14:26:12.387174 secure task start!
941 14:26:12.387585 high task start!
942 14:26:12.390300 low task start!
943 14:26:12.390754 run into bl31
944 14:26:12.397881 NOTICE: BL31: v1.3(release):4fc40b1
945 14:26:12.404760 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 14:26:12.405231 NOTICE: BL31: G12A normal boot!
947 14:26:12.431038 NOTICE: BL31: BL33 decompress pass
948 14:26:12.435760 ERROR: Error initializing runtime service opteed_fast
949 14:26:13.669574
950 14:26:13.670151
951 14:26:13.677037 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 14:26:13.677509
953 14:26:13.677926 Model: Libre Computer AML-A311D-CC Alta
954 14:26:13.885468 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 14:26:13.908820 DRAM: 2 GiB (effective 3.8 GiB)
956 14:26:14.052798 Core: 408 devices, 31 uclasses, devicetree: separate
957 14:26:14.057778 WDT: Not starting watchdog@f0d0
958 14:26:14.090848 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 14:26:14.103359 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 14:26:14.107380 ** Bad device specification mmc 0 **
961 14:26:14.118713 Card did not respond to voltage select! : -110
962 14:26:14.125387 ** Bad device specification mmc 0 **
963 14:26:14.125854 Couldn't find partition mmc 0
964 14:26:14.134745 Card did not respond to voltage select! : -110
965 14:26:14.140184 ** Bad device specification mmc 0 **
966 14:26:14.140641 Couldn't find partition mmc 0
967 14:26:14.144308 Error: could not access storage.
968 14:26:14.486806 Net: eth0: ethernet@ff3f0000
969 14:26:14.487346 starting USB...
970 14:26:14.739491 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 14:26:14.740040 Starting the controller
972 14:26:14.745505 USB XHCI 1.10
973 14:26:16.300649 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
974 14:26:16.307955 scanning usb for storage devices... 0 Storage Device(s) found
976 14:26:16.359577 Hit any key to stop autoboot: 1
977 14:26:16.360424 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
978 14:26:16.361045 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
979 14:26:16.361529 Setting prompt string to ['=>']
980 14:26:16.362001 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
981 14:26:16.365460 0
982 14:26:16.366342 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
983 14:26:16.366858 Sending with 10 millisecond of delay
985 14:26:17.502327 => setenv autoload no
986 14:26:17.513117 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
987 14:26:17.518033 setenv autoload no
988 14:26:17.518757 Sending with 10 millisecond of delay
990 14:26:19.315170 => setenv initrd_high 0xffffffff
991 14:26:19.325915 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
992 14:26:19.326727 setenv initrd_high 0xffffffff
993 14:26:19.327431 Sending with 10 millisecond of delay
995 14:26:20.943428 => setenv fdt_high 0xffffffff
996 14:26:20.954196 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
997 14:26:20.954995 setenv fdt_high 0xffffffff
998 14:26:20.955695 Sending with 10 millisecond of delay
1000 14:26:21.247514 => dhcp
1001 14:26:21.258275 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1002 14:26:21.259063 dhcp
1003 14:26:21.259488 Speed: 1000, full duplex
1004 14:26:21.259896 BOOTP broadcast 1
1005 14:26:21.505159 BOOTP broadcast 2
1006 14:26:21.536506 DHCP client bound to address 192.168.6.33 (279 ms)
1007 14:26:21.537226 Sending with 10 millisecond of delay
1009 14:26:23.214157 => setenv serverip 192.168.6.2
1010 14:26:23.225269 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1011 14:26:23.225838 setenv serverip 192.168.6.2
1012 14:26:23.226328 Sending with 10 millisecond of delay
1014 14:26:26.950477 => tftpboot 0x01080000 745056/tftp-deploy-uwaxng3u/kernel/uImage
1015 14:26:26.961253 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1016 14:26:26.961828 tftpboot 0x01080000 745056/tftp-deploy-uwaxng3u/kernel/uImage
1017 14:26:26.962105 Speed: 1000, full duplex
1018 14:26:26.962340 Using ethernet@ff3f0000 device
1019 14:26:26.963579 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1020 14:26:26.969072 Filename '745056/tftp-deploy-uwaxng3u/kernel/uImage'.
1021 14:26:26.972895 Load address: 0x1080000
1022 14:26:30.840761 Loading: *################################################## 43.4 MiB
1023 14:26:30.841420 11.2 MiB/s
1024 14:26:30.841892 done
1025 14:26:30.845068 Bytes transferred = 45482560 (2b60240 hex)
1026 14:26:30.845930 Sending with 10 millisecond of delay
1028 14:26:35.537777 => tftpboot 0x08000000 745056/tftp-deploy-uwaxng3u/ramdisk/ramdisk.cpio.gz.uboot
1029 14:26:35.548680 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
1030 14:26:35.549556 tftpboot 0x08000000 745056/tftp-deploy-uwaxng3u/ramdisk/ramdisk.cpio.gz.uboot
1031 14:26:35.550026 Speed: 1000, full duplex
1032 14:26:35.550466 Using ethernet@ff3f0000 device
1033 14:26:35.551527 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1034 14:26:35.563143 Filename '745056/tftp-deploy-uwaxng3u/ramdisk/ramdisk.cpio.gz.uboot'.
1035 14:26:35.563764 Load address: 0x8000000
1036 14:26:37.745821 Loading: *################################################# UDP wrong checksum 00000005 00003d17
1037 14:26:42.747757 T UDP wrong checksum 00000005 00003d17
1038 14:26:52.749752 T T UDP wrong checksum 00000005 00003d17
1039 14:26:53.383457 UDP wrong checksum 000000ff 00004b90
1040 14:26:53.409720 UDP wrong checksum 000000ff 0000e082
1041 14:27:04.920364 T T UDP wrong checksum 000000ff 0000eecd
1042 14:27:04.940263 UDP wrong checksum 000000ff 000072c0
1043 14:27:05.531001 UDP wrong checksum 000000ff 0000bf92
1044 14:27:05.561469 UDP wrong checksum 000000ff 00005785
1045 14:27:10.410116 T UDP wrong checksum 000000ff 00002797
1046 14:27:10.466391 UDP wrong checksum 000000ff 0000c189
1047 14:27:12.752980 UDP wrong checksum 00000005 00003d17
1048 14:27:32.759975 T T T T
1049 14:27:32.760679 Retry count exceeded; starting again
1051 14:27:32.762253 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1054 14:27:32.763283 end: 2.4 uboot-commands (duration 00:01:48) [common]
1056 14:27:32.764111 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1058 14:27:32.764735 end: 2 uboot-action (duration 00:01:48) [common]
1060 14:27:32.765636 Cleaning after the job
1061 14:27:32.765991 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/ramdisk
1062 14:27:32.766834 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/kernel
1063 14:27:32.793710 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/dtb
1064 14:27:32.794562 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/nfsrootfs
1065 14:27:32.962217 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745056/tftp-deploy-uwaxng3u/modules
1066 14:27:32.984480 start: 4.1 power-off (timeout 00:00:30) [common]
1067 14:27:32.985139 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1068 14:27:33.016290 >> OK - accepted request
1069 14:27:33.018308 Returned 0 in 0 seconds
1070 14:27:33.119332 end: 4.1 power-off (duration 00:00:00) [common]
1072 14:27:33.120495 start: 4.2 read-feedback (timeout 00:10:00) [common]
1073 14:27:33.121410 Listened to connection for namespace 'common' for up to 1s
1074 14:27:34.122141 Finalising connection for namespace 'common'
1075 14:27:34.122661 Disconnecting from shell: Finalise
1076 14:27:34.122976 =>
1077 14:27:34.223726 end: 4.2 read-feedback (duration 00:00:01) [common]
1078 14:27:34.224308 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/745056
1079 14:27:37.435046 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/745056
1080 14:27:37.435969 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.