Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 15:14:05.082216 lava-dispatcher, installed at version: 2024.01
2 15:14:05.082964 start: 0 validate
3 15:14:05.083416 Start time: 2024-09-19 15:14:05.083386+00:00 (UTC)
4 15:14:05.084005 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 15:14:05.084541 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 15:14:05.125609 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 15:14:05.126173 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 15:14:05.158821 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 15:14:05.159736 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 15:14:05.193559 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 15:14:05.194027 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 15:14:05.225415 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 15:14:05.225875 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-7262-g839c4f596f898%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 15:14:05.271275 validate duration: 0.19
16 15:14:05.272749 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 15:14:05.273352 start: 1.1 download-retry (timeout 00:10:00) [common]
18 15:14:05.273900 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 15:14:05.274871 Not decompressing ramdisk as can be used compressed.
20 15:14:05.275649 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 15:14:05.276146 saving as /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/ramdisk/initrd.cpio.gz
22 15:14:05.276424 total size: 5628140 (5 MB)
23 15:14:05.315400 progress 0 % (0 MB)
24 15:14:05.319698 progress 5 % (0 MB)
25 15:14:05.324068 progress 10 % (0 MB)
26 15:14:05.327824 progress 15 % (0 MB)
27 15:14:05.331922 progress 20 % (1 MB)
28 15:14:05.335640 progress 25 % (1 MB)
29 15:14:05.339802 progress 30 % (1 MB)
30 15:14:05.343912 progress 35 % (1 MB)
31 15:14:05.347530 progress 40 % (2 MB)
32 15:14:05.351579 progress 45 % (2 MB)
33 15:14:05.355269 progress 50 % (2 MB)
34 15:14:05.359322 progress 55 % (2 MB)
35 15:14:05.363435 progress 60 % (3 MB)
36 15:14:05.367262 progress 65 % (3 MB)
37 15:14:05.371348 progress 70 % (3 MB)
38 15:14:05.374997 progress 75 % (4 MB)
39 15:14:05.379021 progress 80 % (4 MB)
40 15:14:05.382625 progress 85 % (4 MB)
41 15:14:05.386660 progress 90 % (4 MB)
42 15:14:05.390560 progress 95 % (5 MB)
43 15:14:05.393850 progress 100 % (5 MB)
44 15:14:05.394492 5 MB downloaded in 0.12 s (45.47 MB/s)
45 15:14:05.395048 end: 1.1.1 http-download (duration 00:00:00) [common]
47 15:14:05.395948 end: 1.1 download-retry (duration 00:00:00) [common]
48 15:14:05.396279 start: 1.2 download-retry (timeout 00:10:00) [common]
49 15:14:05.396553 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 15:14:05.397035 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/kernel/Image
51 15:14:05.397286 saving as /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/kernel/Image
52 15:14:05.397497 total size: 45482496 (43 MB)
53 15:14:05.397707 No compression specified
54 15:14:05.437506 progress 0 % (0 MB)
55 15:14:05.465995 progress 5 % (2 MB)
56 15:14:05.493681 progress 10 % (4 MB)
57 15:14:05.521830 progress 15 % (6 MB)
58 15:14:05.549455 progress 20 % (8 MB)
59 15:14:05.578008 progress 25 % (10 MB)
60 15:14:05.605740 progress 30 % (13 MB)
61 15:14:05.633494 progress 35 % (15 MB)
62 15:14:05.661722 progress 40 % (17 MB)
63 15:14:05.689616 progress 45 % (19 MB)
64 15:14:05.717904 progress 50 % (21 MB)
65 15:14:05.745458 progress 55 % (23 MB)
66 15:14:05.773321 progress 60 % (26 MB)
67 15:14:05.801850 progress 65 % (28 MB)
68 15:14:05.829199 progress 70 % (30 MB)
69 15:14:05.857197 progress 75 % (32 MB)
70 15:14:05.885081 progress 80 % (34 MB)
71 15:14:05.912370 progress 85 % (36 MB)
72 15:14:05.940077 progress 90 % (39 MB)
73 15:14:05.967168 progress 95 % (41 MB)
74 15:14:05.994780 progress 100 % (43 MB)
75 15:14:05.995283 43 MB downloaded in 0.60 s (72.56 MB/s)
76 15:14:05.995761 end: 1.2.1 http-download (duration 00:00:01) [common]
78 15:14:05.996612 end: 1.2 download-retry (duration 00:00:01) [common]
79 15:14:05.996888 start: 1.3 download-retry (timeout 00:09:59) [common]
80 15:14:05.997150 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 15:14:05.997611 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 15:14:05.997886 saving as /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 15:14:05.998094 total size: 53209 (0 MB)
84 15:14:05.998301 No compression specified
85 15:14:06.041424 progress 61 % (0 MB)
86 15:14:06.042256 progress 100 % (0 MB)
87 15:14:06.042782 0 MB downloaded in 0.04 s (1.14 MB/s)
88 15:14:06.043260 end: 1.3.1 http-download (duration 00:00:00) [common]
90 15:14:06.044108 end: 1.3 download-retry (duration 00:00:00) [common]
91 15:14:06.044377 start: 1.4 download-retry (timeout 00:09:59) [common]
92 15:14:06.044642 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 15:14:06.045093 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 15:14:06.045336 saving as /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/nfsrootfs/full.rootfs.tar
95 15:14:06.045542 total size: 474398908 (452 MB)
96 15:14:06.045751 Using unxz to decompress xz
97 15:14:06.087541 progress 0 % (0 MB)
98 15:14:07.234510 progress 5 % (22 MB)
99 15:14:08.707532 progress 10 % (45 MB)
100 15:14:09.163481 progress 15 % (67 MB)
101 15:14:09.942884 progress 20 % (90 MB)
102 15:14:10.474827 progress 25 % (113 MB)
103 15:14:10.841424 progress 30 % (135 MB)
104 15:14:11.448574 progress 35 % (158 MB)
105 15:14:12.284930 progress 40 % (181 MB)
106 15:14:13.022825 progress 45 % (203 MB)
107 15:14:13.590681 progress 50 % (226 MB)
108 15:14:14.271048 progress 55 % (248 MB)
109 15:14:15.530699 progress 60 % (271 MB)
110 15:14:17.004125 progress 65 % (294 MB)
111 15:14:18.644045 progress 70 % (316 MB)
112 15:14:21.737483 progress 75 % (339 MB)
113 15:14:24.209343 progress 80 % (361 MB)
114 15:14:27.154922 progress 85 % (384 MB)
115 15:14:30.431606 progress 90 % (407 MB)
116 15:14:33.659641 progress 95 % (429 MB)
117 15:14:37.079356 progress 100 % (452 MB)
118 15:14:37.094667 452 MB downloaded in 31.05 s (14.57 MB/s)
119 15:14:37.095771 end: 1.4.1 http-download (duration 00:00:31) [common]
121 15:14:37.097748 end: 1.4 download-retry (duration 00:00:31) [common]
122 15:14:37.098390 start: 1.5 download-retry (timeout 00:09:28) [common]
123 15:14:37.099025 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 15:14:37.099941 downloading http://storage.kernelci.org/mainline/master/v6.11-7262-g839c4f596f898/arm64/defconfig/gcc-12/modules.tar.xz
125 15:14:37.100501 saving as /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/modules/modules.tar
126 15:14:37.100950 total size: 11582224 (11 MB)
127 15:14:37.101410 Using unxz to decompress xz
128 15:14:37.145883 progress 0 % (0 MB)
129 15:14:37.212115 progress 5 % (0 MB)
130 15:14:37.294318 progress 10 % (1 MB)
131 15:14:37.376775 progress 15 % (1 MB)
132 15:14:37.457123 progress 20 % (2 MB)
133 15:14:37.534099 progress 25 % (2 MB)
134 15:14:37.612206 progress 30 % (3 MB)
135 15:14:37.683596 progress 35 % (3 MB)
136 15:14:37.762685 progress 40 % (4 MB)
137 15:14:37.844023 progress 45 % (5 MB)
138 15:14:37.918027 progress 50 % (5 MB)
139 15:14:38.002008 progress 55 % (6 MB)
140 15:14:38.079556 progress 60 % (6 MB)
141 15:14:38.159191 progress 65 % (7 MB)
142 15:14:38.238640 progress 70 % (7 MB)
143 15:14:38.320850 progress 75 % (8 MB)
144 15:14:38.413468 progress 80 % (8 MB)
145 15:14:38.513237 progress 85 % (9 MB)
146 15:14:38.588423 progress 90 % (9 MB)
147 15:14:38.662599 progress 95 % (10 MB)
148 15:14:38.737603 progress 100 % (11 MB)
149 15:14:38.749865 11 MB downloaded in 1.65 s (6.70 MB/s)
150 15:14:38.750435 end: 1.5.1 http-download (duration 00:00:02) [common]
152 15:14:38.751235 end: 1.5 download-retry (duration 00:00:02) [common]
153 15:14:38.751496 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 15:14:38.751751 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 15:14:54.592284 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/745028/extract-nfsrootfs-y90_rf_7
156 15:14:54.592885 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 15:14:54.593174 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 15:14:54.593838 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5
159 15:14:54.594348 makedir: /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin
160 15:14:54.594695 makedir: /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/tests
161 15:14:54.595012 makedir: /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/results
162 15:14:54.595346 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-add-keys
163 15:14:54.595882 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-add-sources
164 15:14:54.596458 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-background-process-start
165 15:14:54.597013 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-background-process-stop
166 15:14:54.597541 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-common-functions
167 15:14:54.598034 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-echo-ipv4
168 15:14:54.598522 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-install-packages
169 15:14:54.599013 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-installed-packages
170 15:14:54.599539 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-os-build
171 15:14:54.600055 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-probe-channel
172 15:14:54.600569 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-probe-ip
173 15:14:54.601086 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-target-ip
174 15:14:54.601601 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-target-mac
175 15:14:54.602086 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-target-storage
176 15:14:54.602573 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-test-case
177 15:14:54.603057 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-test-event
178 15:14:54.603532 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-test-feedback
179 15:14:54.604036 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-test-raise
180 15:14:54.604543 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-test-reference
181 15:14:54.605029 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-test-runner
182 15:14:54.605513 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-test-set
183 15:14:54.605987 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-test-shell
184 15:14:54.606481 Updating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-install-packages (oe)
185 15:14:54.607028 Updating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/bin/lava-installed-packages (oe)
186 15:14:54.607507 Creating /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/environment
187 15:14:54.607895 LAVA metadata
188 15:14:54.608186 - LAVA_JOB_ID=745028
189 15:14:54.608402 - LAVA_DISPATCHER_IP=192.168.6.2
190 15:14:54.608775 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 15:14:54.609766 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 15:14:54.610086 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 15:14:54.610290 skipped lava-vland-overlay
194 15:14:54.610527 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 15:14:54.610796 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 15:14:54.610999 skipped lava-multinode-overlay
197 15:14:54.611232 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 15:14:54.611477 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 15:14:54.611723 Loading test definitions
200 15:14:54.612017 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 15:14:54.612250 Using /lava-745028 at stage 0
202 15:14:54.613438 uuid=745028_1.6.2.4.1 testdef=None
203 15:14:54.613753 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 15:14:54.614014 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 15:14:54.615747 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 15:14:54.616565 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 15:14:54.618765 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 15:14:54.619590 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 15:14:54.621724 runner path: /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 745028_1.6.2.4.1
212 15:14:54.622380 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 15:14:54.623143 Creating lava-test-runner.conf files
215 15:14:54.623342 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/745028/lava-overlay-top8jkv5/lava-745028/0 for stage 0
216 15:14:54.623693 - 0_v4l2-decoder-conformance-h265
217 15:14:54.624085 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 15:14:54.624376 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 15:14:54.646405 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 15:14:54.646834 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 15:14:54.647093 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 15:14:54.647357 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 15:14:54.647616 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 15:14:55.295075 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 15:14:55.295537 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 15:14:55.295792 extracting modules file /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/745028/extract-nfsrootfs-y90_rf_7
227 15:14:56.885659 extracting modules file /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/745028/extract-overlay-ramdisk-2ons3iie/ramdisk
228 15:14:58.300774 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 15:14:58.301239 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 15:14:58.301490 [common] Applying overlay to NFS
231 15:14:58.301698 [common] Applying overlay /var/lib/lava/dispatcher/tmp/745028/compress-overlay-pi1ou4p8/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/745028/extract-nfsrootfs-y90_rf_7
232 15:14:58.331021 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 15:14:58.331449 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 15:14:58.331718 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 15:14:58.331950 Converting downloaded kernel to a uImage
236 15:14:58.332297 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/kernel/Image /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/kernel/uImage
237 15:14:58.788720 output: Image Name:
238 15:14:58.789142 output: Created: Thu Sep 19 15:14:58 2024
239 15:14:58.789353 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 15:14:58.789555 output: Data Size: 45482496 Bytes = 44416.50 KiB = 43.38 MiB
241 15:14:58.789755 output: Load Address: 01080000
242 15:14:58.789953 output: Entry Point: 01080000
243 15:14:58.790148 output:
244 15:14:58.790480 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 15:14:58.790743 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 15:14:58.791007 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 15:14:58.791253 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 15:14:58.791505 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 15:14:58.791733 Building ramdisk /var/lib/lava/dispatcher/tmp/745028/extract-overlay-ramdisk-2ons3iie/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/745028/extract-overlay-ramdisk-2ons3iie/ramdisk
250 15:15:01.122663 >> 166205 blocks
251 15:15:08.868456 Adding RAMdisk u-boot header.
252 15:15:08.868930 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/745028/extract-overlay-ramdisk-2ons3iie/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/745028/extract-overlay-ramdisk-2ons3iie/ramdisk.cpio.gz.uboot
253 15:15:09.135039 output: Image Name:
254 15:15:09.135440 output: Created: Thu Sep 19 15:15:08 2024
255 15:15:09.135653 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 15:15:09.135856 output: Data Size: 23391293 Bytes = 22843.06 KiB = 22.31 MiB
257 15:15:09.136153 output: Load Address: 00000000
258 15:15:09.136593 output: Entry Point: 00000000
259 15:15:09.137029 output:
260 15:15:09.138185 rename /var/lib/lava/dispatcher/tmp/745028/extract-overlay-ramdisk-2ons3iie/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/ramdisk/ramdisk.cpio.gz.uboot
261 15:15:09.138952 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 15:15:09.139538 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 15:15:09.140139 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 15:15:09.140647 No LXC device requested
265 15:15:09.141190 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 15:15:09.141738 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 15:15:09.142317 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 15:15:09.142807 Checking files for TFTP limit of 4294967296 bytes.
269 15:15:09.145785 end: 1 tftp-deploy (duration 00:01:04) [common]
270 15:15:09.146424 start: 2 uboot-action (timeout 00:05:00) [common]
271 15:15:09.146985 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 15:15:09.147522 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 15:15:09.148085 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 15:15:09.148623 Using kernel file from prepare-kernel: 745028/tftp-deploy-qdv8p6a_/kernel/uImage
275 15:15:09.149288 substitutions:
276 15:15:09.149721 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 15:15:09.150153 - {DTB_ADDR}: 0x01070000
278 15:15:09.150584 - {DTB}: 745028/tftp-deploy-qdv8p6a_/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 15:15:09.151013 - {INITRD}: 745028/tftp-deploy-qdv8p6a_/ramdisk/ramdisk.cpio.gz.uboot
280 15:15:09.151441 - {KERNEL_ADDR}: 0x01080000
281 15:15:09.151866 - {KERNEL}: 745028/tftp-deploy-qdv8p6a_/kernel/uImage
282 15:15:09.152328 - {LAVA_MAC}: None
283 15:15:09.152775 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/745028/extract-nfsrootfs-y90_rf_7
284 15:15:09.153200 - {NFS_SERVER_IP}: 192.168.6.2
285 15:15:09.153621 - {PRESEED_CONFIG}: None
286 15:15:09.154178 - {PRESEED_LOCAL}: None
287 15:15:09.154598 - {RAMDISK_ADDR}: 0x08000000
288 15:15:09.155016 - {RAMDISK}: 745028/tftp-deploy-qdv8p6a_/ramdisk/ramdisk.cpio.gz.uboot
289 15:15:09.155437 - {ROOT_PART}: None
290 15:15:09.155855 - {ROOT}: None
291 15:15:09.156328 - {SERVER_IP}: 192.168.6.2
292 15:15:09.156717 - {TEE_ADDR}: 0x83000000
293 15:15:09.157095 - {TEE}: None
294 15:15:09.157473 Parsed boot commands:
295 15:15:09.157841 - setenv autoload no
296 15:15:09.158215 - setenv initrd_high 0xffffffff
297 15:15:09.158589 - setenv fdt_high 0xffffffff
298 15:15:09.158962 - dhcp
299 15:15:09.159337 - setenv serverip 192.168.6.2
300 15:15:09.159711 - tftpboot 0x01080000 745028/tftp-deploy-qdv8p6a_/kernel/uImage
301 15:15:09.160118 - tftpboot 0x08000000 745028/tftp-deploy-qdv8p6a_/ramdisk/ramdisk.cpio.gz.uboot
302 15:15:09.160542 - tftpboot 0x01070000 745028/tftp-deploy-qdv8p6a_/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 15:15:09.160960 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/745028/extract-nfsrootfs-y90_rf_7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 15:15:09.161392 - bootm 0x01080000 0x08000000 0x01070000
305 15:15:09.161937 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 15:15:09.163543 start: 2.3 connect-device (timeout 00:05:00) [common]
308 15:15:09.164016 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 15:15:09.178281 Setting prompt string to ['lava-test: # ']
310 15:15:09.180850 end: 2.3 connect-device (duration 00:00:00) [common]
311 15:15:09.181607 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 15:15:09.182219 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 15:15:09.182790 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 15:15:09.184153 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 15:15:09.218987 >> OK - accepted request
316 15:15:09.221130 Returned 0 in 0 seconds
317 15:15:09.322309 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 15:15:09.323520 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 15:15:09.323920 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 15:15:09.324449 Setting prompt string to ['Hit any key to stop autoboot']
322 15:15:09.324784 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 15:15:09.326024 Trying 192.168.56.21...
324 15:15:09.326354 Connected to conserv1.
325 15:15:09.326618 Escape character is '^]'.
326 15:15:09.326875
327 15:15:09.327136 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 15:15:09.327377
329 15:15:16.659465 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 15:15:16.660178 bl2_stage_init 0x01
331 15:15:16.660638 bl2_stage_init 0x81
332 15:15:16.665143 hw id: 0x0000 - pwm id 0x01
333 15:15:16.665650 bl2_stage_init 0xc1
334 15:15:16.670653 bl2_stage_init 0x02
335 15:15:16.671146
336 15:15:16.671590 L0:00000000
337 15:15:16.672072 L1:00000703
338 15:15:16.672518 L2:00008067
339 15:15:16.672983 L3:15000000
340 15:15:16.676287 S1:00000000
341 15:15:16.676800 B2:20282000
342 15:15:16.677249 B1:a0f83180
343 15:15:16.677684
344 15:15:16.678116 TE: 70512
345 15:15:16.678548
346 15:15:16.681857 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 15:15:16.682340
348 15:15:16.687323 Board ID = 1
349 15:15:16.687792 Set cpu clk to 24M
350 15:15:16.688262 Set clk81 to 24M
351 15:15:16.693117 Use GP1_pll as DSU clk.
352 15:15:16.693599 DSU clk: 1200 Mhz
353 15:15:16.694032 CPU clk: 1200 MHz
354 15:15:16.698591 Set clk81 to 166.6M
355 15:15:16.704165 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 15:15:16.704646 board id: 1
357 15:15:16.711303 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 15:15:16.722057 fw parse done
359 15:15:16.728047 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 15:15:16.770650 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 15:15:16.781477 PIEI prepare done
362 15:15:16.781947 fastboot data load
363 15:15:16.782388 fastboot data verify
364 15:15:16.787154 verify result: 266
365 15:15:16.792726 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 15:15:16.793233 LPDDR4 probe
367 15:15:16.793669 ddr clk to 1584MHz
368 15:15:16.800731 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 15:15:16.838067
370 15:15:16.838541 dmc_version 0001
371 15:15:16.845270 Check phy result
372 15:15:16.850589 INFO : End of CA training
373 15:15:16.851054 INFO : End of initialization
374 15:15:16.856291 INFO : Training has run successfully!
375 15:15:16.856887 Check phy result
376 15:15:16.861862 INFO : End of initialization
377 15:15:16.862338 INFO : End of read enable training
378 15:15:16.867353 INFO : End of fine write leveling
379 15:15:16.872980 INFO : End of Write leveling coarse delay
380 15:15:16.873448 INFO : Training has run successfully!
381 15:15:16.873881 Check phy result
382 15:15:16.878588 INFO : End of initialization
383 15:15:16.879051 INFO : End of read dq deskew training
384 15:15:16.884140 INFO : End of MPR read delay center optimization
385 15:15:16.889724 INFO : End of write delay center optimization
386 15:15:16.895323 INFO : End of read delay center optimization
387 15:15:16.895787 INFO : End of max read latency training
388 15:15:16.900862 INFO : Training has run successfully!
389 15:15:16.901332 1D training succeed
390 15:15:16.910165 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 15:15:16.957715 Check phy result
392 15:15:16.958252 INFO : End of initialization
393 15:15:16.980035 INFO : End of 2D read delay Voltage center optimization
394 15:15:16.999218 INFO : End of 2D read delay Voltage center optimization
395 15:15:17.051381 INFO : End of 2D write delay Voltage center optimization
396 15:15:17.100416 INFO : End of 2D write delay Voltage center optimization
397 15:15:17.106053 INFO : Training has run successfully!
398 15:15:17.106546
399 15:15:17.106984 channel==0
400 15:15:17.111469 RxClkDly_Margin_A0==78 ps 8
401 15:15:17.111954 TxDqDly_Margin_A0==98 ps 10
402 15:15:17.117166 RxClkDly_Margin_A1==88 ps 9
403 15:15:17.117632 TxDqDly_Margin_A1==98 ps 10
404 15:15:17.118068 TrainedVREFDQ_A0==74
405 15:15:17.122731 TrainedVREFDQ_A1==74
406 15:15:17.123196 VrefDac_Margin_A0==23
407 15:15:17.123630 DeviceVref_Margin_A0==40
408 15:15:17.128286 VrefDac_Margin_A1==22
409 15:15:17.128580 DeviceVref_Margin_A1==40
410 15:15:17.128778
411 15:15:17.128974
412 15:15:17.133927 channel==1
413 15:15:17.134392 RxClkDly_Margin_A0==78 ps 8
414 15:15:17.134825 TxDqDly_Margin_A0==98 ps 10
415 15:15:17.139430 RxClkDly_Margin_A1==78 ps 8
416 15:15:17.139912 TxDqDly_Margin_A1==88 ps 9
417 15:15:17.145015 TrainedVREFDQ_A0==78
418 15:15:17.145476 TrainedVREFDQ_A1==75
419 15:15:17.145911 VrefDac_Margin_A0==23
420 15:15:17.150943 DeviceVref_Margin_A0==36
421 15:15:17.151417 VrefDac_Margin_A1==22
422 15:15:17.156251 DeviceVref_Margin_A1==39
423 15:15:17.156712
424 15:15:17.157148 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 15:15:17.157576
426 15:15:17.189868 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000015 00000018 00000014 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
427 15:15:17.190489 2D training succeed
428 15:15:17.195561 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 15:15:17.200999 auto size-- 65535DDR cs0 size: 2048MB
430 15:15:17.201467 DDR cs1 size: 2048MB
431 15:15:17.206594 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 15:15:17.207057 cs0 DataBus test pass
433 15:15:17.212242 cs1 DataBus test pass
434 15:15:17.212706 cs0 AddrBus test pass
435 15:15:17.213137 cs1 AddrBus test pass
436 15:15:17.213565
437 15:15:17.218135 100bdlr_step_size ps== 478
438 15:15:17.218619 result report
439 15:15:17.223514 boot times 0Enable ddr reg access
440 15:15:17.228447 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 15:15:17.242431 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 15:15:17.896093 bl2z: ptr: 05129330, size: 00001e40
443 15:15:17.902087 0.0;M3 CHK:0;cm4_sp_mode 0
444 15:15:17.902478 MVN_1=0x00000000
445 15:15:17.902722 MVN_2=0x00000000
446 15:15:17.913569 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 15:15:17.913972 OPS=0x04
448 15:15:17.914214 ring efuse init
449 15:15:17.919166 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 15:15:17.919528 [0.017310 Inits done]
451 15:15:17.919766 secure task start!
452 15:15:17.926719 high task start!
453 15:15:17.927094 low task start!
454 15:15:17.927333 run into bl31
455 15:15:17.935257 NOTICE: BL31: v1.3(release):4fc40b1
456 15:15:17.942790 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 15:15:17.943090 NOTICE: BL31: G12A normal boot!
458 15:15:17.958761 NOTICE: BL31: BL33 decompress pass
459 15:15:17.963380 ERROR: Error initializing runtime service opteed_fast
460 15:15:19.209845 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 15:15:19.210518 bl2_stage_init 0x01
462 15:15:19.211026 bl2_stage_init 0x81
463 15:15:19.215650 hw id: 0x0000 - pwm id 0x01
464 15:15:19.216179 bl2_stage_init 0xc1
465 15:15:19.221099 bl2_stage_init 0x02
466 15:15:19.221580
467 15:15:19.222053 L0:00000000
468 15:15:19.222511 L1:00000703
469 15:15:19.222972 L2:00008067
470 15:15:19.223422 L3:15000000
471 15:15:19.227159 S1:00000000
472 15:15:19.227649 B2:20282000
473 15:15:19.228176 B1:a0f83180
474 15:15:19.228625
475 15:15:19.229065 TE: 70855
476 15:15:19.229504
477 15:15:19.232212 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 15:15:19.232706
479 15:15:19.238451 Board ID = 1
480 15:15:19.238943 Set cpu clk to 24M
481 15:15:19.239389 Set clk81 to 24M
482 15:15:19.243373 Use GP1_pll as DSU clk.
483 15:15:19.243863 DSU clk: 1200 Mhz
484 15:15:19.244354 CPU clk: 1200 MHz
485 15:15:19.249265 Set clk81 to 166.6M
486 15:15:19.254539 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 15:15:19.255026 board id: 1
488 15:15:19.261759 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 15:15:19.272766 fw parse done
490 15:15:19.278613 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 15:15:19.320832 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 15:15:19.332881 PIEI prepare done
493 15:15:19.333389 fastboot data load
494 15:15:19.333865 fastboot data verify
495 15:15:19.338564 verify result: 266
496 15:15:19.344382 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 15:15:19.344961 LPDDR4 probe
498 15:15:19.345393 ddr clk to 1584MHz
499 15:15:20.711097 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
500 15:15:20.711544 bl2_stage_init 0x01
501 15:15:20.711765 bl2_stage_init 0x81
502 15:15:20.716533 hw id: 0x0000 - pwm id 0x01
503 15:15:20.716825 bl2_stage_init 0xc1
504 15:15:20.722230 bl2_stage_init 0x02
505 15:15:20.722533
506 15:15:20.722747 L0:00000000
507 15:15:20.722952 L1:00000703
508 15:15:20.723162 L2:00008067
509 15:15:20.723365 L3:15000000
510 15:15:20.727791 S1:00000000
511 15:15:20.728280 B2:20282000
512 15:15:20.728603 B1:a0f83180
513 15:15:20.728903
514 15:15:20.729203 TE: 71091
515 15:15:20.729500
516 15:15:20.733365 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
517 15:15:20.733672
518 15:15:20.738990 Board ID = 1
519 15:15:20.739394 Set cpu clk to 24M
520 15:15:20.739717 Set clk81 to 24M
521 15:15:20.744528 Use GP1_pll as DSU clk.
522 15:15:20.744830 DSU clk: 1200 Mhz
523 15:15:20.745037 CPU clk: 1200 MHz
524 15:15:20.750203 Set clk81 to 166.6M
525 15:15:20.755750 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
526 15:15:20.756192 board id: 1
527 15:15:20.762942 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
528 15:15:20.773687 fw parse done
529 15:15:20.778990 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
530 15:15:20.822357 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
531 15:15:20.833181 PIEI prepare done
532 15:15:20.833528 fastboot data load
533 15:15:20.833738 fastboot data verify
534 15:15:20.838738 verify result: 266
535 15:15:20.844354 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
536 15:15:20.844790 LPDDR4 probe
537 15:15:20.845104 ddr clk to 1584MHz
538 15:15:20.851499 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 15:15:20.888705
540 15:15:20.889085 dmc_version 0001
541 15:15:20.896233 Check phy result
542 15:15:20.902184 INFO : End of CA training
543 15:15:20.902485 INFO : End of initialization
544 15:15:20.907797 INFO : Training has run successfully!
545 15:15:20.908295 Check phy result
546 15:15:20.913341 INFO : End of initialization
547 15:15:20.913740 INFO : End of read enable training
548 15:15:20.918964 INFO : End of fine write leveling
549 15:15:20.924561 INFO : End of Write leveling coarse delay
550 15:15:20.924863 INFO : Training has run successfully!
551 15:15:20.925072 Check phy result
552 15:15:20.930191 INFO : End of initialization
553 15:15:20.930619 INFO : End of read dq deskew training
554 15:15:20.935739 INFO : End of MPR read delay center optimization
555 15:15:20.941322 INFO : End of write delay center optimization
556 15:15:20.946972 INFO : End of read delay center optimization
557 15:15:20.947311 INFO : End of max read latency training
558 15:15:20.952578 INFO : Training has run successfully!
559 15:15:20.952889 1D training succeed
560 15:15:20.961683 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
561 15:15:21.009521 Check phy result
562 15:15:21.009903 INFO : End of initialization
563 15:15:21.031409 INFO : End of 2D read delay Voltage center optimization
564 15:15:21.050939 INFO : End of 2D read delay Voltage center optimization
565 15:15:21.102478 INFO : End of 2D write delay Voltage center optimization
566 15:15:21.152031 INFO : End of 2D write delay Voltage center optimization
567 15:15:21.157476 INFO : Training has run successfully!
568 15:15:21.157763
569 15:15:21.157975 channel==0
570 15:15:21.163130 RxClkDly_Margin_A0==78 ps 8
571 15:15:21.163540 TxDqDly_Margin_A0==98 ps 10
572 15:15:21.168721 RxClkDly_Margin_A1==78 ps 8
573 15:15:21.169117 TxDqDly_Margin_A1==88 ps 9
574 15:15:21.169439 TrainedVREFDQ_A0==76
575 15:15:21.174388 TrainedVREFDQ_A1==75
576 15:15:21.174694 VrefDac_Margin_A0==24
577 15:15:21.174900 DeviceVref_Margin_A0==38
578 15:15:21.180104 VrefDac_Margin_A1==23
579 15:15:21.180384 DeviceVref_Margin_A1==39
580 15:15:21.180587
581 15:15:21.180791
582 15:15:21.180991 channel==1
583 15:15:21.185543 RxClkDly_Margin_A0==78 ps 8
584 15:15:21.185848 TxDqDly_Margin_A0==98 ps 10
585 15:15:21.191134 RxClkDly_Margin_A1==78 ps 8
586 15:15:21.191441 TxDqDly_Margin_A1==88 ps 9
587 15:15:21.196715 TrainedVREFDQ_A0==78
588 15:15:21.197137 TrainedVREFDQ_A1==77
589 15:15:21.197458 VrefDac_Margin_A0==22
590 15:15:21.202393 DeviceVref_Margin_A0==36
591 15:15:21.202690 VrefDac_Margin_A1==22
592 15:15:21.207875 DeviceVref_Margin_A1==37
593 15:15:21.208333
594 15:15:21.208663 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
595 15:15:21.208974
596 15:15:21.241478 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000014 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
597 15:15:21.241860 2D training succeed
598 15:15:21.247076 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
599 15:15:21.252719 auto size-- 65535DDR cs0 size: 2048MB
600 15:15:21.253175 DDR cs1 size: 2048MB
601 15:15:21.258359 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
602 15:15:21.258649 cs0 DataBus test pass
603 15:15:21.263898 cs1 DataBus test pass
604 15:15:21.264394 cs0 AddrBus test pass
605 15:15:21.264725 cs1 AddrBus test pass
606 15:15:21.265037
607 15:15:21.269495 100bdlr_step_size ps== 478
608 15:15:21.269777 result report
609 15:15:21.275080 boot times 0Enable ddr reg access
610 15:15:21.280132 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
611 15:15:21.293319 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
612 15:15:21.949919 bl2z: ptr: 05129330, size: 00001e40
613 15:15:21.955420 0.0;M3 CHK:0;cm4_sp_mode 0
614 15:15:21.955716 MVN_1=0x00000000
615 15:15:21.955924 MVN_2=0x00000000
616 15:15:21.961062 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
617 15:15:21.961379 OPS=0x04
618 15:15:21.966955 ring efuse init
619 15:15:21.972570 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
620 15:15:21.973015 [0.017319 Inits done]
621 15:15:21.973261 secure task start!
622 15:15:21.979306 high task start!
623 15:15:21.979622 low task start!
624 15:15:21.979828 run into bl31
625 15:15:21.987907 NOTICE: BL31: v1.3(release):4fc40b1
626 15:15:21.995305 NOTICE: BL31: Built : 15:57:33, May 22 2019
627 15:15:21.995738 NOTICE: BL31: G12A normal boot!
628 15:15:22.011306 NOTICE: BL31: BL33 decompress pass
629 15:15:22.016028 ERROR: Error initializing runtime service opteed_fast
630 15:15:23.259334 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
631 15:15:23.259763 bl2_stage_init 0x01
632 15:15:23.260012 bl2_stage_init 0x81
633 15:15:23.264833 hw id: 0x0000 - pwm id 0x01
634 15:15:23.265131 bl2_stage_init 0xc1
635 15:15:23.270541 bl2_stage_init 0x02
636 15:15:23.270949
637 15:15:23.271312 L0:00000000
638 15:15:23.271659 L1:00000703
639 15:15:23.271899 L2:00008067
640 15:15:23.272135 L3:15000000
641 15:15:23.272609 S1:00000000
642 15:15:23.277207 B2:20282000
643 15:15:23.277492 B1:a0f83180
644 15:15:23.277704
645 15:15:23.277909 TE: 70205
646 15:15:23.278109
647 15:15:23.282694 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
648 15:15:23.283113
649 15:15:23.283443 Board ID = 1
650 15:15:23.288196 Set cpu clk to 24M
651 15:15:23.288609 Set clk81 to 24M
652 15:15:23.288926 Use GP1_pll as DSU clk.
653 15:15:23.293983 DSU clk: 1200 Mhz
654 15:15:23.294401 CPU clk: 1200 MHz
655 15:15:23.294742 Set clk81 to 166.6M
656 15:15:23.305034 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
657 15:15:23.305363 board id: 1
658 15:15:23.310474 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
659 15:15:23.321982 fw parse done
660 15:15:23.327937 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
661 15:15:23.371208 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
662 15:15:23.382292 PIEI prepare done
663 15:15:23.382618 fastboot data load
664 15:15:23.382827 fastboot data verify
665 15:15:23.387822 verify result: 266
666 15:15:23.393454 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
667 15:15:23.393987 LPDDR4 probe
668 15:15:23.394448 ddr clk to 1584MHz
669 15:15:23.401018 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
670 15:15:23.439185
671 15:15:23.439703 dmc_version 0001
672 15:15:23.446205 Check phy result
673 15:15:23.452204 INFO : End of CA training
674 15:15:23.452713 INFO : End of initialization
675 15:15:23.457734 INFO : Training has run successfully!
676 15:15:23.458229 Check phy result
677 15:15:23.463326 INFO : End of initialization
678 15:15:23.463823 INFO : End of read enable training
679 15:15:23.466665 INFO : End of fine write leveling
680 15:15:23.472295 INFO : End of Write leveling coarse delay
681 15:15:23.477870 INFO : Training has run successfully!
682 15:15:23.478366 Check phy result
683 15:15:23.478823 INFO : End of initialization
684 15:15:23.483463 INFO : End of read dq deskew training
685 15:15:23.489078 INFO : End of MPR read delay center optimization
686 15:15:23.489582 INFO : End of write delay center optimization
687 15:15:23.494675 INFO : End of read delay center optimization
688 15:15:23.500271 INFO : End of max read latency training
689 15:15:23.500773 INFO : Training has run successfully!
690 15:15:23.505863 1D training succeed
691 15:15:23.510854 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
692 15:15:23.560113 Check phy result
693 15:15:23.560670 INFO : End of initialization
694 15:15:23.586590 INFO : End of 2D read delay Voltage center optimization
695 15:15:23.611599 INFO : End of 2D read delay Voltage center optimization
696 15:15:23.668343 INFO : End of 2D write delay Voltage center optimization
697 15:15:23.722337 INFO : End of 2D write delay Voltage center optimization
698 15:15:23.727821 INFO : Training has run successfully!
699 15:15:23.728370
700 15:15:23.728829 channel==0
701 15:15:23.733420 RxClkDly_Margin_A0==78 ps 8
702 15:15:23.733910 TxDqDly_Margin_A0==98 ps 10
703 15:15:23.739024 RxClkDly_Margin_A1==88 ps 9
704 15:15:23.739514 TxDqDly_Margin_A1==98 ps 10
705 15:15:23.739969 TrainedVREFDQ_A0==74
706 15:15:23.744751 TrainedVREFDQ_A1==74
707 15:15:23.745254 VrefDac_Margin_A0==24
708 15:15:23.745709 DeviceVref_Margin_A0==40
709 15:15:23.750264 VrefDac_Margin_A1==22
710 15:15:23.750753 DeviceVref_Margin_A1==40
711 15:15:23.751203
712 15:15:23.751647
713 15:15:23.755855 channel==1
714 15:15:23.756374 RxClkDly_Margin_A0==88 ps 9
715 15:15:23.756831 TxDqDly_Margin_A0==98 ps 10
716 15:15:23.761426 RxClkDly_Margin_A1==78 ps 8
717 15:15:23.761920 TxDqDly_Margin_A1==88 ps 9
718 15:15:23.767006 TrainedVREFDQ_A0==78
719 15:15:23.767506 TrainedVREFDQ_A1==77
720 15:15:23.767959 VrefDac_Margin_A0==22
721 15:15:23.772757 DeviceVref_Margin_A0==36
722 15:15:23.773252 VrefDac_Margin_A1==22
723 15:15:23.778230 DeviceVref_Margin_A1==37
724 15:15:23.778720
725 15:15:23.779175 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
726 15:15:23.779620
727 15:15:23.811849 soc_vref_reg_value 0x 00000019 00000018 00000017 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000019 00000015 00000017 00000015 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000062
728 15:15:23.812446 2D training succeed
729 15:15:23.817445 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
730 15:15:23.823026 auto size-- 65535DDR cs0 size: 2048MB
731 15:15:23.823522 DDR cs1 size: 2048MB
732 15:15:23.828699 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
733 15:15:23.829198 cs0 DataBus test pass
734 15:15:23.834210 cs1 DataBus test pass
735 15:15:23.834707 cs0 AddrBus test pass
736 15:15:23.835159 cs1 AddrBus test pass
737 15:15:23.835604
738 15:15:23.839823 100bdlr_step_size ps== 471
739 15:15:23.840356 result report
740 15:15:23.845465 boot times 0Enable ddr reg access
741 15:15:23.849898 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
742 15:15:23.864644 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
743 15:15:24.524048 bl2z: ptr: 05129330, size: 00001e40
744 15:15:24.532659 0.0;M3 CHK:0;cm4_sp_mode 0
745 15:15:24.533007 MVN_1=0x00000000
746 15:15:24.533226 MVN_2=0x00000000
747 15:15:24.544142 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
748 15:15:24.544487 OPS=0x04
749 15:15:24.544703 ring efuse init
750 15:15:24.549848 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
751 15:15:24.550156 [0.017355 Inits done]
752 15:15:24.550367 secure task start!
753 15:15:24.557292 high task start!
754 15:15:24.557633 low task start!
755 15:15:24.557850 run into bl31
756 15:15:24.566517 NOTICE: BL31: v1.3(release):4fc40b1
757 15:15:24.573683 NOTICE: BL31: Built : 15:57:33, May 22 2019
758 15:15:24.573990 NOTICE: BL31: G12A normal boot!
759 15:15:24.589267 NOTICE: BL31: BL33 decompress pass
760 15:15:24.594954 ERROR: Error initializing runtime service opteed_fast
761 15:15:25.390324
762 15:15:25.390729
763 15:15:25.395735 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
764 15:15:25.396186
765 15:15:25.399224 Model: Libre Computer AML-S905D3-CC Solitude
766 15:15:25.546243 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
767 15:15:25.561690 DRAM: 2 GiB (effective 3.8 GiB)
768 15:15:25.662820 Core: 406 devices, 33 uclasses, devicetree: separate
769 15:15:25.667611 WDT: Not starting watchdog@f0d0
770 15:15:25.693670 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
771 15:15:25.705883 Loading Environment from FAT... Card did not respond to voltage select! : -110
772 15:15:25.710924 ** Bad device specification mmc 0 **
773 15:15:25.720926 Card did not respond to voltage select! : -110
774 15:15:25.728540 ** Bad device specification mmc 0 **
775 15:15:25.729151 Couldn't find partition mmc 0
776 15:15:25.736881 Card did not respond to voltage select! : -110
777 15:15:25.742413 ** Bad device specification mmc 0 **
778 15:15:25.743016 Couldn't find partition mmc 0
779 15:15:25.747446 Error: could not access storage.
780 15:15:26.043875 Net: eth0: ethernet@ff3f0000
781 15:15:26.044337 starting USB...
782 15:15:26.288475 Bus usb@ff500000: Register 3000140 NbrPorts 3
783 15:15:26.289050 Starting the controller
784 15:15:26.295440 USB XHCI 1.10
785 15:15:27.849520 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
786 15:15:27.857874 scanning usb for storage devices... 0 Storage Device(s) found
788 15:15:27.908920 Hit any key to stop autoboot: 1
789 15:15:27.909679 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
790 15:15:27.910049 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
791 15:15:27.910401 Setting prompt string to ['=>']
792 15:15:27.910662 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
793 15:15:27.923893 0
794 15:15:27.924563 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
796 15:15:28.025344 => setenv autoload no
797 15:15:28.026034 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
798 15:15:28.030176 setenv autoload no
800 15:15:28.131205 => setenv initrd_high 0xffffffff
801 15:15:28.131857 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
802 15:15:28.136122 setenv initrd_high 0xffffffff
804 15:15:28.237171 => setenv fdt_high 0xffffffff
805 15:15:28.237832 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
806 15:15:28.242150 setenv fdt_high 0xffffffff
808 15:15:28.343187 => dhcp
809 15:15:28.343833 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
810 15:15:28.348132 dhcp
811 15:15:29.504157 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete... done
812 15:15:29.504561 Speed: 1000, full duplex
813 15:15:29.504781 BOOTP broadcast 1
814 15:15:29.890308 BOOTP broadcast 2
815 15:15:30.252807 BOOTP broadcast 3
816 15:15:31.253307 BOOTP broadcast 4
817 15:15:33.255458 BOOTP broadcast 5
818 15:15:33.275609 DHCP client bound to address 192.168.6.12 (3771 ms)
820 15:15:33.377247 => setenv serverip 192.168.6.2
821 15:15:33.378026 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
822 15:15:33.382802 setenv serverip 192.168.6.2
824 15:15:33.484390 => tftpboot 0x01080000 745028/tftp-deploy-qdv8p6a_/kernel/uImage
825 15:15:33.485164 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
826 15:15:33.492257 tftpboot 0x01080000 745028/tftp-deploy-qdv8p6a_/kernel/uImage
827 15:15:33.492741 Speed: 1000, full duplex
828 15:15:33.493155 Using ethernet@ff3f0000 device
829 15:15:33.497741 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
830 15:15:33.503199 Filename '745028/tftp-deploy-qdv8p6a_/kernel/uImage'.
831 15:15:33.507091 Load address: 0x1080000
832 15:15:36.846295 Loading: *################################################## 43.4 MiB
833 15:15:36.846722 13 MiB/s
834 15:15:36.846936 done
835 15:15:36.849955 Bytes transferred = 45482560 (2b60240 hex)
837 15:15:36.950930 => tftpboot 0x08000000 745028/tftp-deploy-qdv8p6a_/ramdisk/ramdisk.cpio.gz.uboot
838 15:15:36.951442 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
839 15:15:36.958182 tftpboot 0x08000000 745028/tftp-deploy-qdv8p6a_/ramdisk/ramdisk.cpio.gz.uboot
840 15:15:36.958500 Speed: 1000, full duplex
841 15:15:36.958729 Using ethernet@ff3f0000 device
842 15:15:36.963835 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
843 15:15:36.973381 Filename '745028/tftp-deploy-qdv8p6a_/ramdisk/ramdisk.cpio.gz.uboot'.
844 15:15:36.973826 Load address: 0x8000000
845 15:15:43.947957 Loading: *##########################################T ####### UDP wrong checksum 00000005 0000736e
846 15:15:48.948372 T UDP wrong checksum 00000005 0000736e
847 15:15:58.951132 T T UDP wrong checksum 00000005 0000736e
848 15:16:18.953592 T T T UDP wrong checksum 00000005 0000736e
849 15:16:33.959115 T T T
850 15:16:33.959753 Retry count exceeded; starting again
852 15:16:33.961347 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
855 15:16:33.963259 end: 2.4 uboot-commands (duration 00:01:25) [common]
857 15:16:33.964753 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
859 15:16:33.965820 end: 2 uboot-action (duration 00:01:25) [common]
861 15:16:33.967442 Cleaning after the job
862 15:16:33.968046 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/ramdisk
863 15:16:33.969392 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/kernel
864 15:16:33.996307 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/dtb
865 15:16:33.997615 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/nfsrootfs
866 15:16:34.059663 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/745028/tftp-deploy-qdv8p6a_/modules
867 15:16:34.067064 start: 4.1 power-off (timeout 00:00:30) [common]
868 15:16:34.067727 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
869 15:16:34.104182 >> OK - accepted request
870 15:16:34.106347 Returned 0 in 0 seconds
871 15:16:34.207134 end: 4.1 power-off (duration 00:00:00) [common]
873 15:16:34.208182 start: 4.2 read-feedback (timeout 00:10:00) [common]
874 15:16:34.208867 Listened to connection for namespace 'common' for up to 1s
875 15:16:35.209840 Finalising connection for namespace 'common'
876 15:16:35.210344 Disconnecting from shell: Finalise
877 15:16:35.210627 =>
878 15:16:35.311368 end: 4.2 read-feedback (duration 00:00:01) [common]
879 15:16:35.312160 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/745028
880 15:16:37.729366 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/745028
881 15:16:37.730064 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.