Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 02:27:57.250364 lava-dispatcher, installed at version: 2024.01
2 02:27:57.250663 start: 0 validate
3 02:27:57.250823 Start time: 2024-08-30 02:27:57.250811+00:00 (UTC)
4 02:27:57.250998 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 02:27:57.533951 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 02:27:57.675137 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 02:27:57.815649 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 02:27:57.956845 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 02:27:58.100106 validate duration: 0.85
11 02:27:58.100732 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 02:27:58.100955 start: 1.1 download-retry (timeout 00:10:00) [common]
13 02:27:58.101163 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 02:27:58.101521 Not decompressing ramdisk as can be used compressed.
15 02:27:58.101772 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 02:27:58.101981 saving as /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/ramdisk/initrd.cpio.gz
17 02:27:58.102160 total size: 4775763 (4 MB)
18 02:27:58.380876 progress 0 % (0 MB)
19 02:27:59.303497 progress 5 % (0 MB)
20 02:27:59.306631 progress 10 % (0 MB)
21 02:27:59.444050 progress 15 % (0 MB)
22 02:27:59.579271 progress 20 % (0 MB)
23 02:27:59.583518 progress 25 % (1 MB)
24 02:27:59.586294 progress 30 % (1 MB)
25 02:27:59.716752 progress 35 % (1 MB)
26 02:27:59.719880 progress 40 % (1 MB)
27 02:27:59.722788 progress 45 % (2 MB)
28 02:27:59.726241 progress 50 % (2 MB)
29 02:27:59.729608 progress 55 % (2 MB)
30 02:27:59.732807 progress 60 % (2 MB)
31 02:27:59.854374 progress 65 % (2 MB)
32 02:27:59.857676 progress 70 % (3 MB)
33 02:27:59.860618 progress 75 % (3 MB)
34 02:27:59.863641 progress 80 % (3 MB)
35 02:27:59.866597 progress 85 % (3 MB)
36 02:27:59.869939 progress 90 % (4 MB)
37 02:27:59.872922 progress 95 % (4 MB)
38 02:28:00.149326 progress 100 % (4 MB)
39 02:28:00.149964 4 MB downloaded in 2.05 s (2.22 MB/s)
40 02:28:00.150343 end: 1.1.1 http-download (duration 00:00:02) [common]
42 02:28:00.150853 end: 1.1 download-retry (duration 00:00:02) [common]
43 02:28:00.151024 start: 1.2 download-retry (timeout 00:09:58) [common]
44 02:28:00.151260 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 02:28:00.151625 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 02:28:00.151766 saving as /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/kernel/zImage
47 02:28:00.151909 total size: 11350528 (10 MB)
48 02:28:00.152091 No compression specified
49 02:28:00.292609 progress 0 % (0 MB)
50 02:28:00.299012 progress 5 % (0 MB)
51 02:28:00.445917 progress 10 % (1 MB)
52 02:28:00.451647 progress 15 % (1 MB)
53 02:28:00.457954 progress 20 % (2 MB)
54 02:28:00.463511 progress 25 % (2 MB)
55 02:28:00.573511 progress 30 % (3 MB)
56 02:28:00.594220 progress 35 % (3 MB)
57 02:28:00.601887 progress 40 % (4 MB)
58 02:28:00.748615 progress 45 % (4 MB)
59 02:28:00.754805 progress 50 % (5 MB)
60 02:28:00.760427 progress 55 % (5 MB)
61 02:28:00.765969 progress 60 % (6 MB)
62 02:28:00.771774 progress 65 % (7 MB)
63 02:28:00.875382 progress 70 % (7 MB)
64 02:28:00.892249 progress 75 % (8 MB)
65 02:28:00.989144 progress 80 % (8 MB)
66 02:28:01.025872 progress 85 % (9 MB)
67 02:28:01.033560 progress 90 % (9 MB)
68 02:28:01.131069 progress 95 % (10 MB)
69 02:28:01.169701 progress 100 % (10 MB)
70 02:28:01.170122 10 MB downloaded in 1.02 s (10.63 MB/s)
71 02:28:01.170426 end: 1.2.1 http-download (duration 00:00:01) [common]
73 02:28:01.170880 end: 1.2 download-retry (duration 00:00:01) [common]
74 02:28:01.171044 start: 1.3 download-retry (timeout 00:09:57) [common]
75 02:28:01.171197 start: 1.3.1 http-download (timeout 00:09:57) [common]
76 02:28:01.171471 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 02:28:01.171600 saving as /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/dtb/am335x-boneblack.dtb
78 02:28:01.171715 total size: 70308 (0 MB)
79 02:28:01.171831 No compression specified
80 02:28:01.312134 progress 46 % (0 MB)
81 02:28:01.312744 progress 93 % (0 MB)
82 02:28:01.313234 progress 100 % (0 MB)
83 02:28:01.313459 0 MB downloaded in 0.14 s (0.47 MB/s)
84 02:28:01.313735 end: 1.3.1 http-download (duration 00:00:00) [common]
86 02:28:01.314220 end: 1.3 download-retry (duration 00:00:00) [common]
87 02:28:01.314377 start: 1.4 download-retry (timeout 00:09:57) [common]
88 02:28:01.314532 start: 1.4.1 http-download (timeout 00:09:57) [common]
89 02:28:01.314805 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 02:28:01.314936 saving as /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/nfsrootfs/full.rootfs.tar
91 02:28:01.315053 total size: 117747780 (112 MB)
92 02:28:01.315173 Using unxz to decompress xz
93 02:28:01.455780 progress 0 % (0 MB)
94 02:28:01.935266 progress 5 % (5 MB)
95 02:28:02.602650 progress 10 % (11 MB)
96 02:28:03.213998 progress 15 % (16 MB)
97 02:28:03.881192 progress 20 % (22 MB)
98 02:28:04.486747 progress 25 % (28 MB)
99 02:28:05.128809 progress 30 % (33 MB)
100 02:28:05.721127 progress 35 % (39 MB)
101 02:28:06.305141 progress 40 % (44 MB)
102 02:28:06.905164 progress 45 % (50 MB)
103 02:28:07.499369 progress 50 % (56 MB)
104 02:28:08.067976 progress 55 % (61 MB)
105 02:28:08.641518 progress 60 % (67 MB)
106 02:28:09.211645 progress 65 % (73 MB)
107 02:28:09.785888 progress 70 % (78 MB)
108 02:28:10.400354 progress 75 % (84 MB)
109 02:28:10.975651 progress 80 % (89 MB)
110 02:28:11.552197 progress 85 % (95 MB)
111 02:28:12.121318 progress 90 % (101 MB)
112 02:28:12.686301 progress 95 % (106 MB)
113 02:28:13.254860 progress 100 % (112 MB)
114 02:28:13.257874 112 MB downloaded in 11.94 s (9.40 MB/s)
115 02:28:13.258234 end: 1.4.1 http-download (duration 00:00:12) [common]
117 02:28:13.258698 end: 1.4 download-retry (duration 00:00:12) [common]
118 02:28:13.258859 start: 1.5 download-retry (timeout 00:09:45) [common]
119 02:28:13.259015 start: 1.5.1 http-download (timeout 00:09:45) [common]
120 02:28:13.259289 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 02:28:13.259421 saving as /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/modules/modules.tar
122 02:28:13.259535 total size: 6605748 (6 MB)
123 02:28:13.259650 Using unxz to decompress xz
124 02:28:13.400829 progress 0 % (0 MB)
125 02:28:13.418525 progress 5 % (0 MB)
126 02:28:13.438915 progress 10 % (0 MB)
127 02:28:13.459121 progress 15 % (0 MB)
128 02:28:13.480868 progress 20 % (1 MB)
129 02:28:13.550176 progress 25 % (1 MB)
130 02:28:13.571641 progress 30 % (1 MB)
131 02:28:13.592023 progress 35 % (2 MB)
132 02:28:13.612245 progress 40 % (2 MB)
133 02:28:13.680961 progress 45 % (2 MB)
134 02:28:13.701762 progress 50 % (3 MB)
135 02:28:13.721494 progress 55 % (3 MB)
136 02:28:13.741696 progress 60 % (3 MB)
137 02:28:13.816942 progress 65 % (4 MB)
138 02:28:13.836677 progress 70 % (4 MB)
139 02:28:13.857813 progress 75 % (4 MB)
140 02:28:13.879168 progress 80 % (5 MB)
141 02:28:13.899972 progress 85 % (5 MB)
142 02:28:13.965051 progress 90 % (5 MB)
143 02:28:13.985502 progress 95 % (6 MB)
144 02:28:14.006286 progress 100 % (6 MB)
145 02:28:14.012101 6 MB downloaded in 0.75 s (8.37 MB/s)
146 02:28:14.012499 end: 1.5.1 http-download (duration 00:00:01) [common]
148 02:28:14.012906 end: 1.5 download-retry (duration 00:00:01) [common]
149 02:28:14.012989 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
150 02:28:14.013070 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
151 02:28:23.327289 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/675320/extract-nfsrootfs-86biawjy
152 02:28:23.327562 end: 1.6.1 extract-nfsrootfs (duration 00:00:09) [common]
153 02:28:23.327658 start: 1.6.2 lava-overlay (timeout 00:09:35) [common]
154 02:28:23.327907 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3
155 02:28:23.328030 makedir: /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin
156 02:28:23.328129 makedir: /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/tests
157 02:28:23.328216 makedir: /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/results
158 02:28:23.328324 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-add-keys
159 02:28:23.328489 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-add-sources
160 02:28:23.328622 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-background-process-start
161 02:28:23.328753 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-background-process-stop
162 02:28:23.328890 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-common-functions
163 02:28:23.329047 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-echo-ipv4
164 02:28:23.329181 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-install-packages
165 02:28:23.329308 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-installed-packages
166 02:28:23.329435 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-os-build
167 02:28:23.329561 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-probe-channel
168 02:28:23.329688 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-probe-ip
169 02:28:23.329853 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-target-ip
170 02:28:23.329990 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-target-mac
171 02:28:23.330122 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-target-storage
172 02:28:23.330260 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-test-case
173 02:28:23.330390 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-test-event
174 02:28:23.330521 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-test-feedback
175 02:28:23.330647 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-test-raise
176 02:28:23.330774 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-test-reference
177 02:28:23.330899 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-test-runner
178 02:28:23.331026 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-test-set
179 02:28:23.331155 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-test-shell
180 02:28:23.331289 Updating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-add-keys (debian)
181 02:28:26.155727 Updating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-add-sources (debian)
182 02:28:26.156302 Updating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-install-packages (debian)
183 02:28:26.156672 Updating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-installed-packages (debian)
184 02:28:26.156984 Updating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/bin/lava-os-build (debian)
185 02:28:26.157246 Creating /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/environment
186 02:28:26.157461 LAVA metadata
187 02:28:26.157604 - LAVA_JOB_ID=675320
188 02:28:26.157722 - LAVA_DISPATCHER_IP=192.168.56.76
189 02:28:26.157966 start: 1.6.2.1 ssh-authorize (timeout 00:09:32) [common]
190 02:28:26.158325 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 02:28:26.158457 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:32) [common]
192 02:28:26.158546 skipped lava-vland-overlay
193 02:28:26.158632 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 02:28:26.158708 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:32) [common]
195 02:28:26.158763 skipped lava-multinode-overlay
196 02:28:26.158830 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 02:28:26.158906 start: 1.6.2.4 test-definition (timeout 00:09:32) [common]
198 02:28:26.159000 Loading test definitions
199 02:28:26.159082 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:32) [common]
200 02:28:26.159143 Using /lava-675320 at stage 0
201 02:28:26.159527 uuid=675320_1.6.2.4.1 testdef=None
202 02:28:26.159623 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 02:28:26.159700 start: 1.6.2.4.2 test-overlay (timeout 00:09:32) [common]
204 02:28:26.160174 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 02:28:26.160384 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:32) [common]
207 02:28:26.161049 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 02:28:26.161300 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:32) [common]
210 02:28:26.197015 runner path: /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/0/tests/0_timesync-off test_uuid 675320_1.6.2.4.1
211 02:28:26.197313 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 02:28:26.197588 start: 1.6.2.4.5 git-repo-action (timeout 00:09:32) [common]
214 02:28:26.197668 Using /lava-675320 at stage 0
215 02:28:26.197817 Fetching tests from https://github.com/kernelci/test-definitions.git
216 02:28:26.197933 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/0/tests/1_kselftest-dt'
217 02:28:31.080894 Running '/usr/bin/git checkout kernelci.org
218 02:28:31.158605 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 02:28:31.159422 uuid=675320_1.6.2.4.5 testdef=None
220 02:28:31.159651 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 02:28:31.160079 start: 1.6.2.4.6 test-overlay (timeout 00:09:27) [common]
223 02:28:31.161634 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 02:28:31.162102 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:27) [common]
226 02:28:31.164418 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 02:28:31.164897 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:27) [common]
229 02:28:31.166895 runner path: /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/0/tests/1_kselftest-dt test_uuid 675320_1.6.2.4.5
230 02:28:31.167063 BOARD='beaglebone-black'
231 02:28:31.167177 BRANCH='mainline'
232 02:28:31.167284 SKIPFILE='/dev/null'
233 02:28:31.167391 SKIP_INSTALL='True'
234 02:28:31.167497 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 02:28:31.167605 TST_CASENAME=''
236 02:28:31.167713 TST_CMDFILES='dt'
237 02:28:31.168025 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 02:28:31.168439 Creating lava-test-runner.conf files
240 02:28:31.168553 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/675320/lava-overlay-k2ku45c3/lava-675320/0 for stage 0
241 02:28:31.168729 - 0_timesync-off
242 02:28:31.168857 - 1_kselftest-dt
243 02:28:31.169054 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 02:28:31.169215 start: 1.6.2.5 compress-overlay (timeout 00:09:27) [common]
245 02:28:39.569283 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 02:28:39.569451 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:19) [common]
247 02:28:39.569535 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 02:28:39.569628 end: 1.6.2 lava-overlay (duration 00:00:16) [common]
249 02:28:39.569711 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:19) [common]
250 02:28:39.666439 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 02:28:39.666713 start: 1.6.4 extract-modules (timeout 00:09:18) [common]
252 02:28:39.666871 extracting modules file /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/modules/modules.tar to /var/lib/lava/dispatcher/tmp/675320/extract-nfsrootfs-86biawjy
253 02:28:39.884999 extracting modules file /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/modules/modules.tar to /var/lib/lava/dispatcher/tmp/675320/extract-overlay-ramdisk-r3trnu1t/ramdisk
254 02:28:40.110812 end: 1.6.4 extract-modules (duration 00:00:00) [common]
255 02:28:40.110996 start: 1.6.5 apply-overlay-tftp (timeout 00:09:18) [common]
256 02:28:40.111089 [common] Applying overlay to NFS
257 02:28:40.111148 [common] Applying overlay /var/lib/lava/dispatcher/tmp/675320/compress-overlay-uwfav_wg/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/675320/extract-nfsrootfs-86biawjy
258 02:28:41.152418 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 02:28:41.152615 start: 1.6.6 prepare-kernel (timeout 00:09:17) [common]
260 02:28:41.152729 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:17) [common]
261 02:28:41.152833 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 02:28:41.152923 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 02:28:41.153017 start: 1.6.7 configure-preseed-file (timeout 00:09:17) [common]
264 02:28:41.153108 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 02:28:41.153199 start: 1.6.8 compress-ramdisk (timeout 00:09:17) [common]
266 02:28:41.153277 Building ramdisk /var/lib/lava/dispatcher/tmp/675320/extract-overlay-ramdisk-r3trnu1t/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/675320/extract-overlay-ramdisk-r3trnu1t/ramdisk
267 02:28:41.308127 >> 74798 blocks
268 02:28:43.003288 Adding RAMdisk u-boot header.
269 02:28:43.003604 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/675320/extract-overlay-ramdisk-r3trnu1t/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/675320/extract-overlay-ramdisk-r3trnu1t/ramdisk.cpio.gz.uboot
270 02:28:43.245903 output: Image Name:
271 02:28:43.246156 output: Created: Fri Aug 30 02:28:43 2024
272 02:28:43.246332 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 02:28:43.246490 output: Data Size: 14792358 Bytes = 14445.66 KiB = 14.11 MiB
274 02:28:43.246642 output: Load Address: 00000000
275 02:28:43.246792 output: Entry Point: 00000000
276 02:28:43.246941 output:
277 02:28:43.247212 rename /var/lib/lava/dispatcher/tmp/675320/extract-overlay-ramdisk-r3trnu1t/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/ramdisk/ramdisk.cpio.gz.uboot
278 02:28:43.247461 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 02:28:43.247663 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
280 02:28:43.247857 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
281 02:28:43.248027 No LXC device requested
282 02:28:43.248220 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 02:28:43.248409 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
284 02:28:43.248635 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 02:28:43.248818 Checking files for TFTP limit of 4294967296 bytes.
286 02:28:43.249961 end: 1 tftp-deploy (duration 00:00:45) [common]
287 02:28:43.250230 start: 2 uboot-action (timeout 00:05:00) [common]
288 02:28:43.250485 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 02:28:43.250721 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 02:28:43.250959 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 02:28:43.251314 substitutions:
292 02:28:43.251489 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 02:28:43.251654 - {DTB_ADDR}: 0x88000000
294 02:28:43.251804 - {DTB}: 675320/tftp-deploy-hss_xpab/dtb/am335x-boneblack.dtb
295 02:28:43.251955 - {INITRD}: 675320/tftp-deploy-hss_xpab/ramdisk/ramdisk.cpio.gz.uboot
296 02:28:43.252105 - {KERNEL_ADDR}: 0x82000000
297 02:28:43.252254 - {KERNEL}: 675320/tftp-deploy-hss_xpab/kernel/zImage
298 02:28:43.252401 - {LAVA_MAC}: None
299 02:28:43.252619 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/675320/extract-nfsrootfs-86biawjy
300 02:28:43.252801 - {NFS_SERVER_IP}: 192.168.56.76
301 02:28:43.252987 - {PRESEED_CONFIG}: None
302 02:28:43.253174 - {PRESEED_LOCAL}: None
303 02:28:43.253361 - {RAMDISK_ADDR}: 0x83000000
304 02:28:43.253549 - {RAMDISK}: 675320/tftp-deploy-hss_xpab/ramdisk/ramdisk.cpio.gz.uboot
305 02:28:43.253736 - {ROOT_PART}: None
306 02:28:43.253947 - {ROOT}: None
307 02:28:43.254138 - {SERVER_IP}: 192.168.56.76
308 02:28:43.254325 - {TEE_ADDR}: 0x83000000
309 02:28:43.254512 - {TEE}: None
310 02:28:43.254702 Parsed boot commands:
311 02:28:43.254889 - setenv autoload no
312 02:28:43.255075 - setenv initrd_high 0xffffffff
313 02:28:43.255262 - setenv fdt_high 0xffffffff
314 02:28:43.255447 - dhcp
315 02:28:43.255631 - setenv serverip 192.168.56.76
316 02:28:43.255815 - tftp 0x82000000 675320/tftp-deploy-hss_xpab/kernel/zImage
317 02:28:43.256003 - tftp 0x83000000 675320/tftp-deploy-hss_xpab/ramdisk/ramdisk.cpio.gz.uboot
318 02:28:43.256191 - setenv initrd_size ${filesize}
319 02:28:43.256377 - tftp 0x88000000 675320/tftp-deploy-hss_xpab/dtb/am335x-boneblack.dtb
320 02:28:43.256561 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/675320/extract-nfsrootfs-86biawjy,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 02:28:43.256754 - bootz 0x82000000 0x83000000 0x88000000
322 02:28:43.257007 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 02:28:43.257611 start: 2.3 connect-device (timeout 00:05:00) [common]
325 02:28:43.257807 [common] connect-device Connecting to device using 'telnet conserv3 3000'
326 02:28:43.263586 Setting prompt string to ['lava-test: # ']
327 02:28:43.264178 end: 2.3 connect-device (duration 00:00:00) [common]
328 02:28:43.264408 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 02:28:43.264616 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 02:28:43.264805 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 02:28:43.265217 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
332 02:28:43.278326 >> OK - accepted request
333 02:28:43.279152 Returned 0 in 0 seconds
334 02:28:43.380012 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
336 02:28:43.380801 end: 2.4.1 reset-device (duration 00:00:00) [common]
337 02:28:43.381041 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
338 02:28:43.381258 Setting prompt string to ['Hit any key to stop autoboot']
339 02:28:43.381435 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
340 02:28:43.382233 Trying 192.168.56.22...
341 02:28:43.382421 Connected to conserv3.
342 02:28:43.382579 Escape character is '^]'.
343 02:28:43.382728
344 02:28:43.382877 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
345 02:28:43.383025
346 02:28:51.640385
347 02:28:51.647728 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
348 02:28:51.648063 Trying to boot from MMC1
349 02:28:52.224119
350 02:28:52.224417
351 02:28:52.229502 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
352 02:28:52.229824
353 02:28:52.229994 CPU : AM335X-GP rev 2.0
354 02:28:52.234696 Model: TI AM335x BeagleBone Black
355 02:28:52.234930 DRAM: 512 MiB
356 02:28:55.697598
357 02:28:55.704468 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
358 02:28:55.704770 Trying to boot from MMC1
359 02:28:56.284464
360 02:28:56.284775
361 02:28:56.290127 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
362 02:28:56.290513
363 02:28:56.290677 CPU : AM335X-GP rev 2.0
364 02:28:56.295179 Model: TI AM335x BeagleBone Black
365 02:28:56.295482 DRAM: 512 MiB
366 02:28:58.389895
367 02:28:58.396953 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
368 02:28:58.397207 Trying to boot from MMC1
369 02:28:58.973160
370 02:28:58.973461
371 02:28:58.978624 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
372 02:28:58.978983
373 02:28:58.979199 CPU : AM335X-GP rev 2.0
374 02:28:58.983819 Model: TI AM335x BeagleBone Black
375 02:28:58.984120 DRAM: 512 MiB
376 02:28:59.067881 Core: 160 devices, 18 uclasses, devicetree: separate
377 02:28:59.082187 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
378 02:28:59.482529 NAND: 0 MiB
379 02:28:59.492980 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
380 02:28:59.566553 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
381 02:28:59.588715 <ethaddr> not set. Validating first E-fuse MAC
382 02:28:59.617713 Net: eth2: ethernet@4a100000, eth3: usb_ether
384 02:28:59.676166 Hit any key to stop autoboot: 2
385 02:28:59.676700 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
386 02:28:59.677020 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
387 02:28:59.677243 Setting prompt string to ['=>']
388 02:28:59.677475 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
389 02:28:59.686064 0
390 02:28:59.686639 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
391 02:28:59.686845 Sending with 10 millisecond of delay
393 02:29:00.824472 => setenv autoload no
394 02:29:00.834947 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
395 02:29:00.836879 setenv autoload no
396 02:29:00.837295 Sending with 10 millisecond of delay
398 02:29:02.641245 => setenv initrd_high 0xffffffff
399 02:29:02.651741 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
400 02:29:02.652223 setenv initrd_high 0xffffffff
401 02:29:02.652627 Sending with 10 millisecond of delay
403 02:29:04.274846 => setenv fdt_high 0xffffffff
404 02:29:04.285325 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
405 02:29:04.285772 setenv fdt_high 0xffffffff
406 02:29:04.286204 Sending with 10 millisecond of delay
408 02:29:04.578006 => dhcp
409 02:29:04.588424 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 02:29:04.588838 dhcp
411 02:29:04.588979 link up on port 0, speed 100, full duplex
412 02:29:04.589092 BOOTP broadcast 1
413 02:29:04.843253 BOOTP broadcast 2
414 02:29:05.344355 BOOTP broadcast 3
415 02:29:06.346120 BOOTP broadcast 4
416 02:29:08.348051 BOOTP broadcast 5
417 02:29:08.374094 *** Unhandled DHCP Option in OFFER/ACK: 42
418 02:29:08.417728 *** Unhandled DHCP Option in OFFER/ACK: 42
419 02:29:08.424500 DHCP client bound to address 192.168.56.2 (3831 ms)
420 02:29:08.425097 Sending with 10 millisecond of delay
422 02:29:10.231877 => setenv serverip 192.168.56.76
423 02:29:10.242442 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
424 02:29:10.243045 setenv serverip 192.168.56.76
425 02:29:10.243465 Sending with 10 millisecond of delay
427 02:29:13.743044 => tftp 0x82000000 675320/tftp-deploy-hss_xpab/kernel/zImage
428 02:29:13.753489 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
429 02:29:13.753967 tftp 0x82000000 675320/tftp-deploy-hss_xpab/kernel/zImage
430 02:29:13.754156 link up on port 0, speed 100, full duplex
431 02:29:13.758000 Using ethernet@4a100000 device
432 02:29:13.763957 TFTP from server 192.168.56.76; our IP address is 192.168.56.2
433 02:29:13.771100 Filename '675320/tftp-deploy-hss_xpab/kernel/zImage'.
434 02:29:13.771230 Load address: 0x82000000
435 02:29:15.633632 Loading: *################################################## 10.8 MiB
436 02:29:15.633935 5.8 MiB/s
437 02:29:15.634100 done
438 02:29:15.637996 Bytes transferred = 11350528 (ad3200 hex)
439 02:29:15.638434 Sending with 10 millisecond of delay
441 02:29:20.114773 => tftp 0x83000000 675320/tftp-deploy-hss_xpab/ramdisk/ramdisk.cpio.gz.uboot
442 02:29:20.125331 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
443 02:29:20.125853 tftp 0x83000000 675320/tftp-deploy-hss_xpab/ramdisk/ramdisk.cpio.gz.uboot
444 02:29:20.126039 link up on port 0, speed 100, full duplex
445 02:29:20.130041 Using ethernet@4a100000 device
446 02:29:20.135902 TFTP from server 192.168.56.76; our IP address is 192.168.56.2
447 02:29:20.144566 Filename '675320/tftp-deploy-hss_xpab/ramdisk/ramdisk.cpio.gz.uboot'.
448 02:29:20.144863 Load address: 0x83000000
449 02:29:22.539367 Loading: *################################################## 14.1 MiB
450 02:29:22.539657 5.9 MiB/s
451 02:29:22.539820 done
452 02:29:22.543662 Bytes transferred = 14792422 (e1b6e6 hex)
453 02:29:22.544112 Sending with 10 millisecond of delay
455 02:29:24.407838 => setenv initrd_size ${filesize}
456 02:29:24.418635 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
457 02:29:24.419216 setenv initrd_size ${filesize}
458 02:29:24.419624 Sending with 10 millisecond of delay
460 02:29:28.575251 => tftp 0x88000000 675320/tftp-deploy-hss_xpab/dtb/am335x-boneblack.dtb
461 02:29:28.585845 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
462 02:29:28.586288 tftp 0x88000000 675320/tftp-deploy-hss_xpab/dtb/am335x-boneblack.dtb
463 02:29:28.586465 link up on port 0, speed 100, full duplex
464 02:29:28.590267 Using ethernet@4a100000 device
465 02:29:28.596195 TFTP from server 192.168.56.76; our IP address is 192.168.56.2
466 02:29:28.605663 Filename '675320/tftp-deploy-hss_xpab/dtb/am335x-boneblack.dtb'.
467 02:29:28.605893 Load address: 0x88000000
468 02:29:28.615506 Loading: *################################################## 68.7 KiB
469 02:29:28.615697 5.2 MiB/s
470 02:29:28.624108 done
471 02:29:28.624323 Bytes transferred = 70308 (112a4 hex)
472 02:29:28.624697 Sending with 10 millisecond of delay
474 02:29:42.006259 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/675320/extract-nfsrootfs-86biawjy,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
475 02:29:42.016656 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
476 02:29:42.017037 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/675320/extract-nfsrootfs-86biawjy,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
477 02:29:42.017384 Sending with 10 millisecond of delay
479 02:29:44.358215 => bootz 0x82000000 0x83000000 0x88000000
480 02:29:44.368580 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
481 02:29:44.368789 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
482 02:29:44.369050 bootz 0x82000000 0x83000000 0x88000000
483 02:29:44.369140 Kernel image @ 0x82000000 [ 0x000000 - 0xad3200 ]
484 02:29:44.370502 ## Loading init Ramdisk from Legacy Image at 83000000 ...
485 02:29:44.376087 Image Name:
486 02:29:44.376284 Created: 2024-08-30 2:28:43 UTC
487 02:29:44.385045 Image Type: ARM Linux RAMDisk Image (uncompressed)
488 02:29:44.385243 Data Size: 14792358 Bytes = 14.1 MiB
489 02:29:44.392810 Load Address: 00000000
490 02:29:44.392998 Entry Point: 00000000
491 02:29:44.561873 Verifying Checksum ... OK
492 02:29:44.562209 ## Flattened Device Tree blob at 88000000
493 02:29:44.568470 Booting using the fdt blob at 0x88000000
494 02:29:44.568710 Working FDT set to 88000000
495 02:29:44.574106 Using Device Tree in place at 88000000, end 880142a3
496 02:29:44.578334 Working FDT set to 88000000
497 02:29:44.591570
498 02:29:44.591811 Starting kernel ...
499 02:29:44.591942
500 02:29:44.592349 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
501 02:29:44.592532 start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
502 02:29:44.592670 Setting prompt string to ['Linux version [0-9]']
503 02:29:44.592806 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
504 02:29:44.592943 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
505 02:29:45.429218 [ 0.000000] Booting Linux on physical CPU 0x0
506 02:29:45.435105 start: 2.4.4.1 login-action (timeout 00:03:58) [common]
507 02:29:45.435419 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
508 02:29:45.435621 Setting prompt string to []
509 02:29:45.435824 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
510 02:29:45.436021 Using line separator: #'\n'#
511 02:29:45.436196 No login prompt set.
512 02:29:45.436372 Parsing kernel messages
513 02:29:45.436520 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
514 02:29:45.436814 [login-action] Waiting for messages, (timeout 00:03:58)
515 02:29:45.436979 Waiting using forced prompt support (timeout 00:01:59)
516 02:29:45.449239 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j300988-arm-gcc-12-multi-v7-defconfig-mqhxl) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Aug 30 02:02:35 UTC 2024
517 02:29:45.460603 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
518 02:29:45.463990 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
519 02:29:45.469611 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
520 02:29:45.481330 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
521 02:29:45.481483 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
522 02:29:45.486961 [ 0.000000] Memory policy: Data cache writeback
523 02:29:45.493778 [ 0.000000] efi: UEFI not found.
524 02:29:45.501960 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
525 02:29:45.502287 [ 0.000000] Zone ranges:
526 02:29:45.513053 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
527 02:29:45.513344 [ 0.000000] Normal empty
528 02:29:45.518898 [ 0.000000] HighMem empty
529 02:29:45.519200 [ 0.000000] Movable zone start for each node
530 02:29:45.524680 [ 0.000000] Early memory node ranges
531 02:29:45.530178 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
532 02:29:45.538286 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
533 02:29:45.562657 [ 0.000000] CPU: All CPU(s) started in SVC mode.
534 02:29:45.568445 [ 0.000000] AM335X ES2.0 (sgx neon)
535 02:29:45.579924 [ 0.000000] percpu: Embedded 17 pages/cpu s40332 r8192 d21108 u69632
536 02:29:45.597507 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/675320/extract-nfsrootfs-86biawjy,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
537 02:29:45.609069 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
538 02:29:45.614926 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
539 02:29:45.620509 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
540 02:29:45.631118 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
541 02:29:45.660357 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
542 02:29:45.666156 <6>[ 0.000000] trace event string verifier disabled
543 02:29:45.666319 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
544 02:29:45.674109 <6>[ 0.000000] rcu: RCU event tracing is enabled.
545 02:29:45.679936 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
546 02:29:45.688837 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
547 02:29:45.696236 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
548 02:29:45.710875 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
549 02:29:45.727973 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
550 02:29:45.734689 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
551 02:29:45.827078 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
552 02:29:45.838409 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
553 02:29:45.845139 <6>[ 0.008332] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
554 02:29:45.858219 <6>[ 0.019141] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
555 02:29:45.865421 <6>[ 0.033861] Console: colour dummy device 80x30
556 02:29:45.871498 Matched prompt #6: WARNING:
557 02:29:45.871848 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
558 02:29:45.876961 <3>[ 0.038756] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
559 02:29:45.882666 <3>[ 0.045824] This ensures that you still see kernel messages. Please
560 02:29:45.886009 <3>[ 0.052550] update your kernel commandline.
561 02:29:45.926737 <6>[ 0.057161] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
562 02:29:45.932473 <6>[ 0.096145] CPU: Testing write buffer coherency: ok
563 02:29:45.938506 <6>[ 0.101510] CPU0: Spectre v2: using BPIALL workaround
564 02:29:45.938775 <6>[ 0.106976] pid_max: default: 32768 minimum: 301
565 02:29:45.950211 <6>[ 0.112159] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 02:29:45.956998 <6>[ 0.119976] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 02:29:45.963717 <6>[ 0.129254] CPU0: thread -1, cpu 0, socket -1, mpidr 0
568 02:29:45.972006 <6>[ 0.136103] Setting up static identity map for 0x80300000 - 0x803000ac
569 02:29:45.977760 <6>[ 0.145659] rcu: Hierarchical SRCU implementation.
570 02:29:45.985448 <6>[ 0.150935] rcu: Max phase no-delay instances is 1000.
571 02:29:45.993684 <6>[ 0.161920] EFI services will not be available.
572 02:29:45.999472 <6>[ 0.167161] smp: Bringing up secondary CPUs ...
573 02:29:46.005286 <6>[ 0.172199] smp: Brought up 1 node, 1 CPU
574 02:29:46.010962 <6>[ 0.176598] SMP: Total of 1 processors activated (996.14 BogoMIPS).
575 02:29:46.016900 <6>[ 0.183348] CPU: All CPU(s) started in SVC mode.
576 02:29:46.037637 <6>[ 0.188526] Memory: 407012K/522240K available (16384K kernel code, 2540K rwdata, 6736K rodata, 2048K init, 430K bss, 48024K reserved, 65536K cma-reserved, 0K highmem)
577 02:29:46.037974 <6>[ 0.204764] devtmpfs: initialized
578 02:29:46.059477 <6>[ 0.221712] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
579 02:29:46.067582 <6>[ 0.230286] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
580 02:29:46.076907 <6>[ 0.240718] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
581 02:29:46.087896 <6>[ 0.253030] pinctrl core: initialized pinctrl subsystem
582 02:29:46.096713 <6>[ 0.263641] DMI not present or invalid.
583 02:29:46.105199 <6>[ 0.269383] NET: Registered PF_NETLINK/PF_ROUTE protocol family
584 02:29:46.114397 <6>[ 0.278288] DMA: preallocated 256 KiB pool for atomic coherent allocations
585 02:29:46.129427 <6>[ 0.289670] thermal_sys: Registered thermal governor 'step_wise'
586 02:29:46.129600 <6>[ 0.289810] cpuidle: using governor menu
587 02:29:46.156543 <6>[ 0.325083] No ATAGs?
588 02:29:46.162747 <6>[ 0.327726] hw-breakpoint: debug architecture 0x4 unsupported.
589 02:29:46.173448 <6>[ 0.339677] Serial: AMBA PL011 UART driver
590 02:29:46.214578 <6>[ 0.382814] iommu: Default domain type: Translated
591 02:29:46.223981 <6>[ 0.388044] iommu: DMA domain TLB invalidation policy: strict mode
592 02:29:46.233434 <5>[ 0.400508] SCSI subsystem initialized
593 02:29:46.257427 <6>[ 0.420223] usbcore: registered new interface driver usbfs
594 02:29:46.264338 <6>[ 0.426178] usbcore: registered new interface driver hub
595 02:29:46.264526 <6>[ 0.431997] usbcore: registered new device driver usb
596 02:29:46.270082 <6>[ 0.438486] pps_core: LinuxPPS API ver. 1 registered
597 02:29:46.281862 <6>[ 0.443920] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
598 02:29:46.286655 <6>[ 0.453618] PTP clock support registered
599 02:29:46.312394 <6>[ 0.479616] EDAC MC: Ver: 3.0.0
600 02:29:46.330599 <6>[ 0.496531] scmi_core: SCMI protocol bus registered
601 02:29:46.346014 <6>[ 0.513805] vgaarb: loaded
602 02:29:46.358148 <6>[ 0.526736] clocksource: Switched to clocksource dmtimer
603 02:29:46.394399 <6>[ 0.562477] NET: Registered PF_INET protocol family
604 02:29:46.406954 <6>[ 0.568133] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
605 02:29:46.414032 <6>[ 0.576978] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
606 02:29:46.419753 <6>[ 0.585868] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
607 02:29:46.431383 <6>[ 0.594136] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
608 02:29:46.437439 <6>[ 0.602422] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
609 02:29:46.443423 <6>[ 0.610139] TCP: Hash tables configured (established 4096 bind 4096)
610 02:29:46.454478 <6>[ 0.617055] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
611 02:29:46.460987 <6>[ 0.624063] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
612 02:29:46.465542 <6>[ 0.631684] NET: Registered PF_UNIX/PF_LOCAL protocol family
613 02:29:46.503404 <6>[ 0.666140] RPC: Registered named UNIX socket transport module.
614 02:29:46.503572 <6>[ 0.672564] RPC: Registered udp transport module.
615 02:29:46.509508 <6>[ 0.677695] RPC: Registered tcp transport module.
616 02:29:46.514880 <6>[ 0.682800] RPC: Registered tcp-with-tls transport module.
617 02:29:46.527893 <6>[ 0.688732] RPC: Registered tcp NFSv4.1 backchannel transport module.
618 02:29:46.528169 <6>[ 0.695637] PCI: CLS 0 bytes, default 64
619 02:29:46.535068 <5>[ 0.701416] Initialise system trusted keyrings
620 02:29:46.559875 <6>[ 0.725326] Trying to unpack rootfs image as initramfs...
621 02:29:46.585502 <6>[ 0.747348] workingset: timestamp_bits=30 max_order=17 bucket_order=0
622 02:29:46.590036 <6>[ 0.754826] squashfs: version 4.0 (2009/01/31) Phillip Lougher
623 02:29:46.631741 <5>[ 0.799809] NFS: Registering the id_resolver key type
624 02:29:46.637137 <5>[ 0.805389] Key type id_resolver registered
625 02:29:46.643247 <5>[ 0.810013] Key type id_legacy registered
626 02:29:46.648649 <6>[ 0.814451] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
627 02:29:46.658239 <6>[ 0.821670] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
628 02:29:46.688945 <5>[ 0.857484] Key type asymmetric registered
629 02:29:46.694874 <5>[ 0.862008] Asymmetric key parser 'x509' registered
630 02:29:46.706944 <6>[ 0.867535] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
631 02:29:46.707103 <6>[ 0.875424] io scheduler mq-deadline registered
632 02:29:46.712618 <6>[ 0.880388] io scheduler kyber registered
633 02:29:46.717930 <6>[ 0.884838] io scheduler bfq registered
634 02:29:47.046101 <6>[ 1.210627] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
635 02:29:47.092153 <6>[ 1.260479] msm_serial: driver initialized
636 02:29:47.098258 <6>[ 1.265263] SuperH (H)SCI(F) driver initialized
637 02:29:47.104096 <6>[ 1.270563] STMicroelectronics ASC driver initialized
638 02:29:47.109310 <6>[ 1.276168] STM32 USART driver initialized
639 02:29:47.204349 <6>[ 1.372221] brd: module loaded
640 02:29:47.241994 <6>[ 1.409775] loop: module loaded
641 02:29:47.286985 <6>[ 1.454465] CAN device driver interface
642 02:29:47.293808 <6>[ 1.459821] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
643 02:29:47.299481 <6>[ 1.466896] e1000e: Intel(R) PRO/1000 Network Driver
644 02:29:47.306114 <6>[ 1.472281] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
645 02:29:47.311752 <6>[ 1.478724] igb: Intel(R) Gigabit Ethernet Network Driver
646 02:29:47.319234 <6>[ 1.484547] igb: Copyright (c) 2007-2014 Intel Corporation.
647 02:29:47.331108 <6>[ 1.493856] pegasus: Pegasus/Pegasus II USB Ethernet driver
648 02:29:47.336852 <6>[ 1.500004] usbcore: registered new interface driver pegasus
649 02:29:47.342661 <6>[ 1.506129] usbcore: registered new interface driver asix
650 02:29:47.348510 <6>[ 1.512014] usbcore: registered new interface driver ax88179_178a
651 02:29:47.354160 <6>[ 1.518604] usbcore: registered new interface driver cdc_ether
652 02:29:47.359967 <6>[ 1.524904] usbcore: registered new interface driver smsc75xx
653 02:29:47.365741 <6>[ 1.531144] usbcore: registered new interface driver smsc95xx
654 02:29:47.371567 <6>[ 1.537378] usbcore: registered new interface driver net1080
655 02:29:47.377322 <6>[ 1.543498] usbcore: registered new interface driver cdc_subset
656 02:29:47.383262 <6>[ 1.549903] usbcore: registered new interface driver zaurus
657 02:29:47.391351 <6>[ 1.555971] usbcore: registered new interface driver cdc_ncm
658 02:29:47.400673 <6>[ 1.565487] usbcore: registered new interface driver usb-storage
659 02:29:47.482264 <6>[ 1.648890] i2c_dev: i2c /dev entries driver
660 02:29:47.543174 <5>[ 1.703471] cpuidle: enable-method property 'ti,am3352' found operations
661 02:29:47.548976 <6>[ 1.713172] sdhci: Secure Digital Host Controller Interface driver
662 02:29:47.557129 <6>[ 1.719936] sdhci: Copyright(c) Pierre Ossman
663 02:29:47.563987 <6>[ 1.726406] Synopsys Designware Multimedia Card Interface Driver
664 02:29:47.568611 <6>[ 1.734411] sdhci-pltfm: SDHCI platform and OF driver helper
665 02:29:47.622028 <6>[ 1.786879] ledtrig-cpu: registered to indicate activity on CPUs
666 02:29:47.660148 <6>[ 1.820656] usbcore: registered new interface driver usbhid
667 02:29:47.660457 <6>[ 1.826817] usbhid: USB HID core driver
668 02:29:47.701569 <6>[ 1.867286] NET: Registered PF_INET6 protocol family
669 02:29:47.739868 <6>[ 1.907949] Segment Routing with IPv6
670 02:29:47.745214 <6>[ 1.912092] In-situ OAM (IOAM) with IPv6
671 02:29:47.752011 <6>[ 1.916474] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
672 02:29:47.757798 <6>[ 1.923818] NET: Registered PF_PACKET protocol family
673 02:29:47.763850 <6>[ 1.929370] can: controller area network core
674 02:29:47.769390 <6>[ 1.934198] NET: Registered PF_CAN protocol family
675 02:29:47.769688 <6>[ 1.939422] can: raw protocol
676 02:29:47.775155 <6>[ 1.942748] can: broadcast manager protocol
677 02:29:47.781558 <6>[ 1.947342] can: netlink gateway - max_hops=1
678 02:29:47.787890 <5>[ 1.952808] Key type dns_resolver registered
679 02:29:47.794119 <6>[ 1.957870] ThumbEE CPU extension supported.
680 02:29:47.794362 <5>[ 1.962555] Registering SWP/SWPB emulation handler
681 02:29:47.803872 <3>[ 1.968235] omap_voltage_late_init: Voltage driver support not added
682 02:29:47.871393 <5>[ 2.037471] Loading compiled-in X.509 certificates
683 02:29:48.030033 <6>[ 2.185615] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
684 02:29:48.037235 <6>[ 2.202247] pinctrl-single 44e10800.pinmux: 142 pins, size 568
685 02:29:48.063757 <3>[ 2.225739] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
686 02:29:48.148713 <3>[ 2.311066] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
687 02:29:48.241006 <6>[ 2.407367] OMAP GPIO hardware version 0.1
688 02:29:48.261099 <6>[ 2.425815] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
689 02:29:48.328206 <4>[ 2.492678] at24 2-0054: supply vcc not found, using dummy regulator
690 02:29:48.426255 <4>[ 2.590709] at24 2-0055: supply vcc not found, using dummy regulator
691 02:29:48.473462 <4>[ 2.637291] at24 2-0056: supply vcc not found, using dummy regulator
692 02:29:48.507782 <4>[ 2.671903] at24 2-0057: supply vcc not found, using dummy regulator
693 02:29:48.554437 <6>[ 2.719726] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
694 02:29:48.638483 <3>[ 2.799715] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
695 02:29:48.662920 <6>[ 2.820471] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
696 02:29:48.693808 <4>[ 2.856897] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
697 02:29:48.724349 <4>[ 2.887502] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
698 02:29:48.793465 <6>[ 2.958096] omap_rng 48310000.rng: Random Number Generator ver. 20
699 02:29:48.816340 <5>[ 2.983858] random: crng init done
700 02:29:48.914207 <6>[ 3.077314] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
701 02:29:49.616611 <6>[ 3.783504] Freeing initrd memory: 14448K
702 02:29:49.656946 <6>[ 3.819185] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
703 02:29:49.662486 <6>[ 3.829375] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
704 02:29:49.671056 <6>[ 3.836640] cpsw-switch 4a100000.switch: ALE Table size 1024
705 02:29:49.676821 <6>[ 3.843101] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
706 02:29:49.694382 <6>[ 3.851231] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
707 02:29:49.701528 <6>[ 3.862860] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
708 02:29:49.711190 <5>[ 3.871890] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
709 02:29:49.738844 <3>[ 3.901536] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
710 02:29:49.744502 <6>[ 3.910107] edma 49000000.dma: TI EDMA DMA engine driver
711 02:29:49.814966 <3>[ 3.976992] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
712 02:29:49.828972 <6>[ 3.991245] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
713 02:29:49.846397 <3>[ 4.012814] l3-aon-clkctrl:0000:0: failed to disable
714 02:29:49.884422 <6>[ 4.047334] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
715 02:29:49.890193 <6>[ 4.056660] printk: legacy console [ttyS0] enabled
716 02:29:49.895889 <6>[ 4.056660] printk: legacy console [ttyS0] enabled
717 02:29:49.902056 <6>[ 4.067054] printk: legacy bootconsole [omap8250] disabled
718 02:29:49.907838 <6>[ 4.067054] printk: legacy bootconsole [omap8250] disabled
719 02:29:49.966210 <4>[ 4.127470] tps65217-pmic: Failed to locate of_node [id: -1]
720 02:29:49.969677 <4>[ 4.134838] tps65217-bl: Failed to locate of_node [id: -1]
721 02:29:49.985382 <6>[ 4.154072] tps65217 0-0024: TPS65217 ID 0xe version 1.2
722 02:29:50.006001 <6>[ 4.161002] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
723 02:29:50.017471 <6>[ 4.174699] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
724 02:29:50.021005 <6>[ 4.186547] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
725 02:29:50.043479 <6>[ 4.206306] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
726 02:29:50.049173 <6>[ 4.215545] sdhci-omap 48060000.mmc: Got CD GPIO
727 02:29:50.057188 <4>[ 4.220702] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
728 02:29:50.072002 <4>[ 4.234114] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
729 02:29:50.078580 <4>[ 4.243042] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
730 02:29:50.088870 <4>[ 4.251836] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
731 02:29:50.210745 <6>[ 4.374890] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
732 02:29:50.248439 <6>[ 4.411586] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
733 02:29:50.271353 <6>[ 4.433697] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 02:29:50.278127 <6>[ 4.442644] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
735 02:29:50.326887 <6>[ 4.486024] mmc0: new high speed SDHC card at address 0001
736 02:29:50.327151 <6>[ 4.493561] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
737 02:29:50.335028 <6>[ 4.501870] mmcblk0: p1
738 02:29:50.342297 <6>[ 4.506629] mmc1: new high speed MMC card at address 0001
739 02:29:50.347689 <6>[ 4.513978] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
740 02:29:50.356133 <6>[ 4.523915] mmcblk1:
741 02:29:50.363856 <6>[ 4.527221] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
742 02:29:50.371429 <6>[ 4.534287] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
743 02:29:50.376862 <6>[ 4.541368] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
744 02:29:50.387773 <6>[ 4.548130] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
745 02:29:52.525140 <6>[ 6.687697] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 02:29:59.188220 <5>[ 6.746863] Sending DHCP requests ..., OK
747 02:29:59.199479 <6>[ 13.361305] IP-Config: Got DHCP answer from 192.168.56.254, my address is 192.168.56.2
748 02:29:59.199673 <6>[ 13.369717] IP-Config: Complete:
749 02:29:59.210739 <6>[ 13.373255] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.56.2, mask=255.255.255.0, gw=192.168.56.254
750 02:29:59.221964 <6>[ 13.384021] host=192.168.56.2, domain=mayfield.sirena.org.uk, nis-domain=(none)
751 02:29:59.227699 <6>[ 13.392141] bootserver=192.168.56.254, rootserver=192.168.56.76, rootpath=
752 02:29:59.233382 <6>[ 13.392175] nameserver0=192.168.56.254
753 02:29:59.240103 <6>[ 13.404344] ntpserver0=50.205.244.22, ntpserver1=85.199.214.99
754 02:29:59.245854 <6>[ 13.411963] clk: Disabling unused clocks
755 02:29:59.250350 <6>[ 13.416573] PM: genpd: Disabling unused power domains
756 02:29:59.270638 <6>[ 13.435829] Freeing unused kernel image (initmem) memory: 2048K
757 02:29:59.278105 <6>[ 13.445473] Run /init as init process
758 02:29:59.300259 Loading, please wait...
759 02:29:59.374618 Starting systemd-udevd version 252.22-1~deb12u1
760 02:30:02.369915 <4>[ 16.531209] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 02:30:02.576415 <4>[ 16.737755] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 02:30:02.746525 <6>[ 16.915415] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
763 02:30:02.757200 <6>[ 16.921244] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
764 02:30:02.890215 <6>[ 17.057318] hub 1-0:1.0: USB hub found
765 02:30:02.921615 <6>[ 17.088542] tda998x 0-0070: found TDA19988
766 02:30:02.932234 <6>[ 17.099316] hub 1-0:1.0: 1 port detected
767 02:30:05.860183 Begin: Loading essential drivers ... done.
768 02:30:05.865494 Begin: Running /scripts/init-premount ... done.
769 02:30:05.871190 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
770 02:30:05.881470 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
771 02:30:05.892231 Device /sys/class/net/eth0 found
772 02:30:05.892465 done.
773 02:30:05.950193 Begin: Waiting up to 180 secs for any network device to become available ... done.
774 02:30:06.021022 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
775 02:30:06.114176 IP-Config: eth0 complete (dhcp from 192.168.56.254):
776 02:30:06.125609 address: 192.168.56.2 broadcast: 192.168.56.255 netmask: 255.255.255.0
777 02:30:06.131233 gateway: 192.168.56.254 dns0 : 192.168.56.254 dns1 : 0.0.0.0
778 02:30:06.136607 domain : mayfield.sirena.org.uk
779 02:30:06.142453 rootserver: 192.168.56.254 rootpath:
780 02:30:06.142792 filename :
781 02:30:06.235042 done.
782 02:30:06.248398 Begin: Running /scripts/nfs-bottom ... done.
783 02:30:06.310487 Begin: Running /scripts/init-bottom ... done.
784 02:30:07.623954 <30>[ 21.788733] systemd[1]: System time before build time, advancing clock.
785 02:30:07.897304 <30>[ 22.035923] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
786 02:30:07.906705 <30>[ 22.073327] systemd[1]: Detected architecture arm.
787 02:30:07.918020
788 02:30:07.918212 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
789 02:30:07.918296
790 02:30:07.951137 <30>[ 22.116514] systemd[1]: Hostname set to <debian-bookworm-armhf>.
791 02:30:09.967569 <30>[ 24.132048] systemd[1]: Queued start job for default target graphical.target.
792 02:30:09.984331 <30>[ 24.146611] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
793 02:30:09.991933 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
794 02:30:10.024457 <30>[ 24.189138] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
795 02:30:10.036323 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
796 02:30:10.070852 <30>[ 24.232644] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
797 02:30:10.078166 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
798 02:30:10.115453 <30>[ 24.278513] systemd[1]: Created slice user.slice - User and Session Slice.
799 02:30:10.121206 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
800 02:30:10.158559 <30>[ 24.318961] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
801 02:30:10.171621 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
802 02:30:10.205621 <30>[ 24.368115] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
803 02:30:10.215792 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
804 02:30:10.255875 <30>[ 24.407776] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
805 02:30:10.262274 <30>[ 24.428250] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
806 02:30:10.270816 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
807 02:30:10.303204 <30>[ 24.468117] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
808 02:30:10.315122 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
809 02:30:10.345350 <30>[ 24.507456] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
810 02:30:10.352860 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
811 02:30:10.384631 <30>[ 24.547703] systemd[1]: Reached target paths.target - Path Units.
812 02:30:10.388842 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
813 02:30:10.424401 <30>[ 24.587417] systemd[1]: Reached target remote-fs.target - Remote File Systems.
814 02:30:10.431803 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
815 02:30:10.464272 <30>[ 24.627278] systemd[1]: Reached target slices.target - Slice Units.
816 02:30:10.469772 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
817 02:30:10.505851 <30>[ 24.668210] systemd[1]: Reached target swap.target - Swaps.
818 02:30:10.509838 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
819 02:30:10.546272 <30>[ 24.708248] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
820 02:30:10.554143 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
821 02:30:10.585466 <30>[ 24.748282] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
822 02:30:10.593765 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
823 02:30:10.682385 <30>[ 24.840421] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
824 02:30:10.694923 <30>[ 24.857844] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
825 02:30:10.703422 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
826 02:30:10.736212 <30>[ 24.900570] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
827 02:30:10.748761 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
828 02:30:10.788288 <30>[ 24.950551] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
829 02:30:10.796097 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
830 02:30:10.833656 <30>[ 24.995179] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
831 02:30:10.839226 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
832 02:30:10.876279 <30>[ 25.038877] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
833 02:30:10.884966 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
834 02:30:10.921712 <30>[ 25.078480] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
835 02:30:10.938321 <30>[ 25.095151] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
836 02:30:10.975422 <30>[ 25.139286] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
837 02:30:10.994062 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
838 02:30:11.055000 <30>[ 25.218529] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
839 02:30:11.070548 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
840 02:30:11.149417 <30>[ 25.311937] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
841 02:30:11.174393 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
842 02:30:11.243326 <30>[ 25.406568] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
843 02:30:11.260953 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
844 02:30:11.324669 <30>[ 25.488365] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
845 02:30:11.336456 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
846 02:30:11.370028 <30>[ 25.534217] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
847 02:30:11.403028 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
848 02:30:11.468982 <30>[ 25.631905] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
849 02:30:11.488098 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
850 02:30:11.555478 <30>[ 25.719262] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
851 02:30:11.587215 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
852 02:30:11.664432 <30>[ 25.827965] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
853 02:30:11.680818 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
854 02:30:11.702432 <28>[ 25.861170] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
855 02:30:11.719117 <28>[ 25.883166] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
856 02:30:11.766035 <30>[ 25.930204] systemd[1]: Starting systemd-journald.service - Journal Service...
857 02:30:11.784082 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
858 02:30:11.865038 <30>[ 26.028718] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
859 02:30:11.876926 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
860 02:30:11.965946 <30>[ 26.129676] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
861 02:30:12.003678 Starting [0;1;39msystemd-network-g… units from Kernel command line...
862 02:30:12.094936 <30>[ 26.258145] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
863 02:30:12.134326 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
864 02:30:12.196694 <30>[ 26.359950] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
865 02:30:12.256157 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
866 02:30:12.297221 <30>[ 26.462255] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
867 02:30:12.335255 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
868 02:30:12.373755 <30>[ 26.538447] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
869 02:30:12.403312 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
870 02:30:12.441137 <30>[ 26.603995] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
871 02:30:12.467221 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
872 02:30:12.615257 <30>[ 26.779961] systemd[1]: Started systemd-journald.service - Journal Service.
873 02:30:12.633835 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
874 02:30:12.684478 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
875 02:30:12.704466 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
876 02:30:12.724322 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
877 02:30:12.759867 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
878 02:30:12.805463 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
879 02:30:12.855233 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
880 02:30:12.894252 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
881 02:30:12.927752 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
882 02:30:12.966341 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
883 02:30:12.998586 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
884 02:30:13.043807 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
885 02:30:13.088775 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
886 02:30:13.165923 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
887 02:30:13.227970 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
888 02:30:13.318563 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
889 02:30:13.483425 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kerne<46>[ 27.641715] systemd-journald[163]: Received client request to flush runtime journal.
890 02:30:13.483663 l Configuration File System.
891 02:30:13.659503 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
892 02:30:13.706140 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
893 02:30:13.785913 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
894 02:30:14.084650 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
895 02:30:14.104860 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
896 02:30:14.144081 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
897 02:30:14.200990 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
898 02:30:14.779019 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
899 02:30:14.864177 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
900 02:30:15.555794 <5>[ 29.719656] cfg80211: Loading compiled-in X.509 certificates for regulatory database
901 02:30:15.925194 <5>[ 30.091098] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
902 02:30:15.987428 <5>[ 30.149076] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
903 02:30:15.993100 <4>[ 30.158768] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
904 02:30:16.000777 <6>[ 30.167857] cfg80211: failed to load regulatory.db
905 02:30:16.936568 [[0m[0;31m* [0m] (1 of 5) Job systemd-udev-trigger.s…vice/start running (6s / no limit)
906 02:30:17.382601 M
[K[[0;1;31m*[0m[0;31m* [0m] (1 of 5) Job systemd-udev-trigger.s…vice/start running (7s / no limit)
907 02:30:17.616838 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
908 02:30:17.997321 [K[[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
909 02:30:18.610422 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
910 02:30:18.657335 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
911 02:30:20.827645 [[0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (10s / 1min 33s)
912 02:30:21.267470 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (11s / 1min 33s)
913 02:30:21.651041 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (11s / 1min 33s)
914 02:30:22.054287 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job systemd-journal-flush.service/start running (12s / 1min 33s)
915 02:30:22.502795 M
[K[ [0;31m*[0;1;31m*[0m] Job systemd-journal-flush.service/start running (12s / 1min 33s)
916 02:30:23.000858 M
[K[ [0;31m*[0m] Job systemd-journal-flush.service/start running (12s / 1min 33s)
917 02:30:23.370903 M
[K[ [0;31m*[0;1;31m*[0m] Job systemd-journal-flush.service/start running (13s / 1min 33s)
918 02:30:23.820139 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job systemd-journal-flush.service/start running (13s / 1min 33s)
919 02:30:24.344992 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (14s / 1min 33s)
920 02:30:24.771398 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (14s / 1min 33s)
921 02:30:25.261233 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (15s / 1min 33s)
922 02:30:25.716701 M
[K[[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (15s / 1min 33s)
923 02:30:26.149535 M
[K[[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (16s / 1min 33s)
924 02:30:26.495947 M
[K[[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (16s / 1min 33s)
925 02:30:26.843648 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (16s / 1min 33s)
926 02:30:27.187830 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (17s / 1min 33s)
927 02:30:27.530840 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-journal-flush.service/start running (17s / 1min 33s)
928 02:30:27.875218 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job systemd-journal-flush.service/start running (17s / 1min 33s)
929 02:30:28.194479 M
[K[[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
930 02:30:28.226162 [K[[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
931 02:30:28.255919 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
932 02:30:28.326427 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
933 02:30:28.356968 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
934 02:30:28.407000 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
935 02:30:28.433865 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
936 02:30:28.471671 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
937 02:30:28.505428 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
938 02:30:28.541723 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
939 02:30:28.578206 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
940 02:30:30.872676 [ [0;31m*[0;1;31m*[0m] Job systemd-journal-flush.service/start running (2s / 1min 14s)
941 02:30:31.455731 M
[K[ [0;31m*[0m] Job systemd-journal-flush.service/start running (3s / 1min 14s)
942 02:30:32.038991 M
[K[ [0;31m*[0;1;31m*[0m] Job systemd-journal-flush.service/start running (3s / 1min 14s)
943 02:30:32.624322 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job systemd-journal-flush.service/start running (4s / 1min 14s)
944 02:30:32.923695 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
945 02:30:32.993841 [K Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
946 02:30:35.260221 [ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-tmpfiles-setup.service/start running (7s / no limit)
947 02:30:35.844867 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-tmpfiles-setup.service/start running (7s / no limit)
948 02:30:36.427866 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-tmpfiles-setup.service/start running (8s / no limit)
949 02:30:37.010512 M
[K[[0;1;31m*[0m[0;31m* [0m] Job systemd-tmpfiles-setup.service/start running (8s / no limit)
950 02:30:37.593184 M
[K[[0m[0;31m* [0m] Job systemd-tmpfiles-setup.service/start running (9s / no limit)
951 02:30:38.177179 M
[K[[0;1;31m*[0m[0;31m* [0m] Job systemd-tmpfiles-setup.service/start running (9s / no limit)
952 02:30:38.761767 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-tmpfiles-setup.service/start running (10s / no limit)
953 02:30:39.345164 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-tmpfiles-setup.service/start running (11s / no limit)
954 02:30:39.928433 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-tmpfiles-setup.service/start running (11s / no limit)
955 02:30:40.511755 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job systemd-tmpfiles-setup.service/start running (12s / no limit)
956 02:30:41.094407 M
[K[ [0;31m*[0;1;31m*[0m] Job systemd-tmpfiles-setup.service/start running (12s / no limit)
957 02:30:41.677878 M
[K[ [0;31m*[0m] Job systemd-tmpfiles-setup.service/start running (13s / no limit)
958 02:30:42.261611 M
[K[ [0;31m*[0;1;31m*[0m] Job systemd-tmpfiles-setup.service/start running (14s / no limit)
959 02:30:42.334393 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
960 02:30:47.398155 [K Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
961 02:30:47.476510 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
962 02:30:47.730558 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
963 02:30:49.878881 [ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job systemd-timesyncd.service/start running (21s / 1min 49s)
964 02:30:50.379988 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-timesyncd.service/start running (22s / 1min 49s)
965 02:30:50.880352 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-timesyncd.service/start running (22s / 1min 49s)
966 02:30:51.379614 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-timesyncd.service/start running (23s / 1min 49s)
967 02:30:51.880274 M
[K[[0;1;31m*[0m[0;31m* [0m] Job systemd-timesyncd.service/start running (23s / 1min 49s)
968 02:30:52.378897 M
[K[[0m[0;31m* [0m] Job systemd-timesyncd.service/start running (24s / 1min 49s)
969 02:30:52.879876 M
[K[[0;1;31m*[0m[0;31m* [0m] Job systemd-timesyncd.service/start running (24s / 1min 49s)
970 02:30:53.380019 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-timesyncd.service/start running (25s / 1min 49s)
971 02:30:53.775926 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-timesyncd.service/start running (25s / 1min 49s)
972 02:30:54.129689 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job systemd-timesyncd.service/start running (25s / 1min 49s)
973 02:30:54.167682 M
[K[[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
974 02:30:54.205485 [K[[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
975 02:30:54.248097 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
976 02:30:54.281703 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
977 02:30:56.343232 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
978 02:30:56.509706 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
979 02:30:56.545465 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
980 02:30:56.651277 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
981 02:30:56.765693 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
982 02:30:56.802184 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
983 02:30:56.845732 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
984 02:30:56.881338 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
985 02:30:56.916365 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
986 02:30:56.997587 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
987 02:30:57.041354 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
988 02:30:57.342412 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
989 02:30:57.843074 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
990 02:30:57.899184 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
991 02:30:57.953131 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
992 02:30:57.983182 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
993 02:30:58.099804 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
994 02:30:58.187577 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
995 02:30:58.282197 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
996 02:30:58.357287 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
997 02:30:58.392371 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
998 02:30:58.831356 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
999 02:30:58.876807 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1000 02:30:58.934364 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1001 02:30:58.991982 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1002 02:30:59.031299 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1003 02:30:59.119211 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1004 02:31:00.110561 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1005 02:31:00.722508 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
1006 02:31:01.513214
1007 02:31:01.516886 Debian GNU/Linux 12 de�kworm-armhf login: root (automatic login)
1008 02:31:01.517123
1009 02:31:02.596561 Linux debian-bookworm-armhf 6.11.0-rc5 #1 SMP Fri Aug 30 02:02:35 UTC 2024 armv7l
1010 02:31:02.609256
1011 02:31:02.614540 The programs included with the Debian GNU/Linux system are free software;
1012 02:31:02.620245 the exact distribution terms for each program are described in the
1013 02:31:02.625858 individual files in /usr/share/doc/*/copyright.
1014 02:31:02.626084
1015 02:31:02.632188 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1016 02:31:02.632447 permitted by applicable law.
1017 02:31:07.401697 <46>[ 81.558366] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1018 02:31:07.418324 <46>[ 81.578297] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
1019 02:31:14.342737 Unable to match end of the kernel message
1021 02:31:14.343358 Setting prompt string to ['/ #']
1022 02:31:14.343560 end: 2.4.4.1 login-action (duration 00:01:29) [common]
1024 02:31:14.343956 end: 2.4.4 auto-login-action (duration 00:01:30) [common]
1025 02:31:14.344153 start: 2.4.5 expect-shell-connection (timeout 00:02:29) [common]
1026 02:31:14.344327 Setting prompt string to ['/ #']
1027 02:31:14.344452 Forcing a shell prompt, looking for ['/ #']
1029 02:31:14.394848 / #
1030 02:31:14.395184 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1031 02:31:14.395359 Waiting using forced prompt support (timeout 00:02:30)
1032 02:31:14.399752
1033 02:31:14.402552 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1034 02:31:14.402811 start: 2.4.6 export-device-env (timeout 00:02:29) [common]
1035 02:31:14.402988 Sending with 10 millisecond of delay
1037 02:31:19.394169 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/675320/extract-nfsrootfs-86biawjy'
1038 02:31:19.404743 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/675320/extract-nfsrootfs-86biawjy'
1039 02:31:19.405255 Sending with 10 millisecond of delay
1041 02:31:21.625106 / # export NFS_SERVER_IP='192.168.56.76'
1042 02:31:21.635731 export NFS_SERVER_IP='192.168.56.76'
1043 02:31:21.636936 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1044 02:31:21.637193 end: 2.4 uboot-commands (duration 00:02:38) [common]
1045 02:31:21.637467 end: 2 uboot-action (duration 00:02:38) [common]
1046 02:31:21.637778 start: 3 lava-test-retry (timeout 00:06:36) [common]
1047 02:31:21.638193 start: 3.1 lava-test-shell (timeout 00:06:36) [common]
1048 02:31:21.638487 Using namespace: common
1050 02:31:21.739228 / # #
1051 02:31:21.739585 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1052 02:31:21.744383 #
1053 02:31:21.750219 Using /lava-675320
1055 02:31:21.851110 / # export SHELL=/bin/bash
1056 02:31:21.856325 export SHELL=/bin/bash
1058 02:31:21.962390 / # . /lava-675320/environment
1059 02:31:21.967516 . /lava-675320/environment
1061 02:31:22.083025 / # /lava-675320/bin/lava-test-runner /lava-675320/0
1062 02:31:22.083536 Test shell timeout: 10s (minimum of the action and connection timeout)
1063 02:31:22.087110 /lava-675320/bin/lava-test-runner /lava-675320/0
1064 02:31:22.956487 + export TESTRUN_ID=0_timesync-off
1065 02:31:22.963734 + TESTRUN_ID=0_timesync-off
1066 02:31:22.964166 + cd /lava-675320/0/tests/0_timesync-off
1067 02:31:22.964421 ++ cat uuid
1068 02:31:22.995380 + UUID=675320_1.6.2.4.1
1069 02:31:22.995670 + set +x
1070 02:31:23.003808 <LAVA_SIGNAL_STARTRUN 0_timesync-off 675320_1.6.2.4.1>
1071 02:31:23.004148 + systemctl stop systemd-timesyncd
1072 02:31:23.004651 Received signal: <STARTRUN> 0_timesync-off 675320_1.6.2.4.1
1073 02:31:23.004929 Starting test lava.0_timesync-off (675320_1.6.2.4.1)
1074 02:31:23.005247 Skipping test definition patterns.
1075 02:31:23.772797 + set +x
1076 02:31:23.773166 <LAVA_SIGNAL_ENDRUN 0_timesync-off 675320_1.6.2.4.1>
1077 02:31:23.773566 Received signal: <ENDRUN> 0_timesync-off 675320_1.6.2.4.1
1078 02:31:23.773777 Ending use of test pattern.
1079 02:31:23.773963 Ending test lava.0_timesync-off (675320_1.6.2.4.1), duration 0.77
1081 02:31:24.859851 + export TESTRUN_ID=1_kselftest-dt
1082 02:31:24.867865 + TESTRUN_ID=1_kselftest-dt
1083 02:31:24.868233 + cd /lava-675320/0/tests/1_kselftest-dt
1084 02:31:24.868493 ++ cat uuid
1085 02:31:24.954376 + UUID=675320_1.6.2.4.5
1086 02:31:24.954673 + set +x
1087 02:31:24.960474 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 675320_1.6.2.4.5>
1088 02:31:24.960658 + cd ./automated/linux/kselftest/
1089 02:31:24.961015 Received signal: <STARTRUN> 1_kselftest-dt 675320_1.6.2.4.5
1090 02:31:24.961180 Starting test lava.1_kselftest-dt (675320_1.6.2.4.5)
1091 02:31:24.961367 Skipping test definition patterns.
1092 02:31:24.985696 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1093 02:31:25.428350 INFO: install_deps skipped
1094 02:31:26.759517 --2024-08-30 02:31:26-- http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1095 02:31:26.803777 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1096 02:31:26.941237 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1097 02:31:27.078623 HTTP request sent, awaiting response... 200 OK
1098 02:31:27.078993 Length: 3605944 (3.4M) [application/octet-stream]
1099 02:31:27.084304 Saving to: 'kselftest_armhf.tar.gz'
1100 02:31:27.084523
1101 02:31:28.514559
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 187KB/s
kselftest_armhf.tar 5%[> ] 194.76K 359KB/s
kselftest_armhf.tar 22%[===> ] 792.85K 988KB/s
kselftest_armhf.tar 37%[======> ] 1.29M 1.29MB/s
kselftest_armhf.tar 56%[==========> ] 1.94M 1.50MB/s
kselftest_armhf.tar 100%[===================>] 3.44M 2.41MB/s in 1.4s
1102 02:31:28.514918
1103 02:31:31.476923 2024-08-30 02:31:28 (2.41 MB/s) - 'kselftest_armhf.tar.gz' saved [3605944/3605944]
1104 02:31:31.477246
1105 02:35:27.231870 skiplist:
1106 02:35:27.232198 ========================================
1107 02:35:27.237634 ========================================
1108 02:35:27.472046 dt:test_unprobed_devices.sh
1109 02:35:27.584911 ============== Tests to run ===============
1110 02:35:27.596112 dt:test_unprobed_devices.sh
1111 02:35:27.599051 ===========End Tests to run ===============
1112 02:35:27.625093 shardfile-dt pass
1113 02:35:28.023421 <12>[ 342.201755] kselftest: Running tests in dt
1114 02:35:28.058396 TAP version 13
1115 02:35:28.112592 1..1
1116 02:35:28.168920 # timeout set to 45
1117 02:35:28.169237 # selftests: dt: test_unprobed_devices.sh
1118 02:35:29.187895 # TAP version 13
1119 02:35:40.905533 # 1..255
1120 02:35:41.070026 # ok 1 / # SKIP
1121 02:35:41.090673 # ok 2 /clk_mcasp0
1122 02:35:41.159950 # ok 3 /clk_mcasp0_fixed # SKIP
1123 02:35:41.229215 # ok 4 /cpus/cpu@0 # SKIP
1124 02:35:41.299774 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1125 02:35:41.319386 # ok 6 /fixedregulator0
1126 02:35:41.339211 # ok 7 /leds
1127 02:35:41.363467 # ok 8 /ocp
1128 02:35:41.382149 # ok 9 /ocp/interconnect@44c00000
1129 02:35:41.407739 # ok 10 /ocp/interconnect@44c00000/segment@0
1130 02:35:41.428543 # ok 11 /ocp/interconnect@44c00000/segment@100000
1131 02:35:41.459098 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1132 02:35:41.520931 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1133 02:35:41.546998 # ok 14 /ocp/interconnect@44c00000/segment@200000
1134 02:35:41.563213 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1135 02:35:41.663270 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1136 02:35:41.738142 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1137 02:35:41.805705 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1138 02:35:41.875653 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1139 02:35:41.945978 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1140 02:35:42.015587 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1141 02:35:42.085604 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1142 02:35:42.152232 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1143 02:35:42.225339 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1144 02:35:42.290861 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1145 02:35:42.359892 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1146 02:35:42.422136 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1147 02:35:42.495863 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1148 02:35:42.563904 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1149 02:35:42.634704 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1150 02:35:42.697562 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1151 02:35:42.771744 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1152 02:35:42.834890 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1153 02:35:42.910377 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1154 02:35:42.975870 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1155 02:35:43.039698 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1156 02:35:43.115494 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1157 02:35:43.177479 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1158 02:35:43.252648 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1159 02:35:43.313410 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1160 02:35:43.391142 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1161 02:35:43.459352 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1162 02:35:43.532886 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1163 02:35:43.601290 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1164 02:35:43.663644 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1165 02:35:43.736936 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1166 02:35:43.798178 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1167 02:35:43.872633 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1168 02:35:43.941888 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1169 02:35:44.011158 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1170 02:35:44.077064 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1171 02:35:44.146974 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1172 02:35:44.216902 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1173 02:35:44.279949 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1174 02:35:44.356431 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1175 02:35:44.417515 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1176 02:35:44.493639 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1177 02:35:44.563553 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1178 02:35:44.632025 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1179 02:35:44.704452 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1180 02:35:44.765824 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1181 02:35:44.843668 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1182 02:35:44.911772 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1183 02:35:44.984389 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1184 02:35:45.045561 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1185 02:35:45.122985 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1186 02:35:45.192791 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1187 02:35:45.263696 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1188 02:35:45.330015 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1189 02:35:45.406911 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1190 02:35:45.474575 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1191 02:35:45.543323 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1192 02:35:45.619026 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1193 02:35:45.690355 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1194 02:35:45.761322 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1195 02:35:45.831289 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1196 02:35:45.900500 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1197 02:35:45.963292 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1198 02:35:46.040504 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1199 02:35:46.106387 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1200 02:35:46.176890 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1201 02:35:46.245148 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1202 02:35:46.314286 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1203 02:35:46.384606 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1204 02:35:46.453346 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1205 02:35:46.526291 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1206 02:35:46.599599 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1207 02:35:46.669469 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1208 02:35:46.739450 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1209 02:35:46.812082 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1210 02:35:46.876641 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1211 02:35:46.949330 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1212 02:35:47.021159 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1213 02:35:47.085306 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1214 02:35:47.110141 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1215 02:35:47.127028 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1216 02:35:47.151737 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1217 02:35:47.179736 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1218 02:35:47.203963 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1219 02:35:47.221917 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1220 02:35:47.242433 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1221 02:35:47.271630 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1222 02:35:47.367665 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1223 02:35:47.397361 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1224 02:35:47.423558 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1225 02:35:47.439526 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1226 02:35:47.542654 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1227 02:35:47.617638 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1228 02:35:47.695873 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1229 02:35:47.767617 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1230 02:35:47.842254 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1231 02:35:47.912525 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1232 02:35:47.981458 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1233 02:35:48.053936 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1234 02:35:48.123926 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1235 02:35:48.187272 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1236 02:35:48.264678 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1237 02:35:48.328273 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1238 02:35:48.402772 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1239 02:35:48.468427 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1240 02:35:48.545125 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1241 02:35:48.615250 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1242 02:35:48.635781 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1243 02:35:48.698918 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1244 02:35:48.769745 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1245 02:35:48.840686 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1246 02:35:48.861803 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1247 02:35:48.926178 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1248 02:35:48.951400 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1249 02:35:49.021492 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1250 02:35:49.049432 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1251 02:35:49.071430 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1252 02:35:49.089000 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1253 02:35:49.120579 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1254 02:35:49.134588 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1255 02:35:49.162021 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1256 02:35:49.183763 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1257 02:35:49.212335 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1258 02:35:49.228944 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1259 02:35:49.305240 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1260 02:35:49.367827 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1261 02:35:49.392208 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1262 02:35:49.461122 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1263 02:35:49.531627 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1264 02:35:49.626262 # not ok 145 /ocp/interconnect@47c00000
1265 02:35:49.695684 # not ok 146 /ocp/interconnect@47c00000/segment@0
1266 02:35:49.722951 # ok 147 /ocp/interconnect@48000000
1267 02:35:49.746720 # ok 148 /ocp/interconnect@48000000/segment@0
1268 02:35:49.764370 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1269 02:35:49.787414 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1270 02:35:49.814952 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1271 02:35:49.839459 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1272 02:35:49.855051 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1273 02:35:49.878959 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1274 02:35:49.907835 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1275 02:35:49.971286 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1276 02:35:50.040272 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1277 02:35:50.067582 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1278 02:35:50.084799 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1279 02:35:50.106033 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1280 02:35:50.136616 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1281 02:35:50.156469 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1282 02:35:50.175879 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1283 02:35:50.199417 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1284 02:35:50.226926 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1285 02:35:50.249436 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1286 02:35:50.268309 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1287 02:35:50.294153 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1288 02:35:50.313000 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1289 02:35:50.335097 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1290 02:35:50.363157 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1291 02:35:50.386723 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1292 02:35:50.409652 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1293 02:35:50.429423 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1294 02:35:50.454669 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1295 02:35:50.477485 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1296 02:35:50.500974 # ok 177 /ocp/interconnect@48000000/segment@100000
1297 02:35:50.516369 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1298 02:35:50.547441 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1299 02:35:50.613157 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1300 02:35:50.685814 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1301 02:35:50.755304 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1302 02:35:50.815552 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1303 02:35:50.842999 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1304 02:35:50.857002 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1305 02:35:50.889148 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1306 02:35:50.904765 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1307 02:35:50.932265 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1308 02:35:50.950643 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1309 02:35:50.978275 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1310 02:35:51.003364 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1311 02:35:51.018092 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1312 02:35:51.048229 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1313 02:35:51.062242 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1314 02:35:51.091666 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1315 02:35:51.108593 # ok 196 /ocp/interconnect@48000000/segment@200000
1316 02:35:51.132237 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1317 02:35:51.205405 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1318 02:35:51.227353 # ok 199 /ocp/interconnect@48000000/segment@300000
1319 02:35:51.243696 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1320 02:35:51.266730 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1321 02:35:51.294159 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1322 02:35:51.317851 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1323 02:35:51.338417 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1324 02:35:51.359441 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1325 02:35:51.428235 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1326 02:35:51.445579 # ok 207 /ocp/interconnect@4a000000
1327 02:35:51.467208 # ok 208 /ocp/interconnect@4a000000/segment@0
1328 02:35:51.489285 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1329 02:35:51.515785 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1330 02:35:51.541143 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1331 02:35:51.555302 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1332 02:35:51.630314 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1333 02:35:51.722811 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1334 02:35:51.796183 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1335 02:35:51.892836 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1336 02:35:51.964313 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1337 02:35:52.034731 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1338 02:35:52.129331 # not ok 219 /ocp/interconnect@4b140000
1339 02:35:52.189893 # not ok 220 /ocp/interconnect@4b140000/segment@0
1340 02:35:52.259566 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1341 02:35:52.278127 # ok 222 /ocp/target-module@40300000
1342 02:35:52.304192 # ok 223 /ocp/target-module@40300000/sram@0
1343 02:35:52.375744 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1344 02:35:52.445550 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1345 02:35:52.467215 # ok 226 /ocp/target-module@47400000
1346 02:35:52.488475 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1347 02:35:52.507744 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1348 02:35:52.529654 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1349 02:35:52.555001 # ok 230 /ocp/target-module@47400000/usb@1400
1350 02:35:52.576832 # ok 231 /ocp/target-module@47400000/usb@1800
1351 02:35:52.599461 # ok 232 /ocp/target-module@47810000
1352 02:35:52.613430 # ok 233 /ocp/target-module@49000000
1353 02:35:52.635035 # ok 234 /ocp/target-module@49000000/dma@0
1354 02:35:52.661310 # ok 235 /ocp/target-module@49800000
1355 02:35:52.683937 # ok 236 /ocp/target-module@49800000/dma@0
1356 02:35:52.703399 # ok 237 /ocp/target-module@49900000
1357 02:35:52.726295 # ok 238 /ocp/target-module@49900000/dma@0
1358 02:35:52.746713 # ok 239 /ocp/target-module@49a00000
1359 02:35:52.766943 # ok 240 /ocp/target-module@49a00000/dma@0
1360 02:35:52.787799 # ok 241 /ocp/target-module@4c000000
1361 02:35:52.856952 # not ok 242 /ocp/target-module@4c000000/emif@0
1362 02:35:52.882268 # ok 243 /ocp/target-module@50000000
1363 02:35:52.902462 # ok 244 /ocp/target-module@53100000
1364 02:35:52.968868 # not ok 245 /ocp/target-module@53100000/sham@0
1365 02:35:52.994557 # ok 246 /ocp/target-module@53500000
1366 02:35:53.059306 # not ok 247 /ocp/target-module@53500000/aes@0
1367 02:35:53.078818 # ok 248 /ocp/target-module@56000000
1368 02:35:53.177035 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1369 02:35:53.246144 # ok 250 /opp-table # SKIP
1370 02:35:53.313504 # ok 251 /soc # SKIP
1371 02:35:53.330342 # ok 252 /sound
1372 02:35:53.351906 # ok 253 /target-module@4b000000
1373 02:35:53.377327 # ok 254 /target-module@4b000000/target-module@140000
1374 02:35:53.396760 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1375 02:35:53.405997 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1376 02:35:53.411557 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1377 02:35:55.804984 dt_test_unprobed_devices_sh_ skip
1378 02:35:55.810496 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1379 02:35:55.816106 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1380 02:35:55.816394 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1381 02:35:55.825241 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1382 02:35:55.825494 dt_test_unprobed_devices_sh_fixedregulator0 pass
1383 02:35:55.830773 dt_test_unprobed_devices_sh_leds pass
1384 02:35:55.836598 dt_test_unprobed_devices_sh_ocp pass
1385 02:35:55.836824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1386 02:35:55.845564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1387 02:35:55.851302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1388 02:35:55.860066 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1389 02:35:55.865894 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1390 02:35:55.876835 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1391 02:35:55.880190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1392 02:35:55.891370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1393 02:35:55.902627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1394 02:35:55.908330 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1395 02:35:55.919507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1396 02:35:55.930738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1397 02:35:55.942083 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1398 02:35:55.953160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1399 02:35:55.959059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1400 02:35:55.969840 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1401 02:35:55.981145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1402 02:35:55.992358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1403 02:35:56.003550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1404 02:35:56.009144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1405 02:35:56.020282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1406 02:35:56.031462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1407 02:35:56.042573 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1408 02:35:56.048143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1409 02:35:56.059439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1410 02:35:56.070549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1411 02:35:56.081663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1412 02:35:56.087481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1413 02:35:56.098494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1414 02:35:56.109602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1415 02:35:56.120859 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1416 02:35:56.132164 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1417 02:35:56.143857 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1418 02:35:56.154708 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1419 02:35:56.166051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1420 02:35:56.176969 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1421 02:35:56.188429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1422 02:35:56.199294 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1423 02:35:56.210389 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1424 02:35:56.221632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1425 02:35:56.232887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1426 02:35:56.244015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1427 02:35:56.255239 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1428 02:35:56.266357 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1429 02:35:56.277528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1430 02:35:56.288763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1431 02:35:56.300296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1432 02:35:56.311591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1433 02:35:56.322409 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1434 02:35:56.333643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1435 02:35:56.344839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1436 02:35:56.355921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1437 02:35:56.361702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1438 02:35:56.372654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1439 02:35:56.383877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1440 02:35:56.395041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1441 02:35:56.406291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1442 02:35:56.417433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1443 02:35:56.428754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1444 02:35:56.439951 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1445 02:35:56.451137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1446 02:35:56.462464 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1447 02:35:56.473623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1448 02:35:56.484730 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1449 02:35:56.495751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1450 02:35:56.506958 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1451 02:35:56.512583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1452 02:35:56.523713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1453 02:35:56.534895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1454 02:35:56.546092 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1455 02:35:56.557228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1456 02:35:56.568524 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1457 02:35:56.579668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1458 02:35:56.591228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1459 02:35:56.602128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1460 02:35:56.613324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1461 02:35:56.624804 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1462 02:35:56.630121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1463 02:35:56.641183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1464 02:35:56.652394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1465 02:35:56.663602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1466 02:35:56.674827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1467 02:35:56.686032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1468 02:35:56.697208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1469 02:35:56.708330 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1470 02:35:56.719584 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1471 02:35:56.731073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1472 02:35:56.742013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1473 02:35:56.747696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1474 02:35:56.759130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1475 02:35:56.770019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1476 02:35:56.775582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1477 02:35:56.786815 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1478 02:35:56.792383 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1479 02:35:56.803531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1480 02:35:56.814677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1481 02:35:56.825899 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1482 02:35:56.831474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1483 02:35:56.842684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1484 02:35:56.853866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1485 02:35:56.865019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1486 02:35:56.876237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1487 02:35:56.893002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1488 02:35:56.904254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1489 02:35:56.915444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1490 02:35:56.926560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1491 02:35:56.937862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1492 02:35:56.948935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1493 02:35:56.960180 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1494 02:35:56.976982 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1495 02:35:56.988108 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1496 02:35:56.999324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1497 02:35:57.010533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1498 02:35:57.027314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1499 02:35:57.038502 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1500 02:35:57.049685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1501 02:35:57.055302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1502 02:35:57.066463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1503 02:35:57.072122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1504 02:35:57.083304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1505 02:35:57.088851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1506 02:35:57.100009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1507 02:35:57.105579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1508 02:35:57.116818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1509 02:35:57.122440 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1510 02:35:57.133654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1511 02:35:57.139243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1512 02:35:57.150744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1513 02:35:57.161616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1514 02:35:57.173074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1515 02:35:57.178396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1516 02:35:57.189691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1517 02:35:57.201019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1518 02:35:57.206394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1519 02:35:57.217569 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1520 02:35:57.228728 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1521 02:35:57.234427 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1522 02:35:57.240095 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1523 02:35:57.245542 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1524 02:35:57.251140 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1525 02:35:57.256723 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1526 02:35:57.267890 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1527 02:35:57.273461 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1528 02:35:57.279058 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1529 02:35:57.290724 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1530 02:35:57.296043 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1531 02:35:57.307097 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1532 02:35:57.312647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1533 02:35:57.323829 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1534 02:35:57.329478 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1535 02:35:57.340658 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1536 02:35:57.346274 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1537 02:35:57.357406 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1538 02:35:57.363025 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1539 02:35:57.368599 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1540 02:35:57.379991 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1541 02:35:57.385375 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1542 02:35:57.396637 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1543 02:35:57.402209 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1544 02:35:57.413579 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1545 02:35:57.419145 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1546 02:35:57.430134 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1547 02:35:57.435732 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1548 02:35:57.446958 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1549 02:35:57.452505 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1550 02:35:57.463719 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1551 02:35:57.469354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1552 02:35:57.480526 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1553 02:35:57.486191 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1554 02:35:57.491988 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1555 02:35:57.502924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1556 02:35:57.514098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1557 02:35:57.519788 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1558 02:35:57.530853 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1559 02:35:57.542054 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1560 02:35:57.553381 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1561 02:35:57.558865 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1562 02:35:57.570250 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1563 02:35:57.575693 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1564 02:35:57.581259 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1565 02:35:57.592413 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1566 02:35:57.603645 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1567 02:35:57.609386 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1568 02:35:57.620446 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1569 02:35:57.626022 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1570 02:35:57.637193 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1571 02:35:57.642821 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1572 02:35:57.648410 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1573 02:35:57.659661 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1574 02:35:57.665156 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1575 02:35:57.670844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1576 02:35:57.682028 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1577 02:35:57.687563 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1578 02:35:57.698791 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1579 02:35:57.704548 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1580 02:35:57.715743 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1581 02:35:57.721502 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1582 02:35:57.732496 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1583 02:35:57.738071 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1584 02:35:57.743698 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1585 02:35:57.749471 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1586 02:35:57.760417 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1587 02:35:57.771700 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1588 02:35:57.777517 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1589 02:35:57.788579 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1590 02:35:57.794115 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1591 02:35:57.805301 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1592 02:35:57.816466 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1593 02:35:57.827885 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1594 02:35:57.833294 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1595 02:35:57.838934 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1596 02:35:57.844685 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1597 02:35:57.855795 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1598 02:35:57.861249 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1599 02:35:57.866905 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1600 02:35:57.872442 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1601 02:35:57.878167 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1602 02:35:57.883760 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1603 02:35:57.889296 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1604 02:35:57.900529 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1605 02:35:57.906149 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1606 02:35:57.911753 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1607 02:35:57.917308 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1608 02:35:57.922990 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1609 02:35:57.928445 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1610 02:35:57.934093 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1611 02:35:57.939861 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1612 02:35:57.945436 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1613 02:35:57.951073 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1614 02:35:57.956803 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1615 02:35:57.962411 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1616 02:35:57.967928 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1617 02:35:57.973556 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1618 02:35:57.979229 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1619 02:35:57.984790 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1620 02:35:57.990475 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1621 02:35:57.995985 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1622 02:35:58.001612 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1623 02:35:58.007194 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1624 02:35:58.012723 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1625 02:35:58.018503 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1626 02:35:58.023942 dt_test_unprobed_devices_sh_opp-table skip
1627 02:35:58.024176 dt_test_unprobed_devices_sh_soc skip
1628 02:35:58.029571 dt_test_unprobed_devices_sh_sound pass
1629 02:35:58.035106 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1630 02:35:58.040707 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1631 02:35:58.046412 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1632 02:35:58.051948 dt_test_unprobed_devices_sh fail
1633 02:35:58.055203 + ../../utils/send-to-lava.sh ./output/result.txt
1634 02:35:58.074413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1635 02:35:58.074954 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1637 02:35:58.186245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1638 02:35:58.186755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1640 02:35:58.298653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1641 02:35:58.299131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1643 02:35:58.398458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1644 02:35:58.398954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1646 02:35:58.496781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1647 02:35:58.497292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1649 02:35:58.596555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1650 02:35:58.596969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1652 02:35:58.693261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1653 02:35:58.693766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1655 02:35:58.799690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1656 02:35:58.800184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1658 02:35:58.914876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1659 02:35:58.915310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1661 02:35:59.056231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1662 02:35:59.056788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1664 02:35:59.199078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1665 02:35:59.199613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1667 02:35:59.328101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1668 02:35:59.328658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1670 02:35:59.459940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1671 02:35:59.460438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1673 02:35:59.599005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1674 02:35:59.599513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1676 02:35:59.724985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1677 02:35:59.725492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1679 02:35:59.858564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1680 02:35:59.859053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1682 02:35:59.959494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1683 02:35:59.959983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1685 02:36:00.071230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1686 02:36:00.071734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1688 02:36:00.182008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1689 02:36:00.182509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1691 02:36:00.289340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1692 02:36:00.289857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1694 02:36:00.388256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1695 02:36:00.388804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1697 02:36:00.497479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1698 02:36:00.497993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1700 02:36:00.604042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1701 02:36:00.604564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1703 02:36:00.729646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1704 02:36:00.730165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1706 02:36:00.878853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1707 02:36:00.879394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1709 02:36:01.009740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1710 02:36:01.010278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1712 02:36:01.124316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1713 02:36:01.124798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1715 02:36:01.230168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1716 02:36:01.230669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1718 02:36:01.348662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1719 02:36:01.349165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1721 02:36:01.469147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1722 02:36:01.469646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1724 02:36:01.585212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1725 02:36:01.585716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1727 02:36:01.701058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1728 02:36:01.701555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1730 02:36:01.805609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1731 02:36:01.806196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1733 02:36:01.911601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1734 02:36:01.912097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1736 02:36:02.014805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1737 02:36:02.015307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1739 02:36:02.141108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1740 02:36:02.141584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1742 02:36:02.279070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1743 02:36:02.279560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1745 02:36:02.433292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1746 02:36:02.433806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1748 02:36:02.605135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1749 02:36:02.605637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1751 02:36:02.748355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1752 02:36:02.748837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1754 02:36:02.896295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1755 02:36:02.896788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1757 02:36:03.027846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1758 02:36:03.028375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1760 02:36:03.173079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1761 02:36:03.173630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1763 02:36:03.314786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1764 02:36:03.315312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1766 02:36:03.468272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1767 02:36:03.468743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1769 02:36:03.608813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1770 02:36:03.609278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1772 02:36:03.731094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1773 02:36:03.731600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1775 02:36:03.841185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1776 02:36:03.841679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1778 02:36:03.946260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1779 02:36:03.946749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1781 02:36:04.059942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1782 02:36:04.060452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1784 02:36:04.165971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1785 02:36:04.166467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1787 02:36:04.281889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1788 02:36:04.282414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1790 02:36:04.412751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1791 02:36:04.413243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1793 02:36:04.529627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1794 02:36:04.530167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1796 02:36:04.671652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1797 02:36:04.672153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1799 02:36:04.771090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1800 02:36:04.771589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1802 02:36:04.901747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1803 02:36:04.902259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1805 02:36:05.042411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1806 02:36:05.042910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1808 02:36:05.166933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1809 02:36:05.167542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1811 02:36:05.401677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1812 02:36:05.402227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1814 02:36:05.598115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1815 02:36:05.598650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1817 02:36:05.769395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1818 02:36:05.769933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1820 02:36:06.097908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1821 02:36:06.098459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1823 02:36:06.213475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1824 02:36:06.214033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1826 02:36:06.350820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1827 02:36:06.351352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1829 02:36:06.515083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1830 02:36:06.515557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1832 02:36:06.630210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1833 02:36:06.630697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1835 02:36:06.752021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1836 02:36:06.752527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1838 02:36:06.891781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1839 02:36:06.892291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1841 02:36:07.010373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1842 02:36:07.010860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1844 02:36:07.125924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1845 02:36:07.126410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1847 02:36:07.260546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1848 02:36:07.261028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1850 02:36:07.399976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1851 02:36:07.400479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1853 02:36:07.531533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1854 02:36:07.532029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1856 02:36:07.651586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1857 02:36:07.652084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1859 02:36:07.786426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1860 02:36:07.786914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1862 02:36:07.906360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1863 02:36:07.906845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1865 02:36:08.030496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1866 02:36:08.030994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1868 02:36:08.144666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1869 02:36:08.145167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1871 02:36:08.264006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1872 02:36:08.264531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1874 02:36:08.383593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1875 02:36:08.384109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1877 02:36:08.490755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1878 02:36:08.491261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1880 02:36:08.602326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1881 02:36:08.602829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1883 02:36:08.718760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1884 02:36:08.719275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1886 02:36:08.849888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1887 02:36:08.850396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1889 02:36:08.977509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1890 02:36:08.978069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1892 02:36:09.100187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1893 02:36:09.100687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1895 02:36:09.233138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1896 02:36:09.233657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1898 02:36:09.336313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1899 02:36:09.336820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1901 02:36:09.436345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1902 02:36:09.436857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1904 02:36:09.557068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1905 02:36:09.557576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1907 02:36:09.682032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1908 02:36:09.682531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1910 02:36:09.836048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1911 02:36:09.836556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1913 02:36:09.964504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1914 02:36:09.965019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1916 02:36:10.103888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1917 02:36:10.104427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1919 02:36:10.258646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1920 02:36:10.259150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1922 02:36:10.399180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1923 02:36:10.399768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1925 02:36:10.538408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1926 02:36:10.538939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1928 02:36:10.654872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1929 02:36:10.655422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1931 02:36:10.768971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1932 02:36:10.769428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1934 02:36:10.879048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1935 02:36:10.879550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1937 02:36:10.988540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1938 02:36:10.989037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1940 02:36:11.100644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1941 02:36:11.101160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1943 02:36:11.202077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1944 02:36:11.202583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1946 02:36:11.331718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1947 02:36:11.332195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1949 02:36:11.452604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1950 02:36:11.453095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1952 02:36:11.581140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1953 02:36:11.581641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1955 02:36:11.970314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1956 02:36:11.970731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1957 02:36:11.971151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1959 02:36:11.971664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1961 02:36:11.974061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1962 02:36:11.974571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1964 02:36:12.105364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1965 02:36:12.105863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1967 02:36:12.382743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1968 02:36:12.383213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1970 02:36:12.513850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1971 02:36:12.514406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1973 02:36:12.641739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1974 02:36:12.642332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1976 02:36:12.828866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1977 02:36:12.829388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1979 02:36:12.965433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1980 02:36:12.965979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1982 02:36:13.097402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1983 02:36:13.097981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1985 02:36:13.267533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1986 02:36:13.268080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1988 02:36:13.397717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1989 02:36:13.398286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1991 02:36:13.535008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1992 02:36:13.535641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1994 02:36:13.808823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1996 02:36:13.811989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1997 02:36:13.945294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1999 02:36:13.948352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2000 02:36:14.109357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2002 02:36:14.112668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2003 02:36:14.241031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2004 02:36:14.241521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2006 02:36:14.375282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2007 02:36:14.375770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2009 02:36:14.498034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2010 02:36:14.498514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2012 02:36:14.611598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2013 02:36:14.612075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2015 02:36:14.744244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2016 02:36:14.744728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2018 02:36:14.878069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2019 02:36:14.878550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2021 02:36:15.009743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2022 02:36:15.010237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2024 02:36:15.180032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2025 02:36:15.180521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2027 02:36:15.312372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2028 02:36:15.312858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2030 02:36:15.426105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2031 02:36:15.426605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2033 02:36:15.538494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2034 02:36:15.539010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2036 02:36:15.638708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2037 02:36:15.639214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2039 02:36:15.740895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2040 02:36:15.741438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2042 02:36:15.858111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2043 02:36:15.858725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2045 02:36:15.970539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2046 02:36:15.971018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2048 02:36:16.072522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2049 02:36:16.073024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2051 02:36:16.176684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2052 02:36:16.177188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2054 02:36:16.284899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2055 02:36:16.285394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2057 02:36:16.385877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2058 02:36:16.386409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2060 02:36:16.486930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2061 02:36:16.487425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2063 02:36:16.589384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2064 02:36:16.589847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2066 02:36:16.781760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2067 02:36:16.782292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2069 02:36:17.000693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2070 02:36:17.001138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2072 02:36:17.177741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2073 02:36:17.178174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2075 02:36:17.283680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2076 02:36:17.284120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2078 02:36:17.401492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2079 02:36:17.402112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2081 02:36:17.522909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2082 02:36:17.523343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2084 02:36:17.684933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2085 02:36:17.685383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2087 02:36:17.794987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2088 02:36:17.795436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2090 02:36:17.895964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2091 02:36:17.896448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2093 02:36:18.002878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2094 02:36:18.003326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2096 02:36:18.107445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2097 02:36:18.107888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2099 02:36:18.219780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2100 02:36:18.220258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2102 02:36:18.318581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2103 02:36:18.318918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2105 02:36:18.423343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2106 02:36:18.423833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2108 02:36:18.522711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2109 02:36:18.523204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2111 02:36:18.621555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2112 02:36:18.622064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2114 02:36:18.744761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2115 02:36:18.745246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2117 02:36:18.846323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2118 02:36:18.846818 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2120 02:36:18.957080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2121 02:36:18.957578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2123 02:36:19.071679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2124 02:36:19.072190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2126 02:36:19.179278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2127 02:36:19.179802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2129 02:36:19.290211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2130 02:36:19.290729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2132 02:36:19.393001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2133 02:36:19.393498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2135 02:36:19.498912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2136 02:36:19.499415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2138 02:36:19.605659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2139 02:36:19.606178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2141 02:36:19.719626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2142 02:36:19.720072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2144 02:36:19.820687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2145 02:36:19.821204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2147 02:36:19.919574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2148 02:36:19.920076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2150 02:36:20.029849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2151 02:36:20.030334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2153 02:36:20.129427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2154 02:36:20.129928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2156 02:36:20.236043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2157 02:36:20.236520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2159 02:36:20.332343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2160 02:36:20.332848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2162 02:36:20.435997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2163 02:36:20.436502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2165 02:36:20.536673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2166 02:36:20.537156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2168 02:36:20.642317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2169 02:36:20.642829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2171 02:36:20.752349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2172 02:36:20.752868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2174 02:36:20.853639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2175 02:36:20.854185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2177 02:36:20.962653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2178 02:36:20.963105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2180 02:36:21.067752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2181 02:36:21.068216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2183 02:36:21.168552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2184 02:36:21.169008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2186 02:36:21.280919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2187 02:36:21.281357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2189 02:36:21.441316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2190 02:36:21.441870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2192 02:36:21.607836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2193 02:36:21.608289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2195 02:36:21.706747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2196 02:36:21.707218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2198 02:36:21.806170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2199 02:36:21.806619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2201 02:36:21.922040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2202 02:36:21.922489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2204 02:36:22.028814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2205 02:36:22.029271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2207 02:36:22.135396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2208 02:36:22.135723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2210 02:36:22.238582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2211 02:36:22.238962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2213 02:36:22.343597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2214 02:36:22.344158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2216 02:36:22.448606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2217 02:36:22.449019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2219 02:36:22.551244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2220 02:36:22.551726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2222 02:36:22.647420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2223 02:36:22.647915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2225 02:36:22.759021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2226 02:36:22.759542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2228 02:36:22.859287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2229 02:36:22.859771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2231 02:36:22.961870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2232 02:36:22.962380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2234 02:36:23.072724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2235 02:36:23.073215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2237 02:36:23.174345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2238 02:36:23.174857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2240 02:36:23.283129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2241 02:36:23.283619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2243 02:36:23.382425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2244 02:36:23.382932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2246 02:36:23.482577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2247 02:36:23.483067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2249 02:36:23.591545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2250 02:36:23.592029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2252 02:36:23.693593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2253 02:36:23.694138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2255 02:36:23.793333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2256 02:36:23.793891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2258 02:36:23.897033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2259 02:36:23.897509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2261 02:36:23.998580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2262 02:36:23.999104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2264 02:36:24.110305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2265 02:36:24.110795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2267 02:36:24.209222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2268 02:36:24.209744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2270 02:36:24.318593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2271 02:36:24.319178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2273 02:36:24.422080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2274 02:36:24.422582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2276 02:36:24.537251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2277 02:36:24.537748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2279 02:36:24.641742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2280 02:36:24.642365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2282 02:36:24.739688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2283 02:36:24.740199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2285 02:36:24.841273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2286 02:36:24.841876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2288 02:36:24.982242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2289 02:36:24.982765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2291 02:36:25.091343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2292 02:36:25.091869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2294 02:36:25.196326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2295 02:36:25.196845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2297 02:36:25.304154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2298 02:36:25.304673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2300 02:36:25.402155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2301 02:36:25.402695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2303 02:36:25.501361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2304 02:36:25.501870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2306 02:36:25.609221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2307 02:36:25.609709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2309 02:36:25.708194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2311 02:36:25.711314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2312 02:36:25.812462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2313 02:36:25.812988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2315 02:36:25.923661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2316 02:36:25.924184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2318 02:36:26.024437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2319 02:36:26.024946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2321 02:36:26.129887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2322 02:36:26.130399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2324 02:36:26.233204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2325 02:36:26.233752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2327 02:36:26.330330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2328 02:36:26.330851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2330 02:36:26.439221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2331 02:36:26.439694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2333 02:36:26.537518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2334 02:36:26.538060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2336 02:36:26.638782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2337 02:36:26.639277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2339 02:36:26.743382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2340 02:36:26.743862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2342 02:36:26.845022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2343 02:36:26.845502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2345 02:36:26.949751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2346 02:36:26.950266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2348 02:36:27.055550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2349 02:36:27.056056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2351 02:36:27.159102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2352 02:36:27.159601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2354 02:36:27.266512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2355 02:36:27.267015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2357 02:36:27.368030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2358 02:36:27.368529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2360 02:36:27.472124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2361 02:36:27.472636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2363 02:36:27.583929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2364 02:36:27.584455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2366 02:36:27.693247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2367 02:36:27.693775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2369 02:36:27.807789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2370 02:36:27.808283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2372 02:36:27.919111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2373 02:36:27.919618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2375 02:36:28.035935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2376 02:36:28.036452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2378 02:36:28.153737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2379 02:36:28.154312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2381 02:36:28.254775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2382 02:36:28.255287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2384 02:36:28.354558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2385 02:36:28.355049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2387 02:36:28.456194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2388 02:36:28.456686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2390 02:36:28.561105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2391 02:36:28.561622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2393 02:36:28.662893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2394 02:36:28.663387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2396 02:36:28.766112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2397 02:36:28.766650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2399 02:36:28.867274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2400 02:36:28.867747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2402 02:36:28.970318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2403 02:36:28.970614 + set +x
2404 02:36:28.970986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2406 02:36:28.974514 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 675320_1.6.2.4.5>
2407 02:36:28.974959 Received signal: <ENDRUN> 1_kselftest-dt 675320_1.6.2.4.5
2408 02:36:28.975157 Ending use of test pattern.
2409 02:36:28.975314 Ending test lava.1_kselftest-dt (675320_1.6.2.4.5), duration 304.01
2411 02:36:28.985646 <LAVA_TEST_RUNNER EXIT>
2412 02:36:28.986128 ok: lava_test_shell seems to have completed
2413 02:36:28.990084 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2414 02:36:28.990925 end: 3.1 lava-test-shell (duration 00:05:07) [common]
2415 02:36:28.991171 end: 3 lava-test-retry (duration 00:05:07) [common]
2416 02:36:28.991402 start: 4 finalize (timeout 00:01:29) [common]
2417 02:36:28.991634 start: 4.1 power-off (timeout 00:00:30) [common]
2418 02:36:28.992005 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2419 02:36:29.021320 >> OK - accepted request
2420 02:36:29.022240 Returned 0 in 0 seconds
2421 02:36:29.122879 end: 4.1 power-off (duration 00:00:00) [common]
2423 02:36:29.123698 start: 4.2 read-feedback (timeout 00:01:29) [common]
2424 02:36:29.124224 Listened to connection for namespace 'common' for up to 1s
2425 02:36:29.124716 Listened to connection for namespace 'common' for up to 1s
2426 02:36:30.125130 Finalising connection for namespace 'common'
2427 02:36:30.125475 Disconnecting from shell: Finalise
2428 02:36:30.125730 / #
2429 02:36:30.226336 end: 4.2 read-feedback (duration 00:00:01) [common]
2430 02:36:30.226734 end: 4 finalize (duration 00:00:01) [common]
2431 02:36:30.227062 Cleaning after the job
2432 02:36:30.229220 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/ramdisk
2433 02:36:30.234417 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/kernel
2434 02:36:30.235605 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/dtb
2435 02:36:30.236144 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/nfsrootfs
2436 02:36:30.272167 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675320/tftp-deploy-hss_xpab/modules
2437 02:36:30.274944 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/675320
2438 02:36:31.469161 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/675320
2439 02:36:31.469379 Job finished correctly