Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:46:05.347408 lava-dispatcher, installed at version: 2024.01
2 02:46:05.348179 start: 0 validate
3 02:46:05.348641 Start time: 2024-08-30 02:46:05.348611+00:00 (UTC)
4 02:46:05.349186 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:46:05.349712 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 02:46:05.392684 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:46:05.393256 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-151-g1b5fe53681d9%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 02:46:05.425953 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:46:05.426845 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-151-g1b5fe53681d9%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:46:06.478962 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:46:06.479582 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-151-g1b5fe53681d9%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
12 02:46:06.522189 validate duration: 1.17
14 02:46:06.523825 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 02:46:06.524593 start: 1.1 download-retry (timeout 00:10:00) [common]
16 02:46:06.525262 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 02:46:06.526299 Not decompressing ramdisk as can be used compressed.
18 02:46:06.527115 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 02:46:06.527623 saving as /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/ramdisk/rootfs.cpio.gz
20 02:46:06.528199 total size: 8181887 (7 MB)
21 02:46:06.571243 progress 0 % (0 MB)
22 02:46:06.583958 progress 5 % (0 MB)
23 02:46:06.595521 progress 10 % (0 MB)
24 02:46:06.605535 progress 15 % (1 MB)
25 02:46:06.610851 progress 20 % (1 MB)
26 02:46:06.616698 progress 25 % (1 MB)
27 02:46:06.621953 progress 30 % (2 MB)
28 02:46:06.627589 progress 35 % (2 MB)
29 02:46:06.632896 progress 40 % (3 MB)
30 02:46:06.638564 progress 45 % (3 MB)
31 02:46:06.643795 progress 50 % (3 MB)
32 02:46:06.649604 progress 55 % (4 MB)
33 02:46:06.654885 progress 60 % (4 MB)
34 02:46:06.660570 progress 65 % (5 MB)
35 02:46:06.665858 progress 70 % (5 MB)
36 02:46:06.671475 progress 75 % (5 MB)
37 02:46:06.676745 progress 80 % (6 MB)
38 02:46:06.682409 progress 85 % (6 MB)
39 02:46:06.687553 progress 90 % (7 MB)
40 02:46:06.692873 progress 95 % (7 MB)
41 02:46:06.697665 progress 100 % (7 MB)
42 02:46:06.698322 7 MB downloaded in 0.17 s (45.87 MB/s)
43 02:46:06.698901 end: 1.1.1 http-download (duration 00:00:00) [common]
45 02:46:06.699841 end: 1.1 download-retry (duration 00:00:00) [common]
46 02:46:06.700185 start: 1.2 download-retry (timeout 00:10:00) [common]
47 02:46:06.700479 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 02:46:06.700969 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
49 02:46:06.701252 saving as /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/kernel/Image
50 02:46:06.701474 total size: 39019008 (37 MB)
51 02:46:06.701693 No compression specified
52 02:46:06.739681 progress 0 % (0 MB)
53 02:46:06.768994 progress 5 % (1 MB)
54 02:46:06.798725 progress 10 % (3 MB)
55 02:46:06.828190 progress 15 % (5 MB)
56 02:46:06.857727 progress 20 % (7 MB)
57 02:46:06.887093 progress 25 % (9 MB)
58 02:46:06.917003 progress 30 % (11 MB)
59 02:46:06.947672 progress 35 % (13 MB)
60 02:46:06.974340 progress 40 % (14 MB)
61 02:46:06.998732 progress 45 % (16 MB)
62 02:46:07.023615 progress 50 % (18 MB)
63 02:46:07.047965 progress 55 % (20 MB)
64 02:46:07.072714 progress 60 % (22 MB)
65 02:46:07.097400 progress 65 % (24 MB)
66 02:46:07.121916 progress 70 % (26 MB)
67 02:46:07.146575 progress 75 % (27 MB)
68 02:46:07.170611 progress 80 % (29 MB)
69 02:46:07.195606 progress 85 % (31 MB)
70 02:46:07.219648 progress 90 % (33 MB)
71 02:46:07.243953 progress 95 % (35 MB)
72 02:46:07.266999 progress 100 % (37 MB)
73 02:46:07.267730 37 MB downloaded in 0.57 s (65.72 MB/s)
74 02:46:07.268270 end: 1.2.1 http-download (duration 00:00:01) [common]
76 02:46:07.269114 end: 1.2 download-retry (duration 00:00:01) [common]
77 02:46:07.269396 start: 1.3 download-retry (timeout 00:09:59) [common]
78 02:46:07.269666 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 02:46:07.270143 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 02:46:07.270438 saving as /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/dtb/meson-g12b-a311d-libretech-cc.dtb
81 02:46:07.270650 total size: 54667 (0 MB)
82 02:46:07.270861 No compression specified
83 02:46:07.313730 progress 59 % (0 MB)
84 02:46:07.314585 progress 100 % (0 MB)
85 02:46:07.315156 0 MB downloaded in 0.04 s (1.17 MB/s)
86 02:46:07.315629 end: 1.3.1 http-download (duration 00:00:00) [common]
88 02:46:07.316502 end: 1.3 download-retry (duration 00:00:00) [common]
89 02:46:07.316770 start: 1.4 download-retry (timeout 00:09:59) [common]
90 02:46:07.317036 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 02:46:07.317494 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
92 02:46:07.317758 saving as /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/modules/modules.tar
93 02:46:07.317969 total size: 11626196 (11 MB)
94 02:46:07.318180 Using unxz to decompress xz
95 02:46:07.354565 progress 0 % (0 MB)
96 02:46:07.420530 progress 5 % (0 MB)
97 02:46:07.503778 progress 10 % (1 MB)
98 02:46:07.587323 progress 15 % (1 MB)
99 02:46:07.668637 progress 20 % (2 MB)
100 02:46:07.747394 progress 25 % (2 MB)
101 02:46:07.825195 progress 30 % (3 MB)
102 02:46:07.902076 progress 35 % (3 MB)
103 02:46:07.978167 progress 40 % (4 MB)
104 02:46:08.060872 progress 45 % (5 MB)
105 02:46:08.141230 progress 50 % (5 MB)
106 02:46:08.225821 progress 55 % (6 MB)
107 02:46:08.299669 progress 60 % (6 MB)
108 02:46:08.385808 progress 65 % (7 MB)
109 02:46:08.467307 progress 70 % (7 MB)
110 02:46:08.550171 progress 75 % (8 MB)
111 02:46:08.639494 progress 80 % (8 MB)
112 02:46:08.738935 progress 85 % (9 MB)
113 02:46:08.813696 progress 90 % (10 MB)
114 02:46:08.893088 progress 95 % (10 MB)
115 02:46:08.965303 progress 100 % (11 MB)
116 02:46:08.979033 11 MB downloaded in 1.66 s (6.68 MB/s)
117 02:46:08.979625 end: 1.4.1 http-download (duration 00:00:02) [common]
119 02:46:08.981270 end: 1.4 download-retry (duration 00:00:02) [common]
120 02:46:08.981822 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 02:46:08.982344 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 02:46:08.982837 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 02:46:08.983336 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 02:46:08.984348 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay
125 02:46:08.985160 makedir: /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin
126 02:46:08.985792 makedir: /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/tests
127 02:46:08.986666 makedir: /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/results
128 02:46:08.987296 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-add-keys
129 02:46:08.988258 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-add-sources
130 02:46:08.989199 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-background-process-start
131 02:46:08.990241 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-background-process-stop
132 02:46:08.991253 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-common-functions
133 02:46:08.992511 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-echo-ipv4
134 02:46:08.993474 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-install-packages
135 02:46:08.994390 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-installed-packages
136 02:46:08.995297 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-os-build
137 02:46:08.996231 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-probe-channel
138 02:46:08.997154 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-probe-ip
139 02:46:08.998160 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-target-ip
140 02:46:08.999068 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-target-mac
141 02:46:09.000033 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-target-storage
142 02:46:09.001008 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-test-case
143 02:46:09.001954 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-test-event
144 02:46:09.002859 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-test-feedback
145 02:46:09.003754 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-test-raise
146 02:46:09.004728 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-test-reference
147 02:46:09.005633 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-test-runner
148 02:46:09.006525 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-test-set
149 02:46:09.007416 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-test-shell
150 02:46:09.008351 Updating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-install-packages (oe)
151 02:46:09.009331 Updating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/bin/lava-installed-packages (oe)
152 02:46:09.010163 Creating /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/environment
153 02:46:09.010867 LAVA metadata
154 02:46:09.011357 - LAVA_JOB_ID=675402
155 02:46:09.011789 - LAVA_DISPATCHER_IP=192.168.6.2
156 02:46:09.012480 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 02:46:09.014246 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 02:46:09.014850 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 02:46:09.015265 skipped lava-vland-overlay
160 02:46:09.015751 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 02:46:09.016296 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 02:46:09.016725 skipped lava-multinode-overlay
163 02:46:09.017210 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 02:46:09.017707 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 02:46:09.018183 Loading test definitions
166 02:46:09.018725 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 02:46:09.019162 Using /lava-675402 at stage 0
168 02:46:09.020783 uuid=675402_1.5.2.4.1 testdef=None
169 02:46:09.021124 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 02:46:09.021399 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 02:46:09.023205 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 02:46:09.024054 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 02:46:09.026346 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 02:46:09.027205 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 02:46:09.029442 runner path: /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/0/tests/0_dmesg test_uuid 675402_1.5.2.4.1
178 02:46:09.030024 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 02:46:09.030819 Creating lava-test-runner.conf files
181 02:46:09.031025 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/675402/lava-overlay-6wg9m8ay/lava-675402/0 for stage 0
182 02:46:09.031365 - 0_dmesg
183 02:46:09.031723 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 02:46:09.032031 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 02:46:09.055840 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 02:46:09.056400 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 02:46:09.056809 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 02:46:09.057139 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 02:46:09.057457 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 02:46:09.973578 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 02:46:09.974044 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 02:46:09.974295 extracting modules file /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/675402/extract-overlay-ramdisk-oklh_m40/ramdisk
193 02:46:11.328073 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 02:46:11.328548 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 02:46:11.328876 [common] Applying overlay /var/lib/lava/dispatcher/tmp/675402/compress-overlay-j94xooiv/overlay-1.5.2.5.tar.gz to ramdisk
196 02:46:11.329119 [common] Applying overlay /var/lib/lava/dispatcher/tmp/675402/compress-overlay-j94xooiv/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/675402/extract-overlay-ramdisk-oklh_m40/ramdisk
197 02:46:11.359594 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 02:46:11.360000 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 02:46:11.360283 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 02:46:11.360509 Converting downloaded kernel to a uImage
201 02:46:11.360809 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/kernel/Image /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/kernel/uImage
202 02:46:11.761688 output: Image Name:
203 02:46:11.762169 output: Created: Fri Aug 30 02:46:11 2024
204 02:46:11.762427 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 02:46:11.762678 output: Data Size: 39019008 Bytes = 38104.50 KiB = 37.21 MiB
206 02:46:11.762925 output: Load Address: 01080000
207 02:46:11.763169 output: Entry Point: 01080000
208 02:46:11.763412 output:
209 02:46:11.763806 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 02:46:11.764197 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 02:46:11.764539 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 02:46:11.764856 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 02:46:11.765166 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 02:46:11.765483 Building ramdisk /var/lib/lava/dispatcher/tmp/675402/extract-overlay-ramdisk-oklh_m40/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/675402/extract-overlay-ramdisk-oklh_m40/ramdisk
215 02:46:14.679572 >> 186561 blocks
216 02:46:23.091443 Adding RAMdisk u-boot header.
217 02:46:23.092118 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/675402/extract-overlay-ramdisk-oklh_m40/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/675402/extract-overlay-ramdisk-oklh_m40/ramdisk.cpio.gz.uboot
218 02:46:23.377794 output: Image Name:
219 02:46:23.378204 output: Created: Fri Aug 30 02:46:23 2024
220 02:46:23.378410 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 02:46:23.378614 output: Data Size: 26566495 Bytes = 25943.84 KiB = 25.34 MiB
222 02:46:23.378815 output: Load Address: 00000000
223 02:46:23.379014 output: Entry Point: 00000000
224 02:46:23.379210 output:
225 02:46:23.379766 rename /var/lib/lava/dispatcher/tmp/675402/extract-overlay-ramdisk-oklh_m40/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/ramdisk/ramdisk.cpio.gz.uboot
226 02:46:23.380308 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 02:46:23.380856 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 02:46:23.381380 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 02:46:23.381832 No LXC device requested
230 02:46:23.382324 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 02:46:23.382826 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 02:46:23.383311 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 02:46:23.383727 Checking files for TFTP limit of 4294967296 bytes.
234 02:46:23.386374 end: 1 tftp-deploy (duration 00:00:17) [common]
235 02:46:23.386942 start: 2 uboot-action (timeout 00:05:00) [common]
236 02:46:23.387458 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 02:46:23.387955 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 02:46:23.388483 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 02:46:23.389009 Using kernel file from prepare-kernel: 675402/tftp-deploy-09wx57i_/kernel/uImage
240 02:46:23.389608 substitutions:
241 02:46:23.390013 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 02:46:23.390415 - {DTB_ADDR}: 0x01070000
243 02:46:23.390810 - {DTB}: 675402/tftp-deploy-09wx57i_/dtb/meson-g12b-a311d-libretech-cc.dtb
244 02:46:23.391205 - {INITRD}: 675402/tftp-deploy-09wx57i_/ramdisk/ramdisk.cpio.gz.uboot
245 02:46:23.391598 - {KERNEL_ADDR}: 0x01080000
246 02:46:23.392009 - {KERNEL}: 675402/tftp-deploy-09wx57i_/kernel/uImage
247 02:46:23.392410 - {LAVA_MAC}: None
248 02:46:23.392841 - {PRESEED_CONFIG}: None
249 02:46:23.393235 - {PRESEED_LOCAL}: None
250 02:46:23.393622 - {RAMDISK_ADDR}: 0x08000000
251 02:46:23.394004 - {RAMDISK}: 675402/tftp-deploy-09wx57i_/ramdisk/ramdisk.cpio.gz.uboot
252 02:46:23.394397 - {ROOT_PART}: None
253 02:46:23.394783 - {ROOT}: None
254 02:46:23.395168 - {SERVER_IP}: 192.168.6.2
255 02:46:23.395556 - {TEE_ADDR}: 0x83000000
256 02:46:23.395943 - {TEE}: None
257 02:46:23.396357 Parsed boot commands:
258 02:46:23.396734 - setenv autoload no
259 02:46:23.397118 - setenv initrd_high 0xffffffff
260 02:46:23.397503 - setenv fdt_high 0xffffffff
261 02:46:23.397886 - dhcp
262 02:46:23.398270 - setenv serverip 192.168.6.2
263 02:46:23.398654 - tftpboot 0x01080000 675402/tftp-deploy-09wx57i_/kernel/uImage
264 02:46:23.399040 - tftpboot 0x08000000 675402/tftp-deploy-09wx57i_/ramdisk/ramdisk.cpio.gz.uboot
265 02:46:23.399426 - tftpboot 0x01070000 675402/tftp-deploy-09wx57i_/dtb/meson-g12b-a311d-libretech-cc.dtb
266 02:46:23.399813 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 02:46:23.400226 - bootm 0x01080000 0x08000000 0x01070000
268 02:46:23.400716 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 02:46:23.402184 start: 2.3 connect-device (timeout 00:05:00) [common]
271 02:46:23.402626 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 02:46:23.417443 Setting prompt string to ['lava-test: # ']
273 02:46:23.418929 end: 2.3 connect-device (duration 00:00:00) [common]
274 02:46:23.419524 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 02:46:23.420089 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 02:46:23.420621 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 02:46:23.421759 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 02:46:23.464390 >> OK - accepted request
279 02:46:23.466585 Returned 0 in 0 seconds
280 02:46:23.567652 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 02:46:23.569238 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 02:46:23.569789 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 02:46:23.570291 Setting prompt string to ['Hit any key to stop autoboot']
285 02:46:23.570735 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 02:46:23.572288 Trying 192.168.56.21...
287 02:46:23.572775 Connected to conserv1.
288 02:46:23.573192 Escape character is '^]'.
289 02:46:23.573613
290 02:46:23.574033 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 02:46:23.574463
292 02:46:34.635623 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 02:46:34.636308 bl2_stage_init 0x01
294 02:46:34.636773 bl2_stage_init 0x81
295 02:46:34.641207 hw id: 0x0000 - pwm id 0x01
296 02:46:34.641743 bl2_stage_init 0xc1
297 02:46:34.642149 bl2_stage_init 0x02
298 02:46:34.642553
299 02:46:34.646696 L0:00000000
300 02:46:34.647138 L1:20000703
301 02:46:34.647543 L2:00008067
302 02:46:34.647927 L3:14000000
303 02:46:34.649607 B2:00402000
304 02:46:34.650020 B1:e0f83180
305 02:46:34.650408
306 02:46:34.650797 TE: 58167
307 02:46:34.651184
308 02:46:34.660712 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 02:46:34.661214
310 02:46:34.661607 Board ID = 1
311 02:46:34.661992 Set A53 clk to 24M
312 02:46:34.662377 Set A73 clk to 24M
313 02:46:34.666266 Set clk81 to 24M
314 02:46:34.666688 A53 clk: 1200 MHz
315 02:46:34.667077 A73 clk: 1200 MHz
316 02:46:34.671951 CLK81: 166.6M
317 02:46:34.672403 smccc: 00012abd
318 02:46:34.677525 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 02:46:34.677969 board id: 1
320 02:46:34.686317 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 02:46:34.696685 fw parse done
322 02:46:34.702613 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 02:46:34.745301 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 02:46:34.756168 PIEI prepare done
325 02:46:34.756610 fastboot data load
326 02:46:34.757003 fastboot data verify
327 02:46:34.761767 verify result: 266
328 02:46:34.767341 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 02:46:34.767808 LPDDR4 probe
330 02:46:34.768260 ddr clk to 1584MHz
331 02:46:34.775358 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 02:46:34.812603
333 02:46:34.813152 dmc_version 0001
334 02:46:34.819194 Check phy result
335 02:46:34.825000 INFO : End of CA training
336 02:46:34.825481 INFO : End of initialization
337 02:46:34.830628 INFO : Training has run successfully!
338 02:46:34.831066 Check phy result
339 02:46:34.836271 INFO : End of initialization
340 02:46:34.836695 INFO : End of read enable training
341 02:46:34.841861 INFO : End of fine write leveling
342 02:46:34.847462 INFO : End of Write leveling coarse delay
343 02:46:34.847882 INFO : Training has run successfully!
344 02:46:34.848320 Check phy result
345 02:46:34.853000 INFO : End of initialization
346 02:46:34.853424 INFO : End of read dq deskew training
347 02:46:34.858641 INFO : End of MPR read delay center optimization
348 02:46:34.864301 INFO : End of write delay center optimization
349 02:46:34.869878 INFO : End of read delay center optimization
350 02:46:34.870322 INFO : End of max read latency training
351 02:46:34.875530 INFO : Training has run successfully!
352 02:46:34.875952 1D training succeed
353 02:46:34.884786 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 02:46:34.932301 Check phy result
355 02:46:34.932744 INFO : End of initialization
356 02:46:34.954098 INFO : End of 2D read delay Voltage center optimization
357 02:46:34.974266 INFO : End of 2D read delay Voltage center optimization
358 02:46:35.026514 INFO : End of 2D write delay Voltage center optimization
359 02:46:35.076044 INFO : End of 2D write delay Voltage center optimization
360 02:46:35.081477 INFO : Training has run successfully!
361 02:46:35.081955
362 02:46:35.082381 channel==0
363 02:46:35.086970 RxClkDly_Margin_A0==88 ps 9
364 02:46:35.087406 TxDqDly_Margin_A0==98 ps 10
365 02:46:35.092786 RxClkDly_Margin_A1==88 ps 9
366 02:46:35.093228 TxDqDly_Margin_A1==98 ps 10
367 02:46:35.093642 TrainedVREFDQ_A0==74
368 02:46:35.098640 TrainedVREFDQ_A1==74
369 02:46:35.099088 VrefDac_Margin_A0==25
370 02:46:35.099496 DeviceVref_Margin_A0==40
371 02:46:35.103955 VrefDac_Margin_A1==25
372 02:46:35.104405 DeviceVref_Margin_A1==40
373 02:46:35.104810
374 02:46:35.105210
375 02:46:35.109479 channel==1
376 02:46:35.109965 RxClkDly_Margin_A0==98 ps 10
377 02:46:35.110385 TxDqDly_Margin_A0==98 ps 10
378 02:46:35.114954 RxClkDly_Margin_A1==98 ps 10
379 02:46:35.115438 TxDqDly_Margin_A1==88 ps 9
380 02:46:35.120462 TrainedVREFDQ_A0==77
381 02:46:35.120932 TrainedVREFDQ_A1==77
382 02:46:35.121342 VrefDac_Margin_A0==22
383 02:46:35.126125 DeviceVref_Margin_A0==37
384 02:46:35.126595 VrefDac_Margin_A1==22
385 02:46:35.131656 DeviceVref_Margin_A1==37
386 02:46:35.132124
387 02:46:35.132540 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 02:46:35.137250
389 02:46:35.165252 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 02:46:35.165788 2D training succeed
391 02:46:35.170804 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 02:46:35.176427 auto size-- 65535DDR cs0 size: 2048MB
393 02:46:35.176878 DDR cs1 size: 2048MB
394 02:46:35.182131 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 02:46:35.182589 cs0 DataBus test pass
396 02:46:35.187631 cs1 DataBus test pass
397 02:46:35.188150 cs0 AddrBus test pass
398 02:46:35.188588 cs1 AddrBus test pass
399 02:46:35.189017
400 02:46:35.193280 100bdlr_step_size ps== 420
401 02:46:35.193762 result report
402 02:46:35.198847 boot times 0Enable ddr reg access
403 02:46:35.204313 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 02:46:35.217960 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 02:46:35.790858 0.0;M3 CHK:0;cm4_sp_mode 0
406 02:46:35.791488 MVN_1=0x00000000
407 02:46:35.796195 MVN_2=0x00000000
408 02:46:35.802278 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 02:46:35.802719 OPS=0x10
410 02:46:35.803132 ring efuse init
411 02:46:35.803536 chipver efuse init
412 02:46:35.810344 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 02:46:35.810846 [0.018961 Inits done]
414 02:46:35.811258 secure task start!
415 02:46:35.817858 high task start!
416 02:46:35.818300 low task start!
417 02:46:35.818707 run into bl31
418 02:46:35.824449 NOTICE: BL31: v1.3(release):4fc40b1
419 02:46:35.832366 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 02:46:35.832814 NOTICE: BL31: G12A normal boot!
421 02:46:35.857525 NOTICE: BL31: BL33 decompress pass
422 02:46:35.863375 ERROR: Error initializing runtime service opteed_fast
423 02:46:37.096280
424 02:46:37.096877
425 02:46:37.104543 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 02:46:37.104990
427 02:46:37.105403 Model: Libre Computer AML-A311D-CC Alta
428 02:46:37.313062 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 02:46:37.336536 DRAM: 2 GiB (effective 3.8 GiB)
430 02:46:37.479663 Core: 408 devices, 31 uclasses, devicetree: separate
431 02:46:37.485441 WDT: Not starting watchdog@f0d0
432 02:46:37.517537 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 02:46:37.530074 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 02:46:37.535038 ** Bad device specification mmc 0 **
435 02:46:37.545384 Card did not respond to voltage select! : -110
436 02:46:37.552948 ** Bad device specification mmc 0 **
437 02:46:37.553373 Couldn't find partition mmc 0
438 02:46:37.561316 Card did not respond to voltage select! : -110
439 02:46:37.566816 ** Bad device specification mmc 0 **
440 02:46:37.567247 Couldn't find partition mmc 0
441 02:46:37.571875 Error: could not access storage.
442 02:46:38.836013 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 02:46:38.836566 bl2_stage_init 0x81
444 02:46:38.841679 hw id: 0x0000 - pwm id 0x01
445 02:46:38.842125 bl2_stage_init 0xc1
446 02:46:38.842537 bl2_stage_init 0x02
447 02:46:38.842936
448 02:46:38.847173 L0:00000000
449 02:46:38.847612 L1:20000703
450 02:46:38.848046 L2:00008067
451 02:46:38.848450 L3:14000000
452 02:46:38.848844 B2:00402000
453 02:46:38.852763 B1:e0f83180
454 02:46:38.853190
455 02:46:38.853592 TE: 58150
456 02:46:38.853995
457 02:46:38.858320 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 02:46:38.858747
459 02:46:38.859152 Board ID = 1
460 02:46:38.863935 Set A53 clk to 24M
461 02:46:38.864383 Set A73 clk to 24M
462 02:46:38.864783 Set clk81 to 24M
463 02:46:38.869675 A53 clk: 1200 MHz
464 02:46:38.870106 A73 clk: 1200 MHz
465 02:46:38.870512 CLK81: 166.6M
466 02:46:38.870908 smccc: 00012aab
467 02:46:38.875280 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 02:46:38.880711 board id: 1
469 02:46:38.886817 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 02:46:38.897077 fw parse done
471 02:46:38.903038 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 02:46:38.945713 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 02:46:38.956626 PIEI prepare done
474 02:46:38.957069 fastboot data load
475 02:46:38.957486 fastboot data verify
476 02:46:38.962272 verify result: 266
477 02:46:38.967834 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 02:46:38.968298 LPDDR4 probe
479 02:46:38.968707 ddr clk to 1584MHz
480 02:46:38.975832 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 02:46:39.013088
482 02:46:39.013558 dmc_version 0001
483 02:46:39.019765 Check phy result
484 02:46:39.025629 INFO : End of CA training
485 02:46:39.026058 INFO : End of initialization
486 02:46:39.031197 INFO : Training has run successfully!
487 02:46:39.031626 Check phy result
488 02:46:39.036795 INFO : End of initialization
489 02:46:39.037218 INFO : End of read enable training
490 02:46:39.042424 INFO : End of fine write leveling
491 02:46:39.048035 INFO : End of Write leveling coarse delay
492 02:46:39.048460 INFO : Training has run successfully!
493 02:46:39.048868 Check phy result
494 02:46:39.053637 INFO : End of initialization
495 02:46:39.054059 INFO : End of read dq deskew training
496 02:46:39.059207 INFO : End of MPR read delay center optimization
497 02:46:39.064819 INFO : End of write delay center optimization
498 02:46:39.070414 INFO : End of read delay center optimization
499 02:46:39.070876 INFO : End of max read latency training
500 02:46:39.076034 INFO : Training has run successfully!
501 02:46:39.076468 1D training succeed
502 02:46:39.085219 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 02:46:39.132780 Check phy result
504 02:46:39.133240 INFO : End of initialization
505 02:46:39.154256 INFO : End of 2D read delay Voltage center optimization
506 02:46:39.174362 INFO : End of 2D read delay Voltage center optimization
507 02:46:39.226350 INFO : End of 2D write delay Voltage center optimization
508 02:46:39.275678 INFO : End of 2D write delay Voltage center optimization
509 02:46:39.281171 INFO : Training has run successfully!
510 02:46:39.281614
511 02:46:39.282026 channel==0
512 02:46:39.286764 RxClkDly_Margin_A0==88 ps 9
513 02:46:39.287194 TxDqDly_Margin_A0==98 ps 10
514 02:46:39.292357 RxClkDly_Margin_A1==88 ps 9
515 02:46:39.292786 TxDqDly_Margin_A1==98 ps 10
516 02:46:39.293194 TrainedVREFDQ_A0==74
517 02:46:39.297971 TrainedVREFDQ_A1==76
518 02:46:39.298398 VrefDac_Margin_A0==25
519 02:46:39.298800 DeviceVref_Margin_A0==40
520 02:46:39.303675 VrefDac_Margin_A1==25
521 02:46:39.304151 DeviceVref_Margin_A1==38
522 02:46:39.304563
523 02:46:39.304965
524 02:46:39.309187 channel==1
525 02:46:39.309638 RxClkDly_Margin_A0==98 ps 10
526 02:46:39.310048 TxDqDly_Margin_A0==98 ps 10
527 02:46:39.314799 RxClkDly_Margin_A1==98 ps 10
528 02:46:39.315230 TxDqDly_Margin_A1==88 ps 9
529 02:46:39.320357 TrainedVREFDQ_A0==77
530 02:46:39.320788 TrainedVREFDQ_A1==77
531 02:46:39.321196 VrefDac_Margin_A0==22
532 02:46:39.325962 DeviceVref_Margin_A0==37
533 02:46:39.326392 VrefDac_Margin_A1==24
534 02:46:39.331670 DeviceVref_Margin_A1==37
535 02:46:39.332119
536 02:46:39.332525 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 02:46:39.337180
538 02:46:39.365198 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
539 02:46:39.365674 2D training succeed
540 02:46:39.370772 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 02:46:39.376364 auto size-- 65535DDR cs0 size: 2048MB
542 02:46:39.376796 DDR cs1 size: 2048MB
543 02:46:39.381969 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 02:46:39.382395 cs0 DataBus test pass
545 02:46:39.387657 cs1 DataBus test pass
546 02:46:39.388122 cs0 AddrBus test pass
547 02:46:39.388528 cs1 AddrBus test pass
548 02:46:39.388924
549 02:46:39.393163 100bdlr_step_size ps== 420
550 02:46:39.393632 result report
551 02:46:39.398776 boot times 0Enable ddr reg access
552 02:46:39.404198 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 02:46:39.417751 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 02:46:39.989738 0.0;M3 CHK:0;cm4_sp_mode 0
555 02:46:39.990370 MVN_1=0x00000000
556 02:46:39.995176 MVN_2=0x00000000
557 02:46:40.000966 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 02:46:40.001500 OPS=0x10
559 02:46:40.001908 ring efuse init
560 02:46:40.002302 chipver efuse init
561 02:46:40.009128 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 02:46:40.009629 [0.018961 Inits done]
563 02:46:40.016817 secure task start!
564 02:46:40.017290 high task start!
565 02:46:40.017685 low task start!
566 02:46:40.018075 run into bl31
567 02:46:40.023330 NOTICE: BL31: v1.3(release):4fc40b1
568 02:46:40.031120 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 02:46:40.031594 NOTICE: BL31: G12A normal boot!
570 02:46:40.056508 NOTICE: BL31: BL33 decompress pass
571 02:46:40.062180 ERROR: Error initializing runtime service opteed_fast
572 02:46:41.294987
573 02:46:41.295601
574 02:46:41.303444 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 02:46:41.303925
576 02:46:41.304379 Model: Libre Computer AML-A311D-CC Alta
577 02:46:41.511882 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 02:46:41.535258 DRAM: 2 GiB (effective 3.8 GiB)
579 02:46:41.678344 Core: 408 devices, 31 uclasses, devicetree: separate
580 02:46:41.684195 WDT: Not starting watchdog@f0d0
581 02:46:41.716429 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 02:46:41.728855 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 02:46:41.733845 ** Bad device specification mmc 0 **
584 02:46:41.744190 Card did not respond to voltage select! : -110
585 02:46:41.751857 ** Bad device specification mmc 0 **
586 02:46:41.752383 Couldn't find partition mmc 0
587 02:46:41.760196 Card did not respond to voltage select! : -110
588 02:46:41.765708 ** Bad device specification mmc 0 **
589 02:46:41.766186 Couldn't find partition mmc 0
590 02:46:41.770742 Error: could not access storage.
591 02:46:42.113198 Net: eth0: ethernet@ff3f0000
592 02:46:42.113784 starting USB...
593 02:46:42.365060 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 02:46:42.365631 Starting the controller
595 02:46:42.371970 USB XHCI 1.10
596 02:46:44.075903 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 02:46:44.076520 bl2_stage_init 0x01
598 02:46:44.076944 bl2_stage_init 0x81
599 02:46:44.081554 hw id: 0x0000 - pwm id 0x01
600 02:46:44.082022 bl2_stage_init 0xc1
601 02:46:44.082439 bl2_stage_init 0x02
602 02:46:44.082844
603 02:46:44.087120 L0:00000000
604 02:46:44.087582 L1:20000703
605 02:46:44.088028 L2:00008067
606 02:46:44.088439 L3:14000000
607 02:46:44.092657 B2:00402000
608 02:46:44.093116 B1:e0f83180
609 02:46:44.093528
610 02:46:44.093933 TE: 58124
611 02:46:44.094333
612 02:46:44.098267 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 02:46:44.098729
614 02:46:44.099137 Board ID = 1
615 02:46:44.103854 Set A53 clk to 24M
616 02:46:44.104339 Set A73 clk to 24M
617 02:46:44.104747 Set clk81 to 24M
618 02:46:44.109440 A53 clk: 1200 MHz
619 02:46:44.109899 A73 clk: 1200 MHz
620 02:46:44.110308 CLK81: 166.6M
621 02:46:44.110704 smccc: 00012a92
622 02:46:44.115050 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 02:46:44.120645 board id: 1
624 02:46:44.126533 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 02:46:44.137246 fw parse done
626 02:46:44.143165 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 02:46:44.185798 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 02:46:44.196716 PIEI prepare done
629 02:46:44.197171 fastboot data load
630 02:46:44.197582 fastboot data verify
631 02:46:44.202509 verify result: 266
632 02:46:44.207975 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 02:46:44.208461 LPDDR4 probe
634 02:46:44.208867 ddr clk to 1584MHz
635 02:46:44.215975 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 02:46:44.253235
637 02:46:44.253744 dmc_version 0001
638 02:46:44.259936 Check phy result
639 02:46:44.265773 INFO : End of CA training
640 02:46:44.266237 INFO : End of initialization
641 02:46:44.271363 INFO : Training has run successfully!
642 02:46:44.271819 Check phy result
643 02:46:44.277005 INFO : End of initialization
644 02:46:44.277464 INFO : End of read enable training
645 02:46:44.280268 INFO : End of fine write leveling
646 02:46:44.285885 INFO : End of Write leveling coarse delay
647 02:46:44.291567 INFO : Training has run successfully!
648 02:46:44.292058 Check phy result
649 02:46:44.292475 INFO : End of initialization
650 02:46:44.296983 INFO : End of read dq deskew training
651 02:46:44.302590 INFO : End of MPR read delay center optimization
652 02:46:44.303053 INFO : End of write delay center optimization
653 02:46:44.308242 INFO : End of read delay center optimization
654 02:46:44.313776 INFO : End of max read latency training
655 02:46:44.314239 INFO : Training has run successfully!
656 02:46:44.319490 1D training succeed
657 02:46:44.325414 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 02:46:44.372952 Check phy result
659 02:46:44.373521 INFO : End of initialization
660 02:46:44.393716 INFO : End of 2D read delay Voltage center optimization
661 02:46:44.414709 INFO : End of 2D read delay Voltage center optimization
662 02:46:44.465704 INFO : End of 2D write delay Voltage center optimization
663 02:46:44.515933 INFO : End of 2D write delay Voltage center optimization
664 02:46:44.521456 INFO : Training has run successfully!
665 02:46:44.521766
666 02:46:44.522000 channel==0
667 02:46:44.526992 RxClkDly_Margin_A0==88 ps 9
668 02:46:44.527481 TxDqDly_Margin_A0==98 ps 10
669 02:46:44.530343 RxClkDly_Margin_A1==88 ps 9
670 02:46:44.530807 TxDqDly_Margin_A1==98 ps 10
671 02:46:44.535717 TrainedVREFDQ_A0==74
672 02:46:44.536241 TrainedVREFDQ_A1==76
673 02:46:44.541416 VrefDac_Margin_A0==25
674 02:46:44.541915 DeviceVref_Margin_A0==40
675 02:46:44.542354 VrefDac_Margin_A1==25
676 02:46:44.546779 DeviceVref_Margin_A1==38
677 02:46:44.547062
678 02:46:44.547286
679 02:46:44.547663 channel==1
680 02:46:44.548101 RxClkDly_Margin_A0==98 ps 10
681 02:46:44.552597 TxDqDly_Margin_A0==88 ps 9
682 02:46:44.553075 RxClkDly_Margin_A1==88 ps 9
683 02:46:44.558182 TxDqDly_Margin_A1==88 ps 9
684 02:46:44.558657 TrainedVREFDQ_A0==77
685 02:46:44.559073 TrainedVREFDQ_A1==77
686 02:46:44.563795 VrefDac_Margin_A0==22
687 02:46:44.564291 DeviceVref_Margin_A0==37
688 02:46:44.569383 VrefDac_Margin_A1==24
689 02:46:44.569865 DeviceVref_Margin_A1==37
690 02:46:44.570213
691 02:46:44.574968 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 02:46:44.575450
693 02:46:44.602834 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
694 02:46:44.608403 2D training succeed
695 02:46:44.614057 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 02:46:44.614528 auto size-- 65535DDR cs0 size: 2048MB
697 02:46:44.619673 DDR cs1 size: 2048MB
698 02:46:44.620201 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 02:46:44.625288 cs0 DataBus test pass
700 02:46:44.625761 cs1 DataBus test pass
701 02:46:44.626178 cs0 AddrBus test pass
702 02:46:44.630863 cs1 AddrBus test pass
703 02:46:44.631338
704 02:46:44.631772 100bdlr_step_size ps== 420
705 02:46:44.632222 result report
706 02:46:44.636511 boot times 0Enable ddr reg access
707 02:46:44.644246 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 02:46:44.657586 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 02:46:45.229646 0.0;M3 CHK:0;cm4_sp_mode 0
710 02:46:45.230270 MVN_1=0x00000000
711 02:46:45.235221 MVN_2=0x00000000
712 02:46:45.240919 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 02:46:45.241434 OPS=0x10
714 02:46:45.241833 ring efuse init
715 02:46:45.242225 chipver efuse init
716 02:46:45.249059 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 02:46:45.249567 [0.018961 Inits done]
718 02:46:45.256657 secure task start!
719 02:46:45.257113 high task start!
720 02:46:45.257506 low task start!
721 02:46:45.257891 run into bl31
722 02:46:45.263345 NOTICE: BL31: v1.3(release):4fc40b1
723 02:46:45.271139 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 02:46:45.271602 NOTICE: BL31: G12A normal boot!
725 02:46:45.296570 NOTICE: BL31: BL33 decompress pass
726 02:46:45.302172 ERROR: Error initializing runtime service opteed_fast
727 02:46:46.540107
728 02:46:46.540519
729 02:46:46.542481 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 02:46:46.542750
731 02:46:46.542955 Model: Libre Computer AML-A311D-CC Alta
732 02:46:46.751924 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 02:46:46.774317 DRAM: 2 GiB (effective 3.8 GiB)
734 02:46:46.918322 Core: 408 devices, 31 uclasses, devicetree: separate
735 02:46:46.924273 WDT: Not starting watchdog@f0d0
736 02:46:46.956497 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 02:46:46.968947 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 02:46:46.973965 ** Bad device specification mmc 0 **
739 02:46:46.984302 Card did not respond to voltage select! : -110
740 02:46:46.991971 ** Bad device specification mmc 0 **
741 02:46:46.992496 Couldn't find partition mmc 0
742 02:46:47.000298 Card did not respond to voltage select! : -110
743 02:46:47.005852 ** Bad device specification mmc 0 **
744 02:46:47.006334 Couldn't find partition mmc 0
745 02:46:47.010932 Error: could not access storage.
746 02:46:47.352346 Net: eth0: ethernet@ff3f0000
747 02:46:47.352917 starting USB...
748 02:46:47.605100 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 02:46:47.605681 Starting the controller
750 02:46:47.612083 USB XHCI 1.10
751 02:46:49.776000 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 02:46:49.776413 bl2_stage_init 0x01
753 02:46:49.776632 bl2_stage_init 0x81
754 02:46:49.781508 hw id: 0x0000 - pwm id 0x01
755 02:46:49.781920 bl2_stage_init 0xc1
756 02:46:49.782282 bl2_stage_init 0x02
757 02:46:49.782601
758 02:46:49.787054 L0:00000000
759 02:46:49.787330 L1:20000703
760 02:46:49.787542 L2:00008067
761 02:46:49.787752 L3:14000000
762 02:46:49.792669 B2:00402000
763 02:46:49.793054 B1:e0f83180
764 02:46:49.793377
765 02:46:49.793703 TE: 58124
766 02:46:49.794052
767 02:46:49.798266 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 02:46:49.798671
769 02:46:49.799002 Board ID = 1
770 02:46:49.803856 Set A53 clk to 24M
771 02:46:49.804150 Set A73 clk to 24M
772 02:46:49.804382 Set clk81 to 24M
773 02:46:49.809455 A53 clk: 1200 MHz
774 02:46:49.809836 A73 clk: 1200 MHz
775 02:46:49.810185 CLK81: 166.6M
776 02:46:49.810516 smccc: 00012a92
777 02:46:49.815056 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 02:46:49.820588 board id: 1
779 02:46:49.826567 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 02:46:49.837102 fw parse done
781 02:46:49.843074 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 02:46:49.885727 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 02:46:49.896595 PIEI prepare done
784 02:46:49.896876 fastboot data load
785 02:46:49.897090 fastboot data verify
786 02:46:49.902259 verify result: 266
787 02:46:49.907855 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 02:46:49.908271 LPDDR4 probe
789 02:46:49.908659 ddr clk to 1584MHz
790 02:46:49.915846 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 02:46:49.952397
792 02:46:49.952699 dmc_version 0001
793 02:46:49.959837 Check phy result
794 02:46:49.965679 INFO : End of CA training
795 02:46:49.966069 INFO : End of initialization
796 02:46:49.971293 INFO : Training has run successfully!
797 02:46:49.971566 Check phy result
798 02:46:49.976894 INFO : End of initialization
799 02:46:49.977277 INFO : End of read enable training
800 02:46:49.982487 INFO : End of fine write leveling
801 02:46:49.988092 INFO : End of Write leveling coarse delay
802 02:46:49.988372 INFO : Training has run successfully!
803 02:46:49.988583 Check phy result
804 02:46:49.993640 INFO : End of initialization
805 02:46:49.994030 INFO : End of read dq deskew training
806 02:46:49.999288 INFO : End of MPR read delay center optimization
807 02:46:50.004890 INFO : End of write delay center optimization
808 02:46:50.010486 INFO : End of read delay center optimization
809 02:46:50.010763 INFO : End of max read latency training
810 02:46:50.016092 INFO : Training has run successfully!
811 02:46:50.016362 1D training succeed
812 02:46:50.025289 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 02:46:50.072764 Check phy result
814 02:46:50.073071 INFO : End of initialization
815 02:46:50.095370 INFO : End of 2D read delay Voltage center optimization
816 02:46:50.115616 INFO : End of 2D read delay Voltage center optimization
817 02:46:50.167658 INFO : End of 2D write delay Voltage center optimization
818 02:46:50.217065 INFO : End of 2D write delay Voltage center optimization
819 02:46:50.222597 INFO : Training has run successfully!
820 02:46:50.222874
821 02:46:50.223094 channel==0
822 02:46:50.228195 RxClkDly_Margin_A0==88 ps 9
823 02:46:50.228577 TxDqDly_Margin_A0==98 ps 10
824 02:46:50.233781 RxClkDly_Margin_A1==88 ps 9
825 02:46:50.238046 TxDqDly_Margin_A1==98 ps 10
826 02:46:50.238337 TrainedVREFDQ_A0==74
827 02:46:50.239403 TrainedVREFDQ_A1==76
828 02:46:50.239670 VrefDac_Margin_A0==24
829 02:46:50.239892 DeviceVref_Margin_A0==40
830 02:46:50.245027 VrefDac_Margin_A1==24
831 02:46:50.245287 DeviceVref_Margin_A1==38
832 02:46:50.245490
833 02:46:50.245688
834 02:46:50.250578 channel==1
835 02:46:50.250837 RxClkDly_Margin_A0==98 ps 10
836 02:46:50.251057 TxDqDly_Margin_A0==98 ps 10
837 02:46:50.256194 RxClkDly_Margin_A1==88 ps 9
838 02:46:50.256450 TxDqDly_Margin_A1==88 ps 9
839 02:46:50.261785 TrainedVREFDQ_A0==77
840 02:46:50.262047 TrainedVREFDQ_A1==77
841 02:46:50.262253 VrefDac_Margin_A0==22
842 02:46:50.267378 DeviceVref_Margin_A0==37
843 02:46:50.267636 VrefDac_Margin_A1==24
844 02:46:50.273035 DeviceVref_Margin_A1==37
845 02:46:50.273303
846 02:46:50.273522 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 02:46:50.273733
848 02:46:50.306574 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
849 02:46:50.306857 2D training succeed
850 02:46:50.312193 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 02:46:50.317782 auto size-- 65535DDR cs0 size: 2048MB
852 02:46:50.318041 DDR cs1 size: 2048MB
853 02:46:50.323374 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 02:46:50.323639 cs0 DataBus test pass
855 02:46:50.329049 cs1 DataBus test pass
856 02:46:50.329313 cs0 AddrBus test pass
857 02:46:50.329531 cs1 AddrBus test pass
858 02:46:50.329746
859 02:46:50.334561 100bdlr_step_size ps== 420
860 02:46:50.334823 result report
861 02:46:50.340198 boot times 0Enable ddr reg access
862 02:46:50.345530 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 02:46:50.359031 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 02:46:50.932697 0.0;M3 CHK:0;cm4_sp_mode 0
865 02:46:50.933074 MVN_1=0x00000000
866 02:46:50.938211 MVN_2=0x00000000
867 02:46:50.943933 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 02:46:50.944433 OPS=0x10
869 02:46:50.944853 ring efuse init
870 02:46:50.945256 chipver efuse init
871 02:46:50.949589 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 02:46:50.955188 [0.018961 Inits done]
873 02:46:50.955639 secure task start!
874 02:46:50.956075 high task start!
875 02:46:50.959748 low task start!
876 02:46:50.960226 run into bl31
877 02:46:50.966448 NOTICE: BL31: v1.3(release):4fc40b1
878 02:46:50.974218 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 02:46:50.974682 NOTICE: BL31: G12A normal boot!
880 02:46:50.999661 NOTICE: BL31: BL33 decompress pass
881 02:46:51.005334 ERROR: Error initializing runtime service opteed_fast
882 02:46:52.238171
883 02:46:52.238721
884 02:46:52.246637 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 02:46:52.247098
886 02:46:52.247513 Model: Libre Computer AML-A311D-CC Alta
887 02:46:52.455057 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 02:46:52.478408 DRAM: 2 GiB (effective 3.8 GiB)
889 02:46:52.621478 Core: 408 devices, 31 uclasses, devicetree: separate
890 02:46:52.627363 WDT: Not starting watchdog@f0d0
891 02:46:52.659572 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 02:46:52.671934 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 02:46:52.676931 ** Bad device specification mmc 0 **
894 02:46:52.687278 Card did not respond to voltage select! : -110
895 02:46:52.694905 ** Bad device specification mmc 0 **
896 02:46:52.695161 Couldn't find partition mmc 0
897 02:46:52.703365 Card did not respond to voltage select! : -110
898 02:46:52.708829 ** Bad device specification mmc 0 **
899 02:46:52.709077 Couldn't find partition mmc 0
900 02:46:52.713862 Error: could not access storage.
901 02:46:53.056359 Net: eth0: ethernet@ff3f0000
902 02:46:53.056870 starting USB...
903 02:46:53.308164 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 02:46:53.308641 Starting the controller
905 02:46:53.317075 USB XHCI 1.10
906 02:46:54.869104 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 02:46:54.877450 scanning usb for storage devices... 0 Storage Device(s) found
909 02:46:54.928965 Hit any key to stop autoboot: 1
910 02:46:54.929833 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
911 02:46:54.930471 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 02:46:54.930952 Setting prompt string to ['=>']
913 02:46:54.931429 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 02:46:54.944942 0
915 02:46:54.945796 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 02:46:54.946281 Sending with 10 millisecond of delay
918 02:46:56.080722 => setenv autoload no
919 02:46:56.091490 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 02:46:56.096367 setenv autoload no
921 02:46:56.097081 Sending with 10 millisecond of delay
923 02:46:57.894842 => setenv initrd_high 0xffffffff
924 02:46:57.905670 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 02:46:57.906363 setenv initrd_high 0xffffffff
926 02:46:57.906928 Sending with 10 millisecond of delay
928 02:46:59.524150 => setenv fdt_high 0xffffffff
929 02:46:59.534914 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
930 02:46:59.535721 setenv fdt_high 0xffffffff
931 02:46:59.536477 Sending with 10 millisecond of delay
933 02:46:59.828588 => dhcp
934 02:46:59.839294 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
935 02:46:59.840155 dhcp
936 02:46:59.840605 Speed: 1000, full duplex
937 02:46:59.841026 BOOTP broadcast 1
938 02:47:00.087187 BOOTP broadcast 2
939 02:47:00.234987 DHCP client bound to address 192.168.6.33 (397 ms)
940 02:47:00.235761 Sending with 10 millisecond of delay
942 02:47:01.911845 => setenv serverip 192.168.6.2
943 02:47:01.922666 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 02:47:01.923552 setenv serverip 192.168.6.2
945 02:47:01.924277 Sending with 10 millisecond of delay
947 02:47:05.648758 => tftpboot 0x01080000 675402/tftp-deploy-09wx57i_/kernel/uImage
948 02:47:05.659507 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 02:47:05.660084 tftpboot 0x01080000 675402/tftp-deploy-09wx57i_/kernel/uImage
950 02:47:05.660351 Speed: 1000, full duplex
951 02:47:05.660567 Using ethernet@ff3f0000 device
952 02:47:05.662033 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
953 02:47:05.667557 Filename '675402/tftp-deploy-09wx57i_/kernel/uImage'.
954 02:47:05.670651 Load address: 0x1080000
955 02:47:08.307448 Loading: *################################################## 37.2 MiB
956 02:47:08.308151 14.1 MiB/s
957 02:47:08.308635 done
958 02:47:08.311374 Bytes transferred = 39019072 (2536240 hex)
959 02:47:08.312212 Sending with 10 millisecond of delay
961 02:47:12.998980 => tftpboot 0x08000000 675402/tftp-deploy-09wx57i_/ramdisk/ramdisk.cpio.gz.uboot
962 02:47:13.009832 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
963 02:47:13.010710 tftpboot 0x08000000 675402/tftp-deploy-09wx57i_/ramdisk/ramdisk.cpio.gz.uboot
964 02:47:13.011217 Speed: 1000, full duplex
965 02:47:13.011679 Using ethernet@ff3f0000 device
966 02:47:13.012524 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
967 02:47:13.020963 Filename '675402/tftp-deploy-09wx57i_/ramdisk/ramdisk.cpio.gz.uboot'.
968 02:47:13.021473 Load address: 0x8000000
969 02:47:19.860308 Loading: *#######################T ########################## UDP wrong checksum 00000005 00000b3b
970 02:47:24.862202 T UDP wrong checksum 00000005 00000b3b
971 02:47:34.367496 T UDP wrong checksum 000000ff 0000c997
972 02:47:34.379842 UDP wrong checksum 000000ff 00004d8a
973 02:47:34.864028 T UDP wrong checksum 00000005 00000b3b
974 02:47:50.721700 T T T UDP wrong checksum 000000ff 00009252
975 02:47:50.728695 UDP wrong checksum 000000ff 00002645
976 02:47:54.867191 T UDP wrong checksum 00000005 00000b3b
977 02:47:55.033501 UDP wrong checksum 000000ff 0000abb6
978 02:47:55.055002 UDP wrong checksum 000000ff 000032a9
979 02:47:57.174046 UDP wrong checksum 000000ff 00002689
980 02:47:57.202561 UDP wrong checksum 000000ff 0000b77b
981 02:48:09.871907 T T
982 02:48:09.872586 Retry count exceeded; starting again
984 02:48:09.874304 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
987 02:48:09.875459 end: 2.4 uboot-commands (duration 00:01:46) [common]
989 02:48:09.878686 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
991 02:48:09.880871 end: 2 uboot-action (duration 00:01:46) [common]
993 02:48:09.884241 Cleaning after the job
994 02:48:09.885340 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/ramdisk
995 02:48:09.888023 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/kernel
996 02:48:09.938345 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/dtb
997 02:48:09.939640 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675402/tftp-deploy-09wx57i_/modules
998 02:48:09.971027 start: 4.1 power-off (timeout 00:00:30) [common]
999 02:48:09.972070 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1000 02:48:10.011575 >> OK - accepted request
1001 02:48:10.013666 Returned 0 in 0 seconds
1002 02:48:10.114842 end: 4.1 power-off (duration 00:00:00) [common]
1004 02:48:10.116482 start: 4.2 read-feedback (timeout 00:10:00) [common]
1005 02:48:10.117539 Listened to connection for namespace 'common' for up to 1s
1006 02:48:11.118371 Finalising connection for namespace 'common'
1007 02:48:11.119138 Disconnecting from shell: Finalise
1008 02:48:11.119610 =>
1009 02:48:11.220526 end: 4.2 read-feedback (duration 00:00:01) [common]
1010 02:48:11.220997 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/675402
1011 02:48:11.507224 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/675402
1012 02:48:11.507860 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.