Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:42:05.212578 lava-dispatcher, installed at version: 2024.01
2 02:42:05.213417 start: 0 validate
3 02:42:05.213891 Start time: 2024-08-30 02:42:05.213861+00:00 (UTC)
4 02:42:05.214432 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:42:05.214972 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 02:42:05.256193 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:42:05.256774 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-151-g1b5fe53681d9%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 02:42:05.284604 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:42:05.285263 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-151-g1b5fe53681d9%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 02:42:06.329623 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:42:06.330146 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-151-g1b5fe53681d9%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
12 02:42:06.368911 validate duration: 1.16
14 02:42:06.369767 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 02:42:06.370093 start: 1.1 download-retry (timeout 00:10:00) [common]
16 02:42:06.370394 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 02:42:06.371074 Not decompressing ramdisk as can be used compressed.
18 02:42:06.371608 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 02:42:06.372147 saving as /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/ramdisk/rootfs.cpio.gz
20 02:42:06.372692 total size: 8181887 (7 MB)
21 02:42:06.410616 progress 0 % (0 MB)
22 02:42:06.418518 progress 5 % (0 MB)
23 02:42:06.428765 progress 10 % (0 MB)
24 02:42:06.437967 progress 15 % (1 MB)
25 02:42:06.443099 progress 20 % (1 MB)
26 02:42:06.448760 progress 25 % (1 MB)
27 02:42:06.453937 progress 30 % (2 MB)
28 02:42:06.459453 progress 35 % (2 MB)
29 02:42:06.464548 progress 40 % (3 MB)
30 02:42:06.470099 progress 45 % (3 MB)
31 02:42:06.475319 progress 50 % (3 MB)
32 02:42:06.481289 progress 55 % (4 MB)
33 02:42:06.486454 progress 60 % (4 MB)
34 02:42:06.491995 progress 65 % (5 MB)
35 02:42:06.497427 progress 70 % (5 MB)
36 02:42:06.503047 progress 75 % (5 MB)
37 02:42:06.508234 progress 80 % (6 MB)
38 02:42:06.513812 progress 85 % (6 MB)
39 02:42:06.518708 progress 90 % (7 MB)
40 02:42:06.523845 progress 95 % (7 MB)
41 02:42:06.528724 progress 100 % (7 MB)
42 02:42:06.529372 7 MB downloaded in 0.16 s (49.80 MB/s)
43 02:42:06.529933 end: 1.1.1 http-download (duration 00:00:00) [common]
45 02:42:06.530833 end: 1.1 download-retry (duration 00:00:00) [common]
46 02:42:06.531286 start: 1.2 download-retry (timeout 00:10:00) [common]
47 02:42:06.531611 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 02:42:06.532365 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
49 02:42:06.532660 saving as /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/kernel/Image
50 02:42:06.532882 total size: 39019008 (37 MB)
51 02:42:06.533101 No compression specified
52 02:42:06.567929 progress 0 % (0 MB)
53 02:42:06.591443 progress 5 % (1 MB)
54 02:42:06.615778 progress 10 % (3 MB)
55 02:42:06.639458 progress 15 % (5 MB)
56 02:42:06.663595 progress 20 % (7 MB)
57 02:42:06.687434 progress 25 % (9 MB)
58 02:42:06.711423 progress 30 % (11 MB)
59 02:42:06.735415 progress 35 % (13 MB)
60 02:42:06.759519 progress 40 % (14 MB)
61 02:42:06.783339 progress 45 % (16 MB)
62 02:42:06.807592 progress 50 % (18 MB)
63 02:42:06.831472 progress 55 % (20 MB)
64 02:42:06.855380 progress 60 % (22 MB)
65 02:42:06.879001 progress 65 % (24 MB)
66 02:42:06.903057 progress 70 % (26 MB)
67 02:42:06.927041 progress 75 % (27 MB)
68 02:42:06.950515 progress 80 % (29 MB)
69 02:42:06.974383 progress 85 % (31 MB)
70 02:42:06.997500 progress 90 % (33 MB)
71 02:42:07.021223 progress 95 % (35 MB)
72 02:42:07.043638 progress 100 % (37 MB)
73 02:42:07.044397 37 MB downloaded in 0.51 s (72.75 MB/s)
74 02:42:07.044920 end: 1.2.1 http-download (duration 00:00:01) [common]
76 02:42:07.045801 end: 1.2 download-retry (duration 00:00:01) [common]
77 02:42:07.046115 start: 1.3 download-retry (timeout 00:09:59) [common]
78 02:42:07.046464 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 02:42:07.046970 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 02:42:07.047250 saving as /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 02:42:07.047460 total size: 53173 (0 MB)
82 02:42:07.047671 No compression specified
83 02:42:07.086968 progress 61 % (0 MB)
84 02:42:07.087901 progress 100 % (0 MB)
85 02:42:07.088580 0 MB downloaded in 0.04 s (1.23 MB/s)
86 02:42:07.089144 end: 1.3.1 http-download (duration 00:00:00) [common]
88 02:42:07.090007 end: 1.3 download-retry (duration 00:00:00) [common]
89 02:42:07.090283 start: 1.4 download-retry (timeout 00:09:59) [common]
90 02:42:07.090551 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 02:42:07.091157 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
92 02:42:07.091447 saving as /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/modules/modules.tar
93 02:42:07.091653 total size: 11626196 (11 MB)
94 02:42:07.091868 Using unxz to decompress xz
95 02:42:07.127255 progress 0 % (0 MB)
96 02:42:07.201304 progress 5 % (0 MB)
97 02:42:07.285369 progress 10 % (1 MB)
98 02:42:07.370688 progress 15 % (1 MB)
99 02:42:07.452787 progress 20 % (2 MB)
100 02:42:07.532383 progress 25 % (2 MB)
101 02:42:07.611006 progress 30 % (3 MB)
102 02:42:07.688701 progress 35 % (3 MB)
103 02:42:07.765587 progress 40 % (4 MB)
104 02:42:07.849080 progress 45 % (5 MB)
105 02:42:07.930002 progress 50 % (5 MB)
106 02:42:08.017678 progress 55 % (6 MB)
107 02:42:08.092347 progress 60 % (6 MB)
108 02:42:08.179086 progress 65 % (7 MB)
109 02:42:08.261394 progress 70 % (7 MB)
110 02:42:08.344803 progress 75 % (8 MB)
111 02:42:08.435138 progress 80 % (8 MB)
112 02:42:08.534277 progress 85 % (9 MB)
113 02:42:08.609499 progress 90 % (10 MB)
114 02:42:08.689905 progress 95 % (10 MB)
115 02:42:08.762739 progress 100 % (11 MB)
116 02:42:08.776705 11 MB downloaded in 1.69 s (6.58 MB/s)
117 02:42:08.777299 end: 1.4.1 http-download (duration 00:00:02) [common]
119 02:42:08.778119 end: 1.4 download-retry (duration 00:00:02) [common]
120 02:42:08.778388 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 02:42:08.778653 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 02:42:08.778903 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 02:42:08.779155 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 02:42:08.779753 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u
125 02:42:08.780516 makedir: /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin
126 02:42:08.781174 makedir: /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/tests
127 02:42:08.781794 makedir: /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/results
128 02:42:08.782399 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-add-keys
129 02:42:08.783356 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-add-sources
130 02:42:08.784321 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-background-process-start
131 02:42:08.785269 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-background-process-stop
132 02:42:08.786279 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-common-functions
133 02:42:08.787194 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-echo-ipv4
134 02:42:08.788226 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-install-packages
135 02:42:08.789140 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-installed-packages
136 02:42:08.790023 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-os-build
137 02:42:08.790901 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-probe-channel
138 02:42:08.791784 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-probe-ip
139 02:42:08.792715 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-target-ip
140 02:42:08.793601 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-target-mac
141 02:42:08.794486 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-target-storage
142 02:42:08.795385 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-test-case
143 02:42:08.796368 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-test-event
144 02:42:08.797292 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-test-feedback
145 02:42:08.798238 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-test-raise
146 02:42:08.799177 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-test-reference
147 02:42:08.800169 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-test-runner
148 02:42:08.801081 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-test-set
149 02:42:08.801968 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-test-shell
150 02:42:08.802863 Updating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-install-packages (oe)
151 02:42:08.803828 Updating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/bin/lava-installed-packages (oe)
152 02:42:08.804691 Creating /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/environment
153 02:42:08.805452 LAVA metadata
154 02:42:08.805938 - LAVA_JOB_ID=675406
155 02:42:08.806361 - LAVA_DISPATCHER_IP=192.168.6.2
156 02:42:08.807018 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 02:42:08.808840 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 02:42:08.809421 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 02:42:08.809829 skipped lava-vland-overlay
160 02:42:08.810310 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 02:42:08.810812 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 02:42:08.811235 skipped lava-multinode-overlay
163 02:42:08.811712 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 02:42:08.812242 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 02:42:08.812713 Loading test definitions
166 02:42:08.813254 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 02:42:08.813691 Using /lava-675406 at stage 0
168 02:42:08.816017 uuid=675406_1.5.2.4.1 testdef=None
169 02:42:08.816592 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 02:42:08.817103 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 02:42:08.820479 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 02:42:08.822008 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 02:42:08.825020 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 02:42:08.825878 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 02:42:08.828102 runner path: /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/0/tests/0_dmesg test_uuid 675406_1.5.2.4.1
178 02:42:08.828679 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 02:42:08.829444 Creating lava-test-runner.conf files
181 02:42:08.829649 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/675406/lava-overlay-v0dpu75u/lava-675406/0 for stage 0
182 02:42:08.830020 - 0_dmesg
183 02:42:08.830377 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 02:42:08.830657 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 02:42:08.854661 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 02:42:08.855062 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:58) [common]
187 02:42:08.855327 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 02:42:08.855595 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 02:42:08.855855 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
190 02:42:09.810905 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 02:42:09.811389 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 02:42:09.811638 extracting modules file /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/675406/extract-overlay-ramdisk-i7jmzdz3/ramdisk
193 02:42:11.131271 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 02:42:11.131754 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 02:42:11.132045 [common] Applying overlay /var/lib/lava/dispatcher/tmp/675406/compress-overlay-60y_gf30/overlay-1.5.2.5.tar.gz to ramdisk
196 02:42:11.132264 [common] Applying overlay /var/lib/lava/dispatcher/tmp/675406/compress-overlay-60y_gf30/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/675406/extract-overlay-ramdisk-i7jmzdz3/ramdisk
197 02:42:11.162495 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 02:42:11.162889 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 02:42:11.163160 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 02:42:11.163384 Converting downloaded kernel to a uImage
201 02:42:11.163689 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/kernel/Image /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/kernel/uImage
202 02:42:11.545877 output: Image Name:
203 02:42:11.546277 output: Created: Fri Aug 30 02:42:11 2024
204 02:42:11.546489 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 02:42:11.546693 output: Data Size: 39019008 Bytes = 38104.50 KiB = 37.21 MiB
206 02:42:11.546895 output: Load Address: 01080000
207 02:42:11.547093 output: Entry Point: 01080000
208 02:42:11.547289 output:
209 02:42:11.547617 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 02:42:11.547880 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 02:42:11.548193 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 02:42:11.548448 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 02:42:11.548704 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 02:42:11.548968 Building ramdisk /var/lib/lava/dispatcher/tmp/675406/extract-overlay-ramdisk-i7jmzdz3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/675406/extract-overlay-ramdisk-i7jmzdz3/ramdisk
215 02:42:14.007813 >> 186561 blocks
216 02:42:22.293260 Adding RAMdisk u-boot header.
217 02:42:22.293920 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/675406/extract-overlay-ramdisk-i7jmzdz3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/675406/extract-overlay-ramdisk-i7jmzdz3/ramdisk.cpio.gz.uboot
218 02:42:22.589769 output: Image Name:
219 02:42:22.590266 output: Created: Fri Aug 30 02:42:22 2024
220 02:42:22.590518 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 02:42:22.591056 output: Data Size: 26566493 Bytes = 25943.84 KiB = 25.34 MiB
222 02:42:22.591616 output: Load Address: 00000000
223 02:42:22.592211 output: Entry Point: 00000000
224 02:42:22.592739 output:
225 02:42:22.593890 rename /var/lib/lava/dispatcher/tmp/675406/extract-overlay-ramdisk-i7jmzdz3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/ramdisk/ramdisk.cpio.gz.uboot
226 02:42:22.594807 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 02:42:22.595492 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 02:42:22.596196 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 02:42:22.596826 No LXC device requested
230 02:42:22.597527 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 02:42:22.598221 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 02:42:22.598854 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 02:42:22.599380 Checking files for TFTP limit of 4294967296 bytes.
234 02:42:22.602979 end: 1 tftp-deploy (duration 00:00:16) [common]
235 02:42:22.603773 start: 2 uboot-action (timeout 00:05:00) [common]
236 02:42:22.604495 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 02:42:22.605151 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 02:42:22.605806 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 02:42:22.606525 Using kernel file from prepare-kernel: 675406/tftp-deploy-wz6fmwbn/kernel/uImage
240 02:42:22.607351 substitutions:
241 02:42:22.607938 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 02:42:22.608564 - {DTB_ADDR}: 0x01070000
243 02:42:22.609087 - {DTB}: 675406/tftp-deploy-wz6fmwbn/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 02:42:22.609599 - {INITRD}: 675406/tftp-deploy-wz6fmwbn/ramdisk/ramdisk.cpio.gz.uboot
245 02:42:22.610111 - {KERNEL_ADDR}: 0x01080000
246 02:42:22.610613 - {KERNEL}: 675406/tftp-deploy-wz6fmwbn/kernel/uImage
247 02:42:22.611118 - {LAVA_MAC}: None
248 02:42:22.611676 - {PRESEED_CONFIG}: None
249 02:42:22.612286 - {PRESEED_LOCAL}: None
250 02:42:22.612813 - {RAMDISK_ADDR}: 0x08000000
251 02:42:22.613361 - {RAMDISK}: 675406/tftp-deploy-wz6fmwbn/ramdisk/ramdisk.cpio.gz.uboot
252 02:42:22.613925 - {ROOT_PART}: None
253 02:42:22.614513 - {ROOT}: None
254 02:42:22.615077 - {SERVER_IP}: 192.168.6.2
255 02:42:22.615605 - {TEE_ADDR}: 0x83000000
256 02:42:22.616158 - {TEE}: None
257 02:42:22.616668 Parsed boot commands:
258 02:42:22.617167 - setenv autoload no
259 02:42:22.617670 - setenv initrd_high 0xffffffff
260 02:42:22.618174 - setenv fdt_high 0xffffffff
261 02:42:22.618705 - dhcp
262 02:42:22.619273 - setenv serverip 192.168.6.2
263 02:42:22.619817 - tftpboot 0x01080000 675406/tftp-deploy-wz6fmwbn/kernel/uImage
264 02:42:22.620377 - tftpboot 0x08000000 675406/tftp-deploy-wz6fmwbn/ramdisk/ramdisk.cpio.gz.uboot
265 02:42:22.620905 - tftpboot 0x01070000 675406/tftp-deploy-wz6fmwbn/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 02:42:22.621417 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 02:42:22.621940 - bootm 0x01080000 0x08000000 0x01070000
268 02:42:22.623039 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 02:42:22.625191 start: 2.3 connect-device (timeout 00:05:00) [common]
271 02:42:22.625845 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 02:42:22.642529 Setting prompt string to ['lava-test: # ']
273 02:42:22.644497 end: 2.3 connect-device (duration 00:00:00) [common]
274 02:42:22.645306 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 02:42:22.646062 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 02:42:22.646876 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 02:42:22.648532 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 02:42:22.699171 >> OK - accepted request
279 02:42:22.701370 Returned 0 in 0 seconds
280 02:42:22.802518 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 02:42:22.804217 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 02:42:22.804784 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 02:42:22.805283 Setting prompt string to ['Hit any key to stop autoboot']
285 02:42:22.805722 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 02:42:22.807293 Trying 192.168.56.21...
287 02:42:22.807772 Connected to conserv1.
288 02:42:22.808223 Escape character is '^]'.
289 02:42:22.808640
290 02:42:22.809058 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 02:42:22.809481
292 02:42:30.450315 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 02:42:30.450966 bl2_stage_init 0x01
294 02:42:30.451402 bl2_stage_init 0x81
295 02:42:30.456060 hw id: 0x0000 - pwm id 0x01
296 02:42:30.456523 bl2_stage_init 0xc1
297 02:42:30.461841 bl2_stage_init 0x02
298 02:42:30.462432
299 02:42:30.462862 L0:00000000
300 02:42:30.463273 L1:00000703
301 02:42:30.463664 L2:00008067
302 02:42:30.464100 L3:15000000
303 02:42:30.466330 S1:00000000
304 02:42:30.466835 B2:20282000
305 02:42:30.467273 B1:a0f83180
306 02:42:30.467698
307 02:42:30.468155 TE: 68253
308 02:42:30.468556
309 02:42:30.471718 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 02:42:30.472209
311 02:42:30.477270 Board ID = 1
312 02:42:30.477839 Set cpu clk to 24M
313 02:42:30.478247 Set clk81 to 24M
314 02:42:30.482797 Use GP1_pll as DSU clk.
315 02:42:30.483272 DSU clk: 1200 Mhz
316 02:42:30.483670 CPU clk: 1200 MHz
317 02:42:30.488396 Set clk81 to 166.6M
318 02:42:30.493930 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 02:42:30.494460 board id: 1
320 02:42:30.500728 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 02:42:30.511706 fw parse done
322 02:42:30.517661 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 02:42:30.560334 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 02:42:30.571132 PIEI prepare done
325 02:42:30.571573 fastboot data load
326 02:42:30.571972 fastboot data verify
327 02:42:30.576815 verify result: 266
328 02:42:30.582371 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 02:42:30.582843 LPDDR4 probe
330 02:42:30.583239 ddr clk to 1584MHz
331 02:42:30.589465 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 02:42:30.627608
333 02:42:30.628123 dmc_version 0001
334 02:42:30.634293 Check phy result
335 02:42:30.640223 INFO : End of CA training
336 02:42:30.640699 INFO : End of initialization
337 02:42:30.645767 INFO : Training has run successfully!
338 02:42:30.646221 Check phy result
339 02:42:30.651423 INFO : End of initialization
340 02:42:30.651871 INFO : End of read enable training
341 02:42:30.657001 INFO : End of fine write leveling
342 02:42:30.662591 INFO : End of Write leveling coarse delay
343 02:42:30.663043 INFO : Training has run successfully!
344 02:42:30.663437 Check phy result
345 02:42:30.668306 INFO : End of initialization
346 02:42:30.668765 INFO : End of read dq deskew training
347 02:42:30.673815 INFO : End of MPR read delay center optimization
348 02:42:30.679487 INFO : End of write delay center optimization
349 02:42:30.685053 INFO : End of read delay center optimization
350 02:42:30.685518 INFO : End of max read latency training
351 02:42:30.690616 INFO : Training has run successfully!
352 02:42:30.691089 1D training succeed
353 02:42:30.698761 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 02:42:30.747385 Check phy result
355 02:42:30.747883 INFO : End of initialization
356 02:42:30.769749 INFO : End of 2D read delay Voltage center optimization
357 02:42:30.788904 INFO : End of 2D read delay Voltage center optimization
358 02:42:30.840789 INFO : End of 2D write delay Voltage center optimization
359 02:42:30.889974 INFO : End of 2D write delay Voltage center optimization
360 02:42:30.895516 INFO : Training has run successfully!
361 02:42:30.896021
362 02:42:30.896444 channel==0
363 02:42:30.901111 RxClkDly_Margin_A0==88 ps 9
364 02:42:30.901570 TxDqDly_Margin_A0==98 ps 10
365 02:42:30.904486 RxClkDly_Margin_A1==88 ps 9
366 02:42:30.904946 TxDqDly_Margin_A1==88 ps 9
367 02:42:30.910072 TrainedVREFDQ_A0==75
368 02:42:30.910529 TrainedVREFDQ_A1==75
369 02:42:30.910937 VrefDac_Margin_A0==24
370 02:42:30.915653 DeviceVref_Margin_A0==39
371 02:42:30.916130 VrefDac_Margin_A1==23
372 02:42:30.921282 DeviceVref_Margin_A1==39
373 02:42:30.921773
374 02:42:30.922197
375 02:42:30.922609 channel==1
376 02:42:30.923020 RxClkDly_Margin_A0==78 ps 8
377 02:42:30.924683 TxDqDly_Margin_A0==98 ps 10
378 02:42:30.930187 RxClkDly_Margin_A1==88 ps 9
379 02:42:30.930651 TxDqDly_Margin_A1==88 ps 9
380 02:42:30.931060 TrainedVREFDQ_A0==78
381 02:42:30.935851 TrainedVREFDQ_A1==75
382 02:42:30.936338 VrefDac_Margin_A0==22
383 02:42:30.941515 DeviceVref_Margin_A0==36
384 02:42:30.941981 VrefDac_Margin_A1==22
385 02:42:30.942389 DeviceVref_Margin_A1==39
386 02:42:30.942789
387 02:42:30.950552 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 02:42:30.951015
389 02:42:30.976219 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000016 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 02:42:30.981777 2D training succeed
391 02:42:30.985147 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 02:42:30.990757 auto size-- 65535DDR cs0 size: 2048MB
393 02:42:30.991225 DDR cs1 size: 2048MB
394 02:42:30.996484 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 02:42:30.996968 cs0 DataBus test pass
396 02:42:31.001993 cs1 DataBus test pass
397 02:42:31.002424 cs0 AddrBus test pass
398 02:42:31.002823 cs1 AddrBus test pass
399 02:42:31.003214
400 02:42:31.007560 100bdlr_step_size ps== 478
401 02:42:31.008071 result report
402 02:42:31.013145 boot times 0Enable ddr reg access
403 02:42:31.017321 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 02:42:31.031433 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 02:42:31.686276 bl2z: ptr: 05129330, size: 00001e40
406 02:42:31.693400 0.0;M3 CHK:0;cm4_sp_mode 0
407 02:42:31.693859 MVN_1=0x00000000
408 02:42:31.694277 MVN_2=0x00000000
409 02:42:31.704846 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 02:42:31.705288 OPS=0x04
411 02:42:31.705700 ring efuse init
412 02:42:31.710464 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 02:42:31.710902 [0.017319 Inits done]
414 02:42:31.711303 secure task start!
415 02:42:31.718161 high task start!
416 02:42:31.718594 low task start!
417 02:42:31.718999 run into bl31
418 02:42:31.726764 NOTICE: BL31: v1.3(release):4fc40b1
419 02:42:31.734570 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 02:42:31.735023 NOTICE: BL31: G12A normal boot!
421 02:42:31.750116 NOTICE: BL31: BL33 decompress pass
422 02:42:31.755788 ERROR: Error initializing runtime service opteed_fast
423 02:42:33.002338 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 02:42:33.002719 bl2_stage_init 0x01
425 02:42:33.002935 bl2_stage_init 0x81
426 02:42:33.007945 hw id: 0x0000 - pwm id 0x01
427 02:42:33.008565 bl2_stage_init 0xc1
428 02:42:33.013680 bl2_stage_init 0x02
429 02:42:33.014007
430 02:42:33.014239 L0:00000000
431 02:42:33.014444 L1:00000703
432 02:42:33.014648 L2:00008067
433 02:42:33.014848 L3:15000000
434 02:42:33.019130 S1:00000000
435 02:42:33.019436 B2:20282000
436 02:42:33.019649 B1:a0f83180
437 02:42:33.019859
438 02:42:33.020109 TE: 70047
439 02:42:33.020338
440 02:42:33.025484 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 02:42:33.026317
442 02:42:33.034087 Board ID = 1
443 02:42:33.034728 Set cpu clk to 24M
444 02:42:33.035203 Set clk81 to 24M
445 02:42:33.036510 Use GP1_pll as DSU clk.
446 02:42:33.037262 DSU clk: 1200 Mhz
447 02:42:33.037798 CPU clk: 1200 MHz
448 02:42:33.041827 Set clk81 to 166.6M
449 02:42:33.047232 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 02:42:33.047672 board id: 1
451 02:42:33.055182 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 02:42:33.065392 fw parse done
453 02:42:33.071387 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 02:42:33.115229 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 02:42:33.125769 PIEI prepare done
456 02:42:33.126599 fastboot data load
457 02:42:33.127224 fastboot data verify
458 02:42:33.131589 verify result: 266
459 02:42:33.136768 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 02:42:33.137402 LPDDR4 probe
461 02:42:33.137922 ddr clk to 1584MHz
462 02:42:34.502308 Load ddrfw from SPI, src: 0x00018000, des SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 02:42:34.502753 bl2_stage_init 0x01
464 02:42:34.502982 bl2_stage_init 0x81
465 02:42:34.507862 hw id: 0x0000 - pwm id 0x01
466 02:42:34.508212 bl2_stage_init 0xc1
467 02:42:34.513438 bl2_stage_init 0x02
468 02:42:34.513737
469 02:42:34.513959 L0:00000000
470 02:42:34.514166 L1:00000703
471 02:42:34.514376 L2:00008067
472 02:42:34.514580 L3:15000000
473 02:42:34.519053 S1:00000000
474 02:42:34.519350 B2:20282000
475 02:42:34.519566 B1:a0f83180
476 02:42:34.519772
477 02:42:34.519976 TE: 71655
478 02:42:34.520211
479 02:42:34.524688 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 02:42:34.524993
481 02:42:34.530259 Board ID = 1
482 02:42:34.530587 Set cpu clk to 24M
483 02:42:34.530805 Set clk81 to 24M
484 02:42:34.535847 Use GP1_pll as DSU clk.
485 02:42:34.536164 DSU clk: 1200 Mhz
486 02:42:34.536384 CPU clk: 1200 MHz
487 02:42:34.541434 Set clk81 to 166.6M
488 02:42:34.547015 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 02:42:34.547306 board id: 1
490 02:42:34.554231 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 02:42:34.565159 fw parse done
492 02:42:34.571093 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 02:42:34.614207 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 02:42:34.625323 PIEI prepare done
495 02:42:34.625643 fastboot data load
496 02:42:34.625865 fastboot data verify
497 02:42:34.630953 verify result: 266
498 02:42:34.636507 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 02:42:34.636801 LPDDR4 probe
500 02:42:34.637018 ddr clk to 1584MHz
501 02:42:34.644535 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 02:42:34.681362
503 02:42:34.681719 dmc_version 0001
504 02:42:34.688390 Check phy result
505 02:42:34.695347 INFO : End of CA training
506 02:42:34.695647 INFO : End of initialization
507 02:42:34.700933 INFO : Training has run successfully!
508 02:42:34.701254 Check phy result
509 02:42:34.706469 INFO : End of initialization
510 02:42:34.706768 INFO : End of read enable training
511 02:42:34.709872 INFO : End of fine write leveling
512 02:42:34.715286 INFO : End of Write leveling coarse delay
513 02:42:34.720958 INFO : Training has run successfully!
514 02:42:34.721253 Check phy result
515 02:42:34.721489 INFO : End of initialization
516 02:42:34.726594 INFO : End of read dq deskew training
517 02:42:34.729994 INFO : End of MPR read delay center optimization
518 02:42:34.735606 INFO : End of write delay center optimization
519 02:42:34.741192 INFO : End of read delay center optimization
520 02:42:34.741488 INFO : End of max read latency training
521 02:42:34.746864 INFO : Training has run successfully!
522 02:42:34.747160 1D training succeed
523 02:42:34.754940 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 02:42:34.802851 Check phy result
525 02:42:34.803182 INFO : End of initialization
526 02:42:34.830575 INFO : End of 2D read delay Voltage center optimization
527 02:42:34.853820 INFO : End of 2D read delay Voltage center optimization
528 02:42:34.910468 INFO : End of 2D write delay Voltage center optimization
529 02:42:34.965389 INFO : End of 2D write delay Voltage center optimization
530 02:42:34.970957 INFO : Training has run successfully!
531 02:42:34.971257
532 02:42:34.971470 channel==0
533 02:42:34.976538 RxClkDly_Margin_A0==78 ps 8
534 02:42:34.976838 TxDqDly_Margin_A0==98 ps 10
535 02:42:34.979944 RxClkDly_Margin_A1==88 ps 9
536 02:42:34.980261 TxDqDly_Margin_A1==88 ps 9
537 02:42:34.985477 TrainedVREFDQ_A0==75
538 02:42:34.985790 TrainedVREFDQ_A1==74
539 02:42:34.986003 VrefDac_Margin_A0==24
540 02:42:34.991068 DeviceVref_Margin_A0==39
541 02:42:34.991362 VrefDac_Margin_A1==23
542 02:42:34.996693 DeviceVref_Margin_A1==40
543 02:42:34.997031
544 02:42:34.997247
545 02:42:34.997451 channel==1
546 02:42:34.997649 RxClkDly_Margin_A0==88 ps 9
547 02:42:35.002284 TxDqDly_Margin_A0==98 ps 10
548 02:42:35.002583 RxClkDly_Margin_A1==88 ps 9
549 02:42:35.007881 TxDqDly_Margin_A1==78 ps 8
550 02:42:35.008195 TrainedVREFDQ_A0==78
551 02:42:35.008408 TrainedVREFDQ_A1==75
552 02:42:35.013469 VrefDac_Margin_A0==23
553 02:42:35.013769 DeviceVref_Margin_A0==36
554 02:42:35.019108 VrefDac_Margin_A1==22
555 02:42:35.019421 DeviceVref_Margin_A1==39
556 02:42:35.019634
557 02:42:35.024697 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 02:42:35.025013
559 02:42:35.052678 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
560 02:42:35.058276 2D training succeed
561 02:42:35.063908 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 02:42:35.064223 auto size-- 65535DDR cs0 size: 2048MB
563 02:42:35.069488 DDR cs1 size: 2048MB
564 02:42:35.069803 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 02:42:35.075101 cs0 DataBus test pass
566 02:42:35.075431 cs1 DataBus test pass
567 02:42:35.075653 cs0 AddrBus test pass
568 02:42:35.080780 cs1 AddrBus test pass
569 02:42:35.081107
570 02:42:35.081327 100bdlr_step_size ps== 478
571 02:42:35.081539 result report
572 02:42:35.086285 boot times 0Enable ddr reg access
573 02:42:35.093748 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 02:42:35.106614 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 02:42:35.767272 bl2z: ptr: 05129330, size: 00001e40
576 02:42:35.775537 0.0;M3 CHK:0;cm4_sp_mode 0
577 02:42:35.776024 MVN_1=0x00000000
578 02:42:35.776293 MVN_2=0x00000000
579 02:42:35.786869 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 02:42:35.787207 OPS=0x04
581 02:42:35.787423 ring efuse init
582 02:42:35.789878 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 02:42:35.796209 [0.017354 Inits done]
584 02:42:35.796603 secure task start!
585 02:42:35.796936 high task start!
586 02:42:35.797251 low task start!
587 02:42:35.800358 run into bl31
588 02:42:35.809020 NOTICE: BL31: v1.3(release):4fc40b1
589 02:42:35.816566 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 02:42:35.816876 NOTICE: BL31: G12A normal boot!
591 02:42:35.832755 NOTICE: BL31: BL33 decompress pass
592 02:42:35.837203 ERROR: Error initializing runtime service opteed_fast
593 02:42:37.053354 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 02:42:37.053959 bl2_stage_init 0x01
595 02:42:37.054391 bl2_stage_init 0x81
596 02:42:37.058805 hw id: 0x0000 - pwm id 0x01
597 02:42:37.059303 bl2_stage_init 0xc1
598 02:42:37.064312 bl2_stage_init 0x02
599 02:42:37.064781
600 02:42:37.065196 L0:00000000
601 02:42:37.065595 L1:00000703
602 02:42:37.065988 L2:00008067
603 02:42:37.066381 L3:15000000
604 02:42:37.069814 S1:00000000
605 02:42:37.070285 B2:20282000
606 02:42:37.070692 B1:a0f83180
607 02:42:37.071088
608 02:42:37.071505 TE: 72186
609 02:42:37.071931
610 02:42:37.075551 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 02:42:37.076058
612 02:42:37.081160 Board ID = 1
613 02:42:37.081659 Set cpu clk to 24M
614 02:42:37.082067 Set clk81 to 24M
615 02:42:37.086759 Use GP1_pll as DSU clk.
616 02:42:37.087224 DSU clk: 1200 Mhz
617 02:42:37.087633 CPU clk: 1200 MHz
618 02:42:37.092327 Set clk81 to 166.6M
619 02:42:37.097969 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 02:42:37.098466 board id: 1
621 02:42:37.105134 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 02:42:37.115773 fw parse done
623 02:42:37.120934 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 02:42:37.164222 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 02:42:37.175302 PIEI prepare done
626 02:42:37.175777 fastboot data load
627 02:42:37.176236 fastboot data verify
628 02:42:37.180888 verify result: 266
629 02:42:37.186468 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 02:42:37.186975 LPDDR4 probe
631 02:42:37.187388 ddr clk to 1584MHz
632 02:42:37.194401 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 02:42:37.231690
634 02:42:37.232253 dmc_version 0001
635 02:42:37.238359 Check phy result
636 02:42:37.244311 INFO : End of CA training
637 02:42:37.244782 INFO : End of initialization
638 02:42:37.249830 INFO : Training has run successfully!
639 02:42:37.250313 Check phy result
640 02:42:37.255404 INFO : End of initialization
641 02:42:37.255884 INFO : End of read enable training
642 02:42:37.261056 INFO : End of fine write leveling
643 02:42:37.266689 INFO : End of Write leveling coarse delay
644 02:42:37.267179 INFO : Training has run successfully!
645 02:42:37.267594 Check phy result
646 02:42:37.272343 INFO : End of initialization
647 02:42:37.272809 INFO : End of read dq deskew training
648 02:42:37.277859 INFO : End of MPR read delay center optimization
649 02:42:37.283438 INFO : End of write delay center optimization
650 02:42:37.289060 INFO : End of read delay center optimization
651 02:42:37.289541 INFO : End of max read latency training
652 02:42:37.294660 INFO : Training has run successfully!
653 02:42:37.295123 1D training succeed
654 02:42:37.303800 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 02:42:37.351551 Check phy result
656 02:42:37.352120 INFO : End of initialization
657 02:42:37.373764 INFO : End of 2D read delay Voltage center optimization
658 02:42:37.392955 INFO : End of 2D read delay Voltage center optimization
659 02:42:37.444783 INFO : End of 2D write delay Voltage center optimization
660 02:42:37.493975 INFO : End of 2D write delay Voltage center optimization
661 02:42:37.499573 INFO : Training has run successfully!
662 02:42:37.500266
663 02:42:37.500732 channel==0
664 02:42:37.505207 RxClkDly_Margin_A0==78 ps 8
665 02:42:37.505689 TxDqDly_Margin_A0==98 ps 10
666 02:42:37.510847 RxClkDly_Margin_A1==88 ps 9
667 02:42:37.511333 TxDqDly_Margin_A1==98 ps 10
668 02:42:37.511751 TrainedVREFDQ_A0==74
669 02:42:37.516371 TrainedVREFDQ_A1==74
670 02:42:37.516838 VrefDac_Margin_A0==24
671 02:42:37.517245 DeviceVref_Margin_A0==40
672 02:42:37.521968 VrefDac_Margin_A1==23
673 02:42:37.522430 DeviceVref_Margin_A1==40
674 02:42:37.522834
675 02:42:37.523234
676 02:42:37.527562 channel==1
677 02:42:37.528047 RxClkDly_Margin_A0==88 ps 9
678 02:42:37.528454 TxDqDly_Margin_A0==88 ps 9
679 02:42:37.533182 RxClkDly_Margin_A1==88 ps 9
680 02:42:37.533643 TxDqDly_Margin_A1==88 ps 9
681 02:42:37.538762 TrainedVREFDQ_A0==75
682 02:42:37.539224 TrainedVREFDQ_A1==78
683 02:42:37.539632 VrefDac_Margin_A0==23
684 02:42:37.544416 DeviceVref_Margin_A0==39
685 02:42:37.544871 VrefDac_Margin_A1==22
686 02:42:37.549966 DeviceVref_Margin_A1==36
687 02:42:37.550459
688 02:42:37.550896 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 02:42:37.551299
690 02:42:37.583513 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
691 02:42:37.584047 2D training succeed
692 02:42:37.589264 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 02:42:37.594771 auto size-- 65535DDR cs0 size: 2048MB
694 02:42:37.595238 DDR cs1 size: 2048MB
695 02:42:37.600351 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 02:42:37.600810 cs0 DataBus test pass
697 02:42:37.606060 cs1 DataBus test pass
698 02:42:37.606596 cs0 AddrBus test pass
699 02:42:37.607005 cs1 AddrBus test pass
700 02:42:37.607402
701 02:42:37.611538 100bdlr_step_size ps== 471
702 02:42:37.612040 result report
703 02:42:37.617150 boot times 0Enable ddr reg access
704 02:42:37.622298 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 02:42:37.636115 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 02:42:38.291045 bl2z: ptr: 05129330, size: 00001e40
707 02:42:38.298572 0.0;M3 CHK:0;cm4_sp_mode 0
708 02:42:38.299003 MVN_1=0x00000000
709 02:42:38.299254 MVN_2=0x00000000
710 02:42:38.310492 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 02:42:38.312331 OPS=0x04
712 02:42:38.312899 ring efuse init
713 02:42:38.315693 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 02:42:38.316268 [0.017319 Inits done]
715 02:42:38.316670 secure task start!
716 02:42:38.323434 high task start!
717 02:42:38.323845 low task start!
718 02:42:38.324213 run into bl31
719 02:42:38.334189 NOTICE: BL31: v1.3(release):4fc40b1
720 02:42:38.341408 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 02:42:38.341992 NOTICE: BL31: G12A normal boot!
722 02:42:38.355405 NOTICE: BL31: BL33 decompress pass
723 02:42:38.360906 ERROR: Error initializing runtime service opteed_fast
724 02:42:39.156319
725 02:42:39.156953
726 02:42:39.161791 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 02:42:39.162277
728 02:42:39.165266 Model: Libre Computer AML-S905D3-CC Solitude
729 02:42:39.312245 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 02:42:39.327658 DRAM: 2 GiB (effective 3.8 GiB)
731 02:42:39.428619 Core: 406 devices, 33 uclasses, devicetree: separate
732 02:42:39.434599 WDT: Not starting watchdog@f0d0
733 02:42:39.459553 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 02:42:39.471779 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 02:42:39.476789 ** Bad device specification mmc 0 **
736 02:42:39.486823 Card did not respond to voltage select! : -110
737 02:42:39.494649 ** Bad device specification mmc 0 **
738 02:42:39.495149 Couldn't find partition mmc 0
739 02:42:39.502859 Card did not respond to voltage select! : -110
740 02:42:39.508405 ** Bad device specification mmc 0 **
741 02:42:39.508874 Couldn't find partition mmc 0
742 02:42:39.513477 Error: could not access storage.
743 02:42:39.809848 Net: eth0: ethernet@ff3f0000
744 02:42:39.810422 starting USB...
745 02:42:40.054447 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 02:42:40.055002 Starting the controller
747 02:42:40.061478 USB XHCI 1.10
748 02:42:41.615723 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 02:42:41.624070 scanning usb for storage devices... 0 Storage Device(s) found
751 02:42:41.675539 Hit any key to stop autoboot: 1
752 02:42:41.676575 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 02:42:41.677191 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 02:42:41.677665 Setting prompt string to ['=>']
755 02:42:41.678138 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 02:42:41.690075 0
757 02:42:41.690967 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 02:42:41.792180 => setenv autoload no
760 02:42:41.793133 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 02:42:41.797937 setenv autoload no
763 02:42:41.899354 => setenv initrd_high 0xffffffff
764 02:42:41.900227 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 02:42:41.904423 setenv initrd_high 0xffffffff
767 02:42:42.005839 => setenv fdt_high 0xffffffff
768 02:42:42.006684 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 02:42:42.010991 setenv fdt_high 0xffffffff
771 02:42:42.112467 => dhcp
772 02:42:42.113318 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
773 02:42:42.117235 dhcp
774 02:42:42.972910 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 02:42:42.973287 Speed: 1000, full duplex
776 02:42:42.973496 BOOTP broadcast 1
777 02:42:43.221454 BOOTP broadcast 2
778 02:42:43.733304 BOOTP broadcast 3
779 02:42:44.723336 BOOTP broadcast 4
780 02:42:46.724233 BOOTP broadcast 5
781 02:42:46.737651 DHCP client bound to address 192.168.6.12 (3764 ms)
783 02:42:46.839138 => setenv serverip 192.168.6.2
784 02:42:46.840039 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
785 02:42:46.844187 setenv serverip 192.168.6.2
787 02:42:46.945609 => tftpboot 0x01080000 675406/tftp-deploy-wz6fmwbn/kernel/uImage
788 02:42:46.946421 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
789 02:42:46.952652 tftpboot 0x01080000 675406/tftp-deploy-wz6fmwbn/kernel/uImage
790 02:42:46.952949 Speed: 1000, full duplex
791 02:42:46.953165 Using ethernet@ff3f0000 device
792 02:42:46.958142 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 02:42:46.963679 Filename '675406/tftp-deploy-wz6fmwbn/kernel/uImage'.
794 02:42:46.967562 Load address: 0x1080000
795 02:42:49.468051 Loading: *################################################## 37.2 MiB
796 02:42:49.468484 14.9 MiB/s
797 02:42:49.468698 done
798 02:42:49.472432 Bytes transferred = 39019072 (2536240 hex)
800 02:42:49.573485 => tftpboot 0x08000000 675406/tftp-deploy-wz6fmwbn/ramdisk/ramdisk.cpio.gz.uboot
801 02:42:49.574032 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
802 02:42:49.580673 tftpboot 0x08000000 675406/tftp-deploy-wz6fmwbn/ramdisk/ramdisk.cpio.gz.uboot
803 02:42:49.580981 Speed: 1000, full duplex
804 02:42:49.581188 Using ethernet@ff3f0000 device
805 02:42:49.586172 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
806 02:42:49.595896 Filename '675406/tftp-deploy-wz6fmwbn/ramdisk/ramdisk.cpio.gz.uboot'.
807 02:42:49.596268 Load address: 0x8000000
808 02:42:51.217017 Loading: *################################################# UDP wrong checksum 00000005 00002614
809 02:42:56.217277 T UDP wrong checksum 00000005 00002614
810 02:43:06.218454 T T UDP wrong checksum 00000005 00002614
811 02:43:26.222891 T T T T UDP wrong checksum 00000005 00002614
812 02:43:34.639609 T UDP wrong checksum 000000ff 0000c7f3
813 02:43:34.688919 UDP wrong checksum 000000ff 00004ee6
814 02:43:46.227277 T T
815 02:43:46.227909 Retry count exceeded; starting again
817 02:43:46.229404 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
820 02:43:46.231286 end: 2.4 uboot-commands (duration 00:01:24) [common]
822 02:43:46.232825 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
824 02:43:46.233839 end: 2 uboot-action (duration 00:01:24) [common]
826 02:43:46.235332 Cleaning after the job
827 02:43:46.235875 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/ramdisk
828 02:43:46.237572 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/kernel
829 02:43:46.278856 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/dtb
830 02:43:46.280937 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675406/tftp-deploy-wz6fmwbn/modules
831 02:43:46.312139 start: 4.1 power-off (timeout 00:00:30) [common]
832 02:43:46.312810 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
833 02:43:46.345147 >> OK - accepted request
834 02:43:46.347150 Returned 0 in 0 seconds
835 02:43:46.447850 end: 4.1 power-off (duration 00:00:00) [common]
837 02:43:46.448774 start: 4.2 read-feedback (timeout 00:10:00) [common]
838 02:43:46.449413 Listened to connection for namespace 'common' for up to 1s
839 02:43:47.450349 Finalising connection for namespace 'common'
840 02:43:47.450871 Disconnecting from shell: Finalise
841 02:43:47.451165 =>
842 02:43:47.551901 end: 4.2 read-feedback (duration 00:00:01) [common]
843 02:43:47.552636 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/675406
844 02:43:47.836002 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/675406
845 02:43:47.836611 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.