Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:48:45.467146 lava-dispatcher, installed at version: 2024.01
2 02:48:45.467951 start: 0 validate
3 02:48:45.468459 Start time: 2024-08-30 02:48:45.468428+00:00 (UTC)
4 02:48:45.468998 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:48:45.469545 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:48:45.511103 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:48:45.511663 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-151-g1b5fe53681d9%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 02:48:45.540688 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:48:45.541286 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-151-g1b5fe53681d9%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:48:45.575037 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:48:45.575543 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:48:45.608634 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:48:45.609113 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-151-g1b5fe53681d9%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
14 02:48:45.649700 validate duration: 0.18
16 02:48:45.651180 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:48:45.651781 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:48:45.652417 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:48:45.653495 Not decompressing ramdisk as can be used compressed.
20 02:48:45.654263 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 02:48:45.654774 saving as /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/ramdisk/initrd.cpio.gz
22 02:48:45.655270 total size: 5628182 (5 MB)
23 02:48:45.698453 progress 0 % (0 MB)
24 02:48:45.710135 progress 5 % (0 MB)
25 02:48:45.717857 progress 10 % (0 MB)
26 02:48:45.724749 progress 15 % (0 MB)
27 02:48:45.732233 progress 20 % (1 MB)
28 02:48:45.736623 progress 25 % (1 MB)
29 02:48:45.741470 progress 30 % (1 MB)
30 02:48:45.746526 progress 35 % (1 MB)
31 02:48:45.751124 progress 40 % (2 MB)
32 02:48:45.756254 progress 45 % (2 MB)
33 02:48:45.760816 progress 50 % (2 MB)
34 02:48:45.765732 progress 55 % (2 MB)
35 02:48:45.770793 progress 60 % (3 MB)
36 02:48:45.775059 progress 65 % (3 MB)
37 02:48:45.778996 progress 70 % (3 MB)
38 02:48:45.782698 progress 75 % (4 MB)
39 02:48:45.786938 progress 80 % (4 MB)
40 02:48:45.790399 progress 85 % (4 MB)
41 02:48:45.794087 progress 90 % (4 MB)
42 02:48:45.797709 progress 95 % (5 MB)
43 02:48:45.801266 progress 100 % (5 MB)
44 02:48:45.801948 5 MB downloaded in 0.15 s (36.60 MB/s)
45 02:48:45.802521 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:48:45.803434 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:48:45.803742 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:48:45.804045 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:48:45.804732 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
51 02:48:45.805033 saving as /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/kernel/Image
52 02:48:45.805255 total size: 39019008 (37 MB)
53 02:48:45.805474 No compression specified
54 02:48:45.843793 progress 0 % (0 MB)
55 02:48:45.867659 progress 5 % (1 MB)
56 02:48:45.891683 progress 10 % (3 MB)
57 02:48:45.914924 progress 15 % (5 MB)
58 02:48:45.938431 progress 20 % (7 MB)
59 02:48:45.961261 progress 25 % (9 MB)
60 02:48:45.984843 progress 30 % (11 MB)
61 02:48:46.007638 progress 35 % (13 MB)
62 02:48:46.030799 progress 40 % (14 MB)
63 02:48:46.053614 progress 45 % (16 MB)
64 02:48:46.076767 progress 50 % (18 MB)
65 02:48:46.100061 progress 55 % (20 MB)
66 02:48:46.123332 progress 60 % (22 MB)
67 02:48:46.146290 progress 65 % (24 MB)
68 02:48:46.169455 progress 70 % (26 MB)
69 02:48:46.192932 progress 75 % (27 MB)
70 02:48:46.215748 progress 80 % (29 MB)
71 02:48:46.238833 progress 85 % (31 MB)
72 02:48:46.261494 progress 90 % (33 MB)
73 02:48:46.284875 progress 95 % (35 MB)
74 02:48:46.306493 progress 100 % (37 MB)
75 02:48:46.307219 37 MB downloaded in 0.50 s (74.13 MB/s)
76 02:48:46.307697 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:48:46.308575 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:48:46.308850 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:48:46.309113 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:48:46.309590 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:48:46.309840 saving as /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:48:46.310046 total size: 54667 (0 MB)
84 02:48:46.310255 No compression specified
85 02:48:46.347314 progress 59 % (0 MB)
86 02:48:46.348201 progress 100 % (0 MB)
87 02:48:46.348764 0 MB downloaded in 0.04 s (1.35 MB/s)
88 02:48:46.349228 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:48:46.350043 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:48:46.350304 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:48:46.350565 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:48:46.351048 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 02:48:46.351292 saving as /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/nfsrootfs/full.rootfs.tar
95 02:48:46.351499 total size: 107552908 (102 MB)
96 02:48:46.351707 Using unxz to decompress xz
97 02:48:46.385497 progress 0 % (0 MB)
98 02:48:47.042497 progress 5 % (5 MB)
99 02:48:47.779418 progress 10 % (10 MB)
100 02:48:48.497178 progress 15 % (15 MB)
101 02:48:49.249549 progress 20 % (20 MB)
102 02:48:49.815928 progress 25 % (25 MB)
103 02:48:50.433723 progress 30 % (30 MB)
104 02:48:51.164388 progress 35 % (35 MB)
105 02:48:51.515079 progress 40 % (41 MB)
106 02:48:51.936192 progress 45 % (46 MB)
107 02:48:52.620099 progress 50 % (51 MB)
108 02:48:53.317434 progress 55 % (56 MB)
109 02:48:54.073418 progress 60 % (61 MB)
110 02:48:54.842560 progress 65 % (66 MB)
111 02:48:55.693534 progress 70 % (71 MB)
112 02:48:56.455342 progress 75 % (76 MB)
113 02:48:57.126644 progress 80 % (82 MB)
114 02:48:57.823771 progress 85 % (87 MB)
115 02:48:58.542371 progress 90 % (92 MB)
116 02:48:59.242140 progress 95 % (97 MB)
117 02:48:59.975561 progress 100 % (102 MB)
118 02:48:59.987306 102 MB downloaded in 13.64 s (7.52 MB/s)
119 02:48:59.987856 end: 1.4.1 http-download (duration 00:00:14) [common]
121 02:48:59.989528 end: 1.4 download-retry (duration 00:00:14) [common]
122 02:48:59.990093 start: 1.5 download-retry (timeout 00:09:46) [common]
123 02:48:59.990650 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 02:48:59.991503 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-151-g1b5fe53681d9/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
125 02:48:59.992031 saving as /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/modules/modules.tar
126 02:48:59.992485 total size: 11626196 (11 MB)
127 02:48:59.992944 Using unxz to decompress xz
128 02:49:00.041288 progress 0 % (0 MB)
129 02:49:00.111465 progress 5 % (0 MB)
130 02:49:00.194560 progress 10 % (1 MB)
131 02:49:00.277873 progress 15 % (1 MB)
132 02:49:00.358645 progress 20 % (2 MB)
133 02:49:00.436903 progress 25 % (2 MB)
134 02:49:00.514097 progress 30 % (3 MB)
135 02:49:00.590567 progress 35 % (3 MB)
136 02:49:00.666332 progress 40 % (4 MB)
137 02:49:00.748882 progress 45 % (5 MB)
138 02:49:00.828943 progress 50 % (5 MB)
139 02:49:00.913114 progress 55 % (6 MB)
140 02:49:00.986627 progress 60 % (6 MB)
141 02:49:01.072289 progress 65 % (7 MB)
142 02:49:01.153589 progress 70 % (7 MB)
143 02:49:01.236017 progress 75 % (8 MB)
144 02:49:01.323748 progress 80 % (8 MB)
145 02:49:01.422126 progress 85 % (9 MB)
146 02:49:01.496462 progress 90 % (10 MB)
147 02:49:01.575496 progress 95 % (10 MB)
148 02:49:01.657547 progress 100 % (11 MB)
149 02:49:01.671063 11 MB downloaded in 1.68 s (6.61 MB/s)
150 02:49:01.671625 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:49:01.672943 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:49:01.673464 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 02:49:01.673973 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 02:49:11.486199 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/675417/extract-nfsrootfs-u_lpqv2e
156 02:49:11.486799 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 02:49:11.487087 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 02:49:11.487721 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev
159 02:49:11.488238 makedir: /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin
160 02:49:11.488590 makedir: /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/tests
161 02:49:11.488907 makedir: /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/results
162 02:49:11.489245 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-add-keys
163 02:49:11.489768 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-add-sources
164 02:49:11.490274 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-background-process-start
165 02:49:11.490769 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-background-process-stop
166 02:49:11.491313 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-common-functions
167 02:49:11.491827 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-echo-ipv4
168 02:49:11.492389 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-install-packages
169 02:49:11.492892 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-installed-packages
170 02:49:11.493367 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-os-build
171 02:49:11.493839 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-probe-channel
172 02:49:11.494314 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-probe-ip
173 02:49:11.494786 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-target-ip
174 02:49:11.495255 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-target-mac
175 02:49:11.495749 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-target-storage
176 02:49:11.496303 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-test-case
177 02:49:11.496795 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-test-event
178 02:49:11.497269 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-test-feedback
179 02:49:11.497738 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-test-raise
180 02:49:11.498204 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-test-reference
181 02:49:11.498675 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-test-runner
182 02:49:11.499146 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-test-set
183 02:49:11.499633 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-test-shell
184 02:49:11.500175 Updating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-install-packages (oe)
185 02:49:11.500718 Updating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/bin/lava-installed-packages (oe)
186 02:49:11.501168 Creating /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/environment
187 02:49:11.501541 LAVA metadata
188 02:49:11.501802 - LAVA_JOB_ID=675417
189 02:49:11.502017 - LAVA_DISPATCHER_IP=192.168.6.2
190 02:49:11.502374 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 02:49:11.503381 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 02:49:11.503694 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 02:49:11.503907 skipped lava-vland-overlay
194 02:49:11.504175 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 02:49:11.504434 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 02:49:11.504656 skipped lava-multinode-overlay
197 02:49:11.504899 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 02:49:11.505152 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 02:49:11.505402 Loading test definitions
200 02:49:11.505679 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 02:49:11.505900 Using /lava-675417 at stage 0
202 02:49:11.507053 uuid=675417_1.6.2.4.1 testdef=None
203 02:49:11.507355 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 02:49:11.507618 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 02:49:11.509449 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 02:49:11.510266 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 02:49:11.512522 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 02:49:11.513350 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 02:49:11.515481 runner path: /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/0/tests/0_dmesg test_uuid 675417_1.6.2.4.1
212 02:49:11.516058 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 02:49:11.516817 Creating lava-test-runner.conf files
215 02:49:11.517020 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/675417/lava-overlay-yfap9zev/lava-675417/0 for stage 0
216 02:49:11.517356 - 0_dmesg
217 02:49:11.517693 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 02:49:11.517965 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 02:49:11.539309 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 02:49:11.539681 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 02:49:11.539944 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 02:49:11.540238 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 02:49:11.540504 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 02:49:12.154269 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 02:49:12.154747 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 02:49:12.154993 extracting modules file /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/675417/extract-nfsrootfs-u_lpqv2e
227 02:49:13.668503 extracting modules file /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/675417/extract-overlay-ramdisk-0wti5nh5/ramdisk
228 02:49:15.102519 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 02:49:15.103015 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
230 02:49:15.103313 [common] Applying overlay to NFS
231 02:49:15.103543 [common] Applying overlay /var/lib/lava/dispatcher/tmp/675417/compress-overlay-w4dn941a/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/675417/extract-nfsrootfs-u_lpqv2e
232 02:49:15.132998 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 02:49:15.133426 start: 1.6.6 prepare-kernel (timeout 00:09:31) [common]
234 02:49:15.133702 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:31) [common]
235 02:49:15.133937 Converting downloaded kernel to a uImage
236 02:49:15.134250 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/kernel/Image /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/kernel/uImage
237 02:49:15.529422 output: Image Name:
238 02:49:15.529851 output: Created: Fri Aug 30 02:49:15 2024
239 02:49:15.530064 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 02:49:15.530270 output: Data Size: 39019008 Bytes = 38104.50 KiB = 37.21 MiB
241 02:49:15.530471 output: Load Address: 01080000
242 02:49:15.530672 output: Entry Point: 01080000
243 02:49:15.530869 output:
244 02:49:15.531200 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 02:49:15.531463 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 02:49:15.531730 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 02:49:15.532013 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 02:49:15.532289 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 02:49:15.532548 Building ramdisk /var/lib/lava/dispatcher/tmp/675417/extract-overlay-ramdisk-0wti5nh5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/675417/extract-overlay-ramdisk-0wti5nh5/ramdisk
250 02:49:17.747374 >> 171777 blocks
251 02:49:25.455604 Adding RAMdisk u-boot header.
252 02:49:25.456074 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/675417/extract-overlay-ramdisk-0wti5nh5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/675417/extract-overlay-ramdisk-0wti5nh5/ramdisk.cpio.gz.uboot
253 02:49:25.724206 output: Image Name:
254 02:49:25.724817 output: Created: Fri Aug 30 02:49:25 2024
255 02:49:25.725254 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 02:49:25.725672 output: Data Size: 23942449 Bytes = 23381.30 KiB = 22.83 MiB
257 02:49:25.726075 output: Load Address: 00000000
258 02:49:25.726476 output: Entry Point: 00000000
259 02:49:25.726874 output:
260 02:49:25.728068 rename /var/lib/lava/dispatcher/tmp/675417/extract-overlay-ramdisk-0wti5nh5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/ramdisk/ramdisk.cpio.gz.uboot
261 02:49:25.728813 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 02:49:25.729374 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 02:49:25.729920 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 02:49:25.730391 No LXC device requested
265 02:49:25.730909 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 02:49:25.731431 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 02:49:25.731936 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 02:49:25.732392 Checking files for TFTP limit of 4294967296 bytes.
269 02:49:25.735062 end: 1 tftp-deploy (duration 00:00:40) [common]
270 02:49:25.735650 start: 2 uboot-action (timeout 00:05:00) [common]
271 02:49:25.736221 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 02:49:25.736738 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 02:49:25.737254 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 02:49:25.737795 Using kernel file from prepare-kernel: 675417/tftp-deploy-iv9ddjmu/kernel/uImage
275 02:49:25.738430 substitutions:
276 02:49:25.738843 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 02:49:25.739253 - {DTB_ADDR}: 0x01070000
278 02:49:25.739656 - {DTB}: 675417/tftp-deploy-iv9ddjmu/dtb/meson-g12b-a311d-libretech-cc.dtb
279 02:49:25.740087 - {INITRD}: 675417/tftp-deploy-iv9ddjmu/ramdisk/ramdisk.cpio.gz.uboot
280 02:49:25.740496 - {KERNEL_ADDR}: 0x01080000
281 02:49:25.740896 - {KERNEL}: 675417/tftp-deploy-iv9ddjmu/kernel/uImage
282 02:49:25.741293 - {LAVA_MAC}: None
283 02:49:25.741729 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/675417/extract-nfsrootfs-u_lpqv2e
284 02:49:25.742137 - {NFS_SERVER_IP}: 192.168.6.2
285 02:49:25.742531 - {PRESEED_CONFIG}: None
286 02:49:25.742924 - {PRESEED_LOCAL}: None
287 02:49:25.743315 - {RAMDISK_ADDR}: 0x08000000
288 02:49:25.743707 - {RAMDISK}: 675417/tftp-deploy-iv9ddjmu/ramdisk/ramdisk.cpio.gz.uboot
289 02:49:25.744128 - {ROOT_PART}: None
290 02:49:25.744531 - {ROOT}: None
291 02:49:25.744928 - {SERVER_IP}: 192.168.6.2
292 02:49:25.745324 - {TEE_ADDR}: 0x83000000
293 02:49:25.745718 - {TEE}: None
294 02:49:25.746118 Parsed boot commands:
295 02:49:25.746504 - setenv autoload no
296 02:49:25.746898 - setenv initrd_high 0xffffffff
297 02:49:25.747287 - setenv fdt_high 0xffffffff
298 02:49:25.747675 - dhcp
299 02:49:25.748095 - setenv serverip 192.168.6.2
300 02:49:25.748490 - tftpboot 0x01080000 675417/tftp-deploy-iv9ddjmu/kernel/uImage
301 02:49:25.748886 - tftpboot 0x08000000 675417/tftp-deploy-iv9ddjmu/ramdisk/ramdisk.cpio.gz.uboot
302 02:49:25.749278 - tftpboot 0x01070000 675417/tftp-deploy-iv9ddjmu/dtb/meson-g12b-a311d-libretech-cc.dtb
303 02:49:25.749668 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/675417/extract-nfsrootfs-u_lpqv2e,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 02:49:25.750075 - bootm 0x01080000 0x08000000 0x01070000
305 02:49:25.750591 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 02:49:25.752119 start: 2.3 connect-device (timeout 00:05:00) [common]
308 02:49:25.752554 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 02:49:25.767614 Setting prompt string to ['lava-test: # ']
310 02:49:25.769138 end: 2.3 connect-device (duration 00:00:00) [common]
311 02:49:25.769761 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 02:49:25.770334 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 02:49:25.770903 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 02:49:25.772121 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 02:49:25.808863 >> OK - accepted request
316 02:49:25.811026 Returned 0 in 0 seconds
317 02:49:25.912536 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 02:49:25.914263 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 02:49:25.914863 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 02:49:25.915400 Setting prompt string to ['Hit any key to stop autoboot']
322 02:49:25.915878 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 02:49:25.917506 Trying 192.168.56.21...
324 02:49:25.917995 Connected to conserv1.
325 02:49:25.918423 Escape character is '^]'.
326 02:49:25.918852
327 02:49:25.919277 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 02:49:25.919708
329 02:49:36.726424 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 02:49:36.727059 bl2_stage_init 0x01
331 02:49:36.727495 bl2_stage_init 0x81
332 02:49:36.732183 hw id: 0x0000 - pwm id 0x01
333 02:49:36.732683 bl2_stage_init 0xc1
334 02:49:36.733081 bl2_stage_init 0x02
335 02:49:36.733471
336 02:49:36.737585 L0:00000000
337 02:49:36.738030 L1:20000703
338 02:49:36.738432 L2:00008067
339 02:49:36.738826 L3:14000000
340 02:49:36.740546 B2:00402000
341 02:49:36.740981 B1:e0f83180
342 02:49:36.741382
343 02:49:36.741769 TE: 58124
344 02:49:36.742152
345 02:49:36.751576 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 02:49:36.752043
347 02:49:36.752441 Board ID = 1
348 02:49:36.752825 Set A53 clk to 24M
349 02:49:36.753207 Set A73 clk to 24M
350 02:49:36.757050 Set clk81 to 24M
351 02:49:36.757470 A53 clk: 1200 MHz
352 02:49:36.757855 A73 clk: 1200 MHz
353 02:49:36.762796 CLK81: 166.6M
354 02:49:36.763214 smccc: 00012a92
355 02:49:36.768294 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 02:49:36.768715 board id: 1
357 02:49:36.773897 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 02:49:36.787737 fw parse done
359 02:49:36.793151 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 02:49:36.835573 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 02:49:36.847102 PIEI prepare done
362 02:49:36.847524 fastboot data load
363 02:49:36.847915 fastboot data verify
364 02:49:36.852758 verify result: 266
365 02:49:36.858319 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 02:49:36.858738 LPDDR4 probe
367 02:49:36.859137 ddr clk to 1584MHz
368 02:49:36.865608 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 02:49:36.902794
370 02:49:36.903253 dmc_version 0001
371 02:49:36.910221 Check phy result
372 02:49:36.916130 INFO : End of CA training
373 02:49:36.916564 INFO : End of initialization
374 02:49:36.921713 INFO : Training has run successfully!
375 02:49:36.922143 Check phy result
376 02:49:36.927314 INFO : End of initialization
377 02:49:36.927740 INFO : End of read enable training
378 02:49:36.932911 INFO : End of fine write leveling
379 02:49:36.938527 INFO : End of Write leveling coarse delay
380 02:49:36.938956 INFO : Training has run successfully!
381 02:49:36.939364 Check phy result
382 02:49:36.944100 INFO : End of initialization
383 02:49:36.944545 INFO : End of read dq deskew training
384 02:49:36.949740 INFO : End of MPR read delay center optimization
385 02:49:36.955329 INFO : End of write delay center optimization
386 02:49:36.960966 INFO : End of read delay center optimization
387 02:49:36.961400 INFO : End of max read latency training
388 02:49:36.966517 INFO : Training has run successfully!
389 02:49:36.966945 1D training succeed
390 02:49:36.975168 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 02:49:37.022928 Check phy result
392 02:49:37.023394 INFO : End of initialization
393 02:49:37.044493 INFO : End of 2D read delay Voltage center optimization
394 02:49:37.064248 INFO : End of 2D read delay Voltage center optimization
395 02:49:37.116444 INFO : End of 2D write delay Voltage center optimization
396 02:49:37.166223 INFO : End of 2D write delay Voltage center optimization
397 02:49:37.171712 INFO : Training has run successfully!
398 02:49:37.172188
399 02:49:37.172606 channel==0
400 02:49:37.177420 RxClkDly_Margin_A0==88 ps 9
401 02:49:37.177853 TxDqDly_Margin_A0==98 ps 10
402 02:49:37.180741 RxClkDly_Margin_A1==88 ps 9
403 02:49:37.181167 TxDqDly_Margin_A1==98 ps 10
404 02:49:37.186395 TrainedVREFDQ_A0==74
405 02:49:37.186840 TrainedVREFDQ_A1==74
406 02:49:37.187247 VrefDac_Margin_A0==25
407 02:49:37.192036 DeviceVref_Margin_A0==40
408 02:49:37.192464 VrefDac_Margin_A1==25
409 02:49:37.197509 DeviceVref_Margin_A1==40
410 02:49:37.197931
411 02:49:37.198337
412 02:49:37.198735 channel==1
413 02:49:37.199128 RxClkDly_Margin_A0==98 ps 10
414 02:49:37.203155 TxDqDly_Margin_A0==98 ps 10
415 02:49:37.203586 RxClkDly_Margin_A1==88 ps 9
416 02:49:37.208704 TxDqDly_Margin_A1==88 ps 9
417 02:49:37.209140 TrainedVREFDQ_A0==76
418 02:49:37.209543 TrainedVREFDQ_A1==77
419 02:49:37.214416 VrefDac_Margin_A0==22
420 02:49:37.214851 DeviceVref_Margin_A0==38
421 02:49:37.219912 VrefDac_Margin_A1==24
422 02:49:37.220365 DeviceVref_Margin_A1==37
423 02:49:37.220761
424 02:49:37.225488 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 02:49:37.225917
426 02:49:37.253438 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 02:49:37.258978 2D training succeed
428 02:49:37.264589 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 02:49:37.265019 auto size-- 65535DDR cs0 size: 2048MB
430 02:49:37.270188 DDR cs1 size: 2048MB
431 02:49:37.270612 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 02:49:37.275815 cs0 DataBus test pass
433 02:49:37.276275 cs1 DataBus test pass
434 02:49:37.276680 cs0 AddrBus test pass
435 02:49:37.281418 cs1 AddrBus test pass
436 02:49:37.281839
437 02:49:37.282243 100bdlr_step_size ps== 420
438 02:49:37.282650 result report
439 02:49:37.287014 boot times 0Enable ddr reg access
440 02:49:37.294714 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 02:49:37.307698 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 02:49:37.880123 0.0;M3 CHK:0;cm4_sp_mode 0
443 02:49:37.880662 MVN_1=0x00000000
444 02:49:37.885626 MVN_2=0x00000000
445 02:49:37.891385 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 02:49:37.891825 OPS=0x10
447 02:49:37.892275 ring efuse init
448 02:49:37.892691 chipver efuse init
449 02:49:37.899558 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 02:49:37.900020 [0.018961 Inits done]
451 02:49:37.907270 secure task start!
452 02:49:37.907694 high task start!
453 02:49:37.908123 low task start!
454 02:49:37.908522 run into bl31
455 02:49:37.913765 NOTICE: BL31: v1.3(release):4fc40b1
456 02:49:37.921534 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 02:49:37.921972 NOTICE: BL31: G12A normal boot!
458 02:49:37.946944 NOTICE: BL31: BL33 decompress pass
459 02:49:37.952407 ERROR: Error initializing runtime service opteed_fast
460 02:49:39.185640
461 02:49:39.186320
462 02:49:39.193076 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 02:49:39.193608
464 02:49:39.194073 Model: Libre Computer AML-A311D-CC Alta
465 02:49:39.401583 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 02:49:39.425652 DRAM: 2 GiB (effective 3.8 GiB)
467 02:49:39.569321 Core: 408 devices, 31 uclasses, devicetree: separate
468 02:49:39.574672 WDT: Not starting watchdog@f0d0
469 02:49:39.606932 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 02:49:39.619332 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 02:49:39.623421 ** Bad device specification mmc 0 **
472 02:49:39.634741 Card did not respond to voltage select! : -110
473 02:49:39.642364 ** Bad device specification mmc 0 **
474 02:49:39.642731 Couldn't find partition mmc 0
475 02:49:39.650713 Card did not respond to voltage select! : -110
476 02:49:39.656232 ** Bad device specification mmc 0 **
477 02:49:39.656713 Couldn't find partition mmc 0
478 02:49:39.660308 Error: could not access storage.
479 02:49:40.927023 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 02:49:40.927713 bl2_stage_init 0x01
481 02:49:40.928291 bl2_stage_init 0x81
482 02:49:40.932556 hw id: 0x0000 - pwm id 0x01
483 02:49:40.933196 bl2_stage_init 0xc1
484 02:49:40.933672 bl2_stage_init 0x02
485 02:49:40.934128
486 02:49:40.938104 L0:00000000
487 02:49:40.938724 L1:20000703
488 02:49:40.939192 L2:00008067
489 02:49:40.939637 L3:14000000
490 02:49:40.943718 B2:00402000
491 02:49:40.944361 B1:e0f83180
492 02:49:40.944824
493 02:49:40.945276 TE: 58124
494 02:49:40.945719
495 02:49:40.949293 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 02:49:40.949875
497 02:49:40.950333 Board ID = 1
498 02:49:40.954966 Set A53 clk to 24M
499 02:49:40.955551 Set A73 clk to 24M
500 02:49:40.956044 Set clk81 to 24M
501 02:49:40.960504 A53 clk: 1200 MHz
502 02:49:40.961088 A73 clk: 1200 MHz
503 02:49:40.961547 CLK81: 166.6M
504 02:49:40.961999 smccc: 00012a92
505 02:49:40.966095 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 02:49:40.971693 board id: 1
507 02:49:40.977174 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 02:49:40.988294 fw parse done
509 02:49:40.994348 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 02:49:41.035937 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 02:49:41.047678 PIEI prepare done
512 02:49:41.048231 fastboot data load
513 02:49:41.048692 fastboot data verify
514 02:49:41.053360 verify result: 266
515 02:49:41.059011 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 02:49:41.059523 LPDDR4 probe
517 02:49:41.059976 ddr clk to 1584MHz
518 02:49:41.066936 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 02:49:41.104187
520 02:49:41.104721 dmc_version 0001
521 02:49:41.110848 Check phy result
522 02:49:41.116787 INFO : End of CA training
523 02:49:41.117300 INFO : End of initialization
524 02:49:41.122342 INFO : Training has run successfully!
525 02:49:41.122845 Check phy result
526 02:49:41.128050 INFO : End of initialization
527 02:49:41.128554 INFO : End of read enable training
528 02:49:41.133527 INFO : End of fine write leveling
529 02:49:41.139121 INFO : End of Write leveling coarse delay
530 02:49:41.139626 INFO : Training has run successfully!
531 02:49:41.140124 Check phy result
532 02:49:41.144758 INFO : End of initialization
533 02:49:41.145261 INFO : End of read dq deskew training
534 02:49:41.150335 INFO : End of MPR read delay center optimization
535 02:49:41.156025 INFO : End of write delay center optimization
536 02:49:41.161543 INFO : End of read delay center optimization
537 02:49:41.162048 INFO : End of max read latency training
538 02:49:41.167123 INFO : Training has run successfully!
539 02:49:41.167634 1D training succeed
540 02:49:41.176256 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 02:49:41.223534 Check phy result
542 02:49:41.224103 INFO : End of initialization
543 02:49:41.245564 INFO : End of 2D read delay Voltage center optimization
544 02:49:41.265667 INFO : End of 2D read delay Voltage center optimization
545 02:49:41.317587 INFO : End of 2D write delay Voltage center optimization
546 02:49:41.366867 INFO : End of 2D write delay Voltage center optimization
547 02:49:41.372402 INFO : Training has run successfully!
548 02:49:41.372980
549 02:49:41.373443 channel==0
550 02:49:41.378088 RxClkDly_Margin_A0==88 ps 9
551 02:49:41.378626 TxDqDly_Margin_A0==98 ps 10
552 02:49:41.383611 RxClkDly_Margin_A1==88 ps 9
553 02:49:41.384177 TxDqDly_Margin_A1==88 ps 9
554 02:49:41.384650 TrainedVREFDQ_A0==74
555 02:49:41.389190 TrainedVREFDQ_A1==74
556 02:49:41.389739 VrefDac_Margin_A0==25
557 02:49:41.390233 DeviceVref_Margin_A0==40
558 02:49:41.394836 VrefDac_Margin_A1==25
559 02:49:41.395366 DeviceVref_Margin_A1==40
560 02:49:41.395826
561 02:49:41.396307
562 02:49:41.396756 channel==1
563 02:49:41.400386 RxClkDly_Margin_A0==98 ps 10
564 02:49:41.400907 TxDqDly_Margin_A0==88 ps 9
565 02:49:41.406063 RxClkDly_Margin_A1==98 ps 10
566 02:49:41.406586 TxDqDly_Margin_A1==88 ps 9
567 02:49:41.411556 TrainedVREFDQ_A0==77
568 02:49:41.412241 TrainedVREFDQ_A1==77
569 02:49:41.412755 VrefDac_Margin_A0==22
570 02:49:41.417126 DeviceVref_Margin_A0==37
571 02:49:41.417576 VrefDac_Margin_A1==22
572 02:49:41.422732 DeviceVref_Margin_A1==37
573 02:49:41.423178
574 02:49:41.423594 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 02:49:41.424032
576 02:49:41.456257 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 02:49:41.456784 2D training succeed
578 02:49:41.461992 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 02:49:41.467462 auto size-- 65535DDR cs0 size: 2048MB
580 02:49:41.467928 DDR cs1 size: 2048MB
581 02:49:41.473159 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 02:49:41.473617 cs0 DataBus test pass
583 02:49:41.478774 cs1 DataBus test pass
584 02:49:41.479225 cs0 AddrBus test pass
585 02:49:41.479637 cs1 AddrBus test pass
586 02:49:41.480072
587 02:49:41.484273 100bdlr_step_size ps== 420
588 02:49:41.484739 result report
589 02:49:41.489983 boot times 0Enable ddr reg access
590 02:49:41.495124 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 02:49:41.508612 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 02:49:42.080799 0.0;M3 CHK:0;cm4_sp_mode 0
593 02:49:42.081409 MVN_1=0x00000000
594 02:49:42.086149 MVN_2=0x00000000
595 02:49:42.091917 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 02:49:42.092496 OPS=0x10
597 02:49:42.092964 ring efuse init
598 02:49:42.093403 chipver efuse init
599 02:49:42.097483 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 02:49:42.103090 [0.018961 Inits done]
601 02:49:42.103528 secure task start!
602 02:49:42.103918 high task start!
603 02:49:42.107674 low task start!
604 02:49:42.108217 run into bl31
605 02:49:42.114337 NOTICE: BL31: v1.3(release):4fc40b1
606 02:49:42.121216 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 02:49:42.121690 NOTICE: BL31: G12A normal boot!
608 02:49:42.147491 NOTICE: BL31: BL33 decompress pass
609 02:49:42.153187 ERROR: Error initializing runtime service opteed_fast
610 02:49:43.386286
611 02:49:43.386918
612 02:49:43.394640 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 02:49:43.395149
614 02:49:43.395593 Model: Libre Computer AML-A311D-CC Alta
615 02:49:43.603086 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 02:49:43.625831 DRAM: 2 GiB (effective 3.8 GiB)
617 02:49:43.769430 Core: 408 devices, 31 uclasses, devicetree: separate
618 02:49:43.775194 WDT: Not starting watchdog@f0d0
619 02:49:43.807470 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 02:49:43.820014 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 02:49:43.824913 ** Bad device specification mmc 0 **
622 02:49:43.835379 Card did not respond to voltage select! : -110
623 02:49:43.842929 ** Bad device specification mmc 0 **
624 02:49:43.843371 Couldn't find partition mmc 0
625 02:49:43.851301 Card did not respond to voltage select! : -110
626 02:49:43.856687 ** Bad device specification mmc 0 **
627 02:49:43.857136 Couldn't find partition mmc 0
628 02:49:43.861853 Error: could not access storage.
629 02:49:44.203931 Net: eth0: ethernet@ff3f0000
630 02:49:44.204556 starting USB...
631 02:49:44.456194 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 02:49:44.456768 Starting the controller
633 02:49:44.462439 USB XHCI 1.10
634 02:49:46.176893 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 02:49:46.177319 bl2_stage_init 0x01
636 02:49:46.177560 bl2_stage_init 0x81
637 02:49:46.182624 hw id: 0x0000 - pwm id 0x01
638 02:49:46.183046 bl2_stage_init 0xc1
639 02:49:46.183409 bl2_stage_init 0x02
640 02:49:46.183758
641 02:49:46.188153 L0:00000000
642 02:49:46.188571 L1:20000703
643 02:49:46.188833 L2:00008067
644 02:49:46.189055 L3:14000000
645 02:49:46.193737 B2:00402000
646 02:49:46.194146 B1:e0f83180
647 02:49:46.194495
648 02:49:46.194840 TE: 58124
649 02:49:46.195177
650 02:49:46.199360 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 02:49:46.199656
652 02:49:46.199882 Board ID = 1
653 02:49:46.204870 Set A53 clk to 24M
654 02:49:46.205169 Set A73 clk to 24M
655 02:49:46.205393 Set clk81 to 24M
656 02:49:46.210643 A53 clk: 1200 MHz
657 02:49:46.211052 A73 clk: 1200 MHz
658 02:49:46.211407 CLK81: 166.6M
659 02:49:46.211751 smccc: 00012a91
660 02:49:46.216174 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 02:49:46.221734 board id: 1
662 02:49:46.227733 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 02:49:46.238288 fw parse done
664 02:49:46.244277 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 02:49:46.286746 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 02:49:46.297657 PIEI prepare done
667 02:49:46.297953 fastboot data load
668 02:49:46.298180 fastboot data verify
669 02:49:46.303323 verify result: 266
670 02:49:46.308906 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 02:49:46.309322 LPDDR4 probe
672 02:49:46.309685 ddr clk to 1584MHz
673 02:49:46.316894 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 02:49:46.354102
675 02:49:46.354405 dmc_version 0001
676 02:49:46.360830 Check phy result
677 02:49:46.366711 INFO : End of CA training
678 02:49:46.367128 INFO : End of initialization
679 02:49:46.372325 INFO : Training has run successfully!
680 02:49:46.372621 Check phy result
681 02:49:46.377901 INFO : End of initialization
682 02:49:46.378316 INFO : End of read enable training
683 02:49:46.383580 INFO : End of fine write leveling
684 02:49:46.389115 INFO : End of Write leveling coarse delay
685 02:49:46.389413 INFO : Training has run successfully!
686 02:49:46.389638 Check phy result
687 02:49:46.394722 INFO : End of initialization
688 02:49:46.395141 INFO : End of read dq deskew training
689 02:49:46.400336 INFO : End of MPR read delay center optimization
690 02:49:46.405890 INFO : End of write delay center optimization
691 02:49:46.411586 INFO : End of read delay center optimization
692 02:49:46.411887 INFO : End of max read latency training
693 02:49:46.417100 INFO : Training has run successfully!
694 02:49:46.417396 1D training succeed
695 02:49:46.426288 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 02:49:46.473859 Check phy result
697 02:49:46.474288 INFO : End of initialization
698 02:49:46.494714 INFO : End of 2D read delay Voltage center optimization
699 02:49:46.515064 INFO : End of 2D read delay Voltage center optimization
700 02:49:46.567858 INFO : End of 2D write delay Voltage center optimization
701 02:49:46.617290 INFO : End of 2D write delay Voltage center optimization
702 02:49:46.622854 INFO : Training has run successfully!
703 02:49:46.623149
704 02:49:46.623376 channel==0
705 02:49:46.628444 RxClkDly_Margin_A0==88 ps 9
706 02:49:46.628879 TxDqDly_Margin_A0==98 ps 10
707 02:49:46.634046 RxClkDly_Margin_A1==88 ps 9
708 02:49:46.634468 TxDqDly_Margin_A1==98 ps 10
709 02:49:46.634835 TrainedVREFDQ_A0==74
710 02:49:46.639627 TrainedVREFDQ_A1==74
711 02:49:46.639920 VrefDac_Margin_A0==25
712 02:49:46.640177 DeviceVref_Margin_A0==40
713 02:49:46.645250 VrefDac_Margin_A1==25
714 02:49:46.645672 DeviceVref_Margin_A1==40
715 02:49:46.646033
716 02:49:46.646381
717 02:49:46.650824 channel==1
718 02:49:46.651238 RxClkDly_Margin_A0==98 ps 10
719 02:49:46.651499 TxDqDly_Margin_A0==88 ps 9
720 02:49:46.656419 RxClkDly_Margin_A1==88 ps 9
721 02:49:46.656711 TxDqDly_Margin_A1==88 ps 9
722 02:49:46.662052 TrainedVREFDQ_A0==74
723 02:49:46.662479 TrainedVREFDQ_A1==77
724 02:49:46.662842 VrefDac_Margin_A0==22
725 02:49:46.667631 DeviceVref_Margin_A0==40
726 02:49:46.667923 VrefDac_Margin_A1==24
727 02:49:46.673248 DeviceVref_Margin_A1==37
728 02:49:46.673673
729 02:49:46.674038 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 02:49:46.674470
731 02:49:46.706809 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 02:49:46.707259 2D training succeed
733 02:49:46.712420 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 02:49:46.718006 auto size-- 65535DDR cs0 size: 2048MB
735 02:49:46.718306 DDR cs1 size: 2048MB
736 02:49:46.723633 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 02:49:46.724084 cs0 DataBus test pass
738 02:49:46.729269 cs1 DataBus test pass
739 02:49:46.729568 cs0 AddrBus test pass
740 02:49:46.729790 cs1 AddrBus test pass
741 02:49:46.729997
742 02:49:46.734835 100bdlr_step_size ps== 420
743 02:49:46.735260 result report
744 02:49:46.740418 boot times 0Enable ddr reg access
745 02:49:46.746033 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 02:49:46.758292 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 02:49:47.332767 0.0;M3 CHK:0;cm4_sp_mode 0
748 02:49:47.333132 MVN_1=0x00000000
749 02:49:47.338305 MVN_2=0x00000000
750 02:49:47.344032 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 02:49:47.344321 OPS=0x10
752 02:49:47.344543 ring efuse init
753 02:49:47.344754 chipver efuse init
754 02:49:47.349609 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 02:49:47.355208 [0.018961 Inits done]
756 02:49:47.355504 secure task start!
757 02:49:47.355719 high task start!
758 02:49:47.358856 low task start!
759 02:49:47.359113 run into bl31
760 02:49:47.366441 NOTICE: BL31: v1.3(release):4fc40b1
761 02:49:47.374239 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 02:49:47.374503 NOTICE: BL31: G12A normal boot!
763 02:49:47.399645 NOTICE: BL31: BL33 decompress pass
764 02:49:47.405264 ERROR: Error initializing runtime service opteed_fast
765 02:49:48.638118
766 02:49:48.638525
767 02:49:48.646535 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 02:49:48.646977
769 02:49:48.647331 Model: Libre Computer AML-A311D-CC Alta
770 02:49:48.855009 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 02:49:48.878310 DRAM: 2 GiB (effective 3.8 GiB)
772 02:49:49.021248 Core: 408 devices, 31 uclasses, devicetree: separate
773 02:49:49.027144 WDT: Not starting watchdog@f0d0
774 02:49:49.059380 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 02:49:49.071866 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 02:49:49.076930 ** Bad device specification mmc 0 **
777 02:49:49.087163 Card did not respond to voltage select! : -110
778 02:49:49.094930 ** Bad device specification mmc 0 **
779 02:49:49.095219 Couldn't find partition mmc 0
780 02:49:49.103152 Card did not respond to voltage select! : -110
781 02:49:49.108655 ** Bad device specification mmc 0 **
782 02:49:49.108942 Couldn't find partition mmc 0
783 02:49:49.113733 Error: could not access storage.
784 02:49:49.456207 Net: eth0: ethernet@ff3f0000
785 02:49:49.456568 starting USB...
786 02:49:49.708078 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 02:49:49.708601 Starting the controller
788 02:49:49.715049 USB XHCI 1.10
789 02:49:51.877127 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 02:49:51.877726 bl2_stage_init 0x01
791 02:49:51.878163 bl2_stage_init 0x81
792 02:49:51.882619 hw id: 0x0000 - pwm id 0x01
793 02:49:51.883081 bl2_stage_init 0xc1
794 02:49:51.883498 bl2_stage_init 0x02
795 02:49:51.883910
796 02:49:51.888218 L0:00000000
797 02:49:51.888672 L1:20000703
798 02:49:51.889091 L2:00008067
799 02:49:51.889495 L3:14000000
800 02:49:51.891163 B2:00402000
801 02:49:51.891598 B1:e0f83180
802 02:49:51.892028
803 02:49:51.892448 TE: 58124
804 02:49:51.892858
805 02:49:51.902392 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 02:49:51.902866
807 02:49:51.903288 Board ID = 1
808 02:49:51.903695 Set A53 clk to 24M
809 02:49:51.904136 Set A73 clk to 24M
810 02:49:51.907962 Set clk81 to 24M
811 02:49:51.908440 A53 clk: 1200 MHz
812 02:49:51.908860 A73 clk: 1200 MHz
813 02:49:51.913503 CLK81: 166.6M
814 02:49:51.913954 smccc: 00012a92
815 02:49:51.919127 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 02:49:51.919581 board id: 1
817 02:49:51.927835 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 02:49:51.938419 fw parse done
819 02:49:51.944352 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 02:49:51.986975 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 02:49:51.997882 PIEI prepare done
822 02:49:51.998375 fastboot data load
823 02:49:51.998806 fastboot data verify
824 02:49:52.003547 verify result: 266
825 02:49:52.009196 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 02:49:52.009704 LPDDR4 probe
827 02:49:52.010133 ddr clk to 1584MHz
828 02:49:52.017105 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 02:49:52.054400
830 02:49:52.054894 dmc_version 0001
831 02:49:52.061083 Check phy result
832 02:49:52.066963 INFO : End of CA training
833 02:49:52.067421 INFO : End of initialization
834 02:49:52.072469 INFO : Training has run successfully!
835 02:49:52.072926 Check phy result
836 02:49:52.078122 INFO : End of initialization
837 02:49:52.078582 INFO : End of read enable training
838 02:49:52.081499 INFO : End of fine write leveling
839 02:49:52.087121 INFO : End of Write leveling coarse delay
840 02:49:52.092770 INFO : Training has run successfully!
841 02:49:52.093231 Check phy result
842 02:49:52.093645 INFO : End of initialization
843 02:49:52.098322 INFO : End of read dq deskew training
844 02:49:52.101644 INFO : End of MPR read delay center optimization
845 02:49:52.107240 INFO : End of write delay center optimization
846 02:49:52.112894 INFO : End of read delay center optimization
847 02:49:52.113386 INFO : End of max read latency training
848 02:49:52.118467 INFO : Training has run successfully!
849 02:49:52.118938 1D training succeed
850 02:49:52.126563 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 02:49:52.174126 Check phy result
852 02:49:52.174623 INFO : End of initialization
853 02:49:52.196709 INFO : End of 2D read delay Voltage center optimization
854 02:49:52.216948 INFO : End of 2D read delay Voltage center optimization
855 02:49:52.269032 INFO : End of 2D write delay Voltage center optimization
856 02:49:52.318387 INFO : End of 2D write delay Voltage center optimization
857 02:49:52.323944 INFO : Training has run successfully!
858 02:49:52.324442
859 02:49:52.324870 channel==0
860 02:49:52.329530 RxClkDly_Margin_A0==88 ps 9
861 02:49:52.329979 TxDqDly_Margin_A0==98 ps 10
862 02:49:52.332778 RxClkDly_Margin_A1==88 ps 9
863 02:49:52.333217 TxDqDly_Margin_A1==98 ps 10
864 02:49:52.338443 TrainedVREFDQ_A0==74
865 02:49:52.338988 TrainedVREFDQ_A1==74
866 02:49:52.339418 VrefDac_Margin_A0==24
867 02:49:52.344059 DeviceVref_Margin_A0==40
868 02:49:52.344565 VrefDac_Margin_A1==24
869 02:49:52.349642 DeviceVref_Margin_A1==40
870 02:49:52.350074
871 02:49:52.350461
872 02:49:52.350846 channel==1
873 02:49:52.351226 RxClkDly_Margin_A0==98 ps 10
874 02:49:52.355193 TxDqDly_Margin_A0==98 ps 10
875 02:49:52.355623 RxClkDly_Margin_A1==88 ps 9
876 02:49:52.360864 TxDqDly_Margin_A1==98 ps 10
877 02:49:52.361293 TrainedVREFDQ_A0==77
878 02:49:52.361680 TrainedVREFDQ_A1==77
879 02:49:52.366536 VrefDac_Margin_A0==22
880 02:49:52.366959 DeviceVref_Margin_A0==37
881 02:49:52.372003 VrefDac_Margin_A1==24
882 02:49:52.372433 DeviceVref_Margin_A1==37
883 02:49:52.372818
884 02:49:52.377548 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 02:49:52.377976
886 02:49:52.405554 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 02:49:52.411110 2D training succeed
888 02:49:52.416745 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 02:49:52.417168 auto size-- 65535DDR cs0 size: 2048MB
890 02:49:52.422350 DDR cs1 size: 2048MB
891 02:49:52.422781 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 02:49:52.427936 cs0 DataBus test pass
893 02:49:52.428397 cs1 DataBus test pass
894 02:49:52.428789 cs0 AddrBus test pass
895 02:49:52.433552 cs1 AddrBus test pass
896 02:49:52.433973
897 02:49:52.434358 100bdlr_step_size ps== 415
898 02:49:52.434748 result report
899 02:49:52.439241 boot times 0Enable ddr reg access
900 02:49:52.446882 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 02:49:52.460396 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 02:49:53.033955 0.0;M3 CHK:0;cm4_sp_mode 0
903 02:49:53.034528 MVN_1=0x00000000
904 02:49:53.039537 MVN_2=0x00000000
905 02:49:53.045271 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 02:49:53.045722 OPS=0x10
907 02:49:53.046135 ring efuse init
908 02:49:53.046536 chipver efuse init
909 02:49:53.053510 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 02:49:53.053962 [0.018961 Inits done]
911 02:49:53.060075 secure task start!
912 02:49:53.060507 high task start!
913 02:49:53.060909 low task start!
914 02:49:53.061306 run into bl31
915 02:49:53.067808 NOTICE: BL31: v1.3(release):4fc40b1
916 02:49:53.074669 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 02:49:53.075108 NOTICE: BL31: G12A normal boot!
918 02:49:53.100827 NOTICE: BL31: BL33 decompress pass
919 02:49:53.106606 ERROR: Error initializing runtime service opteed_fast
920 02:49:54.339454
921 02:49:54.339887
922 02:49:54.347967 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 02:49:54.348316
924 02:49:54.348579 Model: Libre Computer AML-A311D-CC Alta
925 02:49:54.556299 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 02:49:54.579661 DRAM: 2 GiB (effective 3.8 GiB)
927 02:49:54.722616 Core: 408 devices, 31 uclasses, devicetree: separate
928 02:49:54.728426 WDT: Not starting watchdog@f0d0
929 02:49:54.760759 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 02:49:54.773247 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 02:49:54.777275 ** Bad device specification mmc 0 **
932 02:49:54.788601 Card did not respond to voltage select! : -110
933 02:49:54.795344 ** Bad device specification mmc 0 **
934 02:49:54.795820 Couldn't find partition mmc 0
935 02:49:54.804576 Card did not respond to voltage select! : -110
936 02:49:54.810042 ** Bad device specification mmc 0 **
937 02:49:54.810516 Couldn't find partition mmc 0
938 02:49:54.815101 Error: could not access storage.
939 02:49:55.157544 Net: eth0: ethernet@ff3f0000
940 02:49:55.158128 starting USB...
941 02:49:55.409391 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 02:49:55.409983 Starting the controller
943 02:49:55.416345 USB XHCI 1.10
944 02:49:57.277015 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 02:49:57.277673 bl2_stage_init 0x01
946 02:49:57.278166 bl2_stage_init 0x81
947 02:49:57.282612 hw id: 0x0000 - pwm id 0x01
948 02:49:57.283169 bl2_stage_init 0xc1
949 02:49:57.283639 bl2_stage_init 0x02
950 02:49:57.284161
951 02:49:57.288274 L0:00000000
952 02:49:57.288827 L1:20000703
953 02:49:57.289294 L2:00008067
954 02:49:57.289751 L3:14000000
955 02:49:57.291072 B2:00402000
956 02:49:57.291616 B1:e0f83180
957 02:49:57.292122
958 02:49:57.292591 TE: 58124
959 02:49:57.293049
960 02:49:57.302237 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 02:49:57.302802
962 02:49:57.303271 Board ID = 1
963 02:49:57.303724 Set A53 clk to 24M
964 02:49:57.304227 Set A73 clk to 24M
965 02:49:57.307831 Set clk81 to 24M
966 02:49:57.308408 A53 clk: 1200 MHz
967 02:49:57.308868 A73 clk: 1200 MHz
968 02:49:57.313431 CLK81: 166.6M
969 02:49:57.313975 smccc: 00012a91
970 02:49:57.319020 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 02:49:57.319570 board id: 1
972 02:49:57.324607 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 02:49:57.338406 fw parse done
974 02:49:57.344406 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 02:49:57.385900 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 02:49:57.397740 PIEI prepare done
977 02:49:57.398275 fastboot data load
978 02:49:57.398720 fastboot data verify
979 02:49:57.403407 verify result: 266
980 02:49:57.409038 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 02:49:57.409562 LPDDR4 probe
982 02:49:57.409997 ddr clk to 1584MHz
983 02:49:57.417014 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 02:49:57.453475
985 02:49:57.454008 dmc_version 0001
986 02:49:57.460068 Check phy result
987 02:49:57.466840 INFO : End of CA training
988 02:49:57.467358 INFO : End of initialization
989 02:49:57.472414 INFO : Training has run successfully!
990 02:49:57.472954 Check phy result
991 02:49:57.478087 INFO : End of initialization
992 02:49:57.478645 INFO : End of read enable training
993 02:49:57.481329 INFO : End of fine write leveling
994 02:49:57.486878 INFO : End of Write leveling coarse delay
995 02:49:57.492482 INFO : Training has run successfully!
996 02:49:57.492872 Check phy result
997 02:49:57.493108 INFO : End of initialization
998 02:49:57.497957 INFO : End of read dq deskew training
999 02:49:57.503528 INFO : End of MPR read delay center optimization
1000 02:49:57.503834 INFO : End of write delay center optimization
1001 02:49:57.509121 INFO : End of read delay center optimization
1002 02:49:57.514786 INFO : End of max read latency training
1003 02:49:57.515282 INFO : Training has run successfully!
1004 02:49:57.520410 1D training succeed
1005 02:49:57.526437 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 02:49:57.574083 Check phy result
1007 02:49:57.574698 INFO : End of initialization
1008 02:49:57.595825 INFO : End of 2D read delay Voltage center optimization
1009 02:49:57.615102 INFO : End of 2D read delay Voltage center optimization
1010 02:49:57.668090 INFO : End of 2D write delay Voltage center optimization
1011 02:49:57.717412 INFO : End of 2D write delay Voltage center optimization
1012 02:49:57.723082 INFO : Training has run successfully!
1013 02:49:57.723621
1014 02:49:57.724145 channel==0
1015 02:49:57.728600 RxClkDly_Margin_A0==88 ps 9
1016 02:49:57.729135 TxDqDly_Margin_A0==98 ps 10
1017 02:49:57.734332 RxClkDly_Margin_A1==88 ps 9
1018 02:49:57.734865 TxDqDly_Margin_A1==98 ps 10
1019 02:49:57.735324 TrainedVREFDQ_A0==74
1020 02:49:57.739819 TrainedVREFDQ_A1==74
1021 02:49:57.740404 VrefDac_Margin_A0==25
1022 02:49:57.740894 DeviceVref_Margin_A0==40
1023 02:49:57.745465 VrefDac_Margin_A1==25
1024 02:49:57.746015 DeviceVref_Margin_A1==40
1025 02:49:57.746478
1026 02:49:57.746926
1027 02:49:57.751109 channel==1
1028 02:49:57.751692 RxClkDly_Margin_A0==98 ps 10
1029 02:49:57.752208 TxDqDly_Margin_A0==98 ps 10
1030 02:49:57.756650 RxClkDly_Margin_A1==88 ps 9
1031 02:49:57.757202 TxDqDly_Margin_A1==88 ps 9
1032 02:49:57.762387 TrainedVREFDQ_A0==77
1033 02:49:57.762939 TrainedVREFDQ_A1==77
1034 02:49:57.763409 VrefDac_Margin_A0==22
1035 02:49:57.767852 DeviceVref_Margin_A0==37
1036 02:49:57.768430 VrefDac_Margin_A1==24
1037 02:49:57.773426 DeviceVref_Margin_A1==37
1038 02:49:57.773969
1039 02:49:57.774439 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 02:49:57.774896
1041 02:49:57.806957 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
1042 02:49:57.807603 2D training succeed
1043 02:49:57.812665 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 02:49:57.818243 auto size-- 65535DDR cs0 size: 2048MB
1045 02:49:57.818803 DDR cs1 size: 2048MB
1046 02:49:57.823804 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 02:49:57.824401 cs0 DataBus test pass
1048 02:49:57.829418 cs1 DataBus test pass
1049 02:49:57.829964 cs0 AddrBus test pass
1050 02:49:57.830420 cs1 AddrBus test pass
1051 02:49:57.830864
1052 02:49:57.835028 100bdlr_step_size ps== 420
1053 02:49:57.835577 result report
1054 02:49:57.840613 boot times 0Enable ddr reg access
1055 02:49:57.845983 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 02:49:57.859436 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 02:49:58.432598 0.0;M3 CHK:0;cm4_sp_mode 0
1058 02:49:58.433237 MVN_1=0x00000000
1059 02:49:58.437952 MVN_2=0x00000000
1060 02:49:58.443790 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 02:49:58.444101 OPS=0x10
1062 02:49:58.444325 ring efuse init
1063 02:49:58.444539 chipver efuse init
1064 02:49:58.449482 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 02:49:58.454974 [0.018961 Inits done]
1066 02:49:58.455507 secure task start!
1067 02:49:58.455967 high task start!
1068 02:49:58.459595 low task start!
1069 02:49:58.460146 run into bl31
1070 02:49:58.466253 NOTICE: BL31: v1.3(release):4fc40b1
1071 02:49:58.474172 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 02:49:58.474713 NOTICE: BL31: G12A normal boot!
1073 02:49:58.499470 NOTICE: BL31: BL33 decompress pass
1074 02:49:58.505091 ERROR: Error initializing runtime service opteed_fast
1075 02:49:59.737812
1076 02:49:59.738231
1077 02:49:59.745641 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 02:49:59.746062
1079 02:49:59.746418 Model: Libre Computer AML-A311D-CC Alta
1080 02:49:59.954897 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 02:49:59.977792 DRAM: 2 GiB (effective 3.8 GiB)
1082 02:50:00.121366 Core: 408 devices, 31 uclasses, devicetree: separate
1083 02:50:00.127169 WDT: Not starting watchdog@f0d0
1084 02:50:00.159538 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 02:50:00.171966 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 02:50:00.176097 ** Bad device specification mmc 0 **
1087 02:50:00.187218 Card did not respond to voltage select! : -110
1088 02:50:00.194926 ** Bad device specification mmc 0 **
1089 02:50:00.195449 Couldn't find partition mmc 0
1090 02:50:00.203155 Card did not respond to voltage select! : -110
1091 02:50:00.208826 ** Bad device specification mmc 0 **
1092 02:50:00.209351 Couldn't find partition mmc 0
1093 02:50:00.213196 Error: could not access storage.
1094 02:50:00.557299 Net: eth0: ethernet@ff3f0000
1095 02:50:00.557951 starting USB...
1096 02:50:00.809060 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 02:50:00.809716 Starting the controller
1098 02:50:00.816200 USB XHCI 1.10
1099 02:50:02.372953 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 02:50:02.381219 scanning usb for storage devices... 0 Storage Device(s) found
1102 02:50:02.432257 Hit any key to stop autoboot: 1
1103 02:50:02.433170 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 02:50:02.433987 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 02:50:02.434502 Setting prompt string to ['=>']
1106 02:50:02.435017 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 02:50:02.438766 0
1108 02:50:02.439762 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 02:50:02.440384 Sending with 10 millisecond of delay
1111 02:50:03.575184 => setenv autoload no
1112 02:50:03.586051 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 02:50:03.591452 setenv autoload no
1114 02:50:03.592270 Sending with 10 millisecond of delay
1116 02:50:05.392045 => setenv initrd_high 0xffffffff
1117 02:50:05.402656 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 02:50:05.403613 setenv initrd_high 0xffffffff
1119 02:50:05.404436 Sending with 10 millisecond of delay
1121 02:50:07.022028 => setenv fdt_high 0xffffffff
1122 02:50:07.032863 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1123 02:50:07.033704 setenv fdt_high 0xffffffff
1124 02:50:07.034454 Sending with 10 millisecond of delay
1126 02:50:07.326243 => dhcp
1127 02:50:07.336975 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 02:50:07.337806 dhcp
1129 02:50:07.338272 Speed: 1000, full duplex
1130 02:50:07.338716 BOOTP broadcast 1
1131 02:50:07.585312 BOOTP broadcast 2
1132 02:50:07.737634 DHCP client bound to address 192.168.6.33 (400 ms)
1133 02:50:07.738186 Sending with 10 millisecond of delay
1135 02:50:09.415585 => setenv serverip 192.168.6.2
1136 02:50:09.426359 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1137 02:50:09.426980 setenv serverip 192.168.6.2
1138 02:50:09.427479 Sending with 10 millisecond of delay
1140 02:50:13.151193 => tftpboot 0x01080000 675417/tftp-deploy-iv9ddjmu/kernel/uImage
1141 02:50:13.162014 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1142 02:50:13.162948 tftpboot 0x01080000 675417/tftp-deploy-iv9ddjmu/kernel/uImage
1143 02:50:13.163395 Speed: 1000, full duplex
1144 02:50:13.163795 Using ethernet@ff3f0000 device
1145 02:50:13.164825 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1146 02:50:13.170266 Filename '675417/tftp-deploy-iv9ddjmu/kernel/uImage'.
1147 02:50:13.174182 Load address: 0x1080000
1148 02:50:15.706615 Loading: *################################################## 37.2 MiB
1149 02:50:15.707303 14.7 MiB/s
1150 02:50:15.707783 done
1151 02:50:15.710857 Bytes transferred = 39019072 (2536240 hex)
1152 02:50:15.711696 Sending with 10 millisecond of delay
1154 02:50:20.402422 => tftpboot 0x08000000 675417/tftp-deploy-iv9ddjmu/ramdisk/ramdisk.cpio.gz.uboot
1155 02:50:20.413230 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1156 02:50:20.414094 tftpboot 0x08000000 675417/tftp-deploy-iv9ddjmu/ramdisk/ramdisk.cpio.gz.uboot
1157 02:50:20.414515 Speed: 1000, full duplex
1158 02:50:20.414910 Using ethernet@ff3f0000 device
1159 02:50:20.415944 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1160 02:50:20.427691 Filename '675417/tftp-deploy-iv9ddjmu/ramdisk/ramdisk.cpio.gz.uboot'.
1161 02:50:20.428163 Load address: 0x8000000
1162 02:50:23.127209 Loading: *# UDP wrong checksum 000000ff 00004ba8
1163 02:50:23.157622 UDP wrong checksum 000000ff 0000e49a
1164 02:50:26.951572 T ################################################ UDP wrong checksum 00000005 0000920b
1165 02:50:29.425543 UDP wrong checksum 000000ff 0000d50f
1166 02:50:29.486906 UDP wrong checksum 000000ff 00005a02
1167 02:50:31.952915 T UDP wrong checksum 00000005 0000920b
1168 02:50:41.954909 T T UDP wrong checksum 00000005 0000920b
1169 02:51:01.957389 T T T UDP wrong checksum 00000005 0000920b
1170 02:51:16.962984 T T T
1171 02:51:16.963646 Retry count exceeded; starting again
1173 02:51:16.965197 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1176 02:51:16.967165 end: 2.4 uboot-commands (duration 00:01:51) [common]
1178 02:51:16.968781 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1180 02:51:16.969894 end: 2 uboot-action (duration 00:01:51) [common]
1182 02:51:16.971533 Cleaning after the job
1183 02:51:16.972154 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/ramdisk
1184 02:51:16.973668 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/kernel
1185 02:51:16.999040 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/dtb
1186 02:51:17.000547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/nfsrootfs
1187 02:51:17.042074 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675417/tftp-deploy-iv9ddjmu/modules
1188 02:51:17.049016 start: 4.1 power-off (timeout 00:00:30) [common]
1189 02:51:17.049591 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1190 02:51:17.082034 >> OK - accepted request
1191 02:51:17.084244 Returned 0 in 0 seconds
1192 02:51:17.185077 end: 4.1 power-off (duration 00:00:00) [common]
1194 02:51:17.186166 start: 4.2 read-feedback (timeout 00:10:00) [common]
1195 02:51:17.186852 Listened to connection for namespace 'common' for up to 1s
1196 02:51:18.187882 Finalising connection for namespace 'common'
1197 02:51:18.188728 Disconnecting from shell: Finalise
1198 02:51:18.189269 =>
1199 02:51:18.290232 end: 4.2 read-feedback (duration 00:00:01) [common]
1200 02:51:18.290884 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/675417
1201 02:51:19.855958 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/675417
1202 02:51:19.856600 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.