Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:35:09.576970 lava-dispatcher, installed at version: 2024.01
2 04:35:09.577790 start: 0 validate
3 04:35:09.578279 Start time: 2024-08-30 04:35:09.578247+00:00 (UTC)
4 04:35:09.578858 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:35:09.579415 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 04:35:09.623634 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:35:09.624288 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-176-g20371ba12063%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 04:35:09.656031 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:35:09.656761 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-176-g20371ba12063%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:35:10.705789 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:35:10.706349 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-176-g20371ba12063%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
12 04:35:10.758015 validate duration: 1.18
14 04:35:10.759464 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:35:10.760063 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:35:10.760608 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:35:10.764338 Not decompressing ramdisk as can be used compressed.
18 04:35:10.765915 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 04:35:10.766502 saving as /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/ramdisk/rootfs.cpio.gz
20 04:35:10.766916 total size: 8181887 (7 MB)
21 04:35:10.810416 progress 0 % (0 MB)
22 04:35:10.818394 progress 5 % (0 MB)
23 04:35:10.825504 progress 10 % (0 MB)
24 04:35:10.832594 progress 15 % (1 MB)
25 04:35:10.839073 progress 20 % (1 MB)
26 04:35:10.846981 progress 25 % (1 MB)
27 04:35:10.853719 progress 30 % (2 MB)
28 04:35:10.861024 progress 35 % (2 MB)
29 04:35:10.867688 progress 40 % (3 MB)
30 04:35:10.875442 progress 45 % (3 MB)
31 04:35:10.882290 progress 50 % (3 MB)
32 04:35:10.889624 progress 55 % (4 MB)
33 04:35:10.895912 progress 60 % (4 MB)
34 04:35:10.902766 progress 65 % (5 MB)
35 04:35:10.909140 progress 70 % (5 MB)
36 04:35:10.915876 progress 75 % (5 MB)
37 04:35:10.922630 progress 80 % (6 MB)
38 04:35:10.929625 progress 85 % (6 MB)
39 04:35:10.935522 progress 90 % (7 MB)
40 04:35:10.941696 progress 95 % (7 MB)
41 04:35:10.947657 progress 100 % (7 MB)
42 04:35:10.948566 7 MB downloaded in 0.18 s (42.96 MB/s)
43 04:35:10.949278 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:35:10.950417 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:35:10.950813 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:35:10.951200 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:35:10.951896 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-176-g20371ba12063/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
49 04:35:10.952317 saving as /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/kernel/Image
50 04:35:10.952606 total size: 39019008 (37 MB)
51 04:35:10.952891 No compression specified
52 04:35:10.994054 progress 0 % (0 MB)
53 04:35:11.019228 progress 5 % (1 MB)
54 04:35:11.045654 progress 10 % (3 MB)
55 04:35:11.069632 progress 15 % (5 MB)
56 04:35:11.093482 progress 20 % (7 MB)
57 04:35:11.116723 progress 25 % (9 MB)
58 04:35:11.140998 progress 30 % (11 MB)
59 04:35:11.164663 progress 35 % (13 MB)
60 04:35:11.188895 progress 40 % (14 MB)
61 04:35:11.212442 progress 45 % (16 MB)
62 04:35:11.236352 progress 50 % (18 MB)
63 04:35:11.259973 progress 55 % (20 MB)
64 04:35:11.283745 progress 60 % (22 MB)
65 04:35:11.307316 progress 65 % (24 MB)
66 04:35:11.330870 progress 70 % (26 MB)
67 04:35:11.354520 progress 75 % (27 MB)
68 04:35:11.377550 progress 80 % (29 MB)
69 04:35:11.400929 progress 85 % (31 MB)
70 04:35:11.424066 progress 90 % (33 MB)
71 04:35:11.447348 progress 95 % (35 MB)
72 04:35:11.469668 progress 100 % (37 MB)
73 04:35:11.470382 37 MB downloaded in 0.52 s (71.87 MB/s)
74 04:35:11.470862 end: 1.2.1 http-download (duration 00:00:01) [common]
76 04:35:11.471674 end: 1.2 download-retry (duration 00:00:01) [common]
77 04:35:11.471947 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:35:11.472253 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:35:11.472725 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-176-g20371ba12063/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 04:35:11.472995 saving as /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/dtb/meson-g12b-a311d-libretech-cc.dtb
81 04:35:11.473203 total size: 54667 (0 MB)
82 04:35:11.473413 No compression specified
83 04:35:11.505244 progress 59 % (0 MB)
84 04:35:11.506123 progress 100 % (0 MB)
85 04:35:11.506674 0 MB downloaded in 0.03 s (1.56 MB/s)
86 04:35:11.507148 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:35:11.508016 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:35:11.508304 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:35:11.508580 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:35:11.509060 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-176-g20371ba12063/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
92 04:35:11.509321 saving as /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/modules/modules.tar
93 04:35:11.509540 total size: 11631492 (11 MB)
94 04:35:11.509763 Using unxz to decompress xz
95 04:35:11.543485 progress 0 % (0 MB)
96 04:35:11.616697 progress 5 % (0 MB)
97 04:35:11.700409 progress 10 % (1 MB)
98 04:35:11.790323 progress 15 % (1 MB)
99 04:35:11.868008 progress 20 % (2 MB)
100 04:35:11.951580 progress 25 % (2 MB)
101 04:35:12.036180 progress 30 % (3 MB)
102 04:35:12.116833 progress 35 % (3 MB)
103 04:35:12.192595 progress 40 % (4 MB)
104 04:35:12.271829 progress 45 % (5 MB)
105 04:35:12.352872 progress 50 % (5 MB)
106 04:35:12.431578 progress 55 % (6 MB)
107 04:35:12.513437 progress 60 % (6 MB)
108 04:35:12.601835 progress 65 % (7 MB)
109 04:35:12.685609 progress 70 % (7 MB)
110 04:35:12.780310 progress 75 % (8 MB)
111 04:35:12.871577 progress 80 % (8 MB)
112 04:35:12.953336 progress 85 % (9 MB)
113 04:35:13.031269 progress 90 % (10 MB)
114 04:35:13.110230 progress 95 % (10 MB)
115 04:35:13.184523 progress 100 % (11 MB)
116 04:35:13.199167 11 MB downloaded in 1.69 s (6.57 MB/s)
117 04:35:13.199768 end: 1.4.1 http-download (duration 00:00:02) [common]
119 04:35:13.201389 end: 1.4 download-retry (duration 00:00:02) [common]
120 04:35:13.201960 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 04:35:13.202525 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 04:35:13.203063 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:35:13.203611 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 04:35:13.204873 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg
125 04:35:13.205950 makedir: /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin
126 04:35:13.206677 makedir: /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/tests
127 04:35:13.207349 makedir: /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/results
128 04:35:13.208044 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-add-keys
129 04:35:13.209118 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-add-sources
130 04:35:13.210141 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-background-process-start
131 04:35:13.211157 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-background-process-stop
132 04:35:13.212228 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-common-functions
133 04:35:13.213242 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-echo-ipv4
134 04:35:13.214219 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-install-packages
135 04:35:13.215182 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-installed-packages
136 04:35:13.216200 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-os-build
137 04:35:13.217207 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-probe-channel
138 04:35:13.218175 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-probe-ip
139 04:35:13.219140 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-target-ip
140 04:35:13.220155 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-target-mac
141 04:35:13.221155 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-target-storage
142 04:35:13.222142 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-test-case
143 04:35:13.223108 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-test-event
144 04:35:13.224094 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-test-feedback
145 04:35:13.225076 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-test-raise
146 04:35:13.226045 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-test-reference
147 04:35:13.227039 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-test-runner
148 04:35:13.228058 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-test-set
149 04:35:13.229048 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-test-shell
150 04:35:13.230088 Updating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-install-packages (oe)
151 04:35:13.231155 Updating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/bin/lava-installed-packages (oe)
152 04:35:13.232081 Creating /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/environment
153 04:35:13.232907 LAVA metadata
154 04:35:13.233440 - LAVA_JOB_ID=675817
155 04:35:13.233912 - LAVA_DISPATCHER_IP=192.168.6.2
156 04:35:13.234643 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 04:35:13.236752 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 04:35:13.237394 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 04:35:13.237804 skipped lava-vland-overlay
160 04:35:13.238291 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 04:35:13.238797 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 04:35:13.239228 skipped lava-multinode-overlay
163 04:35:13.239711 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 04:35:13.240246 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 04:35:13.240738 Loading test definitions
166 04:35:13.241290 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 04:35:13.241727 Using /lava-675817 at stage 0
168 04:35:13.243603 uuid=675817_1.5.2.4.1 testdef=None
169 04:35:13.243961 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 04:35:13.244271 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 04:35:13.246202 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 04:35:13.247034 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 04:35:13.249420 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 04:35:13.250296 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 04:35:13.252602 runner path: /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/0/tests/0_dmesg test_uuid 675817_1.5.2.4.1
178 04:35:13.253223 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 04:35:13.254008 Creating lava-test-runner.conf files
181 04:35:13.254216 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/675817/lava-overlay-ujlg_pxg/lava-675817/0 for stage 0
182 04:35:13.254575 - 0_dmesg
183 04:35:13.254939 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 04:35:13.255228 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 04:35:13.279786 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 04:35:13.280265 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 04:35:13.280535 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 04:35:13.280807 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 04:35:13.281072 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 04:35:14.276037 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 04:35:14.276518 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 04:35:14.276786 extracting modules file /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/modules/modules.tar to /var/lib/lava/dispatcher/tmp/675817/extract-overlay-ramdisk-do4w3h96/ramdisk
193 04:35:15.626804 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 04:35:15.627288 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 04:35:15.627579 [common] Applying overlay /var/lib/lava/dispatcher/tmp/675817/compress-overlay-c2_1_pnq/overlay-1.5.2.5.tar.gz to ramdisk
196 04:35:15.627807 [common] Applying overlay /var/lib/lava/dispatcher/tmp/675817/compress-overlay-c2_1_pnq/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/675817/extract-overlay-ramdisk-do4w3h96/ramdisk
197 04:35:15.658729 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 04:35:15.659166 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 04:35:15.659434 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 04:35:15.659660 Converting downloaded kernel to a uImage
201 04:35:15.659962 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/kernel/Image /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/kernel/uImage
202 04:35:16.062511 output: Image Name:
203 04:35:16.062951 output: Created: Fri Aug 30 04:35:15 2024
204 04:35:16.063200 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 04:35:16.063411 output: Data Size: 39019008 Bytes = 38104.50 KiB = 37.21 MiB
206 04:35:16.063627 output: Load Address: 01080000
207 04:35:16.063844 output: Entry Point: 01080000
208 04:35:16.064097 output:
209 04:35:16.064453 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 04:35:16.064739 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 04:35:16.065022 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 04:35:16.065296 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 04:35:16.065576 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 04:35:16.065844 Building ramdisk /var/lib/lava/dispatcher/tmp/675817/extract-overlay-ramdisk-do4w3h96/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/675817/extract-overlay-ramdisk-do4w3h96/ramdisk
215 04:35:18.546656 >> 186561 blocks
216 04:35:26.941916 Adding RAMdisk u-boot header.
217 04:35:26.942629 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/675817/extract-overlay-ramdisk-do4w3h96/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/675817/extract-overlay-ramdisk-do4w3h96/ramdisk.cpio.gz.uboot
218 04:35:27.246505 output: Image Name:
219 04:35:27.247003 output: Created: Fri Aug 30 04:35:26 2024
220 04:35:27.247258 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 04:35:27.247506 output: Data Size: 26559353 Bytes = 25936.87 KiB = 25.33 MiB
222 04:35:27.247750 output: Load Address: 00000000
223 04:35:27.248085 output: Entry Point: 00000000
224 04:35:27.248666 output:
225 04:35:27.250063 rename /var/lib/lava/dispatcher/tmp/675817/extract-overlay-ramdisk-do4w3h96/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/ramdisk/ramdisk.cpio.gz.uboot
226 04:35:27.250982 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 04:35:27.251669 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 04:35:27.252437 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 04:35:27.253026 No LXC device requested
230 04:35:27.253671 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 04:35:27.254319 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 04:35:27.254950 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 04:35:27.255481 Checking files for TFTP limit of 4294967296 bytes.
234 04:35:27.258997 end: 1 tftp-deploy (duration 00:00:16) [common]
235 04:35:27.259755 start: 2 uboot-action (timeout 00:05:00) [common]
236 04:35:27.260482 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 04:35:27.261119 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 04:35:27.261755 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 04:35:27.262435 Using kernel file from prepare-kernel: 675817/tftp-deploy-jk4hyzen/kernel/uImage
240 04:35:27.263232 substitutions:
241 04:35:27.263755 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 04:35:27.264324 - {DTB_ADDR}: 0x01070000
243 04:35:27.264848 - {DTB}: 675817/tftp-deploy-jk4hyzen/dtb/meson-g12b-a311d-libretech-cc.dtb
244 04:35:27.265374 - {INITRD}: 675817/tftp-deploy-jk4hyzen/ramdisk/ramdisk.cpio.gz.uboot
245 04:35:27.265895 - {KERNEL_ADDR}: 0x01080000
246 04:35:27.266405 - {KERNEL}: 675817/tftp-deploy-jk4hyzen/kernel/uImage
247 04:35:27.266917 - {LAVA_MAC}: None
248 04:35:27.267484 - {PRESEED_CONFIG}: None
249 04:35:27.268030 - {PRESEED_LOCAL}: None
250 04:35:27.268551 - {RAMDISK_ADDR}: 0x08000000
251 04:35:27.269059 - {RAMDISK}: 675817/tftp-deploy-jk4hyzen/ramdisk/ramdisk.cpio.gz.uboot
252 04:35:27.269579 - {ROOT_PART}: None
253 04:35:27.270092 - {ROOT}: None
254 04:35:27.270604 - {SERVER_IP}: 192.168.6.2
255 04:35:27.271120 - {TEE_ADDR}: 0x83000000
256 04:35:27.271628 - {TEE}: None
257 04:35:27.272162 Parsed boot commands:
258 04:35:27.272666 - setenv autoload no
259 04:35:27.273181 - setenv initrd_high 0xffffffff
260 04:35:27.273686 - setenv fdt_high 0xffffffff
261 04:35:27.274190 - dhcp
262 04:35:27.274696 - setenv serverip 192.168.6.2
263 04:35:27.275203 - tftpboot 0x01080000 675817/tftp-deploy-jk4hyzen/kernel/uImage
264 04:35:27.275713 - tftpboot 0x08000000 675817/tftp-deploy-jk4hyzen/ramdisk/ramdisk.cpio.gz.uboot
265 04:35:27.276241 - tftpboot 0x01070000 675817/tftp-deploy-jk4hyzen/dtb/meson-g12b-a311d-libretech-cc.dtb
266 04:35:27.276744 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 04:35:27.277255 - bootm 0x01080000 0x08000000 0x01070000
268 04:35:27.277904 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 04:35:27.279785 start: 2.3 connect-device (timeout 00:05:00) [common]
271 04:35:27.280404 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 04:35:27.296939 Setting prompt string to ['lava-test: # ']
273 04:35:27.298786 end: 2.3 connect-device (duration 00:00:00) [common]
274 04:35:27.299559 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 04:35:27.300335 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 04:35:27.301006 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 04:35:27.302422 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 04:35:27.340807 >> OK - accepted request
279 04:35:27.342765 Returned 0 in 0 seconds
280 04:35:27.443679 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 04:35:27.445397 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 04:35:27.445956 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 04:35:27.446458 Setting prompt string to ['Hit any key to stop autoboot']
285 04:35:27.446913 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 04:35:27.448534 Trying 192.168.56.21...
287 04:35:27.449020 Connected to conserv1.
288 04:35:27.449433 Escape character is '^]'.
289 04:35:27.449853
290 04:35:27.450270 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 04:35:27.450696
292 04:35:39.468523 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 04:35:39.469215 bl2_stage_init 0x01
294 04:35:39.469687 bl2_stage_init 0x81
295 04:35:39.474036 hw id: 0x0000 - pwm id 0x01
296 04:35:39.474593 bl2_stage_init 0xc1
297 04:35:39.475057 bl2_stage_init 0x02
298 04:35:39.475508
299 04:35:39.479581 L0:00000000
300 04:35:39.480159 L1:20000703
301 04:35:39.480611 L2:00008067
302 04:35:39.481042 L3:14000000
303 04:35:39.485189 B2:00402000
304 04:35:39.485709 B1:e0f83180
305 04:35:39.486140
306 04:35:39.486572 TE: 58167
307 04:35:39.487001
308 04:35:39.490799 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 04:35:39.491313
310 04:35:39.491748 Board ID = 1
311 04:35:39.496515 Set A53 clk to 24M
312 04:35:39.497040 Set A73 clk to 24M
313 04:35:39.497472 Set clk81 to 24M
314 04:35:39.502118 A53 clk: 1200 MHz
315 04:35:39.502645 A73 clk: 1200 MHz
316 04:35:39.503078 CLK81: 166.6M
317 04:35:39.503505 smccc: 00012abd
318 04:35:39.507577 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 04:35:39.513165 board id: 1
320 04:35:39.519085 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 04:35:39.529867 fw parse done
322 04:35:39.535760 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 04:35:39.578163 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 04:35:39.589276 PIEI prepare done
325 04:35:39.589879 fastboot data load
326 04:35:39.590337 fastboot data verify
327 04:35:39.594477 verify result: 266
328 04:35:39.600092 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 04:35:39.600580 LPDDR4 probe
330 04:35:39.601018 ddr clk to 1584MHz
331 04:35:39.608073 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 04:35:39.645373
333 04:35:39.645923 dmc_version 0001
334 04:35:39.652036 Check phy result
335 04:35:39.657860 INFO : End of CA training
336 04:35:39.658350 INFO : End of initialization
337 04:35:39.663524 INFO : Training has run successfully!
338 04:35:39.664028 Check phy result
339 04:35:39.669072 INFO : End of initialization
340 04:35:39.669546 INFO : End of read enable training
341 04:35:39.674682 INFO : End of fine write leveling
342 04:35:39.680296 INFO : End of Write leveling coarse delay
343 04:35:39.680777 INFO : Training has run successfully!
344 04:35:39.681216 Check phy result
345 04:35:39.685879 INFO : End of initialization
346 04:35:39.686354 INFO : End of read dq deskew training
347 04:35:39.691462 INFO : End of MPR read delay center optimization
348 04:35:39.697097 INFO : End of write delay center optimization
349 04:35:39.702686 INFO : End of read delay center optimization
350 04:35:39.703160 INFO : End of max read latency training
351 04:35:39.708282 INFO : Training has run successfully!
352 04:35:39.708755 1D training succeed
353 04:35:39.717566 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 04:35:39.765078 Check phy result
355 04:35:39.765566 INFO : End of initialization
356 04:35:39.786813 INFO : End of 2D read delay Voltage center optimization
357 04:35:39.807094 INFO : End of 2D read delay Voltage center optimization
358 04:35:39.859462 INFO : End of 2D write delay Voltage center optimization
359 04:35:39.908688 INFO : End of 2D write delay Voltage center optimization
360 04:35:39.914217 INFO : Training has run successfully!
361 04:35:39.914693
362 04:35:39.915134 channel==0
363 04:35:39.919803 RxClkDly_Margin_A0==88 ps 9
364 04:35:39.920314 TxDqDly_Margin_A0==98 ps 10
365 04:35:39.925504 RxClkDly_Margin_A1==88 ps 9
366 04:35:39.925978 TxDqDly_Margin_A1==98 ps 10
367 04:35:39.926415 TrainedVREFDQ_A0==74
368 04:35:39.930988 TrainedVREFDQ_A1==74
369 04:35:39.931454 VrefDac_Margin_A0==25
370 04:35:39.931889 DeviceVref_Margin_A0==40
371 04:35:39.936679 VrefDac_Margin_A1==25
372 04:35:39.937150 DeviceVref_Margin_A1==40
373 04:35:39.937585
374 04:35:39.938018
375 04:35:39.942137 channel==1
376 04:35:39.942599 RxClkDly_Margin_A0==98 ps 10
377 04:35:39.943032 TxDqDly_Margin_A0==98 ps 10
378 04:35:39.947829 RxClkDly_Margin_A1==98 ps 10
379 04:35:39.948427 TxDqDly_Margin_A1==88 ps 9
380 04:35:39.953433 TrainedVREFDQ_A0==77
381 04:35:39.953917 TrainedVREFDQ_A1==77
382 04:35:39.954365 VrefDac_Margin_A0==22
383 04:35:39.959042 DeviceVref_Margin_A0==37
384 04:35:39.959527 VrefDac_Margin_A1==24
385 04:35:39.964703 DeviceVref_Margin_A1==37
386 04:35:39.965182
387 04:35:39.965630 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 04:35:39.970125
389 04:35:39.998173 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 04:35:39.998763 2D training succeed
391 04:35:40.003795 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 04:35:40.009339 auto size-- 65535DDR cs0 size: 2048MB
393 04:35:40.009818 DDR cs1 size: 2048MB
394 04:35:40.014865 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 04:35:40.015333 cs0 DataBus test pass
396 04:35:40.020587 cs1 DataBus test pass
397 04:35:40.021063 cs0 AddrBus test pass
398 04:35:40.021502 cs1 AddrBus test pass
399 04:35:40.021934
400 04:35:40.026075 100bdlr_step_size ps== 420
401 04:35:40.026563 result report
402 04:35:40.031658 boot times 0Enable ddr reg access
403 04:35:40.037091 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 04:35:40.050657 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 04:35:40.624287 0.0;M3 CHK:0;cm4_sp_mode 0
406 04:35:40.624927 MVN_1=0x00000000
407 04:35:40.629651 MVN_2=0x00000000
408 04:35:40.635553 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 04:35:40.636092 OPS=0x10
410 04:35:40.636542 ring efuse init
411 04:35:40.636975 chipver efuse init
412 04:35:40.641023 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 04:35:40.646647 [0.018961 Inits done]
414 04:35:40.647129 secure task start!
415 04:35:40.647569 high task start!
416 04:35:40.651211 low task start!
417 04:35:40.651694 run into bl31
418 04:35:40.657856 NOTICE: BL31: v1.3(release):4fc40b1
419 04:35:40.665671 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 04:35:40.666167 NOTICE: BL31: G12A normal boot!
421 04:35:40.691049 NOTICE: BL31: BL33 decompress pass
422 04:35:40.696768 ERROR: Error initializing runtime service opteed_fast
423 04:35:41.929732
424 04:35:41.930336
425 04:35:41.937982 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 04:35:41.938470
427 04:35:41.938910 Model: Libre Computer AML-A311D-CC Alta
428 04:35:42.146524 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 04:35:42.169941 DRAM: 2 GiB (effective 3.8 GiB)
430 04:35:42.312914 Core: 408 devices, 31 uclasses, devicetree: separate
431 04:35:42.317799 WDT: Not starting watchdog@f0d0
432 04:35:42.350873 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 04:35:42.363381 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 04:35:42.368423 ** Bad device specification mmc 0 **
435 04:35:42.378731 Card did not respond to voltage select! : -110
436 04:35:42.386325 ** Bad device specification mmc 0 **
437 04:35:42.386584 Couldn't find partition mmc 0
438 04:35:42.394827 Card did not respond to voltage select! : -110
439 04:35:42.400292 ** Bad device specification mmc 0 **
440 04:35:42.401303 Couldn't find partition mmc 0
441 04:35:42.405236 Error: could not access storage.
442 04:35:43.668687 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 04:35:43.669332 bl2_stage_init 0x01
444 04:35:43.669807 bl2_stage_init 0x81
445 04:35:43.674234 hw id: 0x0000 - pwm id 0x01
446 04:35:43.674721 bl2_stage_init 0xc1
447 04:35:43.675174 bl2_stage_init 0x02
448 04:35:43.675617
449 04:35:43.679830 L0:00000000
450 04:35:43.680340 L1:20000703
451 04:35:43.680791 L2:00008067
452 04:35:43.681231 L3:14000000
453 04:35:43.685439 B2:00402000
454 04:35:43.685910 B1:e0f83180
455 04:35:43.686355
456 04:35:43.686798 TE: 58124
457 04:35:43.687244
458 04:35:43.691045 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 04:35:43.691532
460 04:35:43.692001 Board ID = 1
461 04:35:43.696636 Set A53 clk to 24M
462 04:35:43.697114 Set A73 clk to 24M
463 04:35:43.697560 Set clk81 to 24M
464 04:35:43.702220 A53 clk: 1200 MHz
465 04:35:43.702696 A73 clk: 1200 MHz
466 04:35:43.703146 CLK81: 166.6M
467 04:35:43.703585 smccc: 00012a91
468 04:35:43.707811 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 04:35:43.713425 board id: 1
470 04:35:43.719284 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 04:35:43.730070 fw parse done
472 04:35:43.735925 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 04:35:43.778573 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 04:35:43.789472 PIEI prepare done
475 04:35:43.789966 fastboot data load
476 04:35:43.790426 fastboot data verify
477 04:35:43.795135 verify result: 266
478 04:35:43.800739 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 04:35:43.801232 LPDDR4 probe
480 04:35:43.801682 ddr clk to 1584MHz
481 04:35:43.808709 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 04:35:43.845970
483 04:35:43.846475 dmc_version 0001
484 04:35:43.852649 Check phy result
485 04:35:43.858539 INFO : End of CA training
486 04:35:43.859031 INFO : End of initialization
487 04:35:43.864167 INFO : Training has run successfully!
488 04:35:43.864646 Check phy result
489 04:35:43.869710 INFO : End of initialization
490 04:35:43.870180 INFO : End of read enable training
491 04:35:43.875293 INFO : End of fine write leveling
492 04:35:43.880928 INFO : End of Write leveling coarse delay
493 04:35:43.881439 INFO : Training has run successfully!
494 04:35:43.881887 Check phy result
495 04:35:43.886515 INFO : End of initialization
496 04:35:43.886987 INFO : End of read dq deskew training
497 04:35:43.892136 INFO : End of MPR read delay center optimization
498 04:35:43.897697 INFO : End of write delay center optimization
499 04:35:43.903308 INFO : End of read delay center optimization
500 04:35:43.903782 INFO : End of max read latency training
501 04:35:43.908918 INFO : Training has run successfully!
502 04:35:43.909395 1D training succeed
503 04:35:43.918201 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 04:35:43.965679 Check phy result
505 04:35:43.966230 INFO : End of initialization
506 04:35:43.987279 INFO : End of 2D read delay Voltage center optimization
507 04:35:44.006572 INFO : End of 2D read delay Voltage center optimization
508 04:35:44.058482 INFO : End of 2D write delay Voltage center optimization
509 04:35:44.107698 INFO : End of 2D write delay Voltage center optimization
510 04:35:44.113293 INFO : Training has run successfully!
511 04:35:44.113793
512 04:35:44.114243 channel==0
513 04:35:44.118911 RxClkDly_Margin_A0==88 ps 9
514 04:35:44.119395 TxDqDly_Margin_A0==98 ps 10
515 04:35:44.124479 RxClkDly_Margin_A1==78 ps 8
516 04:35:44.124976 TxDqDly_Margin_A1==88 ps 9
517 04:35:44.125430 TrainedVREFDQ_A0==74
518 04:35:44.130138 TrainedVREFDQ_A1==74
519 04:35:44.130611 VrefDac_Margin_A0==24
520 04:35:44.131055 DeviceVref_Margin_A0==40
521 04:35:44.135667 VrefDac_Margin_A1==25
522 04:35:44.136171 DeviceVref_Margin_A1==40
523 04:35:44.136616
524 04:35:44.137057
525 04:35:44.137491 channel==1
526 04:35:44.141303 RxClkDly_Margin_A0==78 ps 8
527 04:35:44.141785 TxDqDly_Margin_A0==88 ps 9
528 04:35:44.146896 RxClkDly_Margin_A1==88 ps 9
529 04:35:44.147368 TxDqDly_Margin_A1==88 ps 9
530 04:35:44.152458 TrainedVREFDQ_A0==77
531 04:35:44.152939 TrainedVREFDQ_A1==77
532 04:35:44.153386 VrefDac_Margin_A0==23
533 04:35:44.158139 DeviceVref_Margin_A0==37
534 04:35:44.158608 VrefDac_Margin_A1==24
535 04:35:44.159053 DeviceVref_Margin_A1==37
536 04:35:44.163680
537 04:35:44.164193 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 04:35:44.164645
539 04:35:44.197309 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000019 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 04:35:44.197862 2D training succeed
541 04:35:44.202921 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 04:35:44.208481 auto size-- 65535DDR cs0 size: 2048MB
543 04:35:44.208964 DDR cs1 size: 2048MB
544 04:35:44.214176 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 04:35:44.214663 cs0 DataBus test pass
546 04:35:44.219686 cs1 DataBus test pass
547 04:35:44.220204 cs0 AddrBus test pass
548 04:35:44.220653 cs1 AddrBus test pass
549 04:35:44.221099
550 04:35:44.225285 100bdlr_step_size ps== 420
551 04:35:44.225785 result report
552 04:35:44.230916 boot times 0Enable ddr reg access
553 04:35:44.236022 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 04:35:44.249405 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 04:35:44.821380 0.0;M3 CHK:0;cm4_sp_mode 0
556 04:35:44.821787 MVN_1=0x00000000
557 04:35:44.826982 MVN_2=0x00000000
558 04:35:44.832714 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 04:35:44.833084 OPS=0x10
560 04:35:44.833355 ring efuse init
561 04:35:44.833599 chipver efuse init
562 04:35:44.838303 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 04:35:44.843932 [0.018961 Inits done]
564 04:35:44.844404 secure task start!
565 04:35:44.844675 high task start!
566 04:35:44.848475 low task start!
567 04:35:44.848851 run into bl31
568 04:35:44.855270 NOTICE: BL31: v1.3(release):4fc40b1
569 04:35:44.862986 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 04:35:44.863379 NOTICE: BL31: G12A normal boot!
571 04:35:44.888334 NOTICE: BL31: BL33 decompress pass
572 04:35:44.894023 ERROR: Error initializing runtime service opteed_fast
573 04:35:46.127650
574 04:35:46.128090
575 04:35:46.135923 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 04:35:46.136403
577 04:35:46.136643 Model: Libre Computer AML-A311D-CC Alta
578 04:35:46.344921 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 04:35:46.367419 DRAM: 2 GiB (effective 3.8 GiB)
580 04:35:46.510182 Core: 408 devices, 31 uclasses, devicetree: separate
581 04:35:46.516176 WDT: Not starting watchdog@f0d0
582 04:35:46.548338 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 04:35:46.560884 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 04:35:46.565894 ** Bad device specification mmc 0 **
585 04:35:46.576976 Card did not respond to voltage select! : -110
586 04:35:46.584284 ** Bad device specification mmc 0 **
587 04:35:46.584884 Couldn't find partition mmc 0
588 04:35:46.592730 Card did not respond to voltage select! : -110
589 04:35:46.597907 ** Bad device specification mmc 0 **
590 04:35:46.598511 Couldn't find partition mmc 0
591 04:35:46.602798 Error: could not access storage.
592 04:35:46.946267 Net: eth0: ethernet@ff3f0000
593 04:35:46.946716 starting USB...
594 04:35:47.198150 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 04:35:47.198605 Starting the controller
596 04:35:47.205088 USB XHCI 1.10
597 04:35:48.837371 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 04:35:48.837820 bl2_stage_init 0x01
599 04:35:48.838044 bl2_stage_init 0x81
600 04:35:48.842886 hw id: 0x0000 - pwm id 0x01
601 04:35:48.843318 bl2_stage_init 0xc1
602 04:35:48.843679 bl2_stage_init 0x02
603 04:35:48.844024
604 04:35:48.848521 L0:00000000
605 04:35:48.848953 L1:20000703
606 04:35:48.849207 L2:00008067
607 04:35:48.849436 L3:14000000
608 04:35:48.854077 B2:00402000
609 04:35:48.854508 B1:e0f83180
610 04:35:48.854836
611 04:35:48.855165 TE: 58159
612 04:35:48.855511
613 04:35:48.859724 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 04:35:48.860045
615 04:35:48.860296 Board ID = 1
616 04:35:48.865287 Set A53 clk to 24M
617 04:35:48.865619 Set A73 clk to 24M
618 04:35:48.865836 Set clk81 to 24M
619 04:35:48.870889 A53 clk: 1200 MHz
620 04:35:48.871318 A73 clk: 1200 MHz
621 04:35:48.871659 CLK81: 166.6M
622 04:35:48.872046 smccc: 00012ab4
623 04:35:48.876472 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 04:35:48.882083 board id: 1
625 04:35:48.887009 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 04:35:48.898735 fw parse done
627 04:35:48.904581 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 04:35:48.946242 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 04:35:48.958186 PIEI prepare done
630 04:35:48.958546 fastboot data load
631 04:35:48.958766 fastboot data verify
632 04:35:48.963796 verify result: 266
633 04:35:48.969350 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 04:35:48.969662 LPDDR4 probe
635 04:35:48.969896 ddr clk to 1584MHz
636 04:35:48.977351 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 04:35:49.014705
638 04:35:49.015092 dmc_version 0001
639 04:35:49.021287 Check phy result
640 04:35:49.027190 INFO : End of CA training
641 04:35:49.027529 INFO : End of initialization
642 04:35:49.032829 INFO : Training has run successfully!
643 04:35:49.033193 Check phy result
644 04:35:49.038414 INFO : End of initialization
645 04:35:49.038771 INFO : End of read enable training
646 04:35:49.044003 INFO : End of fine write leveling
647 04:35:49.049588 INFO : End of Write leveling coarse delay
648 04:35:49.049967 INFO : Training has run successfully!
649 04:35:49.050196 Check phy result
650 04:35:49.055212 INFO : End of initialization
651 04:35:49.055582 INFO : End of read dq deskew training
652 04:35:49.060830 INFO : End of MPR read delay center optimization
653 04:35:49.066592 INFO : End of write delay center optimization
654 04:35:49.072007 INFO : End of read delay center optimization
655 04:35:49.072377 INFO : End of max read latency training
656 04:35:49.077563 INFO : Training has run successfully!
657 04:35:49.077923 1D training succeed
658 04:35:49.086990 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 04:35:49.134399 Check phy result
660 04:35:49.134823 INFO : End of initialization
661 04:35:49.156114 INFO : End of 2D read delay Voltage center optimization
662 04:35:49.176324 INFO : End of 2D read delay Voltage center optimization
663 04:35:49.228365 INFO : End of 2D write delay Voltage center optimization
664 04:35:49.277697 INFO : End of 2D write delay Voltage center optimization
665 04:35:49.283261 INFO : Training has run successfully!
666 04:35:49.283632
667 04:35:49.283894 channel==0
668 04:35:49.288849 RxClkDly_Margin_A0==88 ps 9
669 04:35:49.289209 TxDqDly_Margin_A0==98 ps 10
670 04:35:49.294486 RxClkDly_Margin_A1==78 ps 8
671 04:35:49.294985 TxDqDly_Margin_A1==98 ps 10
672 04:35:49.295381 TrainedVREFDQ_A0==74
673 04:35:49.300090 TrainedVREFDQ_A1==74
674 04:35:49.300459 VrefDac_Margin_A0==25
675 04:35:49.300715 DeviceVref_Margin_A0==40
676 04:35:49.305634 VrefDac_Margin_A1==25
677 04:35:49.306142 DeviceVref_Margin_A1==40
678 04:35:49.306541
679 04:35:49.306907
680 04:35:49.311256 channel==1
681 04:35:49.311605 RxClkDly_Margin_A0==98 ps 10
682 04:35:49.311888 TxDqDly_Margin_A0==88 ps 9
683 04:35:49.316842 RxClkDly_Margin_A1==98 ps 10
684 04:35:49.317196 TxDqDly_Margin_A1==88 ps 9
685 04:35:49.322461 TrainedVREFDQ_A0==75
686 04:35:49.322828 TrainedVREFDQ_A1==77
687 04:35:49.323067 VrefDac_Margin_A0==22
688 04:35:49.328093 DeviceVref_Margin_A0==38
689 04:35:49.328615 VrefDac_Margin_A1==22
690 04:35:49.333655 DeviceVref_Margin_A1==37
691 04:35:49.334150
692 04:35:49.334527 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 04:35:49.334824
694 04:35:49.367289 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 04:35:49.367889 2D training succeed
696 04:35:49.372925 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 04:35:49.378499 auto size-- 65535DDR cs0 size: 2048MB
698 04:35:49.378888 DDR cs1 size: 2048MB
699 04:35:49.384109 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 04:35:49.384650 cs0 DataBus test pass
701 04:35:49.389709 cs1 DataBus test pass
702 04:35:49.390089 cs0 AddrBus test pass
703 04:35:49.390328 cs1 AddrBus test pass
704 04:35:49.390558
705 04:35:49.395303 100bdlr_step_size ps== 420
706 04:35:49.395707 result report
707 04:35:49.400933 boot times 0Enable ddr reg access
708 04:35:49.406221 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 04:35:49.419711 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 04:35:49.993349 0.0;M3 CHK:0;cm4_sp_mode 0
711 04:35:49.996232 MVN_1=0x00000000
712 04:35:49.998896 MVN_2=0x00000000
713 04:35:50.004611 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 04:35:50.004946 OPS=0x10
715 04:35:50.005164 ring efuse init
716 04:35:50.005367 chipver efuse init
717 04:35:50.010189 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 04:35:50.015861 [0.018961 Inits done]
719 04:35:50.016216 secure task start!
720 04:35:50.016443 high task start!
721 04:35:50.020376 low task start!
722 04:35:50.020716 run into bl31
723 04:35:50.027013 NOTICE: BL31: v1.3(release):4fc40b1
724 04:35:50.034966 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 04:35:50.035322 NOTICE: BL31: G12A normal boot!
726 04:35:50.060212 NOTICE: BL31: BL33 decompress pass
727 04:35:50.065949 ERROR: Error initializing runtime service opteed_fast
728 04:35:51.298766
729 04:35:51.299205
730 04:35:51.307170 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 04:35:51.307518
732 04:35:51.307740 Model: Libre Computer AML-A311D-CC Alta
733 04:35:51.515718 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 04:35:51.539087 DRAM: 2 GiB (effective 3.8 GiB)
735 04:35:51.682069 Core: 408 devices, 31 uclasses, devicetree: separate
736 04:35:51.687866 WDT: Not starting watchdog@f0d0
737 04:35:51.720180 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 04:35:51.732537 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 04:35:51.737968 ** Bad device specification mmc 0 **
740 04:35:51.747910 Card did not respond to voltage select! : -110
741 04:35:51.755587 ** Bad device specification mmc 0 **
742 04:35:51.756313 Couldn't find partition mmc 0
743 04:35:51.763873 Card did not respond to voltage select! : -110
744 04:35:51.769382 ** Bad device specification mmc 0 **
745 04:35:51.769919 Couldn't find partition mmc 0
746 04:35:51.774432 Error: could not access storage.
747 04:35:52.116971 Net: eth0: ethernet@ff3f0000
748 04:35:52.117594 starting USB...
749 04:35:52.368774 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 04:35:52.369601 Starting the controller
751 04:35:52.375692 USB XHCI 1.10
752 04:35:54.537412 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 04:35:54.537842 bl2_stage_init 0x01
754 04:35:54.538063 bl2_stage_init 0x81
755 04:35:54.542924 hw id: 0x0000 - pwm id 0x01
756 04:35:54.543206 bl2_stage_init 0xc1
757 04:35:54.543422 bl2_stage_init 0x02
758 04:35:54.543627
759 04:35:54.548534 L0:00000000
760 04:35:54.548832 L1:20000703
761 04:35:54.549054 L2:00008067
762 04:35:54.549271 L3:14000000
763 04:35:54.553998 B2:00402000
764 04:35:54.554270 B1:e0f83180
765 04:35:54.554489
766 04:35:54.554706 TE: 58124
767 04:35:54.554925
768 04:35:54.559711 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 04:35:54.560041
770 04:35:54.560274 Board ID = 1
771 04:35:54.565409 Set A53 clk to 24M
772 04:35:54.565919 Set A73 clk to 24M
773 04:35:54.566322 Set clk81 to 24M
774 04:35:54.570907 A53 clk: 1200 MHz
775 04:35:54.571369 A73 clk: 1200 MHz
776 04:35:54.571765 CLK81: 166.6M
777 04:35:54.572192 smccc: 00012a91
778 04:35:54.576570 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 04:35:54.582063 board id: 1
780 04:35:54.588169 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 04:35:54.598583 fw parse done
782 04:35:54.604686 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 04:35:54.647191 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 04:35:54.658080 PIEI prepare done
785 04:35:54.658570 fastboot data load
786 04:35:54.658975 fastboot data verify
787 04:35:54.663789 verify result: 266
788 04:35:54.669438 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 04:35:54.669919 LPDDR4 probe
790 04:35:54.670314 ddr clk to 1584MHz
791 04:35:54.677322 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 04:35:54.714610
793 04:35:54.715145 dmc_version 0001
794 04:35:54.721331 Check phy result
795 04:35:54.727102 INFO : End of CA training
796 04:35:54.727581 INFO : End of initialization
797 04:35:54.732772 INFO : Training has run successfully!
798 04:35:54.733258 Check phy result
799 04:35:54.738358 INFO : End of initialization
800 04:35:54.738835 INFO : End of read enable training
801 04:35:54.741672 INFO : End of fine write leveling
802 04:35:54.747141 INFO : End of Write leveling coarse delay
803 04:35:54.752798 INFO : Training has run successfully!
804 04:35:54.753251 Check phy result
805 04:35:54.753642 INFO : End of initialization
806 04:35:54.758296 INFO : End of read dq deskew training
807 04:35:54.764048 INFO : End of MPR read delay center optimization
808 04:35:54.764589 INFO : End of write delay center optimization
809 04:35:54.769606 INFO : End of read delay center optimization
810 04:35:54.775121 INFO : End of max read latency training
811 04:35:54.775622 INFO : Training has run successfully!
812 04:35:54.780782 1D training succeed
813 04:35:54.786692 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 04:35:54.834340 Check phy result
815 04:35:54.834888 INFO : End of initialization
816 04:35:54.855098 INFO : End of 2D read delay Voltage center optimization
817 04:35:54.876375 INFO : End of 2D read delay Voltage center optimization
818 04:35:54.928323 INFO : End of 2D write delay Voltage center optimization
819 04:35:54.980221 INFO : End of 2D write delay Voltage center optimization
820 04:35:54.983181 INFO : Training has run successfully!
821 04:35:54.983466
822 04:35:54.983678 channel==0
823 04:35:54.988842 RxClkDly_Margin_A0==88 ps 9
824 04:35:54.989115 TxDqDly_Margin_A0==98 ps 10
825 04:35:54.994580 RxClkDly_Margin_A1==78 ps 8
826 04:35:54.995190 TxDqDly_Margin_A1==98 ps 10
827 04:35:54.995647 TrainedVREFDQ_A0==74
828 04:35:55.000109 TrainedVREFDQ_A1==74
829 04:35:55.000665 VrefDac_Margin_A0==25
830 04:35:55.001108 DeviceVref_Margin_A0==40
831 04:35:55.005874 VrefDac_Margin_A1==25
832 04:35:55.006441 DeviceVref_Margin_A1==40
833 04:35:55.006882
834 04:35:55.007315
835 04:35:55.011358 channel==1
836 04:35:55.011929 RxClkDly_Margin_A0==88 ps 9
837 04:35:55.012402 TxDqDly_Margin_A0==88 ps 9
838 04:35:55.016964 RxClkDly_Margin_A1==98 ps 10
839 04:35:55.017522 TxDqDly_Margin_A1==88 ps 9
840 04:35:55.022623 TrainedVREFDQ_A0==74
841 04:35:55.023183 TrainedVREFDQ_A1==77
842 04:35:55.023625 VrefDac_Margin_A0==22
843 04:35:55.028162 DeviceVref_Margin_A0==40
844 04:35:55.028732 VrefDac_Margin_A1==22
845 04:35:55.033831 DeviceVref_Margin_A1==37
846 04:35:55.034382
847 04:35:55.034820 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 04:35:55.035255
849 04:35:55.067282 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
850 04:35:55.067916 2D training succeed
851 04:35:55.072964 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 04:35:55.078515 auto size-- 65535DDR cs0 size: 2048MB
853 04:35:55.079086 DDR cs1 size: 2048MB
854 04:35:55.084130 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 04:35:55.084710 cs0 DataBus test pass
856 04:35:55.089817 cs1 DataBus test pass
857 04:35:55.090366 cs0 AddrBus test pass
858 04:35:55.090804 cs1 AddrBus test pass
859 04:35:55.091232
860 04:35:55.095273 100bdlr_step_size ps== 420
861 04:35:55.095836 result report
862 04:35:55.100915 boot times 0Enable ddr reg access
863 04:35:55.106169 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 04:35:55.119586 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 04:35:55.693449 0.0;M3 CHK:0;cm4_sp_mode 0
866 04:35:55.694134 MVN_1=0x00000000
867 04:35:55.699024 MVN_2=0x00000000
868 04:35:55.704739 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 04:35:55.705314 OPS=0x10
870 04:35:55.705780 ring efuse init
871 04:35:55.706228 chipver efuse init
872 04:35:55.712929 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 04:35:55.713532 [0.018960 Inits done]
874 04:35:55.720411 secure task start!
875 04:35:55.720976 high task start!
876 04:35:55.721449 low task start!
877 04:35:55.721913 run into bl31
878 04:35:55.727036 NOTICE: BL31: v1.3(release):4fc40b1
879 04:35:55.735083 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 04:35:55.735651 NOTICE: BL31: G12A normal boot!
881 04:35:55.760190 NOTICE: BL31: BL33 decompress pass
882 04:35:55.765934 ERROR: Error initializing runtime service opteed_fast
883 04:35:56.998782
884 04:35:56.999461
885 04:35:57.007278 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 04:35:57.007837
887 04:35:57.008359 Model: Libre Computer AML-A311D-CC Alta
888 04:35:57.215604 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 04:35:57.239084 DRAM: 2 GiB (effective 3.8 GiB)
890 04:35:57.381915 Core: 408 devices, 31 uclasses, devicetree: separate
891 04:35:57.387917 WDT: Not starting watchdog@f0d0
892 04:35:57.420210 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 04:35:57.432509 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 04:35:57.437555 ** Bad device specification mmc 0 **
895 04:35:57.447886 Card did not respond to voltage select! : -110
896 04:35:57.455509 ** Bad device specification mmc 0 **
897 04:35:57.456072 Couldn't find partition mmc 0
898 04:35:57.463878 Card did not respond to voltage select! : -110
899 04:35:57.469395 ** Bad device specification mmc 0 **
900 04:35:57.469939 Couldn't find partition mmc 0
901 04:35:57.474487 Error: could not access storage.
902 04:35:57.816823 Net: eth0: ethernet@ff3f0000
903 04:35:57.817255 starting USB...
904 04:35:58.069012 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 04:35:58.069653 Starting the controller
906 04:35:58.075009 USB XHCI 1.10
907 04:35:59.629581 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 04:35:59.637888 scanning usb for storage devices... 0 Storage Device(s) found
910 04:35:59.689508 Hit any key to stop autoboot: 1
911 04:35:59.690621 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 04:35:59.691300 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 04:35:59.691829 Setting prompt string to ['=>']
914 04:35:59.692411 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 04:35:59.704467 0
916 04:35:59.705411 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 04:35:59.705956 Sending with 10 millisecond of delay
919 04:36:00.842079 => setenv autoload no
920 04:36:00.852677 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
921 04:36:00.858110 setenv autoload no
922 04:36:00.858892 Sending with 10 millisecond of delay
924 04:36:02.659819 => setenv initrd_high 0xffffffff
925 04:36:02.670960 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 04:36:02.671640 setenv initrd_high 0xffffffff
927 04:36:02.672590 Sending with 10 millisecond of delay
929 04:36:04.289718 => setenv fdt_high 0xffffffff
930 04:36:04.300569 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 04:36:04.301584 setenv fdt_high 0xffffffff
932 04:36:04.302234 Sending with 10 millisecond of delay
934 04:36:04.593782 => dhcp
935 04:36:04.604603 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 04:36:04.605524 dhcp
937 04:36:04.605766 Speed: 1000, full duplex
938 04:36:04.605979 BOOTP broadcast 1
939 04:36:04.852162 BOOTP broadcast 2
940 04:36:05.054875 DHCP client bound to address 192.168.6.33 (451 ms)
941 04:36:05.055830 Sending with 10 millisecond of delay
943 04:36:06.735061 => setenv serverip 192.168.6.2
944 04:36:06.746067 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
945 04:36:06.747202 setenv serverip 192.168.6.2
946 04:36:06.748031 Sending with 10 millisecond of delay
948 04:36:10.473266 => tftpboot 0x01080000 675817/tftp-deploy-jk4hyzen/kernel/uImage
949 04:36:10.484090 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
950 04:36:10.484721 tftpboot 0x01080000 675817/tftp-deploy-jk4hyzen/kernel/uImage
951 04:36:10.484963 Speed: 1000, full duplex
952 04:36:10.485175 Using ethernet@ff3f0000 device
953 04:36:10.486583 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
954 04:36:10.492177 Filename '675817/tftp-deploy-jk4hyzen/kernel/uImage'.
955 04:36:10.496325 Load address: 0x1080000
956 04:36:12.578532 Loading: *######################################### UDP wrong checksum 000000ff 0000c469
957 04:36:12.587213 # UDP wrong checksum 000000ff 0000585c
958 04:36:13.020158 ######## 37.2 MiB
959 04:36:13.020580 14.7 MiB/s
960 04:36:13.020797 done
961 04:36:13.023263 Bytes transferred = 39019072 (2536240 hex)
962 04:36:13.023832 Sending with 10 millisecond of delay
964 04:36:17.714123 => tftpboot 0x08000000 675817/tftp-deploy-jk4hyzen/ramdisk/ramdisk.cpio.gz.uboot
965 04:36:17.724906 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
966 04:36:17.725829 tftpboot 0x08000000 675817/tftp-deploy-jk4hyzen/ramdisk/ramdisk.cpio.gz.uboot
967 04:36:17.726272 Speed: 1000, full duplex
968 04:36:17.726675 Using ethernet@ff3f0000 device
969 04:36:17.727582 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
970 04:36:17.739560 Filename '675817/tftp-deploy-jk4hyzen/ramdisk/ramdisk.cpio.gz.uboot'.
971 04:36:17.740151 Load address: 0x8000000
972 04:36:24.596411 Loading: *#########################T ######################## UDP wrong checksum 00000005 00000f88
973 04:36:29.596682 T UDP wrong checksum 00000005 00000f88
974 04:36:39.598366 T T UDP wrong checksum 00000005 00000f88
975 04:36:51.767283 T T UDP wrong checksum 000000ff 000013c7
976 04:36:51.786680 UDP wrong checksum 000000ff 00009ab9
977 04:36:59.598916 T UDP wrong checksum 00000005 00000f88
978 04:37:12.606188 T T T UDP wrong checksum 000000ff 00001fcf
979 04:37:12.639079 UDP wrong checksum 000000ff 0000a4c1
980 04:37:14.605731
981 04:37:14.606384 Retry count exceeded; starting again
983 04:37:14.607901 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
986 04:37:14.609929 end: 2.4 uboot-commands (duration 00:01:47) [common]
988 04:37:14.611416 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
990 04:37:14.612623 end: 2 uboot-action (duration 00:01:47) [common]
992 04:37:14.614312 Cleaning after the job
993 04:37:14.614929 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/ramdisk
994 04:37:14.616383 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/kernel
995 04:37:14.623882 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/dtb
996 04:37:14.625264 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675817/tftp-deploy-jk4hyzen/modules
997 04:37:14.632681 start: 4.1 power-off (timeout 00:00:30) [common]
998 04:37:14.633795 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
999 04:37:14.690243 >> OK - accepted request
1000 04:37:14.692311 Returned 0 in 0 seconds
1001 04:37:14.793520 end: 4.1 power-off (duration 00:00:00) [common]
1003 04:37:14.795375 start: 4.2 read-feedback (timeout 00:10:00) [common]
1004 04:37:14.796658 Listened to connection for namespace 'common' for up to 1s
1005 04:37:15.796447 Finalising connection for namespace 'common'
1006 04:37:15.797251 Disconnecting from shell: Finalise
1007 04:37:15.797852 =>
1008 04:37:15.898967 end: 4.2 read-feedback (duration 00:00:01) [common]
1009 04:37:15.899743 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/675817
1010 04:37:16.193474 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/675817
1011 04:37:16.194066 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.