Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:12:30.085843 lava-dispatcher, installed at version: 2024.01
2 04:12:30.086638 start: 0 validate
3 04:12:30.087125 Start time: 2024-08-30 04:12:30.087092+00:00 (UTC)
4 04:12:30.087686 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:12:30.088263 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 04:12:30.125247 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:12:30.125861 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-176-g20371ba12063%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:12:30.156125 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:12:30.156807 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-176-g20371ba12063%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:12:31.202643 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:12:31.203186 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-176-g20371ba12063%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 04:12:31.245338 validate duration: 1.16
14 04:12:31.246446 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:12:31.246821 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:12:31.247155 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:12:31.247746 Not decompressing ramdisk as can be used compressed.
18 04:12:31.248214 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 04:12:31.248480 saving as /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/ramdisk/rootfs.cpio.gz
20 04:12:31.248745 total size: 8181887 (7 MB)
21 04:12:31.283086 progress 0 % (0 MB)
22 04:12:31.289359 progress 5 % (0 MB)
23 04:12:31.295109 progress 10 % (0 MB)
24 04:12:31.301304 progress 15 % (1 MB)
25 04:12:31.306953 progress 20 % (1 MB)
26 04:12:31.313143 progress 25 % (1 MB)
27 04:12:31.318814 progress 30 % (2 MB)
28 04:12:31.325073 progress 35 % (2 MB)
29 04:12:31.330786 progress 40 % (3 MB)
30 04:12:31.337166 progress 45 % (3 MB)
31 04:12:31.342855 progress 50 % (3 MB)
32 04:12:31.349977 progress 55 % (4 MB)
33 04:12:31.355799 progress 60 % (4 MB)
34 04:12:31.361923 progress 65 % (5 MB)
35 04:12:31.367803 progress 70 % (5 MB)
36 04:12:31.374076 progress 75 % (5 MB)
37 04:12:31.379878 progress 80 % (6 MB)
38 04:12:31.386108 progress 85 % (6 MB)
39 04:12:31.391747 progress 90 % (7 MB)
40 04:12:31.397454 progress 95 % (7 MB)
41 04:12:31.402820 progress 100 % (7 MB)
42 04:12:31.403746 7 MB downloaded in 0.15 s (50.35 MB/s)
43 04:12:31.404408 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:12:31.405420 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:12:31.405767 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:12:31.406084 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:12:31.406627 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-176-g20371ba12063/arm64/defconfig/gcc-12/kernel/Image
49 04:12:31.406913 saving as /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/kernel/Image
50 04:12:31.407145 total size: 45308416 (43 MB)
51 04:12:31.407395 No compression specified
52 04:12:31.440922 progress 0 % (0 MB)
53 04:12:31.470690 progress 5 % (2 MB)
54 04:12:31.501108 progress 10 % (4 MB)
55 04:12:31.531163 progress 15 % (6 MB)
56 04:12:31.561221 progress 20 % (8 MB)
57 04:12:31.590950 progress 25 % (10 MB)
58 04:12:31.620370 progress 30 % (12 MB)
59 04:12:31.649840 progress 35 % (15 MB)
60 04:12:31.679918 progress 40 % (17 MB)
61 04:12:31.709477 progress 45 % (19 MB)
62 04:12:31.747162 progress 50 % (21 MB)
63 04:12:31.776037 progress 55 % (23 MB)
64 04:12:31.806153 progress 60 % (25 MB)
65 04:12:31.837221 progress 65 % (28 MB)
66 04:12:31.865930 progress 70 % (30 MB)
67 04:12:31.895372 progress 75 % (32 MB)
68 04:12:31.924576 progress 80 % (34 MB)
69 04:12:31.954226 progress 85 % (36 MB)
70 04:12:31.987538 progress 90 % (38 MB)
71 04:12:32.016927 progress 95 % (41 MB)
72 04:12:32.045159 progress 100 % (43 MB)
73 04:12:32.045893 43 MB downloaded in 0.64 s (67.65 MB/s)
74 04:12:32.046404 end: 1.2.1 http-download (duration 00:00:01) [common]
76 04:12:32.047278 end: 1.2 download-retry (duration 00:00:01) [common]
77 04:12:32.047585 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:12:32.047869 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:12:32.048385 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-176-g20371ba12063/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 04:12:32.048675 saving as /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/dtb/meson-g12b-a311d-libretech-cc.dtb
81 04:12:32.048895 total size: 54667 (0 MB)
82 04:12:32.049118 No compression specified
83 04:12:32.089042 progress 59 % (0 MB)
84 04:12:32.089924 progress 100 % (0 MB)
85 04:12:32.090514 0 MB downloaded in 0.04 s (1.25 MB/s)
86 04:12:32.091027 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:12:32.091913 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:12:32.092235 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:12:32.092529 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:12:32.093094 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-176-g20371ba12063/arm64/defconfig/gcc-12/modules.tar.xz
92 04:12:32.093378 saving as /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/modules/modules.tar
93 04:12:32.093597 total size: 11492696 (10 MB)
94 04:12:32.093823 Using unxz to decompress xz
95 04:12:32.130586 progress 0 % (0 MB)
96 04:12:32.205820 progress 5 % (0 MB)
97 04:12:32.294202 progress 10 % (1 MB)
98 04:12:32.380101 progress 15 % (1 MB)
99 04:12:32.476175 progress 20 % (2 MB)
100 04:12:32.559142 progress 25 % (2 MB)
101 04:12:32.642052 progress 30 % (3 MB)
102 04:12:32.719415 progress 35 % (3 MB)
103 04:12:32.809922 progress 40 % (4 MB)
104 04:12:32.889460 progress 45 % (4 MB)
105 04:12:32.971000 progress 50 % (5 MB)
106 04:12:33.051632 progress 55 % (6 MB)
107 04:12:33.131781 progress 60 % (6 MB)
108 04:12:33.213223 progress 65 % (7 MB)
109 04:12:33.294943 progress 70 % (7 MB)
110 04:12:33.378922 progress 75 % (8 MB)
111 04:12:33.473693 progress 80 % (8 MB)
112 04:12:33.575466 progress 85 % (9 MB)
113 04:12:33.649412 progress 90 % (9 MB)
114 04:12:33.728995 progress 95 % (10 MB)
115 04:12:33.806261 progress 100 % (10 MB)
116 04:12:33.821180 10 MB downloaded in 1.73 s (6.34 MB/s)
117 04:12:33.821834 end: 1.4.1 http-download (duration 00:00:02) [common]
119 04:12:33.822722 end: 1.4 download-retry (duration 00:00:02) [common]
120 04:12:33.823018 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 04:12:33.823301 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 04:12:33.823566 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:12:33.823837 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 04:12:33.824606 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo
125 04:12:33.825154 makedir: /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin
126 04:12:33.825547 makedir: /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/tests
127 04:12:33.825922 makedir: /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/results
128 04:12:33.826295 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-add-keys
129 04:12:33.826888 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-add-sources
130 04:12:33.827463 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-background-process-start
131 04:12:33.828093 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-background-process-stop
132 04:12:33.828716 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-common-functions
133 04:12:33.829313 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-echo-ipv4
134 04:12:33.829873 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-install-packages
135 04:12:33.830435 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-installed-packages
136 04:12:33.831009 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-os-build
137 04:12:33.831656 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-probe-channel
138 04:12:33.832258 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-probe-ip
139 04:12:33.832879 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-target-ip
140 04:12:33.833453 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-target-mac
141 04:12:33.834011 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-target-storage
142 04:12:33.834579 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-test-case
143 04:12:33.835128 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-test-event
144 04:12:33.835694 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-test-feedback
145 04:12:33.836267 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-test-raise
146 04:12:33.836813 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-test-reference
147 04:12:33.837362 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-test-runner
148 04:12:33.837908 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-test-set
149 04:12:33.838550 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-test-shell
150 04:12:33.839200 Updating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-install-packages (oe)
151 04:12:33.839818 Updating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/bin/lava-installed-packages (oe)
152 04:12:33.840382 Creating /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/environment
153 04:12:33.840834 LAVA metadata
154 04:12:33.841122 - LAVA_JOB_ID=675681
155 04:12:33.841352 - LAVA_DISPATCHER_IP=192.168.6.2
156 04:12:33.841749 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 04:12:33.842859 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 04:12:33.843209 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 04:12:33.843435 skipped lava-vland-overlay
160 04:12:33.843701 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 04:12:33.844011 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 04:12:33.844269 skipped lava-multinode-overlay
163 04:12:33.844541 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 04:12:33.844820 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 04:12:33.845100 Loading test definitions
166 04:12:33.845411 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 04:12:33.845653 Using /lava-675681 at stage 0
168 04:12:33.846955 uuid=675681_1.5.2.4.1 testdef=None
169 04:12:33.847298 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 04:12:33.847583 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 04:12:33.849631 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 04:12:33.850495 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 04:12:33.853068 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 04:12:33.853985 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 04:12:33.856440 runner path: /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/0/tests/0_dmesg test_uuid 675681_1.5.2.4.1
178 04:12:33.857126 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 04:12:33.857957 Creating lava-test-runner.conf files
181 04:12:33.858175 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/675681/lava-overlay-c4c4h4zo/lava-675681/0 for stage 0
182 04:12:33.858612 - 0_dmesg
183 04:12:33.859056 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 04:12:33.859369 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 04:12:33.885387 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 04:12:33.885847 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 04:12:33.886136 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 04:12:33.886428 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 04:12:33.886714 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 04:12:34.864147 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 04:12:34.864653 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 04:12:34.864929 extracting modules file /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/675681/extract-overlay-ramdisk-nuupfjeo/ramdisk
193 04:12:36.343214 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 04:12:36.348667 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 04:12:36.349110 [common] Applying overlay /var/lib/lava/dispatcher/tmp/675681/compress-overlay-n3jqrbr4/overlay-1.5.2.5.tar.gz to ramdisk
196 04:12:36.349327 [common] Applying overlay /var/lib/lava/dispatcher/tmp/675681/compress-overlay-n3jqrbr4/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/675681/extract-overlay-ramdisk-nuupfjeo/ramdisk
197 04:12:36.383706 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 04:12:36.384221 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 04:12:36.384558 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 04:12:36.384836 Converting downloaded kernel to a uImage
201 04:12:36.385193 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/kernel/Image /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/kernel/uImage
202 04:12:36.883055 output: Image Name:
203 04:12:36.883480 output: Created: Fri Aug 30 04:12:36 2024
204 04:12:36.883707 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 04:12:36.883924 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
206 04:12:36.884197 output: Load Address: 01080000
207 04:12:36.884432 output: Entry Point: 01080000
208 04:12:36.884640 output:
209 04:12:36.885009 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 04:12:36.885324 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 04:12:36.885630 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 04:12:36.885911 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 04:12:36.886198 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 04:12:36.886463 Building ramdisk /var/lib/lava/dispatcher/tmp/675681/extract-overlay-ramdisk-nuupfjeo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/675681/extract-overlay-ramdisk-nuupfjeo/ramdisk
215 04:12:40.284597 >> 179908 blocks
216 04:12:48.785776 Adding RAMdisk u-boot header.
217 04:12:48.786240 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/675681/extract-overlay-ramdisk-nuupfjeo/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/675681/extract-overlay-ramdisk-nuupfjeo/ramdisk.cpio.gz.uboot
218 04:12:49.066698 output: Image Name:
219 04:12:49.067136 output: Created: Fri Aug 30 04:12:48 2024
220 04:12:49.067356 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 04:12:49.067564 output: Data Size: 25882743 Bytes = 25276.12 KiB = 24.68 MiB
222 04:12:49.067768 output: Load Address: 00000000
223 04:12:49.067967 output: Entry Point: 00000000
224 04:12:49.068213 output:
225 04:12:49.068932 rename /var/lib/lava/dispatcher/tmp/675681/extract-overlay-ramdisk-nuupfjeo/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/ramdisk/ramdisk.cpio.gz.uboot
226 04:12:49.069401 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 04:12:49.069847 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 04:12:49.070174 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
229 04:12:49.070433 No LXC device requested
230 04:12:49.070703 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 04:12:49.070975 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
232 04:12:49.071237 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 04:12:49.071456 Checking files for TFTP limit of 4294967296 bytes.
234 04:12:49.072992 end: 1 tftp-deploy (duration 00:00:18) [common]
235 04:12:49.073493 start: 2 uboot-action (timeout 00:05:00) [common]
236 04:12:49.073810 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 04:12:49.074082 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 04:12:49.074357 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 04:12:49.074650 Using kernel file from prepare-kernel: 675681/tftp-deploy-qm8cj02x/kernel/uImage
240 04:12:49.074991 substitutions:
241 04:12:49.075215 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 04:12:49.075417 - {DTB_ADDR}: 0x01070000
243 04:12:49.075640 - {DTB}: 675681/tftp-deploy-qm8cj02x/dtb/meson-g12b-a311d-libretech-cc.dtb
244 04:12:49.075862 - {INITRD}: 675681/tftp-deploy-qm8cj02x/ramdisk/ramdisk.cpio.gz.uboot
245 04:12:49.076096 - {KERNEL_ADDR}: 0x01080000
246 04:12:49.076302 - {KERNEL}: 675681/tftp-deploy-qm8cj02x/kernel/uImage
247 04:12:49.076505 - {LAVA_MAC}: None
248 04:12:49.076737 - {PRESEED_CONFIG}: None
249 04:12:49.076953 - {PRESEED_LOCAL}: None
250 04:12:49.077172 - {RAMDISK_ADDR}: 0x08000000
251 04:12:49.077377 - {RAMDISK}: 675681/tftp-deploy-qm8cj02x/ramdisk/ramdisk.cpio.gz.uboot
252 04:12:49.077579 - {ROOT_PART}: None
253 04:12:49.077779 - {ROOT}: None
254 04:12:49.077972 - {SERVER_IP}: 192.168.6.2
255 04:12:49.078170 - {TEE_ADDR}: 0x83000000
256 04:12:49.078363 - {TEE}: None
257 04:12:49.078558 Parsed boot commands:
258 04:12:49.078752 - setenv autoload no
259 04:12:49.078948 - setenv initrd_high 0xffffffff
260 04:12:49.079144 - setenv fdt_high 0xffffffff
261 04:12:49.079340 - dhcp
262 04:12:49.079539 - setenv serverip 192.168.6.2
263 04:12:49.079735 - tftpboot 0x01080000 675681/tftp-deploy-qm8cj02x/kernel/uImage
264 04:12:49.079930 - tftpboot 0x08000000 675681/tftp-deploy-qm8cj02x/ramdisk/ramdisk.cpio.gz.uboot
265 04:12:49.080984 - tftpboot 0x01070000 675681/tftp-deploy-qm8cj02x/dtb/meson-g12b-a311d-libretech-cc.dtb
266 04:12:49.081345 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 04:12:49.081693 - bootm 0x01080000 0x08000000 0x01070000
268 04:12:49.082124 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 04:12:49.083248 start: 2.3 connect-device (timeout 00:05:00) [common]
271 04:12:49.083643 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 04:12:49.096078 Setting prompt string to ['lava-test: # ']
273 04:12:49.097299 end: 2.3 connect-device (duration 00:00:00) [common]
274 04:12:49.097836 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 04:12:49.098325 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 04:12:49.098779 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 04:12:49.099619 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 04:12:49.135241 >> OK - accepted request
279 04:12:49.137835 Returned 0 in 0 seconds
280 04:12:49.238883 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 04:12:49.240144 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 04:12:49.240466 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 04:12:49.240739 Setting prompt string to ['Hit any key to stop autoboot']
285 04:12:49.240977 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 04:12:49.241899 Trying 192.168.56.21...
287 04:12:49.242157 Connected to conserv1.
288 04:12:49.242365 Escape character is '^]'.
289 04:12:49.242580
290 04:12:49.242795 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 04:12:49.243014
292 04:13:01.098260 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 04:13:01.098694 bl2_stage_init 0x01
294 04:13:01.098937 bl2_stage_init 0x81
295 04:13:01.103874 hw id: 0x0000 - pwm id 0x01
296 04:13:01.104522 bl2_stage_init 0xc1
297 04:13:01.104984 bl2_stage_init 0x02
298 04:13:01.105439
299 04:13:01.109660 L0:00000000
300 04:13:01.110169 L1:20000703
301 04:13:01.110603 L2:00008067
302 04:13:01.111029 L3:14000000
303 04:13:01.114953 B2:00402000
304 04:13:01.115435 B1:e0f83180
305 04:13:01.115868
306 04:13:01.116358 TE: 58159
307 04:13:01.116792
308 04:13:01.120673 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 04:13:01.121156
310 04:13:01.121589 Board ID = 1
311 04:13:01.126093 Set A53 clk to 24M
312 04:13:01.126582 Set A73 clk to 24M
313 04:13:01.127010 Set clk81 to 24M
314 04:13:01.131751 A53 clk: 1200 MHz
315 04:13:01.132264 A73 clk: 1200 MHz
316 04:13:01.132696 CLK81: 166.6M
317 04:13:01.133121 smccc: 00012ab5
318 04:13:01.137250 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 04:13:01.142822 board id: 1
320 04:13:01.148869 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 04:13:01.159413 fw parse done
322 04:13:01.164881 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 04:13:01.208056 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 04:13:01.218878 PIEI prepare done
325 04:13:01.219369 fastboot data load
326 04:13:01.219804 fastboot data verify
327 04:13:01.224670 verify result: 266
328 04:13:01.230237 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 04:13:01.230757 LPDDR4 probe
330 04:13:01.231185 ddr clk to 1584MHz
331 04:13:01.238222 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 04:13:01.275530
333 04:13:01.276166 dmc_version 0001
334 04:13:01.282219 Check phy result
335 04:13:01.288024 INFO : End of CA training
336 04:13:01.288577 INFO : End of initialization
337 04:13:01.293647 INFO : Training has run successfully!
338 04:13:01.294186 Check phy result
339 04:13:01.299196 INFO : End of initialization
340 04:13:01.299730 INFO : End of read enable training
341 04:13:01.304925 INFO : End of fine write leveling
342 04:13:01.310475 INFO : End of Write leveling coarse delay
343 04:13:01.311035 INFO : Training has run successfully!
344 04:13:01.311502 Check phy result
345 04:13:01.316021 INFO : End of initialization
346 04:13:01.316566 INFO : End of read dq deskew training
347 04:13:01.321645 INFO : End of MPR read delay center optimization
348 04:13:01.327146 INFO : End of write delay center optimization
349 04:13:01.332954 INFO : End of read delay center optimization
350 04:13:01.333504 INFO : End of max read latency training
351 04:13:01.338320 INFO : Training has run successfully!
352 04:13:01.338864 1D training succeed
353 04:13:01.346643 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 04:13:01.396154 Check phy result
355 04:13:01.396614 INFO : End of initialization
356 04:13:01.416966 INFO : End of 2D read delay Voltage center optimization
357 04:13:01.437228 INFO : End of 2D read delay Voltage center optimization
358 04:13:01.489353 INFO : End of 2D write delay Voltage center optimization
359 04:13:01.538752 INFO : End of 2D write delay Voltage center optimization
360 04:13:01.544523 INFO : Training has run successfully!
361 04:13:01.545055
362 04:13:01.545520 channel==0
363 04:13:01.549856 RxClkDly_Margin_A0==69 ps 7
364 04:13:01.550400 TxDqDly_Margin_A0==98 ps 10
365 04:13:01.555357 RxClkDly_Margin_A1==88 ps 9
366 04:13:01.555882 TxDqDly_Margin_A1==98 ps 10
367 04:13:01.556398 TrainedVREFDQ_A0==74
368 04:13:01.561051 TrainedVREFDQ_A1==74
369 04:13:01.561621 VrefDac_Margin_A0==25
370 04:13:01.562122 DeviceVref_Margin_A0==40
371 04:13:01.566702 VrefDac_Margin_A1==25
372 04:13:01.567453 DeviceVref_Margin_A1==40
373 04:13:01.567967
374 04:13:01.568503
375 04:13:01.572290 channel==1
376 04:13:01.572825 RxClkDly_Margin_A0==98 ps 10
377 04:13:01.573281 TxDqDly_Margin_A0==88 ps 9
378 04:13:01.577838 RxClkDly_Margin_A1==98 ps 10
379 04:13:01.578365 TxDqDly_Margin_A1==88 ps 9
380 04:13:01.583426 TrainedVREFDQ_A0==76
381 04:13:01.583951 TrainedVREFDQ_A1==77
382 04:13:01.584451 VrefDac_Margin_A0==23
383 04:13:01.589080 DeviceVref_Margin_A0==38
384 04:13:01.589626 VrefDac_Margin_A1==23
385 04:13:01.594592 DeviceVref_Margin_A1==37
386 04:13:01.595112
387 04:13:01.595576 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 04:13:01.596071
389 04:13:01.628123 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 04:13:01.628757 2D training succeed
391 04:13:01.633680 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 04:13:01.639175 auto size-- 65535DDR cs0 size: 2048MB
393 04:13:01.639693 DDR cs1 size: 2048MB
394 04:13:01.644921 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 04:13:01.645440 cs0 DataBus test pass
396 04:13:01.650382 cs1 DataBus test pass
397 04:13:01.650896 cs0 AddrBus test pass
398 04:13:01.651345 cs1 AddrBus test pass
399 04:13:01.651783
400 04:13:01.656018 100bdlr_step_size ps== 420
401 04:13:01.656550 result report
402 04:13:01.661683 boot times 0Enable ddr reg access
403 04:13:01.667044 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 04:13:01.680552 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 04:13:02.254153 0.0;M3 CHK:0;cm4_sp_mode 0
406 04:13:02.254567 MVN_1=0x00000000
407 04:13:02.259593 MVN_2=0x00000000
408 04:13:02.265383 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 04:13:02.265730 OPS=0x10
410 04:13:02.265954 ring efuse init
411 04:13:02.266163 chipver efuse init
412 04:13:02.271039 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 04:13:02.276585 [0.018960 Inits done]
414 04:13:02.277076 secure task start!
415 04:13:02.277499 high task start!
416 04:13:02.281284 low task start!
417 04:13:02.281772 run into bl31
418 04:13:02.287846 NOTICE: BL31: v1.3(release):4fc40b1
419 04:13:02.294664 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 04:13:02.295035 NOTICE: BL31: G12A normal boot!
421 04:13:02.321533 NOTICE: BL31: BL33 decompress pass
422 04:13:02.327274 ERROR: Error initializing runtime service opteed_fast
423 04:13:03.560167
424 04:13:03.560698
425 04:13:03.568483 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 04:13:03.568912
427 04:13:03.569236 Model: Libre Computer AML-A311D-CC Alta
428 04:13:03.777112 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 04:13:03.799607 DRAM: 2 GiB (effective 3.8 GiB)
430 04:13:03.943323 Core: 408 devices, 31 uclasses, devicetree: separate
431 04:13:03.949265 WDT: Not starting watchdog@f0d0
432 04:13:03.981612 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 04:13:03.993935 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 04:13:03.998922 ** Bad device specification mmc 0 **
435 04:13:04.009368 Card did not respond to voltage select! : -110
436 04:13:04.016937 ** Bad device specification mmc 0 **
437 04:13:04.017279 Couldn't find partition mmc 0
438 04:13:04.025178 Card did not respond to voltage select! : -110
439 04:13:04.030802 ** Bad device specification mmc 0 **
440 04:13:04.031174 Couldn't find partition mmc 0
441 04:13:04.035772 Error: could not access storage.
442 04:13:05.298724 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 04:13:05.299382 bl2_stage_init 0x81
444 04:13:05.304280 hw id: 0x0000 - pwm id 0x01
445 04:13:05.304588 bl2_stage_init 0xc1
446 04:13:05.304819 bl2_stage_init 0x02
447 04:13:05.305043
448 04:13:05.309790 L0:00000000
449 04:13:05.310136 L1:20000703
450 04:13:05.310351 L2:00008067
451 04:13:05.310559 L3:14000000
452 04:13:05.310764 B2:00402000
453 04:13:05.312545 B1:e0f83180
454 04:13:05.312841
455 04:13:05.313058 TE: 58150
456 04:13:05.313284
457 04:13:05.323748 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 04:13:05.324228
459 04:13:05.324697 Board ID = 1
460 04:13:05.325142 Set A53 clk to 24M
461 04:13:05.325576 Set A73 clk to 24M
462 04:13:05.329424 Set clk81 to 24M
463 04:13:05.329931 A53 clk: 1200 MHz
464 04:13:05.330383 A73 clk: 1200 MHz
465 04:13:05.335004 CLK81: 166.6M
466 04:13:05.335504 smccc: 00012aab
467 04:13:05.340610 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 04:13:05.341146 board id: 1
469 04:13:05.349218 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 04:13:05.359855 fw parse done
471 04:13:05.365807 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 04:13:05.408448 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 04:13:05.419346 PIEI prepare done
474 04:13:05.419841 fastboot data load
475 04:13:05.420323 fastboot data verify
476 04:13:05.425086 verify result: 266
477 04:13:05.430688 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 04:13:05.431213 LPDDR4 probe
479 04:13:05.431667 ddr clk to 1584MHz
480 04:13:05.438668 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 04:13:05.475881
482 04:13:05.476448 dmc_version 0001
483 04:13:05.482576 Check phy result
484 04:13:05.488475 INFO : End of CA training
485 04:13:05.488978 INFO : End of initialization
486 04:13:05.494051 INFO : Training has run successfully!
487 04:13:05.494560 Check phy result
488 04:13:05.499676 INFO : End of initialization
489 04:13:05.500222 INFO : End of read enable training
490 04:13:05.505242 INFO : End of fine write leveling
491 04:13:05.510877 INFO : End of Write leveling coarse delay
492 04:13:05.511412 INFO : Training has run successfully!
493 04:13:05.511868 Check phy result
494 04:13:05.516473 INFO : End of initialization
495 04:13:05.516978 INFO : End of read dq deskew training
496 04:13:05.522049 INFO : End of MPR read delay center optimization
497 04:13:05.527623 INFO : End of write delay center optimization
498 04:13:05.533235 INFO : End of read delay center optimization
499 04:13:05.533741 INFO : End of max read latency training
500 04:13:05.538840 INFO : Training has run successfully!
501 04:13:05.539338 1D training succeed
502 04:13:05.547972 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 04:13:05.595613 Check phy result
504 04:13:05.596183 INFO : End of initialization
505 04:13:05.618135 INFO : End of 2D read delay Voltage center optimization
506 04:13:05.638227 INFO : End of 2D read delay Voltage center optimization
507 04:13:05.690090 INFO : End of 2D write delay Voltage center optimization
508 04:13:05.739520 INFO : End of 2D write delay Voltage center optimization
509 04:13:05.744927 INFO : Training has run successfully!
510 04:13:05.745445
511 04:13:05.745902 channel==0
512 04:13:05.750567 RxClkDly_Margin_A0==88 ps 9
513 04:13:05.751076 TxDqDly_Margin_A0==98 ps 10
514 04:13:05.756118 RxClkDly_Margin_A1==78 ps 8
515 04:13:05.756623 TxDqDly_Margin_A1==98 ps 10
516 04:13:05.757082 TrainedVREFDQ_A0==74
517 04:13:05.761757 TrainedVREFDQ_A1==74
518 04:13:05.762281 VrefDac_Margin_A0==25
519 04:13:05.762732 DeviceVref_Margin_A0==40
520 04:13:05.767483 VrefDac_Margin_A1==26
521 04:13:05.768003 DeviceVref_Margin_A1==40
522 04:13:05.768457
523 04:13:05.768900
524 04:13:05.772931 channel==1
525 04:13:05.773445 RxClkDly_Margin_A0==98 ps 10
526 04:13:05.773893 TxDqDly_Margin_A0==98 ps 10
527 04:13:05.778518 RxClkDly_Margin_A1==88 ps 9
528 04:13:05.779024 TxDqDly_Margin_A1==88 ps 9
529 04:13:05.784128 TrainedVREFDQ_A0==77
530 04:13:05.784639 TrainedVREFDQ_A1==77
531 04:13:05.785086 VrefDac_Margin_A0==23
532 04:13:05.789719 DeviceVref_Margin_A0==37
533 04:13:05.790219 VrefDac_Margin_A1==24
534 04:13:05.795349 DeviceVref_Margin_A1==37
535 04:13:05.795847
536 04:13:05.796335 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 04:13:05.796776
538 04:13:05.828875 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
539 04:13:05.829466 2D training succeed
540 04:13:05.834537 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 04:13:05.840160 auto size-- 65535DDR cs0 size: 2048MB
542 04:13:05.840668 DDR cs1 size: 2048MB
543 04:13:05.845736 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 04:13:05.846254 cs0 DataBus test pass
545 04:13:05.851330 cs1 DataBus test pass
546 04:13:05.851831 cs0 AddrBus test pass
547 04:13:05.852326 cs1 AddrBus test pass
548 04:13:05.852770
549 04:13:05.856942 100bdlr_step_size ps== 420
550 04:13:05.857456 result report
551 04:13:05.862550 boot times 0Enable ddr reg access
552 04:13:05.867886 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 04:13:05.881340 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 04:13:06.453221 0.0;M3 CHK:0;cm4_sp_mode 0
555 04:13:06.453663 MVN_1=0x00000000
556 04:13:06.458721 MVN_2=0x00000000
557 04:13:06.464581 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 04:13:06.464913 OPS=0x10
559 04:13:06.465131 ring efuse init
560 04:13:06.465339 chipver efuse init
561 04:13:06.472696 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 04:13:06.473033 [0.018961 Inits done]
563 04:13:06.480278 secure task start!
564 04:13:06.480616 high task start!
565 04:13:06.480832 low task start!
566 04:13:06.481031 run into bl31
567 04:13:06.486913 NOTICE: BL31: v1.3(release):4fc40b1
568 04:13:06.494991 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 04:13:06.495326 NOTICE: BL31: G12A normal boot!
570 04:13:06.520201 NOTICE: BL31: BL33 decompress pass
571 04:13:06.524950 ERROR: Error initializing runtime service opteed_fast
572 04:13:07.758843
573 04:13:07.759285
574 04:13:07.768259 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 04:13:07.768632
576 04:13:07.768844 Model: Libre Computer AML-A311D-CC Alta
577 04:13:07.975432 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 04:13:07.999099 DRAM: 2 GiB (effective 3.8 GiB)
579 04:13:08.142170 Core: 408 devices, 31 uclasses, devicetree: separate
580 04:13:08.148075 WDT: Not starting watchdog@f0d0
581 04:13:08.180253 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 04:13:08.192589 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 04:13:08.197735 ** Bad device specification mmc 0 **
584 04:13:08.208194 Card did not respond to voltage select! : -110
585 04:13:08.214898 ** Bad device specification mmc 0 **
586 04:13:08.215415 Couldn't find partition mmc 0
587 04:13:08.224067 Card did not respond to voltage select! : -110
588 04:13:08.229546 ** Bad device specification mmc 0 **
589 04:13:08.230028 Couldn't find partition mmc 0
590 04:13:08.234630 Error: could not access storage.
591 04:13:08.577841 Net: eth0: ethernet@ff3f0000
592 04:13:08.578464 starting USB...
593 04:13:08.829837 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 04:13:08.830260 Starting the controller
595 04:13:08.836761 USB XHCI 1.10
596 04:13:10.547440 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 04:13:10.547913 bl2_stage_init 0x01
598 04:13:10.548183 bl2_stage_init 0x81
599 04:13:10.552892 hw id: 0x0000 - pwm id 0x01
600 04:13:10.553472 bl2_stage_init 0xc1
601 04:13:10.553970 bl2_stage_init 0x02
602 04:13:10.554455
603 04:13:10.558629 L0:00000000
604 04:13:10.559132 L1:20000703
605 04:13:10.559570 L2:00008067
606 04:13:10.560063 L3:14000000
607 04:13:10.561542 B2:00402000
608 04:13:10.562022 B1:e0f83180
609 04:13:10.562467
610 04:13:10.562774 TE: 58167
611 04:13:10.562986
612 04:13:10.572749 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 04:13:10.573278
614 04:13:10.573736 Board ID = 1
615 04:13:10.574177 Set A53 clk to 24M
616 04:13:10.574615 Set A73 clk to 24M
617 04:13:10.578246 Set clk81 to 24M
618 04:13:10.578783 A53 clk: 1200 MHz
619 04:13:10.579231 A73 clk: 1200 MHz
620 04:13:10.584020 CLK81: 166.6M
621 04:13:10.584515 smccc: 00012abe
622 04:13:10.589549 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 04:13:10.590041 board id: 1
624 04:13:10.598076 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 04:13:10.608713 fw parse done
626 04:13:10.614664 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 04:13:10.657251 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 04:13:10.668112 PIEI prepare done
629 04:13:10.668682 fastboot data load
630 04:13:10.669164 fastboot data verify
631 04:13:10.673698 verify result: 266
632 04:13:10.679621 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 04:13:10.679902 LPDDR4 probe
634 04:13:10.680145 ddr clk to 1584MHz
635 04:13:10.686733 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 04:13:10.723754
637 04:13:10.724464 dmc_version 0001
638 04:13:10.730338 Check phy result
639 04:13:10.737230 INFO : End of CA training
640 04:13:10.737801 INFO : End of initialization
641 04:13:10.742676 INFO : Training has run successfully!
642 04:13:10.742988 Check phy result
643 04:13:10.748336 INFO : End of initialization
644 04:13:10.748657 INFO : End of read enable training
645 04:13:10.753813 INFO : End of fine write leveling
646 04:13:10.759787 INFO : End of Write leveling coarse delay
647 04:13:10.762627 INFO : Training has run successfully!
648 04:13:10.762896 Check phy result
649 04:13:10.765356 INFO : End of initialization
650 04:13:10.765668 INFO : End of read dq deskew training
651 04:13:10.770772 INFO : End of MPR read delay center optimization
652 04:13:10.779731 INFO : End of write delay center optimization
653 04:13:10.782083 INFO : End of read delay center optimization
654 04:13:10.782607 INFO : End of max read latency training
655 04:13:10.787617 INFO : Training has run successfully!
656 04:13:10.788166 1D training succeed
657 04:13:10.796192 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 04:13:10.844254 Check phy result
659 04:13:10.844657 INFO : End of initialization
660 04:13:10.865811 INFO : End of 2D read delay Voltage center optimization
661 04:13:10.886009 INFO : End of 2D read delay Voltage center optimization
662 04:13:10.937821 INFO : End of 2D write delay Voltage center optimization
663 04:13:10.987231 INFO : End of 2D write delay Voltage center optimization
664 04:13:10.992767 INFO : Training has run successfully!
665 04:13:10.995301
666 04:13:10.995773 channel==0
667 04:13:10.998941 RxClkDly_Margin_A0==69 ps 7
668 04:13:10.999486 TxDqDly_Margin_A0==98 ps 10
669 04:13:11.003938 RxClkDly_Margin_A1==88 ps 9
670 04:13:11.004513 TxDqDly_Margin_A1==98 ps 10
671 04:13:11.004958 TrainedVREFDQ_A0==74
672 04:13:11.009630 TrainedVREFDQ_A1==74
673 04:13:11.010192 VrefDac_Margin_A0==25
674 04:13:11.010632 DeviceVref_Margin_A0==40
675 04:13:11.015207 VrefDac_Margin_A1==25
676 04:13:11.015769 DeviceVref_Margin_A1==40
677 04:13:11.016243
678 04:13:11.016655
679 04:13:11.021115 channel==1
680 04:13:11.021678 RxClkDly_Margin_A0==88 ps 9
681 04:13:11.022135 TxDqDly_Margin_A0==88 ps 9
682 04:13:11.026367 RxClkDly_Margin_A1==98 ps 10
683 04:13:11.026743 TxDqDly_Margin_A1==98 ps 10
684 04:13:11.032038 TrainedVREFDQ_A0==76
685 04:13:11.032455 TrainedVREFDQ_A1==77
686 04:13:11.032700 VrefDac_Margin_A0==23
687 04:13:11.037611 DeviceVref_Margin_A0==38
688 04:13:11.037975 VrefDac_Margin_A1==23
689 04:13:11.043154 DeviceVref_Margin_A1==37
690 04:13:11.043491
691 04:13:11.043720 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 04:13:11.043942
693 04:13:11.076639 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
694 04:13:11.077050 2D training succeed
695 04:13:11.082291 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 04:13:11.087836 auto size-- 65535DDR cs0 size: 2048MB
697 04:13:11.088205 DDR cs1 size: 2048MB
698 04:13:11.093479 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 04:13:11.093815 cs0 DataBus test pass
700 04:13:11.099169 cs1 DataBus test pass
701 04:13:11.099522 cs0 AddrBus test pass
702 04:13:11.099755 cs1 AddrBus test pass
703 04:13:11.099976
704 04:13:11.104661 100bdlr_step_size ps== 420
705 04:13:11.105004 result report
706 04:13:11.110292 boot times 0Enable ddr reg access
707 04:13:11.115632 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 04:13:11.129266 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 04:13:11.701477 0.0;M3 CHK:0;cm4_sp_mode 0
710 04:13:11.701910 MVN_1=0x00000000
711 04:13:11.706639 MVN_2=0x00000000
712 04:13:11.712349 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 04:13:11.712694 OPS=0x10
714 04:13:11.712920 ring efuse init
715 04:13:11.713129 chipver efuse init
716 04:13:11.717957 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 04:13:11.723685 [0.018961 Inits done]
718 04:13:11.724059 secure task start!
719 04:13:11.724271 high task start!
720 04:13:11.728302 low task start!
721 04:13:11.728665 run into bl31
722 04:13:11.735056 NOTICE: BL31: v1.3(release):4fc40b1
723 04:13:11.742761 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 04:13:11.743148 NOTICE: BL31: G12A normal boot!
725 04:13:11.768037 NOTICE: BL31: BL33 decompress pass
726 04:13:11.773611 ERROR: Error initializing runtime service opteed_fast
727 04:13:13.006574
728 04:13:13.006987
729 04:13:13.015058 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 04:13:13.015496
731 04:13:13.015806 Model: Libre Computer AML-A311D-CC Alta
732 04:13:13.223494 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 04:13:13.246781 DRAM: 2 GiB (effective 3.8 GiB)
734 04:13:13.391597 Core: 408 devices, 31 uclasses, devicetree: separate
735 04:13:13.395698 WDT: Not starting watchdog@f0d0
736 04:13:13.427959 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 04:13:13.440503 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 04:13:13.445142 ** Bad device specification mmc 0 **
739 04:13:13.455703 Card did not respond to voltage select! : -110
740 04:13:13.463382 ** Bad device specification mmc 0 **
741 04:13:13.463871 Couldn't find partition mmc 0
742 04:13:13.471731 Card did not respond to voltage select! : -110
743 04:13:13.477222 ** Bad device specification mmc 0 **
744 04:13:13.477726 Couldn't find partition mmc 0
745 04:13:13.482335 Error: could not access storage.
746 04:13:13.824743 Net: eth0: ethernet@ff3f0000
747 04:13:13.825361 starting USB...
748 04:13:14.076493 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 04:13:14.076975 Starting the controller
750 04:13:14.083521 USB XHCI 1.10
751 04:13:16.267667 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 04:13:16.268390 bl2_stage_init 0x01
753 04:13:16.268865 bl2_stage_init 0x81
754 04:13:16.273103 hw id: 0x0000 - pwm id 0x01
755 04:13:16.273632 bl2_stage_init 0xc1
756 04:13:16.274104 bl2_stage_init 0x02
757 04:13:16.274573
758 04:13:16.278742 L0:00000000
759 04:13:16.279282 L1:20000703
760 04:13:16.279739 L2:00008067
761 04:13:16.280222 L3:14000000
762 04:13:16.281487 B2:00402000
763 04:13:16.282046 B1:e0f83180
764 04:13:16.282530
765 04:13:16.283026 TE: 58159
766 04:13:16.283505
767 04:13:16.292485 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 04:13:16.293040
769 04:13:16.293502 Board ID = 1
770 04:13:16.293957 Set A53 clk to 24M
771 04:13:16.294405 Set A73 clk to 24M
772 04:13:16.298197 Set clk81 to 24M
773 04:13:16.298726 A53 clk: 1200 MHz
774 04:13:16.299178 A73 clk: 1200 MHz
775 04:13:16.301705 CLK81: 166.6M
776 04:13:16.302205 smccc: 00012ab5
777 04:13:16.307310 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 04:13:16.312892 board id: 1
779 04:13:16.317218 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 04:13:16.328740 fw parse done
781 04:13:16.334385 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 04:13:16.376464 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 04:13:16.388231 PIEI prepare done
784 04:13:16.388782 fastboot data load
785 04:13:16.389242 fastboot data verify
786 04:13:16.393866 verify result: 266
787 04:13:16.399309 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 04:13:16.399801 LPDDR4 probe
789 04:13:16.400293 ddr clk to 1584MHz
790 04:13:16.407247 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 04:13:16.443924
792 04:13:16.444559 dmc_version 0001
793 04:13:16.450768 Check phy result
794 04:13:16.457261 INFO : End of CA training
795 04:13:16.457812 INFO : End of initialization
796 04:13:16.462808 INFO : Training has run successfully!
797 04:13:16.463300 Check phy result
798 04:13:16.468360 INFO : End of initialization
799 04:13:16.468850 INFO : End of read enable training
800 04:13:16.473983 INFO : End of fine write leveling
801 04:13:16.479634 INFO : End of Write leveling coarse delay
802 04:13:16.480158 INFO : Training has run successfully!
803 04:13:16.480609 Check phy result
804 04:13:16.485136 INFO : End of initialization
805 04:13:16.485620 INFO : End of read dq deskew training
806 04:13:16.490888 INFO : End of MPR read delay center optimization
807 04:13:16.496363 INFO : End of write delay center optimization
808 04:13:16.501991 INFO : End of read delay center optimization
809 04:13:16.502470 INFO : End of max read latency training
810 04:13:16.507619 INFO : Training has run successfully!
811 04:13:16.508151 1D training succeed
812 04:13:16.516291 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 04:13:16.564538 Check phy result
814 04:13:16.565157 INFO : End of initialization
815 04:13:16.586338 INFO : End of 2D read delay Voltage center optimization
816 04:13:16.606417 INFO : End of 2D read delay Voltage center optimization
817 04:13:16.659025 INFO : End of 2D write delay Voltage center optimization
818 04:13:16.708663 INFO : End of 2D write delay Voltage center optimization
819 04:13:16.714268 INFO : Training has run successfully!
820 04:13:16.714806
821 04:13:16.715266 channel==0
822 04:13:16.719786 RxClkDly_Margin_A0==88 ps 9
823 04:13:16.720355 TxDqDly_Margin_A0==98 ps 10
824 04:13:16.723190 RxClkDly_Margin_A1==88 ps 9
825 04:13:16.723657 TxDqDly_Margin_A1==88 ps 9
826 04:13:16.728644 TrainedVREFDQ_A0==74
827 04:13:16.729115 TrainedVREFDQ_A1==74
828 04:13:16.729546 VrefDac_Margin_A0==25
829 04:13:16.734274 DeviceVref_Margin_A0==40
830 04:13:16.734737 VrefDac_Margin_A1==25
831 04:13:16.739905 DeviceVref_Margin_A1==40
832 04:13:16.740396
833 04:13:16.740828
834 04:13:16.741250 channel==1
835 04:13:16.741673 RxClkDly_Margin_A0==98 ps 10
836 04:13:16.743379 TxDqDly_Margin_A0==98 ps 10
837 04:13:16.748978 RxClkDly_Margin_A1==88 ps 9
838 04:13:16.749439 TxDqDly_Margin_A1==88 ps 9
839 04:13:16.749868 TrainedVREFDQ_A0==77
840 04:13:16.755586 TrainedVREFDQ_A1==77
841 04:13:16.756142 VrefDac_Margin_A0==22
842 04:13:16.760134 DeviceVref_Margin_A0==37
843 04:13:16.760622 VrefDac_Margin_A1==24
844 04:13:16.761051 DeviceVref_Margin_A1==37
845 04:13:16.761474
846 04:13:16.765659 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 04:13:16.766122
848 04:13:16.799269 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
849 04:13:16.799796 2D training succeed
850 04:13:16.804940 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 04:13:16.810488 auto size-- 65535DDR cs0 size: 2048MB
852 04:13:16.810958 DDR cs1 size: 2048MB
853 04:13:16.816090 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 04:13:16.816555 cs0 DataBus test pass
855 04:13:16.816968 cs1 DataBus test pass
856 04:13:16.821679 cs0 AddrBus test pass
857 04:13:16.822175 cs1 AddrBus test pass
858 04:13:16.822626
859 04:13:16.827263 100bdlr_step_size ps== 420
860 04:13:16.827779 result report
861 04:13:16.828272 boot times 0Enable ddr reg access
862 04:13:16.836925 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 04:13:16.849676 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 04:13:17.424100 0.0;M3 CHK:0;cm4_sp_mode 0
865 04:13:17.424771 MVN_1=0x00000000
866 04:13:17.429728 MVN_2=0x00000000
867 04:13:17.435298 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 04:13:17.435704 OPS=0x10
869 04:13:17.436075 ring efuse init
870 04:13:17.436411 chipver efuse init
871 04:13:17.440941 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 04:13:17.446557 [0.018960 Inits done]
873 04:13:17.446964 secure task start!
874 04:13:17.447325 high task start!
875 04:13:17.450493 low task start!
876 04:13:17.450806 run into bl31
877 04:13:17.457847 NOTICE: BL31: v1.3(release):4fc40b1
878 04:13:17.465421 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 04:13:17.465750 NOTICE: BL31: G12A normal boot!
880 04:13:17.490921 NOTICE: BL31: BL33 decompress pass
881 04:13:17.496417 ERROR: Error initializing runtime service opteed_fast
882 04:13:18.729508
883 04:13:18.730116
884 04:13:18.737600 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 04:13:18.738107
886 04:13:18.738535 Model: Libre Computer AML-A311D-CC Alta
887 04:13:18.945767 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 04:13:18.969395 DRAM: 2 GiB (effective 3.8 GiB)
889 04:13:19.112763 Core: 408 devices, 31 uclasses, devicetree: separate
890 04:13:19.117787 WDT: Not starting watchdog@f0d0
891 04:13:19.150929 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 04:13:19.163351 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 04:13:19.168171 ** Bad device specification mmc 0 **
894 04:13:19.178674 Card did not respond to voltage select! : -110
895 04:13:19.185549 ** Bad device specification mmc 0 **
896 04:13:19.186035 Couldn't find partition mmc 0
897 04:13:19.194656 Card did not respond to voltage select! : -110
898 04:13:19.200174 ** Bad device specification mmc 0 **
899 04:13:19.200624 Couldn't find partition mmc 0
900 04:13:19.204622 Error: could not access storage.
901 04:13:19.547727 Net: eth0: ethernet@ff3f0000
902 04:13:19.548379 starting USB...
903 04:13:19.799478 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 04:13:19.800095 Starting the controller
905 04:13:19.806502 USB XHCI 1.10
906 04:13:21.360395 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 04:13:21.368691 scanning usb for storage devices... 0 Storage Device(s) found
909 04:13:21.420354 Hit any key to stop autoboot: 1
910 04:13:21.421468 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 04:13:21.422122 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 04:13:21.422650 Setting prompt string to ['=>']
913 04:13:21.423182 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 04:13:21.436238 0
915 04:13:21.437241 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 04:13:21.437803 Sending with 10 millisecond of delay
918 04:13:22.573374 => setenv autoload no
919 04:13:22.584151 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
920 04:13:22.589052 setenv autoload no
921 04:13:22.589788 Sending with 10 millisecond of delay
923 04:13:24.386270 => setenv initrd_high 0xffffffff
924 04:13:24.397012 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 04:13:24.397819 setenv initrd_high 0xffffffff
926 04:13:24.398517 Sending with 10 millisecond of delay
928 04:13:26.014296 => setenv fdt_high 0xffffffff
929 04:13:26.025157 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 04:13:26.025969 setenv fdt_high 0xffffffff
931 04:13:26.026673 Sending with 10 millisecond of delay
933 04:13:26.318463 => dhcp
934 04:13:26.329075 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 04:13:26.330988 dhcp
936 04:13:26.332043 Speed: 1000, full duplex
937 04:13:26.332328 BOOTP broadcast 1
938 04:13:26.576009 BOOTP broadcast 2
939 04:13:26.612063 DHCP client bound to address 192.168.6.33 (283 ms)
940 04:13:26.612754 Sending with 10 millisecond of delay
942 04:13:28.289597 => setenv serverip 192.168.6.2
943 04:13:28.300398 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 04:13:28.300960 setenv serverip 192.168.6.2
945 04:13:28.301515 Sending with 10 millisecond of delay
947 04:13:32.028670 => tftpboot 0x01080000 675681/tftp-deploy-qm8cj02x/kernel/uImage
948 04:13:32.039744 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
949 04:13:32.041075 tftpboot 0x01080000 675681/tftp-deploy-qm8cj02x/kernel/uImage
950 04:13:32.041719 Speed: 1000, full duplex
951 04:13:32.042279 Using ethernet@ff3f0000 device
952 04:13:32.043043 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
953 04:13:32.047899 Filename '675681/tftp-deploy-qm8cj02x/kernel/uImage'.
954 04:13:32.051611 Load address: 0x1080000
955 04:13:35.109548 Loading: *################################################## 43.2 MiB
956 04:13:35.110126 14.1 MiB/s
957 04:13:35.110534 done
958 04:13:35.112953 Bytes transferred = 45308480 (2b35a40 hex)
959 04:13:35.113693 Sending with 10 millisecond of delay
961 04:13:39.806101 => tftpboot 0x08000000 675681/tftp-deploy-qm8cj02x/ramdisk/ramdisk.cpio.gz.uboot
962 04:13:39.816624 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
963 04:13:39.817129 tftpboot 0x08000000 675681/tftp-deploy-qm8cj02x/ramdisk/ramdisk.cpio.gz.uboot
964 04:13:39.817383 Speed: 1000, full duplex
965 04:13:39.817613 Using ethernet@ff3f0000 device
966 04:13:39.819095 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
967 04:13:39.830194 Filename '675681/tftp-deploy-qm8cj02x/ramdisk/ramdisk.cpio.gz.uboot'.
968 04:13:39.830508 Load address: 0x8000000
969 04:13:46.659908 Loading: *#########T ######################################## UDP wrong checksum 00000005 0000e7e8
970 04:13:51.662212 T UDP wrong checksum 00000005 0000e7e8
971 04:14:01.664383 T T UDP wrong checksum 00000005 0000e7e8
972 04:14:08.157064 T UDP wrong checksum 000000ff 00009063
973 04:14:08.171071 UDP wrong checksum 000000ff 00002556
974 04:14:10.114419 UDP wrong checksum 000000ff 000064b8
975 04:14:10.122318 UDP wrong checksum 000000ff 0000fbaa
976 04:14:11.947771 T UDP wrong checksum 000000ff 0000cc47
977 04:14:11.965439 UDP wrong checksum 000000ff 0000663a
978 04:14:21.668344 T T UDP wrong checksum 00000005 0000e7e8
979 04:14:24.625927 UDP wrong checksum 000000ff 0000cf7b
980 04:14:24.632551 UDP wrong checksum 000000ff 0000636e
981 04:14:31.522802 T UDP wrong checksum 000000ff 000012f1
982 04:14:31.622911 UDP wrong checksum 000000ff 00009be3
983 04:14:36.672559 T
984 04:14:36.673178 Retry count exceeded; starting again
986 04:14:36.674538 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
989 04:14:36.676317 end: 2.4 uboot-commands (duration 00:01:48) [common]
991 04:14:36.677614 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
993 04:14:36.678603 end: 2 uboot-action (duration 00:01:48) [common]
995 04:14:36.680087 Cleaning after the job
996 04:14:36.680637 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/ramdisk
997 04:14:36.681889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/kernel
998 04:14:36.725910 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/dtb
999 04:14:36.726832 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/675681/tftp-deploy-qm8cj02x/modules
1000 04:14:36.740576 start: 4.1 power-off (timeout 00:00:30) [common]
1001 04:14:36.741229 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1002 04:14:36.772347 >> OK - accepted request
1003 04:14:36.774110 Returned 0 in 0 seconds
1004 04:14:36.874848 end: 4.1 power-off (duration 00:00:00) [common]
1006 04:14:36.875827 start: 4.2 read-feedback (timeout 00:10:00) [common]
1007 04:14:36.876532 Listened to connection for namespace 'common' for up to 1s
1008 04:14:37.876976 Finalising connection for namespace 'common'
1009 04:14:37.877709 Disconnecting from shell: Finalise
1010 04:14:37.878207 =>
1011 04:14:37.979179 end: 4.2 read-feedback (duration 00:00:01) [common]
1012 04:14:37.979880 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/675681
1013 04:14:38.247607 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/675681
1014 04:14:38.248234 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.