Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 21:19:28.474629 lava-dispatcher, installed at version: 2024.01
2 21:19:28.474907 start: 0 validate
3 21:19:28.475055 Start time: 2024-08-30 21:19:28.475046+00:00 (UTC)
4 21:19:28.475218 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 21:19:29.248600 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 21:19:29.388867 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 21:19:29.529893 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 21:19:29.671771 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 21:19:29.821702 validate duration: 1.35
11 21:19:29.822623 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 21:19:29.822868 start: 1.1 download-retry (timeout 00:10:00) [common]
13 21:19:29.823152 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 21:19:29.823636 Not decompressing ramdisk as can be used compressed.
15 21:19:29.823915 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 21:19:29.824084 saving as /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/ramdisk/initrd.cpio.gz
17 21:19:29.824239 total size: 4775763 (4 MB)
18 21:19:30.104100 progress 0 % (0 MB)
19 21:19:30.556323 progress 5 % (0 MB)
20 21:19:30.974769 progress 10 % (0 MB)
21 21:19:31.279627 progress 15 % (0 MB)
22 21:19:31.558005 progress 20 % (0 MB)
23 21:19:31.833604 progress 25 % (1 MB)
24 21:19:31.978913 progress 30 % (1 MB)
25 21:19:32.252366 progress 35 % (1 MB)
26 21:19:32.394947 progress 40 % (1 MB)
27 21:19:32.663136 progress 45 % (2 MB)
28 21:19:32.809265 progress 50 % (2 MB)
29 21:19:32.975567 progress 55 % (2 MB)
30 21:19:33.116147 progress 60 % (2 MB)
31 21:19:33.255075 progress 65 % (2 MB)
32 21:19:33.396768 progress 70 % (3 MB)
33 21:19:33.533022 progress 75 % (3 MB)
34 21:19:33.684089 progress 80 % (3 MB)
35 21:19:33.821382 progress 85 % (3 MB)
36 21:19:33.944626 progress 90 % (4 MB)
37 21:19:34.075523 progress 95 % (4 MB)
38 21:19:34.105854 progress 100 % (4 MB)
39 21:19:34.106367 4 MB downloaded in 4.28 s (1.06 MB/s)
40 21:19:34.106689 end: 1.1.1 http-download (duration 00:00:04) [common]
42 21:19:34.107169 end: 1.1 download-retry (duration 00:00:04) [common]
43 21:19:34.107334 start: 1.2 download-retry (timeout 00:09:56) [common]
44 21:19:34.107486 start: 1.2.1 http-download (timeout 00:09:56) [common]
45 21:19:34.107763 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 21:19:34.107896 saving as /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/kernel/zImage
47 21:19:34.108045 total size: 11354624 (10 MB)
48 21:19:34.108192 No compression specified
49 21:19:34.249898 progress 0 % (0 MB)
50 21:19:34.397435 progress 5 % (0 MB)
51 21:19:34.672091 progress 10 % (1 MB)
52 21:19:34.820012 progress 15 % (1 MB)
53 21:19:35.105278 progress 20 % (2 MB)
54 21:19:35.255064 progress 25 % (2 MB)
55 21:19:35.405260 progress 30 % (3 MB)
56 21:19:35.558047 progress 35 % (3 MB)
57 21:19:35.703236 progress 40 % (4 MB)
58 21:19:35.963981 progress 45 % (4 MB)
59 21:19:36.103066 progress 50 % (5 MB)
60 21:19:36.121627 progress 55 % (5 MB)
61 21:19:36.257750 progress 60 % (6 MB)
62 21:19:36.396695 progress 65 % (7 MB)
63 21:19:36.530472 progress 70 % (7 MB)
64 21:19:36.666248 progress 75 % (8 MB)
65 21:19:36.800667 progress 80 % (8 MB)
66 21:19:36.815127 progress 85 % (9 MB)
67 21:19:36.948535 progress 90 % (9 MB)
68 21:19:37.083684 progress 95 % (10 MB)
69 21:19:37.099460 progress 100 % (10 MB)
70 21:19:37.099977 10 MB downloaded in 2.99 s (3.62 MB/s)
71 21:19:37.100278 end: 1.2.1 http-download (duration 00:00:03) [common]
73 21:19:37.100736 end: 1.2 download-retry (duration 00:00:03) [common]
74 21:19:37.100904 start: 1.3 download-retry (timeout 00:09:53) [common]
75 21:19:37.101060 start: 1.3.1 http-download (timeout 00:09:53) [common]
76 21:19:37.101326 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 21:19:37.101458 saving as /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/dtb/am335x-boneblack.dtb
78 21:19:37.101573 total size: 70308 (0 MB)
79 21:19:37.101720 No compression specified
80 21:19:37.248597 progress 46 % (0 MB)
81 21:19:37.249334 progress 93 % (0 MB)
82 21:19:37.249894 progress 100 % (0 MB)
83 21:19:37.250132 0 MB downloaded in 0.15 s (0.45 MB/s)
84 21:19:37.250431 end: 1.3.1 http-download (duration 00:00:00) [common]
86 21:19:37.250900 end: 1.3 download-retry (duration 00:00:00) [common]
87 21:19:37.251058 start: 1.4 download-retry (timeout 00:09:53) [common]
88 21:19:37.251216 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 21:19:37.251487 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 21:19:37.251617 saving as /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/nfsrootfs/full.rootfs.tar
91 21:19:37.251731 total size: 117747780 (112 MB)
92 21:19:37.251851 Using unxz to decompress xz
93 21:19:37.411778 progress 0 % (0 MB)
94 21:19:38.476794 progress 5 % (5 MB)
95 21:19:39.448294 progress 10 % (11 MB)
96 21:19:40.302980 progress 15 % (16 MB)
97 21:19:41.129503 progress 20 % (22 MB)
98 21:19:41.944350 progress 25 % (28 MB)
99 21:19:42.701921 progress 30 % (33 MB)
100 21:19:43.446021 progress 35 % (39 MB)
101 21:19:44.482195 progress 40 % (44 MB)
102 21:19:45.929231 progress 45 % (50 MB)
103 21:19:46.635016 progress 50 % (56 MB)
104 21:19:47.372166 progress 55 % (61 MB)
105 21:19:48.139083 progress 60 % (67 MB)
106 21:19:48.849122 progress 65 % (73 MB)
107 21:19:49.560851 progress 70 % (78 MB)
108 21:19:50.278828 progress 75 % (84 MB)
109 21:19:51.041727 progress 80 % (89 MB)
110 21:19:51.742522 progress 85 % (95 MB)
111 21:19:52.431861 progress 90 % (101 MB)
112 21:19:53.069753 progress 95 % (106 MB)
113 21:19:53.758543 progress 100 % (112 MB)
114 21:19:53.764498 112 MB downloaded in 16.51 s (6.80 MB/s)
115 21:19:53.764906 end: 1.4.1 http-download (duration 00:00:17) [common]
117 21:19:53.765388 end: 1.4 download-retry (duration 00:00:17) [common]
118 21:19:53.765563 start: 1.5 download-retry (timeout 00:09:36) [common]
119 21:19:53.765728 start: 1.5.1 http-download (timeout 00:09:36) [common]
120 21:19:53.766050 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 21:19:53.766190 saving as /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/modules/modules.tar
122 21:19:53.766307 total size: 6609408 (6 MB)
123 21:19:53.766435 Using unxz to decompress xz
124 21:19:53.906995 progress 0 % (0 MB)
125 21:19:53.930004 progress 5 % (0 MB)
126 21:19:54.062319 progress 10 % (0 MB)
127 21:19:54.082758 progress 15 % (0 MB)
128 21:19:54.104779 progress 20 % (1 MB)
129 21:19:54.125088 progress 25 % (1 MB)
130 21:19:54.192496 progress 30 % (1 MB)
131 21:19:54.211791 progress 35 % (2 MB)
132 21:19:54.232192 progress 40 % (2 MB)
133 21:19:54.334932 progress 45 % (2 MB)
134 21:19:54.355685 progress 50 % (3 MB)
135 21:19:54.375481 progress 55 % (3 MB)
136 21:19:54.479730 progress 60 % (3 MB)
137 21:19:54.500213 progress 65 % (4 MB)
138 21:19:54.611746 progress 70 % (4 MB)
139 21:19:54.633721 progress 75 % (4 MB)
140 21:19:54.654884 progress 80 % (5 MB)
141 21:19:54.751622 progress 85 % (5 MB)
142 21:19:54.775370 progress 90 % (5 MB)
143 21:19:54.795846 progress 95 % (6 MB)
144 21:19:54.892526 progress 100 % (6 MB)
145 21:19:54.894741 6 MB downloaded in 1.13 s (5.59 MB/s)
146 21:19:54.895108 end: 1.5.1 http-download (duration 00:00:01) [common]
148 21:19:54.895604 end: 1.5 download-retry (duration 00:00:01) [common]
149 21:19:54.895767 start: 1.6 prepare-tftp-overlay (timeout 00:09:35) [common]
150 21:19:54.895925 start: 1.6.1 extract-nfsrootfs (timeout 00:09:35) [common]
151 21:20:09.195397 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/680152/extract-nfsrootfs-l24gf6vv
152 21:20:09.195733 end: 1.6.1 extract-nfsrootfs (duration 00:00:14) [common]
153 21:20:09.195851 start: 1.6.2 lava-overlay (timeout 00:09:21) [common]
154 21:20:09.196165 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c
155 21:20:09.196339 makedir: /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin
156 21:20:09.196479 makedir: /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/tests
157 21:20:09.196605 makedir: /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/results
158 21:20:09.196739 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-add-keys
159 21:20:09.196942 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-add-sources
160 21:20:09.197084 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-background-process-start
161 21:20:09.197216 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-background-process-stop
162 21:20:09.197360 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-common-functions
163 21:20:09.197496 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-echo-ipv4
164 21:20:09.197675 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-install-packages
165 21:20:09.197833 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-installed-packages
166 21:20:09.197966 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-os-build
167 21:20:09.198096 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-probe-channel
168 21:20:09.198226 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-probe-ip
169 21:20:09.198356 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-target-ip
170 21:20:09.198485 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-target-mac
171 21:20:09.198616 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-target-storage
172 21:20:09.198755 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-test-case
173 21:20:09.198885 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-test-event
174 21:20:09.199014 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-test-feedback
175 21:20:09.199145 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-test-raise
176 21:20:09.199273 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-test-reference
177 21:20:09.199403 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-test-runner
178 21:20:09.199533 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-test-set
179 21:20:09.199669 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-test-shell
180 21:20:09.199806 Updating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-add-keys (debian)
181 21:20:09.770740 Updating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-add-sources (debian)
182 21:20:09.771431 Updating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-install-packages (debian)
183 21:20:09.771878 Updating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-installed-packages (debian)
184 21:20:09.772055 Updating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/bin/lava-os-build (debian)
185 21:20:09.772206 Creating /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/environment
186 21:20:09.772336 LAVA metadata
187 21:20:09.772424 - LAVA_JOB_ID=680152
188 21:20:09.772499 - LAVA_DISPATCHER_IP=192.168.56.76
189 21:20:09.772687 start: 1.6.2.1 ssh-authorize (timeout 00:09:20) [common]
190 21:20:09.773029 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 21:20:09.773128 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:20) [common]
192 21:20:09.773199 skipped lava-vland-overlay
193 21:20:09.773288 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 21:20:09.773375 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:20) [common]
195 21:20:09.773440 skipped lava-multinode-overlay
196 21:20:09.773527 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 21:20:09.773616 start: 1.6.2.4 test-definition (timeout 00:09:20) [common]
198 21:20:09.773696 Loading test definitions
199 21:20:09.773814 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:20) [common]
200 21:20:09.773895 Using /lava-680152 at stage 0
201 21:20:09.774288 uuid=680152_1.6.2.4.1 testdef=None
202 21:20:09.774387 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 21:20:09.774478 start: 1.6.2.4.2 test-overlay (timeout 00:09:20) [common]
204 21:20:09.774978 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 21:20:09.775229 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:20) [common]
207 21:20:09.775841 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 21:20:09.776094 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:20) [common]
210 21:20:09.819823 runner path: /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/0/tests/0_timesync-off test_uuid 680152_1.6.2.4.1
211 21:20:09.820182 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 21:20:09.820442 start: 1.6.2.4.5 git-repo-action (timeout 00:09:20) [common]
214 21:20:09.820520 Using /lava-680152 at stage 0
215 21:20:09.820648 Fetching tests from https://github.com/kernelci/test-definitions.git
216 21:20:09.820751 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/0/tests/1_kselftest-dt'
217 21:20:19.977978 Running '/usr/bin/git checkout kernelci.org
218 21:20:20.836952 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 21:20:20.837423 uuid=680152_1.6.2.4.5 testdef=None
220 21:20:20.837561 end: 1.6.2.4.5 git-repo-action (duration 00:00:11) [common]
222 21:20:20.837773 start: 1.6.2.4.6 test-overlay (timeout 00:09:09) [common]
223 21:20:20.838651 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 21:20:20.838894 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:09) [common]
226 21:20:20.839927 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 21:20:20.840181 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:09) [common]
229 21:20:21.723129 runner path: /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/0/tests/1_kselftest-dt test_uuid 680152_1.6.2.4.5
230 21:20:21.723337 BOARD='beaglebone-black'
231 21:20:21.723460 BRANCH='mainline'
232 21:20:21.723571 SKIPFILE='/dev/null'
233 21:20:21.723680 SKIP_INSTALL='True'
234 21:20:21.723786 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 21:20:21.723896 TST_CASENAME=''
236 21:20:21.724005 TST_CMDFILES='dt'
237 21:20:21.724347 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:01) [common]
239 21:20:21.724773 Creating lava-test-runner.conf files
240 21:20:21.724892 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/680152/lava-overlay-u66eym4c/lava-680152/0 for stage 0
241 21:20:21.725075 - 0_timesync-off
242 21:20:21.725205 - 1_kselftest-dt
243 21:20:21.725406 end: 1.6.2.4 test-definition (duration 00:00:12) [common]
244 21:20:21.725571 start: 1.6.2.5 compress-overlay (timeout 00:09:08) [common]
245 21:20:32.799438 end: 1.6.2.5 compress-overlay (duration 00:00:11) [common]
246 21:20:32.799612 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
247 21:20:32.799696 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 21:20:32.799777 end: 1.6.2 lava-overlay (duration 00:00:24) [common]
249 21:20:32.799855 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
250 21:20:33.549537 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
251 21:20:33.549875 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
252 21:20:33.550038 extracting modules file /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/680152/extract-nfsrootfs-l24gf6vv
253 21:20:33.888870 extracting modules file /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/680152/extract-overlay-ramdisk-_71nr04r/ramdisk
254 21:20:34.831322 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 21:20:34.831524 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
256 21:20:34.831618 [common] Applying overlay to NFS
257 21:20:34.831678 [common] Applying overlay /var/lib/lava/dispatcher/tmp/680152/compress-overlay-p84k14d0/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/680152/extract-nfsrootfs-l24gf6vv
258 21:20:35.834522 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 21:20:35.834738 start: 1.6.6 prepare-kernel (timeout 00:08:54) [common]
260 21:20:35.834845 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:54) [common]
261 21:20:35.834957 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 21:20:35.835049 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 21:20:35.835141 start: 1.6.7 configure-preseed-file (timeout 00:08:54) [common]
264 21:20:35.835230 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 21:20:35.835320 start: 1.6.8 compress-ramdisk (timeout 00:08:54) [common]
266 21:20:35.835404 Building ramdisk /var/lib/lava/dispatcher/tmp/680152/extract-overlay-ramdisk-_71nr04r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/680152/extract-overlay-ramdisk-_71nr04r/ramdisk
267 21:20:38.423604 >> 74798 blocks
268 21:20:40.991499 Adding RAMdisk u-boot header.
269 21:20:40.991718 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/680152/extract-overlay-ramdisk-_71nr04r/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/680152/extract-overlay-ramdisk-_71nr04r/ramdisk.cpio.gz.uboot
270 21:20:48.822594 output: Image Name:
271 21:20:48.822786 output: Created: Fri Aug 30 21:20:40 2024
272 21:20:48.822849 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 21:20:48.822904 output: Data Size: 14793019 Bytes = 14446.31 KiB = 14.11 MiB
274 21:20:48.822956 output: Load Address: 00000000
275 21:20:48.823012 output: Entry Point: 00000000
276 21:20:48.823065 output:
277 21:20:48.823183 rename /var/lib/lava/dispatcher/tmp/680152/extract-overlay-ramdisk-_71nr04r/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/ramdisk/ramdisk.cpio.gz.uboot
278 21:20:48.823309 end: 1.6.8 compress-ramdisk (duration 00:00:13) [common]
279 21:20:48.823406 end: 1.6 prepare-tftp-overlay (duration 00:00:54) [common]
280 21:20:48.823488 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
281 21:20:48.823565 No LXC device requested
282 21:20:48.823641 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 21:20:48.823718 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
284 21:20:48.823790 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 21:20:48.823848 Checking files for TFTP limit of 4294967296 bytes.
286 21:20:48.824255 end: 1 tftp-deploy (duration 00:01:19) [common]
287 21:20:48.824349 start: 2 uboot-action (timeout 00:05:00) [common]
288 21:20:48.824427 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 21:20:48.824499 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 21:20:48.824573 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 21:20:48.824696 substitutions:
292 21:20:48.824756 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 21:20:48.824810 - {DTB_ADDR}: 0x88000000
294 21:20:48.824864 - {DTB}: 680152/tftp-deploy-x16teunw/dtb/am335x-boneblack.dtb
295 21:20:48.824916 - {INITRD}: 680152/tftp-deploy-x16teunw/ramdisk/ramdisk.cpio.gz.uboot
296 21:20:48.824969 - {KERNEL_ADDR}: 0x82000000
297 21:20:48.825021 - {KERNEL}: 680152/tftp-deploy-x16teunw/kernel/zImage
298 21:20:48.825074 - {LAVA_MAC}: None
299 21:20:48.825136 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/680152/extract-nfsrootfs-l24gf6vv
300 21:20:48.825192 - {NFS_SERVER_IP}: 192.168.56.76
301 21:20:48.825243 - {PRESEED_CONFIG}: None
302 21:20:48.825295 - {PRESEED_LOCAL}: None
303 21:20:48.825346 - {RAMDISK_ADDR}: 0x83000000
304 21:20:48.825398 - {RAMDISK}: 680152/tftp-deploy-x16teunw/ramdisk/ramdisk.cpio.gz.uboot
305 21:20:48.825450 - {ROOT_PART}: None
306 21:20:48.825502 - {ROOT}: None
307 21:20:48.825553 - {SERVER_IP}: 192.168.56.76
308 21:20:48.825604 - {TEE_ADDR}: 0x83000000
309 21:20:48.825656 - {TEE}: None
310 21:20:48.825709 Parsed boot commands:
311 21:20:48.825760 - setenv autoload no
312 21:20:48.825831 - setenv initrd_high 0xffffffff
313 21:20:48.825883 - setenv fdt_high 0xffffffff
314 21:20:48.825933 - dhcp
315 21:20:48.825983 - setenv serverip 192.168.56.76
316 21:20:48.826033 - tftp 0x82000000 680152/tftp-deploy-x16teunw/kernel/zImage
317 21:20:48.826084 - tftp 0x83000000 680152/tftp-deploy-x16teunw/ramdisk/ramdisk.cpio.gz.uboot
318 21:20:48.826135 - setenv initrd_size ${filesize}
319 21:20:48.826186 - tftp 0x88000000 680152/tftp-deploy-x16teunw/dtb/am335x-boneblack.dtb
320 21:20:48.826237 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/680152/extract-nfsrootfs-l24gf6vv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 21:20:48.826291 - bootz 0x82000000 0x83000000 0x88000000
322 21:20:48.826382 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 21:20:48.826591 start: 2.3 connect-device (timeout 00:05:00) [common]
325 21:20:48.826655 [common] connect-device Connecting to device using 'telnet conserv3 3000'
326 21:20:48.831337 Setting prompt string to ['lava-test: # ']
327 21:20:48.831944 end: 2.3 connect-device (duration 00:00:00) [common]
328 21:20:48.832174 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 21:20:48.832263 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 21:20:48.832341 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 21:20:48.832562 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
332 21:20:48.845418 >> OK - accepted request
333 21:20:48.846632 Returned 0 in 0 seconds
334 21:20:48.947224 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
336 21:20:48.947787 end: 2.4.1 reset-device (duration 00:00:00) [common]
337 21:20:48.948022 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
338 21:20:48.948228 Setting prompt string to ['Hit any key to stop autoboot']
339 21:20:48.948412 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
340 21:20:48.949078 Trying 192.168.56.22...
341 21:20:48.949261 Connected to conserv3.
342 21:20:48.949413 Escape character is '^]'.
343 21:20:48.949586
344 21:20:48.949756 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
345 21:20:48.949956
346 21:20:56.572075
347 21:20:56.578852 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
348 21:20:56.579065 Trying to boot from MMC1
349 21:20:57.155673
350 21:20:57.156312
351 21:20:57.161399 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
352 21:20:57.161607
353 21:20:57.161684 CPU : AM335X-GP rev 2.0
354 21:20:57.166070 Model: TI AM335x BeagleBone Black
355 21:20:57.166292 DRAM: 512 MiB
356 21:21:00.622804
357 21:21:00.629088 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
358 21:21:00.629363 Trying to boot from MMC1
359 21:21:01.205698
360 21:21:01.206145
361 21:21:01.210723 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
362 21:21:01.210926
363 21:21:01.211088 CPU : AM335X-GP rev 2.0
364 21:21:01.215908 Model: TI AM335x BeagleBone Black
365 21:21:01.216099 DRAM: 512 MiB
366 21:21:03.321373
367 21:21:03.328462 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
368 21:21:03.328770 Trying to boot from MMC1
369 21:21:03.904619
370 21:21:03.905018
371 21:21:03.910201 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
372 21:21:03.910601
373 21:21:03.910775 CPU : AM335X-GP rev 2.0
374 21:21:03.915392 Model: TI AM335x BeagleBone Black
375 21:21:03.915781 DRAM: 512 MiB
376 21:21:03.999596 Core: 160 devices, 18 uclasses, devicetree: separate
377 21:21:04.013136 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
378 21:21:04.414398 NAND: 0 MiB
379 21:21:04.424417 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
380 21:21:04.498814 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
381 21:21:04.520025 <ethaddr> not set. Validating first E-fuse MAC
382 21:21:04.549701 Net: eth2: ethernet@4a100000, eth3: usb_ether
384 21:21:04.607860 Hit any key to stop autoboot: 2
385 21:21:04.608346 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
386 21:21:04.608579 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
387 21:21:04.608748 Setting prompt string to ['=>']
388 21:21:04.608902 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
389 21:21:04.618100 0
390 21:21:04.618674 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
391 21:21:04.618848 Sending with 10 millisecond of delay
393 21:21:05.753323 => setenv autoload no
394 21:21:05.763645 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
395 21:21:05.764743 setenv autoload no
396 21:21:05.765053 Sending with 10 millisecond of delay
398 21:21:07.564860 => setenv initrd_high 0xffffffff
399 21:21:07.575595 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
400 21:21:07.576129 setenv initrd_high 0xffffffff
401 21:21:07.576385 Sending with 10 millisecond of delay
403 21:21:09.205324 => setenv fdt_high 0xffffffff
404 21:21:09.216100 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
405 21:21:09.216668 setenv fdt_high 0xffffffff
406 21:21:09.217076 Sending with 10 millisecond of delay
408 21:21:09.510750 => dhcp
409 21:21:09.521346 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 21:21:09.521991 dhcp
411 21:21:09.522184 link up on port 0, speed 100, full duplex
412 21:21:09.522338 BOOTP broadcast 1
413 21:21:09.776709 BOOTP broadcast 2
414 21:21:10.278630 BOOTP broadcast 3
415 21:21:11.280457 BOOTP broadcast 4
416 21:21:11.311738 *** Unhandled DHCP Option in OFFER/ACK: 42
417 21:21:11.344808 *** Unhandled DHCP Option in OFFER/ACK: 42
418 21:21:11.351257 DHCP client bound to address 192.168.56.2 (1824 ms)
419 21:21:11.351812 Sending with 10 millisecond of delay
421 21:21:13.151778 => setenv serverip 192.168.56.76
422 21:21:13.162099 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
423 21:21:13.162375 setenv serverip 192.168.56.76
424 21:21:13.162688 Sending with 10 millisecond of delay
426 21:21:16.646374 => tftp 0x82000000 680152/tftp-deploy-x16teunw/kernel/zImage
427 21:21:16.656704 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
428 21:21:16.656958 tftp 0x82000000 680152/tftp-deploy-x16teunw/kernel/zImage
429 21:21:16.657032 link up on port 0, speed 100, full duplex
430 21:21:16.661579 Using ethernet@4a100000 device
431 21:21:16.667031 TFTP from server 192.168.56.76; our IP address is 192.168.56.2
432 21:21:16.674339 Filename '680152/tftp-deploy-x16teunw/kernel/zImage'.
433 21:21:16.674538 Load address: 0x82000000
434 21:21:19.975743 Loading: *################################################## 10.8 MiB
435 21:21:19.975939 3.3 MiB/s
436 21:21:19.976010 done
437 21:21:19.980081 Bytes transferred = 11354624 (ad4200 hex)
438 21:21:19.980398 Sending with 10 millisecond of delay
440 21:21:24.436953 => tftp 0x83000000 680152/tftp-deploy-x16teunw/ramdisk/ramdisk.cpio.gz.uboot
441 21:21:24.447355 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
442 21:21:24.447858 tftp 0x83000000 680152/tftp-deploy-x16teunw/ramdisk/ramdisk.cpio.gz.uboot
443 21:21:24.448038 link up on port 0, speed 100, full duplex
444 21:21:24.452016 Using ethernet@4a100000 device
445 21:21:24.457953 TFTP from server 192.168.56.76; our IP address is 192.168.56.2
446 21:21:24.466433 Filename '680152/tftp-deploy-x16teunw/ramdisk/ramdisk.cpio.gz.uboot'.
447 21:21:24.466689 Load address: 0x83000000
448 21:21:26.759313 Loading: *################################################## 14.1 MiB
449 21:21:26.759571 6.2 MiB/s
450 21:21:26.759701 done
451 21:21:26.763594 Bytes transferred = 14793083 (e1b97b hex)
452 21:21:26.764004 Sending with 10 millisecond of delay
454 21:21:28.628827 => setenv initrd_size ${filesize}
455 21:21:28.639549 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
456 21:21:28.640029 setenv initrd_size ${filesize}
457 21:21:28.640426 Sending with 10 millisecond of delay
459 21:21:32.808856 => tftp 0x88000000 680152/tftp-deploy-x16teunw/dtb/am335x-boneblack.dtb
460 21:21:32.819256 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
461 21:21:32.819643 tftp 0x88000000 680152/tftp-deploy-x16teunw/dtb/am335x-boneblack.dtb
462 21:21:32.819791 link up on port 0, speed 100, full duplex
463 21:21:32.824001 Using ethernet@4a100000 device
464 21:21:32.829519 TFTP from server 192.168.56.76; our IP address is 192.168.56.2
465 21:21:32.838067 Filename '680152/tftp-deploy-x16teunw/dtb/am335x-boneblack.dtb'.
466 21:21:32.838296 Load address: 0x88000000
467 21:21:33.538283 Loading: *################################################## 68.7 KiB
468 21:21:33.547261 97.7 KiB/s
469 21:21:33.547488 done
470 21:21:33.547618 Bytes transferred = 70308 (112a4 hex)
471 21:21:33.547950 Sending with 10 millisecond of delay
473 21:21:46.863602 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/680152/extract-nfsrootfs-l24gf6vv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
474 21:21:46.874050 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
475 21:21:46.874498 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/680152/extract-nfsrootfs-l24gf6vv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
476 21:21:46.874901 Sending with 10 millisecond of delay
478 21:21:49.219221 => bootz 0x82000000 0x83000000 0x88000000
479 21:21:49.230048 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
480 21:21:49.230474 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
481 21:21:49.230982 bootz 0x82000000 0x83000000 0x88000000
482 21:21:49.231156 Kernel image @ 0x82000000 [ 0x000000 - 0xad4200 ]
483 21:21:49.231900 ## Loading init Ramdisk from Legacy Image at 83000000 ...
484 21:21:49.237457 Image Name:
485 21:21:49.237703 Created: 2024-08-30 21:20:40 UTC
486 21:21:49.240960 Image Type: ARM Linux RAMDisk Image (uncompressed)
487 21:21:49.246636 Data Size: 14793019 Bytes = 14.1 MiB
488 21:21:49.254856 Load Address: 00000000
489 21:21:49.255123 Entry Point: 00000000
490 21:21:49.422905 Verifying Checksum ... OK
491 21:21:49.423205 ## Flattened Device Tree blob at 88000000
492 21:21:49.429473 Booting using the fdt blob at 0x88000000
493 21:21:49.429692 Working FDT set to 88000000
494 21:21:49.435114 Using Device Tree in place at 88000000, end 880142a3
495 21:21:49.439477 Working FDT set to 88000000
496 21:21:49.452697
497 21:21:49.453049 Starting kernel ...
498 21:21:49.453213
499 21:21:49.453722 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
500 21:21:49.453979 start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
501 21:21:49.454155 Setting prompt string to ['Linux version [0-9]']
502 21:21:49.454324 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
503 21:21:49.454496 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
504 21:21:50.286051 [ 0.000000] Booting Linux on physical CPU 0x0
505 21:21:50.291910 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
506 21:21:50.292166 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
507 21:21:50.292354 Setting prompt string to []
508 21:21:50.292535 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
509 21:21:50.292706 Using line separator: #'\n'#
510 21:21:50.292849 No login prompt set.
511 21:21:50.293007 Parsing kernel messages
512 21:21:50.293148 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
513 21:21:50.293404 [login-action] Waiting for messages, (timeout 00:03:59)
514 21:21:50.293532 Waiting using forced prompt support (timeout 00:01:59)
515 21:21:50.308813 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j302489-arm-gcc-12-multi-v7-defconfig-4tctj) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Aug 30 20:55:00 UTC 2024
516 21:21:50.314677 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
517 21:21:50.320246 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
518 21:21:50.331536 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
519 21:21:50.337247 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
520 21:21:50.343230 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
521 21:21:50.343443 [ 0.000000] Memory policy: Data cache writeback
522 21:21:50.349780 [ 0.000000] efi: UEFI not found.
523 21:21:50.355274 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
524 21:21:50.360815 [ 0.000000] Zone ranges:
525 21:21:50.366536 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
526 21:21:50.372340 [ 0.000000] Normal empty
527 21:21:50.372530 [ 0.000000] HighMem empty
528 21:21:50.378125 [ 0.000000] Movable zone start for each node
529 21:21:50.378317 [ 0.000000] Early memory node ranges
530 21:21:50.390046 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
531 21:21:50.395264 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
532 21:21:50.419819 [ 0.000000] CPU: All CPU(s) started in SVC mode.
533 21:21:50.425507 [ 0.000000] AM335X ES2.0 (sgx neon)
534 21:21:50.437047 [ 0.000000] percpu: Embedded 17 pages/cpu s40332 r8192 d21108 u69632
535 21:21:50.457690 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/680152/extract-nfsrootfs-l24gf6vv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
536 21:21:50.463520 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
537 21:21:50.474943 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
538 21:21:50.480641 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
539 21:21:50.488117 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
540 21:21:50.516966 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
541 21:21:50.523038 <6>[ 0.000000] trace event string verifier disabled
542 21:21:50.523433 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
543 21:21:50.531064 <6>[ 0.000000] rcu: RCU event tracing is enabled.
544 21:21:50.536737 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
545 21:21:50.547963 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
546 21:21:50.553158 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
547 21:21:50.567941 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
548 21:21:50.585113 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
549 21:21:50.591805 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
550 21:21:50.683308 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
551 21:21:50.694759 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
552 21:21:50.701462 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
553 21:21:50.714570 <6>[ 0.019143] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
554 21:21:50.721821 <6>[ 0.033882] Console: colour dummy device 80x30
555 21:21:50.727814 Matched prompt #6: WARNING:
556 21:21:50.728019 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
557 21:21:50.733367 <3>[ 0.038780] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
558 21:21:50.736213 <3>[ 0.045851] This ensures that you still see kernel messages. Please
559 21:21:50.742476 <3>[ 0.052576] update your kernel commandline.
560 21:21:50.783496 <6>[ 0.057186] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
561 21:21:50.788852 <6>[ 0.096145] CPU: Testing write buffer coherency: ok
562 21:21:50.794843 <6>[ 0.101512] CPU0: Spectre v2: using BPIALL workaround
563 21:21:50.795076 <6>[ 0.106976] pid_max: default: 32768 minimum: 301
564 21:21:50.806641 <6>[ 0.112163] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
565 21:21:50.813548 <6>[ 0.119982] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 21:21:50.820465 <6>[ 0.129263] CPU0: thread -1, cpu 0, socket -1, mpidr 0
567 21:21:50.828744 <6>[ 0.136097] Setting up static identity map for 0x80300000 - 0x803000ac
568 21:21:50.834465 <6>[ 0.145641] rcu: Hierarchical SRCU implementation.
569 21:21:50.842284 <6>[ 0.150920] rcu: Max phase no-delay instances is 1000.
570 21:21:50.850455 <6>[ 0.161915] EFI services will not be available.
571 21:21:50.855983 <6>[ 0.167156] smp: Bringing up secondary CPUs ...
572 21:21:50.862076 <6>[ 0.172194] smp: Brought up 1 node, 1 CPU
573 21:21:50.870453 <6>[ 0.176594] SMP: Total of 1 processors activated (996.14 BogoMIPS).
574 21:21:50.876213 <6>[ 0.183347] CPU: All CPU(s) started in SVC mode.
575 21:21:50.888362 <6>[ 0.188524] Memory: 407012K/522240K available (16384K kernel code, 2540K rwdata, 6736K rodata, 2048K init, 430K bss, 48024K reserved, 65536K cma-reserved, 0K highmem)
576 21:21:50.894083 <6>[ 0.204770] devtmpfs: initialized
577 21:21:50.916062 <6>[ 0.221521] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
578 21:21:50.927253 <6>[ 0.230091] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
579 21:21:50.933238 <6>[ 0.240528] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
580 21:21:50.944038 <6>[ 0.252856] pinctrl core: initialized pinctrl subsystem
581 21:21:50.953066 <6>[ 0.263508] DMI not present or invalid.
582 21:21:50.961405 <6>[ 0.269251] NET: Registered PF_NETLINK/PF_ROUTE protocol family
583 21:21:50.970860 <6>[ 0.278163] DMA: preallocated 256 KiB pool for atomic coherent allocations
584 21:21:50.986081 <6>[ 0.289509] thermal_sys: Registered thermal governor 'step_wise'
585 21:21:50.986389 <6>[ 0.289654] cpuidle: using governor menu
586 21:21:51.013720 <6>[ 0.325232] No ATAGs?
587 21:21:51.019823 <6>[ 0.327872] hw-breakpoint: debug architecture 0x4 unsupported.
588 21:21:51.029940 <6>[ 0.339821] Serial: AMBA PL011 UART driver
589 21:21:51.070707 <6>[ 0.382716] iommu: Default domain type: Translated
590 21:21:51.079976 <6>[ 0.387947] iommu: DMA domain TLB invalidation policy: strict mode
591 21:21:51.090279 <5>[ 0.400719] SCSI subsystem initialized
592 21:21:51.114095 <6>[ 0.420398] usbcore: registered new interface driver usbfs
593 21:21:51.120948 <6>[ 0.426351] usbcore: registered new interface driver hub
594 21:21:51.121193 <6>[ 0.432171] usbcore: registered new device driver usb
595 21:21:51.126696 <6>[ 0.438658] pps_core: LinuxPPS API ver. 1 registered
596 21:21:51.138345 <6>[ 0.444090] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
597 21:21:51.143350 <6>[ 0.453790] PTP clock support registered
598 21:21:51.168614 <6>[ 0.479587] EDAC MC: Ver: 3.0.0
599 21:21:51.187331 <6>[ 0.496687] scmi_core: SCMI protocol bus registered
600 21:21:51.202330 <6>[ 0.513950] vgaarb: loaded
601 21:21:51.214871 <6>[ 0.526877] clocksource: Switched to clocksource dmtimer
602 21:21:51.250998 <6>[ 0.562658] NET: Registered PF_INET protocol family
603 21:21:51.263532 <6>[ 0.568317] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
604 21:21:51.269504 <6>[ 0.577159] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
605 21:21:51.280777 <6>[ 0.586045] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
606 21:21:51.286525 <6>[ 0.594316] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
607 21:21:51.298182 <6>[ 0.602601] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
608 21:21:51.304130 <6>[ 0.610317] TCP: Hash tables configured (established 4096 bind 4096)
609 21:21:51.309953 <6>[ 0.617239] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
610 21:21:51.315750 <6>[ 0.624252] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
611 21:21:51.323145 <6>[ 0.631866] NET: Registered PF_UNIX/PF_LOCAL protocol family
612 21:21:51.360136 <6>[ 0.666309] RPC: Registered named UNIX socket transport module.
613 21:21:51.360385 <6>[ 0.672736] RPC: Registered udp transport module.
614 21:21:51.365718 <6>[ 0.677869] RPC: Registered tcp transport module.
615 21:21:51.374341 <6>[ 0.682974] RPC: Registered tcp-with-tls transport module.
616 21:21:51.380128 <6>[ 0.688905] RPC: Registered tcp NFSv4.1 backchannel transport module.
617 21:21:51.387320 <6>[ 0.695812] PCI: CLS 0 bytes, default 64
618 21:21:51.389614 <5>[ 0.701575] Initialise system trusted keyrings
619 21:21:51.416756 <6>[ 0.725482] Trying to unpack rootfs image as initramfs...
620 21:21:51.441664 <6>[ 0.747522] workingset: timestamp_bits=30 max_order=17 bucket_order=0
621 21:21:51.446518 <6>[ 0.755011] squashfs: version 4.0 (2009/01/31) Phillip Lougher
622 21:21:51.488092 <5>[ 0.799974] NFS: Registering the id_resolver key type
623 21:21:51.493920 <5>[ 0.805558] Key type id_resolver registered
624 21:21:51.499503 <5>[ 0.810181] Key type id_legacy registered
625 21:21:51.508153 <6>[ 0.814611] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
626 21:21:51.514982 <6>[ 0.821832] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
627 21:21:51.555520 <5>[ 0.867449] Key type asymmetric registered
628 21:21:51.561482 <5>[ 0.871972] Asymmetric key parser 'x509' registered
629 21:21:51.569679 <6>[ 0.877479] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
630 21:21:51.575565 <6>[ 0.885366] io scheduler mq-deadline registered
631 21:21:51.584303 <6>[ 0.890348] io scheduler kyber registered
632 21:21:51.584498 <6>[ 0.894800] io scheduler bfq registered
633 21:21:51.941843 <6>[ 1.249933] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
634 21:21:51.979341 <6>[ 1.291098] msm_serial: driver initialized
635 21:21:51.985364 <6>[ 1.295879] SuperH (H)SCI(F) driver initialized
636 21:21:51.991381 <6>[ 1.301210] STMicroelectronics ASC driver initialized
637 21:21:51.996638 <6>[ 1.306886] STM32 USART driver initialized
638 21:21:52.097512 <6>[ 1.409325] brd: module loaded
639 21:21:52.137650 <6>[ 1.448324] loop: module loaded
640 21:21:52.173410 <6>[ 1.484322] CAN device driver interface
641 21:21:52.179880 <6>[ 1.489583] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
642 21:21:52.185690 <6>[ 1.496484] e1000e: Intel(R) PRO/1000 Network Driver
643 21:21:52.192803 <6>[ 1.501930] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
644 21:21:52.198145 <6>[ 1.508364] igb: Intel(R) Gigabit Ethernet Network Driver
645 21:21:52.205866 <6>[ 1.514187] igb: Copyright (c) 2007-2014 Intel Corporation.
646 21:21:52.217494 <6>[ 1.523388] pegasus: Pegasus/Pegasus II USB Ethernet driver
647 21:21:52.223317 <6>[ 1.529542] usbcore: registered new interface driver pegasus
648 21:21:52.228811 <6>[ 1.535667] usbcore: registered new interface driver asix
649 21:21:52.234568 <6>[ 1.541553] usbcore: registered new interface driver ax88179_178a
650 21:21:52.240591 <6>[ 1.548139] usbcore: registered new interface driver cdc_ether
651 21:21:52.246146 <6>[ 1.554439] usbcore: registered new interface driver smsc75xx
652 21:21:52.251882 <6>[ 1.560675] usbcore: registered new interface driver smsc95xx
653 21:21:52.258043 <6>[ 1.566922] usbcore: registered new interface driver net1080
654 21:21:52.263725 <6>[ 1.573042] usbcore: registered new interface driver cdc_subset
655 21:21:52.269368 <6>[ 1.579449] usbcore: registered new interface driver zaurus
656 21:21:52.276389 <6>[ 1.585518] usbcore: registered new interface driver cdc_ncm
657 21:21:52.286829 <6>[ 1.595043] usbcore: registered new interface driver usb-storage
658 21:21:52.419152 <6>[ 1.728934] i2c_dev: i2c /dev entries driver
659 21:21:52.479660 <5>[ 1.783452] cpuidle: enable-method property 'ti,am3352' found operations
660 21:21:52.485427 <6>[ 1.793093] sdhci: Secure Digital Host Controller Interface driver
661 21:21:52.492880 <6>[ 1.799846] sdhci: Copyright(c) Pierre Ossman
662 21:21:52.500148 <6>[ 1.806293] Synopsys Designware Multimedia Card Interface Driver
663 21:21:52.505820 <6>[ 1.814285] sdhci-pltfm: SDHCI platform and OF driver helper
664 21:21:52.562071 <6>[ 1.870287] ledtrig-cpu: registered to indicate activity on CPUs
665 21:21:52.603000 <6>[ 1.907218] usbcore: registered new interface driver usbhid
666 21:21:52.603227 <6>[ 1.913257] usbhid: USB HID core driver
667 21:21:52.654473 <6>[ 1.963653] NET: Registered PF_INET6 protocol family
668 21:21:52.705921 <6>[ 2.017689] Segment Routing with IPv6
669 21:21:52.711964 <6>[ 2.021836] In-situ OAM (IOAM) with IPv6
670 21:21:52.718344 <6>[ 2.026226] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
671 21:21:52.724114 <6>[ 2.033602] NET: Registered PF_PACKET protocol family
672 21:21:52.729858 <6>[ 2.039150] can: controller area network core
673 21:21:52.735686 <6>[ 2.043974] NET: Registered PF_CAN protocol family
674 21:21:52.735908 <6>[ 2.049200] can: raw protocol
675 21:21:52.741460 <6>[ 2.052524] can: broadcast manager protocol
676 21:21:52.747956 <6>[ 2.057116] can: netlink gateway - max_hops=1
677 21:21:52.754162 <5>[ 2.062613] Key type dns_resolver registered
678 21:21:52.760396 <6>[ 2.067678] ThumbEE CPU extension supported.
679 21:21:52.760616 <5>[ 2.072362] Registering SWP/SWPB emulation handler
680 21:21:52.770123 <3>[ 2.078054] omap_voltage_late_init: Voltage driver support not added
681 21:21:52.828565 <5>[ 2.138563] Loading compiled-in X.509 certificates
682 21:21:52.976799 <6>[ 2.275373] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
683 21:21:52.984095 <6>[ 2.292019] pinctrl-single 44e10800.pinmux: 142 pins, size 568
684 21:21:53.010135 <3>[ 2.315563] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
685 21:21:53.100299 <3>[ 2.405747] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
686 21:21:53.207352 <6>[ 2.517376] OMAP GPIO hardware version 0.1
687 21:21:53.228136 <6>[ 2.535822] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
688 21:21:53.301028 <4>[ 2.608920] at24 2-0054: supply vcc not found, using dummy regulator
689 21:21:53.349638 <4>[ 2.657507] at24 2-0055: supply vcc not found, using dummy regulator
690 21:21:53.392432 <4>[ 2.700368] at24 2-0056: supply vcc not found, using dummy regulator
691 21:21:53.444327 <4>[ 2.752279] at24 2-0057: supply vcc not found, using dummy regulator
692 21:21:53.508931 <6>[ 2.817664] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
693 21:21:53.574800 <3>[ 2.879423] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
694 21:21:53.599202 <6>[ 2.900257] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
695 21:21:53.625804 <4>[ 2.932341] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
696 21:21:53.670415 <4>[ 2.977629] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
697 21:21:53.729477 <6>[ 3.037521] omap_rng 48310000.rng: Random Number Generator ver. 20
698 21:21:53.752436 <5>[ 3.063389] random: crng init done
699 21:21:53.860509 <6>[ 3.167091] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
700 21:21:54.478280 <6>[ 3.788231] Freeing initrd memory: 14448K
701 21:21:54.521955 <6>[ 3.827346] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
702 21:21:54.527613 <6>[ 3.837549] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
703 21:21:54.539357 <6>[ 3.844813] cpsw-switch 4a100000.switch: ALE Table size 1024
704 21:21:54.544793 <6>[ 3.851214] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
705 21:21:54.556422 <6>[ 3.859336] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
706 21:21:54.563667 <6>[ 3.870968] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
707 21:21:54.576105 <5>[ 3.880006] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
708 21:21:54.603673 <3>[ 3.909601] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
709 21:21:54.609449 <6>[ 3.918146] edma 49000000.dma: TI EDMA DMA engine driver
710 21:21:54.680110 <3>[ 3.985410] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
711 21:21:54.693606 <6>[ 3.999844] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
712 21:21:54.712369 <3>[ 4.021296] l3-aon-clkctrl:0000:0: failed to disable
713 21:21:54.742164 <6>[ 4.047910] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
714 21:21:54.747665 <6>[ 4.057368] printk: legacy console [ttyS0] enabled
715 21:21:54.753039 <6>[ 4.057368] printk: legacy console [ttyS0] enabled
716 21:21:54.759081 <6>[ 4.067698] printk: legacy bootconsole [omap8250] disabled
717 21:21:54.764923 <6>[ 4.067698] printk: legacy bootconsole [omap8250] disabled
718 21:21:54.822978 <4>[ 4.127797] tps65217-pmic: Failed to locate of_node [id: -1]
719 21:21:54.826169 <4>[ 4.135162] tps65217-bl: Failed to locate of_node [id: -1]
720 21:21:54.842623 <6>[ 4.154395] tps65217 0-0024: TPS65217 ID 0xe version 1.2
721 21:21:54.860556 <6>[ 4.161310] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
722 21:21:54.872312 <6>[ 4.174999] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
723 21:21:54.877406 <6>[ 4.186887] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
724 21:21:54.901381 <6>[ 4.207783] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
725 21:21:54.907450 <6>[ 4.216929] sdhci-omap 48060000.mmc: Got CD GPIO
726 21:21:54.915080 <4>[ 4.222050] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
727 21:21:54.929925 <4>[ 4.235090] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
728 21:21:54.936436 <4>[ 4.244443] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
729 21:21:54.946094 <4>[ 4.253017] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
730 21:21:55.042437 <6>[ 4.349940] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
731 21:21:55.077656 <6>[ 4.383964] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
732 21:21:55.100297 <6>[ 4.406150] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
733 21:21:55.106958 <6>[ 4.415041] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
734 21:21:55.160124 <6>[ 4.463684] mmc1: new high speed MMC card at address 0001
735 21:21:55.160376 <6>[ 4.470999] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
736 21:21:55.166240 <6>[ 4.477213] mmc0: new high speed SDHC card at address 0001
737 21:21:55.174072 <6>[ 4.484220] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
738 21:21:55.182605 <6>[ 4.493639] mmcblk1:
739 21:21:55.187270 <6>[ 4.497258] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
740 21:21:55.194694 <6>[ 4.505230] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
741 21:21:55.202953 <6>[ 4.512021] mmcblk0: p1
742 21:21:55.214327 <6>[ 4.517525] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
743 21:21:55.220640 <6>[ 4.528665] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
744 21:21:57.302269 <6>[ 6.607848] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
745 21:22:05.215177 <5>[ 6.667008] Sending DHCP requests ..., OK
746 21:22:05.226465 <6>[ 14.531454] IP-Config: Got DHCP answer from 192.168.56.254, my address is 192.168.56.2
747 21:22:05.226769 <6>[ 14.539871] IP-Config: Complete:
748 21:22:05.240697 <6>[ 14.543406] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.56.2, mask=255.255.255.0, gw=192.168.56.254
749 21:22:05.246289 <6>[ 14.554188] host=192.168.56.2, domain=mayfield.sirena.org.uk, nis-domain=(none)
750 21:22:05.256436 <6>[ 14.562314] bootserver=192.168.56.254, rootserver=192.168.56.76, rootpath=
751 21:22:05.261942 <6>[ 14.562348] nameserver0=192.168.56.254
752 21:22:05.268447 <6>[ 14.574524] ntpserver0=50.205.244.22, ntpserver1=85.199.214.99
753 21:22:05.268755 <6>[ 14.582157] clk: Disabling unused clocks
754 21:22:05.277021 <6>[ 14.586758] PM: genpd: Disabling unused power domains
755 21:22:05.296582 <6>[ 14.605344] Freeing unused kernel image (initmem) memory: 2048K
756 21:22:05.304183 <6>[ 14.615169] Run /init as init process
757 21:22:05.330104 Loading, please wait...
758 21:22:05.404735 Starting systemd-udevd version 252.22-1~deb12u1
759 21:22:08.343891 <4>[ 17.648796] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 21:22:08.482003 <4>[ 17.786998] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 21:22:08.643863 <6>[ 17.956151] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 21:22:08.653673 <6>[ 17.962017] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 21:22:08.778831 <6>[ 18.090348] hub 1-0:1.0: USB hub found
764 21:22:08.799282 <6>[ 18.110219] hub 1-0:1.0: 1 port detected
765 21:22:09.077164 <6>[ 18.388203] tda998x 0-0070: found TDA19988
766 21:22:11.848022 Begin: Loading essential drivers ... done.
767 21:22:11.852733 Begin: Running /scripts/init-premount ... done.
768 21:22:11.858028 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 21:22:11.871968 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 21:22:11.872166 Device /sys/class/net/eth0 found
771 21:22:11.872320 done.
772 21:22:11.928296 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 21:22:12.008224 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
774 21:22:12.127084 IP-Config: eth0 complete (dhcp from 192.168.56.254):
775 21:22:12.137846 address: 192.168.56.2 broadcast: 192.168.56.255 netmask: 255.255.255.0
776 21:22:12.141216 gateway: 192.168.56.254 dns0 : 192.168.56.254 dns1 : 0.0.0.0
777 21:22:12.154834 domain : mayfield.sirena.org.uk
778 21:22:12.155187 rootserver: 192.168.56.254 rootpath:
779 21:22:12.155349 filename :
780 21:22:12.248078 done.
781 21:22:12.561045 Begin: Running /scripts/nfs-bottom ... done.
782 21:22:12.658201 Begin: Running /scripts/init-bottom ... done.
783 21:22:16.488130 <30>[ 25.796587] systemd[1]: System time before build time, advancing clock.
784 21:22:16.725169 <30>[ 26.007456] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 21:22:16.734464 <30>[ 26.044877] systemd[1]: Detected architecture arm.
786 21:22:16.748609
787 21:22:16.748837 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 21:22:16.749015
789 21:22:16.809234 <30>[ 26.118296] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 21:22:20.719916 <30>[ 30.027683] systemd[1]: Queued start job for default target graphical.target.
791 21:22:20.736744 <30>[ 30.042335] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 21:22:20.744285 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 21:22:20.785353 <30>[ 30.092745] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 21:22:20.799043 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 21:22:20.837088 <30>[ 30.143004] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 21:22:20.849617 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 21:22:20.882219 <30>[ 30.188667] systemd[1]: Created slice user.slice - User and Session Slice.
798 21:22:20.888902 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 21:22:20.925273 <30>[ 30.229134] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 21:22:20.937480 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 21:22:20.972041 <30>[ 30.278082] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 21:22:20.982479 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 21:22:21.022700 <30>[ 30.317941] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 21:22:21.029076 <30>[ 30.338446] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 21:22:21.037780 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 21:22:21.070575 <30>[ 30.377328] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 21:22:21.079080 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 21:22:21.111579 <30>[ 30.417748] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 21:22:21.119902 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 21:22:21.151078 <30>[ 30.457957] systemd[1]: Reached target paths.target - Path Units.
811 21:22:21.156544 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 21:22:21.191215 <30>[ 30.497503] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 21:22:21.198030 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 21:22:21.232229 <30>[ 30.538316] systemd[1]: Reached target slices.target - Slice Units.
815 21:22:21.237879 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 21:22:21.271158 <30>[ 30.577652] systemd[1]: Reached target swap.target - Swaps.
817 21:22:21.275180 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 21:22:21.311450 <30>[ 30.617744] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 21:22:21.320439 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 21:22:21.352902 <30>[ 30.660133] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 21:22:21.366148 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 21:22:21.498031 <30>[ 30.799570] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 21:22:21.510678 <30>[ 30.817248] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 21:22:21.519477 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 21:22:21.553406 <30>[ 30.859456] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 21:22:21.560338 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 21:22:21.594490 <30>[ 30.900705] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 21:22:21.602851 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 21:22:21.635597 <30>[ 30.942001] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 21:22:21.641534 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 21:22:21.684979 <30>[ 30.990520] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 21:22:21.692589 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 21:22:21.729567 <30>[ 31.028332] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 21:22:21.745916 <30>[ 31.046365] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 21:22:21.794896 <30>[ 31.102072] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 21:22:21.811774 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 21:22:21.835227 <30>[ 31.143128] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 21:22:21.869911 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 21:22:21.946600 <30>[ 31.252755] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 21:22:21.967324 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 21:22:22.022882 <30>[ 31.329491] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 21:22:22.059729 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 21:22:22.123510 <30>[ 31.430906] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 21:22:22.150024 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 21:22:22.203381 <30>[ 31.511244] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 21:22:22.217919 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 21:22:22.284205 <30>[ 31.590800] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 21:22:22.299531 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 21:22:22.350610 <30>[ 31.658039] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 21:22:22.362860 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 21:22:22.443518 <30>[ 31.751235] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 21:22:22.462063 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 21:22:22.497506 <28>[ 31.799184] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 21:22:22.506065 <28>[ 31.812810] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 21:22:22.541882 <30>[ 31.850030] systemd[1]: Starting systemd-journald.service - Journal Service...
856 21:22:22.570238 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 21:22:22.640761 <30>[ 31.948313] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 21:22:22.659776 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 21:22:22.702475 <30>[ 32.009841] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 21:22:22.751071 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 21:22:22.816336 <30>[ 32.122390] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 21:22:22.869453 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 21:22:22.943208 <30>[ 32.250078] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 21:22:22.989485 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 21:22:23.062823 <30>[ 32.370640] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 21:22:23.100598 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 21:22:23.121037 <30>[ 32.428647] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 21:22:23.152938 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 21:22:23.184597 <30>[ 32.491996] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 21:22:23.216638 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 21:22:23.383287 <30>[ 32.691831] systemd[1]: Started systemd-journald.service - Journal Service.
872 21:22:23.409596 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
873 21:22:23.448526 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 21:22:23.470617 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
875 21:22:23.511535 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
876 21:22:23.562076 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
877 21:22:23.601595 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
878 21:22:23.636242 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
879 21:22:23.653047 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
880 21:22:23.682956 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
881 21:22:23.730738 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
882 21:22:23.764788 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
883 21:22:23.803619 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
884 21:22:23.874450 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
885 21:22:23.962434 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
886 21:22:24.015586 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
887 21:22:24.126139 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
888 21:22:24.230956 <46>[ 33.538811] systemd-journald[164]: Received client request to flush runtime journal.
889 21:22:24.244284 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
890 21:22:24.450392 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
891 21:22:24.482375 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
892 21:22:25.840345 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
893 21:22:25.909582 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
894 21:22:26.172484 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
895 21:22:27.752871 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
896 21:22:27.852652 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
897 21:22:27.951864 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
898 21:22:28.130247 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
899 21:22:28.857232 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
900 21:22:28.930313 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
901 21:22:29.290127 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
902 21:22:29.374414 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
903 21:22:30.680540 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
904 21:22:32.001662 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
905 21:22:32.106306 <5>[ 41.415351] cfg80211: Loading compiled-in X.509 certificates for regulatory database
906 21:22:33.234342 <5>[ 42.545649] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
907 21:22:33.296857 <5>[ 42.605183] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
908 21:22:33.310789 <4>[ 42.618280] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
909 21:22:33.315765 <6>[ 42.627381] cfg80211: failed to load regulatory.db
910 21:22:34.111832 [[0m[0;31m* [0m] Job systemd-networkd.service/start running (13s / 1min 38s)
911 21:22:34.442490 M
[K[[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
912 21:22:41.484653 [K[[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
913 21:22:41.523515 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
914 21:22:41.561564 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
915 21:22:41.654080 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
916 21:22:41.727449 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
917 21:22:41.789586 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
918 21:22:41.836198 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
919 21:22:42.003353 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
920 21:22:42.080208 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
921 21:22:42.127834 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
922 21:22:42.183595 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
923 21:22:42.224075 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
924 21:22:42.272936 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
925 21:22:42.411352 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
926 21:22:42.871909 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
927 21:22:42.910525 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
928 21:22:42.924468 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
929 21:22:42.960599 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
930 21:22:43.118248 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
931 21:22:43.247123 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
932 21:22:43.280416 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
933 21:22:43.373096 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
934 21:22:43.465518 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
935 21:22:43.500118 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
936 21:22:43.537082 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
937 21:22:43.570820 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
938 21:22:43.605118 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
939 21:22:43.703617 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
940 21:22:43.730320 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
941 21:22:43.934838 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
942 21:22:44.089236 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
943 21:22:44.163626 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
944 21:22:44.195628 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
945 21:22:44.213365 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
946 21:22:44.382086 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
947 21:22:44.442412 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
948 21:22:44.500574 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
949 21:22:44.519216 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
950 21:22:44.551379 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
951 21:22:44.873146 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
952 21:22:44.893955 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
953 21:22:45.416315 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
954 21:22:45.507072 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
955 21:22:45.558853 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
956 21:22:45.593144 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
957 21:22:45.678684 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
958 21:22:45.867449 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
959 21:22:46.078570
960 21:22:46.078876 Debian GNU/Linux 12 debian-bookwor
961 21:22:46.083328 debian-bookworm-armhf login: root (automatic login)
962 21:22:46.083576
963 21:22:46.561316 Linux debian-bookworm-armhf 6.11.0-rc5 #1 SMP Fri Aug 30 20:55:00 UTC 2024 armv7l
964 21:22:46.561598
965 21:22:46.567042 The programs included with the Debian GNU/Linux system are free software;
966 21:22:46.572513 the exact distribution terms for each program are described in the
967 21:22:46.578144 individual files in /usr/share/doc/*/copyright.
968 21:22:46.578397
969 21:22:46.585217 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
970 21:22:46.585464 permitted by applicable law.
971 21:22:51.541848 Unable to match end of the kernel message
973 21:22:51.542239 Setting prompt string to ['/ #']
974 21:22:51.542342 end: 2.4.4.1 login-action (duration 00:01:01) [common]
976 21:22:51.542527 end: 2.4.4 auto-login-action (duration 00:01:02) [common]
977 21:22:51.542613 start: 2.4.5 expect-shell-connection (timeout 00:02:57) [common]
978 21:22:51.542678 Setting prompt string to ['/ #']
979 21:22:51.542732 Forcing a shell prompt, looking for ['/ #']
981 21:22:51.592978 / #
982 21:22:51.593404 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
983 21:22:51.593594 Waiting using forced prompt support (timeout 00:02:30)
984 21:22:51.597700
985 21:22:51.604460 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
986 21:22:51.604758 start: 2.4.6 export-device-env (timeout 00:02:57) [common]
987 21:22:51.604955 Sending with 10 millisecond of delay
989 21:22:56.594171 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/680152/extract-nfsrootfs-l24gf6vv'
990 21:22:56.604733 export NFS_ROOTFS='/var<46>[ 62.355202] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
991 21:22:56.605043 /<46>[ 62.381171] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
992 21:22:56.605261 lib/lava/dispatcher/tmp/680152/extract-nfsrootfs-l24gf6vv'
993 21:22:56.606978 Sending with 10 millisecond of delay
995 21:22:58.825733 / # export NFS_SERVER_IP='192.168.56.76'
996 21:22:58.836318 export NFS_SERVER_IP='192.168.56.76'
997 21:22:58.837090 end: 2.4.6 export-device-env (duration 00:00:07) [common]
998 21:22:58.837368 end: 2.4 uboot-commands (duration 00:02:10) [common]
999 21:22:58.837646 end: 2 uboot-action (duration 00:02:10) [common]
1000 21:22:58.837934 start: 3 lava-test-retry (timeout 00:06:31) [common]
1001 21:22:58.838195 start: 3.1 lava-test-shell (timeout 00:06:31) [common]
1002 21:22:58.838429 Using namespace: common
1004 21:22:58.939051 / # #
1005 21:22:58.939499 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1006 21:22:58.943850 #
1007 21:22:58.949159 Using /lava-680152
1009 21:22:59.049848 / # export SHELL=/bin/bash
1010 21:22:59.055859 export SHELL=/bin/bash
1012 21:22:59.179956 / # . /lava-680152/environment
1013 21:22:59.184726 . /lava-680152/environment
1015 21:22:59.297277 / # /lava-680152/bin/lava-test-runner /lava-680152/0
1016 21:22:59.297671 Test shell timeout: 10s (minimum of the action and connection timeout)
1017 21:22:59.301881 /lava-680152/bin/lava-test-runner /lava-680152/0
1018 21:22:59.671219 + export TESTRUN_ID=0_timesync-off
1019 21:22:59.679163 + TESTRUN_ID=0_timesync-off
1020 21:22:59.679438 + cd /lava-680152/0/tests/0_timesync-off
1021 21:22:59.679599 ++ cat uuid
1022 21:22:59.693434 + UUID=680152_1.6.2.4.1
1023 21:22:59.693701 + set +x
1024 21:22:59.702051 <LAVA_SIGNAL_STARTRUN 0_timesync-off 680152_1.6.2.4.1>
1025 21:22:59.702324 + systemctl stop systemd-timesyncd
1026 21:22:59.702720 Received signal: <STARTRUN> 0_timesync-off 680152_1.6.2.4.1
1027 21:22:59.702923 Starting test lava.0_timesync-off (680152_1.6.2.4.1)
1028 21:22:59.703165 Skipping test definition patterns.
1029 21:22:59.985002 + set +x
1030 21:22:59.985308 <LAVA_SIGNAL_ENDRUN 0_timesync-off 680152_1.6.2.4.1>
1031 21:22:59.985693 Received signal: <ENDRUN> 0_timesync-off 680152_1.6.2.4.1
1032 21:22:59.985917 Ending use of test pattern.
1033 21:22:59.986073 Ending test lava.0_timesync-off (680152_1.6.2.4.1), duration 0.28
1035 21:23:00.160856 + export TESTRUN_ID=1_kselftest-dt
1036 21:23:00.168816 + TESTRUN_ID=1_kselftest-dt
1037 21:23:00.169113 + cd /lava-680152/0/tests/1_kselftest-dt
1038 21:23:00.169283 ++ cat uuid
1039 21:23:00.183275 + UUID=680152_1.6.2.4.5
1040 21:23:00.183563 + set +x
1041 21:23:00.188959 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 680152_1.6.2.4.5>
1042 21:23:00.189201 + cd ./automated/linux/kselftest/
1043 21:23:00.189581 Received signal: <STARTRUN> 1_kselftest-dt 680152_1.6.2.4.5
1044 21:23:00.189757 Starting test lava.1_kselftest-dt (680152_1.6.2.4.5)
1045 21:23:00.189998 Skipping test definition patterns.
1046 21:23:00.216738 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1047 21:23:00.334492 INFO: install_deps skipped
1048 21:23:01.049489 --2024-08-30 21:23:01-- http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1049 21:23:01.065187 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1050 21:23:01.204678 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1051 21:23:01.344523 HTTP request sent, awaiting response... 200 OK
1052 21:23:01.344826 Length: 3608612 (3.4M) [application/octet-stream]
1053 21:23:01.350116 Saving to: 'kselftest_armhf.tar.gz'
1054 21:23:01.350339
1055 21:23:02.945354
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 47.54K 173KB/s
kselftest_armhf.tar 6%[> ] 218.67K 396KB/s
kselftest_armhf.tar 22%[===> ] 781.60K 946KB/s
kselftest_armhf.tar 28%[====> ] 1016K 966KB/s
kselftest_armhf.tar 43%[=======> ] 1.49M 1.19MB/s
kselftest_armhf.tar 79%[==============> ] 2.72M 1.87MB/s
kselftest_armhf.tar 100%[===================>] 3.44M 2.16MB/s in 1.6s
1056 21:23:02.945655
1057 21:23:03.462407 2024-08-30 21:23:02 (2.16 MB/s) - 'kselftest_armhf.tar.gz' saved [3608612/3608612]
1058 21:23:03.462652
1059 21:24:19.745273 skiplist:
1060 21:24:19.745632 ========================================
1061 21:24:19.750632 ========================================
1062 21:24:19.880197 dt:test_unprobed_devices.sh
1063 21:24:19.930542 ============== Tests to run ===============
1064 21:24:19.938032 dt:test_unprobed_devices.sh
1065 21:24:19.941954 ===========End Tests to run ===============
1066 21:24:19.955745 shardfile-dt pass
1067 21:24:20.207431 <12>[ 149.522888] kselftest: Running tests in dt
1068 21:24:20.236306 TAP version 13
1069 21:24:20.259070 1..1
1070 21:24:20.310752 # timeout set to 45
1071 21:24:20.311052 # selftests: dt: test_unprobed_devices.sh
1072 21:24:21.079474 # TAP version 13
1073 21:24:33.073107 # 1..255
1074 21:24:33.252209 # ok 1 / # SKIP
1075 21:24:33.272937 # ok 2 /clk_mcasp0
1076 21:24:33.345773 # ok 3 /clk_mcasp0_fixed # SKIP
1077 21:24:33.419498 # ok 4 /cpus/cpu@0 # SKIP
1078 21:24:33.490352 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1079 21:24:33.510437 # ok 6 /fixedregulator0
1080 21:24:33.534930 # ok 7 /leds
1081 21:24:33.551757 # ok 8 /ocp
1082 21:24:33.577142 # ok 9 /ocp/interconnect@44c00000
1083 21:24:33.603999 # ok 10 /ocp/interconnect@44c00000/segment@0
1084 21:24:33.628630 # ok 11 /ocp/interconnect@44c00000/segment@100000
1085 21:24:33.652059 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1086 21:24:33.722181 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1087 21:24:33.744119 # ok 14 /ocp/interconnect@44c00000/segment@200000
1088 21:24:33.760419 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1089 21:24:33.864240 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1090 21:24:33.935663 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1091 21:24:34.008745 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1092 21:24:34.070433 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1093 21:24:34.145490 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1094 21:24:34.213972 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1095 21:24:34.285050 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1096 21:24:34.346331 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1097 21:24:34.418540 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1098 21:24:34.489042 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1099 21:24:34.555232 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1100 21:24:34.626366 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1101 21:24:34.699150 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1102 21:24:34.761052 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1103 21:24:34.837722 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1104 21:24:34.906072 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1105 21:24:34.974567 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1106 21:24:35.042605 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1107 21:24:35.111796 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1108 21:24:35.182583 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1109 21:24:35.244092 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1110 21:24:35.317841 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1111 21:24:35.387146 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1112 21:24:35.459024 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1113 21:24:35.529093 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1114 21:24:35.599303 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1115 21:24:35.663434 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1116 21:24:35.739833 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1117 21:24:35.807595 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1118 21:24:35.879643 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1119 21:24:35.950044 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1120 21:24:36.013487 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1121 21:24:36.089305 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1122 21:24:36.153377 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1123 21:24:36.229550 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1124 21:24:36.291785 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1125 21:24:36.367822 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1126 21:24:36.436789 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1127 21:24:36.509474 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1128 21:24:36.575118 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1129 21:24:36.646717 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1130 21:24:36.717865 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1131 21:24:36.786663 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1132 21:24:36.858933 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1133 21:24:36.921812 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1134 21:24:36.997156 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1135 21:24:37.068511 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1136 21:24:37.138861 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1137 21:24:37.209149 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1138 21:24:37.277315 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1139 21:24:37.340180 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1140 21:24:37.417706 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1141 21:24:37.485872 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1142 21:24:37.551456 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1143 21:24:37.621599 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1144 21:24:37.693240 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1145 21:24:37.758129 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1146 21:24:37.834909 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1147 21:24:37.902059 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1148 21:24:37.970360 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1149 21:24:38.043515 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1150 21:24:38.109574 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1151 21:24:38.182924 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1152 21:24:38.250992 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1153 21:24:38.315042 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1154 21:24:38.389250 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1155 21:24:38.459202 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1156 21:24:38.528441 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1157 21:24:38.596282 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1158 21:24:38.668484 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1159 21:24:38.736594 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1160 21:24:38.805756 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1161 21:24:38.872443 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1162 21:24:38.950256 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1163 21:24:39.021035 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1164 21:24:39.087956 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1165 21:24:39.158303 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1166 21:24:39.230193 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1167 21:24:39.300653 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1168 21:24:39.322318 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1169 21:24:39.346019 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1170 21:24:39.362630 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1171 21:24:39.392706 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1172 21:24:39.415554 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1173 21:24:39.431527 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1174 21:24:39.459683 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1175 21:24:39.482927 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1176 21:24:39.583439 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1177 21:24:39.600589 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1178 21:24:39.625928 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1179 21:24:39.654374 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1180 21:24:39.746834 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1181 21:24:39.827354 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1182 21:24:39.894241 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1183 21:24:39.967271 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1184 21:24:40.036775 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1185 21:24:40.104879 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1186 21:24:40.175595 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1187 21:24:40.237487 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1188 21:24:40.314220 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1189 21:24:40.381106 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1190 21:24:40.451509 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1191 21:24:40.521094 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1192 21:24:40.589813 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1193 21:24:40.665927 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1194 21:24:40.731975 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1195 21:24:40.807195 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1196 21:24:40.827490 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1197 21:24:40.890038 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1198 21:24:40.963020 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1199 21:24:41.032949 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1200 21:24:41.052690 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1201 21:24:41.121813 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1202 21:24:41.145114 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1203 21:24:41.208482 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1204 21:24:41.233645 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1205 21:24:41.259124 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1206 21:24:41.282830 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1207 21:24:41.300273 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1208 21:24:41.329436 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1209 21:24:41.352836 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1210 21:24:41.371245 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1211 21:24:41.400891 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1212 21:24:41.415788 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1213 21:24:41.485449 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1214 21:24:41.558138 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1215 21:24:41.578973 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1216 21:24:41.647647 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1217 21:24:41.717099 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1218 21:24:41.805013 # not ok 145 /ocp/interconnect@47c00000
1219 21:24:41.872703 # not ok 146 /ocp/interconnect@47c00000/segment@0
1220 21:24:41.897142 # ok 147 /ocp/interconnect@48000000
1221 21:24:41.920373 # ok 148 /ocp/interconnect@48000000/segment@0
1222 21:24:41.943598 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1223 21:24:41.960791 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1224 21:24:41.990379 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1225 21:24:42.015473 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1226 21:24:42.030064 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1227 21:24:42.053280 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1228 21:24:42.082834 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1229 21:24:42.142060 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1230 21:24:42.215202 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1231 21:24:42.241903 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1232 21:24:42.257689 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1233 21:24:42.280381 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1234 21:24:42.302064 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1235 21:24:42.330202 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1236 21:24:42.355087 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1237 21:24:42.369280 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1238 21:24:42.394855 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1239 21:24:42.419272 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1240 21:24:42.442850 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1241 21:24:42.462941 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1242 21:24:42.489590 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1243 21:24:42.507908 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1244 21:24:42.533717 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1245 21:24:42.558177 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1246 21:24:42.573948 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1247 21:24:42.602947 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1248 21:24:42.619789 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1249 21:24:42.648279 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1250 21:24:42.670878 # ok 177 /ocp/interconnect@48000000/segment@100000
1251 21:24:42.687809 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1252 21:24:42.713810 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1253 21:24:42.786087 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1254 21:24:42.857253 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1255 21:24:42.923473 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1256 21:24:42.987172 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1257 21:24:43.012377 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1258 21:24:43.035547 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1259 21:24:43.051649 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1260 21:24:43.082661 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1261 21:24:43.097392 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1262 21:24:43.126071 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1263 21:24:43.143476 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1264 21:24:43.171210 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1265 21:24:43.189722 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1266 21:24:43.212706 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1267 21:24:43.241174 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1268 21:24:43.262069 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1269 21:24:43.276590 # ok 196 /ocp/interconnect@48000000/segment@200000
1270 21:24:43.300398 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1271 21:24:43.373343 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1272 21:24:43.393609 # ok 199 /ocp/interconnect@48000000/segment@300000
1273 21:24:43.419033 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1274 21:24:43.443066 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1275 21:24:43.461134 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1276 21:24:43.488551 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1277 21:24:43.510628 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1278 21:24:43.533601 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1279 21:24:43.596508 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1280 21:24:43.613652 # ok 207 /ocp/interconnect@4a000000
1281 21:24:43.641649 # ok 208 /ocp/interconnect@4a000000/segment@0
1282 21:24:43.660663 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1283 21:24:43.693069 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1284 21:24:43.717565 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1285 21:24:43.736464 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1286 21:24:43.806522 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1287 21:24:43.907096 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1288 21:24:43.975615 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1289 21:24:44.081995 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1290 21:24:44.142960 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1291 21:24:44.215810 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1292 21:24:44.309331 # not ok 219 /ocp/interconnect@4b140000
1293 21:24:44.374131 # not ok 220 /ocp/interconnect@4b140000/segment@0
1294 21:24:44.448792 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1295 21:24:44.464393 # ok 222 /ocp/target-module@40300000
1296 21:24:44.491155 # ok 223 /ocp/target-module@40300000/sram@0
1297 21:24:44.562464 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1298 21:24:44.633891 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1299 21:24:44.647168 # ok 226 /ocp/target-module@47400000
1300 21:24:44.678693 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1301 21:24:44.693113 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1302 21:24:44.720547 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1303 21:24:44.740821 # ok 230 /ocp/target-module@47400000/usb@1400
1304 21:24:44.758087 # ok 231 /ocp/target-module@47400000/usb@1800
1305 21:24:44.779768 # ok 232 /ocp/target-module@47810000
1306 21:24:44.804748 # ok 233 /ocp/target-module@49000000
1307 21:24:44.822051 # ok 234 /ocp/target-module@49000000/dma@0
1308 21:24:44.846609 # ok 235 /ocp/target-module@49800000
1309 21:24:44.869337 # ok 236 /ocp/target-module@49800000/dma@0
1310 21:24:44.889010 # ok 237 /ocp/target-module@49900000
1311 21:24:44.910066 # ok 238 /ocp/target-module@49900000/dma@0
1312 21:24:44.930667 # ok 239 /ocp/target-module@49a00000
1313 21:24:44.956529 # ok 240 /ocp/target-module@49a00000/dma@0
1314 21:24:44.976873 # ok 241 /ocp/target-module@4c000000
1315 21:24:45.312398 # not ok 242 /ocp/target-module@4c000000/emif@0
1316 21:24:45.312704 # ok 243 /ocp/target-module@50000000
1317 21:24:45.312873 # ok 244 /ocp/target-module@53100000
1318 21:24:45.313017 # not ok 245 /ocp/target-module@53100000/sham@0
1319 21:24:45.313157 # ok 246 /ocp/target-module@53500000
1320 21:24:45.315566 # not ok 247 /ocp/target-module@53500000/aes@0
1321 21:24:45.315790 # ok 248 /ocp/target-module@56000000
1322 21:24:45.365570 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1323 21:24:45.427918 # ok 250 /opp-table # SKIP
1324 21:24:45.498024 # ok 251 /soc # SKIP
1325 21:24:45.516160 # ok 252 /sound
1326 21:24:45.538832 # ok 253 /target-module@4b000000
1327 21:24:45.562236 # ok 254 /target-module@4b000000/target-module@140000
1328 21:24:45.582697 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1329 21:24:45.590671 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1330 21:24:45.597197 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1331 21:24:47.815420 dt_test_unprobed_devices_sh_ skip
1332 21:24:47.820956 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1333 21:24:47.826461 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1334 21:24:47.826709 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1335 21:24:47.835459 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1336 21:24:47.835755 dt_test_unprobed_devices_sh_fixedregulator0 pass
1337 21:24:47.841010 dt_test_unprobed_devices_sh_leds pass
1338 21:24:47.847241 dt_test_unprobed_devices_sh_ocp pass
1339 21:24:47.852341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1340 21:24:47.857850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1341 21:24:47.863471 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1342 21:24:47.869188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1343 21:24:47.880332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1344 21:24:47.885964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1345 21:24:47.891694 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1346 21:24:47.902732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1347 21:24:47.908497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1348 21:24:47.919417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1349 21:24:47.930787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1350 21:24:47.942028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1351 21:24:47.953157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1352 21:24:47.959244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1353 21:24:47.969940 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1354 21:24:47.981078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1355 21:24:47.992238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1356 21:24:48.003761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1357 21:24:48.009188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1358 21:24:48.020418 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1359 21:24:48.031680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1360 21:24:48.042601 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1361 21:24:48.053962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1362 21:24:48.059473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1363 21:24:48.070765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1364 21:24:48.081907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1365 21:24:48.093523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1366 21:24:48.098791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1367 21:24:48.109904 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1368 21:24:48.120939 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1369 21:24:48.132233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1370 21:24:48.143588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1371 21:24:48.154564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1372 21:24:48.165830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1373 21:24:48.177307 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1374 21:24:48.188269 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1375 21:24:48.199254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1376 21:24:48.210782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1377 21:24:48.221602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1378 21:24:48.232874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1379 21:24:48.244170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1380 21:24:48.255644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1381 21:24:48.266711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1382 21:24:48.277563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1383 21:24:48.288718 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1384 21:24:48.299941 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1385 21:24:48.311500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1386 21:24:48.322382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1387 21:24:48.333801 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1388 21:24:48.344863 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1389 21:24:48.350682 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1390 21:24:48.361651 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1391 21:24:48.372921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1392 21:24:48.383965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1393 21:24:48.395044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1394 21:24:48.406746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1395 21:24:48.417748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1396 21:24:48.428891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1397 21:24:48.439945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1398 21:24:48.451044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1399 21:24:48.456777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1400 21:24:48.467869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1401 21:24:48.479058 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1402 21:24:48.490233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1403 21:24:48.501519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1404 21:24:48.512615 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1405 21:24:48.523780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1406 21:24:48.535095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1407 21:24:48.546598 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1408 21:24:48.557520 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1409 21:24:48.568631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1410 21:24:48.580044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1411 21:24:48.591504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1412 21:24:48.602376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1413 21:24:48.613585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1414 21:24:48.624858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1415 21:24:48.630389 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1416 21:24:48.641584 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1417 21:24:48.652856 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1418 21:24:48.664147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1419 21:24:48.675258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1420 21:24:48.686524 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1421 21:24:48.697690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1422 21:24:48.708885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1423 21:24:48.720076 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1424 21:24:48.731387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1425 21:24:48.742619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1426 21:24:48.753931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1427 21:24:48.759723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1428 21:24:48.770867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1429 21:24:48.781932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1430 21:24:48.787667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1431 21:24:48.798544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1432 21:24:48.804234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1433 21:24:48.815439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1434 21:24:48.826458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1435 21:24:48.832157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1436 21:24:48.843272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1437 21:24:48.854928 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1438 21:24:48.865769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1439 21:24:48.876843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1440 21:24:48.888171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1441 21:24:48.899222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1442 21:24:48.916122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1443 21:24:48.927288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1444 21:24:48.938870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1445 21:24:48.949710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1446 21:24:48.960835 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1447 21:24:48.972185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1448 21:24:48.983298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1449 21:24:48.994453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1450 21:24:49.011591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1451 21:24:49.022789 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1452 21:24:49.039475 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1453 21:24:49.050833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1454 21:24:49.056179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1455 21:24:49.067242 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1456 21:24:49.072808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1457 21:24:49.084095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1458 21:24:49.095539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1459 21:24:49.100915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1460 21:24:49.111980 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1461 21:24:49.117509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1462 21:24:49.128826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1463 21:24:49.134696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1464 21:24:49.145672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1465 21:24:49.151166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1466 21:24:49.162347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1467 21:24:49.173572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1468 21:24:49.179545 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1469 21:24:49.190419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1470 21:24:49.201483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1471 21:24:49.212676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1472 21:24:49.218299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1473 21:24:49.229454 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1474 21:24:49.235183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1475 21:24:49.240627 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1476 21:24:49.251846 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1477 21:24:49.252137 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1478 21:24:49.263251 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1479 21:24:49.269026 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1480 21:24:49.274539 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1481 21:24:49.285521 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1482 21:24:49.291273 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1483 21:24:49.302253 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1484 21:24:49.307828 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1485 21:24:49.319035 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1486 21:24:49.324610 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1487 21:24:49.330223 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1488 21:24:49.341459 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1489 21:24:49.346997 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1490 21:24:49.358308 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1491 21:24:49.364145 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1492 21:24:49.375110 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1493 21:24:49.380510 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1494 21:24:49.391703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1495 21:24:49.397287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1496 21:24:49.408599 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1497 21:24:49.414140 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1498 21:24:49.425272 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1499 21:24:49.431005 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1500 21:24:49.436503 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1501 21:24:49.448092 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1502 21:24:49.453323 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1503 21:24:49.464447 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1504 21:24:49.470212 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1505 21:24:49.481272 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1506 21:24:49.486883 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1507 21:24:49.492810 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1508 21:24:49.503766 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1509 21:24:49.514856 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1510 21:24:49.520552 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1511 21:24:49.531805 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1512 21:24:49.542885 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1513 21:24:49.554122 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1514 21:24:49.559758 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1515 21:24:49.570982 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1516 21:24:49.576563 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1517 21:24:49.587620 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1518 21:24:49.593277 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1519 21:24:49.604750 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1520 21:24:49.610144 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1521 21:24:49.621385 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1522 21:24:49.626847 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1523 21:24:49.638138 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1524 21:24:49.643625 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1525 21:24:49.654937 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1526 21:24:49.660409 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1527 21:24:49.671492 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1528 21:24:49.677292 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1529 21:24:49.683061 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1530 21:24:49.694466 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1531 21:24:49.699959 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1532 21:24:49.711058 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1533 21:24:49.716380 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1534 21:24:49.727589 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1535 21:24:49.733275 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1536 21:24:49.744460 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1537 21:24:49.749998 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1538 21:24:49.755444 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1539 21:24:49.761014 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1540 21:24:49.772612 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1541 21:24:49.777867 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1542 21:24:49.789272 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1543 21:24:49.794711 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1544 21:24:49.805767 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1545 21:24:49.817069 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1546 21:24:49.828312 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1547 21:24:49.839516 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1548 21:24:49.845050 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1549 21:24:49.850693 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1550 21:24:49.856346 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1551 21:24:49.861854 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1552 21:24:49.867370 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1553 21:24:49.872998 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1554 21:24:49.884310 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1555 21:24:49.889724 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1556 21:24:49.895524 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1557 21:24:49.901200 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1558 21:24:49.906591 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1559 21:24:49.917975 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1560 21:24:49.923408 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1561 21:24:49.929146 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1562 21:24:49.934592 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1563 21:24:49.940307 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1564 21:24:49.945973 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1565 21:24:49.951490 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1566 21:24:49.957081 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1567 21:24:49.962707 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1568 21:24:49.968316 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1569 21:24:49.973983 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1570 21:24:49.979381 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1571 21:24:49.984992 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1572 21:24:49.990583 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1573 21:24:49.996233 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1574 21:24:50.001761 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1575 21:24:50.007732 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1576 21:24:50.013107 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1577 21:24:50.018644 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1578 21:24:50.024318 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1579 21:24:50.029880 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1580 21:24:50.030116 dt_test_unprobed_devices_sh_opp-table skip
1581 21:24:50.035800 dt_test_unprobed_devices_sh_soc skip
1582 21:24:50.041189 dt_test_unprobed_devices_sh_sound pass
1583 21:24:50.041504 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1584 21:24:50.052180 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1585 21:24:50.057871 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1586 21:24:50.063386 dt_test_unprobed_devices_sh fail
1587 21:24:50.063677 + ../../utils/send-to-lava.sh ./output/result.txt
1588 21:24:50.070977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1589 21:24:50.071500 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1591 21:24:50.131133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1592 21:24:50.131654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1594 21:24:50.231172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1595 21:24:50.231668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1597 21:24:50.328671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1598 21:24:50.329020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1600 21:24:50.428696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1601 21:24:50.429228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1603 21:24:50.534333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1604 21:24:50.534913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1606 21:24:50.640679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1607 21:24:50.641286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1609 21:24:50.750453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1610 21:24:50.751057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1612 21:24:50.857099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1613 21:24:50.857685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1615 21:24:50.960638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1616 21:24:50.961141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1618 21:24:51.063355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1619 21:24:51.063942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1621 21:24:51.166067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1622 21:24:51.166593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1624 21:24:51.273673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1625 21:24:51.274270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1627 21:24:51.381686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1628 21:24:51.382238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1630 21:24:51.479973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1631 21:24:51.480490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1633 21:24:51.590681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1634 21:24:51.591203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1636 21:24:51.696031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1637 21:24:51.696555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1639 21:24:51.803624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1640 21:24:51.804231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1642 21:24:51.906954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1643 21:24:51.907476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1645 21:24:52.020212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1646 21:24:52.020740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1648 21:24:52.120685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1649 21:24:52.121210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1651 21:24:52.226085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1652 21:24:52.226622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1654 21:24:52.338661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1655 21:24:52.339245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1657 21:24:52.444723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1658 21:24:52.445241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1660 21:24:52.554098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1661 21:24:52.554614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1663 21:24:52.655074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1664 21:24:52.655638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1666 21:24:52.749670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1667 21:24:52.750160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1669 21:24:52.856967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1670 21:24:52.857434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1672 21:24:52.962178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1673 21:24:52.962631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1675 21:24:53.065603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1676 21:24:53.066096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1678 21:24:53.167009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1679 21:24:53.167479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1681 21:24:53.269321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1682 21:24:53.269808 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1684 21:24:53.371909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1685 21:24:53.372346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1687 21:24:53.470343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1688 21:24:53.470844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1690 21:24:53.572943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1691 21:24:53.573549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1693 21:24:53.677364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1694 21:24:53.677944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1696 21:24:53.779382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1697 21:24:53.779898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1699 21:24:53.887461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1700 21:24:53.888072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1702 21:24:53.991775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1703 21:24:53.992299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1705 21:24:54.097099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1706 21:24:54.097615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1708 21:24:54.205681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1709 21:24:54.206252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1711 21:24:54.319041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1712 21:24:54.319543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1714 21:24:54.430017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1715 21:24:54.430562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1717 21:24:54.544524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1718 21:24:54.545052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1720 21:24:54.656224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1721 21:24:54.656757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1723 21:24:54.778214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1724 21:24:54.778749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1726 21:24:54.882255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1727 21:24:54.882805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1729 21:24:54.987990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1730 21:24:54.988513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1732 21:24:55.091303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1733 21:24:55.091824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1735 21:24:55.195389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1736 21:24:55.195912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1738 21:24:55.297404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1739 21:24:55.297928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1741 21:24:55.400344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1742 21:24:55.400871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1744 21:24:55.507843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1745 21:24:55.508364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1747 21:24:55.610752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1748 21:24:55.611277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1750 21:24:55.718709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1751 21:24:55.719231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1753 21:24:55.825060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1754 21:24:55.825581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1756 21:24:55.929197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1757 21:24:55.929801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1759 21:24:56.034087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1760 21:24:56.034620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1762 21:24:56.138723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1763 21:24:56.139313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1765 21:24:56.244910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1766 21:24:56.245431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1768 21:24:56.349737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1769 21:24:56.350392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1771 21:24:56.455231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1772 21:24:56.455762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1774 21:24:56.555235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1775 21:24:56.555760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1777 21:24:56.659066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1778 21:24:56.659648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1780 21:24:56.768629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1781 21:24:56.769217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1783 21:24:56.873300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1784 21:24:56.873857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1786 21:24:56.976742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1787 21:24:56.977283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1789 21:24:57.082389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1790 21:24:57.082977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1792 21:24:57.188888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1793 21:24:57.189472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1795 21:24:57.295334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1796 21:24:57.295856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1798 21:24:57.398962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1799 21:24:57.399498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1801 21:24:57.502863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1802 21:24:57.503364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1804 21:24:57.615310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1805 21:24:57.615831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1807 21:24:57.718119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1808 21:24:57.718693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1810 21:24:57.821616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1811 21:24:57.822188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1813 21:24:57.928036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1814 21:24:57.928630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1816 21:24:58.028785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1817 21:24:58.029305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1819 21:24:58.132681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1820 21:24:58.133196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1822 21:24:58.236508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1823 21:24:58.237027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1825 21:24:58.339412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1826 21:24:58.339955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1828 21:24:58.443607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1829 21:24:58.444129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1831 21:24:58.551528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1832 21:24:58.552051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1834 21:24:58.657011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1835 21:24:58.657536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1837 21:24:58.759352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1838 21:24:58.759869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1840 21:24:58.867140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1841 21:24:58.867663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1843 21:24:58.971333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1844 21:24:58.971859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1846 21:24:59.080237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1847 21:24:59.080759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1849 21:24:59.186561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1850 21:24:59.187139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1852 21:24:59.290087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1853 21:24:59.290682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1855 21:24:59.396109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1856 21:24:59.396629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1858 21:24:59.502111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1859 21:24:59.502639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1861 21:24:59.602106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1862 21:24:59.602639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1864 21:24:59.708776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1865 21:24:59.709295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1867 21:24:59.811868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1868 21:24:59.812389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1870 21:24:59.918258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1871 21:24:59.918778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1873 21:25:00.021972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1874 21:25:00.022481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1876 21:25:00.123924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1877 21:25:00.124444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1879 21:25:00.229416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1880 21:25:00.229924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1882 21:25:00.337638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1883 21:25:00.338245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1885 21:25:00.446456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1886 21:25:00.446976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1888 21:25:00.551196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1889 21:25:00.551698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1891 21:25:00.670763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1892 21:25:00.671294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1894 21:25:00.776733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1895 21:25:00.777258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1897 21:25:00.895049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1898 21:25:00.895546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1900 21:25:01.004689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1901 21:25:01.005274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1903 21:25:01.109386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1904 21:25:01.109987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1906 21:25:01.216523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1907 21:25:01.217054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1909 21:25:01.323761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1910 21:25:01.324287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1912 21:25:01.430692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1913 21:25:01.431233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1915 21:25:01.538192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1916 21:25:01.538731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1918 21:25:01.649065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1919 21:25:01.649594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1921 21:25:01.758158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1922 21:25:01.758773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1924 21:25:01.872630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1925 21:25:01.873228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1927 21:25:01.978757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1928 21:25:01.979283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1930 21:25:02.083802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1931 21:25:02.084320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1933 21:25:02.190090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1934 21:25:02.190623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1936 21:25:02.297963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1937 21:25:02.298544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1939 21:25:02.400770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1940 21:25:02.401293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1942 21:25:02.508096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1943 21:25:02.508615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1945 21:25:02.611444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1946 21:25:02.611999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1948 21:25:02.710794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1950 21:25:02.713900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1951 21:25:02.810762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1953 21:25:02.813685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1954 21:25:02.905890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1956 21:25:02.909023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1957 21:25:03.007570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1958 21:25:03.008222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1960 21:25:03.103241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1961 21:25:03.103768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1963 21:25:03.206201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1964 21:25:03.206700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1966 21:25:03.307594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1967 21:25:03.308112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1969 21:25:03.413815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1970 21:25:03.414383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1972 21:25:03.517819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1973 21:25:03.518333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1975 21:25:03.622197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1976 21:25:03.622807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1978 21:25:03.723785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1979 21:25:03.724320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1981 21:25:03.825753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1982 21:25:03.826309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1984 21:25:03.931942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1985 21:25:03.932548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1987 21:25:04.042592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1988 21:25:04.043087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1990 21:25:04.145728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1991 21:25:04.146395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1993 21:25:04.246730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1994 21:25:04.247236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1996 21:25:04.350569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1997 21:25:04.351106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1999 21:25:04.454295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2000 21:25:04.454887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2002 21:25:04.564316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2003 21:25:04.564847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2005 21:25:04.668398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2006 21:25:04.668936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2008 21:25:04.776498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2009 21:25:04.777079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2011 21:25:04.882617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2012 21:25:04.883142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2014 21:25:04.987064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2015 21:25:04.987550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2017 21:25:05.091938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2018 21:25:05.092463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2020 21:25:05.192665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2021 21:25:05.193183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2023 21:25:05.290292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2024 21:25:05.290760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2026 21:25:05.397842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2027 21:25:05.398373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2029 21:25:05.501110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2030 21:25:05.501621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2032 21:25:05.613894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2033 21:25:05.614471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2035 21:25:05.725226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2036 21:25:05.725878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2038 21:25:05.827528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2039 21:25:05.828048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2041 21:25:05.935295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2042 21:25:05.935825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2044 21:25:06.036636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2045 21:25:06.037129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2047 21:25:06.145771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2048 21:25:06.146316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2050 21:25:06.252613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2051 21:25:06.253096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2053 21:25:06.354100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2054 21:25:06.354623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2056 21:25:06.458934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2057 21:25:06.459460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2059 21:25:06.566646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2060 21:25:06.567169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2062 21:25:06.681853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2063 21:25:06.682338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2065 21:25:06.787281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2066 21:25:06.787802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2068 21:25:06.893867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2069 21:25:06.894370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2071 21:25:07.000831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2072 21:25:07.001405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2074 21:25:07.104817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2075 21:25:07.105372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2077 21:25:07.209311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2078 21:25:07.209882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2080 21:25:07.312722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2081 21:25:07.313315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2083 21:25:07.415946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2084 21:25:07.416432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2086 21:25:07.523082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2087 21:25:07.523605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2089 21:25:07.634190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2090 21:25:07.634816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2092 21:25:07.739878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2093 21:25:07.740416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2095 21:25:07.852362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2096 21:25:07.852883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2098 21:25:07.966121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2099 21:25:07.966678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2101 21:25:08.076859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2102 21:25:08.077415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2104 21:25:08.189364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2105 21:25:08.189857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2107 21:25:08.294898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2108 21:25:08.295380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2110 21:25:08.406065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2111 21:25:08.406500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2113 21:25:08.513922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2114 21:25:08.514351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2116 21:25:08.615624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2117 21:25:08.616165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2119 21:25:08.716564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2120 21:25:08.717081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2122 21:25:08.823207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2123 21:25:08.823721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2125 21:25:08.931636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2126 21:25:08.932177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2128 21:25:09.033732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2129 21:25:09.034280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2131 21:25:09.136616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2132 21:25:09.137140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2134 21:25:09.242943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2135 21:25:09.243450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2137 21:25:09.348776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2138 21:25:09.349281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2140 21:25:09.455369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2141 21:25:09.456001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2143 21:25:09.573370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2144 21:25:09.573975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2146 21:25:09.679213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2147 21:25:09.679734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2149 21:25:09.792941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2150 21:25:09.793598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2152 21:25:09.902863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2153 21:25:09.903388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2155 21:25:10.013933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2156 21:25:10.014453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2158 21:25:10.124411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2159 21:25:10.124939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2161 21:25:10.232604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2162 21:25:10.233085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2164 21:25:10.346359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2165 21:25:10.346924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2167 21:25:10.456896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2168 21:25:10.457397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2170 21:25:10.562358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2171 21:25:10.562933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2173 21:25:10.664536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2174 21:25:10.665052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2176 21:25:10.773228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2177 21:25:10.773754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2179 21:25:10.890656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2180 21:25:10.891176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2182 21:25:10.998791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2183 21:25:10.999316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2185 21:25:11.098897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2186 21:25:11.099419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2188 21:25:11.202596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2189 21:25:11.203085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2191 21:25:11.303547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2192 21:25:11.304139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2194 21:25:11.406271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2195 21:25:11.406766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2197 21:25:11.515855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2198 21:25:11.516366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2200 21:25:11.623406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2201 21:25:11.623931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2203 21:25:11.731837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2204 21:25:11.732354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2206 21:25:11.834686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2207 21:25:11.835120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2209 21:25:11.925602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2210 21:25:11.925973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2212 21:25:12.026780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2213 21:25:12.027183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2215 21:25:12.132030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2216 21:25:12.132454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2218 21:25:12.234960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2219 21:25:12.235409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2221 21:25:12.417752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2222 21:25:12.418180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2224 21:25:12.521674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2225 21:25:12.522115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2227 21:25:12.620630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2228 21:25:12.621060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2230 21:25:12.720004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2231 21:25:12.720414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2233 21:25:12.819392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2234 21:25:12.819821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2236 21:25:12.919806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2237 21:25:12.920224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2239 21:25:13.019552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2240 21:25:13.019966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2242 21:25:13.116263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2243 21:25:13.116683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2245 21:25:13.211174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2246 21:25:13.211595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2248 21:25:13.312017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2249 21:25:13.312435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2251 21:25:13.410881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2252 21:25:13.411302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2254 21:25:13.509314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2255 21:25:13.509730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2257 21:25:13.604404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2258 21:25:13.604861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2260 21:25:13.710163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2261 21:25:13.710601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2263 21:25:13.808898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2265 21:25:13.812018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2266 21:25:13.909661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2267 21:25:13.910109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2269 21:25:14.008982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2270 21:25:14.009472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2272 21:25:14.113298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2273 21:25:14.113801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2275 21:25:14.224410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2276 21:25:14.224935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2278 21:25:14.329858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2279 21:25:14.330388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2281 21:25:14.436963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2282 21:25:14.437448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2284 21:25:14.543742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2285 21:25:14.544252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2287 21:25:14.654327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2288 21:25:14.654853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2290 21:25:14.771477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2291 21:25:14.772005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2293 21:25:14.876381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2294 21:25:14.876912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2296 21:25:14.986120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2297 21:25:14.986648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2299 21:25:15.092477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2300 21:25:15.093012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2302 21:25:15.205088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2303 21:25:15.205579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2305 21:25:15.312746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2306 21:25:15.313267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2308 21:25:15.426054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2309 21:25:15.426569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2311 21:25:15.533852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2312 21:25:15.534437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2314 21:25:15.643655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2315 21:25:15.644181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2317 21:25:15.759360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2318 21:25:15.759885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2320 21:25:15.865471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2321 21:25:15.866089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2323 21:25:15.970623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2324 21:25:15.971131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2326 21:25:16.077434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2327 21:25:16.077934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2329 21:25:16.183777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2330 21:25:16.184297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2332 21:25:16.291405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2333 21:25:16.291937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2335 21:25:16.402936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2336 21:25:16.403429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2338 21:25:16.519762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2339 21:25:16.520283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2341 21:25:16.621939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2342 21:25:16.622465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2344 21:25:16.727435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2345 21:25:16.727952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2347 21:25:16.830816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2348 21:25:16.831360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2350 21:25:16.939594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2351 21:25:16.940120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2353 21:25:17.045965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2354 21:25:17.046555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2356 21:25:17.149483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2357 21:25:17.149779 + set +x
2358 21:25:17.150201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2360 21:25:17.153556 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 680152_1.6.2.4.5>
2361 21:25:17.154070 Received signal: <ENDRUN> 1_kselftest-dt 680152_1.6.2.4.5
2362 21:25:17.154265 Ending use of test pattern.
2363 21:25:17.154428 Ending test lava.1_kselftest-dt (680152_1.6.2.4.5), duration 136.96
2365 21:25:17.165493 <LAVA_TEST_RUNNER EXIT>
2366 21:25:17.165975 ok: lava_test_shell seems to have completed
2367 21:25:17.170017 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2368 21:25:17.170853 end: 3.1 lava-test-shell (duration 00:02:18) [common]
2369 21:25:17.171076 end: 3 lava-test-retry (duration 00:02:18) [common]
2370 21:25:17.171296 start: 4 finalize (timeout 00:04:13) [common]
2371 21:25:17.171517 start: 4.1 power-off (timeout 00:00:30) [common]
2372 21:25:17.171878 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2373 21:25:17.187917 >> OK - accepted request
2374 21:25:17.189412 Returned 0 in 0 seconds
2375 21:25:17.290416 end: 4.1 power-off (duration 00:00:00) [common]
2377 21:25:17.291324 start: 4.2 read-feedback (timeout 00:04:13) [common]
2378 21:25:17.291787 Listened to connection for namespace 'common' for up to 1s
2379 21:25:17.292184 Listened to connection for namespace 'common' for up to 1s
2380 21:25:18.292965 Finalising connection for namespace 'common'
2381 21:25:18.293351 Disconnecting from shell: Finalise
2382 21:25:18.293569 / #
2383 21:25:18.394434 end: 4.2 read-feedback (duration 00:00:01) [common]
2384 21:25:18.394873 end: 4 finalize (duration 00:00:01) [common]
2385 21:25:18.395166 Cleaning after the job
2386 21:25:18.395431 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/ramdisk
2387 21:25:18.400311 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/kernel
2388 21:25:18.402815 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/dtb
2389 21:25:18.403222 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/nfsrootfs
2390 21:25:18.444755 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680152/tftp-deploy-x16teunw/modules
2391 21:25:18.448625 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/680152
2392 21:25:18.992766 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/680152
2393 21:25:18.992991 Job finished correctly