Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 4
1 21:31:00.954302 lava-dispatcher, installed at version: 2024.01
2 21:31:00.955246 start: 0 validate
3 21:31:00.955828 Start time: 2024-08-30 21:31:00.955791+00:00 (UTC)
4 21:31:00.956514 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:31:00.957176 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 21:31:00.999666 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:31:01.000244 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-207-gfb24560f31f9d%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 21:31:01.035938 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:31:01.036619 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-207-gfb24560f31f9d%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:31:01.070526 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:31:01.071070 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 21:31:01.103541 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 21:31:01.104116 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-207-gfb24560f31f9d%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 21:31:01.143004 validate duration: 0.19
16 21:31:01.143847 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 21:31:01.144190 start: 1.1 download-retry (timeout 00:10:00) [common]
18 21:31:01.144498 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 21:31:01.145145 Not decompressing ramdisk as can be used compressed.
20 21:31:01.145623 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 21:31:01.145899 saving as /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/ramdisk/initrd.cpio.gz
22 21:31:01.146165 total size: 5628169 (5 MB)
23 21:31:01.185116 progress 0 % (0 MB)
24 21:31:01.190704 progress 5 % (0 MB)
25 21:31:01.198622 progress 10 % (0 MB)
26 21:31:01.204955 progress 15 % (0 MB)
27 21:31:01.209072 progress 20 % (1 MB)
28 21:31:01.212739 progress 25 % (1 MB)
29 21:31:01.216832 progress 30 % (1 MB)
30 21:31:01.220954 progress 35 % (1 MB)
31 21:31:01.224631 progress 40 % (2 MB)
32 21:31:01.228652 progress 45 % (2 MB)
33 21:31:01.232285 progress 50 % (2 MB)
34 21:31:01.236376 progress 55 % (2 MB)
35 21:31:01.240369 progress 60 % (3 MB)
36 21:31:01.243961 progress 65 % (3 MB)
37 21:31:01.248069 progress 70 % (3 MB)
38 21:31:01.251680 progress 75 % (4 MB)
39 21:31:01.255670 progress 80 % (4 MB)
40 21:31:01.259287 progress 85 % (4 MB)
41 21:31:01.263311 progress 90 % (4 MB)
42 21:31:01.267028 progress 95 % (5 MB)
43 21:31:01.270333 progress 100 % (5 MB)
44 21:31:01.270992 5 MB downloaded in 0.12 s (43.01 MB/s)
45 21:31:01.271525 end: 1.1.1 http-download (duration 00:00:00) [common]
47 21:31:01.272479 end: 1.1 download-retry (duration 00:00:00) [common]
48 21:31:01.272785 start: 1.2 download-retry (timeout 00:10:00) [common]
49 21:31:01.273060 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 21:31:01.273531 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/clang-16/kernel/Image
51 21:31:01.273783 saving as /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/kernel/Image
52 21:31:01.273991 total size: 37409280 (35 MB)
53 21:31:01.274198 No compression specified
54 21:31:01.312289 progress 0 % (0 MB)
55 21:31:01.336098 progress 5 % (1 MB)
56 21:31:01.359974 progress 10 % (3 MB)
57 21:31:01.383013 progress 15 % (5 MB)
58 21:31:01.406242 progress 20 % (7 MB)
59 21:31:01.429418 progress 25 % (8 MB)
60 21:31:01.452779 progress 30 % (10 MB)
61 21:31:01.476588 progress 35 % (12 MB)
62 21:31:01.499922 progress 40 % (14 MB)
63 21:31:01.522940 progress 45 % (16 MB)
64 21:31:01.545969 progress 50 % (17 MB)
65 21:31:01.569799 progress 55 % (19 MB)
66 21:31:01.592956 progress 60 % (21 MB)
67 21:31:01.616789 progress 65 % (23 MB)
68 21:31:01.640316 progress 70 % (25 MB)
69 21:31:01.663724 progress 75 % (26 MB)
70 21:31:01.687686 progress 80 % (28 MB)
71 21:31:01.710970 progress 85 % (30 MB)
72 21:31:01.734058 progress 90 % (32 MB)
73 21:31:01.757203 progress 95 % (33 MB)
74 21:31:01.780452 progress 100 % (35 MB)
75 21:31:01.781148 35 MB downloaded in 0.51 s (70.35 MB/s)
76 21:31:01.781625 end: 1.2.1 http-download (duration 00:00:01) [common]
78 21:31:01.782445 end: 1.2 download-retry (duration 00:00:01) [common]
79 21:31:01.782720 start: 1.3 download-retry (timeout 00:09:59) [common]
80 21:31:01.782984 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 21:31:01.783437 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 21:31:01.783712 saving as /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/dtb/meson-g12b-a311d-libretech-cc.dtb
83 21:31:01.783918 total size: 54667 (0 MB)
84 21:31:01.784150 No compression specified
85 21:31:01.827398 progress 59 % (0 MB)
86 21:31:01.828304 progress 100 % (0 MB)
87 21:31:01.828870 0 MB downloaded in 0.04 s (1.16 MB/s)
88 21:31:01.829362 end: 1.3.1 http-download (duration 00:00:00) [common]
90 21:31:01.830216 end: 1.3 download-retry (duration 00:00:00) [common]
91 21:31:01.830514 start: 1.4 download-retry (timeout 00:09:59) [common]
92 21:31:01.830783 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 21:31:01.831240 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 21:31:01.831483 saving as /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/nfsrootfs/full.rootfs.tar
95 21:31:01.831683 total size: 120894716 (115 MB)
96 21:31:01.831889 Using unxz to decompress xz
97 21:31:01.864899 progress 0 % (0 MB)
98 21:31:02.677004 progress 5 % (5 MB)
99 21:31:03.541384 progress 10 % (11 MB)
100 21:31:04.372810 progress 15 % (17 MB)
101 21:31:05.165268 progress 20 % (23 MB)
102 21:31:05.760963 progress 25 % (28 MB)
103 21:31:06.587864 progress 30 % (34 MB)
104 21:31:07.383959 progress 35 % (40 MB)
105 21:31:07.730678 progress 40 % (46 MB)
106 21:31:08.109605 progress 45 % (51 MB)
107 21:31:08.883419 progress 50 % (57 MB)
108 21:31:09.876442 progress 55 % (63 MB)
109 21:31:10.714804 progress 60 % (69 MB)
110 21:31:11.484022 progress 65 % (74 MB)
111 21:31:12.280020 progress 70 % (80 MB)
112 21:31:13.127758 progress 75 % (86 MB)
113 21:31:13.920099 progress 80 % (92 MB)
114 21:31:14.686093 progress 85 % (98 MB)
115 21:31:15.547584 progress 90 % (103 MB)
116 21:31:16.332372 progress 95 % (109 MB)
117 21:31:17.168657 progress 100 % (115 MB)
118 21:31:17.182957 115 MB downloaded in 15.35 s (7.51 MB/s)
119 21:31:17.183673 end: 1.4.1 http-download (duration 00:00:15) [common]
121 21:31:17.184794 end: 1.4 download-retry (duration 00:00:15) [common]
122 21:31:17.185146 start: 1.5 download-retry (timeout 00:09:44) [common]
123 21:31:17.185485 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 21:31:17.186074 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/clang-16/modules.tar.xz
125 21:31:17.186393 saving as /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/modules/modules.tar
126 21:31:17.186650 total size: 11632600 (11 MB)
127 21:31:17.186912 Using unxz to decompress xz
128 21:31:17.226682 progress 0 % (0 MB)
129 21:31:17.298857 progress 5 % (0 MB)
130 21:31:17.379859 progress 10 % (1 MB)
131 21:31:17.471243 progress 15 % (1 MB)
132 21:31:17.549505 progress 20 % (2 MB)
133 21:31:17.630323 progress 25 % (2 MB)
134 21:31:17.728638 progress 30 % (3 MB)
135 21:31:17.823714 progress 35 % (3 MB)
136 21:31:17.914311 progress 40 % (4 MB)
137 21:31:18.006992 progress 45 % (5 MB)
138 21:31:18.101832 progress 50 % (5 MB)
139 21:31:18.195354 progress 55 % (6 MB)
140 21:31:18.296402 progress 60 % (6 MB)
141 21:31:18.393847 progress 65 % (7 MB)
142 21:31:18.477990 progress 70 % (7 MB)
143 21:31:18.573215 progress 75 % (8 MB)
144 21:31:18.667062 progress 80 % (8 MB)
145 21:31:18.748226 progress 85 % (9 MB)
146 21:31:18.825588 progress 90 % (10 MB)
147 21:31:18.904542 progress 95 % (10 MB)
148 21:31:18.977883 progress 100 % (11 MB)
149 21:31:18.993565 11 MB downloaded in 1.81 s (6.14 MB/s)
150 21:31:18.994193 end: 1.5.1 http-download (duration 00:00:02) [common]
152 21:31:18.995035 end: 1.5 download-retry (duration 00:00:02) [common]
153 21:31:18.995303 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 21:31:18.995568 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 21:31:36.225876 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/680092/extract-nfsrootfs-svn5hbtq
156 21:31:36.226481 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 21:31:36.226771 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 21:31:36.227516 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009
159 21:31:36.228014 makedir: /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin
160 21:31:36.228369 makedir: /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/tests
161 21:31:36.228690 makedir: /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/results
162 21:31:36.229025 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-add-keys
163 21:31:36.229614 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-add-sources
164 21:31:36.230159 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-background-process-start
165 21:31:36.230673 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-background-process-stop
166 21:31:36.231203 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-common-functions
167 21:31:36.231702 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-echo-ipv4
168 21:31:36.232221 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-install-packages
169 21:31:36.232715 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-installed-packages
170 21:31:36.233210 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-os-build
171 21:31:36.233731 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-probe-channel
172 21:31:36.234229 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-probe-ip
173 21:31:36.234718 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-target-ip
174 21:31:36.235219 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-target-mac
175 21:31:36.235702 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-target-storage
176 21:31:36.236235 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-test-case
177 21:31:36.236747 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-test-event
178 21:31:36.237235 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-test-feedback
179 21:31:36.237813 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-test-raise
180 21:31:36.238313 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-test-reference
181 21:31:36.238817 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-test-runner
182 21:31:36.239371 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-test-set
183 21:31:36.239890 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-test-shell
184 21:31:36.240431 Updating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-add-keys (debian)
185 21:31:36.240981 Updating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-add-sources (debian)
186 21:31:36.241581 Updating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-install-packages (debian)
187 21:31:36.242109 Updating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-installed-packages (debian)
188 21:31:36.242626 Updating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/bin/lava-os-build (debian)
189 21:31:36.243073 Creating /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/environment
190 21:31:36.243488 LAVA metadata
191 21:31:36.243762 - LAVA_JOB_ID=680092
192 21:31:36.243975 - LAVA_DISPATCHER_IP=192.168.6.2
193 21:31:36.244385 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 21:31:36.245411 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 21:31:36.245736 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 21:31:36.245944 skipped lava-vland-overlay
197 21:31:36.246181 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 21:31:36.246432 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 21:31:36.246649 skipped lava-multinode-overlay
200 21:31:36.246891 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 21:31:36.247140 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 21:31:36.247387 Loading test definitions
203 21:31:36.247662 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 21:31:36.247878 Using /lava-680092 at stage 0
205 21:31:36.249030 uuid=680092_1.6.2.4.1 testdef=None
206 21:31:36.249345 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 21:31:36.249607 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 21:31:36.251219 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 21:31:36.252027 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 21:31:36.254030 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 21:31:36.254856 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 21:31:36.256811 runner path: /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/0/tests/0_timesync-off test_uuid 680092_1.6.2.4.1
215 21:31:36.257396 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 21:31:36.258213 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 21:31:36.258437 Using /lava-680092 at stage 0
219 21:31:36.258798 Fetching tests from https://github.com/kernelci/test-definitions.git
220 21:31:36.259094 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/0/tests/1_kselftest-alsa'
221 21:31:39.802546 Running '/usr/bin/git checkout kernelci.org
222 21:31:40.251200 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 21:31:40.252664 uuid=680092_1.6.2.4.5 testdef=None
224 21:31:40.253008 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 21:31:40.253752 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 21:31:40.256656 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 21:31:40.257480 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 21:31:40.261246 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 21:31:40.262098 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 21:31:40.265721 runner path: /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/0/tests/1_kselftest-alsa test_uuid 680092_1.6.2.4.5
234 21:31:40.266004 BOARD='meson-g12b-a311d-libretech-cc'
235 21:31:40.266206 BRANCH='mainline'
236 21:31:40.266405 SKIPFILE='/dev/null'
237 21:31:40.266602 SKIP_INSTALL='True'
238 21:31:40.266795 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/clang-16/kselftest.tar.xz'
239 21:31:40.266992 TST_CASENAME=''
240 21:31:40.267187 TST_CMDFILES='alsa'
241 21:31:40.267730 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 21:31:40.268530 Creating lava-test-runner.conf files
244 21:31:40.268731 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/680092/lava-overlay-0t1_3009/lava-680092/0 for stage 0
245 21:31:40.269082 - 0_timesync-off
246 21:31:40.269315 - 1_kselftest-alsa
247 21:31:40.269645 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 21:31:40.269921 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 21:32:03.584448 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 21:32:03.584891 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 21:32:03.585182 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 21:32:03.585487 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 21:32:03.585776 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 21:32:04.203108 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 21:32:04.203602 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 21:32:04.203875 extracting modules file /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/680092/extract-nfsrootfs-svn5hbtq
257 21:32:05.561472 extracting modules file /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/680092/extract-overlay-ramdisk-qiu8dry6/ramdisk
258 21:32:06.954055 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 21:32:06.954540 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 21:32:06.954833 [common] Applying overlay to NFS
261 21:32:06.955056 [common] Applying overlay /var/lib/lava/dispatcher/tmp/680092/compress-overlay-mcfidhna/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/680092/extract-nfsrootfs-svn5hbtq
262 21:32:09.727636 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 21:32:09.728100 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 21:32:09.728406 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 21:32:09.728668 Converting downloaded kernel to a uImage
266 21:32:09.728997 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/kernel/Image /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/kernel/uImage
267 21:32:10.193666 output: Image Name:
268 21:32:10.194091 output: Created: Fri Aug 30 21:32:09 2024
269 21:32:10.194303 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 21:32:10.194505 output: Data Size: 37409280 Bytes = 36532.50 KiB = 35.68 MiB
271 21:32:10.194709 output: Load Address: 01080000
272 21:32:10.194907 output: Entry Point: 01080000
273 21:32:10.195104 output:
274 21:32:10.195434 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 21:32:10.195701 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 21:32:10.195971 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 21:32:10.196274 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 21:32:10.196535 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 21:32:10.196791 Building ramdisk /var/lib/lava/dispatcher/tmp/680092/extract-overlay-ramdisk-qiu8dry6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/680092/extract-overlay-ramdisk-qiu8dry6/ramdisk
280 21:32:12.483319 >> 171766 blocks
281 21:32:20.076890 Adding RAMdisk u-boot header.
282 21:32:20.077330 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/680092/extract-overlay-ramdisk-qiu8dry6/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/680092/extract-overlay-ramdisk-qiu8dry6/ramdisk.cpio.gz.uboot
283 21:32:20.321662 output: Image Name:
284 21:32:20.322341 output: Created: Fri Aug 30 21:32:20 2024
285 21:32:20.322822 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 21:32:20.323289 output: Data Size: 23951576 Bytes = 23390.21 KiB = 22.84 MiB
287 21:32:20.323748 output: Load Address: 00000000
288 21:32:20.324274 output: Entry Point: 00000000
289 21:32:20.324733 output:
290 21:32:20.325945 rename /var/lib/lava/dispatcher/tmp/680092/extract-overlay-ramdisk-qiu8dry6/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/ramdisk/ramdisk.cpio.gz.uboot
291 21:32:20.326782 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 21:32:20.327417 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 21:32:20.328058 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 21:32:20.328598 No LXC device requested
295 21:32:20.329194 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 21:32:20.329783 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 21:32:20.330352 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 21:32:20.330827 Checking files for TFTP limit of 4294967296 bytes.
299 21:32:20.333874 end: 1 tftp-deploy (duration 00:01:19) [common]
300 21:32:20.334572 start: 2 uboot-action (timeout 00:05:00) [common]
301 21:32:20.335179 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 21:32:20.335762 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 21:32:20.336389 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 21:32:20.337001 Using kernel file from prepare-kernel: 680092/tftp-deploy-dccgsc1z/kernel/uImage
305 21:32:20.337713 substitutions:
306 21:32:20.338180 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 21:32:20.338634 - {DTB_ADDR}: 0x01070000
308 21:32:20.339084 - {DTB}: 680092/tftp-deploy-dccgsc1z/dtb/meson-g12b-a311d-libretech-cc.dtb
309 21:32:20.339532 - {INITRD}: 680092/tftp-deploy-dccgsc1z/ramdisk/ramdisk.cpio.gz.uboot
310 21:32:20.339975 - {KERNEL_ADDR}: 0x01080000
311 21:32:20.340461 - {KERNEL}: 680092/tftp-deploy-dccgsc1z/kernel/uImage
312 21:32:20.340909 - {LAVA_MAC}: None
313 21:32:20.341399 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/680092/extract-nfsrootfs-svn5hbtq
314 21:32:20.341849 - {NFS_SERVER_IP}: 192.168.6.2
315 21:32:20.342286 - {PRESEED_CONFIG}: None
316 21:32:20.342721 - {PRESEED_LOCAL}: None
317 21:32:20.343159 - {RAMDISK_ADDR}: 0x08000000
318 21:32:20.343592 - {RAMDISK}: 680092/tftp-deploy-dccgsc1z/ramdisk/ramdisk.cpio.gz.uboot
319 21:32:20.344057 - {ROOT_PART}: None
320 21:32:20.344499 - {ROOT}: None
321 21:32:20.344931 - {SERVER_IP}: 192.168.6.2
322 21:32:20.345363 - {TEE_ADDR}: 0x83000000
323 21:32:20.345792 - {TEE}: None
324 21:32:20.346224 Parsed boot commands:
325 21:32:20.346647 - setenv autoload no
326 21:32:20.347077 - setenv initrd_high 0xffffffff
327 21:32:20.347505 - setenv fdt_high 0xffffffff
328 21:32:20.347934 - dhcp
329 21:32:20.348398 - setenv serverip 192.168.6.2
330 21:32:20.348841 - tftpboot 0x01080000 680092/tftp-deploy-dccgsc1z/kernel/uImage
331 21:32:20.349288 - tftpboot 0x08000000 680092/tftp-deploy-dccgsc1z/ramdisk/ramdisk.cpio.gz.uboot
332 21:32:20.349722 - tftpboot 0x01070000 680092/tftp-deploy-dccgsc1z/dtb/meson-g12b-a311d-libretech-cc.dtb
333 21:32:20.350157 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/680092/extract-nfsrootfs-svn5hbtq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 21:32:20.350607 - bootm 0x01080000 0x08000000 0x01070000
335 21:32:20.351193 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 21:32:20.352929 start: 2.3 connect-device (timeout 00:05:00) [common]
338 21:32:20.353416 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 21:32:20.369157 Setting prompt string to ['lava-test: # ']
340 21:32:20.370899 end: 2.3 connect-device (duration 00:00:00) [common]
341 21:32:20.372456 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 21:32:20.373251 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 21:32:20.373992 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 21:32:20.375349 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 21:32:20.411045 >> OK - accepted request
346 21:32:20.413288 Returned 0 in 0 seconds
347 21:32:20.514505 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 21:32:20.516106 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 21:32:20.516454 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 21:32:20.516763 Setting prompt string to ['Hit any key to stop autoboot']
352 21:32:20.517014 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 21:32:20.518962 Trying 192.168.56.21...
354 21:32:20.519570 Connected to conserv1.
355 21:32:20.520087 Escape character is '^]'.
356 21:32:20.520526
357 21:32:20.520963 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 21:32:20.521292
359 21:32:32.520273 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 21:32:32.521560 bl2_stage_init 0x01
361 21:32:32.521787 bl2_stage_init 0x81
362 21:32:32.525715 hw id: 0x0000 - pwm id 0x01
363 21:32:32.526754 bl2_stage_init 0xc1
364 21:32:32.526976 bl2_stage_init 0x02
365 21:32:32.527185
366 21:32:32.531310 L0:00000000
367 21:32:32.531600 L1:20000703
368 21:32:32.531813 L2:00008067
369 21:32:32.532034 L3:14000000
370 21:32:32.536869 B2:00402000
371 21:32:32.537146 B1:e0f83180
372 21:32:32.537360
373 21:32:32.537563 TE: 58124
374 21:32:32.537764
375 21:32:32.542494 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 21:32:32.543388
377 21:32:32.543595 Board ID = 1
378 21:32:32.548140 Set A53 clk to 24M
379 21:32:32.549236 Set A73 clk to 24M
380 21:32:32.550134 Set clk81 to 24M
381 21:32:32.553674 A53 clk: 1200 MHz
382 21:32:32.554018 A73 clk: 1200 MHz
383 21:32:32.554227 CLK81: 166.6M
384 21:32:32.554427 smccc: 00012a92
385 21:32:32.559148 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 21:32:32.564794 board id: 1
387 21:32:32.570030 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 21:32:32.581271 fw parse done
389 21:32:32.587043 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 21:32:32.629645 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 21:32:32.640882 PIEI prepare done
392 21:32:32.641294 fastboot data load
393 21:32:32.641535 fastboot data verify
394 21:32:32.646511 verify result: 266
395 21:32:32.652047 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 21:32:32.652446 LPDDR4 probe
397 21:32:32.652679 ddr clk to 1584MHz
398 21:32:32.659603 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 21:32:32.696431
400 21:32:32.696871 dmc_version 0001
401 21:32:32.703656 Check phy result
402 21:32:32.709849 INFO : End of CA training
403 21:32:32.710267 INFO : End of initialization
404 21:32:32.715493 INFO : Training has run successfully!
405 21:32:32.715935 Check phy result
406 21:32:32.721071 INFO : End of initialization
407 21:32:32.721507 INFO : End of read enable training
408 21:32:32.733153 INFO : End of fine write leveling
409 21:32:32.733582 INFO : End of Write leveling coarse delay
410 21:32:32.733834 INFO : Training has run successfully!
411 21:32:32.734066 Check phy result
412 21:32:32.738576 INFO : End of initialization
413 21:32:32.738985 INFO : End of read dq deskew training
414 21:32:32.743465 INFO : End of MPR read delay center optimization
415 21:32:32.749177 INFO : End of write delay center optimization
416 21:32:32.755049 INFO : End of read delay center optimization
417 21:32:32.755432 INFO : End of max read latency training
418 21:32:32.760809 INFO : Training has run successfully!
419 21:32:32.761189 1D training succeed
420 21:32:32.770482 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 21:32:32.816654 Check phy result
422 21:32:32.817108 INFO : End of initialization
423 21:32:32.840244 INFO : End of 2D read delay Voltage center optimization
424 21:32:32.859025 INFO : End of 2D read delay Voltage center optimization
425 21:32:32.910932 INFO : End of 2D write delay Voltage center optimization
426 21:32:32.960669 INFO : End of 2D write delay Voltage center optimization
427 21:32:32.966026 INFO : Training has run successfully!
428 21:32:32.966538
429 21:32:32.966988 channel==0
430 21:32:32.971605 RxClkDly_Margin_A0==88 ps 9
431 21:32:32.972227 TxDqDly_Margin_A0==98 ps 10
432 21:32:32.977302 RxClkDly_Margin_A1==88 ps 9
433 21:32:32.977874 TxDqDly_Margin_A1==98 ps 10
434 21:32:32.978345 TrainedVREFDQ_A0==74
435 21:32:32.982902 TrainedVREFDQ_A1==74
436 21:32:32.983409 VrefDac_Margin_A0==25
437 21:32:32.983870 DeviceVref_Margin_A0==40
438 21:32:32.988336 VrefDac_Margin_A1==25
439 21:32:32.988848 DeviceVref_Margin_A1==40
440 21:32:32.989303
441 21:32:32.989756
442 21:32:32.995014 channel==1
443 21:32:32.995513 RxClkDly_Margin_A0==98 ps 10
444 21:32:32.995972 TxDqDly_Margin_A0==98 ps 10
445 21:32:32.999702 RxClkDly_Margin_A1==98 ps 10
446 21:32:33.000087 TxDqDly_Margin_A1==98 ps 10
447 21:32:33.005506 TrainedVREFDQ_A0==77
448 21:32:33.006103 TrainedVREFDQ_A1==78
449 21:32:33.006483 VrefDac_Margin_A0==22
450 21:32:33.011032 DeviceVref_Margin_A0==37
451 21:32:33.011530 VrefDac_Margin_A1==23
452 21:32:33.016450 DeviceVref_Margin_A1==36
453 21:32:33.016974
454 21:32:33.017462 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 21:32:33.022034
456 21:32:33.050247 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 21:32:33.050980 2D training succeed
458 21:32:33.056242 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 21:32:33.061196 auto size-- 65535DDR cs0 size: 2048MB
460 21:32:33.061708 DDR cs1 size: 2048MB
461 21:32:33.066890 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 21:32:33.067417 cs0 DataBus test pass
463 21:32:33.072383 cs1 DataBus test pass
464 21:32:33.072954 cs0 AddrBus test pass
465 21:32:33.073426 cs1 AddrBus test pass
466 21:32:33.073884
467 21:32:33.078011 100bdlr_step_size ps== 420
468 21:32:33.078617 result report
469 21:32:33.083533 boot times 0Enable ddr reg access
470 21:32:33.088468 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 21:32:33.102144 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 21:32:33.677504 0.0;M3 CHK:0;cm4_sp_mode 0
473 21:32:33.677958 MVN_1=0x00000000
474 21:32:33.678203 MVN_2=0x00000000
475 21:32:33.688811 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 21:32:33.689253 OPS=0x10
477 21:32:33.689518 ring efuse init
478 21:32:33.689760 chipver efuse init
479 21:32:33.694431 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 21:32:33.694987 [0.018961 Inits done]
481 21:32:33.700252 secure task start!
482 21:32:33.700655 high task start!
483 21:32:33.700885 low task start!
484 21:32:33.703493 run into bl31
485 21:32:33.710104 NOTICE: BL31: v1.3(release):4fc40b1
486 21:32:33.717861 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 21:32:33.718263 NOTICE: BL31: G12A normal boot!
488 21:32:33.743173 NOTICE: BL31: BL33 decompress pass
489 21:32:33.749000 ERROR: Error initializing runtime service opteed_fast
490 21:32:34.981781
491 21:32:34.982210
492 21:32:34.990000 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 21:32:34.991017
494 21:32:34.991908 Model: Libre Computer AML-A311D-CC Alta
495 21:32:35.197879 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 21:32:35.221798 DRAM: 2 GiB (effective 3.8 GiB)
497 21:32:35.365131 Core: 408 devices, 31 uclasses, devicetree: separate
498 21:32:35.371073 WDT: Not starting watchdog@f0d0
499 21:32:35.403243 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 21:32:35.415574 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 21:32:35.420026 ** Bad device specification mmc 0 **
502 21:32:35.430881 Card did not respond to voltage select! : -110
503 21:32:35.437810 ** Bad device specification mmc 0 **
504 21:32:35.438312 Couldn't find partition mmc 0
505 21:32:35.446917 Card did not respond to voltage select! : -110
506 21:32:35.452372 ** Bad device specification mmc 0 **
507 21:32:35.452893 Couldn't find partition mmc 0
508 21:32:35.457433 Error: could not access storage.
509 21:32:36.720506 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 21:32:36.720927 bl2_stage_init 0x01
511 21:32:36.721143 bl2_stage_init 0x81
512 21:32:36.726162 hw id: 0x0000 - pwm id 0x01
513 21:32:36.726406 bl2_stage_init 0xc1
514 21:32:36.726614 bl2_stage_init 0x02
515 21:32:36.726824
516 21:32:36.731687 L0:00000000
517 21:32:36.732323 L1:20000703
518 21:32:36.732797 L2:00008067
519 21:32:36.733259 L3:14000000
520 21:32:36.737495 B2:00402000
521 21:32:36.738040 B1:e0f83180
522 21:32:36.738506
523 21:32:36.738966 TE: 58159
524 21:32:36.739420
525 21:32:36.743041 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 21:32:36.743582
527 21:32:36.744079 Board ID = 1
528 21:32:36.749444 Set A53 clk to 24M
529 21:32:36.749994 Set A73 clk to 24M
530 21:32:36.750458 Set clk81 to 24M
531 21:32:36.755267 A53 clk: 1200 MHz
532 21:32:36.755817 A73 clk: 1200 MHz
533 21:32:36.756917 CLK81: 166.6M
534 21:32:36.757455 smccc: 00012ab5
535 21:32:36.762864 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 21:32:36.763442 board id: 1
537 21:32:36.771422 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 21:32:36.781919 fw parse done
539 21:32:36.787793 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 21:32:36.830445 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 21:32:36.841394 PIEI prepare done
542 21:32:36.841980 fastboot data load
543 21:32:36.842461 fastboot data verify
544 21:32:36.847010 verify result: 266
545 21:32:36.852565 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 21:32:36.853139 LPDDR4 probe
547 21:32:36.853606 ddr clk to 1584MHz
548 21:32:36.860573 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 21:32:36.897833
550 21:32:36.898428 dmc_version 0001
551 21:32:36.904492 Check phy result
552 21:32:36.910411 INFO : End of CA training
553 21:32:36.910974 INFO : End of initialization
554 21:32:36.916038 INFO : Training has run successfully!
555 21:32:36.916618 Check phy result
556 21:32:36.921571 INFO : End of initialization
557 21:32:36.922135 INFO : End of read enable training
558 21:32:36.927181 INFO : End of fine write leveling
559 21:32:36.932773 INFO : End of Write leveling coarse delay
560 21:32:36.933335 INFO : Training has run successfully!
561 21:32:36.933798 Check phy result
562 21:32:36.938382 INFO : End of initialization
563 21:32:36.938943 INFO : End of read dq deskew training
564 21:32:36.943969 INFO : End of MPR read delay center optimization
565 21:32:36.949560 INFO : End of write delay center optimization
566 21:32:36.955135 INFO : End of read delay center optimization
567 21:32:36.955689 INFO : End of max read latency training
568 21:32:36.960771 INFO : Training has run successfully!
569 21:32:36.961329 1D training succeed
570 21:32:36.969894 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 21:32:37.017562 Check phy result
572 21:32:37.018152 INFO : End of initialization
573 21:32:37.039308 INFO : End of 2D read delay Voltage center optimization
574 21:32:37.059705 INFO : End of 2D read delay Voltage center optimization
575 21:32:37.111637 INFO : End of 2D write delay Voltage center optimization
576 21:32:37.161044 INFO : End of 2D write delay Voltage center optimization
577 21:32:37.166626 INFO : Training has run successfully!
578 21:32:37.167173
579 21:32:37.167646 channel==0
580 21:32:37.172130 RxClkDly_Margin_A0==88 ps 9
581 21:32:37.172688 TxDqDly_Margin_A0==98 ps 10
582 21:32:37.177751 RxClkDly_Margin_A1==88 ps 9
583 21:32:37.178302 TxDqDly_Margin_A1==98 ps 10
584 21:32:37.178772 TrainedVREFDQ_A0==74
585 21:32:37.183346 TrainedVREFDQ_A1==76
586 21:32:37.183893 VrefDac_Margin_A0==25
587 21:32:37.184393 DeviceVref_Margin_A0==40
588 21:32:37.188998 VrefDac_Margin_A1==25
589 21:32:37.189543 DeviceVref_Margin_A1==38
590 21:32:37.190004
591 21:32:37.190457
592 21:32:37.194602 channel==1
593 21:32:37.195157 RxClkDly_Margin_A0==98 ps 10
594 21:32:37.195617 TxDqDly_Margin_A0==98 ps 10
595 21:32:37.200122 RxClkDly_Margin_A1==88 ps 9
596 21:32:37.200676 TxDqDly_Margin_A1==88 ps 9
597 21:32:37.205790 TrainedVREFDQ_A0==77
598 21:32:37.206354 TrainedVREFDQ_A1==77
599 21:32:37.206817 VrefDac_Margin_A0==22
600 21:32:37.211333 DeviceVref_Margin_A0==37
601 21:32:37.211880 VrefDac_Margin_A1==24
602 21:32:37.216858 DeviceVref_Margin_A1==37
603 21:32:37.217410
604 21:32:37.217875 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 21:32:37.218329
606 21:32:37.250463 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 21:32:37.251092 2D training succeed
608 21:32:37.256086 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 21:32:37.261664 auto size-- 65535DDR cs0 size: 2048MB
610 21:32:37.262215 DDR cs1 size: 2048MB
611 21:32:37.267247 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 21:32:37.267803 cs0 DataBus test pass
613 21:32:37.272849 cs1 DataBus test pass
614 21:32:37.273416 cs0 AddrBus test pass
615 21:32:37.273888 cs1 AddrBus test pass
616 21:32:37.274342
617 21:32:37.278520 100bdlr_step_size ps== 420
618 21:32:37.279081 result report
619 21:32:37.284067 boot times 0Enable ddr reg access
620 21:32:37.289399 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 21:32:37.302836 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 21:32:37.876450 0.0;M3 CHK:0;cm4_sp_mode 0
623 21:32:37.877125 MVN_1=0x00000000
624 21:32:37.881979 MVN_2=0x00000000
625 21:32:37.887742 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 21:32:37.888371 OPS=0x10
627 21:32:37.888851 ring efuse init
628 21:32:37.889338 chipver efuse init
629 21:32:37.893297 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 21:32:37.898866 [0.018961 Inits done]
631 21:32:37.899405 secure task start!
632 21:32:37.899844 high task start!
633 21:32:37.903441 low task start!
634 21:32:37.904007 run into bl31
635 21:32:37.910130 NOTICE: BL31: v1.3(release):4fc40b1
636 21:32:37.917927 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 21:32:37.918462 NOTICE: BL31: G12A normal boot!
638 21:32:37.943854 NOTICE: BL31: BL33 decompress pass
639 21:32:37.949581 ERROR: Error initializing runtime service opteed_fast
640 21:32:39.182422
641 21:32:39.183068
642 21:32:39.190856 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 21:32:39.191412
644 21:32:39.191876 Model: Libre Computer AML-A311D-CC Alta
645 21:32:39.399330 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 21:32:39.422625 DRAM: 2 GiB (effective 3.8 GiB)
647 21:32:39.565622 Core: 408 devices, 31 uclasses, devicetree: separate
648 21:32:39.571493 WDT: Not starting watchdog@f0d0
649 21:32:39.603742 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 21:32:39.616238 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 21:32:39.621190 ** Bad device specification mmc 0 **
652 21:32:39.631548 Card did not respond to voltage select! : -110
653 21:32:39.638228 ** Bad device specification mmc 0 **
654 21:32:39.638767 Couldn't find partition mmc 0
655 21:32:39.647509 Card did not respond to voltage select! : -110
656 21:32:39.653024 ** Bad device specification mmc 0 **
657 21:32:39.653571 Couldn't find partition mmc 0
658 21:32:39.657224 Error: could not access storage.
659 21:32:39.999645 Net: eth0: ethernet@ff3f0000
660 21:32:40.000055 starting USB...
661 21:32:40.252380 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 21:32:40.252938 Starting the controller
663 21:32:40.259366 USB XHCI 1.10
664 21:32:41.972061 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 21:32:41.972448 bl2_stage_init 0x01
666 21:32:41.972677 bl2_stage_init 0x81
667 21:32:41.977611 hw id: 0x0000 - pwm id 0x01
668 21:32:41.978177 bl2_stage_init 0xc1
669 21:32:41.978654 bl2_stage_init 0x02
670 21:32:41.979109
671 21:32:41.983218 L0:00000000
672 21:32:41.983745 L1:20000703
673 21:32:41.984248 L2:00008067
674 21:32:41.984702 L3:14000000
675 21:32:41.986066 B2:00402000
676 21:32:41.986602 B1:e0f83180
677 21:32:41.987058
678 21:32:41.987508 TE: 58159
679 21:32:41.987952
680 21:32:41.997178 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 21:32:41.997732
682 21:32:41.998198 Board ID = 1
683 21:32:41.998645 Set A53 clk to 24M
684 21:32:41.999084 Set A73 clk to 24M
685 21:32:42.002781 Set clk81 to 24M
686 21:32:42.003295 A53 clk: 1200 MHz
687 21:32:42.003745 A73 clk: 1200 MHz
688 21:32:42.008445 CLK81: 166.6M
689 21:32:42.008974 smccc: 00012ab5
690 21:32:42.014051 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 21:32:42.014573 board id: 1
692 21:32:42.019571 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 21:32:42.033323 fw parse done
694 21:32:42.039281 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 21:32:42.081920 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 21:32:42.092821 PIEI prepare done
697 21:32:42.093339 fastboot data load
698 21:32:42.093802 fastboot data verify
699 21:32:42.098553 verify result: 266
700 21:32:42.104216 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 21:32:42.104736 LPDDR4 probe
702 21:32:42.105188 ddr clk to 1584MHz
703 21:32:42.112124 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 21:32:42.149442
705 21:32:42.150114 dmc_version 0001
706 21:32:42.156105 Check phy result
707 21:32:42.161922 INFO : End of CA training
708 21:32:42.162466 INFO : End of initialization
709 21:32:42.167480 INFO : Training has run successfully!
710 21:32:42.168024 Check phy result
711 21:32:42.173189 INFO : End of initialization
712 21:32:42.173710 INFO : End of read enable training
713 21:32:42.178694 INFO : End of fine write leveling
714 21:32:42.184293 INFO : End of Write leveling coarse delay
715 21:32:42.184817 INFO : Training has run successfully!
716 21:32:42.185269 Check phy result
717 21:32:42.189898 INFO : End of initialization
718 21:32:42.190413 INFO : End of read dq deskew training
719 21:32:42.195504 INFO : End of MPR read delay center optimization
720 21:32:42.201145 INFO : End of write delay center optimization
721 21:32:42.206683 INFO : End of read delay center optimization
722 21:32:42.207203 INFO : End of max read latency training
723 21:32:42.212434 INFO : Training has run successfully!
724 21:32:42.212974 1D training succeed
725 21:32:42.221586 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 21:32:42.269212 Check phy result
727 21:32:42.269777 INFO : End of initialization
728 21:32:42.290873 INFO : End of 2D read delay Voltage center optimization
729 21:32:42.311049 INFO : End of 2D read delay Voltage center optimization
730 21:32:42.363114 INFO : End of 2D write delay Voltage center optimization
731 21:32:42.412046 INFO : End of 2D write delay Voltage center optimization
732 21:32:42.417732 INFO : Training has run successfully!
733 21:32:42.418260
734 21:32:42.418720 channel==0
735 21:32:42.423301 RxClkDly_Margin_A0==88 ps 9
736 21:32:42.423818 TxDqDly_Margin_A0==98 ps 10
737 21:32:42.426619 RxClkDly_Margin_A1==88 ps 9
738 21:32:42.427126 TxDqDly_Margin_A1==98 ps 10
739 21:32:42.432236 TrainedVREFDQ_A0==74
740 21:32:42.432782 TrainedVREFDQ_A1==74
741 21:32:42.433238 VrefDac_Margin_A0==25
742 21:32:42.437912 DeviceVref_Margin_A0==40
743 21:32:42.438426 VrefDac_Margin_A1==25
744 21:32:42.443448 DeviceVref_Margin_A1==40
745 21:32:42.443972
746 21:32:42.444465
747 21:32:42.444912 channel==1
748 21:32:42.445350 RxClkDly_Margin_A0==98 ps 10
749 21:32:42.447105 TxDqDly_Margin_A0==88 ps 9
750 21:32:42.452544 RxClkDly_Margin_A1==98 ps 10
751 21:32:42.453087 TxDqDly_Margin_A1==88 ps 9
752 21:32:42.453563 TrainedVREFDQ_A0==75
753 21:32:42.458152 TrainedVREFDQ_A1==77
754 21:32:42.458694 VrefDac_Margin_A0==22
755 21:32:42.463839 DeviceVref_Margin_A0==38
756 21:32:42.464411 VrefDac_Margin_A1==24
757 21:32:42.464868 DeviceVref_Margin_A1==37
758 21:32:42.465307
759 21:32:42.473041 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 21:32:42.473606
761 21:32:42.500993 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 21:32:42.501626 2D training succeed
763 21:32:42.506725 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 21:32:42.512312 auto size-- 65535DDR cs0 size: 2048MB
765 21:32:42.512851 DDR cs1 size: 2048MB
766 21:32:42.517709 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 21:32:42.518239 cs0 DataBus test pass
768 21:32:42.523306 cs1 DataBus test pass
769 21:32:42.523849 cs0 AddrBus test pass
770 21:32:42.524352 cs1 AddrBus test pass
771 21:32:42.524801
772 21:32:42.528928 100bdlr_step_size ps== 420
773 21:32:42.529467 result report
774 21:32:42.534507 boot times 0Enable ddr reg access
775 21:32:42.540461 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 21:32:42.553886 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 21:32:43.125845 0.0;M3 CHK:0;cm4_sp_mode 0
778 21:32:43.126268 MVN_1=0x00000000
779 21:32:43.131342 MVN_2=0x00000000
780 21:32:43.137030 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 21:32:43.137339 OPS=0x10
782 21:32:43.137559 ring efuse init
783 21:32:43.137767 chipver efuse init
784 21:32:43.142606 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 21:32:43.148330 [0.018961 Inits done]
786 21:32:43.148631 secure task start!
787 21:32:43.148852 high task start!
788 21:32:43.152858 low task start!
789 21:32:43.153156 run into bl31
790 21:32:43.159505 NOTICE: BL31: v1.3(release):4fc40b1
791 21:32:43.167311 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 21:32:43.167628 NOTICE: BL31: G12A normal boot!
793 21:32:43.192709 NOTICE: BL31: BL33 decompress pass
794 21:32:43.198404 ERROR: Error initializing runtime service opteed_fast
795 21:32:44.431470
796 21:32:44.431909
797 21:32:44.439852 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 21:32:44.440478
799 21:32:44.440930 Model: Libre Computer AML-A311D-CC Alta
800 21:32:44.648262 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 21:32:44.671665 DRAM: 2 GiB (effective 3.8 GiB)
802 21:32:44.814572 Core: 408 devices, 31 uclasses, devicetree: separate
803 21:32:44.820519 WDT: Not starting watchdog@f0d0
804 21:32:44.852697 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 21:32:44.865177 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 21:32:44.870198 ** Bad device specification mmc 0 **
807 21:32:44.880570 Card did not respond to voltage select! : -110
808 21:32:44.888271 ** Bad device specification mmc 0 **
809 21:32:44.888864 Couldn't find partition mmc 0
810 21:32:44.896501 Card did not respond to voltage select! : -110
811 21:32:44.901950 ** Bad device specification mmc 0 **
812 21:32:44.902487 Couldn't find partition mmc 0
813 21:32:44.907016 Error: could not access storage.
814 21:32:45.249419 Net: eth0: ethernet@ff3f0000
815 21:32:45.249837 starting USB...
816 21:32:45.501203 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 21:32:45.501622 Starting the controller
818 21:32:45.508166 USB XHCI 1.10
819 21:32:47.671306 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
820 21:32:47.672066 bl2_stage_init 0x81
821 21:32:47.676619 hw id: 0x0000 - pwm id 0x01
822 21:32:47.677181 bl2_stage_init 0xc1
823 21:32:47.677650 bl2_stage_init 0x02
824 21:32:47.678105
825 21:32:47.682316 L0:00000000
826 21:32:47.682877 L1:20000703
827 21:32:47.683333 L2:00008067
828 21:32:47.683775 L3:14000000
829 21:32:47.684256 B2:00402000
830 21:32:47.685323 B1:e0f83180
831 21:32:47.685835
832 21:32:47.686291 TE: 58141
833 21:32:47.686736
834 21:32:47.696293 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 21:32:47.696830
836 21:32:47.697282 Board ID = 1
837 21:32:47.697724 Set A53 clk to 24M
838 21:32:47.698160 Set A73 clk to 24M
839 21:32:47.702127 Set clk81 to 24M
840 21:32:47.702639 A53 clk: 1200 MHz
841 21:32:47.703091 A73 clk: 1200 MHz
842 21:32:47.705704 CLK81: 166.6M
843 21:32:47.706211 smccc: 00012aa3
844 21:32:47.711306 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 21:32:47.711819 board id: 1
846 21:32:47.721413 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 21:32:47.732129 fw parse done
848 21:32:47.738029 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 21:32:47.780658 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 21:32:47.791711 PIEI prepare done
851 21:32:47.792290 fastboot data load
852 21:32:47.792753 fastboot data verify
853 21:32:47.797293 verify result: 266
854 21:32:47.802866 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 21:32:47.803380 LPDDR4 probe
856 21:32:47.803830 ddr clk to 1584MHz
857 21:32:47.810879 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 21:32:47.848144
859 21:32:47.848711 dmc_version 0001
860 21:32:47.854783 Check phy result
861 21:32:47.860666 INFO : End of CA training
862 21:32:47.861188 INFO : End of initialization
863 21:32:47.866248 INFO : Training has run successfully!
864 21:32:47.866764 Check phy result
865 21:32:47.871848 INFO : End of initialization
866 21:32:47.872406 INFO : End of read enable training
867 21:32:47.877478 INFO : End of fine write leveling
868 21:32:47.883050 INFO : End of Write leveling coarse delay
869 21:32:47.883642 INFO : Training has run successfully!
870 21:32:47.884145 Check phy result
871 21:32:47.888685 INFO : End of initialization
872 21:32:47.889193 INFO : End of read dq deskew training
873 21:32:47.894260 INFO : End of MPR read delay center optimization
874 21:32:47.899869 INFO : End of write delay center optimization
875 21:32:47.905437 INFO : End of read delay center optimization
876 21:32:47.905959 INFO : End of max read latency training
877 21:32:47.911068 INFO : Training has run successfully!
878 21:32:47.911588 1D training succeed
879 21:32:47.920249 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 21:32:47.967782 Check phy result
881 21:32:47.968377 INFO : End of initialization
882 21:32:47.989560 INFO : End of 2D read delay Voltage center optimization
883 21:32:48.009816 INFO : End of 2D read delay Voltage center optimization
884 21:32:48.061836 INFO : End of 2D write delay Voltage center optimization
885 21:32:48.111057 INFO : End of 2D write delay Voltage center optimization
886 21:32:48.116590 INFO : Training has run successfully!
887 21:32:48.116888
888 21:32:48.117127 channel==0
889 21:32:48.122221 RxClkDly_Margin_A0==88 ps 9
890 21:32:48.122624 TxDqDly_Margin_A0==98 ps 10
891 21:32:48.127852 RxClkDly_Margin_A1==88 ps 9
892 21:32:48.129910 TxDqDly_Margin_A1==98 ps 10
893 21:32:48.130467 TrainedVREFDQ_A0==74
894 21:32:48.133424 TrainedVREFDQ_A1==74
895 21:32:48.133948 VrefDac_Margin_A0==25
896 21:32:48.134397 DeviceVref_Margin_A0==40
897 21:32:48.138997 VrefDac_Margin_A1==26
898 21:32:48.139500 DeviceVref_Margin_A1==40
899 21:32:48.139939
900 21:32:48.140408
901 21:32:48.144609 channel==1
902 21:32:48.145139 RxClkDly_Margin_A0==98 ps 10
903 21:32:48.145583 TxDqDly_Margin_A0==98 ps 10
904 21:32:48.150223 RxClkDly_Margin_A1==98 ps 10
905 21:32:48.150754 TxDqDly_Margin_A1==88 ps 9
906 21:32:48.155897 TrainedVREFDQ_A0==77
907 21:32:48.156473 TrainedVREFDQ_A1==77
908 21:32:48.156923 VrefDac_Margin_A0==22
909 21:32:48.161404 DeviceVref_Margin_A0==37
910 21:32:48.161920 VrefDac_Margin_A1==22
911 21:32:48.167015 DeviceVref_Margin_A1==37
912 21:32:48.167564
913 21:32:48.168074 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 21:32:48.172624
915 21:32:48.200646 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
916 21:32:48.201279 2D training succeed
917 21:32:48.206222 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 21:32:48.211902 auto size-- 65535DDR cs0 size: 2048MB
919 21:32:48.212483 DDR cs1 size: 2048MB
920 21:32:48.217436 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 21:32:48.217987 cs0 DataBus test pass
922 21:32:48.223031 cs1 DataBus test pass
923 21:32:48.223579 cs0 AddrBus test pass
924 21:32:48.224051 cs1 AddrBus test pass
925 21:32:48.224497
926 21:32:48.228639 100bdlr_step_size ps== 420
927 21:32:48.229216 result report
928 21:32:48.234228 boot times 0Enable ddr reg access
929 21:32:48.239668 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 21:32:48.253139 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 21:32:48.827947 0.0;M3 CHK:0;cm4_sp_mode 0
932 21:32:48.828662 MVN_1=0x00000000
933 21:32:48.829140 MVN_2=0x00000000
934 21:32:48.833566 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 21:32:48.839359 OPS=0x10
936 21:32:48.839925 ring efuse init
937 21:32:48.840453 chipver efuse init
938 21:32:48.844948 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 21:32:48.845565 [0.018961 Inits done]
940 21:32:48.850553 secure task start!
941 21:32:48.851131 high task start!
942 21:32:48.851604 low task start!
943 21:32:48.853883 run into bl31
944 21:32:48.860558 NOTICE: BL31: v1.3(release):4fc40b1
945 21:32:48.868359 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 21:32:48.868964 NOTICE: BL31: G12A normal boot!
947 21:32:48.893888 NOTICE: BL31: BL33 decompress pass
948 21:32:48.899513 ERROR: Error initializing runtime service opteed_fast
949 21:32:50.132314
950 21:32:50.132991
951 21:32:50.140239 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 21:32:50.140758
953 21:32:50.141229 Model: Libre Computer AML-A311D-CC Alta
954 21:32:50.349049 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 21:32:50.372471 DRAM: 2 GiB (effective 3.8 GiB)
956 21:32:50.515494 Core: 408 devices, 31 uclasses, devicetree: separate
957 21:32:50.521393 WDT: Not starting watchdog@f0d0
958 21:32:50.553676 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 21:32:50.566230 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 21:32:50.570200 ** Bad device specification mmc 0 **
961 21:32:50.581454 Card did not respond to voltage select! : -110
962 21:32:50.589079 ** Bad device specification mmc 0 **
963 21:32:50.589644 Couldn't find partition mmc 0
964 21:32:50.597414 Card did not respond to voltage select! : -110
965 21:32:50.602927 ** Bad device specification mmc 0 **
966 21:32:50.603321 Couldn't find partition mmc 0
967 21:32:50.607969 Error: could not access storage.
968 21:32:50.951483 Net: eth0: ethernet@ff3f0000
969 21:32:50.952098 starting USB...
970 21:32:51.203291 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 21:32:51.203707 Starting the controller
972 21:32:51.210267 USB XHCI 1.10
973 21:32:52.764313 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
974 21:32:52.772207 scanning usb for storage devices... 0 Storage Device(s) found
976 21:32:52.823410 Hit any key to stop autoboot: 1
977 21:32:52.824109 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
978 21:32:52.824501 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
979 21:32:52.824795 Setting prompt string to ['=>']
980 21:32:52.825087 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
981 21:32:52.830009 0
982 21:32:52.830659 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
983 21:32:52.830990 Sending with 10 millisecond of delay
985 21:32:53.966871 => setenv autoload no
986 21:32:53.978179 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
987 21:32:53.980858 setenv autoload no
988 21:32:53.981360 Sending with 10 millisecond of delay
990 21:32:55.781681 => setenv initrd_high 0xffffffff
991 21:32:55.792451 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
992 21:32:55.793032 setenv initrd_high 0xffffffff
993 21:32:55.793548 Sending with 10 millisecond of delay
995 21:32:57.410215 => setenv fdt_high 0xffffffff
996 21:32:57.420828 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
997 21:32:57.422048 setenv fdt_high 0xffffffff
998 21:32:57.423533 Sending with 10 millisecond of delay
1000 21:32:57.716770 => dhcp
1001 21:32:57.727633 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1002 21:32:57.728622 dhcp
1003 21:32:57.729111 Speed: 1000, full duplex
1004 21:32:57.729572 BOOTP broadcast 1
1005 21:32:57.976159 BOOTP broadcast 2
1006 21:32:58.132467 DHCP client bound to address 192.168.6.33 (405 ms)
1007 21:32:58.133357 Sending with 10 millisecond of delay
1009 21:32:59.809982 => setenv serverip 192.168.6.2
1010 21:32:59.820822 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1011 21:32:59.821766 setenv serverip 192.168.6.2
1012 21:32:59.822514 Sending with 10 millisecond of delay
1014 21:33:03.548305 => tftpboot 0x01080000 680092/tftp-deploy-dccgsc1z/kernel/uImage
1015 21:33:03.559135 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1016 21:33:03.560104 tftpboot 0x01080000 680092/tftp-deploy-dccgsc1z/kernel/uImage
1017 21:33:03.560569 Speed: 1000, full duplex
1018 21:33:03.561001 Using ethernet@ff3f0000 device
1019 21:33:03.562097 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1020 21:33:03.567559 Filename '680092/tftp-deploy-dccgsc1z/kernel/uImage'.
1021 21:33:03.571553 Load address: 0x1080000
1022 21:33:06.504345 Loading: *################################################## 35.7 MiB
1023 21:33:06.504773 12.2 MiB/s
1024 21:33:06.504990 done
1025 21:33:06.508551 Bytes transferred = 37409344 (23ad240 hex)
1026 21:33:06.512168 Sending with 10 millisecond of delay
1028 21:33:11.206043 => tftpboot 0x08000000 680092/tftp-deploy-dccgsc1z/ramdisk/ramdisk.cpio.gz.uboot
1029 21:33:11.216797 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
1030 21:33:11.217355 tftpboot 0x08000000 680092/tftp-deploy-dccgsc1z/ramdisk/ramdisk.cpio.gz.uboot
1031 21:33:11.217587 Speed: 1000, full duplex
1032 21:33:11.217792 Using ethernet@ff3f0000 device
1033 21:33:11.219244 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1034 21:33:11.227838 Filename '680092/tftp-deploy-dccgsc1z/ramdisk/ramdisk.cpio.gz.uboot'.
1035 21:33:11.228346 Load address: 0x8000000
1036 21:33:17.805573 Loading: *#############T ##################################### 22.8 MiB
1037 21:33:17.805988 3.5 MiB/s
1038 21:33:17.806221 done
1039 21:33:17.809539 Bytes transferred = 23951640 (16d7918 hex)
1040 21:33:17.810064 Sending with 10 millisecond of delay
1042 21:33:22.981619 => tftpboot 0x01070000 680092/tftp-deploy-dccgsc1z/dtb/meson-g12b-a311d-libretech-cc.dtb
1043 21:33:22.992922 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:57)
1044 21:33:22.994319 tftpboot 0x01070000 680092/tftp-deploy-dccgsc1z/dtb/meson-g12b-a311d-libretech-cc.dtb
1045 21:33:22.994563 Speed: 1000, full duplex
1046 21:33:22.994862 Using ethernet@ff3f0000 device
1047 21:33:22.997710 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1048 21:33:23.009860 Filename '680092/tftp-deploy-dccgsc1z/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1049 21:33:23.010179 Load address: 0x1070000
1050 21:33:23.025869 Loading: *################################################## 53.4 KiB
1051 21:33:23.026118 3.1 MiB/s
1052 21:33:23.026320 done
1053 21:33:23.032280 Bytes transferred = 54667 (d58b hex)
1054 21:33:23.033843 Sending with 10 millisecond of delay
1056 21:33:36.350627 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/680092/extract-nfsrootfs-svn5hbtq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1057 21:33:36.361405 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:44)
1058 21:33:36.362251 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/680092/extract-nfsrootfs-svn5hbtq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1059 21:33:36.362960 Sending with 10 millisecond of delay
1061 21:33:38.701120 => bootm 0x01080000 0x08000000 0x01070000
1062 21:33:38.711864 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1063 21:33:38.712439 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
1064 21:33:38.713398 bootm 0x01080000 0x08000000 0x01070000
1065 21:33:38.713845 ## Booting kernel from Legacy Image at 01080000 ...
1066 21:33:38.716632 Image Name:
1067 21:33:38.722284 Image Type: AArch64 Linux Kernel Image (uncompressed)
1068 21:33:38.722749 Data Size: 37409280 Bytes = 35.7 MiB
1069 21:33:38.727730 Load Address: 01080000
1070 21:33:38.728209 Entry Point: 01080000
1071 21:33:38.888149 Verifying Checksum ... OK
1072 21:33:38.888760 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1073 21:33:38.893453 Image Name:
1074 21:33:38.898956 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1075 21:33:38.899624 Data Size: 23951576 Bytes = 22.8 MiB
1076 21:33:38.904576 Load Address: 00000000
1077 21:33:38.905074 Entry Point: 00000000
1078 21:33:39.008810 Verifying Checksum ... OK
1079 21:33:39.009395 ## Flattened Device Tree blob at 01070000
1080 21:33:39.014326 Booting using the fdt blob at 0x1070000
1081 21:33:39.014930 Working FDT set to 1070000
1082 21:33:39.017993 Loading Kernel Image
1083 21:33:39.059621 Loading Ramdisk to 7e928000, end 7ffff8d8 ... OK
1084 21:33:39.065662 Loading Device Tree to 000000007e917000, end 000000007e92758a ... OK
1085 21:33:39.066256 Working FDT set to 7e917000
1086 21:33:39.070989
1087 21:33:39.071572 Starting kernel ...
1088 21:33:39.072138
1089 21:33:39.073216 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1090 21:33:39.073971 start: 2.4.4 auto-login-action (timeout 00:03:41) [common]
1091 21:33:39.074580 Setting prompt string to ['Linux version [0-9]']
1092 21:33:39.075149 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1093 21:33:39.075734 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1094 21:33:39.116187 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1095 21:33:39.116906 start: 2.4.4.1 login-action (timeout 00:03:41) [common]
1096 21:33:39.117194 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1097 21:33:39.117442 Setting prompt string to []
1098 21:33:39.117700 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1099 21:33:39.117935 Using line separator: #'\n'#
1100 21:33:39.118142 No login prompt set.
1101 21:33:39.118354 Parsing kernel messages
1102 21:33:39.118550 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1103 21:33:39.118966 [login-action] Waiting for messages, (timeout 00:03:41)
1104 21:33:39.119188 Waiting using forced prompt support (timeout 00:01:51)
1105 21:33:39.130813 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j302575-arm64-clang-16-defconfig-77788) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP PREEMPT Fri Aug 30 20:46:46 UTC 2024
1106 21:33:39.136313 [ 0.000000] KASLR disabled due to lack of seed
1107 21:33:39.141920 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1108 21:33:39.145448 [ 0.000000] efi: UEFI not found.
1109 21:33:39.151001 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1110 21:33:39.161964 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1111 21:33:39.171088 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1112 21:33:39.176704 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1113 21:33:39.187715 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1114 21:33:39.198808 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1115 21:33:39.204261 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1116 21:33:39.211232 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1117 21:33:39.216568 [ 0.000000] NUMA: No NUMA configuration found
1118 21:33:39.222129 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1119 21:33:39.227658 [ 0.000000] NUMA: NODE_DATA [mem 0xe46669c0-0xe4668fff]
1120 21:33:39.233291 [ 0.000000] Zone ranges:
1121 21:33:39.238835 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1122 21:33:39.239286 [ 0.000000] DMA32 empty
1123 21:33:39.244312 [ 0.000000] Normal empty
1124 21:33:39.249801 [ 0.000000] Movable zone start for each node
1125 21:33:39.250237 [ 0.000000] Early memory node ranges
1126 21:33:39.255358 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1127 21:33:39.260938 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1128 21:33:39.271932 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1129 21:33:39.275874 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1130 21:33:39.297599 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1131 21:33:39.303183 [ 0.000000] psci: probing for conduit method from DT.
1132 21:33:39.303684 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1133 21:33:39.308646 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1134 21:33:39.314168 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1135 21:33:39.319682 [ 0.000000] psci: SMC Calling Convention v1.1
1136 21:33:39.325208 [ 0.000000] percpu: Embedded 24 pages/cpu s59928 r8192 d30184 u98304
1137 21:33:39.330733 [ 0.000000] Detected VIPT I-cache on CPU0
1138 21:33:39.336249 [ 0.000000] CPU features: detected: ARM erratum 845719
1139 21:33:39.341750 [ 0.000000] alternatives: applying boot alternatives
1140 21:33:39.358296 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/680092/extract-nfsrootfs-svn5hbtq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1141 21:33:39.369357 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1142 21:33:39.374952 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1143 21:33:39.380385 <6>[ 0.000000] Fallback order for Node 0: 0
1144 21:33:39.385952 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1145 21:33:39.391442 <6>[ 0.000000] Policy zone: DMA
1146 21:33:39.396960 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1147 21:33:39.402498 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1148 21:33:39.407962 <6>[ 0.000000] software IO TLB: area num 8.
1149 21:33:39.416399 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1150 21:33:39.464928 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1151 21:33:39.470402 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1152 21:33:39.473961 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1153 21:33:39.479489 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1154 21:33:39.484974 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1155 21:33:39.490465 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1156 21:33:39.499547 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1157 21:33:39.505082 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1158 21:33:39.510583 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
1159 21:33:39.521602 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
1160 21:33:39.527125 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1161 21:33:39.532683 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1162 21:33:39.538218 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1163 21:33:39.543228 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1164 21:33:39.555756 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1165 21:33:39.566808 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1166 21:33:39.572279 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1167 21:33:39.577869 <6>[ 0.008788] Console: colour dummy device 80x25
1168 21:33:39.588840 <6>[ 0.012942] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1169 21:33:39.594404 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1170 21:33:39.600010 <6>[ 0.028189] LSM: initializing lsm=capability
1171 21:33:39.605461 <6>[ 0.032703] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 21:33:39.611015 <6>[ 0.040212] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1173 21:33:39.616465 <6>[ 0.050733] rcu: Hierarchical SRCU implementation.
1174 21:33:39.621986 <6>[ 0.053254] rcu: Max phase no-delay instances is 1000.
1175 21:33:39.633078 <6>[ 0.058857] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1176 21:33:39.638590 <6>[ 0.071514] EFI services will not be available.
1177 21:33:39.639218 <6>[ 0.072083] smp: Bringing up secondary CPUs ...
1178 21:33:39.644097 <6>[ 0.077130] Detected VIPT I-cache on CPU1
1179 21:33:39.649630 <6>[ 0.077245] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1180 21:33:39.655191 <6>[ 0.078542] CPU features: detected: Spectre-v2
1181 21:33:39.660641 <6>[ 0.078555] CPU features: detected: Spectre-v4
1182 21:33:39.666161 <6>[ 0.078559] CPU features: detected: Spectre-BHB
1183 21:33:39.671668 <6>[ 0.078564] CPU features: detected: ARM erratum 858921
1184 21:33:39.677231 <6>[ 0.078570] Detected VIPT I-cache on CPU2
1185 21:33:39.682696 <6>[ 0.078640] arch_timer: Enabling local workaround for ARM erratum 858921
1186 21:33:39.688270 <6>[ 0.078657] arch_timer: CPU2: Trapping CNTVCT access
1187 21:33:39.693749 <6>[ 0.078668] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1188 21:33:39.699257 <6>[ 0.079379] Detected VIPT I-cache on CPU3
1189 21:33:39.704800 <6>[ 0.079423] arch_timer: Enabling local workaround for ARM erratum 858921
1190 21:33:39.710318 <6>[ 0.079432] arch_timer: CPU3: Trapping CNTVCT access
1191 21:33:39.715883 <6>[ 0.079439] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1192 21:33:39.721583 <6>[ 0.080112] Detected VIPT I-cache on CPU4
1193 21:33:39.727031 <6>[ 0.080158] arch_timer: Enabling local workaround for ARM erratum 858921
1194 21:33:39.732437 <6>[ 0.080167] arch_timer: CPU4: Trapping CNTVCT access
1195 21:33:39.738098 <6>[ 0.080174] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1196 21:33:39.743562 <6>[ 0.080908] Detected VIPT I-cache on CPU5
1197 21:33:39.748996 <6>[ 0.080954] arch_timer: Enabling local workaround for ARM erratum 858921
1198 21:33:39.754526 <6>[ 0.080964] arch_timer: CPU5: Trapping CNTVCT access
1199 21:33:39.765569 <6>[ 0.080971] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1200 21:33:39.766188 <6>[ 0.081074] smp: Brought up 1 node, 6 CPUs
1201 21:33:39.771083 <6>[ 0.203224] SMP: Total of 6 processors activated.
1202 21:33:39.776628 <6>[ 0.208130] CPU: All CPU(s) started at EL2
1203 21:33:39.782237 <6>[ 0.212473] CPU features: detected: 32-bit EL0 Support
1204 21:33:39.787724 <6>[ 0.217788] CPU features: detected: 32-bit EL1 Support
1205 21:33:39.793314 <6>[ 0.223148] CPU features: detected: CRC32 instructions
1206 21:33:39.798752 <6>[ 0.228540] alternatives: applying system-wide alternatives
1207 21:33:39.816785 <6>[ 0.235985] Memory: 3565016K/4012396K available (17600K kernel code, 5044K rwdata, 11472K rodata, 2240K init, 733K bss, 180152K reserved, 262144K cma-reserved)
1208 21:33:39.817379 <6>[ 0.250018] devtmpfs: initialized
1209 21:33:39.827833 <6>[ 0.259315] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1210 21:33:39.833414 <6>[ 0.263667] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1211 21:33:39.838935 <6>[ 0.274689] 23424 pages in range for non-PLT usage
1212 21:33:39.844442 <6>[ 0.274698] 514944 pages in range for PLT usage
1213 21:33:39.849987 <6>[ 0.276032] pinctrl core: initialized pinctrl subsystem
1214 21:33:39.855531 <6>[ 0.288066] DMI not present or invalid.
1215 21:33:39.861019 <6>[ 0.291844] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1216 21:33:39.866514 <6>[ 0.297119] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1217 21:33:39.877516 <6>[ 0.303935] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1218 21:33:39.883121 <6>[ 0.312024] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1219 21:33:39.888606 <6>[ 0.319496] audit: initializing netlink subsys (disabled)
1220 21:33:39.899602 <5>[ 0.325215] audit: type=2000 audit(0.244:1): state=initialized audit_enabled=0 res=1
1221 21:33:39.905160 <6>[ 0.326520] thermal_sys: Registered thermal governor 'step_wise'
1222 21:33:39.910633 <6>[ 0.333002] thermal_sys: Registered thermal governor 'power_allocator'
1223 21:33:39.916226 <6>[ 0.339257] cpuidle: using governor menu
1224 21:33:39.921714 <6>[ 0.350237] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1225 21:33:39.927213 <6>[ 0.357156] ASID allocator initialised with 65536 entries
1226 21:33:39.934447 <6>[ 0.364573] Serial: AMBA PL011 UART driver
1227 21:33:39.941367 <6>[ 0.374271] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 21:33:39.957120 <6>[ 0.389586] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1229 21:33:39.968135 <6>[ 0.392236] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1230 21:33:39.973651 <6>[ 0.405321] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1231 21:33:39.979198 <6>[ 0.408626] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1232 21:33:39.990220 <6>[ 0.417029] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1233 21:33:39.995777 <6>[ 0.424672] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1234 21:33:40.006752 <6>[ 0.437962] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1235 21:33:40.012321 <6>[ 0.440493] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1236 21:33:40.017849 <6>[ 0.446972] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1237 21:33:40.023382 <6>[ 0.453952] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1238 21:33:40.034347 <6>[ 0.460421] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1239 21:33:40.039900 <6>[ 0.467406] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1240 21:33:40.045470 <6>[ 0.473882] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1241 21:33:40.050986 <6>[ 0.480861] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1242 21:33:40.056443 <6>[ 0.488901] ACPI: Interpreter disabled.
1243 21:33:40.062022 <6>[ 0.494100] iommu: Default domain type: Translated
1244 21:33:40.067525 <6>[ 0.496399] iommu: DMA domain TLB invalidation policy: strict mode
1245 21:33:40.073012 <5>[ 0.503099] SCSI subsystem initialized
1246 21:33:40.078592 <6>[ 0.507031] usbcore: registered new interface driver usbfs
1247 21:33:40.084202 <6>[ 0.512452] usbcore: registered new interface driver hub
1248 21:33:40.089607 <6>[ 0.517969] usbcore: registered new device driver usb
1249 21:33:40.095157 <6>[ 0.524183] pps_core: LinuxPPS API ver. 1 registered
1250 21:33:40.100680 <6>[ 0.528387] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1251 21:33:40.106208 <6>[ 0.537708] PTP clock support registered
1252 21:33:40.111689 <6>[ 0.542004] EDAC MC: Ver: 3.0.0
1253 21:33:40.117232 <6>[ 0.545601] scmi_core: SCMI protocol bus registered
1254 21:33:40.117787 <6>[ 0.551224] FPGA manager framework
1255 21:33:40.122727 <6>[ 0.553970] Advanced Linux Sound Architecture Driver Initialized.
1256 21:33:40.128291 <6>[ 0.560875] vgaarb: loaded
1257 21:33:40.133825 <6>[ 0.563462] clocksource: Switched to clocksource arch_sys_counter
1258 21:33:40.139311 <5>[ 0.569610] VFS: Disk quotas dquot_6.6.0
1259 21:33:40.144837 <6>[ 0.573601] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1260 21:33:40.150328 <6>[ 0.580813] pnp: PnP ACPI: disabled
1261 21:33:40.155889 <6>[ 0.588985] NET: Registered PF_INET protocol family
1262 21:33:40.161399 <6>[ 0.589637] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1263 21:33:40.172438 <6>[ 0.599606] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1264 21:33:40.177909 <6>[ 0.605805] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1265 21:33:40.188930 <6>[ 0.613700] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1266 21:33:40.194523 <6>[ 0.621939] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1267 21:33:40.200057 <6>[ 0.629740] TCP: Hash tables configured (established 32768 bind 32768)
1268 21:33:40.205573 <6>[ 0.636214] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 21:33:40.216564 <6>[ 0.643057] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1270 21:33:40.222079 <6>[ 0.650477] NET: Registered PF_UNIX/PF_LOCAL protocol family
1271 21:33:40.227610 <6>[ 0.656522] RPC: Registered named UNIX socket transport module.
1272 21:33:40.233168 <6>[ 0.662344] RPC: Registered udp transport module.
1273 21:33:40.238664 <6>[ 0.667250] RPC: Registered tcp transport module.
1274 21:33:40.244168 <6>[ 0.672165] RPC: Registered tcp-with-tls transport module.
1275 21:33:40.249695 <6>[ 0.677858] RPC: Registered tcp NFSv4.1 backchannel transport module.
1276 21:33:40.255403 <6>[ 0.684506] PCI: CLS 0 bytes, default 64
1277 21:33:40.256251 <6>[ 0.688830] Unpacking initramfs...
1278 21:33:40.260907 <6>[ 0.698069] kvm [1]: nv: 529 coarse grained trap handlers
1279 21:33:40.266450 <6>[ 0.698357] kvm [1]: IPA Size Limit: 40 bits
1280 21:33:40.271912 <6>[ 0.704109] kvm [1]: vgic interrupt IRQ9
1281 21:33:40.277450 <6>[ 0.706740] kvm [1]: Hyp nVHE mode initialized successfully
1282 21:33:40.282989 <5>[ 0.713703] Initialise system trusted keyrings
1283 21:33:40.288497 <6>[ 0.717343] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1284 21:33:40.294132 <6>[ 0.724047] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1285 21:33:40.299532 <5>[ 0.730054] NFS: Registering the id_resolver key type
1286 21:33:40.305138 <5>[ 0.735128] Key type id_resolver registered
1287 21:33:40.310561 <5>[ 0.739495] Key type id_legacy registered
1288 21:33:40.316151 <6>[ 0.743747] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1289 21:33:40.321620 <6>[ 0.750621] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1290 21:33:40.328518 <6>[ 0.758386] 9p: Installing v9fs 9p2000 file system support
1291 21:33:40.358623 <5>[ 0.796595] Key type asymmetric registered
1292 21:33:40.364155 <5>[ 0.796638] Asymmetric key parser 'x509' registered
1293 21:33:40.373133 <6>[ 0.800494] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1294 21:33:40.378615 <6>[ 0.808016] io scheduler mq-deadline registered
1295 21:33:40.384220 <6>[ 0.812754] io scheduler kyber registered
1296 21:33:40.384848 <6>[ 0.817017] io scheduler bfq registered
1297 21:33:40.391754 <6>[ 0.822868] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1298 21:33:40.437420 <6>[ 0.870986] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1299 21:33:40.456978 <6>[ 0.883718] Serial: 8250/16550 driver, 4 por<6>[ 0.888186] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1300 21:33:40.462492 <6>[ 0.897814] printk: legacy console [ttyAML0] enabled
1301 21:33:40.468138 <6>[ 0.897814] printk: legacy console [ttyAML0] enabled
1302 21:33:40.473678 <6>[ 0.902606] printk: legacy bootconsole [meson0] disabled
1303 21:33:40.479166 <6>[ 0.902606] printk: legacy bootconsole [meson0] disabled
1304 21:33:40.484686 <6>[ 0.916169] msm_serial: driver initialized
1305 21:33:40.490202 <6>[ 0.918495] SuperH (H)SCI(F) driver initialized
1306 21:33:40.490855 <6>[ 0.923060] STM32 USART driver initialized
1307 21:33:40.495762 <5>[ 0.929159] random: crng init done
1308 21:33:40.502474 <6>[ 0.934614] loop: module loaded
1309 21:33:40.503029 <6>[ 0.935808] megasas: 07.727.03.00-rc1
1310 21:33:40.508041 <6>[ 0.944809] tun: Universal TUN/TAP device driver, 1.6
1311 21:33:40.513574 <6>[ 0.945886] thunder_xcv, ver 1.0
1312 21:33:40.514120 <6>[ 0.947999] thunder_bgx, ver 1.0
1313 21:33:40.519175 <6>[ 0.951434] nicpf, ver 1.0
1314 21:33:40.524664 <6>[ 0.955845] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1315 21:33:40.530210 <6>[ 0.961829] hns3: Copyright (c) 2017 Huawei Corporation.
1316 21:33:40.535756 <6>[ 0.967415] hclge is initializing
1317 21:33:40.541293 <6>[ 0.970955] e1000: Intel(R) PRO/1000 Network Driver
1318 21:33:40.546871 <6>[ 0.976039] e1000: Copyright (c) 1999-2006 Intel Corporation.
1319 21:33:40.552400 <6>[ 0.982051] e1000e: Intel(R) PRO/1000 Network Driver
1320 21:33:40.557965 <6>[ 0.987218] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1321 21:33:40.563481 <6>[ 0.993399] igb: Intel(R) Gigabit Ethernet Network Driver
1322 21:33:40.569021 <6>[ 0.999004] igb: Copyright (c) 2007-2014 Intel Corporation.
1323 21:33:40.574562 <6>[ 1.004845] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1324 21:33:40.580232 <6>[ 1.011313] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1325 21:33:40.585696 <6>[ 1.017997] sky2: driver version 1.30
1326 21:33:40.591201 <6>[ 1.022926] VFIO - User Level meta-driver version: 0.3
1327 21:33:40.596762 <6>[ 1.030266] usbcore: registered new interface driver usb-storage
1328 21:33:40.602376 <6>[ 1.036588] i2c_dev: i2c /dev entries driver
1329 21:33:40.614831 <6>[ 1.046986] sdhci: Secure Digital Host Controller Interface driver
1330 21:33:40.615396 <6>[ 1.047813] sdhci: Copyright(c) Pierre Ossman
1331 21:33:40.625616 <6>[ 1.053428] Synopsys Designware Multimedia Card Interface Driver
1332 21:33:40.631166 <6>[ 1.059922] sdhci-pltfm: SDHCI platform and OF driver helper
1333 21:33:40.636728 <6>[ 1.067599] ledtrig-cpu: registered to indicate activity on CPUs
1334 21:33:40.642286 <6>[ 1.071620] meson-sm: secure-monitor enabled
1335 21:33:40.649660 <6>[ 1.076497] usbcore: registered new interface driver usbhid
1336 21:33:40.650244 <6>[ 1.081091] usbhid: USB HID core driver
1337 21:33:40.656977 <6>[ 1.094981] NET: Registered PF_PACKET protocol family
1338 21:33:40.662552 <6>[ 1.095080] 9pnet: Installing 9P2000 support
1339 21:33:40.669748 <5>[ 1.099242] Key type dns_resolver registered
1340 21:33:40.675313 <6>[ 1.110967] registered taskstats version 1
1341 21:33:40.680849 <5>[ 1.111137] Loading compiled-in X.509 certificates
1342 21:33:40.684248 <6>[ 1.120305] Demotion targets for Node 0: null
1343 21:33:40.720750 <6>[ 1.158680] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1344 21:33:40.726260 <6>[ 1.158725] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1345 21:33:40.737281 <4>[ 1.168901] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1346 21:33:40.742853 <4>[ 1.171496] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1347 21:33:40.748351 <6>[ 1.179155] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1348 21:33:40.753879 <6>[ 1.189819] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1349 21:33:40.765023 <6>[ 1.191807] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1350 21:33:40.776229 <6>[ 1.199784] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1351 21:33:40.781691 <6>[ 1.209338] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1352 21:33:40.787210 <6>[ 1.215535] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1353 21:33:40.792745 <6>[ 1.221124] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1354 21:33:40.798283 <6>[ 1.229010] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1355 21:33:40.803815 <6>[ 1.236310] hub 1-0:1.0: USB hub found
1356 21:33:40.809421 <6>[ 1.239773] hub 1-0:1.0: 2 ports detected
1357 21:33:40.814921 <6>[ 1.245826] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1358 21:33:40.820482 <6>[ 1.252734] hub 2-0:1.0: USB hub found
1359 21:33:40.824635 <6>[ 1.256322] hub 2-0:1.0: 1 port detected
1360 21:33:40.848298 <6>[ 1.284385] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1361 21:33:40.859516 <6>[ 1.294266] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1362 21:33:40.890206 <6>[ 1.325458] Trying to probe devices needed for running init ...
1363 21:33:41.069270 <6>[ 1.503492] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1364 21:33:41.206263 <6>[ 1.638753] mmc0: new ultra high speed SDR104 SDXC card at address e624
1365 21:33:41.212389 <6>[ 1.641349] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1366 21:33:41.212876 <6>[ 1.647028] mmcblk0: p1
1367 21:33:41.249061 <6>[ 1.685580] Freeing initrd memory: 23388K
1368 21:33:41.278108 <6>[ 1.716111] hub 1-1:1.0: USB hub found
1369 21:33:41.283237 <6>[ 1.716416] hub 1-1:1.0: 4 ports detected
1370 21:33:41.348947 <6>[ 1.783600] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1371 21:33:41.390732 <6>[ 1.828764] hub 2-1:1.0: USB hub found
1372 21:33:41.396525 <6>[ 1.829583] hub 2-1:1.0: 4 ports detected
1373 21:33:53.177570 <6>[ 13.615525] clk: Disabling unused clocks
1374 21:33:53.183018 <6>[ 13.615693] PM: genpd: Disabling unused power domains
1375 21:33:53.189182 <6>[ 13.619375] ALSA device list:
1376 21:33:53.189672 <6>[ 13.622587] No soundcards found.
1377 21:33:53.197385 <6>[ 13.632427] Freeing unused kernel memory: 2240K
1378 21:33:53.197861 <6>[ 13.632503] Run /init as init process
1379 21:33:53.205479 Loading, please wait...
1380 21:33:53.243917 Starting systemd-udevd version 252.22-1~deb12u1
1381 21:33:53.680617 <3>[ 14.113017] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1382 21:33:53.686109 <4>[ 14.116177] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1383 21:33:53.694997 <6>[ 14.127350] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1384 21:33:53.700542 <6>[ 14.127566] mc: Linux media interface: v0.10
1385 21:33:53.706089 <6>[ 14.130936] meson-vrtc ff8000a8.rtc: registered as rtc0
1386 21:33:53.709605 <6>[ 14.131700] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1387 21:33:53.715044 <6>[ 14.131716] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1388 21:33:53.726201 <6>[ 14.131723] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1389 21:33:53.731740 <6>[ 14.131844] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1390 21:33:53.737315 <6>[ 14.134387] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1391 21:33:53.748367 <6>[ 14.139643] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1392 21:33:53.753945 <6>[ 14.146474] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1393 21:33:53.754464 <6>[ 14.152777] Registered IR keymap rc-empty
1394 21:33:53.765029 <6>[ 14.152866] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1395 21:33:53.770630 <6>[ 14.152990] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1396 21:33:53.776194 <6>[ 14.153820] panfrost ffe40000.gpu: clock rate = 24000000
1397 21:33:53.787265 <3>[ 14.153879] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1398 21:33:53.792825 <6>[ 14.159032] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1399 21:33:53.798499 <6>[ 14.166142] rc rc0: sw decoder init
1400 21:33:53.804664 <6>[ 14.172605] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1401 21:33:53.809580 <6>[ 14.172616] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1402 21:33:53.820589 <6>[ 14.172624] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1403 21:33:53.826216 <6>[ 14.182356] meson-ir ff808000.ir: receiver initialized
1404 21:33:53.831702 <6>[ 14.186463] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1405 21:33:53.837199 <6>[ 14.192147] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1406 21:33:53.842875 <6>[ 14.237412] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1407 21:33:53.848387 <6>[ 14.241121] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1408 21:33:53.859882 <6>[ 14.253863] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1409 21:33:53.865026 <6>[ 14.259243] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1410 21:33:53.870557 <6>[ 14.267580] videodev: Linux video capture interface: v2.00
1411 21:33:53.887149 <6>[ 14.276074] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1412 21:33:53.892258 <6>[ 14.320467] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1413 21:33:53.918221 <6>[ 14.351722] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1414 21:33:53.945993 <4>[ 14.376489] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1415 21:33:53.962262 <6>[ 14.391766] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1416 21:33:53.979226 <6>[ 14.411685] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1417 21:33:53.984895 <6>[ 14.416653] usbcore: registered new device driver onboard-usb-dev
1418 21:33:53.995839 <6>[ 14.417700] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1419 21:33:54.006930 <6>[ 14.431197] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1420 21:33:54.012514 <6>[ 14.438810] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1421 21:33:54.018064 <3>[ 14.439877] meson-drm ff900000.vpu: DSI transceiver device is disabled
1422 21:33:54.024765 <6>[ 14.453444] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1423 21:33:54.215478 <6>[ 14.630264] Console: switching to colour frame buffer device 128x48
1424 21:33:54.221429 <6>[ 14.648809] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1425 21:33:54.462285 <6>[ 14.900239] hub 1-1:1.0: USB hub found
1426 21:33:54.467658 <6>[ 14.900623] hub 1-1:1.0: 4 ports detected
1427 21:33:54.474127 <6>[ 14.906012] onboard-usb-dev 1-1: USB disconnect, device number 2
1428 21:33:54.601237 Begin: Loading essential drivers ... done.
1429 21:33:54.606768 Begin: Running /scripts/init-premount ... done.
1430 21:33:54.612239 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1431 21:33:54.623318 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1432 21:33:54.623674 Device /sys/class/net/end0 found
1433 21:33:54.623905 done.
1434 21:33:54.632610 Begin: Waiting up to 180 secs for any network device to become available ... done.
1435 21:33:54.708713 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.136902] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1436 21:33:54.709343
1437 21:33:54.805815 <6>[ 15.235631] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=28)
1438 21:33:54.819354 <6>[ 15.251704] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1439 21:33:54.825062 <6>[ 15.253904] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1440 21:33:54.834215 <6>[ 15.261418] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1441 21:33:54.868865 <6>[ 15.303486] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1442 21:33:55.070802 <6>[ 15.508189] hub 1-1:1.0: USB hub found
1443 21:33:55.076299 <6>[ 15.508548] hub 1-1:1.0: 4 ports detected
1444 21:33:55.282775 <6>[ 15.716042] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1445 21:33:55.555010 <6>[ 15.988397] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1446 21:33:56.202618 IP-Config: no response after 2 secs - giving up
1447 21:33:56.251680 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1448 21:33:57.237383 <4>[ 17.675481] rc rc0: two consecutive events of type space
1449 21:33:57.796718 <6>[ 18.228630] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1450 21:33:59.453791 IP-Config: no response after 3 secs - giving up
1451 21:33:59.500660 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1452 21:34:03.016874 IP-Config: end0 guessed broadcast address 192.168.6.255
1453 21:34:03.022024 IP-Config: end0 complete (dhcp from 192.168.6.1):
1454 21:34:03.027548 address: 192.168.6.33 broadcast: 192.168.6.255 netmask: 255.255.255.0
1455 21:34:03.038587 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1456 21:34:03.038950 rootserver: 192.168.6.1 rootpath:
1457 21:34:03.041087 filename :
1458 21:34:03.085722 done.
1459 21:34:03.096034 Begin: Running /scripts/nfs-bottom ... done.
1460 21:34:03.110165 Begin: Running /scripts/init-bottom ... done.
1461 21:34:03.449932 <30>[ 23.884425] systemd[1]: System time before build time, advancing clock.
1462 21:34:03.503167 <6>[ 23.941060] NET: Registered PF_INET6 protocol family
1463 21:34:03.508658 <6>[ 23.943335] Segment Routing with IPv6
1464 21:34:03.513835 <6>[ 23.944582] In-situ OAM (IOAM) with IPv6
1465 21:34:03.600957 <30>[ 24.007778] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1466 21:34:03.606511 <30>[ 24.035141] systemd[1]: Detected architecture arm64.
1467 21:34:03.607047
1468 21:34:03.610433 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1469 21:34:03.610955
1470 21:34:03.623081 <30>[ 24.057186] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1471 21:34:04.301948 <30>[ 24.735297] systemd[1]: Queued start job for default target graphical.target.
1472 21:34:04.345225 <30>[ 24.777785] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1473 21:34:04.351839 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1474 21:34:04.367882 <30>[ 24.800469] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1475 21:34:04.375741 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1476 21:34:04.391884 <30>[ 24.824435] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1477 21:34:04.400588 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1478 21:34:04.415656 <30>[ 24.848205] systemd[1]: Created slice user.slice - User and Session Slice.
1479 21:34:04.422195 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1480 21:34:04.440741 <30>[ 24.867734] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1481 21:34:04.444199 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1482 21:34:04.459109 <30>[ 24.891653] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1483 21:34:04.469120 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1484 21:34:04.494153 <30>[ 24.915648] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1485 21:34:04.499712 <30>[ 24.929705] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1486 21:34:04.508499 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1487 21:34:04.522982 <30>[ 24.955555] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1488 21:34:04.530197 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1489 21:34:04.542991 <30>[ 24.975584] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1490 21:34:04.551709 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1491 21:34:04.567068 <30>[ 24.999589] systemd[1]: Reached target paths.target - Path Units.
1492 21:34:04.571273 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1493 21:34:04.587024 <30>[ 25.019567] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1494 21:34:04.594356 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1495 21:34:04.607076 <30>[ 25.039606] systemd[1]: Reached target slices.target - Slice Units.
1496 21:34:04.612506 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1497 21:34:04.627070 <30>[ 25.059565] systemd[1]: Reached target swap.target - Swaps.
1498 21:34:04.630546 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1499 21:34:04.647094 <30>[ 25.079591] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1500 21:34:04.655470 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1501 21:34:04.667247 <30>[ 25.099779] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1502 21:34:04.675553 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1503 21:34:04.692353 <30>[ 25.124873] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1504 21:34:04.700505 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1505 21:34:04.716078 <30>[ 25.148557] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1506 21:34:04.725086 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1507 21:34:04.739336 <30>[ 25.171885] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1508 21:34:04.745800 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1509 21:34:04.760129 <30>[ 25.192598] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1510 21:34:04.768583 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1511 21:34:04.785024 <30>[ 25.217588] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1512 21:34:04.790601 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1513 21:34:04.807272 <30>[ 25.239785] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1514 21:34:04.814761 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1515 21:34:04.851226 <30>[ 25.283672] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1516 21:34:04.857731 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1517 21:34:04.873746 <30>[ 25.306178] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1518 21:34:04.880350 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1519 21:34:04.901675 <30>[ 25.334148] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1520 21:34:04.908237 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1521 21:34:04.932963 <30>[ 25.359899] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1522 21:34:04.944075 <30>[ 25.372973] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1523 21:34:04.950647 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1524 21:34:04.969901 <30>[ 25.402399] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1525 21:34:04.977843 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1526 21:34:04.997993 <30>[ 25.430428] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1527 21:34:05.004624 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1528 21:34:05.020877 <6>[ 25.453329] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1529 21:34:05.029866 <30>[ 25.454089] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1530 21:34:05.036508 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1531 21:34:05.053910 <30>[ 25.486419] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1532 21:34:05.062218 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1533 21:34:05.077899 <30>[ 25.510447] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1534 21:34:05.084394 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1535 21:34:05.094596 <6>[ 25.531165] fuse: init (API version 7.40)
1536 21:34:05.127490 <30>[ 25.559787] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1537 21:34:05.134171 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1538 21:34:05.156272 <30>[ 25.584293] systemd[1]: Starting systemd-journald.service - Journal Service...
1539 21:34:05.157835 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1540 21:34:05.177588 <30>[ 25.609816] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1541 21:34:05.185120 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1542 21:34:05.201567 <30>[ 25.634055] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1543 21:34:05.212758 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1544 21:34:05.229290 <30>[ 25.661751] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1545 21:34:05.238042 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1546 21:34:05.253514 <30>[ 25.685931] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1547 21:34:05.260554 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1548 21:34:05.279787 <30>[ 25.711487] systemd[1]: Started systemd-journald.service - Journal Service.
1549 21:34:05.284884 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1550 21:34:05.303505 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1551 21:34:05.320822 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1552 21:34:05.331695 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1553 21:34:05.343882 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1554 21:34:05.356251 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1555 21:34:05.371680 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1556 21:34:05.384468 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1557 21:34:05.395315 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1558 21:34:05.407200 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1559 21:34:05.425226 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1560 21:34:05.436007 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1561 21:34:05.448105 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1562 21:34:05.459305 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1563 21:34:05.473315 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1564 21:34:05.530707 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1565 21:34:05.548247 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1566 21:34:05.567422 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1567 21:34:05.587825 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1568 21:34:05.605063 <46>[ 26.036726] systemd-journald[230]: Received client request to flush runtime journal.
1569 21:34:05.614225 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1570 21:34:05.634537 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1571 21:34:05.666617 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1572 21:34:05.680179 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1573 21:34:05.691797 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1574 21:34:05.703476 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1575 21:34:05.719486 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1576 21:34:05.766777 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1577 21:34:05.801697 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1578 21:34:05.888566 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1579 21:34:05.913564 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1580 21:34:05.928584 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1581 21:34:05.939642 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1582 21:34:05.984273 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1583 21:34:06.003284 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1584 21:34:06.210532 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1585 21:34:06.258654 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1586 21:34:06.309203 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1587 21:34:06.325727 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1588 21:34:06.379828 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1589 21:34:06.393907 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1590 21:34:06.461070 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1591 21:34:06.482705 <5>[ 26.916181] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1592 21:34:06.532773 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1593 21:34:06.537357 <5>[ 26.972520] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1594 21:34:06.542792 <5>[ 26.974091] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1595 21:34:06.553917 <4>[ 26.981711] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1596 21:34:06.559203 <6>[ 26.989913] cfg80211: failed to load regulatory.db
1597 21:34:06.604883 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1598 21:34:06.618750 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1599 21:34:06.631469 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1600 21:34:06.651326 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1601 21:34:06.674689 <46>[ 27.096095] systemd-journald[230]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1602 21:34:06.687600 <46>[ 27.108670] systemd-journald[230]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1603 21:34:06.701728 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1604 21:34:06.737883 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1605 21:34:06.761782 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1606 21:34:06.792758 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1607 21:34:06.837958 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1608 21:34:06.855924 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1609 21:34:06.876887 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1610 21:34:06.896369 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1611 21:34:06.958802 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1612 21:34:06.975933 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1613 21:34:06.987463 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1614 21:34:07.006031 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1615 21:34:07.025513 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1616 21:34:07.043454 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1617 21:34:07.053928 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1618 21:34:07.068806 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1619 21:34:07.086092 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1620 21:34:07.102073 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1621 21:34:07.134915 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1622 21:34:07.152903 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1623 21:34:07.176966 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1624 21:34:07.234984 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1625 21:34:07.248944 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1626 21:34:07.264546 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1627 21:34:07.282765 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1628 21:34:07.300631 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1629 21:34:07.316698 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1630 21:34:07.329987 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1631 21:34:07.370400 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1632 21:34:07.386520 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1633 21:34:07.401431 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1634 21:34:07.420275 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1635 21:34:07.435905 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1636 21:34:07.450818 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1637 21:34:07.499139 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1638 21:34:07.569755 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1639 21:34:07.649313
1640 21:34:07.649756 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1641 21:34:07.650048
1642 21:34:07.656503 debian-bookworm-arm64 login: root (automatic login)
1643 21:34:07.656982
1644 21:34:07.772344 Linux debian-bookworm-arm64 6.11.0-rc5 #1 SMP PREEMPT Fri Aug 30 20:46:46 UTC 2024 aarch64
1645 21:34:07.772769
1646 21:34:07.777759 The programs included with the Debian GNU/Linux system are free software;
1647 21:34:07.786906 the exact distribution terms for each program are described in the
1648 21:34:07.787251 individual files in /usr/share/doc/*/copyright.
1649 21:34:07.787514
1650 21:34:07.792460 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1651 21:34:07.797062 permitted by applicable law.
1652 21:34:08.479329 Matched prompt #10: / #
1654 21:34:08.480934 Setting prompt string to ['/ #']
1655 21:34:08.481682 end: 2.4.4.1 login-action (duration 00:00:29) [common]
1657 21:34:08.483435 end: 2.4.4 auto-login-action (duration 00:00:29) [common]
1658 21:34:08.484152 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
1659 21:34:08.484717 Setting prompt string to ['/ #']
1660 21:34:08.485237 Forcing a shell prompt, looking for ['/ #']
1662 21:34:08.536399 / #
1663 21:34:08.537154 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1664 21:34:08.537743 Waiting using forced prompt support (timeout 00:02:30)
1665 21:34:08.543172
1666 21:34:08.544209 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1667 21:34:08.544929 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
1668 21:34:08.545516 Sending with 10 millisecond of delay
1670 21:34:13.534292 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/680092/extract-nfsrootfs-svn5hbtq'
1671 21:34:13.545204 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/680092/extract-nfsrootfs-svn5hbtq'
1672 21:34:13.545930 Sending with 10 millisecond of delay
1674 21:34:15.645489 / # export NFS_SERVER_IP='192.168.6.2'
1675 21:34:15.656462 export NFS_SERVER_IP='192.168.6.2'
1676 21:34:15.657368 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1677 21:34:15.657949 end: 2.4 uboot-commands (duration 00:01:55) [common]
1678 21:34:15.658562 end: 2 uboot-action (duration 00:01:55) [common]
1679 21:34:15.659161 start: 3 lava-test-retry (timeout 00:06:45) [common]
1680 21:34:15.659804 start: 3.1 lava-test-shell (timeout 00:06:45) [common]
1681 21:34:15.660550 Using namespace: common
1683 21:34:15.761794 / # #
1684 21:34:15.762784 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1685 21:34:15.773531 #
1686 21:34:15.774534 Using /lava-680092
1688 21:34:15.875722 / # export SHELL=/bin/bash
1689 21:34:15.881368 export SHELL=/bin/bash
1691 21:34:15.982842 / # . /lava-680092/environment
1692 21:34:15.986754 . /lava-680092/environment
1694 21:34:16.091144 / # /lava-680092/bin/lava-test-runner /lava-680092/0
1695 21:34:16.091923 Test shell timeout: 10s (minimum of the action and connection timeout)
1696 21:34:16.095634 /lava-680092/bin/lava-test-runner /lava-680092/0
1697 21:34:16.282655 + export TESTRUN_ID=0_timesync-off
1698 21:34:16.289215 + TESTRUN_ID=0_timesync-off
1699 21:34:16.289817 + cd /lava-680092/0/tests/0_timesync-off
1700 21:34:16.290380 ++ cat uuid
1701 21:34:16.294782 + UUID=680092_1.6.2.4.1
1702 21:34:16.295455 + set +x
1703 21:34:16.297015 <LAVA_SIGNAL_STARTRUN 0_timesync-off 680092_1.6.2.4.1>
1704 21:34:16.297916 Received signal: <STARTRUN> 0_timesync-off 680092_1.6.2.4.1
1705 21:34:16.298496 Starting test lava.0_timesync-off (680092_1.6.2.4.1)
1706 21:34:16.299135 Skipping test definition patterns.
1707 21:34:16.302631 + systemctl stop systemd-timesyncd
1708 21:34:16.365265 + set +x
1709 21:34:16.366003 <LAVA_SIGNAL_ENDRUN 0_timesync-off 680092_1.6.2.4.1>
1710 21:34:16.366813 Received signal: <ENDRUN> 0_timesync-off 680092_1.6.2.4.1
1711 21:34:16.367429 Ending use of test pattern.
1712 21:34:16.367949 Ending test lava.0_timesync-off (680092_1.6.2.4.1), duration 0.07
1714 21:34:16.466027 + export TESTRUN_ID=1_kselftest-alsa
1715 21:34:16.473291 + TESTRUN_ID=1_kselftest-alsa
1716 21:34:16.473910 + cd /lava-680092/0/tests/1_kselftest-alsa
1717 21:34:16.474430 ++ cat uuid
1718 21:34:16.478775 + UUID=680092_1.6.2.4.5
1719 21:34:16.479407 + set +x
1720 21:34:16.484400 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 680092_1.6.2.4.5>
1721 21:34:16.485034 + cd ./automated/linux/kselftest/
1722 21:34:16.485839 Received signal: <STARTRUN> 1_kselftest-alsa 680092_1.6.2.4.5
1723 21:34:16.486364 Starting test lava.1_kselftest-alsa (680092_1.6.2.4.5)
1724 21:34:16.486974 Skipping test definition patterns.
1725 21:34:16.513158 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1726 21:34:16.536933 INFO: install_deps skipped
1727 21:34:16.666745 --2024-08-30 21:34:16-- http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/clang-16/kselftest.tar.xz
1728 21:34:16.928425 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1729 21:34:17.074422 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1730 21:34:17.218127 HTTP request sent, awaiting response... 200 OK
1731 21:34:17.218918 Length: 4390908 (4.2M) [application/octet-stream]
1732 21:34:17.223428 Saving to: 'kselftest_armhf.tar.gz'
1733 21:34:17.224019
1734 21:34:18.387214
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 175KB/s
kselftest_armhf.tar 5%[> ] 218.67K 379KB/s
kselftest_armhf.tar 20%[===> ] 891.29K 1.00MB/s
kselftest_armhf.tar 83%[===============> ] 3.51M 3.04MB/s
kselftest_armhf.tar 100%[===================>] 4.19M 3.60MB/s in 1.2s
1735 21:34:18.387726
1736 21:34:18.446415 2024-08-30 21:34:18 (3.60 MB/s) - 'kselftest_armhf.tar.gz' saved [4390908/4390908]
1737 21:34:18.446844
1738 21:34:26.452228 skiplist:
1739 21:34:26.452663 ========================================
1740 21:34:26.457855 ========================================
1741 21:34:26.501360 alsa:mixer-test
1742 21:34:26.501761 alsa:pcm-test
1743 21:34:26.502000 alsa:test-pcmtest-driver
1744 21:34:26.517446 ============== Tests to run ===============
1745 21:34:26.517807 alsa:mixer-test
1746 21:34:26.523197 alsa:pcm-test
1747 21:34:26.523517 alsa:test-pcmtest-driver
1748 21:34:26.528799 ===========End Tests to run ===============
1749 21:34:26.529248 shardfile-alsa pass
1750 21:34:26.636356 <12>[ 47.071324] kselftest: Running tests in alsa
1751 21:34:26.639720 TAP version 13
1752 21:34:26.648866 1..3
1753 21:34:26.668375 # timeout set to 45
1754 21:34:26.668968 # selftests: alsa: mixer-test
1755 21:34:26.874940 # TAP version 13
1756 21:34:26.875563 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1757 21:34:26.880287 # 1..427
1758 21:34:26.880827 # ok 1 get_value.LCALTA.60
1759 21:34:26.881311 # # LCALTA.60 TDMOUT_A SRC SEL
1760 21:34:26.885825 # ok 2 name.LCALTA.60
1761 21:34:26.886340 # ok 3 write_default.LCALTA.60
1762 21:34:26.889496 # ok 4 write_valid.LCALTA.60
1763 21:34:26.894901 # ok 5 write_invalid.LCALTA.60
1764 21:34:26.895430 # ok 6 event_missing.LCALTA.60
1765 21:34:26.900674 # ok 7 event_spurious.LCALTA.60
1766 21:34:26.901213 # ok 8 get_value.LCALTA.59
1767 21:34:26.906198 # # LCALTA.59 TDMOUT_B SRC SEL
1768 21:34:26.906724 # ok 9 name.LCALTA.59
1769 21:34:26.909963 # ok 10 write_default.LCALTA.59
1770 21:34:26.910484 # ok 11 write_valid.LCALTA.59
1771 21:34:26.915385 # ok 12 write_invalid.LCALTA.59
1772 21:34:26.915924 # ok 13 event_missing.LCALTA.59
1773 21:34:26.920968 # ok 14 event_spurious.LCALTA.59
1774 21:34:26.921490 # ok 15 get_value.LCALTA.58
1775 21:34:26.926459 # # LCALTA.58 TDMOUT_C SRC SEL
1776 21:34:26.926967 # ok 16 name.LCALTA.58
1777 21:34:26.930352 # ok 17 write_default.LCALTA.58
1778 21:34:26.935798 # ok 18 write_valid.LCALTA.58
1779 21:34:26.936343 # ok 19 write_invalid.LCALTA.58
1780 21:34:26.941263 # ok 20 event_missing.LCALTA.58
1781 21:34:26.941776 # ok 21 event_spurious.LCALTA.58
1782 21:34:26.947047 # ok 22 get_value.LCALTA.57
1783 21:34:26.947578 # # LCALTA.57 TDMIN_A SRC SEL
1784 21:34:26.948075 # ok 23 name.LCALTA.57
1785 21:34:26.950614 # ok 24 write_default.LCALTA.57
1786 21:34:26.955893 # ok 25 write_valid.LCALTA.57
1787 21:34:26.956438 # ok 26 write_invalid.LCALTA.57
1788 21:34:26.961516 # ok 27 event_missing.LCALTA.57
1789 21:34:26.962025 # ok 28 event_spurious.LCALTA.57
1790 21:34:26.967027 # ok 29 get_value.LCALTA.56
1791 21:34:26.967573 # # LCALTA.56 TDMIN_B SRC SEL
1792 21:34:26.972634 # ok 30 name.LCALTA.56
1793 21:34:26.973183 # ok 31 write_default.LCALTA.56
1794 21:34:26.978102 # ok 32 write_valid.LCALTA.56
1795 21:34:26.978630 # ok 33 write_invalid.LCALTA.56
1796 21:34:26.983653 # ok 34 event_missing.LCALTA.56
1797 21:34:26.984209 # ok 35 event_spurious.LCALTA.56
1798 21:34:26.989219 # ok 36 get_value.LCALTA.55
1799 21:34:26.989742 # # LCALTA.55 TDMIN_C SRC SEL
1800 21:34:27.000326 <3>[ 47.425396] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1801 21:34:27.005827 # ok 37 name.LCALTA.55
1802 21:34:27.006363 # ok 38 write_default.LCALTA.55
1803 21:34:27.011387 # ok 39 write_valid.LCALTA.55
1804 21:34:27.011906 # ok 40 write_invalid.LCALTA.55
1805 21:34:27.016968 # ok 41 event_missing.LCALTA.55
1806 21:34:27.017512 # ok 42 event_spurious.LCALTA.55
1807 21:34:27.022428 # ok 43 get_value.LCALTA.54
1808 21:34:27.022943 # # LCALTA.54 ACODEC Left DAC Sel
1809 21:34:27.028054 # ok 44 name.LCALTA.54
1810 21:34:27.028564 # ok 45 write_default.LCALTA.54
1811 21:34:27.033567 # ok 46 write_valid.LCALTA.54
1812 21:34:27.034073 # ok 47 write_invalid.LCALTA.54
1813 21:34:27.039066 # ok 48 event_missing.LCALTA.54
1814 21:34:27.039582 # ok 49 event_spurious.LCALTA.54
1815 21:34:27.044635 # ok 50 get_value.LCALTA.53
1816 21:34:27.045153 # # LCALTA.53 ACODEC Right DAC Sel
1817 21:34:27.050313 # ok 51 name.LCALTA.53
1818 21:34:27.050820 # ok 52 write_default.LCALTA.53
1819 21:34:27.055774 # ok 53 write_valid.LCALTA.53
1820 21:34:27.056350 # ok 54 write_invalid.LCALTA.53
1821 21:34:27.061237 # ok 55 event_missing.LCALTA.53
1822 21:34:27.061754 # ok 56 event_spurious.LCALTA.53
1823 21:34:27.066849 # ok 57 get_value.LCALTA.52
1824 21:34:27.067363 # # LCALTA.52 TOACODEC OUT EN Switch
1825 21:34:27.072385 # ok 58 name.LCALTA.52
1826 21:34:27.072889 # ok 59 write_default.LCALTA.52
1827 21:34:27.077916 # ok 60 write_valid.LCALTA.52
1828 21:34:27.078432 # ok 61 write_invalid.LCALTA.52
1829 21:34:27.083470 # ok 62 event_missing.LCALTA.52
1830 21:34:27.084030 # ok 63 event_spurious.LCALTA.52
1831 21:34:27.089076 # ok 64 get_value.LCALTA.51
1832 21:34:27.089591 # # LCALTA.51 TOACODEC SRC
1833 21:34:27.090036 # ok 65 name.LCALTA.51
1834 21:34:27.094763 # ok 66 write_default.LCALTA.51
1835 21:34:27.095303 # ok 67 write_valid.LCALTA.51
1836 21:34:27.100141 # ok 68 write_invalid.LCALTA.51
1837 21:34:27.100666 # ok 69 event_missing.LCALTA.51
1838 21:34:27.105661 # ok 70 event_spurious.LCALTA.51
1839 21:34:27.106183 # ok 71 get_value.LCALTA.50
1840 21:34:27.111250 # # LCALTA.50 TOHDMITX SPDIF SRC
1841 21:34:27.111766 # ok 72 name.LCALTA.50
1842 21:34:27.116794 # ok 73 write_default.LCALTA.50
1843 21:34:27.117301 # ok 74 write_valid.LCALTA.50
1844 21:34:27.122252 # ok 75 write_invalid.LCALTA.50
1845 21:34:27.122771 # ok 76 event_missing.LCALTA.50
1846 21:34:27.127867 # ok 77 event_spurious.LCALTA.50
1847 21:34:27.128421 # ok 78 get_value.LCALTA.49
1848 21:34:27.133424 # # LCALTA.49 TOHDMITX Switch
1849 21:34:27.133931 # ok 79 name.LCALTA.49
1850 21:34:27.139023 # ok 80 write_default.LCALTA.49
1851 21:34:27.139534 # ok 81 write_valid.LCALTA.49
1852 21:34:27.144525 # ok 82 write_invalid.LCALTA.49
1853 21:34:27.145058 # ok 83 event_missing.LCALTA.49
1854 21:34:27.150069 # ok 84 event_spurious.LCALTA.49
1855 21:34:27.150599 # ok 85 get_value.LCALTA.48
1856 21:34:27.155594 # # LCALTA.48 TOHDMITX I2S SRC
1857 21:34:27.156186 # ok 86 name.LCALTA.48
1858 21:34:27.161188 # ok 87 write_default.LCALTA.48
1859 21:34:27.161699 # ok 88 write_valid.LCALTA.48
1860 21:34:27.166668 # ok 89 write_invalid.LCALTA.48
1861 21:34:27.167196 # ok 90 event_missing.LCALTA.48
1862 21:34:27.172270 # ok 91 event_spurious.LCALTA.48
1863 21:34:27.172806 # ok 92 get_value.LCALTA.47
1864 21:34:27.177771 # # LCALTA.47 TODDR_C SRC SEL
1865 21:34:27.178280 # ok 93 name.LCALTA.47
1866 21:34:27.178725 # ok 94 write_default.LCALTA.47
1867 21:34:27.183314 # ok 95 write_valid.LCALTA.47
1868 21:34:27.183832 # ok 96 write_invalid.LCALTA.47
1869 21:34:27.188914 # ok 97 event_missing.LCALTA.47
1870 21:34:27.194429 # ok 98 event_spurious.LCALTA.47
1871 21:34:27.194950 # ok 99 get_value.LCALTA.46
1872 21:34:27.195402 # # LCALTA.46 TODDR_B SRC SEL
1873 21:34:27.200018 # ok 100 name.LCALTA.46
1874 21:34:27.200534 # ok 101 write_default.LCALTA.46
1875 21:34:27.205546 # ok 102 write_valid.LCALTA.46
1876 21:34:27.206094 # ok 103 write_invalid.LCALTA.46
1877 21:34:27.211095 # ok 104 event_missing.LCALTA.46
1878 21:34:27.216637 # ok 105 event_spurious.LCALTA.46
1879 21:34:27.217147 # ok 106 get_value.LCALTA.45
1880 21:34:27.217596 # # LCALTA.45 TODDR_A SRC SEL
1881 21:34:27.222194 # ok 107 name.LCALTA.45
1882 21:34:27.222709 # ok 108 write_default.LCALTA.45
1883 21:34:27.227727 # ok 109 write_valid.LCALTA.45
1884 21:34:27.228313 # ok 110 write_invalid.LCALTA.45
1885 21:34:27.233261 # ok 111 event_missing.LCALTA.45
1886 21:34:27.233787 # ok 112 event_spurious.LCALTA.45
1887 21:34:27.238856 # ok 113 get_value.LCALTA.44
1888 21:34:27.239362 # # LCALTA.44 FRDDR_C SINK 3 SEL
1889 21:34:27.244335 # ok 114 name.LCALTA.44
1890 21:34:27.244855 # ok 115 write_default.LCALTA.44
1891 21:34:27.249911 # ok 116 write_valid.LCALTA.44
1892 21:34:27.250443 # ok 117 write_invalid.LCALTA.44
1893 21:34:27.255450 # ok 118 event_missing.LCALTA.44
1894 21:34:27.260993 # ok 119 event_spurious.LCALTA.44
1895 21:34:27.261530 # ok 120 get_value.LCALTA.43
1896 21:34:27.266538 # # LCALTA.43 FRDDR_C SINK 2 SEL
1897 21:34:27.267067 # ok 121 name.LCALTA.43
1898 21:34:27.267516 # ok 122 write_default.LCALTA.43
1899 21:34:27.272076 # ok 123 write_valid.LCALTA.43
1900 21:34:27.272596 # ok 124 write_invalid.LCALTA.43
1901 21:34:27.277641 # ok 125 event_missing.LCALTA.43
1902 21:34:27.283216 # ok 126 event_spurious.LCALTA.43
1903 21:34:27.283726 # ok 127 get_value.LCALTA.42
1904 21:34:27.288766 # # LCALTA.42 FRDDR_C SINK 1 SEL
1905 21:34:27.289298 # ok 128 name.LCALTA.42
1906 21:34:27.289751 # ok 129 write_default.LCALTA.42
1907 21:34:27.294289 # ok 130 write_valid.LCALTA.42
1908 21:34:27.299823 # ok 131 write_invalid.LCALTA.42
1909 21:34:27.300390 # ok 132 event_missing.LCALTA.42
1910 21:34:27.305370 # ok 133 event_spurious.LCALTA.42
1911 21:34:27.305894 # ok 134 get_value.LCALTA.41
1912 21:34:27.310962 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1913 21:34:27.311512 # ok 135 name.LCALTA.41
1914 21:34:27.316469 # ok 136 write_default.LCALTA.41
1915 21:34:27.317013 # ok 137 write_valid.LCALTA.41
1916 21:34:27.322010 # ok 138 write_invalid.LCALTA.41
1917 21:34:27.322541 # ok 139 event_missing.LCALTA.41
1918 21:34:27.327588 # ok 140 event_spurious.LCALTA.41
1919 21:34:27.328135 # ok 141 get_value.LCALTA.40
1920 21:34:27.333100 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1921 21:34:27.333617 # ok 142 name.LCALTA.40
1922 21:34:27.338658 # ok 143 write_default.LCALTA.40
1923 21:34:27.339211 # ok 144 write_valid.LCALTA.40
1924 21:34:27.344175 # ok 145 write_invalid.LCALTA.40
1925 21:34:27.344702 # ok 146 event_missing.LCALTA.40
1926 21:34:27.349725 # ok 147 event_spurious.LCALTA.40
1927 21:34:27.350259 # ok 148 get_value.LCALTA.39
1928 21:34:27.355289 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1929 21:34:27.355821 # ok 149 name.LCALTA.39
1930 21:34:27.360801 # ok 150 write_default.LCALTA.39
1931 21:34:27.361363 # ok 151 write_valid.LCALTA.39
1932 21:34:27.366341 # ok 152 write_invalid.LCALTA.39
1933 21:34:27.366881 # ok 153 event_missing.LCALTA.39
1934 21:34:27.371888 # ok 154 event_spurious.LCALTA.39
1935 21:34:27.372448 # ok 155 get_value.LCALTA.38
1936 21:34:27.377453 # # LCALTA.38 FRDDR_B SINK 3 SEL
1937 21:34:27.377979 # ok 156 name.LCALTA.38
1938 21:34:27.383008 # ok 157 write_default.LCALTA.38
1939 21:34:27.383529 # ok 158 write_valid.LCALTA.38
1940 21:34:27.388511 # ok 159 write_invalid.LCALTA.38
1941 21:34:27.389025 # ok 160 event_missing.LCALTA.38
1942 21:34:27.394129 # ok 161 event_spurious.LCALTA.38
1943 21:34:27.394636 # ok 162 get_value.LCALTA.37
1944 21:34:27.399664 # # LCALTA.37 FRDDR_B SINK 2 SEL
1945 21:34:27.400229 # ok 163 name.LCALTA.37
1946 21:34:27.405177 # ok 164 write_default.LCALTA.37
1947 21:34:27.405696 # ok 165 write_valid.LCALTA.37
1948 21:34:27.410700 # ok 166 write_invalid.LCALTA.37
1949 21:34:27.411239 # ok 167 event_missing.LCALTA.37
1950 21:34:27.416293 # ok 168 event_spurious.LCALTA.37
1951 21:34:27.416814 # ok 169 get_value.LCALTA.36
1952 21:34:27.421809 # # LCALTA.36 FRDDR_B SINK 1 SEL
1953 21:34:27.422336 # ok 170 name.LCALTA.36
1954 21:34:27.427425 # ok 171 write_default.LCALTA.36
1955 21:34:27.427928 # ok 172 write_valid.LCALTA.36
1956 21:34:27.432844 # ok 173 write_invalid.LCALTA.36
1957 21:34:27.433359 # ok 174 event_missing.LCALTA.36
1958 21:34:27.438326 # ok 175 event_spurious.LCALTA.36
1959 21:34:27.438801 # ok 176 get_value.LCALTA.35
1960 21:34:27.443928 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1961 21:34:27.444430 # ok 177 name.LCALTA.35
1962 21:34:27.449478 # ok 178 write_default.LCALTA.35
1963 21:34:27.455025 # ok 179 write_valid.LCALTA.35
1964 21:34:27.455647 # ok 180 write_invalid.LCALTA.35
1965 21:34:27.460539 # ok 181 event_missing.LCALTA.35
1966 21:34:27.461051 # ok 182 event_spurious.LCALTA.35
1967 21:34:27.466098 # ok 183 get_value.LCALTA.34
1968 21:34:27.466600 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1969 21:34:27.471701 # ok 184 name.LCALTA.34
1970 21:34:27.472340 # ok 185 write_default.LCALTA.34
1971 21:34:27.477210 # ok 186 write_valid.LCALTA.34
1972 21:34:27.477714 # ok 187 write_invalid.LCALTA.34
1973 21:34:27.482734 # ok 188 event_missing.LCALTA.34
1974 21:34:27.483244 # ok 189 event_spurious.LCALTA.34
1975 21:34:27.488281 # ok 190 get_value.LCALTA.33
1976 21:34:27.488845 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1977 21:34:27.493807 # ok 191 name.LCALTA.33
1978 21:34:27.494307 # ok 192 write_default.LCALTA.33
1979 21:34:27.499358 # ok 193 write_valid.LCALTA.33
1980 21:34:27.499854 # ok 194 write_invalid.LCALTA.33
1981 21:34:27.504895 # ok 195 event_missing.LCALTA.33
1982 21:34:27.505499 # ok 196 event_spurious.LCALTA.33
1983 21:34:27.510446 # ok 197 get_value.LCALTA.32
1984 21:34:27.510943 # # LCALTA.32 FRDDR_A SINK 3 SEL
1985 21:34:27.516053 # ok 198 name.LCALTA.32
1986 21:34:27.516577 # ok 199 write_default.LCALTA.32
1987 21:34:27.521585 # ok 200 write_valid.LCALTA.32
1988 21:34:27.522085 # ok 201 write_invalid.LCALTA.32
1989 21:34:27.527071 # ok 202 event_missing.LCALTA.32
1990 21:34:27.527579 # ok 203 event_spurious.LCALTA.32
1991 21:34:27.532691 # ok 204 get_value.LCALTA.31
1992 21:34:27.533207 # # LCALTA.31 FRDDR_A SINK 2 SEL
1993 21:34:27.538181 # ok 205 name.LCALTA.31
1994 21:34:27.538677 # ok 206 write_default.LCALTA.31
1995 21:34:27.543746 # ok 207 write_valid.LCALTA.31
1996 21:34:27.544347 # ok 208 write_invalid.LCALTA.31
1997 21:34:27.549307 # ok 209 event_missing.LCALTA.31
1998 21:34:27.549806 # ok 210 event_spurious.LCALTA.31
1999 21:34:27.554841 # ok 211 get_value.LCALTA.30
2000 21:34:27.555444 # # LCALTA.30 FRDDR_A SINK 1 SEL
2001 21:34:27.560361 # ok 212 name.LCALTA.30
2002 21:34:27.560851 # ok 213 write_default.LCALTA.30
2003 21:34:27.565994 # ok 214 write_valid.LCALTA.30
2004 21:34:27.566629 # ok 215 write_invalid.LCALTA.30
2005 21:34:27.571559 # ok 216 event_missing.LCALTA.30
2006 21:34:27.572086 # ok 217 event_spurious.LCALTA.30
2007 21:34:27.577038 # ok 218 get_value.LCALTA.29
2008 21:34:27.582600 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2009 21:34:27.583130 # ok 219 name.LCALTA.29
2010 21:34:27.583586 # ok 220 write_default.LCALTA.29
2011 21:34:27.588145 # ok 221 write_valid.LCALTA.29
2012 21:34:27.588650 # ok 222 write_invalid.LCALTA.29
2013 21:34:27.593694 # ok 223 event_missing.LCALTA.29
2014 21:34:27.599195 # ok 224 event_spurious.LCALTA.29
2015 21:34:27.599691 # ok 225 get_value.LCALTA.28
2016 21:34:27.604736 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2017 21:34:27.605224 # ok 226 name.LCALTA.28
2018 21:34:27.610324 # ok 227 write_default.LCALTA.28
2019 21:34:27.610809 # ok 228 write_valid.LCALTA.28
2020 21:34:27.615873 # ok 229 write_invalid.LCALTA.28
2021 21:34:27.616413 # ok 230 event_missing.LCALTA.28
2022 21:34:27.621460 # ok 231 event_spurious.LCALTA.28
2023 21:34:27.621935 # ok 232 get_value.LCALTA.27
2024 21:34:27.626949 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2025 21:34:27.627475 # ok 233 name.LCALTA.27
2026 21:34:27.632562 # ok 234 write_default.LCALTA.27
2027 21:34:27.633496 # ok 235 write_valid.LCALTA.27
2028 21:34:27.638016 # ok 236 write_invalid.LCALTA.27
2029 21:34:27.638522 # ok 237 event_missing.LCALTA.27
2030 21:34:27.643603 # ok 238 event_spurious.LCALTA.27
2031 21:34:27.644182 # ok 239 get_value.LCALTA.26
2032 21:34:27.649114 # # LCALTA.26 ELD
2033 21:34:27.649667 # ok 240 name.LCALTA.26
2034 21:34:27.650157 # # ELD is not writeable
2035 21:34:27.654663 # ok 241 # SKIP write_default.LCALTA.26
2036 21:34:27.655151 # # ELD is not writeable
2037 21:34:27.660236 # ok 242 # SKIP write_valid.LCALTA.26
2038 21:34:27.660726 # # ELD is not writeable
2039 21:34:27.665757 # ok 243 # SKIP write_invalid.LCALTA.26
2040 21:34:27.671317 # ok 244 event_missing.LCALTA.26
2041 21:34:27.671827 # ok 245 event_spurious.LCALTA.26
2042 21:34:27.676821 # ok 246 get_value.LCALTA.25
2043 21:34:27.677290 # # LCALTA.25 IEC958 Playback Default
2044 21:34:27.682433 # ok 247 name.LCALTA.25
2045 21:34:27.682980 # ok 248 write_default.LCALTA.25
2046 21:34:27.688029 # ok 249 # SKIP write_valid.LCALTA.25
2047 21:34:27.688582 # ok 250 # SKIP write_invalid.LCALTA.25
2048 21:34:27.693540 # ok 251 event_missing.LCALTA.25
2049 21:34:27.694022 # ok 252 event_spurious.LCALTA.25
2050 21:34:27.699043 # ok 253 get_value.LCALTA.24
2051 21:34:27.699612 # # LCALTA.24 IEC958 Playback Mask
2052 21:34:27.704617 # ok 254 name.LCALTA.24
2053 21:34:27.710123 # # IEC958 Playback Mask is not writeable
2054 21:34:27.710587 # ok 255 # SKIP write_default.LCALTA.24
2055 21:34:27.715672 # # IEC958 Playback Mask is not writeable
2056 21:34:27.716173 # ok 256 # SKIP write_valid.LCALTA.24
2057 21:34:27.721240 # # IEC958 Playback Mask is not writeable
2058 21:34:27.726783 # ok 257 # SKIP write_invalid.LCALTA.24
2059 21:34:27.727273 # ok 258 event_missing.LCALTA.24
2060 21:34:27.732368 # ok 259 event_spurious.LCALTA.24
2061 21:34:27.732857 # ok 260 get_value.LCALTA.23
2062 21:34:27.738010 # # LCALTA.23 Playback Channel Map
2063 21:34:27.738501 # ok 261 name.LCALTA.23
2064 21:34:27.743440 # # Playback Channel Map is not writeable
2065 21:34:27.748956 # ok 262 # SKIP write_default.LCALTA.23
2066 21:34:27.749426 # # Playback Channel Map is not writeable
2067 21:34:27.754594 # ok 263 # SKIP write_valid.LCALTA.23
2068 21:34:27.760078 # # Playback Channel Map is not writeable
2069 21:34:27.760556 # ok 264 # SKIP write_invalid.LCALTA.23
2070 21:34:27.765597 # ok 265 event_missing.LCALTA.23
2071 21:34:27.766052 # ok 266 event_spurious.LCALTA.23
2072 21:34:27.771184 # ok 267 get_value.LCALTA.22
2073 21:34:27.771764 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2074 21:34:27.776692 # ok 268 name.LCALTA.22
2075 21:34:27.777167 # ok 269 write_default.LCALTA.22
2076 21:34:27.782238 # ok 270 write_valid.LCALTA.22
2077 21:34:27.782712 # ok 271 write_invalid.LCALTA.22
2078 21:34:27.787795 # ok 272 event_missing.LCALTA.22
2079 21:34:27.788401 # ok 273 event_spurious.LCALTA.22
2080 21:34:27.793306 # ok 274 get_value.LCALTA.21
2081 21:34:27.793779 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2082 21:34:27.798876 # ok 275 name.LCALTA.21
2083 21:34:27.799357 # ok 276 write_default.LCALTA.21
2084 21:34:27.804418 # ok 277 write_valid.LCALTA.21
2085 21:34:27.804998 # ok 278 write_invalid.LCALTA.21
2086 21:34:27.809965 # ok 279 event_missing.LCALTA.21
2087 21:34:27.815636 # ok 280 event_spurious.LCALTA.21
2088 21:34:27.816142 # ok 281 get_value.LCALTA.20
2089 21:34:27.821162 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2090 21:34:27.821639 # ok 282 name.LCALTA.20
2091 21:34:27.822065 # ok 283 write_default.LCALTA.20
2092 21:34:27.826621 # ok 284 write_valid.LCALTA.20
2093 21:34:27.832223 # ok 285 write_invalid.LCALTA.20
2094 21:34:27.832791 # ok 286 event_missing.LCALTA.20
2095 21:34:27.837716 # ok 287 event_spurious.LCALTA.20
2096 21:34:27.838194 # ok 288 get_value.LCALTA.19
2097 21:34:27.843253 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2098 21:34:27.843711 # ok 289 name.LCALTA.19
2099 21:34:27.848872 # ok 290 write_default.LCALTA.19
2100 21:34:27.849416 # ok 291 write_valid.LCALTA.19
2101 21:34:27.854383 # ok 292 write_invalid.LCALTA.19
2102 21:34:27.854860 # ok 293 event_missing.LCALTA.19
2103 21:34:27.860000 # ok 294 event_spurious.LCALTA.19
2104 21:34:27.860487 # ok 295 get_value.LCALTA.18
2105 21:34:27.865486 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2106 21:34:27.866055 # ok 296 name.LCALTA.18
2107 21:34:27.871030 # ok 297 write_default.LCALTA.18
2108 21:34:27.871509 # ok 298 write_valid.LCALTA.18
2109 21:34:27.876604 # ok 299 write_invalid.LCALTA.18
2110 21:34:27.877078 # ok 300 event_missing.LCALTA.18
2111 21:34:27.882105 # ok 301 event_spurious.LCALTA.18
2112 21:34:27.882689 # ok 302 get_value.LCALTA.17
2113 21:34:27.887650 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2114 21:34:27.888224 # ok 303 name.LCALTA.17
2115 21:34:27.893190 # ok 304 write_default.LCALTA.17
2116 21:34:27.893649 # ok 305 write_valid.LCALTA.17
2117 21:34:27.898805 # ok 306 write_invalid.LCALTA.17
2118 21:34:27.899276 # ok 307 event_missing.LCALTA.17
2119 21:34:27.904341 # ok 308 event_spurious.LCALTA.17
2120 21:34:27.904914 # ok 309 get_value.LCALTA.16
2121 21:34:27.909905 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2122 21:34:27.910386 # ok 310 name.LCALTA.16
2123 21:34:27.915371 # ok 311 write_default.LCALTA.16
2124 21:34:27.915845 # ok 312 write_valid.LCALTA.16
2125 21:34:27.920950 # ok 313 write_invalid.LCALTA.16
2126 21:34:27.926474 # ok 314 event_missing.LCALTA.16
2127 21:34:27.927037 # ok 315 event_spurious.LCALTA.16
2128 21:34:27.932086 # ok 316 get_value.LCALTA.15
2129 21:34:27.932632 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2130 21:34:27.937603 # ok 317 name.LCALTA.15
2131 21:34:27.938082 # ok 318 write_default.LCALTA.15
2132 21:34:27.943090 # ok 319 write_valid.LCALTA.15
2133 21:34:27.943573 # ok 320 write_invalid.LCALTA.15
2134 21:34:27.948630 # ok 321 event_missing.LCALTA.15
2135 21:34:27.949103 # ok 322 event_spurious.LCALTA.15
2136 21:34:27.954162 # ok 323 get_value.LCALTA.14
2137 21:34:27.954631 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2138 21:34:27.959756 # ok 324 name.LCALTA.14
2139 21:34:27.960358 # ok 325 write_default.LCALTA.14
2140 21:34:27.965280 # ok 326 write_valid.LCALTA.14
2141 21:34:27.965756 # ok 327 write_invalid.LCALTA.14
2142 21:34:27.970826 # ok 328 event_missing.LCALTA.14
2143 21:34:27.971317 # ok 329 event_spurious.LCALTA.14
2144 21:34:27.976358 # ok 330 get_value.LCALTA.13
2145 21:34:27.976844 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2146 21:34:27.981911 # ok 331 name.LCALTA.13
2147 21:34:27.982389 # ok 332 write_default.LCALTA.13
2148 21:34:27.987489 # ok 333 write_valid.LCALTA.13
2149 21:34:27.987967 # ok 334 write_invalid.LCALTA.13
2150 21:34:27.993203 # ok 335 event_missing.LCALTA.13
2151 21:34:27.993681 # ok 336 event_spurious.LCALTA.13
2152 21:34:27.998617 # ok 337 get_value.LCALTA.12
2153 21:34:27.999092 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2154 21:34:28.004183 # ok 338 name.LCALTA.12
2155 21:34:28.004659 # ok 339 write_default.LCALTA.12
2156 21:34:28.009668 # ok 340 write_valid.LCALTA.12
2157 21:34:28.010136 # ok 341 write_invalid.LCALTA.12
2158 21:34:28.015234 # ok 342 event_missing.LCALTA.12
2159 21:34:28.020853 # ok 343 event_spurious.LCALTA.12
2160 21:34:28.021312 # ok 344 get_value.LCALTA.11
2161 21:34:28.026337 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2162 21:34:28.026849 # ok 345 name.LCALTA.11
2163 21:34:28.027294 # ok 346 write_default.LCALTA.11
2164 21:34:28.032086 # ok 347 write_valid.LCALTA.11
2165 21:34:28.037529 # ok 348 write_invalid.LCALTA.11
2166 21:34:28.038120 # ok 349 event_missing.LCALTA.11
2167 21:34:28.042962 # ok 350 event_spurious.LCALTA.11
2168 21:34:28.043446 # ok 351 get_value.LCALTA.10
2169 21:34:28.048479 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2170 21:34:28.048950 # ok 352 name.LCALTA.10
2171 21:34:28.053999 # ok 353 write_default.LCALTA.10
2172 21:34:28.054456 # ok 354 write_valid.LCALTA.10
2173 21:34:28.059622 # ok 355 write_invalid.LCALTA.10
2174 21:34:28.060235 # ok 356 event_missing.LCALTA.10
2175 21:34:28.065146 # ok 357 event_spurious.LCALTA.10
2176 21:34:28.065627 # ok 358 get_value.LCALTA.9
2177 21:34:28.070637 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2178 21:34:28.071127 # ok 359 name.LCALTA.9
2179 21:34:28.076211 # ok 360 write_default.LCALTA.9
2180 21:34:28.076757 # ok 361 write_valid.LCALTA.9
2181 21:34:28.081735 # ok 362 write_invalid.LCALTA.9
2182 21:34:28.082210 # ok 363 event_missing.LCALTA.9
2183 21:34:28.087285 # ok 364 event_spurious.LCALTA.9
2184 21:34:28.087758 # ok 365 get_value.LCALTA.8
2185 21:34:28.092859 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2186 21:34:28.093379 # ok 366 name.LCALTA.8
2187 21:34:28.098361 # ok 367 write_default.LCALTA.8
2188 21:34:28.098835 # ok 368 write_valid.LCALTA.8
2189 21:34:28.103910 # ok 369 write_invalid.LCALTA.8
2190 21:34:28.104413 # ok 370 event_missing.LCALTA.8
2191 21:34:28.109482 # ok 371 event_spurious.LCALTA.8
2192 21:34:28.109946 # ok 372 get_value.LCALTA.7
2193 21:34:28.115034 # # LCALTA.7 ACODEC Unmute Ramp Switch
2194 21:34:28.115501 # ok 373 name.LCALTA.7
2195 21:34:28.120616 # ok 374 write_default.LCALTA.7
2196 21:34:28.121183 # ok 375 write_valid.LCALTA.7
2197 21:34:28.126115 # ok 376 write_invalid.LCALTA.7
2198 21:34:28.126599 # ok 377 event_missing.LCALTA.7
2199 21:34:28.131679 # ok 378 event_spurious.LCALTA.7
2200 21:34:28.132208 # ok 379 get_value.LCALTA.6
2201 21:34:28.137228 # # LCALTA.6 ACODEC Mute Ramp Switch
2202 21:34:28.137708 # ok 380 name.LCALTA.6
2203 21:34:28.142863 # ok 381 write_default.LCALTA.6
2204 21:34:28.143445 # ok 382 write_valid.LCALTA.6
2205 21:34:28.148318 # ok 383 write_invalid.LCALTA.6
2206 21:34:28.148793 # ok 384 event_missing.LCALTA.6
2207 21:34:28.153899 # ok 385 event_spurious.LCALTA.6
2208 21:34:28.154435 # ok 386 get_value.LCALTA.5
2209 21:34:28.159452 # # LCALTA.5 ACODEC Volume Ramp Switch
2210 21:34:28.160086 # ok 387 name.LCALTA.5
2211 21:34:28.164974 # ok 388 write_default.LCALTA.5
2212 21:34:28.165449 # ok 389 write_valid.LCALTA.5
2213 21:34:28.170524 # ok 390 write_invalid.LCALTA.5
2214 21:34:28.171027 # ok 391 event_missing.LCALTA.5
2215 21:34:28.176071 # ok 392 event_spurious.LCALTA.5
2216 21:34:28.176555 # ok 393 get_value.LCALTA.4
2217 21:34:28.181813 # # LCALTA.4 ACODEC Ramp Rate
2218 21:34:28.182356 # ok 394 name.LCALTA.4
2219 21:34:28.182790 # ok 395 write_default.LCALTA.4
2220 21:34:28.187306 # ok 396 write_valid.LCALTA.4
2221 21:34:28.187886 # ok 397 write_invalid.LCALTA.4
2222 21:34:28.192719 # ok 398 event_missing.LCALTA.4
2223 21:34:28.198254 # ok 399 event_spurious.LCALTA.4
2224 21:34:28.198731 # ok 400 get_value.LCALTA.3
2225 21:34:28.203801 # # LCALTA.3 ACODEC Playback Volume
2226 21:34:28.204309 # ok 401 name.LCALTA.3
2227 21:34:28.204741 # ok 402 write_default.LCALTA.3
2228 21:34:28.209323 # ok 403 write_valid.LCALTA.3
2229 21:34:28.209835 # ok 404 write_invalid.LCALTA.3
2230 21:34:28.214887 # ok 405 event_missing.LCALTA.3
2231 21:34:28.215362 # ok 406 event_spurious.LCALTA.3
2232 21:34:28.220427 # ok 407 get_value.LCALTA.2
2233 21:34:28.225957 # # LCALTA.2 ACODEC Playback Switch
2234 21:34:28.226494 # ok 408 name.LCALTA.2
2235 21:34:28.226927 # ok 409 write_default.LCALTA.2
2236 21:34:28.231583 # ok 410 write_valid.LCALTA.2
2237 21:34:28.232108 # ok 411 write_invalid.LCALTA.2
2238 21:34:28.237053 # ok 412 event_missing.LCALTA.2
2239 21:34:28.237528 # ok 413 event_spurious.LCALTA.2
2240 21:34:28.242641 # ok 414 get_value.LCALTA.1
2241 21:34:28.248178 # # LCALTA.1 ACODEC Playback Channel Mode
2242 21:34:28.248656 # ok 415 name.LCALTA.1
2243 21:34:28.249083 # ok 416 write_default.LCALTA.1
2244 21:34:28.253677 # ok 417 write_valid.LCALTA.1
2245 21:34:28.254205 # ok 418 write_invalid.LCALTA.1
2246 21:34:28.259271 # ok 419 event_missing.LCALTA.1
2247 21:34:28.264819 # ok 420 event_spurious.LCALTA.1
2248 21:34:28.265305 # ok 421 get_value.LCALTA.0
2249 21:34:28.270391 # # LCALTA.0 TOACODEC Lane Select
2250 21:34:28.270869 # ok 422 name.LCALTA.0
2251 21:34:28.271297 # ok 423 write_default.LCALTA.0
2252 21:34:28.275974 # ok 424 write_valid.LCALTA.0
2253 21:34:28.276474 # ok 425 write_invalid.LCALTA.0
2254 21:34:28.281448 # ok 426 event_missing.LCALTA.0
2255 21:34:28.281942 # ok 427 event_spurious.LCALTA.0
2256 21:34:28.287022 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2257 21:34:28.292570 ok 1 selftests: alsa: mixer-test
2258 21:34:28.293056 # timeout set to 45
2259 21:34:28.298085 # selftests: alsa: pcm-test
2260 21:34:28.298559 # TAP version 13
2261 21:34:28.303617 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2262 21:34:28.304115 # # LCALTA.0 - fe.dai-link-0 (*)
2263 21:34:28.309167 # # LCALTA.0 - fe.dai-link-1 (*)
2264 21:34:28.309644 # # LCALTA.0 - fe.dai-link-2 (*)
2265 21:34:28.314688 # # LCALTA.0 - fe.dai-link-3 (*)
2266 21:34:28.315277 # # LCALTA.0 - fe.dai-link-4 (*)
2267 21:34:28.320253 # # LCALTA.0 - fe.dai-link-5 (*)
2268 21:34:28.320732 # 1..42
2269 21:34:28.325783 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2270 21:34:28.331468 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2271 21:34:28.332111 # # snd_pcm_hw_params: Invalid argument
2272 21:34:28.336980 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2273 21:34:28.342462 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2274 21:34:28.348016 # # snd_pcm_hw_params: Invalid argument
2275 21:34:28.353525 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2276 21:34:28.359083 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2277 21:34:28.359672 # # snd_pcm_hw_params: Invalid argument
2278 21:34:28.364667 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2279 21:34:28.370298 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2280 21:34:28.375760 # # snd_pcm_hw_params: Invalid argument
2281 21:34:28.381330 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2282 21:34:28.382213 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2283 21:34:28.386865 # # snd_pcm_hw_params: Invalid argument
2284 21:34:28.392359 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2285 21:34:28.397928 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2286 21:34:28.403479 # # snd_pcm_hw_params: Invalid argument
2287 21:34:28.409119 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2288 21:34:28.409708 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2289 21:34:28.414541 # # snd_pcm_hw_params: Invalid argument
2290 21:34:28.420126 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2291 21:34:28.425638 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2292 21:34:28.426117 # # snd_pcm_hw_params: Invalid argument
2293 21:34:28.431247 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2294 21:34:28.436743 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2295 21:34:28.442282 # # snd_pcm_hw_params: Invalid argument
2296 21:34:28.447912 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2297 21:34:28.453880 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2298 21:34:28.454422 # # snd_pcm_hw_params: Invalid argument
2299 21:34:28.458976 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2300 21:34:28.464510 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2301 21:34:28.470036 # # snd_pcm_hw_params: Invalid argument
2302 21:34:28.475586 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2303 21:34:28.481116 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2304 21:34:28.481593 # # snd_pcm_hw_params: Invalid argument
2305 21:34:28.486649 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2306 21:34:28.492212 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2307 21:34:28.497738 # # snd_pcm_hw_params: Invalid argument
2308 21:34:28.503285 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2309 21:34:28.508899 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2310 21:34:28.509417 # # snd_pcm_hw_params: Invalid argument
2311 21:34:28.514460 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2312 21:34:28.519937 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2313 21:34:28.525527 # # snd_pcm_hw_params: Invalid argument
2314 21:34:28.531053 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2315 21:34:28.531559 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2316 21:34:28.536591 # # snd_pcm_hw_params: Invalid argument
2317 21:34:28.542188 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2318 21:34:28.547684 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2319 21:34:28.553260 # # snd_pcm_hw_params: Invalid argument
2320 21:34:28.558822 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2321 21:34:28.559310 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2322 21:34:28.564306 # # snd_pcm_hw_params: Invalid argument
2323 21:34:28.569887 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2324 21:34:28.575515 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2325 21:34:28.576029 # # snd_pcm_hw_params: Invalid argument
2326 21:34:28.586556 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2327 21:34:28.587096 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2328 21:34:28.592081 # # snd_pcm_hw_params: Invalid argument
2329 21:34:28.597691 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2330 21:34:28.603139 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2331 21:34:28.603611 # # snd_pcm_hw_params: Invalid argument
2332 21:34:28.608713 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2333 21:34:28.614243 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2334 21:34:28.619791 # # snd_pcm_hw_params: Invalid argument
2335 21:34:28.625351 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2336 21:34:28.630862 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2337 21:34:28.631326 # # snd_pcm_hw_params: Invalid argument
2338 21:34:28.636421 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2339 21:34:28.641990 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2340 21:34:28.647523 # # snd_pcm_hw_params: Invalid argument
2341 21:34:28.653071 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2342 21:34:28.658696 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2343 21:34:28.659164 # # snd_pcm_hw_params: Invalid argument
2344 21:34:28.664193 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2345 21:34:28.669699 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2346 21:34:28.675266 # # snd_pcm_hw_params: Invalid argument
2347 21:34:28.680819 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2348 21:34:28.686348 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2349 21:34:28.686820 # # snd_pcm_hw_params: Invalid argument
2350 21:34:28.691880 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2351 21:34:28.697436 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2352 21:34:28.702961 # # snd_pcm_hw_params: Invalid argument
2353 21:34:28.708505 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2354 21:34:28.714079 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2355 21:34:28.714547 # # snd_pcm_hw_params: Invalid argument
2356 21:34:28.719577 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2357 21:34:28.725158 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2358 21:34:28.730768 # # snd_pcm_hw_params: Invalid argument
2359 21:34:28.736258 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2360 21:34:28.741846 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2361 21:34:28.742333 # # snd_pcm_hw_params: Invalid argument
2362 21:34:28.747363 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2363 21:34:28.752895 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2364 21:34:28.758466 # # snd_pcm_hw_params: Invalid argument
2365 21:34:28.764048 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2366 21:34:28.769533 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2367 21:34:28.770013 # # snd_pcm_hw_params: Invalid argument
2368 21:34:28.775122 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2369 21:34:28.780729 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2370 21:34:28.786220 # # snd_pcm_hw_params: Invalid argument
2371 21:34:28.791803 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2372 21:34:28.797433 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2373 21:34:28.798001 # # snd_pcm_hw_params: Invalid argument
2374 21:34:28.802914 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2375 21:34:28.808443 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2376 21:34:28.814239 # # snd_pcm_hw_params: Invalid argument
2377 21:34:28.819588 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2378 21:34:28.820161 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2379 21:34:28.825090 # # snd_pcm_hw_params: Invalid argument
2380 21:34:28.830692 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2381 21:34:28.836169 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2382 21:34:28.841933 # # snd_pcm_hw_params: Invalid argument
2383 21:34:28.847241 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2384 21:34:28.847766 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2385 21:34:28.852892 # # snd_pcm_hw_params: Invalid argument
2386 21:34:28.858420 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2387 21:34:28.863926 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2388 21:34:28.869516 # # snd_pcm_hw_params: Invalid argument
2389 21:34:28.875033 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2390 21:34:28.875610 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2391 21:34:28.880586 # # snd_pcm_hw_params: Invalid argument
2392 21:34:28.886084 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2393 21:34:28.891631 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2394 21:34:28.897146 # # snd_pcm_hw_params: Invalid argument
2395 21:34:28.902828 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2396 21:34:28.903446 ok 2 selftests: alsa: pcm-test
2397 21:34:28.903917 # timeout set to 45
2398 21:34:28.908389 # selftests: alsa: test-pcmtest-driver
2399 21:34:28.909021 # TAP version 13
2400 21:34:28.909490 # 1..5
2401 21:34:28.913915 # # Starting 5 tests from 1 test cases.
2402 21:34:28.919498 # # RUN pcmtest.playback ...
2403 21:34:28.931562 # # SKIP Can't read patterns. Probably, module isn't loaded
2404 21:34:28.932021 # # OK pcmtest.playback
2405 21:34:28.936220 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2406 21:34:28.936868 # # RUN pcmtest.capture ...
2407 21:34:28.941730 # # SKIP Can't read patterns. Probably, module isn't loaded
2408 21:34:28.947205 # # OK pcmtest.capture
2409 21:34:28.952843 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2410 21:34:28.958247 # # RUN pcmtest.ni_capture ...
2411 21:34:28.963825 # # SKIP Can't read patterns. Probably, module isn't loaded
2412 21:34:28.969350 # # OK pcmtest.ni_capture
2413 21:34:28.974959 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2414 21:34:28.981039 # # RUN pcmtest.ni_playback ...
2415 21:34:28.985934 # # SKIP Can't read patterns. Probably, module isn't loaded
2416 21:34:28.986521 # # OK pcmtest.ni_playback
2417 21:34:28.997082 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2418 21:34:28.997698 # # RUN pcmtest.reset_ioctl ...
2419 21:34:29.002654 # # SKIP Can't read patterns. Probably, module isn't loaded
2420 21:34:29.008202 # # OK pcmtest.reset_ioctl
2421 21:34:29.013724 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2422 21:34:29.019252 # # PASSED: 5 / 5 tests passed.
2423 21:34:29.025022 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2424 21:34:29.028230 ok 3 selftests: alsa: test-pcmtest-driver
2425 21:34:29.925159 alsa_mixer-test_get_value_LCALTA_60 pass
2426 21:34:29.930596 alsa_mixer-test_name_LCALTA_60 pass
2427 21:34:29.931113 alsa_mixer-test_write_default_LCALTA_60 pass
2428 21:34:29.936182 alsa_mixer-test_write_valid_LCALTA_60 pass
2429 21:34:29.941651 alsa_mixer-test_write_invalid_LCALTA_60 pass
2430 21:34:29.947193 alsa_mixer-test_event_missing_LCALTA_60 pass
2431 21:34:29.947688 alsa_mixer-test_event_spurious_LCALTA_60 pass
2432 21:34:29.952741 alsa_mixer-test_get_value_LCALTA_59 pass
2433 21:34:29.958287 alsa_mixer-test_name_LCALTA_59 pass
2434 21:34:29.958783 alsa_mixer-test_write_default_LCALTA_59 pass
2435 21:34:29.963903 alsa_mixer-test_write_valid_LCALTA_59 pass
2436 21:34:29.969387 alsa_mixer-test_write_invalid_LCALTA_59 pass
2437 21:34:29.969883 alsa_mixer-test_event_missing_LCALTA_59 pass
2438 21:34:29.974962 alsa_mixer-test_event_spurious_LCALTA_59 pass
2439 21:34:29.980487 alsa_mixer-test_get_value_LCALTA_58 pass
2440 21:34:29.980983 alsa_mixer-test_name_LCALTA_58 pass
2441 21:34:29.986049 alsa_mixer-test_write_default_LCALTA_58 pass
2442 21:34:29.991585 alsa_mixer-test_write_valid_LCALTA_58 pass
2443 21:34:29.992104 alsa_mixer-test_write_invalid_LCALTA_58 pass
2444 21:34:29.997149 alsa_mixer-test_event_missing_LCALTA_58 pass
2445 21:34:30.002638 alsa_mixer-test_event_spurious_LCALTA_58 pass
2446 21:34:30.008222 alsa_mixer-test_get_value_LCALTA_57 pass
2447 21:34:30.008713 alsa_mixer-test_name_LCALTA_57 pass
2448 21:34:30.013876 alsa_mixer-test_write_default_LCALTA_57 pass
2449 21:34:30.019391 alsa_mixer-test_write_valid_LCALTA_57 pass
2450 21:34:30.019884 alsa_mixer-test_write_invalid_LCALTA_57 pass
2451 21:34:30.025007 alsa_mixer-test_event_missing_LCALTA_57 pass
2452 21:34:30.030498 alsa_mixer-test_event_spurious_LCALTA_57 pass
2453 21:34:30.030988 alsa_mixer-test_get_value_LCALTA_56 pass
2454 21:34:30.036076 alsa_mixer-test_name_LCALTA_56 pass
2455 21:34:30.041578 alsa_mixer-test_write_default_LCALTA_56 pass
2456 21:34:30.042071 alsa_mixer-test_write_valid_LCALTA_56 pass
2457 21:34:30.047168 alsa_mixer-test_write_invalid_LCALTA_56 pass
2458 21:34:30.052703 alsa_mixer-test_event_missing_LCALTA_56 pass
2459 21:34:30.058188 alsa_mixer-test_event_spurious_LCALTA_56 pass
2460 21:34:30.058679 alsa_mixer-test_get_value_LCALTA_55 pass
2461 21:34:30.063745 alsa_mixer-test_name_LCALTA_55 pass
2462 21:34:30.069300 alsa_mixer-test_write_default_LCALTA_55 pass
2463 21:34:30.069792 alsa_mixer-test_write_valid_LCALTA_55 pass
2464 21:34:30.074914 alsa_mixer-test_write_invalid_LCALTA_55 pass
2465 21:34:30.080404 alsa_mixer-test_event_missing_LCALTA_55 pass
2466 21:34:30.080892 alsa_mixer-test_event_spurious_LCALTA_55 pass
2467 21:34:30.086029 alsa_mixer-test_get_value_LCALTA_54 pass
2468 21:34:30.091533 alsa_mixer-test_name_LCALTA_54 pass
2469 21:34:30.092053 alsa_mixer-test_write_default_LCALTA_54 pass
2470 21:34:30.097061 alsa_mixer-test_write_valid_LCALTA_54 pass
2471 21:34:30.102587 alsa_mixer-test_write_invalid_LCALTA_54 pass
2472 21:34:30.103074 alsa_mixer-test_event_missing_LCALTA_54 pass
2473 21:34:30.108205 alsa_mixer-test_event_spurious_LCALTA_54 pass
2474 21:34:30.113660 alsa_mixer-test_get_value_LCALTA_53 pass
2475 21:34:30.114149 alsa_mixer-test_name_LCALTA_53 pass
2476 21:34:30.119245 alsa_mixer-test_write_default_LCALTA_53 pass
2477 21:34:30.124778 alsa_mixer-test_write_valid_LCALTA_53 pass
2478 21:34:30.130341 alsa_mixer-test_write_invalid_LCALTA_53 pass
2479 21:34:30.130839 alsa_mixer-test_event_missing_LCALTA_53 pass
2480 21:34:30.135897 alsa_mixer-test_event_spurious_LCALTA_53 pass
2481 21:34:30.141491 alsa_mixer-test_get_value_LCALTA_52 pass
2482 21:34:30.141989 alsa_mixer-test_name_LCALTA_52 pass
2483 21:34:30.146981 alsa_mixer-test_write_default_LCALTA_52 pass
2484 21:34:30.152484 alsa_mixer-test_write_valid_LCALTA_52 pass
2485 21:34:30.152968 alsa_mixer-test_write_invalid_LCALTA_52 pass
2486 21:34:30.158051 alsa_mixer-test_event_missing_LCALTA_52 pass
2487 21:34:30.163657 alsa_mixer-test_event_spurious_LCALTA_52 pass
2488 21:34:30.164190 alsa_mixer-test_get_value_LCALTA_51 pass
2489 21:34:30.169143 alsa_mixer-test_name_LCALTA_51 pass
2490 21:34:30.174733 alsa_mixer-test_write_default_LCALTA_51 pass
2491 21:34:30.175245 alsa_mixer-test_write_valid_LCALTA_51 pass
2492 21:34:30.180308 alsa_mixer-test_write_invalid_LCALTA_51 pass
2493 21:34:30.185797 alsa_mixer-test_event_missing_LCALTA_51 pass
2494 21:34:30.191325 alsa_mixer-test_event_spurious_LCALTA_51 pass
2495 21:34:30.191809 alsa_mixer-test_get_value_LCALTA_50 pass
2496 21:34:30.196902 alsa_mixer-test_name_LCALTA_50 pass
2497 21:34:30.202470 alsa_mixer-test_write_default_LCALTA_50 pass
2498 21:34:30.202960 alsa_mixer-test_write_valid_LCALTA_50 pass
2499 21:34:30.208056 alsa_mixer-test_write_invalid_LCALTA_50 pass
2500 21:34:30.213535 alsa_mixer-test_event_missing_LCALTA_50 pass
2501 21:34:30.214019 alsa_mixer-test_event_spurious_LCALTA_50 pass
2502 21:34:30.219084 alsa_mixer-test_get_value_LCALTA_49 pass
2503 21:34:30.224648 alsa_mixer-test_name_LCALTA_49 pass
2504 21:34:30.225140 alsa_mixer-test_write_default_LCALTA_49 pass
2505 21:34:30.230177 alsa_mixer-test_write_valid_LCALTA_49 pass
2506 21:34:30.235705 alsa_mixer-test_write_invalid_LCALTA_49 pass
2507 21:34:30.241301 alsa_mixer-test_event_missing_LCALTA_49 pass
2508 21:34:30.241785 alsa_mixer-test_event_spurious_LCALTA_49 pass
2509 21:34:30.246806 alsa_mixer-test_get_value_LCALTA_48 pass
2510 21:34:30.247294 alsa_mixer-test_name_LCALTA_48 pass
2511 21:34:30.252368 alsa_mixer-test_write_default_LCALTA_48 pass
2512 21:34:30.257932 alsa_mixer-test_write_valid_LCALTA_48 pass
2513 21:34:30.263430 alsa_mixer-test_write_invalid_LCALTA_48 pass
2514 21:34:30.263927 alsa_mixer-test_event_missing_LCALTA_48 pass
2515 21:34:30.269027 alsa_mixer-test_event_spurious_LCALTA_48 pass
2516 21:34:30.274527 alsa_mixer-test_get_value_LCALTA_47 pass
2517 21:34:30.275021 alsa_mixer-test_name_LCALTA_47 pass
2518 21:34:30.280144 alsa_mixer-test_write_default_LCALTA_47 pass
2519 21:34:30.285670 alsa_mixer-test_write_valid_LCALTA_47 pass
2520 21:34:30.286153 alsa_mixer-test_write_invalid_LCALTA_47 pass
2521 21:34:30.291176 alsa_mixer-test_event_missing_LCALTA_47 pass
2522 21:34:30.296718 alsa_mixer-test_event_spurious_LCALTA_47 pass
2523 21:34:30.302273 alsa_mixer-test_get_value_LCALTA_46 pass
2524 21:34:30.302755 alsa_mixer-test_name_LCALTA_46 pass
2525 21:34:30.307832 alsa_mixer-test_write_default_LCALTA_46 pass
2526 21:34:30.313415 alsa_mixer-test_write_valid_LCALTA_46 pass
2527 21:34:30.313901 alsa_mixer-test_write_invalid_LCALTA_46 pass
2528 21:34:30.318932 alsa_mixer-test_event_missing_LCALTA_46 pass
2529 21:34:30.324481 alsa_mixer-test_event_spurious_LCALTA_46 pass
2530 21:34:30.324971 alsa_mixer-test_get_value_LCALTA_45 pass
2531 21:34:30.330044 alsa_mixer-test_name_LCALTA_45 pass
2532 21:34:30.335539 alsa_mixer-test_write_default_LCALTA_45 pass
2533 21:34:30.336050 alsa_mixer-test_write_valid_LCALTA_45 pass
2534 21:34:30.341074 alsa_mixer-test_write_invalid_LCALTA_45 pass
2535 21:34:30.346688 alsa_mixer-test_event_missing_LCALTA_45 pass
2536 21:34:30.347170 alsa_mixer-test_event_spurious_LCALTA_45 pass
2537 21:34:30.352255 alsa_mixer-test_get_value_LCALTA_44 pass
2538 21:34:30.357756 alsa_mixer-test_name_LCALTA_44 pass
2539 21:34:30.358240 alsa_mixer-test_write_default_LCALTA_44 pass
2540 21:34:30.363305 alsa_mixer-test_write_valid_LCALTA_44 pass
2541 21:34:30.368828 alsa_mixer-test_write_invalid_LCALTA_44 pass
2542 21:34:30.374350 alsa_mixer-test_event_missing_LCALTA_44 pass
2543 21:34:30.374836 alsa_mixer-test_event_spurious_LCALTA_44 pass
2544 21:34:30.379929 alsa_mixer-test_get_value_LCALTA_43 pass
2545 21:34:30.385523 alsa_mixer-test_name_LCALTA_43 pass
2546 21:34:30.386013 alsa_mixer-test_write_default_LCALTA_43 pass
2547 21:34:30.391054 alsa_mixer-test_write_valid_LCALTA_43 pass
2548 21:34:30.396571 alsa_mixer-test_write_invalid_LCALTA_43 pass
2549 21:34:30.397060 alsa_mixer-test_event_missing_LCALTA_43 pass
2550 21:34:30.402109 alsa_mixer-test_event_spurious_LCALTA_43 pass
2551 21:34:30.407702 alsa_mixer-test_get_value_LCALTA_42 pass
2552 21:34:30.408224 alsa_mixer-test_name_LCALTA_42 pass
2553 21:34:30.413229 alsa_mixer-test_write_default_LCALTA_42 pass
2554 21:34:30.418791 alsa_mixer-test_write_valid_LCALTA_42 pass
2555 21:34:30.419273 alsa_mixer-test_write_invalid_LCALTA_42 pass
2556 21:34:30.424325 alsa_mixer-test_event_missing_LCALTA_42 pass
2557 21:34:30.429856 alsa_mixer-test_event_spurious_LCALTA_42 pass
2558 21:34:30.435398 alsa_mixer-test_get_value_LCALTA_41 pass
2559 21:34:30.435884 alsa_mixer-test_name_LCALTA_41 pass
2560 21:34:30.440947 alsa_mixer-test_write_default_LCALTA_41 pass
2561 21:34:30.446500 alsa_mixer-test_write_valid_LCALTA_41 pass
2562 21:34:30.446989 alsa_mixer-test_write_invalid_LCALTA_41 pass
2563 21:34:30.452067 alsa_mixer-test_event_missing_LCALTA_41 pass
2564 21:34:30.457599 alsa_mixer-test_event_spurious_LCALTA_41 pass
2565 21:34:30.458087 alsa_mixer-test_get_value_LCALTA_40 pass
2566 21:34:30.463108 alsa_mixer-test_name_LCALTA_40 pass
2567 21:34:30.468657 alsa_mixer-test_write_default_LCALTA_40 pass
2568 21:34:30.469143 alsa_mixer-test_write_valid_LCALTA_40 pass
2569 21:34:30.474194 alsa_mixer-test_write_invalid_LCALTA_40 pass
2570 21:34:30.479758 alsa_mixer-test_event_missing_LCALTA_40 pass
2571 21:34:30.485320 alsa_mixer-test_event_spurious_LCALTA_40 pass
2572 21:34:30.485822 alsa_mixer-test_get_value_LCALTA_39 pass
2573 21:34:30.490819 alsa_mixer-test_name_LCALTA_39 pass
2574 21:34:30.496407 alsa_mixer-test_write_default_LCALTA_39 pass
2575 21:34:30.496899 alsa_mixer-test_write_valid_LCALTA_39 pass
2576 21:34:30.501966 alsa_mixer-test_write_invalid_LCALTA_39 pass
2577 21:34:30.507508 alsa_mixer-test_event_missing_LCALTA_39 pass
2578 21:34:30.508027 alsa_mixer-test_event_spurious_LCALTA_39 pass
2579 21:34:30.513072 alsa_mixer-test_get_value_LCALTA_38 pass
2580 21:34:30.518586 alsa_mixer-test_name_LCALTA_38 pass
2581 21:34:30.519073 alsa_mixer-test_write_default_LCALTA_38 pass
2582 21:34:30.524197 alsa_mixer-test_write_valid_LCALTA_38 pass
2583 21:34:30.529687 alsa_mixer-test_write_invalid_LCALTA_38 pass
2584 21:34:30.530173 alsa_mixer-test_event_missing_LCALTA_38 pass
2585 21:34:30.535200 alsa_mixer-test_event_spurious_LCALTA_38 pass
2586 21:34:30.540783 alsa_mixer-test_get_value_LCALTA_37 pass
2587 21:34:30.541269 alsa_mixer-test_name_LCALTA_37 pass
2588 21:34:30.546327 alsa_mixer-test_write_default_LCALTA_37 pass
2589 21:34:30.551891 alsa_mixer-test_write_valid_LCALTA_37 pass
2590 21:34:30.557466 alsa_mixer-test_write_invalid_LCALTA_37 pass
2591 21:34:30.557956 alsa_mixer-test_event_missing_LCALTA_37 pass
2592 21:34:30.562979 alsa_mixer-test_event_spurious_LCALTA_37 pass
2593 21:34:30.568518 alsa_mixer-test_get_value_LCALTA_36 pass
2594 21:34:30.569007 alsa_mixer-test_name_LCALTA_36 pass
2595 21:34:30.574054 alsa_mixer-test_write_default_LCALTA_36 pass
2596 21:34:30.579594 alsa_mixer-test_write_valid_LCALTA_36 pass
2597 21:34:30.580135 alsa_mixer-test_write_invalid_LCALTA_36 pass
2598 21:34:30.585190 alsa_mixer-test_event_missing_LCALTA_36 pass
2599 21:34:30.590728 alsa_mixer-test_event_spurious_LCALTA_36 pass
2600 21:34:30.591215 alsa_mixer-test_get_value_LCALTA_35 pass
2601 21:34:30.596252 alsa_mixer-test_name_LCALTA_35 pass
2602 21:34:30.601791 alsa_mixer-test_write_default_LCALTA_35 pass
2603 21:34:30.602281 alsa_mixer-test_write_valid_LCALTA_35 pass
2604 21:34:30.607365 alsa_mixer-test_write_invalid_LCALTA_35 pass
2605 21:34:30.612901 alsa_mixer-test_event_missing_LCALTA_35 pass
2606 21:34:30.618435 alsa_mixer-test_event_spurious_LCALTA_35 pass
2607 21:34:30.618922 alsa_mixer-test_get_value_LCALTA_34 pass
2608 21:34:30.623963 alsa_mixer-test_name_LCALTA_34 pass
2609 21:34:30.629518 alsa_mixer-test_write_default_LCALTA_34 pass
2610 21:34:30.630002 alsa_mixer-test_write_valid_LCALTA_34 pass
2611 21:34:30.635062 alsa_mixer-test_write_invalid_LCALTA_34 pass
2612 21:34:30.640599 alsa_mixer-test_event_missing_LCALTA_34 pass
2613 21:34:30.641081 alsa_mixer-test_event_spurious_LCALTA_34 pass
2614 21:34:30.646188 alsa_mixer-test_get_value_LCALTA_33 pass
2615 21:34:30.651707 alsa_mixer-test_name_LCALTA_33 pass
2616 21:34:30.652225 alsa_mixer-test_write_default_LCALTA_33 pass
2617 21:34:30.657202 alsa_mixer-test_write_valid_LCALTA_33 pass
2618 21:34:30.662795 alsa_mixer-test_write_invalid_LCALTA_33 pass
2619 21:34:30.668365 alsa_mixer-test_event_missing_LCALTA_33 pass
2620 21:34:30.668852 alsa_mixer-test_event_spurious_LCALTA_33 pass
2621 21:34:30.673879 alsa_mixer-test_get_value_LCALTA_32 pass
2622 21:34:30.674363 alsa_mixer-test_name_LCALTA_32 pass
2623 21:34:30.679445 alsa_mixer-test_write_default_LCALTA_32 pass
2624 21:34:30.685009 alsa_mixer-test_write_valid_LCALTA_32 pass
2625 21:34:30.690571 alsa_mixer-test_write_invalid_LCALTA_32 pass
2626 21:34:30.691059 alsa_mixer-test_event_missing_LCALTA_32 pass
2627 21:34:30.696102 alsa_mixer-test_event_spurious_LCALTA_32 pass
2628 21:34:30.701624 alsa_mixer-test_get_value_LCALTA_31 pass
2629 21:34:30.702107 alsa_mixer-test_name_LCALTA_31 pass
2630 21:34:30.707170 alsa_mixer-test_write_default_LCALTA_31 pass
2631 21:34:30.712710 alsa_mixer-test_write_valid_LCALTA_31 pass
2632 21:34:30.713197 alsa_mixer-test_write_invalid_LCALTA_31 pass
2633 21:34:30.718258 alsa_mixer-test_event_missing_LCALTA_31 pass
2634 21:34:30.723837 alsa_mixer-test_event_spurious_LCALTA_31 pass
2635 21:34:30.729387 alsa_mixer-test_get_value_LCALTA_30 pass
2636 21:34:30.729875 alsa_mixer-test_name_LCALTA_30 pass
2637 21:34:30.734979 alsa_mixer-test_write_default_LCALTA_30 pass
2638 21:34:30.740518 alsa_mixer-test_write_valid_LCALTA_30 pass
2639 21:34:30.741021 alsa_mixer-test_write_invalid_LCALTA_30 pass
2640 21:34:30.746037 alsa_mixer-test_event_missing_LCALTA_30 pass
2641 21:34:30.751590 alsa_mixer-test_event_spurious_LCALTA_30 pass
2642 21:34:30.752129 alsa_mixer-test_get_value_LCALTA_29 pass
2643 21:34:30.757135 alsa_mixer-test_name_LCALTA_29 pass
2644 21:34:30.762695 alsa_mixer-test_write_default_LCALTA_29 pass
2645 21:34:30.763200 alsa_mixer-test_write_valid_LCALTA_29 pass
2646 21:34:30.768252 alsa_mixer-test_write_invalid_LCALTA_29 pass
2647 21:34:30.773735 alsa_mixer-test_event_missing_LCALTA_29 pass
2648 21:34:30.774222 alsa_mixer-test_event_spurious_LCALTA_29 pass
2649 21:34:30.779251 alsa_mixer-test_get_value_LCALTA_28 pass
2650 21:34:30.784864 alsa_mixer-test_name_LCALTA_28 pass
2651 21:34:30.785352 alsa_mixer-test_write_default_LCALTA_28 pass
2652 21:34:30.790402 alsa_mixer-test_write_valid_LCALTA_28 pass
2653 21:34:30.795947 alsa_mixer-test_write_invalid_LCALTA_28 pass
2654 21:34:30.801509 alsa_mixer-test_event_missing_LCALTA_28 pass
2655 21:34:30.802015 alsa_mixer-test_event_spurious_LCALTA_28 pass
2656 21:34:30.807016 alsa_mixer-test_get_value_LCALTA_27 pass
2657 21:34:30.812643 alsa_mixer-test_name_LCALTA_27 pass
2658 21:34:30.813159 alsa_mixer-test_write_default_LCALTA_27 pass
2659 21:34:30.818162 alsa_mixer-test_write_valid_LCALTA_27 pass
2660 21:34:30.823686 alsa_mixer-test_write_invalid_LCALTA_27 pass
2661 21:34:30.824220 alsa_mixer-test_event_missing_LCALTA_27 pass
2662 21:34:30.829282 alsa_mixer-test_event_spurious_LCALTA_27 pass
2663 21:34:30.834786 alsa_mixer-test_get_value_LCALTA_26 pass
2664 21:34:30.835269 alsa_mixer-test_name_LCALTA_26 pass
2665 21:34:30.840337 alsa_mixer-test_write_default_LCALTA_26 skip
2666 21:34:30.845879 alsa_mixer-test_write_valid_LCALTA_26 skip
2667 21:34:30.846377 alsa_mixer-test_write_invalid_LCALTA_26 skip
2668 21:34:30.851433 alsa_mixer-test_event_missing_LCALTA_26 pass
2669 21:34:30.856998 alsa_mixer-test_event_spurious_LCALTA_26 pass
2670 21:34:30.862532 alsa_mixer-test_get_value_LCALTA_25 pass
2671 21:34:30.863021 alsa_mixer-test_name_LCALTA_25 pass
2672 21:34:30.868055 alsa_mixer-test_write_default_LCALTA_25 pass
2673 21:34:30.873601 alsa_mixer-test_write_valid_LCALTA_25 skip
2674 21:34:30.874085 alsa_mixer-test_write_invalid_LCALTA_25 skip
2675 21:34:30.879181 alsa_mixer-test_event_missing_LCALTA_25 pass
2676 21:34:30.884691 alsa_mixer-test_event_spurious_LCALTA_25 pass
2677 21:34:30.885185 alsa_mixer-test_get_value_LCALTA_24 pass
2678 21:34:30.890279 alsa_mixer-test_name_LCALTA_24 pass
2679 21:34:30.895807 alsa_mixer-test_write_default_LCALTA_24 skip
2680 21:34:30.896342 alsa_mixer-test_write_valid_LCALTA_24 skip
2681 21:34:30.901335 alsa_mixer-test_write_invalid_LCALTA_24 skip
2682 21:34:30.906888 alsa_mixer-test_event_missing_LCALTA_24 pass
2683 21:34:30.912392 alsa_mixer-test_event_spurious_LCALTA_24 pass
2684 21:34:30.912879 alsa_mixer-test_get_value_LCALTA_23 pass
2685 21:34:30.917978 alsa_mixer-test_name_LCALTA_23 pass
2686 21:34:30.923508 alsa_mixer-test_write_default_LCALTA_23 skip
2687 21:34:30.924063 alsa_mixer-test_write_valid_LCALTA_23 skip
2688 21:34:30.929218 alsa_mixer-test_write_invalid_LCALTA_23 skip
2689 21:34:30.934823 alsa_mixer-test_event_missing_LCALTA_23 pass
2690 21:34:30.935329 alsa_mixer-test_event_spurious_LCALTA_23 pass
2691 21:34:30.940201 alsa_mixer-test_get_value_LCALTA_22 pass
2692 21:34:30.945755 alsa_mixer-test_name_LCALTA_22 pass
2693 21:34:30.946250 alsa_mixer-test_write_default_LCALTA_22 pass
2694 21:34:30.951283 alsa_mixer-test_write_valid_LCALTA_22 pass
2695 21:34:30.956802 alsa_mixer-test_write_invalid_LCALTA_22 pass
2696 21:34:30.957286 alsa_mixer-test_event_missing_LCALTA_22 pass
2697 21:34:30.962334 alsa_mixer-test_event_spurious_LCALTA_22 pass
2698 21:34:30.967905 alsa_mixer-test_get_value_LCALTA_21 pass
2699 21:34:30.968436 alsa_mixer-test_name_LCALTA_21 pass
2700 21:34:30.973426 alsa_mixer-test_write_default_LCALTA_21 pass
2701 21:34:30.978946 alsa_mixer-test_write_valid_LCALTA_21 pass
2702 21:34:30.984485 alsa_mixer-test_write_invalid_LCALTA_21 pass
2703 21:34:30.984977 alsa_mixer-test_event_missing_LCALTA_21 pass
2704 21:34:30.990041 alsa_mixer-test_event_spurious_LCALTA_21 pass
2705 21:34:30.995638 alsa_mixer-test_get_value_LCALTA_20 pass
2706 21:34:30.996163 alsa_mixer-test_name_LCALTA_20 pass
2707 21:34:31.001189 alsa_mixer-test_write_default_LCALTA_20 pass
2708 21:34:31.006754 alsa_mixer-test_write_valid_LCALTA_20 pass
2709 21:34:31.007243 alsa_mixer-test_write_invalid_LCALTA_20 pass
2710 21:34:31.012333 alsa_mixer-test_event_missing_LCALTA_20 pass
2711 21:34:31.017879 alsa_mixer-test_event_spurious_LCALTA_20 pass
2712 21:34:31.018369 alsa_mixer-test_get_value_LCALTA_19 pass
2713 21:34:31.023296 alsa_mixer-test_name_LCALTA_19 pass
2714 21:34:31.028899 alsa_mixer-test_write_default_LCALTA_19 pass
2715 21:34:31.029387 alsa_mixer-test_write_valid_LCALTA_19 pass
2716 21:34:31.034494 alsa_mixer-test_write_invalid_LCALTA_19 pass
2717 21:34:31.039937 alsa_mixer-test_event_missing_LCALTA_19 pass
2718 21:34:31.045529 alsa_mixer-test_event_spurious_LCALTA_19 pass
2719 21:34:31.046012 alsa_mixer-test_get_value_LCALTA_18 pass
2720 21:34:31.051138 alsa_mixer-test_name_LCALTA_18 pass
2721 21:34:31.056629 alsa_mixer-test_write_default_LCALTA_18 pass
2722 21:34:31.057113 alsa_mixer-test_write_valid_LCALTA_18 pass
2723 21:34:31.062281 alsa_mixer-test_write_invalid_LCALTA_18 pass
2724 21:34:31.067683 alsa_mixer-test_event_missing_LCALTA_18 pass
2725 21:34:31.068204 alsa_mixer-test_event_spurious_LCALTA_18 pass
2726 21:34:31.073235 alsa_mixer-test_get_value_LCALTA_17 pass
2727 21:34:31.078795 alsa_mixer-test_name_LCALTA_17 pass
2728 21:34:31.079282 alsa_mixer-test_write_default_LCALTA_17 pass
2729 21:34:31.084311 alsa_mixer-test_write_valid_LCALTA_17 pass
2730 21:34:31.089883 alsa_mixer-test_write_invalid_LCALTA_17 pass
2731 21:34:31.095436 alsa_mixer-test_event_missing_LCALTA_17 pass
2732 21:34:31.095946 alsa_mixer-test_event_spurious_LCALTA_17 pass
2733 21:34:31.101041 alsa_mixer-test_get_value_LCALTA_16 pass
2734 21:34:31.101525 alsa_mixer-test_name_LCALTA_16 pass
2735 21:34:31.106572 alsa_mixer-test_write_default_LCALTA_16 pass
2736 21:34:31.112260 alsa_mixer-test_write_valid_LCALTA_16 pass
2737 21:34:31.117639 alsa_mixer-test_write_invalid_LCALTA_16 pass
2738 21:34:31.118127 alsa_mixer-test_event_missing_LCALTA_16 pass
2739 21:34:31.123156 alsa_mixer-test_event_spurious_LCALTA_16 pass
2740 21:34:31.128736 alsa_mixer-test_get_value_LCALTA_15 pass
2741 21:34:31.129228 alsa_mixer-test_name_LCALTA_15 pass
2742 21:34:31.134276 alsa_mixer-test_write_default_LCALTA_15 pass
2743 21:34:31.139799 alsa_mixer-test_write_valid_LCALTA_15 pass
2744 21:34:31.140314 alsa_mixer-test_write_invalid_LCALTA_15 pass
2745 21:34:31.145379 alsa_mixer-test_event_missing_LCALTA_15 pass
2746 21:34:31.150895 alsa_mixer-test_event_spurious_LCALTA_15 pass
2747 21:34:31.156477 alsa_mixer-test_get_value_LCALTA_14 pass
2748 21:34:31.156966 alsa_mixer-test_name_LCALTA_14 pass
2749 21:34:31.162001 alsa_mixer-test_write_default_LCALTA_14 pass
2750 21:34:31.167570 alsa_mixer-test_write_valid_LCALTA_14 pass
2751 21:34:31.168102 alsa_mixer-test_write_invalid_LCALTA_14 pass
2752 21:34:31.173191 alsa_mixer-test_event_missing_LCALTA_14 pass
2753 21:34:31.178641 alsa_mixer-test_event_spurious_LCALTA_14 pass
2754 21:34:31.179129 alsa_mixer-test_get_value_LCALTA_13 pass
2755 21:34:31.184245 alsa_mixer-test_name_LCALTA_13 pass
2756 21:34:31.189717 alsa_mixer-test_write_default_LCALTA_13 pass
2757 21:34:31.190206 alsa_mixer-test_write_valid_LCALTA_13 pass
2758 21:34:31.195268 alsa_mixer-test_write_invalid_LCALTA_13 pass
2759 21:34:31.200853 alsa_mixer-test_event_missing_LCALTA_13 pass
2760 21:34:31.201350 alsa_mixer-test_event_spurious_LCALTA_13 pass
2761 21:34:31.206380 alsa_mixer-test_get_value_LCALTA_12 pass
2762 21:34:31.211923 alsa_mixer-test_name_LCALTA_12 pass
2763 21:34:31.212441 alsa_mixer-test_write_default_LCALTA_12 pass
2764 21:34:31.217473 alsa_mixer-test_write_valid_LCALTA_12 pass
2765 21:34:31.223038 alsa_mixer-test_write_invalid_LCALTA_12 pass
2766 21:34:31.228536 alsa_mixer-test_event_missing_LCALTA_12 pass
2767 21:34:31.229029 alsa_mixer-test_event_spurious_LCALTA_12 pass
2768 21:34:31.234173 alsa_mixer-test_get_value_LCALTA_11 pass
2769 21:34:31.239668 alsa_mixer-test_name_LCALTA_11 pass
2770 21:34:31.240205 alsa_mixer-test_write_default_LCALTA_11 pass
2771 21:34:31.245230 alsa_mixer-test_write_valid_LCALTA_11 pass
2772 21:34:31.250750 alsa_mixer-test_write_invalid_LCALTA_11 pass
2773 21:34:31.251234 alsa_mixer-test_event_missing_LCALTA_11 pass
2774 21:34:31.256303 alsa_mixer-test_event_spurious_LCALTA_11 pass
2775 21:34:31.261876 alsa_mixer-test_get_value_LCALTA_10 pass
2776 21:34:31.262360 alsa_mixer-test_name_LCALTA_10 pass
2777 21:34:31.267382 alsa_mixer-test_write_default_LCALTA_10 pass
2778 21:34:31.272947 alsa_mixer-test_write_valid_LCALTA_10 pass
2779 21:34:31.273433 alsa_mixer-test_write_invalid_LCALTA_10 pass
2780 21:34:31.278424 alsa_mixer-test_event_missing_LCALTA_10 pass
2781 21:34:31.284065 alsa_mixer-test_event_spurious_LCALTA_10 pass
2782 21:34:31.289559 alsa_mixer-test_get_value_LCALTA_9 pass
2783 21:34:31.290048 alsa_mixer-test_name_LCALTA_9 pass
2784 21:34:31.295168 alsa_mixer-test_write_default_LCALTA_9 pass
2785 21:34:31.300719 alsa_mixer-test_write_valid_LCALTA_9 pass
2786 21:34:31.301216 alsa_mixer-test_write_invalid_LCALTA_9 pass
2787 21:34:31.306201 alsa_mixer-test_event_missing_LCALTA_9 pass
2788 21:34:31.311690 alsa_mixer-test_event_spurious_LCALTA_9 pass
2789 21:34:31.311994 alsa_mixer-test_get_value_LCALTA_8 pass
2790 21:34:31.317199 alsa_mixer-test_name_LCALTA_8 pass
2791 21:34:31.322742 alsa_mixer-test_write_default_LCALTA_8 pass
2792 21:34:31.323037 alsa_mixer-test_write_valid_LCALTA_8 pass
2793 21:34:31.328305 alsa_mixer-test_write_invalid_LCALTA_8 pass
2794 21:34:31.333888 alsa_mixer-test_event_missing_LCALTA_8 pass
2795 21:34:31.334189 alsa_mixer-test_event_spurious_LCALTA_8 pass
2796 21:34:31.339417 alsa_mixer-test_get_value_LCALTA_7 pass
2797 21:34:31.344893 alsa_mixer-test_name_LCALTA_7 pass
2798 21:34:31.345148 alsa_mixer-test_write_default_LCALTA_7 pass
2799 21:34:31.350374 alsa_mixer-test_write_valid_LCALTA_7 pass
2800 21:34:31.356090 alsa_mixer-test_write_invalid_LCALTA_7 pass
2801 21:34:31.356544 alsa_mixer-test_event_missing_LCALTA_7 pass
2802 21:34:31.361629 alsa_mixer-test_event_spurious_LCALTA_7 pass
2803 21:34:31.367184 alsa_mixer-test_get_value_LCALTA_6 pass
2804 21:34:31.367670 alsa_mixer-test_name_LCALTA_6 pass
2805 21:34:31.372762 alsa_mixer-test_write_default_LCALTA_6 pass
2806 21:34:31.378300 alsa_mixer-test_write_valid_LCALTA_6 pass
2807 21:34:31.378784 alsa_mixer-test_write_invalid_LCALTA_6 pass
2808 21:34:31.383829 alsa_mixer-test_event_missing_LCALTA_6 pass
2809 21:34:31.389418 alsa_mixer-test_event_spurious_LCALTA_6 pass
2810 21:34:31.389902 alsa_mixer-test_get_value_LCALTA_5 pass
2811 21:34:31.394920 alsa_mixer-test_name_LCALTA_5 pass
2812 21:34:31.400454 alsa_mixer-test_write_default_LCALTA_5 pass
2813 21:34:31.400940 alsa_mixer-test_write_valid_LCALTA_5 pass
2814 21:34:31.406095 alsa_mixer-test_write_invalid_LCALTA_5 pass
2815 21:34:31.411573 alsa_mixer-test_event_missing_LCALTA_5 pass
2816 21:34:31.412089 alsa_mixer-test_event_spurious_LCALTA_5 pass
2817 21:34:31.417154 alsa_mixer-test_get_value_LCALTA_4 pass
2818 21:34:31.422660 alsa_mixer-test_name_LCALTA_4 pass
2819 21:34:31.423141 alsa_mixer-test_write_default_LCALTA_4 pass
2820 21:34:31.428232 alsa_mixer-test_write_valid_LCALTA_4 pass
2821 21:34:31.433741 alsa_mixer-test_write_invalid_LCALTA_4 pass
2822 21:34:31.434226 alsa_mixer-test_event_missing_LCALTA_4 pass
2823 21:34:31.439265 alsa_mixer-test_event_spurious_LCALTA_4 pass
2824 21:34:31.444900 alsa_mixer-test_get_value_LCALTA_3 pass
2825 21:34:31.445409 alsa_mixer-test_name_LCALTA_3 pass
2826 21:34:31.450465 alsa_mixer-test_write_default_LCALTA_3 pass
2827 21:34:31.456006 alsa_mixer-test_write_valid_LCALTA_3 pass
2828 21:34:31.456512 alsa_mixer-test_write_invalid_LCALTA_3 pass
2829 21:34:31.461582 alsa_mixer-test_event_missing_LCALTA_3 pass
2830 21:34:31.467098 alsa_mixer-test_event_spurious_LCALTA_3 pass
2831 21:34:31.467584 alsa_mixer-test_get_value_LCALTA_2 pass
2832 21:34:31.472651 alsa_mixer-test_name_LCALTA_2 pass
2833 21:34:31.478218 alsa_mixer-test_write_default_LCALTA_2 pass
2834 21:34:31.478704 alsa_mixer-test_write_valid_LCALTA_2 pass
2835 21:34:31.483723 alsa_mixer-test_write_invalid_LCALTA_2 pass
2836 21:34:31.489251 alsa_mixer-test_event_missing_LCALTA_2 pass
2837 21:34:31.494822 alsa_mixer-test_event_spurious_LCALTA_2 pass
2838 21:34:31.495310 alsa_mixer-test_get_value_LCALTA_1 pass
2839 21:34:31.500329 alsa_mixer-test_name_LCALTA_1 pass
2840 21:34:31.500816 alsa_mixer-test_write_default_LCALTA_1 pass
2841 21:34:31.505948 alsa_mixer-test_write_valid_LCALTA_1 pass
2842 21:34:31.511532 alsa_mixer-test_write_invalid_LCALTA_1 pass
2843 21:34:31.517069 alsa_mixer-test_event_missing_LCALTA_1 pass
2844 21:34:31.517553 alsa_mixer-test_event_spurious_LCALTA_1 pass
2845 21:34:31.522581 alsa_mixer-test_get_value_LCALTA_0 pass
2846 21:34:31.523064 alsa_mixer-test_name_LCALTA_0 pass
2847 21:34:31.528097 alsa_mixer-test_write_default_LCALTA_0 pass
2848 21:34:31.533627 alsa_mixer-test_write_valid_LCALTA_0 pass
2849 21:34:31.539211 alsa_mixer-test_write_invalid_LCALTA_0 pass
2850 21:34:31.539695 alsa_mixer-test_event_missing_LCALTA_0 pass
2851 21:34:31.544763 alsa_mixer-test_event_spurious_LCALTA_0 pass
2852 21:34:31.545250 alsa_mixer-test pass
2853 21:34:31.550287 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2854 21:34:31.555876 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2855 21:34:31.561357 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2856 21:34:31.566987 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2857 21:34:31.567471 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2858 21:34:31.572470 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2859 21:34:31.578023 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2860 21:34:31.583565 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2861 21:34:31.589110 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2862 21:34:31.594645 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2863 21:34:31.595129 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2864 21:34:31.600285 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2865 21:34:31.605801 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2866 21:34:31.611272 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2867 21:34:31.616833 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2868 21:34:31.622355 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2869 21:34:31.622839 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2870 21:34:31.627914 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2871 21:34:31.633478 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2872 21:34:31.638984 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2873 21:34:31.644630 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2874 21:34:31.650106 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2875 21:34:31.650589 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2876 21:34:31.655677 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2877 21:34:31.661211 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2878 21:34:31.666775 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2879 21:34:31.672284 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2880 21:34:31.677885 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2881 21:34:31.678370 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2882 21:34:31.683423 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2883 21:34:31.688933 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2884 21:34:31.694542 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2885 21:34:31.700089 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2886 21:34:31.705599 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2887 21:34:31.711151 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2888 21:34:31.711644 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2889 21:34:31.716687 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2890 21:34:31.722241 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2891 21:34:31.727771 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2892 21:34:31.733315 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2893 21:34:31.738867 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2894 21:34:31.739351 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2895 21:34:31.744422 alsa_pcm-test pass
2896 21:34:31.749928 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2897 21:34:31.761031 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2898 21:34:31.766617 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2899 21:34:31.777637 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2900 21:34:31.783241 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2901 21:34:31.788775 alsa_test-pcmtest-driver pass
2902 21:34:31.794291 + ../../utils/send-to-lava.sh ./output/result.txt
2903 21:34:31.799820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2904 21:34:31.800807 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2906 21:34:31.805390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2907 21:34:31.806136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2909 21:34:31.812848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2910 21:34:31.813599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2912 21:34:31.855780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2913 21:34:31.856636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2915 21:34:31.906930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2916 21:34:31.907686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2918 21:34:31.962913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2919 21:34:31.963669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2921 21:34:32.018932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2922 21:34:32.019693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2924 21:34:32.064243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2925 21:34:32.064919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2927 21:34:32.114110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2928 21:34:32.114711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2930 21:34:32.163435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2931 21:34:32.164143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2933 21:34:32.214032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2934 21:34:32.214812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2936 21:34:32.260267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2937 21:34:32.261034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2939 21:34:32.308669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2940 21:34:32.309457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2942 21:34:32.363406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2943 21:34:32.364187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2945 21:34:32.420254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2946 21:34:32.421031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2948 21:34:32.467320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2949 21:34:32.468087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2951 21:34:32.519931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2952 21:34:32.520731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2954 21:34:32.563497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2955 21:34:32.564283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2957 21:34:32.605304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2958 21:34:32.606072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2960 21:34:32.670861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2961 21:34:32.671628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2963 21:34:32.716358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2964 21:34:32.717112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2966 21:34:32.764730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2967 21:34:32.765482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2969 21:34:32.818336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2970 21:34:32.819148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2972 21:34:32.870169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2973 21:34:32.870934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2975 21:34:32.921342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2976 21:34:32.922098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2978 21:34:32.966757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2979 21:34:32.967568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2981 21:34:33.024030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2982 21:34:33.024806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
2984 21:34:33.075695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
2985 21:34:33.076520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
2987 21:34:33.123920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
2988 21:34:33.124724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
2990 21:34:33.181683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
2991 21:34:33.182460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
2993 21:34:33.244680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
2994 21:34:33.245450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
2996 21:34:33.298763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
2997 21:34:33.299561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
2999 21:34:33.343478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3000 21:34:33.344311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3002 21:34:33.394181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3003 21:34:33.394964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3005 21:34:33.439284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3006 21:34:33.440078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3008 21:34:33.491158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3009 21:34:33.491958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3011 21:34:33.536497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3012 21:34:33.537306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3014 21:34:33.599127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3015 21:34:33.599894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3017 21:34:33.653885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3018 21:34:33.654714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3020 21:34:33.706891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3021 21:34:33.707677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3023 21:34:33.753588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3024 21:34:33.754375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3026 21:34:33.805594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3027 21:34:33.806403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3029 21:34:33.851582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3030 21:34:33.852440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3032 21:34:33.897173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3033 21:34:33.897947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3035 21:34:33.950728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3036 21:34:33.951499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3038 21:34:34.003951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3039 21:34:34.004757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3041 21:34:34.052283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3042 21:34:34.053060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3044 21:34:34.107432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3045 21:34:34.108204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3047 21:34:34.158234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3048 21:34:34.159009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3050 21:34:34.202925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3051 21:34:34.203699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3053 21:34:34.255750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3054 21:34:34.256560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3056 21:34:34.304467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3057 21:34:34.305251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3059 21:34:34.355157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3060 21:34:34.355939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3062 21:34:34.403059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3063 21:34:34.403839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3065 21:34:34.453954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3066 21:34:34.454719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3068 21:34:34.507271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3069 21:34:34.508059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3071 21:34:34.557514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3072 21:34:34.558293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3074 21:34:34.610679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3075 21:34:34.611474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3077 21:34:34.665898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3078 21:34:34.666669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3080 21:34:34.728406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3081 21:34:34.729301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3083 21:34:34.814939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3084 21:34:34.815587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3086 21:34:34.862604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3087 21:34:34.863244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3089 21:34:34.904540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3090 21:34:34.905340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3092 21:34:34.955181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3093 21:34:34.955961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3095 21:34:35.009367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3096 21:34:35.010164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3098 21:34:35.060112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3099 21:34:35.060997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3101 21:34:35.118645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3102 21:34:35.119522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3104 21:34:35.171366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3105 21:34:35.172179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3107 21:34:35.223246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3108 21:34:35.224074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3110 21:34:35.276173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3111 21:34:35.277074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3113 21:34:35.328807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3114 21:34:35.329599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3116 21:34:35.381162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3117 21:34:35.382024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3119 21:34:35.431432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3120 21:34:35.432332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3122 21:34:35.482315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3123 21:34:35.483187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3125 21:34:35.525351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3126 21:34:35.526232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3128 21:34:35.581902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3129 21:34:35.582802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3131 21:34:35.627286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3132 21:34:35.628227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3134 21:34:35.679148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3135 21:34:35.680052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3137 21:34:35.729511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3138 21:34:35.730308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3140 21:34:35.781071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3141 21:34:35.781959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3143 21:34:35.832285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3144 21:34:35.833432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3146 21:34:35.877992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3147 21:34:35.878850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3149 21:34:35.933438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3150 21:34:35.934352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3152 21:34:35.988635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3153 21:34:35.989502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3155 21:34:36.039054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3156 21:34:36.039876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3158 21:34:36.082478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3159 21:34:36.083261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3161 21:34:36.133752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3162 21:34:36.134566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3164 21:34:36.187955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3165 21:34:36.188793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3167 21:34:36.237652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3168 21:34:36.238452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3170 21:34:36.289750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3171 21:34:36.290537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3173 21:34:36.332608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3174 21:34:36.333406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3176 21:34:36.384174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3177 21:34:36.384965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3179 21:34:36.431042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3180 21:34:36.431831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3182 21:34:36.477102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3183 21:34:36.477888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3185 21:34:36.524979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3186 21:34:36.525774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3188 21:34:36.576799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3189 21:34:36.577601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3191 21:34:36.633090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3192 21:34:36.633891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3194 21:34:36.675732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3195 21:34:36.676560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3197 21:34:36.732748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3198 21:34:36.733411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3200 21:34:36.786493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3201 21:34:36.787184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3203 21:34:36.830869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3204 21:34:36.831531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3206 21:34:36.888299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3207 21:34:36.888971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3209 21:34:36.938620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3210 21:34:36.939371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3212 21:34:36.980982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3213 21:34:36.981796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3215 21:34:37.034871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3216 21:34:37.035694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3218 21:34:37.081237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3219 21:34:37.082031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3221 21:34:37.128539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3222 21:34:37.129321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3224 21:34:37.173698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3225 21:34:37.174501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3227 21:34:37.218373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3228 21:34:37.219218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3230 21:34:37.267145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3231 21:34:37.267972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3233 21:34:37.313642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3234 21:34:37.314490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3236 21:34:37.357018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3237 21:34:37.357854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3239 21:34:37.421565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3240 21:34:37.422390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3242 21:34:37.472886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3243 21:34:37.473777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3245 21:34:37.523161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3246 21:34:37.524053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3248 21:34:37.569730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3249 21:34:37.570542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3251 21:34:37.627127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3252 21:34:37.627938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3254 21:34:37.688814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3255 21:34:37.689613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3257 21:34:37.738311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3258 21:34:37.739130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3260 21:34:37.791836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3261 21:34:37.792703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3263 21:34:37.836353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3264 21:34:37.837192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3266 21:34:37.880895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3267 21:34:37.881710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3269 21:34:37.934485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3270 21:34:37.935320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3272 21:34:37.977787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3273 21:34:37.978589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3275 21:34:38.021831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3276 21:34:38.022660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3278 21:34:38.068248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3279 21:34:38.069090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3281 21:34:38.118783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3282 21:34:38.119595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3284 21:34:38.170345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3285 21:34:38.171194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3287 21:34:38.217203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3288 21:34:38.218039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3290 21:34:38.263528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3291 21:34:38.264366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3293 21:34:38.313126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3294 21:34:38.313929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3296 21:34:38.366936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3297 21:34:38.367736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3299 21:34:38.416844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3300 21:34:38.417673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3302 21:34:38.470024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3303 21:34:38.470829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3305 21:34:38.519015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3306 21:34:38.519807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3308 21:34:38.563527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3309 21:34:38.564350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3311 21:34:38.608876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3312 21:34:38.609667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3314 21:34:38.656197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3315 21:34:38.656978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3317 21:34:38.701938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3318 21:34:38.702715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3320 21:34:38.760887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3321 21:34:38.761678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3323 21:34:38.805026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3324 21:34:38.805814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3326 21:34:38.853868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3327 21:34:38.854659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3329 21:34:38.897779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3330 21:34:38.898598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3332 21:34:38.954876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3333 21:34:38.955671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3335 21:34:39.005960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3336 21:34:39.006772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3338 21:34:39.049110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3339 21:34:39.049924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3341 21:34:39.101003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3342 21:34:39.101843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3344 21:34:39.163344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3345 21:34:39.164149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3347 21:34:39.213073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3348 21:34:39.213922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3350 21:34:39.262286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3351 21:34:39.263165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3353 21:34:39.319551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3354 21:34:39.320419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3356 21:34:39.364950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3357 21:34:39.365752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3359 21:34:39.414014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3360 21:34:39.414834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3362 21:34:39.459362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3363 21:34:39.460201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3365 21:34:39.503543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3366 21:34:39.504375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3368 21:34:39.559170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3369 21:34:39.560015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3371 21:34:39.606841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3372 21:34:39.607661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3374 21:34:39.660302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3375 21:34:39.661106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3377 21:34:39.710486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3378 21:34:39.711293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3380 21:34:39.761912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3381 21:34:39.762744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3383 21:34:39.816293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3384 21:34:39.817101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3386 21:34:39.861512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3387 21:34:39.862344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3389 21:34:39.918549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3390 21:34:39.919365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3392 21:34:39.970445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3393 21:34:39.971275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3395 21:34:40.023936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3396 21:34:40.024775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3398 21:34:40.078797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3399 21:34:40.079765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3401 21:34:40.132465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3402 21:34:40.133340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3404 21:34:40.184425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3405 21:34:40.185201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3407 21:34:40.230616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3408 21:34:40.231394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3410 21:34:40.281681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3411 21:34:40.282491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3413 21:34:40.335058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3414 21:34:40.335876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3416 21:34:40.381543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3417 21:34:40.382365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3419 21:34:40.440947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3420 21:34:40.441758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3422 21:34:40.491759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3423 21:34:40.492562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3425 21:34:40.534929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3426 21:34:40.535764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3428 21:34:40.589379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3429 21:34:40.590152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3431 21:34:40.635553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3432 21:34:40.636370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3434 21:34:40.693103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3435 21:34:40.693876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3437 21:34:40.740199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3438 21:34:40.740971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3440 21:34:40.790477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3441 21:34:40.791329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3443 21:34:40.843803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3444 21:34:40.844667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3446 21:34:40.892351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3447 21:34:40.893164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3449 21:34:40.936312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3450 21:34:40.937129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3452 21:34:40.991689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3453 21:34:40.992544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3455 21:34:41.034748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3456 21:34:41.035561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3458 21:34:41.086354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3459 21:34:41.087165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3461 21:34:41.135904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3462 21:34:41.136766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3464 21:34:41.179686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3465 21:34:41.180542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3467 21:34:41.237214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3468 21:34:41.238036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3470 21:34:41.283196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3471 21:34:41.284030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3473 21:34:41.331355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3474 21:34:41.332166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3476 21:34:41.384065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3477 21:34:41.384877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3479 21:34:41.437855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3480 21:34:41.438665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3482 21:34:41.485053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3483 21:34:41.485866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3485 21:34:41.530181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3486 21:34:41.530999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3488 21:34:41.582483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3489 21:34:41.583295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3491 21:34:41.631527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3492 21:34:41.632378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3494 21:34:41.683190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3495 21:34:41.684033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3497 21:34:41.735612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3498 21:34:41.736471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3500 21:34:41.786940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3501 21:34:41.787753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3503 21:34:41.839949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3504 21:34:41.840818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3506 21:34:41.886339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3507 21:34:41.887175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3509 21:34:41.936717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3510 21:34:41.937517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3512 21:34:41.981669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3513 21:34:41.982469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3515 21:34:42.031287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3516 21:34:42.032088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3518 21:34:42.079508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3519 21:34:42.080366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3521 21:34:42.130901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3522 21:34:42.131802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3524 21:34:42.182760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3525 21:34:42.183588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3527 21:34:42.231950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3528 21:34:42.232975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3530 21:34:42.277203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3531 21:34:42.278021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3533 21:34:42.331260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3534 21:34:42.332619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3536 21:34:42.376520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3537 21:34:42.377308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3539 21:34:42.427232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3540 21:34:42.428170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3542 21:34:42.472399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3543 21:34:42.473183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3545 21:34:42.525724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3546 21:34:42.526525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3548 21:34:42.576443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3549 21:34:42.577252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3551 21:34:42.623104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3552 21:34:42.623925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3554 21:34:42.667353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3555 21:34:42.668152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3557 21:34:42.709589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3558 21:34:42.710400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3560 21:34:42.753208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3561 21:34:42.754077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3563 21:34:42.804796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3564 21:34:42.805656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3566 21:34:42.849280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3567 21:34:42.850127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3569 21:34:42.900247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3570 21:34:42.901098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3572 21:34:42.958595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3573 21:34:42.959433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3575 21:34:43.001782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3576 21:34:43.002644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3578 21:34:43.045242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3579 21:34:43.046064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3581 21:34:43.089754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3582 21:34:43.090606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3584 21:34:43.133353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3585 21:34:43.134168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3587 21:34:43.185492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3588 21:34:43.186333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3590 21:34:43.229461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3591 21:34:43.230279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3593 21:34:43.271898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3594 21:34:43.272773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3596 21:34:43.320416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3597 21:34:43.321229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3599 21:34:43.375918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3600 21:34:43.376794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3602 21:34:43.427698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3603 21:34:43.428549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3605 21:34:43.483721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3606 21:34:43.484624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3608 21:34:43.534296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3609 21:34:43.535107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3611 21:34:43.578568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3612 21:34:43.579403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3614 21:34:43.630497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3615 21:34:43.631301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3617 21:34:43.678091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3618 21:34:43.678882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3620 21:34:43.725335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3621 21:34:43.726159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3623 21:34:43.774600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3624 21:34:43.775394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3626 21:34:43.828711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3627 21:34:43.829509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3629 21:34:43.885687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3630 21:34:43.887751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3632 21:34:43.936938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3633 21:34:43.937447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3635 21:34:43.987060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3636 21:34:43.987850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3638 21:34:44.037947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3639 21:34:44.038751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3641 21:34:44.086712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3642 21:34:44.087514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3644 21:34:44.138243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3645 21:34:44.139054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3647 21:34:44.194536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3648 21:34:44.195352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3650 21:34:44.244937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3651 21:34:44.245744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3653 21:34:44.297681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3654 21:34:44.298493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3656 21:34:44.348485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3657 21:34:44.349315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3659 21:34:44.401569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3660 21:34:44.402411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3662 21:34:44.445768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3663 21:34:44.446588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3665 21:34:44.503921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3666 21:34:44.504756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3668 21:34:44.547639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3669 21:34:44.548465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3671 21:34:44.591319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3672 21:34:44.592110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3674 21:34:44.642545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3675 21:34:44.643365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3677 21:34:44.686805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3678 21:34:44.687609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3680 21:34:44.734166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3681 21:34:44.734981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3683 21:34:44.782533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3684 21:34:44.783331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3686 21:34:44.839191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3687 21:34:44.840028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3689 21:34:44.887385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3690 21:34:44.888182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3692 21:34:44.938359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3693 21:34:44.939158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3695 21:34:44.984238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3696 21:34:44.985029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3698 21:34:45.036715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3699 21:34:45.037511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3701 21:34:45.091469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3702 21:34:45.092297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3704 21:34:45.134051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3705 21:34:45.134845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3707 21:34:45.189225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3708 21:34:45.190149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3710 21:34:45.243771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3711 21:34:45.244756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3713 21:34:45.295231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3714 21:34:45.296094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3716 21:34:45.350019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3717 21:34:45.350838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3719 21:34:45.397831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3720 21:34:45.398626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3722 21:34:45.453272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3723 21:34:45.454071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3725 21:34:45.506427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3726 21:34:45.507219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3728 21:34:45.556451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3729 21:34:45.557276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3731 21:34:45.609355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3732 21:34:45.610147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3734 21:34:45.654108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3735 21:34:45.654920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3737 21:34:45.702943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3738 21:34:45.703748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3740 21:34:45.767502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3741 21:34:45.768361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3743 21:34:45.812184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3744 21:34:45.813002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3746 21:34:45.862325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3747 21:34:45.863134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3749 21:34:45.917200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3750 21:34:45.917994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3752 21:34:45.968641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3753 21:34:45.969457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3755 21:34:46.019071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3756 21:34:46.019864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3758 21:34:46.071909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3759 21:34:46.072724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3761 21:34:46.123485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3762 21:34:46.124294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3764 21:34:46.176375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3765 21:34:46.177170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3767 21:34:46.226401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3768 21:34:46.227183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3770 21:34:46.276086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3771 21:34:46.276879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3773 21:34:46.320796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3774 21:34:46.321589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3776 21:34:46.363358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3777 21:34:46.363895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3779 21:34:46.417279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3780 21:34:46.418011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3782 21:34:46.471858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3783 21:34:46.472600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3785 21:34:46.522697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3786 21:34:46.523424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3788 21:34:46.570146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3789 21:34:46.570778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3791 21:34:46.615825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3792 21:34:46.616489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3794 21:34:46.661869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3795 21:34:46.662693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3797 21:34:46.706327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3798 21:34:46.707109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3800 21:34:46.761095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3801 21:34:46.761889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3803 21:34:46.816401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3804 21:34:46.817180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3806 21:34:46.859238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3807 21:34:46.860061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3809 21:34:46.916572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3810 21:34:46.917357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3812 21:34:46.964835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3813 21:34:46.965620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3815 21:34:47.010426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3816 21:34:47.011195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3818 21:34:47.057989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3819 21:34:47.058781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3821 21:34:47.107768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3822 21:34:47.108571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3824 21:34:47.162054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3825 21:34:47.162843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3827 21:34:47.218447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3828 21:34:47.219235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3830 21:34:47.268243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3831 21:34:47.269029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3833 21:34:47.318932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3834 21:34:47.319712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3836 21:34:47.368550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3837 21:34:47.369339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3839 21:34:47.420949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3840 21:34:47.421758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3842 21:34:47.473992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3843 21:34:47.474786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3845 21:34:47.525818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3846 21:34:47.526600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3848 21:34:47.573542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3849 21:34:47.574335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3851 21:34:47.622288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3852 21:34:47.623079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3854 21:34:47.669762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3855 21:34:47.670555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3857 21:34:47.716356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3858 21:34:47.717150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3860 21:34:47.767141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3861 21:34:47.768035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3863 21:34:47.811545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3864 21:34:47.812370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3866 21:34:47.860862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3867 21:34:47.861665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3869 21:34:47.907784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3870 21:34:47.908621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3872 21:34:47.953799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3873 21:34:47.954592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3875 21:34:48.006059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3876 21:34:48.006953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3878 21:34:48.053280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3879 21:34:48.054112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3881 21:34:48.096150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3882 21:34:48.096951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3884 21:34:48.155235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3885 21:34:48.156077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3887 21:34:48.207002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3888 21:34:48.207813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3890 21:34:48.255705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3891 21:34:48.256501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3893 21:34:48.308058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3894 21:34:48.308811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3896 21:34:48.357739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3897 21:34:48.358465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3899 21:34:48.402620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3900 21:34:48.403476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3902 21:34:48.451657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3903 21:34:48.452473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3905 21:34:48.497371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3906 21:34:48.498145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3908 21:34:48.543189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3909 21:34:48.544020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3911 21:34:48.590550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3912 21:34:48.591328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3914 21:34:48.633949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3915 21:34:48.634743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3917 21:34:48.690544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3918 21:34:48.691285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3920 21:34:48.735626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3921 21:34:48.736329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3923 21:34:48.786869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3924 21:34:48.787643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3926 21:34:48.836858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3927 21:34:48.837550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3929 21:34:48.893402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3930 21:34:48.894143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3932 21:34:48.949869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3933 21:34:48.950631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3935 21:34:48.996603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3936 21:34:48.997364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3938 21:34:49.051618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3939 21:34:49.052348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3941 21:34:49.104923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3942 21:34:49.105687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3944 21:34:49.159739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3945 21:34:49.160476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3947 21:34:49.203717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3948 21:34:49.204513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3950 21:34:49.253318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3951 21:34:49.254012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3953 21:34:49.304641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3954 21:34:49.305413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3956 21:34:49.353035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3957 21:34:49.353817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3959 21:34:49.396408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3960 21:34:49.397162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3962 21:34:49.445846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3963 21:34:49.446582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3965 21:34:49.498510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3966 21:34:49.499292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3968 21:34:49.541683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3969 21:34:49.542383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3971 21:34:49.593455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3972 21:34:49.594225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3974 21:34:49.641498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3975 21:34:49.642206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3977 21:34:49.684456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3978 21:34:49.685227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3980 21:34:49.739761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3981 21:34:49.740524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
3983 21:34:49.790095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
3984 21:34:49.790876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
3986 21:34:49.842506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
3987 21:34:49.843257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
3989 21:34:49.889892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
3990 21:34:49.890743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
3992 21:34:49.941223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
3993 21:34:49.941965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
3995 21:34:49.988056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
3996 21:34:49.988827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
3998 21:34:50.031549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
3999 21:34:50.032277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4001 21:34:50.073971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4002 21:34:50.074653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4004 21:34:50.129090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4005 21:34:50.129827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4007 21:34:50.181558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4008 21:34:50.182293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4010 21:34:50.239824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4011 21:34:50.240569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4013 21:34:50.283032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4014 21:34:50.283771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4016 21:34:50.340255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4017 21:34:50.341053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4019 21:34:50.394514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4020 21:34:50.395379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4022 21:34:50.444197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4023 21:34:50.444996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4025 21:34:50.492101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4026 21:34:50.493014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4028 21:34:50.538380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4029 21:34:50.539174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4031 21:34:50.593526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4032 21:34:50.594269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4034 21:34:50.645097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4035 21:34:50.645862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4037 21:34:50.695022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4038 21:34:50.695765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4040 21:34:50.746392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4041 21:34:50.747118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4043 21:34:50.797191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4044 21:34:50.797945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4046 21:34:50.848563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4047 21:34:50.849291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4049 21:34:50.896258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4050 21:34:50.897006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4052 21:34:50.947590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4053 21:34:50.948351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4055 21:34:50.996401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4056 21:34:50.997139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4058 21:34:51.049035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4059 21:34:51.049767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4061 21:34:51.113177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4062 21:34:51.113927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4064 21:34:51.164609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4065 21:34:51.165328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4067 21:34:51.214344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4068 21:34:51.215077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4070 21:34:51.268448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4071 21:34:51.269143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4073 21:34:51.325177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4074 21:34:51.325921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4076 21:34:51.376335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4077 21:34:51.377075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4079 21:34:51.423099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4080 21:34:51.423877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4082 21:34:51.472394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4083 21:34:51.473108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4085 21:34:51.527868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4086 21:34:51.528695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4088 21:34:51.581332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4089 21:34:51.582102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4091 21:34:51.635676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4092 21:34:51.636540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4094 21:34:51.696195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4095 21:34:51.696979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4097 21:34:51.740278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4098 21:34:51.741007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4100 21:34:51.792901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4101 21:34:51.793666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4103 21:34:51.844500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4104 21:34:51.845248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4106 21:34:51.895635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4107 21:34:51.896515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4109 21:34:51.952291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4110 21:34:51.953050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4112 21:34:51.997219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4113 21:34:51.997742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4115 21:34:52.055458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4116 21:34:52.058813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4118 21:34:52.105399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4119 21:34:52.106394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4121 21:34:52.152553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4122 21:34:52.153758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4124 21:34:52.203335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4125 21:34:52.204071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4127 21:34:52.246401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4128 21:34:52.247088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4130 21:34:52.305453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4131 21:34:52.306148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4133 21:34:52.355292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4134 21:34:52.356041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4136 21:34:52.412265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4137 21:34:52.412958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4139 21:34:52.463671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4140 21:34:52.464397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4142 21:34:52.799588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4143 21:34:52.800220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4144 21:34:52.800755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4145 21:34:52.801190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4146 21:34:52.801606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4147 21:34:52.802292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4149 21:34:52.803537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4151 21:34:52.804776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4153 21:34:52.805954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4155 21:34:52.807127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4157 21:34:52.808389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4158 21:34:52.809071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4160 21:34:52.826099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4161 21:34:52.826789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4163 21:34:52.876712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4164 21:34:52.877419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4166 21:34:52.925755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4167 21:34:52.926451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4169 21:34:52.974436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4170 21:34:52.975130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4172 21:34:53.027462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4173 21:34:53.028172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4175 21:34:53.083445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4176 21:34:53.084152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4178 21:34:53.131912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4179 21:34:53.132641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4181 21:34:53.181950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4182 21:34:53.182644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4184 21:34:53.238595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4185 21:34:53.239304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4187 21:34:53.291826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4189 21:34:53.294845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4190 21:34:53.350539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4191 21:34:53.351288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4193 21:34:53.397952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4194 21:34:53.398658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4196 21:34:53.456463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4197 21:34:53.457183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4199 21:34:53.509477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4200 21:34:53.510173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4202 21:34:53.559229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4203 21:34:53.559937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4205 21:34:53.613699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4206 21:34:53.614492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4208 21:34:53.665949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4209 21:34:53.666627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4211 21:34:53.714918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4212 21:34:53.715586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4214 21:34:53.770703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4215 21:34:53.771368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4217 21:34:53.819187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4218 21:34:53.819849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4220 21:34:53.870358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4221 21:34:53.871041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4223 21:34:53.919717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4224 21:34:53.920447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4226 21:34:53.979945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4227 21:34:53.980673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4229 21:34:54.033561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4230 21:34:54.034259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4232 21:34:54.084074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4233 21:34:54.084832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4235 21:34:54.132857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4236 21:34:54.133568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4238 21:34:54.182556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4239 21:34:54.183270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4241 21:34:54.232326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4242 21:34:54.233027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4244 21:34:54.281271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4245 21:34:54.281960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4247 21:34:54.338563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4248 21:34:54.339433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4250 21:34:54.380637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4251 21:34:54.381451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4253 21:34:54.432526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4254 21:34:54.433358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4256 21:34:54.486075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4257 21:34:54.486893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4259 21:34:54.539120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4260 21:34:54.539955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4262 21:34:54.586479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4263 21:34:54.587354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4265 21:34:54.644810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4266 21:34:54.645689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4268 21:34:54.839799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4269 21:34:54.840760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4271 21:34:54.894623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4272 21:34:54.895461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4274 21:34:54.945401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4275 21:34:54.946271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4277 21:34:54.992820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4278 21:34:54.993652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4280 21:34:55.046831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4281 21:34:55.047690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4283 21:34:55.100937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4284 21:34:55.101801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4286 21:34:55.154009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4287 21:34:55.154850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4289 21:34:55.212285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4290 21:34:55.213131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4292 21:34:55.262445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4293 21:34:55.263280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4295 21:34:55.310667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4296 21:34:55.311523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4298 21:34:55.359277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4299 21:34:55.360112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4301 21:34:55.409443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4302 21:34:55.410300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4304 21:34:55.462145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4305 21:34:55.463039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4307 21:34:55.505411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4308 21:34:55.506255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4310 21:34:55.558904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4311 21:34:55.559740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4313 21:34:55.609270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4314 21:34:55.610129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4316 21:34:55.662049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4317 21:34:55.662897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4319 21:34:55.725550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4320 21:34:55.726411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4322 21:34:55.771727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4323 21:34:55.772605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4325 21:34:55.830863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4326 21:34:55.831741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4328 21:34:55.887194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4329 21:34:55.888064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4331 21:34:55.941578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4332 21:34:55.942434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4334 21:34:55.987048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4335 21:34:55.987631 + set +x
4336 21:34:55.988393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4338 21:34:55.993769 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 680092_1.6.2.4.5>
4339 21:34:55.994289 <LAVA_TEST_RUNNER EXIT>
4340 21:34:55.994984 Received signal: <ENDRUN> 1_kselftest-alsa 680092_1.6.2.4.5
4341 21:34:55.995467 Ending use of test pattern.
4342 21:34:55.995902 Ending test lava.1_kselftest-alsa (680092_1.6.2.4.5), duration 39.51
4344 21:34:55.997586 ok: lava_test_shell seems to have completed
4345 21:34:56.021520 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
shardfile-alsa: pass
4346 21:34:56.023399 end: 3.1 lava-test-shell (duration 00:00:40) [common]
4347 21:34:56.024038 end: 3 lava-test-retry (duration 00:00:40) [common]
4348 21:34:56.024665 start: 4 finalize (timeout 00:06:05) [common]
4349 21:34:56.025272 start: 4.1 power-off (timeout 00:00:30) [common]
4350 21:34:56.026245 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4351 21:34:56.060213 >> OK - accepted request
4352 21:34:56.062439 Returned 0 in 0 seconds
4353 21:34:56.163807 end: 4.1 power-off (duration 00:00:00) [common]
4355 21:34:56.165785 start: 4.2 read-feedback (timeout 00:06:05) [common]
4356 21:34:56.167135 Listened to connection for namespace 'common' for up to 1s
4357 21:34:57.167728 Finalising connection for namespace 'common'
4358 21:34:57.168247 Disconnecting from shell: Finalise
4359 21:34:57.168541 / #
4360 21:34:57.269206 end: 4.2 read-feedback (duration 00:00:01) [common]
4361 21:34:57.269699 end: 4 finalize (duration 00:00:01) [common]
4362 21:34:57.270108 Cleaning after the job
4363 21:34:57.270451 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/ramdisk
4364 21:34:57.278617 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/kernel
4365 21:34:57.294480 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/dtb
4366 21:34:57.295629 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/nfsrootfs
4367 21:34:57.350291 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680092/tftp-deploy-dccgsc1z/modules
4368 21:34:57.357412 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/680092
4369 21:35:00.738321 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/680092
4370 21:35:00.738946 Job finished correctly