Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 21:49:21.367524 lava-dispatcher, installed at version: 2024.01
2 21:49:21.368346 start: 0 validate
3 21:49:21.368850 Start time: 2024-08-30 21:49:21.368819+00:00 (UTC)
4 21:49:21.369426 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:49:21.370046 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 21:49:21.409791 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:49:21.410388 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-207-gfb24560f31f9d%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:49:21.441432 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:49:21.442443 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-207-gfb24560f31f9d%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:49:21.474631 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:49:21.475254 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 21:49:21.509833 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 21:49:21.510435 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-207-gfb24560f31f9d%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 21:49:21.549545 validate duration: 0.18
16 21:49:21.550583 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 21:49:21.550986 start: 1.1 download-retry (timeout 00:10:00) [common]
18 21:49:21.551387 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 21:49:21.552110 Not decompressing ramdisk as can be used compressed.
20 21:49:21.552691 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 21:49:21.553045 saving as /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/ramdisk/initrd.cpio.gz
22 21:49:21.553390 total size: 5628169 (5 MB)
23 21:49:21.591149 progress 0 % (0 MB)
24 21:49:21.595370 progress 5 % (0 MB)
25 21:49:21.599619 progress 10 % (0 MB)
26 21:49:21.603273 progress 15 % (0 MB)
27 21:49:21.607260 progress 20 % (1 MB)
28 21:49:21.610941 progress 25 % (1 MB)
29 21:49:21.615043 progress 30 % (1 MB)
30 21:49:21.619087 progress 35 % (1 MB)
31 21:49:21.622794 progress 40 % (2 MB)
32 21:49:21.626886 progress 45 % (2 MB)
33 21:49:21.630533 progress 50 % (2 MB)
34 21:49:21.634595 progress 55 % (2 MB)
35 21:49:21.638737 progress 60 % (3 MB)
36 21:49:21.642395 progress 65 % (3 MB)
37 21:49:21.646446 progress 70 % (3 MB)
38 21:49:21.650217 progress 75 % (4 MB)
39 21:49:21.654347 progress 80 % (4 MB)
40 21:49:21.658119 progress 85 % (4 MB)
41 21:49:21.662316 progress 90 % (4 MB)
42 21:49:21.666357 progress 95 % (5 MB)
43 21:49:21.669750 progress 100 % (5 MB)
44 21:49:21.670411 5 MB downloaded in 0.12 s (45.87 MB/s)
45 21:49:21.670959 end: 1.1.1 http-download (duration 00:00:00) [common]
47 21:49:21.671872 end: 1.1 download-retry (duration 00:00:00) [common]
48 21:49:21.672207 start: 1.2 download-retry (timeout 00:10:00) [common]
49 21:49:21.672497 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 21:49:21.672966 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/gcc-12/kernel/Image
51 21:49:21.673220 saving as /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/kernel/Image
52 21:49:21.673438 total size: 45308416 (43 MB)
53 21:49:21.673654 No compression specified
54 21:49:21.711723 progress 0 % (0 MB)
55 21:49:21.741606 progress 5 % (2 MB)
56 21:49:21.771658 progress 10 % (4 MB)
57 21:49:21.801408 progress 15 % (6 MB)
58 21:49:21.831468 progress 20 % (8 MB)
59 21:49:21.861468 progress 25 % (10 MB)
60 21:49:21.891355 progress 30 % (12 MB)
61 21:49:21.921592 progress 35 % (15 MB)
62 21:49:21.952181 progress 40 % (17 MB)
63 21:49:21.982053 progress 45 % (19 MB)
64 21:49:22.012846 progress 50 % (21 MB)
65 21:49:22.043421 progress 55 % (23 MB)
66 21:49:22.073466 progress 60 % (25 MB)
67 21:49:22.104034 progress 65 % (28 MB)
68 21:49:22.135069 progress 70 % (30 MB)
69 21:49:22.167642 progress 75 % (32 MB)
70 21:49:22.197725 progress 80 % (34 MB)
71 21:49:22.227457 progress 85 % (36 MB)
72 21:49:22.257315 progress 90 % (38 MB)
73 21:49:22.287016 progress 95 % (41 MB)
74 21:49:22.316265 progress 100 % (43 MB)
75 21:49:22.316958 43 MB downloaded in 0.64 s (67.15 MB/s)
76 21:49:22.317430 end: 1.2.1 http-download (duration 00:00:01) [common]
78 21:49:22.318247 end: 1.2 download-retry (duration 00:00:01) [common]
79 21:49:22.318523 start: 1.3 download-retry (timeout 00:09:59) [common]
80 21:49:22.318788 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 21:49:22.319402 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 21:49:22.319689 saving as /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/dtb/meson-g12b-a311d-libretech-cc.dtb
83 21:49:22.319904 total size: 54667 (0 MB)
84 21:49:22.320145 No compression specified
85 21:49:22.362743 progress 59 % (0 MB)
86 21:49:22.363754 progress 100 % (0 MB)
87 21:49:22.364446 0 MB downloaded in 0.04 s (1.17 MB/s)
88 21:49:22.365032 end: 1.3.1 http-download (duration 00:00:00) [common]
90 21:49:22.366019 end: 1.3 download-retry (duration 00:00:00) [common]
91 21:49:22.366332 start: 1.4 download-retry (timeout 00:09:59) [common]
92 21:49:22.366656 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 21:49:22.367316 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 21:49:22.367630 saving as /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/nfsrootfs/full.rootfs.tar
95 21:49:22.367895 total size: 120894716 (115 MB)
96 21:49:22.368198 Using unxz to decompress xz
97 21:49:22.401399 progress 0 % (0 MB)
98 21:49:23.189559 progress 5 % (5 MB)
99 21:49:24.030774 progress 10 % (11 MB)
100 21:49:24.922155 progress 15 % (17 MB)
101 21:49:25.792039 progress 20 % (23 MB)
102 21:49:26.452807 progress 25 % (28 MB)
103 21:49:27.285180 progress 30 % (34 MB)
104 21:49:28.118351 progress 35 % (40 MB)
105 21:49:28.484388 progress 40 % (46 MB)
106 21:49:28.882684 progress 45 % (51 MB)
107 21:49:29.678104 progress 50 % (57 MB)
108 21:49:30.577791 progress 55 % (63 MB)
109 21:49:31.369420 progress 60 % (69 MB)
110 21:49:32.129387 progress 65 % (74 MB)
111 21:49:32.912526 progress 70 % (80 MB)
112 21:49:33.739468 progress 75 % (86 MB)
113 21:49:34.535481 progress 80 % (92 MB)
114 21:49:35.358138 progress 85 % (98 MB)
115 21:49:36.220142 progress 90 % (103 MB)
116 21:49:36.995623 progress 95 % (109 MB)
117 21:49:37.834027 progress 100 % (115 MB)
118 21:49:37.846473 115 MB downloaded in 15.48 s (7.45 MB/s)
119 21:49:37.847471 end: 1.4.1 http-download (duration 00:00:15) [common]
121 21:49:37.849258 end: 1.4 download-retry (duration 00:00:15) [common]
122 21:49:37.849820 start: 1.5 download-retry (timeout 00:09:44) [common]
123 21:49:37.850377 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 21:49:37.851233 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/gcc-12/modules.tar.xz
125 21:49:37.851722 saving as /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/modules/modules.tar
126 21:49:37.852203 total size: 11509952 (10 MB)
127 21:49:37.852653 Using unxz to decompress xz
128 21:49:37.891614 progress 0 % (0 MB)
129 21:49:37.960451 progress 5 % (0 MB)
130 21:49:38.037379 progress 10 % (1 MB)
131 21:49:38.119962 progress 15 % (1 MB)
132 21:49:38.200085 progress 20 % (2 MB)
133 21:49:38.276794 progress 25 % (2 MB)
134 21:49:38.358976 progress 30 % (3 MB)
135 21:49:38.433555 progress 35 % (3 MB)
136 21:49:38.512436 progress 40 % (4 MB)
137 21:49:38.587972 progress 45 % (4 MB)
138 21:49:38.664895 progress 50 % (5 MB)
139 21:49:38.741151 progress 55 % (6 MB)
140 21:49:38.820697 progress 60 % (6 MB)
141 21:49:38.908319 progress 65 % (7 MB)
142 21:49:38.985934 progress 70 % (7 MB)
143 21:49:39.081369 progress 75 % (8 MB)
144 21:49:39.175850 progress 80 % (8 MB)
145 21:49:39.251831 progress 85 % (9 MB)
146 21:49:39.327048 progress 90 % (9 MB)
147 21:49:39.399136 progress 95 % (10 MB)
148 21:49:39.475621 progress 100 % (10 MB)
149 21:49:39.486398 10 MB downloaded in 1.63 s (6.72 MB/s)
150 21:49:39.486996 end: 1.5.1 http-download (duration 00:00:02) [common]
152 21:49:39.487847 end: 1.5 download-retry (duration 00:00:02) [common]
153 21:49:39.488349 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 21:49:39.488924 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 21:49:56.147739 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/680279/extract-nfsrootfs-n8mi20uc
156 21:49:56.148391 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 21:49:56.148717 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 21:49:56.149466 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf
159 21:49:56.150038 makedir: /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin
160 21:49:56.150474 makedir: /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/tests
161 21:49:56.150893 makedir: /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/results
162 21:49:56.151370 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-add-keys
163 21:49:56.151973 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-add-sources
164 21:49:56.152551 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-background-process-start
165 21:49:56.153073 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-background-process-stop
166 21:49:56.153605 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-common-functions
167 21:49:56.154108 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-echo-ipv4
168 21:49:56.154645 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-install-packages
169 21:49:56.155180 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-installed-packages
170 21:49:56.155670 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-os-build
171 21:49:56.156194 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-probe-channel
172 21:49:56.156751 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-probe-ip
173 21:49:56.157284 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-target-ip
174 21:49:56.157889 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-target-mac
175 21:49:56.158402 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-target-storage
176 21:49:56.158907 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-test-case
177 21:49:56.159392 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-test-event
178 21:49:56.159881 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-test-feedback
179 21:49:56.160406 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-test-raise
180 21:49:56.160891 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-test-reference
181 21:49:56.161378 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-test-runner
182 21:49:56.161864 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-test-set
183 21:49:56.162342 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-test-shell
184 21:49:56.162828 Updating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-add-keys (debian)
185 21:49:56.163356 Updating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-add-sources (debian)
186 21:49:56.164005 Updating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-install-packages (debian)
187 21:49:56.164533 Updating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-installed-packages (debian)
188 21:49:56.165028 Updating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/bin/lava-os-build (debian)
189 21:49:56.165460 Creating /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/environment
190 21:49:56.165829 LAVA metadata
191 21:49:56.166082 - LAVA_JOB_ID=680279
192 21:49:56.166293 - LAVA_DISPATCHER_IP=192.168.6.2
193 21:49:56.166652 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 21:49:56.167589 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 21:49:56.167895 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 21:49:56.168127 skipped lava-vland-overlay
197 21:49:56.168368 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 21:49:56.168623 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 21:49:56.168838 skipped lava-multinode-overlay
200 21:49:56.169186 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 21:49:56.169443 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 21:49:56.169695 Loading test definitions
203 21:49:56.169967 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 21:49:56.170181 Using /lava-680279 at stage 0
205 21:49:56.171241 uuid=680279_1.6.2.4.1 testdef=None
206 21:49:56.171538 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 21:49:56.171796 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 21:49:56.173368 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 21:49:56.174148 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 21:49:56.176202 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 21:49:56.177037 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 21:49:56.178865 runner path: /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/0/tests/0_timesync-off test_uuid 680279_1.6.2.4.1
215 21:49:56.179409 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 21:49:56.180240 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 21:49:56.180574 Using /lava-680279 at stage 0
219 21:49:56.180939 Fetching tests from https://github.com/kernelci/test-definitions.git
220 21:49:56.181232 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/0/tests/1_kselftest-alsa'
221 21:49:59.813436 Running '/usr/bin/git checkout kernelci.org
222 21:50:00.266395 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 21:50:00.268977 uuid=680279_1.6.2.4.5 testdef=None
224 21:50:00.269664 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 21:50:00.271304 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 21:50:00.277547 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 21:50:00.279350 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 21:50:00.288537 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 21:50:00.291803 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 21:50:00.302024 runner path: /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/0/tests/1_kselftest-alsa test_uuid 680279_1.6.2.4.5
234 21:50:00.302620 BOARD='meson-g12b-a311d-libretech-cc'
235 21:50:00.303079 BRANCH='mainline'
236 21:50:00.303523 SKIPFILE='/dev/null'
237 21:50:00.303964 SKIP_INSTALL='True'
238 21:50:00.304485 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 21:50:00.304952 TST_CASENAME=''
240 21:50:00.305400 TST_CMDFILES='alsa'
241 21:50:00.306589 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 21:50:00.308411 Creating lava-test-runner.conf files
244 21:50:00.308839 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/680279/lava-overlay-l8p4z8uf/lava-680279/0 for stage 0
245 21:50:00.309534 - 0_timesync-off
246 21:50:00.310003 - 1_kselftest-alsa
247 21:50:00.310662 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 21:50:00.311220 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 21:50:23.732641 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 21:50:23.733070 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 21:50:23.733363 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 21:50:23.733670 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 21:50:23.733962 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 21:50:24.357146 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 21:50:24.357683 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 21:50:24.357993 extracting modules file /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/modules/modules.tar to /var/lib/lava/dispatcher/tmp/680279/extract-nfsrootfs-n8mi20uc
257 21:50:26.114271 extracting modules file /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/modules/modules.tar to /var/lib/lava/dispatcher/tmp/680279/extract-overlay-ramdisk-phv5pjhf/ramdisk
258 21:50:27.574505 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 21:50:27.575000 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 21:50:27.575282 [common] Applying overlay to NFS
261 21:50:27.575499 [common] Applying overlay /var/lib/lava/dispatcher/tmp/680279/compress-overlay-sfh5k0um/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/680279/extract-nfsrootfs-n8mi20uc
262 21:50:30.357509 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 21:50:30.357993 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 21:50:30.358283 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 21:50:30.358528 Converting downloaded kernel to a uImage
266 21:50:30.358850 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/kernel/Image /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/kernel/uImage
267 21:50:30.813242 output: Image Name:
268 21:50:30.813665 output: Created: Fri Aug 30 21:50:30 2024
269 21:50:30.813924 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 21:50:30.814142 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
271 21:50:30.814383 output: Load Address: 01080000
272 21:50:30.814618 output: Entry Point: 01080000
273 21:50:30.814854 output:
274 21:50:30.815232 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 21:50:30.815554 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 21:50:30.815840 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 21:50:30.816203 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 21:50:30.816539 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 21:50:30.816856 Building ramdisk /var/lib/lava/dispatcher/tmp/680279/extract-overlay-ramdisk-phv5pjhf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/680279/extract-overlay-ramdisk-phv5pjhf/ramdisk
280 21:50:32.991318 >> 165125 blocks
281 21:50:41.062763 Adding RAMdisk u-boot header.
282 21:50:41.063479 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/680279/extract-overlay-ramdisk-phv5pjhf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/680279/extract-overlay-ramdisk-phv5pjhf/ramdisk.cpio.gz.uboot
283 21:50:41.305447 output: Image Name:
284 21:50:41.305878 output: Created: Fri Aug 30 21:50:41 2024
285 21:50:41.306087 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 21:50:41.306289 output: Data Size: 23247262 Bytes = 22702.40 KiB = 22.17 MiB
287 21:50:41.306491 output: Load Address: 00000000
288 21:50:41.306689 output: Entry Point: 00000000
289 21:50:41.306886 output:
290 21:50:41.307579 rename /var/lib/lava/dispatcher/tmp/680279/extract-overlay-ramdisk-phv5pjhf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/ramdisk/ramdisk.cpio.gz.uboot
291 21:50:41.308038 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 21:50:41.308602 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 21:50:41.309127 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 21:50:41.309577 No LXC device requested
295 21:50:41.310070 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 21:50:41.310571 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 21:50:41.311058 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 21:50:41.311464 Checking files for TFTP limit of 4294967296 bytes.
299 21:50:41.314146 end: 1 tftp-deploy (duration 00:01:20) [common]
300 21:50:41.314718 start: 2 uboot-action (timeout 00:05:00) [common]
301 21:50:41.315237 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 21:50:41.315730 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 21:50:41.316263 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 21:50:41.316786 Using kernel file from prepare-kernel: 680279/tftp-deploy-1zi1cn26/kernel/uImage
305 21:50:41.317404 substitutions:
306 21:50:41.317805 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 21:50:41.318204 - {DTB_ADDR}: 0x01070000
308 21:50:41.318602 - {DTB}: 680279/tftp-deploy-1zi1cn26/dtb/meson-g12b-a311d-libretech-cc.dtb
309 21:50:41.318997 - {INITRD}: 680279/tftp-deploy-1zi1cn26/ramdisk/ramdisk.cpio.gz.uboot
310 21:50:41.319388 - {KERNEL_ADDR}: 0x01080000
311 21:50:41.319775 - {KERNEL}: 680279/tftp-deploy-1zi1cn26/kernel/uImage
312 21:50:41.320199 - {LAVA_MAC}: None
313 21:50:41.320626 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/680279/extract-nfsrootfs-n8mi20uc
314 21:50:41.321023 - {NFS_SERVER_IP}: 192.168.6.2
315 21:50:41.321409 - {PRESEED_CONFIG}: None
316 21:50:41.321794 - {PRESEED_LOCAL}: None
317 21:50:41.322180 - {RAMDISK_ADDR}: 0x08000000
318 21:50:41.322563 - {RAMDISK}: 680279/tftp-deploy-1zi1cn26/ramdisk/ramdisk.cpio.gz.uboot
319 21:50:41.322948 - {ROOT_PART}: None
320 21:50:41.323331 - {ROOT}: None
321 21:50:41.323712 - {SERVER_IP}: 192.168.6.2
322 21:50:41.324118 - {TEE_ADDR}: 0x83000000
323 21:50:41.324503 - {TEE}: None
324 21:50:41.324885 Parsed boot commands:
325 21:50:41.325259 - setenv autoload no
326 21:50:41.325639 - setenv initrd_high 0xffffffff
327 21:50:41.326016 - setenv fdt_high 0xffffffff
328 21:50:41.326395 - dhcp
329 21:50:41.326772 - setenv serverip 192.168.6.2
330 21:50:41.327154 - tftpboot 0x01080000 680279/tftp-deploy-1zi1cn26/kernel/uImage
331 21:50:41.327538 - tftpboot 0x08000000 680279/tftp-deploy-1zi1cn26/ramdisk/ramdisk.cpio.gz.uboot
332 21:50:41.327923 - tftpboot 0x01070000 680279/tftp-deploy-1zi1cn26/dtb/meson-g12b-a311d-libretech-cc.dtb
333 21:50:41.328334 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/680279/extract-nfsrootfs-n8mi20uc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 21:50:41.328732 - bootm 0x01080000 0x08000000 0x01070000
335 21:50:41.329220 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 21:50:41.330681 start: 2.3 connect-device (timeout 00:05:00) [common]
338 21:50:41.331089 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 21:50:41.346747 Setting prompt string to ['lava-test: # ']
340 21:50:41.347686 end: 2.3 connect-device (duration 00:00:00) [common]
341 21:50:41.348123 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 21:50:41.348492 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 21:50:41.348812 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 21:50:41.349451 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 21:50:41.384315 >> OK - accepted request
346 21:50:41.386715 Returned 0 in 0 seconds
347 21:50:41.487774 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 21:50:41.489417 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 21:50:41.489963 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 21:50:41.490463 Setting prompt string to ['Hit any key to stop autoboot']
352 21:50:41.490906 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 21:50:41.492438 Trying 192.168.56.21...
354 21:50:41.492908 Connected to conserv1.
355 21:50:41.493307 Escape character is '^]'.
356 21:50:41.493715
357 21:50:41.494128 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 21:50:41.494546
359 21:50:52.727210 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 21:50:52.727626 bl2_stage_init 0x01
361 21:50:52.727856 bl2_stage_init 0x81
362 21:50:52.732745 hw id: 0x0000 - pwm id 0x01
363 21:50:52.733078 bl2_stage_init 0xc1
364 21:50:52.733302 bl2_stage_init 0x02
365 21:50:52.733523
366 21:50:52.738318 L0:00000000
367 21:50:52.738609 L1:20000703
368 21:50:52.738828 L2:00008067
369 21:50:52.739062 L3:14000000
370 21:50:52.743824 B2:00402000
371 21:50:52.744125 B1:e0f83180
372 21:50:52.744354
373 21:50:52.744564 TE: 58124
374 21:50:52.744769
375 21:50:52.749422 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 21:50:52.749695
377 21:50:52.749916 Board ID = 1
378 21:50:52.755125 Set A53 clk to 24M
379 21:50:52.755391 Set A73 clk to 24M
380 21:50:52.755600 Set clk81 to 24M
381 21:50:52.760686 A53 clk: 1200 MHz
382 21:50:52.760952 A73 clk: 1200 MHz
383 21:50:52.761158 CLK81: 166.6M
384 21:50:52.761375 smccc: 00012a91
385 21:50:52.766250 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 21:50:52.771911 board id: 1
387 21:50:52.777850 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 21:50:52.788477 fw parse done
389 21:50:52.794398 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 21:50:52.836948 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 21:50:52.847838 PIEI prepare done
392 21:50:52.848151 fastboot data load
393 21:50:52.848365 fastboot data verify
394 21:50:52.853420 verify result: 266
395 21:50:52.859023 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 21:50:52.859293 LPDDR4 probe
397 21:50:52.859518 ddr clk to 1584MHz
398 21:50:52.867010 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 21:50:52.904266
400 21:50:52.904566 dmc_version 0001
401 21:50:52.910944 Check phy result
402 21:50:52.916810 INFO : End of CA training
403 21:50:52.917084 INFO : End of initialization
404 21:50:52.922423 INFO : Training has run successfully!
405 21:50:52.922693 Check phy result
406 21:50:52.928030 INFO : End of initialization
407 21:50:52.928307 INFO : End of read enable training
408 21:50:52.933686 INFO : End of fine write leveling
409 21:50:52.939242 INFO : End of Write leveling coarse delay
410 21:50:52.939520 INFO : Training has run successfully!
411 21:50:52.939730 Check phy result
412 21:50:52.944845 INFO : End of initialization
413 21:50:52.945120 INFO : End of read dq deskew training
414 21:50:52.950387 INFO : End of MPR read delay center optimization
415 21:50:52.956113 INFO : End of write delay center optimization
416 21:50:52.961648 INFO : End of read delay center optimization
417 21:50:52.961912 INFO : End of max read latency training
418 21:50:52.967189 INFO : Training has run successfully!
419 21:50:52.967451 1D training succeed
420 21:50:52.976479 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 21:50:53.024099 Check phy result
422 21:50:53.024689 INFO : End of initialization
423 21:50:53.046780 INFO : End of 2D read delay Voltage center optimization
424 21:50:53.066887 INFO : End of 2D read delay Voltage center optimization
425 21:50:53.118970 INFO : End of 2D write delay Voltage center optimization
426 21:50:53.168403 INFO : End of 2D write delay Voltage center optimization
427 21:50:53.173908 INFO : Training has run successfully!
428 21:50:53.174408
429 21:50:53.174859 channel==0
430 21:50:53.179518 RxClkDly_Margin_A0==88 ps 9
431 21:50:53.180053 TxDqDly_Margin_A0==98 ps 10
432 21:50:53.185121 RxClkDly_Margin_A1==88 ps 9
433 21:50:53.185603 TxDqDly_Margin_A1==88 ps 9
434 21:50:53.186048 TrainedVREFDQ_A0==74
435 21:50:53.190746 TrainedVREFDQ_A1==74
436 21:50:53.191229 VrefDac_Margin_A0==24
437 21:50:53.191667 DeviceVref_Margin_A0==40
438 21:50:53.196266 VrefDac_Margin_A1==25
439 21:50:53.196751 DeviceVref_Margin_A1==40
440 21:50:53.197193
441 21:50:53.197627
442 21:50:53.198061 channel==1
443 21:50:53.201845 RxClkDly_Margin_A0==98 ps 10
444 21:50:53.202325 TxDqDly_Margin_A0==98 ps 10
445 21:50:53.207493 RxClkDly_Margin_A1==98 ps 10
446 21:50:53.207968 TxDqDly_Margin_A1==88 ps 9
447 21:50:53.213081 TrainedVREFDQ_A0==77
448 21:50:53.213561 TrainedVREFDQ_A1==77
449 21:50:53.214000 VrefDac_Margin_A0==22
450 21:50:53.218749 DeviceVref_Margin_A0==37
451 21:50:53.219233 VrefDac_Margin_A1==22
452 21:50:53.224280 DeviceVref_Margin_A1==37
453 21:50:53.224753
454 21:50:53.225192 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 21:50:53.225622
456 21:50:53.257890 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 21:50:53.258536 2D training succeed
458 21:50:53.263358 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 21:50:53.269022 auto size-- 65535DDR cs0 size: 2048MB
460 21:50:53.269597 DDR cs1 size: 2048MB
461 21:50:53.274667 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 21:50:53.275242 cs0 DataBus test pass
463 21:50:53.280217 cs1 DataBus test pass
464 21:50:53.280772 cs0 AddrBus test pass
465 21:50:53.281245 cs1 AddrBus test pass
466 21:50:53.281712
467 21:50:53.285791 100bdlr_step_size ps== 420
468 21:50:53.286353 result report
469 21:50:53.291393 boot times 0Enable ddr reg access
470 21:50:53.296707 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 21:50:53.310218 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 21:50:53.884025 0.0;M3 CHK:0;cm4_sp_mode 0
473 21:50:53.884691 MVN_1=0x00000000
474 21:50:53.889482 MVN_2=0x00000000
475 21:50:53.895176 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 21:50:53.895680 OPS=0x10
477 21:50:53.896162 ring efuse init
478 21:50:53.896599 chipver efuse init
479 21:50:53.900765 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 21:50:53.906406 [0.018961 Inits done]
481 21:50:53.906951 secure task start!
482 21:50:53.907387 high task start!
483 21:50:53.910960 low task start!
484 21:50:53.911452 run into bl31
485 21:50:53.917713 NOTICE: BL31: v1.3(release):4fc40b1
486 21:50:53.925443 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 21:50:53.925985 NOTICE: BL31: G12A normal boot!
488 21:50:53.951335 NOTICE: BL31: BL33 decompress pass
489 21:50:53.956986 ERROR: Error initializing runtime service opteed_fast
490 21:50:55.189920
491 21:50:55.190570
492 21:50:55.198277 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 21:50:55.198795
494 21:50:55.199256 Model: Libre Computer AML-A311D-CC Alta
495 21:50:55.406755 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 21:50:55.430035 DRAM: 2 GiB (effective 3.8 GiB)
497 21:50:55.573128 Core: 408 devices, 31 uclasses, devicetree: separate
498 21:50:55.579015 WDT: Not starting watchdog@f0d0
499 21:50:55.611206 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 21:50:55.623706 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 21:50:55.628581 ** Bad device specification mmc 0 **
502 21:50:55.638952 Card did not respond to voltage select! : -110
503 21:50:55.646569 ** Bad device specification mmc 0 **
504 21:50:55.647058 Couldn't find partition mmc 0
505 21:50:55.654916 Card did not respond to voltage select! : -110
506 21:50:55.660426 ** Bad device specification mmc 0 **
507 21:50:55.660925 Couldn't find partition mmc 0
508 21:50:55.665485 Error: could not access storage.
509 21:50:56.927372 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 21:50:56.928090 bl2_stage_init 0x01
511 21:50:56.928586 bl2_stage_init 0x81
512 21:50:56.932903 hw id: 0x0000 - pwm id 0x01
513 21:50:56.933399 bl2_stage_init 0xc1
514 21:50:56.933860 bl2_stage_init 0x02
515 21:50:56.934308
516 21:50:56.938499 L0:00000000
517 21:50:56.938987 L1:20000703
518 21:50:56.939443 L2:00008067
519 21:50:56.939897 L3:14000000
520 21:50:56.944111 B2:00402000
521 21:50:56.944602 B1:e0f83180
522 21:50:56.945055
523 21:50:56.945503 TE: 58159
524 21:50:56.945947
525 21:50:56.949668 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 21:50:56.950173
527 21:50:56.950633 Board ID = 1
528 21:50:56.955265 Set A53 clk to 24M
529 21:50:56.955755 Set A73 clk to 24M
530 21:50:56.956245 Set clk81 to 24M
531 21:50:56.960928 A53 clk: 1200 MHz
532 21:50:56.961410 A73 clk: 1200 MHz
533 21:50:56.961859 CLK81: 166.6M
534 21:50:56.962305 smccc: 00012ab5
535 21:50:56.966464 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 21:50:56.972085 board id: 1
537 21:50:56.978043 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 21:50:56.988682 fw parse done
539 21:50:56.993920 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 21:50:57.037250 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 21:50:57.048182 PIEI prepare done
542 21:50:57.048873 fastboot data load
543 21:50:57.049447 fastboot data verify
544 21:50:57.053873 verify result: 266
545 21:50:57.059391 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 21:50:57.059898 LPDDR4 probe
547 21:50:57.060376 ddr clk to 1584MHz
548 21:50:57.067379 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 21:50:57.104736
550 21:50:57.105320 dmc_version 0001
551 21:50:57.110342 Check phy result
552 21:50:57.117240 INFO : End of CA training
553 21:50:57.117770 INFO : End of initialization
554 21:50:57.122811 INFO : Training has run successfully!
555 21:50:57.123321 Check phy result
556 21:50:57.128389 INFO : End of initialization
557 21:50:57.128885 INFO : End of read enable training
558 21:50:57.133992 INFO : End of fine write leveling
559 21:50:57.139585 INFO : End of Write leveling coarse delay
560 21:50:57.140105 INFO : Training has run successfully!
561 21:50:57.140540 Check phy result
562 21:50:57.145213 INFO : End of initialization
563 21:50:57.145708 INFO : End of read dq deskew training
564 21:50:57.150789 INFO : End of MPR read delay center optimization
565 21:50:57.156399 INFO : End of write delay center optimization
566 21:50:57.162027 INFO : End of read delay center optimization
567 21:50:57.162530 INFO : End of max read latency training
568 21:50:57.167612 INFO : Training has run successfully!
569 21:50:57.168147 1D training succeed
570 21:50:57.176759 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 21:50:57.224519 Check phy result
572 21:50:57.225507 INFO : End of initialization
573 21:50:57.247156 INFO : End of 2D read delay Voltage center optimization
574 21:50:57.267277 INFO : End of 2D read delay Voltage center optimization
575 21:50:57.319255 INFO : End of 2D write delay Voltage center optimization
576 21:50:57.368592 INFO : End of 2D write delay Voltage center optimization
577 21:50:57.374253 INFO : Training has run successfully!
578 21:50:57.374774
579 21:50:57.375209 channel==0
580 21:50:57.379723 RxClkDly_Margin_A0==88 ps 9
581 21:50:57.380262 TxDqDly_Margin_A0==98 ps 10
582 21:50:57.383078 RxClkDly_Margin_A1==88 ps 9
583 21:50:57.383738 TxDqDly_Margin_A1==98 ps 10
584 21:50:57.388574 TrainedVREFDQ_A0==74
585 21:50:57.389110 TrainedVREFDQ_A1==74
586 21:50:57.394270 VrefDac_Margin_A0==24
587 21:50:57.394800 DeviceVref_Margin_A0==40
588 21:50:57.395258 VrefDac_Margin_A1==24
589 21:50:57.399791 DeviceVref_Margin_A1==40
590 21:50:57.400351
591 21:50:57.400823
592 21:50:57.401270 channel==1
593 21:50:57.401716 RxClkDly_Margin_A0==98 ps 10
594 21:50:57.403131 TxDqDly_Margin_A0==98 ps 10
595 21:50:57.408700 RxClkDly_Margin_A1==88 ps 9
596 21:50:57.409239 TxDqDly_Margin_A1==88 ps 9
597 21:50:57.409693 TrainedVREFDQ_A0==77
598 21:50:57.414299 TrainedVREFDQ_A1==77
599 21:50:57.414809 VrefDac_Margin_A0==22
600 21:50:57.419913 DeviceVref_Margin_A0==37
601 21:50:57.420464 VrefDac_Margin_A1==24
602 21:50:57.420916 DeviceVref_Margin_A1==37
603 21:50:57.421358
604 21:50:57.428786 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 21:50:57.429316
606 21:50:57.456802 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000018 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 21:50:57.457369 2D training succeed
608 21:50:57.468007 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 21:50:57.468536 auto size-- 65535DDR cs0 size: 2048MB
610 21:50:57.473630 DDR cs1 size: 2048MB
611 21:50:57.474154 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 21:50:57.474575 cs0 DataBus test pass
613 21:50:57.479287 cs1 DataBus test pass
614 21:50:57.479793 cs0 AddrBus test pass
615 21:50:57.484824 cs1 AddrBus test pass
616 21:50:57.485327
617 21:50:57.485748 100bdlr_step_size ps== 420
618 21:50:57.486205 result report
619 21:50:57.490416 boot times 0Enable ddr reg access
620 21:50:57.497094 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 21:50:57.510576 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 21:50:58.084326 0.0;M3 CHK:0;cm4_sp_mode 0
623 21:50:58.084970 MVN_1=0x00000000
624 21:50:58.089740 MVN_2=0x00000000
625 21:50:58.095570 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 21:50:58.096158 OPS=0x10
627 21:50:58.096636 ring efuse init
628 21:50:58.097042 chipver efuse init
629 21:50:58.101105 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 21:50:58.106661 [0.018961 Inits done]
631 21:50:58.107118 secure task start!
632 21:50:58.107512 high task start!
633 21:50:58.111343 low task start!
634 21:50:58.111795 run into bl31
635 21:50:58.117910 NOTICE: BL31: v1.3(release):4fc40b1
636 21:50:58.125708 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 21:50:58.126166 NOTICE: BL31: G12A normal boot!
638 21:50:58.151123 NOTICE: BL31: BL33 decompress pass
639 21:50:58.156737 ERROR: Error initializing runtime service opteed_fast
640 21:50:59.389772
641 21:50:59.390179
642 21:50:59.398228 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 21:50:59.398558
644 21:50:59.398786 Model: Libre Computer AML-A311D-CC Alta
645 21:50:59.606632 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 21:50:59.630034 DRAM: 2 GiB (effective 3.8 GiB)
647 21:50:59.772968 Core: 408 devices, 31 uclasses, devicetree: separate
648 21:50:59.778860 WDT: Not starting watchdog@f0d0
649 21:50:59.811073 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 21:50:59.823633 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 21:50:59.828541 ** Bad device specification mmc 0 **
652 21:50:59.838900 Card did not respond to voltage select! : -110
653 21:50:59.846536 ** Bad device specification mmc 0 **
654 21:50:59.847055 Couldn't find partition mmc 0
655 21:50:59.854860 Card did not respond to voltage select! : -110
656 21:50:59.860426 ** Bad device specification mmc 0 **
657 21:50:59.860985 Couldn't find partition mmc 0
658 21:50:59.865438 Error: could not access storage.
659 21:51:00.209013 Net: eth0: ethernet@ff3f0000
660 21:51:00.209661 starting USB...
661 21:51:00.460829 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 21:51:00.461446 Starting the controller
663 21:51:00.467829 USB XHCI 1.10
664 21:51:02.179339 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 21:51:02.180042 bl2_stage_init 0x01
666 21:51:02.180529 bl2_stage_init 0x81
667 21:51:02.184928 hw id: 0x0000 - pwm id 0x01
668 21:51:02.185434 bl2_stage_init 0xc1
669 21:51:02.185890 bl2_stage_init 0x02
670 21:51:02.186337
671 21:51:02.190450 L0:00000000
672 21:51:02.190947 L1:20000703
673 21:51:02.191399 L2:00008067
674 21:51:02.191836 L3:14000000
675 21:51:02.196168 B2:00402000
676 21:51:02.196663 B1:e0f83180
677 21:51:02.197107
678 21:51:02.197548 TE: 58124
679 21:51:02.197991
680 21:51:02.201749 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 21:51:02.202258
682 21:51:02.202720 Board ID = 1
683 21:51:02.207296 Set A53 clk to 24M
684 21:51:02.207798 Set A73 clk to 24M
685 21:51:02.208286 Set clk81 to 24M
686 21:51:02.212975 A53 clk: 1200 MHz
687 21:51:02.213487 A73 clk: 1200 MHz
688 21:51:02.213940 CLK81: 166.6M
689 21:51:02.214386 smccc: 00012a92
690 21:51:02.218477 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 21:51:02.224116 board id: 1
692 21:51:02.230147 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 21:51:02.240675 fw parse done
694 21:51:02.246641 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 21:51:02.289149 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 21:51:02.300101 PIEI prepare done
697 21:51:02.300658 fastboot data load
698 21:51:02.301162 fastboot data verify
699 21:51:02.305771 verify result: 266
700 21:51:02.311333 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 21:51:02.311887 LPDDR4 probe
702 21:51:02.312423 ddr clk to 1584MHz
703 21:51:02.318379 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 21:51:02.356607
705 21:51:02.357166 dmc_version 0001
706 21:51:02.363258 Check phy result
707 21:51:02.369157 INFO : End of CA training
708 21:51:02.369725 INFO : End of initialization
709 21:51:02.374798 INFO : Training has run successfully!
710 21:51:02.375368 Check phy result
711 21:51:02.380328 INFO : End of initialization
712 21:51:02.380901 INFO : End of read enable training
713 21:51:02.386016 INFO : End of fine write leveling
714 21:51:02.391503 INFO : End of Write leveling coarse delay
715 21:51:02.392024 INFO : Training has run successfully!
716 21:51:02.392478 Check phy result
717 21:51:02.397057 INFO : End of initialization
718 21:51:02.397545 INFO : End of read dq deskew training
719 21:51:02.402716 INFO : End of MPR read delay center optimization
720 21:51:02.408253 INFO : End of write delay center optimization
721 21:51:02.413974 INFO : End of read delay center optimization
722 21:51:02.414460 INFO : End of max read latency training
723 21:51:02.419506 INFO : Training has run successfully!
724 21:51:02.420021 1D training succeed
725 21:51:02.428690 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 21:51:02.476352 Check phy result
727 21:51:02.476939 INFO : End of initialization
728 21:51:02.498158 INFO : End of 2D read delay Voltage center optimization
729 21:51:02.518358 INFO : End of 2D read delay Voltage center optimization
730 21:51:02.570431 INFO : End of 2D write delay Voltage center optimization
731 21:51:02.619907 INFO : End of 2D write delay Voltage center optimization
732 21:51:02.625299 INFO : Training has run successfully!
733 21:51:02.625903
734 21:51:02.626423 channel==0
735 21:51:02.631013 RxClkDly_Margin_A0==88 ps 9
736 21:51:02.631588 TxDqDly_Margin_A0==98 ps 10
737 21:51:02.634265 RxClkDly_Margin_A1==88 ps 9
738 21:51:02.634817 TxDqDly_Margin_A1==98 ps 10
739 21:51:02.639899 TrainedVREFDQ_A0==74
740 21:51:02.640505 TrainedVREFDQ_A1==76
741 21:51:02.645332 VrefDac_Margin_A0==25
742 21:51:02.645911 DeviceVref_Margin_A0==40
743 21:51:02.646380 VrefDac_Margin_A1==25
744 21:51:02.651033 DeviceVref_Margin_A1==38
745 21:51:02.651615
746 21:51:02.652150
747 21:51:02.652659 channel==1
748 21:51:02.653156 RxClkDly_Margin_A0==98 ps 10
749 21:51:02.656594 TxDqDly_Margin_A0==98 ps 10
750 21:51:02.657173 RxClkDly_Margin_A1==98 ps 10
751 21:51:02.662157 TxDqDly_Margin_A1==88 ps 9
752 21:51:02.662729 TrainedVREFDQ_A0==77
753 21:51:02.663197 TrainedVREFDQ_A1==77
754 21:51:02.667884 VrefDac_Margin_A0==22
755 21:51:02.668502 DeviceVref_Margin_A0==37
756 21:51:02.673400 VrefDac_Margin_A1==24
757 21:51:02.673982 DeviceVref_Margin_A1==37
758 21:51:02.674489
759 21:51:02.678955 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 21:51:02.679528
761 21:51:02.706833 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 21:51:02.712451 2D training succeed
763 21:51:02.718055 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 21:51:02.718644 auto size-- 65535DDR cs0 size: 2048MB
765 21:51:02.723687 DDR cs1 size: 2048MB
766 21:51:02.724323 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 21:51:02.729276 cs0 DataBus test pass
768 21:51:02.729865 cs1 DataBus test pass
769 21:51:02.730374 cs0 AddrBus test pass
770 21:51:02.734863 cs1 AddrBus test pass
771 21:51:02.735486
772 21:51:02.736032 100bdlr_step_size ps== 420
773 21:51:02.736572 result report
774 21:51:02.740470 boot times 0Enable ddr reg access
775 21:51:02.748317 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 21:51:02.761711 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 21:51:03.335312 0.0;M3 CHK:0;cm4_sp_mode 0
778 21:51:03.335757 MVN_1=0x00000000
779 21:51:03.340803 MVN_2=0x00000000
780 21:51:03.346557 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 21:51:03.346875 OPS=0x10
782 21:51:03.347103 ring efuse init
783 21:51:03.347319 chipver efuse init
784 21:51:03.352222 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 21:51:03.357818 [0.018961 Inits done]
786 21:51:03.358305 secure task start!
787 21:51:03.358711 high task start!
788 21:51:03.362367 low task start!
789 21:51:03.362842 run into bl31
790 21:51:03.369082 NOTICE: BL31: v1.3(release):4fc40b1
791 21:51:03.376911 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 21:51:03.377408 NOTICE: BL31: G12A normal boot!
793 21:51:03.402189 NOTICE: BL31: BL33 decompress pass
794 21:51:03.407861 ERROR: Error initializing runtime service opteed_fast
795 21:51:04.640667
796 21:51:04.641095
797 21:51:04.649131 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 21:51:04.649504
799 21:51:04.649726 Model: Libre Computer AML-A311D-CC Alta
800 21:51:04.857607 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 21:51:04.880986 DRAM: 2 GiB (effective 3.8 GiB)
802 21:51:05.023972 Core: 408 devices, 31 uclasses, devicetree: separate
803 21:51:05.029813 WDT: Not starting watchdog@f0d0
804 21:51:05.062110 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 21:51:05.074495 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 21:51:05.079511 ** Bad device specification mmc 0 **
807 21:51:05.089838 Card did not respond to voltage select! : -110
808 21:51:05.097509 ** Bad device specification mmc 0 **
809 21:51:05.098015 Couldn't find partition mmc 0
810 21:51:05.105846 Card did not respond to voltage select! : -110
811 21:51:05.111351 ** Bad device specification mmc 0 **
812 21:51:05.111859 Couldn't find partition mmc 0
813 21:51:05.116409 Error: could not access storage.
814 21:51:05.458964 Net: eth0: ethernet@ff3f0000
815 21:51:05.459593 starting USB...
816 21:51:05.710775 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 21:51:05.711393 Starting the controller
818 21:51:05.717725 USB XHCI 1.10
819 21:51:07.877845 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 21:51:07.878475 bl2_stage_init 0x01
821 21:51:07.878909 bl2_stage_init 0x81
822 21:51:07.883380 hw id: 0x0000 - pwm id 0x01
823 21:51:07.883876 bl2_stage_init 0xc1
824 21:51:07.884349 bl2_stage_init 0x02
825 21:51:07.884766
826 21:51:07.888948 L0:00000000
827 21:51:07.889433 L1:20000703
828 21:51:07.889846 L2:00008067
829 21:51:07.890254 L3:14000000
830 21:51:07.891886 B2:00402000
831 21:51:07.892384 B1:e0f83180
832 21:51:07.892800
833 21:51:07.893204 TE: 58167
834 21:51:07.893613
835 21:51:07.903144 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 21:51:07.903464
837 21:51:07.903681 Board ID = 1
838 21:51:07.903890 Set A53 clk to 24M
839 21:51:07.904121 Set A73 clk to 24M
840 21:51:07.908891 Set clk81 to 24M
841 21:51:07.909193 A53 clk: 1200 MHz
842 21:51:07.909406 A73 clk: 1200 MHz
843 21:51:07.912190 CLK81: 166.6M
844 21:51:07.912464 smccc: 00012abe
845 21:51:07.917944 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 21:51:07.923471 board id: 1
847 21:51:07.928662 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 21:51:07.939026 fw parse done
849 21:51:07.945020 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 21:51:07.987600 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 21:51:07.998581 PIEI prepare done
852 21:51:07.999090 fastboot data load
853 21:51:07.999510 fastboot data verify
854 21:51:08.004168 verify result: 266
855 21:51:08.009860 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 21:51:08.010356 LPDDR4 probe
857 21:51:08.010771 ddr clk to 1584MHz
858 21:51:08.017784 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 21:51:08.055043
860 21:51:08.055567 dmc_version 0001
861 21:51:08.061730 Check phy result
862 21:51:08.067619 INFO : End of CA training
863 21:51:08.068123 INFO : End of initialization
864 21:51:08.073084 INFO : Training has run successfully!
865 21:51:08.073555 Check phy result
866 21:51:08.078873 INFO : End of initialization
867 21:51:08.079346 INFO : End of read enable training
868 21:51:08.082036 INFO : End of fine write leveling
869 21:51:08.087602 INFO : End of Write leveling coarse delay
870 21:51:08.093230 INFO : Training has run successfully!
871 21:51:08.093709 Check phy result
872 21:51:08.094126 INFO : End of initialization
873 21:51:08.098906 INFO : End of read dq deskew training
874 21:51:08.104430 INFO : End of MPR read delay center optimization
875 21:51:08.104905 INFO : End of write delay center optimization
876 21:51:08.110026 INFO : End of read delay center optimization
877 21:51:08.115618 INFO : End of max read latency training
878 21:51:08.116142 INFO : Training has run successfully!
879 21:51:08.121198 1D training succeed
880 21:51:08.127188 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 21:51:08.174852 Check phy result
882 21:51:08.175463 INFO : End of initialization
883 21:51:08.196335 INFO : End of 2D read delay Voltage center optimization
884 21:51:08.216446 INFO : End of 2D read delay Voltage center optimization
885 21:51:08.268452 INFO : End of 2D write delay Voltage center optimization
886 21:51:08.317568 INFO : End of 2D write delay Voltage center optimization
887 21:51:08.323181 INFO : Training has run successfully!
888 21:51:08.323714
889 21:51:08.324197 channel==0
890 21:51:08.329204 RxClkDly_Margin_A0==88 ps 9
891 21:51:08.329731 TxDqDly_Margin_A0==98 ps 10
892 21:51:08.332103 RxClkDly_Margin_A1==88 ps 9
893 21:51:08.332612 TxDqDly_Margin_A1==98 ps 10
894 21:51:08.337997 TrainedVREFDQ_A0==74
895 21:51:08.338522 TrainedVREFDQ_A1==74
896 21:51:08.343205 VrefDac_Margin_A0==25
897 21:51:08.343716 DeviceVref_Margin_A0==40
898 21:51:08.344192 VrefDac_Margin_A1==25
899 21:51:08.348934 DeviceVref_Margin_A1==40
900 21:51:08.349444
901 21:51:08.349840
902 21:51:08.350226 channel==1
903 21:51:08.350609 RxClkDly_Margin_A0==98 ps 10
904 21:51:08.352402 TxDqDly_Margin_A0==98 ps 10
905 21:51:08.357881 RxClkDly_Margin_A1==88 ps 9
906 21:51:08.358367 TxDqDly_Margin_A1==88 ps 9
907 21:51:08.358781 TrainedVREFDQ_A0==77
908 21:51:08.363419 TrainedVREFDQ_A1==77
909 21:51:08.363897 VrefDac_Margin_A0==22
910 21:51:08.369070 DeviceVref_Margin_A0==37
911 21:51:08.369672 VrefDac_Margin_A1==24
912 21:51:08.370146 DeviceVref_Margin_A1==37
913 21:51:08.370575
914 21:51:08.377870 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 21:51:08.378385
916 21:51:08.405966 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 21:51:08.406546 2D training succeed
918 21:51:08.417116 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 21:51:08.417612 auto size-- 65535DDR cs0 size: 2048MB
920 21:51:08.418003 DDR cs1 size: 2048MB
921 21:51:08.422876 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 21:51:08.423349 cs0 DataBus test pass
923 21:51:08.428334 cs1 DataBus test pass
924 21:51:08.428811 cs0 AddrBus test pass
925 21:51:08.433948 cs1 AddrBus test pass
926 21:51:08.434417
927 21:51:08.434834 100bdlr_step_size ps== 420
928 21:51:08.435239 result report
929 21:51:08.439618 boot times 0Enable ddr reg access
930 21:51:08.446099 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 21:51:08.459484 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 21:51:09.031585 0.0;M3 CHK:0;cm4_sp_mode 0
933 21:51:09.032248 MVN_1=0x00000000
934 21:51:09.037086 MVN_2=0x00000000
935 21:51:09.042854 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 21:51:09.043342 OPS=0x10
937 21:51:09.043757 ring efuse init
938 21:51:09.044198 chipver efuse init
939 21:51:09.051031 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 21:51:09.051525 [0.018961 Inits done]
941 21:51:09.051941 secure task start!
942 21:51:09.058588 high task start!
943 21:51:09.059060 low task start!
944 21:51:09.059474 run into bl31
945 21:51:09.065286 NOTICE: BL31: v1.3(release):4fc40b1
946 21:51:09.073064 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 21:51:09.073540 NOTICE: BL31: G12A normal boot!
948 21:51:09.098484 NOTICE: BL31: BL33 decompress pass
949 21:51:09.104176 ERROR: Error initializing runtime service opteed_fast
950 21:51:10.336997
951 21:51:10.337403
952 21:51:10.345469 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 21:51:10.345911
954 21:51:10.346243 Model: Libre Computer AML-A311D-CC Alta
955 21:51:10.554079 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 21:51:10.577313 DRAM: 2 GiB (effective 3.8 GiB)
957 21:51:10.720357 Core: 408 devices, 31 uclasses, devicetree: separate
958 21:51:10.726231 WDT: Not starting watchdog@f0d0
959 21:51:10.758398 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 21:51:10.771017 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 21:51:10.775850 ** Bad device specification mmc 0 **
962 21:51:10.786263 Card did not respond to voltage select! : -110
963 21:51:10.795031 ** Bad device specification mmc 0 **
964 21:51:10.804895 Couldn't find partition mmc 0
965 21:51:10.814548 Card did not respond to voltage select! : -110
966 21:51:10.823413 ** Bad device specification mmc 0 **
967 21:51:10.831361 Couldn't find partition mmc 0
968 21:51:10.831750 Error: could not access storage.
969 21:51:11.156458 Net: eth0: ethernet@ff3f0000
970 21:51:11.156865 starting USB...
971 21:51:11.408385 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 21:51:11.408995 Starting the controller
973 21:51:11.415164 USB XHCI 1.10
974 21:51:12.968888 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 21:51:12.977328 scanning usb for storage devices... 0 Storage Device(s) found
977 21:51:13.028464 Hit any key to stop autoboot: 1
978 21:51:13.029283 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
979 21:51:13.029729 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
980 21:51:13.030200 Setting prompt string to ['=>']
981 21:51:13.030568 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
982 21:51:13.044760 0
983 21:51:13.045743 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 21:51:13.046295 Sending with 10 millisecond of delay
986 21:51:14.181864 => setenv autoload no
987 21:51:14.192683 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
988 21:51:14.197468 setenv autoload no
989 21:51:14.198215 Sending with 10 millisecond of delay
991 21:51:15.997293 => setenv initrd_high 0xffffffff
992 21:51:16.007911 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
993 21:51:16.009024 setenv initrd_high 0xffffffff
994 21:51:16.009790 Sending with 10 millisecond of delay
996 21:51:17.626740 => setenv fdt_high 0xffffffff
997 21:51:17.637567 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
998 21:51:17.638436 setenv fdt_high 0xffffffff
999 21:51:17.639198 Sending with 10 millisecond of delay
1001 21:51:17.931140 => dhcp
1002 21:51:17.941715 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1003 21:51:17.942272 dhcp
1004 21:51:17.942522 Speed: 1000, full duplex
1005 21:51:17.942737 BOOTP broadcast 1
1006 21:51:18.189561 BOOTP broadcast 2
1007 21:51:18.334158 DHCP client bound to address 192.168.6.33 (392 ms)
1008 21:51:18.334782 Sending with 10 millisecond of delay
1010 21:51:20.010998 => setenv serverip 192.168.6.2
1011 21:51:20.021599 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1012 21:51:20.022158 setenv serverip 192.168.6.2
1013 21:51:20.022619 Sending with 10 millisecond of delay
1015 21:51:23.749060 => tftpboot 0x01080000 680279/tftp-deploy-1zi1cn26/kernel/uImage
1016 21:51:23.760091 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1017 21:51:23.761197 tftpboot 0x01080000 680279/tftp-deploy-1zi1cn26/kernel/uImage
1018 21:51:23.761776 Speed: 1000, full duplex
1019 21:51:23.762330 Using ethernet@ff3f0000 device
1020 21:51:23.763014 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1021 21:51:23.768384 Filename '680279/tftp-deploy-1zi1cn26/kernel/uImage'.
1022 21:51:23.772235 Load address: 0x1080000
1023 21:51:26.650616 Loading: *################################################## 43.2 MiB
1024 21:51:26.651411 15 MiB/s
1025 21:51:26.651974 done
1026 21:51:26.654737 Bytes transferred = 45308480 (2b35a40 hex)
1027 21:51:26.655276 Sending with 10 millisecond of delay
1029 21:51:31.344464 => tftpboot 0x08000000 680279/tftp-deploy-1zi1cn26/ramdisk/ramdisk.cpio.gz.uboot
1030 21:51:31.355238 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1031 21:51:31.356136 tftpboot 0x08000000 680279/tftp-deploy-1zi1cn26/ramdisk/ramdisk.cpio.gz.uboot
1032 21:51:31.356597 Speed: 1000, full duplex
1033 21:51:31.357002 Using ethernet@ff3f0000 device
1034 21:51:31.359194 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1035 21:51:31.370999 Filename '680279/tftp-deploy-1zi1cn26/ramdisk/ramdisk.cpio.gz.uboot'.
1036 21:51:31.371535 Load address: 0x8000000
1037 21:51:37.934230 Loading: *#####################T ############################# 22.2 MiB
1038 21:51:37.934645 3.4 MiB/s
1039 21:51:37.934865 done
1040 21:51:37.937807 Bytes transferred = 23247326 (162b9de hex)
1041 21:51:37.938329 Sending with 10 millisecond of delay
1043 21:51:43.110851 => tftpboot 0x01070000 680279/tftp-deploy-1zi1cn26/dtb/meson-g12b-a311d-libretech-cc.dtb
1044 21:51:43.121619 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
1045 21:51:43.122433 tftpboot 0x01070000 680279/tftp-deploy-1zi1cn26/dtb/meson-g12b-a311d-libretech-cc.dtb
1046 21:51:43.122873 Speed: 1000, full duplex
1047 21:51:43.123272 Using ethernet@ff3f0000 device
1048 21:51:43.126787 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1049 21:51:43.134166 Filename '680279/tftp-deploy-1zi1cn26/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1050 21:51:43.144298 Load address: 0x1070000
1051 21:51:43.156033 Loading: *################################################## 53.4 KiB
1052 21:51:43.156511 3.1 MiB/s
1053 21:51:43.156909 done
1054 21:51:43.160645 Bytes transferred = 54667 (d58b hex)
1055 21:51:43.161360 Sending with 10 millisecond of delay
1057 21:51:56.476726 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/680279/extract-nfsrootfs-n8mi20uc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1058 21:51:56.487302 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:45)
1059 21:51:56.487917 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/680279/extract-nfsrootfs-n8mi20uc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1060 21:51:56.488406 Sending with 10 millisecond of delay
1062 21:51:58.833926 => bootm 0x01080000 0x08000000 0x01070000
1063 21:51:58.844475 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1064 21:51:58.844751 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
1065 21:51:58.845302 bootm 0x01080000 0x08000000 0x01070000
1066 21:51:58.845544 ## Booting kernel from Legacy Image at 01080000 ...
1067 21:51:58.849327 Image Name:
1068 21:51:58.854955 Image Type: AArch64 Linux Kernel Image (uncompressed)
1069 21:51:58.855334 Data Size: 45308416 Bytes = 43.2 MiB
1070 21:51:58.860546 Load Address: 01080000
1071 21:51:58.861153 Entry Point: 01080000
1072 21:51:59.054117 Verifying Checksum ... OK
1073 21:51:59.054528 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1074 21:51:59.059364 Image Name:
1075 21:51:59.064935 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1076 21:51:59.065298 Data Size: 23247262 Bytes = 22.2 MiB
1077 21:51:59.071501 Load Address: 00000000
1078 21:51:59.071854 Entry Point: 00000000
1079 21:51:59.172076 Verifying Checksum ... OK
1080 21:51:59.172699 ## Flattened Device Tree blob at 01070000
1081 21:51:59.177283 Booting using the fdt blob at 0x1070000
1082 21:51:59.177773 Working FDT set to 1070000
1083 21:51:59.181833 Loading Kernel Image
1084 21:51:59.332112 Loading Ramdisk to 7e9d4000, end 7ffff99e ... OK
1085 21:51:59.340320 Loading Device Tree to 000000007e9c3000, end 000000007e9d358a ... OK
1086 21:51:59.340742 Working FDT set to 7e9c3000
1087 21:51:59.340958
1088 21:51:59.341655 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1089 21:51:59.342225 start: 2.4.4 auto-login-action (timeout 00:03:42) [common]
1090 21:51:59.342710 Setting prompt string to ['Linux version [0-9]']
1091 21:51:59.343212 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1092 21:51:59.343561 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1093 21:51:59.344476 Starting kernel ...
1094 21:51:59.344830
1095 21:51:59.380223 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1096 21:51:59.381239 start: 2.4.4.1 login-action (timeout 00:03:42) [common]
1097 21:51:59.381768 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1098 21:51:59.382135 Setting prompt string to []
1099 21:51:59.382501 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1100 21:51:59.382846 Using line separator: #'\n'#
1101 21:51:59.383171 No login prompt set.
1102 21:51:59.383460 Parsing kernel messages
1103 21:51:59.383695 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1104 21:51:59.384210 [login-action] Waiting for messages, (timeout 00:03:42)
1105 21:51:59.384726 Waiting using forced prompt support (timeout 00:01:51)
1106 21:51:59.399938 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j302637-arm64-gcc-12-defconfig-grnjw) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Fri Aug 30 21:13:35 UTC 2024
1107 21:51:59.400329 [ 0.000000] KASLR disabled due to lack of seed
1108 21:51:59.405585 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1109 21:51:59.411029 [ 0.000000] efi: UEFI not found.
1110 21:51:59.416544 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1111 21:51:59.427519 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1112 21:51:59.433114 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1113 21:51:59.444234 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1114 21:51:59.455273 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1115 21:51:59.466304 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1116 21:51:59.471948 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1117 21:51:59.477399 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1118 21:51:59.482973 [ 0.000000] NUMA: No NUMA configuration found
1119 21:51:59.488458 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1120 21:51:59.493965 [ 0.000000] NUMA: NODE_DATA [mem 0xe46669c0-0xe4668fff]
1121 21:51:59.494457 [ 0.000000] Zone ranges:
1122 21:51:59.499421 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1123 21:51:59.504933 [ 0.000000] DMA32 empty
1124 21:51:59.505421 [ 0.000000] Normal empty
1125 21:51:59.510463 [ 0.000000] Movable zone start for each node
1126 21:51:59.516031 [ 0.000000] Early memory node ranges
1127 21:51:59.521528 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1128 21:51:59.527019 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1129 21:51:59.532546 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1130 21:51:59.541218 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1131 21:51:59.565599 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1132 21:51:59.571134 [ 0.000000] psci: probing for conduit method from DT.
1133 21:51:59.571599 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1134 21:51:59.580047 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1135 21:51:59.585672 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1136 21:51:59.586165 [ 0.000000] psci: SMC Calling Convention v1.1
1137 21:51:59.591153 [ 0.000000] percpu: Embedded 24 pages/cpu s60056 r8192 d30056 u98304
1138 21:51:59.596678 [ 0.000000] Detected VIPT I-cache on CPU0
1139 21:51:59.602194 [ 0.000000] CPU features: detected: ARM erratum 845719
1140 21:51:59.607703 [ 0.000000] alternatives: applying boot alternatives
1141 21:51:59.629864 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/680279/extract-nfsrootfs-n8mi20uc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1142 21:51:59.635304 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1143 21:51:59.646267 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1144 21:51:59.646768 <6>[ 0.000000] Fallback order for Node 0: 0
1145 21:51:59.657344 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1146 21:51:59.657845 <6>[ 0.000000] Policy zone: DMA
1147 21:51:59.662898 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1148 21:51:59.673874 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1149 21:51:59.674385 <6>[ 0.000000] software IO TLB: area num 8.
1150 21:51:59.684942 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1151 21:51:59.731363 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1152 21:51:59.736971 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1153 21:51:59.742422 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1154 21:51:59.748018 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1155 21:51:59.753470 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1156 21:51:59.759024 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1157 21:51:59.764594 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1158 21:51:59.770060 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1159 21:51:59.781015 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
1160 21:51:59.786704 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
1161 21:51:59.792137 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1162 21:51:59.797668 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1163 21:51:59.803198 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1164 21:51:59.809822 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1165 21:51:59.821912 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1166 21:51:59.832916 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1167 21:51:59.838542 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1168 21:51:59.844084 <6>[ 0.008765] Console: colour dummy device 80x25
1169 21:51:59.855026 <6>[ 0.012941] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1170 21:51:59.860606 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1171 21:51:59.866131 <6>[ 0.028187] LSM: initializing lsm=capability
1172 21:51:59.871729 <6>[ 0.032702] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1173 21:51:59.877171 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1174 21:51:59.882714 <6>[ 0.050742] rcu: Hierarchical SRCU implementation.
1175 21:51:59.888219 <6>[ 0.053250] rcu: Max phase no-delay instances is 1000.
1176 21:51:59.899213 <6>[ 0.058852] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1177 21:51:59.904758 <6>[ 0.071448] EFI services will not be available.
1178 21:51:59.905268 <6>[ 0.072085] smp: Bringing up secondary CPUs ...
1179 21:51:59.910229 <6>[ 0.077146] Detected VIPT I-cache on CPU1
1180 21:51:59.915711 <6>[ 0.077265] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1181 21:51:59.921184 <6>[ 0.078571] CPU features: detected: Spectre-v2
1182 21:51:59.926778 <6>[ 0.078586] CPU features: detected: Spectre-v4
1183 21:51:59.932219 <6>[ 0.078591] CPU features: detected: Spectre-BHB
1184 21:51:59.937842 <6>[ 0.078596] CPU features: detected: ARM erratum 858921
1185 21:51:59.943286 <6>[ 0.078603] Detected VIPT I-cache on CPU2
1186 21:51:59.948833 <6>[ 0.078677] arch_timer: Enabling local workaround for ARM erratum 858921
1187 21:51:59.954342 <6>[ 0.078695] arch_timer: CPU2: Trapping CNTVCT access
1188 21:51:59.959819 <6>[ 0.078705] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1189 21:51:59.965330 <6>[ 0.079437] Detected VIPT I-cache on CPU3
1190 21:51:59.970961 <6>[ 0.079483] arch_timer: Enabling local workaround for ARM erratum 858921
1191 21:51:59.976388 <6>[ 0.079492] arch_timer: CPU3: Trapping CNTVCT access
1192 21:51:59.981851 <6>[ 0.079499] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1193 21:51:59.987384 <6>[ 0.080175] Detected VIPT I-cache on CPU4
1194 21:51:59.992930 <6>[ 0.080222] arch_timer: Enabling local workaround for ARM erratum 858921
1195 21:51:59.998405 <6>[ 0.080231] arch_timer: CPU4: Trapping CNTVCT access
1196 21:52:00.004023 <6>[ 0.080238] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1197 21:52:00.009596 <6>[ 0.080987] Detected VIPT I-cache on CPU5
1198 21:52:00.015034 <6>[ 0.081035] arch_timer: Enabling local workaround for ARM erratum 858921
1199 21:52:00.020593 <6>[ 0.081044] arch_timer: CPU5: Trapping CNTVCT access
1200 21:52:00.031622 <6>[ 0.081051] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1201 21:52:00.031976 <6>[ 0.081161] smp: Brought up 1 node, 6 CPUs
1202 21:52:00.037118 <6>[ 0.203225] SMP: Total of 6 processors activated.
1203 21:52:00.042674 <6>[ 0.208130] CPU: All CPU(s) started at EL2
1204 21:52:00.048208 <6>[ 0.212471] CPU features: detected: 32-bit EL0 Support
1205 21:52:00.053712 <6>[ 0.217787] CPU features: detected: 32-bit EL1 Support
1206 21:52:00.059223 <6>[ 0.223148] CPU features: detected: CRC32 instructions
1207 21:52:00.065009 <6>[ 0.228542] alternatives: applying system-wide alternatives
1208 21:52:00.082727 <6>[ 0.235667] Memory: 3558024K/4012396K available (17152K kernel code, 5014K rwdata, 11660K rodata, 10240K init, 733K bss, 187144K reserved, 262144K cma-reserved)
1209 21:52:00.083274 <6>[ 0.250067] devtmpfs: initialized
1210 21:52:00.093707 <6>[ 0.259187] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1211 21:52:00.099291 <6>[ 0.263546] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1212 21:52:00.104807 <6>[ 0.274335] 21504 pages in range for non-PLT usage
1213 21:52:00.110349 <6>[ 0.274345] 513024 pages in range for PLT usage
1214 21:52:00.116009 <6>[ 0.275905] pinctrl core: initialized pinctrl subsystem
1215 21:52:00.121374 <6>[ 0.287910] DMI not present or invalid.
1216 21:52:00.126998 <6>[ 0.291977] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1217 21:52:00.132428 <6>[ 0.297000] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1218 21:52:00.143381 <6>[ 0.303824] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1219 21:52:00.148972 <6>[ 0.311920] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1220 21:52:00.154512 <6>[ 0.319375] audit: initializing netlink subsys (disabled)
1221 21:52:00.165472 <5>[ 0.325122] audit: type=2000 audit(0.244:1): state=initialized audit_enabled=0 res=1
1222 21:52:00.171029 <6>[ 0.326483] thermal_sys: Registered thermal governor 'step_wise'
1223 21:52:00.176553 <6>[ 0.332884] thermal_sys: Registered thermal governor 'power_allocator'
1224 21:52:00.182142 <6>[ 0.339138] cpuidle: using governor menu
1225 21:52:00.187633 <6>[ 0.350122] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1226 21:52:00.193139 <6>[ 0.357047] ASID allocator initialised with 65536 entries
1227 21:52:00.201366 <6>[ 0.364440] Serial: AMBA PL011 UART driver
1228 21:52:00.209069 <6>[ 0.375135] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1229 21:52:00.223572 <6>[ 0.389991] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1230 21:52:00.232691 <6>[ 0.392650] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1231 21:52:00.238108 <6>[ 0.405560] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1232 21:52:00.249130 <6>[ 0.409027] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1233 21:52:00.254735 <6>[ 0.417423] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1234 21:52:00.265759 <6>[ 0.425077] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1235 21:52:00.271295 <6>[ 0.438442] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1236 21:52:00.276763 <6>[ 0.440898] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1237 21:52:00.288041 <6>[ 0.447378] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1238 21:52:00.293303 <6>[ 0.454356] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1239 21:52:00.298875 <6>[ 0.460825] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1240 21:52:00.304304 <6>[ 0.467810] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1241 21:52:00.309909 <6>[ 0.474280] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1242 21:52:00.320877 <6>[ 0.481265] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1243 21:52:00.321247 <6>[ 0.489159] ACPI: Interpreter disabled.
1244 21:52:00.326398 <6>[ 0.494515] iommu: Default domain type: Translated
1245 21:52:00.331947 <6>[ 0.496802] iommu: DMA domain TLB invalidation policy: strict mode
1246 21:52:00.337435 <5>[ 0.503490] SCSI subsystem initialized
1247 21:52:00.342964 <6>[ 0.507408] usbcore: registered new interface driver usbfs
1248 21:52:00.348482 <6>[ 0.512860] usbcore: registered new interface driver hub
1249 21:52:00.354037 <6>[ 0.518383] usbcore: registered new device driver usb
1250 21:52:00.359532 <6>[ 0.524572] pps_core: LinuxPPS API ver. 1 registered
1251 21:52:00.370950 <6>[ 0.528792] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1252 21:52:00.371690 <6>[ 0.538112] PTP clock support registered
1253 21:52:00.376270 <6>[ 0.542406] EDAC MC: Ver: 3.0.0
1254 21:52:00.381762 <6>[ 0.545997] scmi_core: SCMI protocol bus registered
1255 21:52:00.387297 <6>[ 0.551557] FPGA manager framework
1256 21:52:00.392793 <6>[ 0.554372] Advanced Linux Sound Architecture Driver Initialized.
1257 21:52:00.393367 <6>[ 0.561308] vgaarb: loaded
1258 21:52:00.398276 <6>[ 0.563846] clocksource: Switched to clocksource arch_sys_counter
1259 21:52:00.403811 <5>[ 0.570012] VFS: Disk quotas dquot_6.6.0
1260 21:52:00.409326 <6>[ 0.574003] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1261 21:52:00.414847 <6>[ 0.581418] pnp: PnP ACPI: disabled
1262 21:52:00.420351 <6>[ 0.589369] NET: Registered PF_INET protocol family
1263 21:52:00.426009 <6>[ 0.590039] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1264 21:52:00.437029 <6>[ 0.600201] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1265 21:52:00.442379 <6>[ 0.606208] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1266 21:52:00.453715 <6>[ 0.614103] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1267 21:52:00.459808 <6>[ 0.622343] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1268 21:52:00.470093 <6>[ 0.630139] TCP: Hash tables configured (established 32768 bind 32768)
1269 21:52:00.475720 <6>[ 0.636618] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1270 21:52:00.481250 <6>[ 0.643463] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1271 21:52:00.488183 <6>[ 0.650884] NET: Registered PF_UNIX/PF_LOCAL protocol family
1272 21:52:00.492161 <6>[ 0.656974] RPC: Registered named UNIX socket transport module.
1273 21:52:00.497646 <6>[ 0.662750] RPC: Registered udp transport module.
1274 21:52:00.503176 <6>[ 0.667655] RPC: Registered tcp transport module.
1275 21:52:00.508757 <6>[ 0.672570] RPC: Registered tcp-with-tls transport module.
1276 21:52:00.514104 <6>[ 0.678263] RPC: Registered tcp NFSv4.1 backchannel transport module.
1277 21:52:00.519605 <6>[ 0.684912] PCI: CLS 0 bytes, default 64
1278 21:52:00.525211 <6>[ 0.689232] Unpacking initramfs...
1279 21:52:00.530654 <6>[ 0.695387] kvm [1]: nv: 529 coarse grained trap handlers
1280 21:52:00.536125 <6>[ 0.698555] kvm [1]: IPA Size Limit: 40 bits
1281 21:52:00.536705 <6>[ 0.704187] kvm [1]: vgic interrupt IRQ9
1282 21:52:00.541630 <6>[ 0.706924] kvm [1]: Hyp nVHE mode initialized successfully
1283 21:52:00.547120 <5>[ 0.713933] Initialise system trusted keyrings
1284 21:52:00.552667 <6>[ 0.717566] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1285 21:52:00.558234 <6>[ 0.724264] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1286 21:52:00.563737 <5>[ 0.730288] NFS: Registering the id_resolver key type
1287 21:52:00.569320 <5>[ 0.735299] Key type id_resolver registered
1288 21:52:00.574916 <5>[ 0.739676] Key type id_legacy registered
1289 21:52:00.580389 <6>[ 0.743913] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1290 21:52:00.591378 <6>[ 0.750800] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1291 21:52:00.595216 <6>[ 0.758595] 9p: Installing v9fs 9p2000 file system support
1292 21:52:00.633465 <5>[ 0.805304] Key type asymmetric registered
1293 21:52:00.638966 <5>[ 0.805339] Asymmetric key parser 'x509' registered
1294 21:52:00.649950 <6>[ 0.809200] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1295 21:52:00.650526 <6>[ 0.816726] io scheduler mq-deadline registered
1296 21:52:00.655393 <6>[ 0.821468] io scheduler kyber registered
1297 21:52:00.660949 <6>[ 0.825741] io scheduler bfq registered
1298 21:52:00.667358 <6>[ 0.833536] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1299 21:52:00.713142 <6>[ 0.880147] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1300 21:52:00.732180 <6>[ 0.892983] Serial: 8250/16550 driver, 4 por�<6>[ 0.897463] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1301 21:52:00.737716 <6>[ 0.907087] printk: legacy console [ttyAML0] enabled
1302 21:52:00.743225 <6>[ 0.907087] printk: legacy console [ttyAML0] enabled
1303 21:52:00.748765 <6>[ 0.911887] printk: legacy bootconsole [meson0] disabled
1304 21:52:00.754317 <6>[ 0.911887] printk: legacy bootconsole [meson0] disabled
1305 21:52:00.759939 <6>[ 0.924618] msm_serial: driver initialized
1306 21:52:00.765432 <6>[ 0.927803] SuperH (H)SCI(F) driver initialized
1307 21:52:00.765990 <6>[ 0.932335] STM32 USART driver initialized
1308 21:52:00.770969 <5>[ 0.938429] random: crng init done
1309 21:52:00.777759 <6>[ 0.943831] loop: module loaded
1310 21:52:00.778296 <6>[ 0.945110] megasas: 07.727.03.00-rc1
1311 21:52:00.783296 <6>[ 0.954184] tun: Universal TUN/TAP device driver, 1.6
1312 21:52:00.788997 <6>[ 0.955370] thunder_xcv, ver 1.0
1313 21:52:00.789565 <6>[ 0.957369] thunder_bgx, ver 1.0
1314 21:52:00.794499 <6>[ 0.960815] nicpf, ver 1.0
1315 21:52:00.800086 <6>[ 0.965286] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1316 21:52:00.805750 <6>[ 0.971205] hns3: Copyright (c) 2017 Huawei Corporation.
1317 21:52:00.811256 <6>[ 0.976793] hclge is initializing
1318 21:52:00.816724 <6>[ 0.980331] e1000: Intel(R) PRO/1000 Network Driver
1319 21:52:00.822286 <6>[ 0.985412] e1000: Copyright (c) 1999-2006 Intel Corporation.
1320 21:52:00.827801 <6>[ 0.991431] e1000e: Intel(R) PRO/1000 Network Driver
1321 21:52:00.833362 <6>[ 0.996593] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1322 21:52:00.838910 <6>[ 1.002780] igb: Intel(R) Gigabit Ethernet Network Driver
1323 21:52:00.844483 <6>[ 1.008378] igb: Copyright (c) 2007-2014 Intel Corporation.
1324 21:52:00.850089 <6>[ 1.014214] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1325 21:52:00.855542 <6>[ 1.020685] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1326 21:52:00.861132 <6>[ 1.027423] sky2: driver version 1.30
1327 21:52:00.866649 <6>[ 1.032351] VFIO - User Level meta-driver version: 0.3
1328 21:52:00.872230 <6>[ 1.039799] usbcore: registered new interface driver usb-storage
1329 21:52:00.878155 <6>[ 1.046111] i2c_dev: i2c /dev entries driver
1330 21:52:00.890514 <6>[ 1.056880] sdhci: Secure Digital Host Controller Interface driver
1331 21:52:00.891040 <6>[ 1.057677] sdhci: Copyright(c) Pierre Ossman
1332 21:52:00.901614 <6>[ 1.063408] Synopsys Designware Multimedia Card Interface Driver
1333 21:52:00.907228 <6>[ 1.069900] sdhci-pltfm: SDHCI platform and OF driver helper
1334 21:52:00.912728 <6>[ 1.077497] ledtrig-cpu: registered to indicate activity on CPUs
1335 21:52:00.918287 <6>[ 1.081485] meson-sm: secure-monitor enabled
1336 21:52:00.926321 <6>[ 1.086429] usbcore: registered new interface driver usbhid
1337 21:52:00.926822 <6>[ 1.090980] usbhid: USB HID core driver
1338 21:52:00.933452 <6>[ 1.105294] NET: Registered PF_PACKET protocol family
1339 21:52:00.939100 <6>[ 1.105387] 9pnet: Installing 9P2000 support
1340 21:52:00.945901 <5>[ 1.109549] Key type dns_resolver registered
1341 21:52:00.948088 <6>[ 1.120954] registered taskstats version 1
1342 21:52:00.953639 <5>[ 1.121121] Loading compiled-in X.509 certificates
1343 21:52:00.960698 <6>[ 1.129934] Demotion targets for Node 0: null
1344 21:52:00.996818 <6>[ 1.168585] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1345 21:52:01.002272 <6>[ 1.168629] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1346 21:52:01.013330 <4>[ 1.178745] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1347 21:52:01.018910 <4>[ 1.181411] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1348 21:52:01.024464 <6>[ 1.188941] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1349 21:52:01.030085 <6>[ 1.199608] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1350 21:52:01.041073 <6>[ 1.201733] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1351 21:52:01.052180 <6>[ 1.209684] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1352 21:52:01.057761 <6>[ 1.219222] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1353 21:52:01.063275 <6>[ 1.225417] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1354 21:52:01.068861 <6>[ 1.231029] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1355 21:52:01.074359 <6>[ 1.238915] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1356 21:52:01.079927 <6>[ 1.246210] hub 1-0:1.0: USB hub found
1357 21:52:01.085500 <6>[ 1.249677] hub 1-0:1.0: 2 ports detected
1358 21:52:01.091116 <6>[ 1.255675] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1359 21:52:01.096549 <6>[ 1.262629] hub 2-0:1.0: USB hub found
1360 21:52:01.101614 <6>[ 1.266225] hub 2-0:1.0: 1 port detected
1361 21:52:01.126609 <6>[ 1.295896] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1362 21:52:01.141643 <6>[ 1.310212] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1363 21:52:01.179163 <6>[ 1.347430] Trying to probe devices needed for running init ...
1364 21:52:01.340293 <6>[ 1.507876] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1365 21:52:01.484729 <6>[ 1.651127] mmc0: new ultra high speed SDR104 SDXC card at address e624
1366 21:52:01.490271 <6>[ 1.653009] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1367 21:52:01.490617 <6>[ 1.657850] Freeing initrd memory: 22700K
1368 21:52:01.494340 <6>[ 1.658605] mmcblk0: p1
1369 21:52:01.522222 <6>[ 1.693989] hub 1-1:1.0: USB hub found
1370 21:52:01.527804 <6>[ 1.694321] hub 1-1:1.0: 4 ports detected
1371 21:52:01.616230 <6>[ 1.783981] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1372 21:52:01.666676 <6>[ 1.838617] hub 2-1:1.0: USB hub found
1373 21:52:01.672394 <6>[ 1.839454] hub 2-1:1.0: 4 ports detected
1374 21:52:13.476294 <6>[ 13.647909] clk: Disabling unused clocks
1375 21:52:13.481801 <6>[ 13.648073] PM: genpd: Disabling unused power domains
1376 21:52:13.490040 <6>[ 13.651762] ALSA device list:
1377 21:52:13.490341 <6>[ 13.654966] No soundcards found.
1378 21:52:13.495566 <6>[ 13.667161] Freeing unused kernel memory: 10240K
1379 21:52:13.501609 <6>[ 13.667245] Run /init as init process
1380 21:52:13.507575 Loading, please wait...
1381 21:52:13.538967 Starting systemd-udevd version 252.22-1~deb12u1
1382 21:52:14.015496 <6>[ 14.184337] mc: Linux media interface: v0.10
1383 21:52:14.023259 <6>[ 14.191663] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1384 21:52:14.038661 <6>[ 14.204900] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1385 21:52:14.044147 <4>[ 14.205332] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1386 21:52:14.049668 <6>[ 14.206155] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1387 21:52:14.055184 <6>[ 14.216827] videodev: Linux video capture interface: v2.00
1388 21:52:14.066330 <6>[ 14.221134] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1389 21:52:14.071819 <6>[ 14.233090] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1390 21:52:14.077429 <6>[ 14.233118] usbcore: registered new device driver onboard-usb-dev
1391 21:52:14.083030 <6>[ 14.245558] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1392 21:52:14.088511 <6>[ 14.252899] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1393 21:52:14.099791 <6>[ 14.258345] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1394 21:52:14.105085 <6>[ 14.258747] panfrost ffe40000.gpu: clock rate = 24000000
1395 21:52:14.110657 <6>[ 14.266053] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1396 21:52:14.116317 <6>[ 14.266068] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1397 21:52:14.122064 <3>[ 14.266941] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1398 21:52:14.133033 <3>[ 14.272118] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1399 21:52:14.138575 <6>[ 14.279328] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1400 21:52:14.149705 <6>[ 14.288565] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1401 21:52:14.155118 <6>[ 14.293522] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1402 21:52:14.160757 <6>[ 14.301699] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1403 21:52:14.166185 <6>[ 14.312710] meson-vrtc ff8000a8.rtc: registered as rtc0
1404 21:52:14.182885 <6>[ 14.316948] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1405 21:52:14.188276 <6>[ 14.321326] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1406 21:52:14.193877 <6>[ 14.321338] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1407 21:52:14.199412 <6>[ 14.321344] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1408 21:52:14.210424 <6>[ 14.323626] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1409 21:52:14.215964 <6>[ 14.326417] Registered IR keymap rc-empty
1410 21:52:14.221625 <6>[ 14.326562] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1411 21:52:14.232650 <6>[ 14.326704] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1412 21:52:14.238218 <6>[ 14.331994] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1413 21:52:14.238775 <6>[ 14.350244] rc rc0: sw decoder init
1414 21:52:14.249458 <6>[ 14.401224] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1415 21:52:14.256080 <6>[ 14.406085] meson-ir ff808000.ir: receiver initialized
1416 21:52:14.260433 <6>[ 14.420153] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1417 21:52:14.271483 <4>[ 14.434137] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1418 21:52:14.283046 <6>[ 14.438072] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1419 21:52:14.288230 <6>[ 14.451273] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1420 21:52:14.299229 <3>[ 14.459328] meson-drm ff900000.vpu: DSI transceiver device is disabled
1421 21:52:14.302665 <4>[ 14.467891] rc rc0: two consecutive events of type space
1422 21:52:14.315160 <6>[ 14.481574] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1423 21:52:14.320305 <6>[ 14.482677] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1424 21:52:14.517221 <6>[ 14.664630] Console: switching to colour frame buffer device 128x48
1425 21:52:14.523130 <6>[ 14.684498] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1426 21:52:14.640570 <6>[ 14.804125] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1427 21:52:14.738125 <6>[ 14.910018] hub 1-1:1.0: USB hub found
1428 21:52:14.743689 <6>[ 14.910341] hub 1-1:1.0: 4 ports detected
1429 21:52:14.750075 <6>[ 14.915727] onboard-usb-dev 1-1: USB disconnect, device number 2
1430 21:52:14.877088 Begin: Loading essential drivers ... done.
1431 21:52:14.882573 Begin: Running /scripts/init-premount ... done.
1432 21:52:14.888370 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1433 21:52:14.899292 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1434 21:52:14.899669 Device /sys/class/net/end0 found
1435 21:52:14.899879 done.
1436 21:52:14.909242 Begin: Waiting up to 180 secs for any network device to become available ... done.
1437 21:52:14.954392 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1438 21:52:14.959988 <6>[ 15.123666] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1439 21:52:15.056241 <6>[ 15.219953] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1440 21:52:15.071621 <6>[ 15.237976] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1441 21:52:15.077212 <6>[ 15.240214] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1442 21:52:15.086468 <6>[ 15.247686] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1443 21:52:15.145277 <6>[ 15.312911] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1444 21:52:15.346256 <6>[ 15.518096] hub 1-1:1.0: USB hub found
1445 21:52:15.352056 <6>[ 15.518412] hub 1-1:1.0: 4 ports detected
1446 21:52:15.558545 <6>[ 15.725947] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1447 21:52:15.830503 <6>[ 15.997946] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1448 21:52:16.653517 IP-Config: no response after 2 secs - giving up
1449 21:52:16.699160 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1450 21:52:18.048378 <6>[ 18.214155] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1451 21:52:19.901258 IP-Config: no response after 3 secs - giving up
1452 21:52:19.948230 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1453 21:52:23.066189 IP-Config: end0 guessed broadcast address 192.168.6.255
1454 21:52:23.071340 IP-Config: end0 complete (dhcp from 192.168.6.1):
1455 21:52:23.076845 address: 192.168.6.33 broadcast: 192.168.6.255 netmask: 255.255.255.0
1456 21:52:23.088018 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1457 21:52:23.088589 rootserver: 192.168.6.1 rootpath:
1458 21:52:23.091479 filename :
1459 21:52:23.147397 done.
1460 21:52:23.147834 Begin: Running /scripts/nfs-bottom ... done.
1461 21:52:23.158025 Begin: Running /scripts/init-bottom ... done.
1462 21:52:23.471899 <30>[ 23.639261] systemd[1]: System time before build time, advancing clock.
1463 21:52:23.534303 <6>[ 23.706040] NET: Registered PF_INET6 protocol family
1464 21:52:23.539784 <6>[ 23.707894] Segment Routing with IPv6
1465 21:52:23.544990 <6>[ 23.709564] In-situ OAM (IOAM) with IPv6
1466 21:52:23.628212 <30>[ 23.769000] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1467 21:52:23.631917 <30>[ 23.796427] systemd[1]: Detected architecture arm64.
1468 21:52:23.632459
1469 21:52:23.637757 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1470 21:52:23.638262
1471 21:52:23.653768 <30>[ 23.821841] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1472 21:52:24.322657 <30>[ 24.489517] systemd[1]: Queued start job for default target graphical.target.
1473 21:52:24.359932 <30>[ 24.526268] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1474 21:52:24.367497 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1475 21:52:24.382438 <30>[ 24.548840] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1476 21:52:24.390930 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1477 21:52:24.406551 <30>[ 24.572884] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1478 21:52:24.415723 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1479 21:52:24.430171 <30>[ 24.596600] systemd[1]: Created slice user.slice - User and Session Slice.
1480 21:52:24.436733 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1481 21:52:24.455268 <30>[ 24.616121] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1482 21:52:24.459359 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1483 21:52:24.473619 <30>[ 24.640050] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1484 21:52:24.483619 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1485 21:52:24.508722 <30>[ 24.664029] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1486 21:52:24.514280 <30>[ 24.678096] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1487 21:52:24.523372 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1488 21:52:24.541505 <30>[ 24.707943] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1489 21:52:24.549711 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1490 21:52:24.561520 <30>[ 24.727971] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1491 21:52:24.570936 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1492 21:52:24.585553 <30>[ 24.751989] systemd[1]: Reached target paths.target - Path Units.
1493 21:52:24.590616 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1494 21:52:24.605474 <30>[ 24.771948] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1495 21:52:24.612764 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1496 21:52:24.625510 <30>[ 24.791940] systemd[1]: Reached target slices.target - Slice Units.
1497 21:52:24.630918 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1498 21:52:24.645575 <30>[ 24.811955] systemd[1]: Reached target swap.target - Swaps.
1499 21:52:24.649550 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1500 21:52:24.665506 <30>[ 24.831974] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1501 21:52:24.674390 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1502 21:52:24.685656 <30>[ 24.852130] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1503 21:52:24.694899 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1504 21:52:24.710736 <30>[ 24.877199] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1505 21:52:24.719540 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1506 21:52:24.734464 <30>[ 24.900903] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1507 21:52:24.743858 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1508 21:52:24.757870 <30>[ 24.924299] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1509 21:52:24.765187 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1510 21:52:24.778494 <30>[ 24.944942] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1511 21:52:24.787617 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1512 21:52:24.803413 <30>[ 24.969864] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1513 21:52:24.809034 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1514 21:52:24.825706 <30>[ 24.992185] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1515 21:52:24.834181 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1516 21:52:24.869714 <30>[ 25.036101] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1517 21:52:24.876355 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1518 21:52:24.892135 <30>[ 25.058540] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1519 21:52:24.899655 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1520 21:52:24.920873 <30>[ 25.087301] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1521 21:52:24.928401 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1522 21:52:24.948297 <30>[ 25.108556] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1523 21:52:24.959309 <30>[ 25.124239] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1524 21:52:24.966383 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1525 21:52:24.986623 <30>[ 25.153054] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1526 21:52:24.994547 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1527 21:52:25.014661 <30>[ 25.181129] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1528 21:52:25.022404 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1529 21:52:25.038531 <6>[ 25.205051] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1530 21:52:25.049659 <30>[ 25.209166] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1531 21:52:25.054545 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1532 21:52:25.074531 <30>[ 25.241022] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1533 21:52:25.082849 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1534 21:52:25.138157 <30>[ 25.304519] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1535 21:52:25.145403 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1536 21:52:25.161327 <30>[ 25.327697] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1537 21:52:25.166837 <6>[ 25.330730] fuse: init (API version 7.40)
1538 21:52:25.170761 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1539 21:52:25.194529 <30>[ 25.360997] systemd[1]: Starting systemd-journald.service - Journal Service...
1540 21:52:25.200954 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1541 21:52:25.226402 <30>[ 25.392665] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1542 21:52:25.233741 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1543 21:52:25.255648 <30>[ 25.422040] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1544 21:52:25.264967 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1545 21:52:25.314567 <30>[ 25.480564] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1546 21:52:25.322921 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1547 21:52:25.347196 <30>[ 25.513463] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1548 21:52:25.355142 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1549 21:52:25.378415 <30>[ 25.544732] systemd[1]: Started systemd-journald.service - Journal Service.
1550 21:52:25.385280 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1551 21:52:25.406305 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1552 21:52:25.422829 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1553 21:52:25.439714 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1554 21:52:25.454896 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1555 21:52:25.475073 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1556 21:52:25.490901 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1557 21:52:25.508132 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1558 21:52:25.524565 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1559 21:52:25.540307 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1560 21:52:25.556588 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1561 21:52:25.571579 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1562 21:52:25.587953 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1563 21:52:25.603485 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1564 21:52:25.620972 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1565 21:52:25.685512 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1566 21:52:25.701641 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1567 21:52:25.718940 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1568 21:52:25.739945 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1569 21:52:25.766967 <46>[ 25.933329] systemd-journald[231]: Received client request to flush runtime journal.
1570 21:52:25.774343 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1571 21:52:25.799997 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1572 21:52:25.824550 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1573 21:52:25.839014 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1574 21:52:25.858967 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1575 21:52:25.875193 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1576 21:52:25.891190 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1577 21:52:25.934353 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1578 21:52:26.056434 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1579 21:52:26.070663 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1580 21:52:26.081592 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1581 21:52:26.141734 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1582 21:52:26.167492 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1583 21:52:26.408064 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1584 21:52:26.461287 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1585 21:52:26.487693 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1586 21:52:26.512843 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1587 21:52:26.582264 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1588 21:52:26.700921 <5>[ 26.867440] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1589 21:52:26.738340 <5>[ 26.904836] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1590 21:52:26.743923 <5>[ 26.905503] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1591 21:52:26.749499 <4>[ 26.913834] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1592 21:52:26.757664 <6>[ 26.921760] cfg80211: failed to load regulatory.db
1593 21:52:26.820205 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1594 21:52:26.839022 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1595 21:52:26.854462 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1596 21:52:26.870691 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1597 21:52:26.888950 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1598 21:52:26.957203 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1599 21:52:26.971195 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1600 21:52:26.987485 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1601 21:52:27.010790 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1602 21:52:27.027736 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1603 21:52:27.043902 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1604 21:52:27.059401 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1605 21:52:27.074775 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1606 21:52:27.105711 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1607 21:52:27.168491 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1608 21:52:27.181741 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1609 21:52:27.193946 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1610 21:52:27.209682 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1611 21:52:27.226330 <46>[ 27.379482] systemd-journald[231]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1612 21:52:27.241989 <46>[ 27.395951] systemd-journald[231]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1613 21:52:27.266709 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1614 21:52:27.284223 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1615 21:52:27.297912 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1616 21:52:27.376299 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1617 21:52:27.392164 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1618 21:52:27.408507 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1619 21:52:27.450817 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1620 21:52:27.468690 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1621 21:52:27.484735 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1622 21:52:27.513124 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1623 21:52:27.530400 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1624 21:52:27.551649 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1625 21:52:27.584879 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1626 21:52:27.599230 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1627 21:52:27.615242 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1628 21:52:27.629726 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1629 21:52:27.646890 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1630 21:52:27.661725 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1631 21:52:27.677513 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1632 21:52:27.724996 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1633 21:52:27.740594 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1634 21:52:27.752742 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1635 21:52:27.770225 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1636 21:52:27.782942 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1637 21:52:27.801915 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1638 21:52:27.853653 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1639 21:52:27.893590 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1640 21:52:27.949431
1641 21:52:27.950164 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1642 21:52:27.950719
1643 21:52:27.956545 debian-bookworm-arm64 login: root (automatic login)
1644 21:52:27.957194
1645 21:52:28.102333 Linux debian-bookworm-arm64 6.11.0-rc5 #1 SMP PREEMPT Fri Aug 30 21:13:35 UTC 2024 aarch64
1646 21:52:28.103520
1647 21:52:28.107873 The programs included with the Debian GNU/Linux system are free software;
1648 21:52:28.113316 the exact distribution terms for each program are described in the
1649 21:52:28.118906 individual files in /usr/share/doc/*/copyright.
1650 21:52:28.119467
1651 21:52:28.124437 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1652 21:52:28.127555 permitted by applicable law.
1653 21:52:28.807214 Matched prompt #10: / #
1655 21:52:28.808979 Setting prompt string to ['/ #']
1656 21:52:28.809639 end: 2.4.4.1 login-action (duration 00:00:29) [common]
1658 21:52:28.811245 end: 2.4.4 auto-login-action (duration 00:00:29) [common]
1659 21:52:28.811882 start: 2.4.5 expect-shell-connection (timeout 00:03:13) [common]
1660 21:52:28.812440 Setting prompt string to ['/ #']
1661 21:52:28.812910 Forcing a shell prompt, looking for ['/ #']
1663 21:52:28.864020 / #
1664 21:52:28.865178 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1665 21:52:28.865751 Waiting using forced prompt support (timeout 00:02:30)
1666 21:52:28.871278
1667 21:52:28.872230 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1668 21:52:28.872933 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
1669 21:52:28.873494 Sending with 10 millisecond of delay
1671 21:52:33.863139 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/680279/extract-nfsrootfs-n8mi20uc'
1672 21:52:33.874185 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/680279/extract-nfsrootfs-n8mi20uc'
1673 21:52:33.875056 Sending with 10 millisecond of delay
1675 21:52:35.975584 / # export NFS_SERVER_IP='192.168.6.2'
1676 21:52:35.986323 export NFS_SERVER_IP='192.168.6.2'
1677 21:52:35.987008 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1678 21:52:35.987360 end: 2.4 uboot-commands (duration 00:01:55) [common]
1679 21:52:35.987668 end: 2 uboot-action (duration 00:01:55) [common]
1680 21:52:35.987952 start: 3 lava-test-retry (timeout 00:06:46) [common]
1681 21:52:35.988277 start: 3.1 lava-test-shell (timeout 00:06:46) [common]
1682 21:52:35.988526 Using namespace: common
1684 21:52:36.089259 / # #
1685 21:52:36.089967 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1686 21:52:36.095448 #
1687 21:52:36.096016 Using /lava-680279
1689 21:52:36.196772 / # export SHELL=/bin/bash
1690 21:52:36.203197 export SHELL=/bin/bash
1692 21:52:36.304296 / # . /lava-680279/environment
1693 21:52:36.309157 . /lava-680279/environment
1695 21:52:36.413874 / # /lava-680279/bin/lava-test-runner /lava-680279/0
1696 21:52:36.414572 Test shell timeout: 10s (minimum of the action and connection timeout)
1697 21:52:36.418790 /lava-680279/bin/lava-test-runner /lava-680279/0
1698 21:52:36.614308 + export TESTRUN_ID=0_timesync-off
1699 21:52:36.621993 + TESTRUN_ID=0_timesync-off
1700 21:52:36.622649 + cd /lava-680279/0/tests/0_timesync-off
1701 21:52:36.623072 ++ cat uuid
1702 21:52:36.631114 + UUID=680279_1.6.2.4.1
1703 21:52:36.631512 + set +x
1704 21:52:36.639738 <LAVA_SIGNAL_STARTRUN 0_timesync-off 680279_1.6.2.4.1>
1705 21:52:36.640329 + systemctl stop systemd-timesyncd
1706 21:52:36.640910 Received signal: <STARTRUN> 0_timesync-off 680279_1.6.2.4.1
1707 21:52:36.641285 Starting test lava.0_timesync-off (680279_1.6.2.4.1)
1708 21:52:36.641719 Skipping test definition patterns.
1709 21:52:36.685656 + set +x
1710 21:52:36.686142 <LAVA_SIGNAL_ENDRUN 0_timesync-off 680279_1.6.2.4.1>
1711 21:52:36.686627 Received signal: <ENDRUN> 0_timesync-off 680279_1.6.2.4.1
1712 21:52:36.687063 Ending use of test pattern.
1713 21:52:36.687316 Ending test lava.0_timesync-off (680279_1.6.2.4.1), duration 0.05
1715 21:52:36.781415 + export TESTRUN_ID=1_kselftest-alsa
1716 21:52:36.789696 + TESTRUN_ID=1_kselftest-alsa
1717 21:52:36.790270 + cd /lava-680279/0/tests/1_kselftest-alsa
1718 21:52:36.790725 ++ cat uuid
1719 21:52:36.795597 + UUID=680279_1.6.2.4.5
1720 21:52:36.796804 + set +x
1721 21:52:36.801328 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 680279_1.6.2.4.5>
1722 21:52:36.801941 + cd ./automated/linux/kselftest/
1723 21:52:36.802703 Received signal: <STARTRUN> 1_kselftest-alsa 680279_1.6.2.4.5
1724 21:52:36.803193 Starting test lava.1_kselftest-alsa (680279_1.6.2.4.5)
1725 21:52:36.803728 Skipping test definition patterns.
1726 21:52:36.829302 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1727 21:52:36.854194 INFO: install_deps skipped
1728 21:52:36.966370 --2024-08-30 21:52:36-- http://storage.kernelci.org/mainline/master/v6.11-rc5-207-gfb24560f31f9d/arm64/defconfig/gcc-12/kselftest.tar.xz
1729 21:52:36.998533 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1730 21:52:37.139580 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1731 21:52:37.276515 HTTP request sent, awaiting response... 200 OK
1732 21:52:37.276901 Length: 6478508 (6.2M) [application/octet-stream]
1733 21:52:37.282084 Saving to: 'kselftest_armhf.tar.gz'
1734 21:52:37.282350
1735 21:52:38.593447
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 167KB/s
kselftest_armhf.tar 2%[ ] 179.29K 319KB/s
kselftest_armhf.tar 10%[=> ] 693.98K 826KB/s
kselftest_armhf.tar 39%[======> ] 2.42M 2.07MB/s
kselftest_armhf.tar 100%[===================>] 6.18M 4.71MB/s in 1.3s
1736 21:52:38.593876
1737 21:52:38.675214 2024-08-30 21:52:38 (4.71 MB/s) - 'kselftest_armhf.tar.gz' saved [6478508/6478508]
1738 21:52:38.675779
1739 21:52:47.038134 skiplist:
1740 21:52:47.038538 ========================================
1741 21:52:47.043753 ========================================
1742 21:52:47.081371 alsa:mixer-test
1743 21:52:47.081809 alsa:pcm-test
1744 21:52:47.082140 alsa:test-pcmtest-driver
1745 21:52:47.093906 ============== Tests to run ===============
1746 21:52:47.094181 alsa:mixer-test
1747 21:52:47.099447 alsa:pcm-test
1748 21:52:47.099713 alsa:test-pcmtest-driver
1749 21:52:47.106077 ===========End Tests to run ===============
1750 21:52:47.107005 shardfile-alsa pass
1751 21:52:47.201155 <12>[ 47.371578] kselftest: Running tests in alsa
1752 21:52:47.204656 TAP version 13
1753 21:52:47.213351 1..3
1754 21:52:47.232405 # timeout set to 45
1755 21:52:47.233004 # selftests: alsa: mixer-test
1756 21:52:47.421374 # TAP version 13
1757 21:52:47.421953 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1758 21:52:47.426767 # 1..427
1759 21:52:47.427200 # ok 1 get_value.LCALTA.60
1760 21:52:47.427599 # # LCALTA.60 TDMOUT_A SRC SEL
1761 21:52:47.432300 # ok 2 name.LCALTA.60
1762 21:52:47.432734 # ok 3 write_default.LCALTA.60
1763 21:52:47.437834 # ok 4 write_valid.LCALTA.60
1764 21:52:47.438256 # ok 5 write_invalid.LCALTA.60
1765 21:52:47.443400 # ok 6 event_missing.LCALTA.60
1766 21:52:47.443816 # ok 7 event_spurious.LCALTA.60
1767 21:52:47.448959 # ok 8 get_value.LCALTA.59
1768 21:52:47.449380 # # LCALTA.59 TDMOUT_B SRC SEL
1769 21:52:47.454457 # ok 9 name.LCALTA.59
1770 21:52:47.454871 # ok 10 write_default.LCALTA.59
1771 21:52:47.460029 # ok 11 write_valid.LCALTA.59
1772 21:52:47.460479 # ok 12 write_invalid.LCALTA.59
1773 21:52:47.465643 # ok 13 event_missing.LCALTA.59
1774 21:52:47.466070 # ok 14 event_spurious.LCALTA.59
1775 21:52:47.471271 # ok 15 get_value.LCALTA.58
1776 21:52:47.471847 # # LCALTA.58 TDMOUT_C SRC SEL
1777 21:52:47.476778 # ok 16 name.LCALTA.58
1778 21:52:47.477225 # ok 17 write_default.LCALTA.58
1779 21:52:47.482318 # ok 18 write_valid.LCALTA.58
1780 21:52:47.482898 # ok 19 write_invalid.LCALTA.58
1781 21:52:47.487891 # ok 20 event_missing.LCALTA.58
1782 21:52:47.488429 # ok 21 event_spurious.LCALTA.58
1783 21:52:47.493600 # ok 22 get_value.LCALTA.57
1784 21:52:47.494050 # # LCALTA.57 TDMIN_A SRC SEL
1785 21:52:47.494516 # ok 23 name.LCALTA.57
1786 21:52:47.498950 # ok 24 write_default.LCALTA.57
1787 21:52:47.499521 # ok 25 write_valid.LCALTA.57
1788 21:52:47.504512 # ok 26 write_invalid.LCALTA.57
1789 21:52:47.505022 # ok 27 event_missing.LCALTA.57
1790 21:52:47.510177 # ok 28 event_spurious.LCALTA.57
1791 21:52:47.510660 # ok 29 get_value.LCALTA.56
1792 21:52:47.515547 # # LCALTA.56 TDMIN_B SRC SEL
1793 21:52:47.516080 # ok 30 name.LCALTA.56
1794 21:52:47.521078 # ok 31 write_default.LCALTA.56
1795 21:52:47.521573 # ok 32 write_valid.LCALTA.56
1796 21:52:47.526739 # ok 33 write_invalid.LCALTA.56
1797 21:52:47.527251 # ok 34 event_missing.LCALTA.56
1798 21:52:47.532073 # ok 35 event_spurious.LCALTA.56
1799 21:52:47.532518 # ok 36 get_value.LCALTA.55
1800 21:52:47.537612 # # LCALTA.55 TDMIN_C SRC SEL
1801 21:52:47.538036 # ok 37 name.LCALTA.55
1802 21:52:47.554500 # ok 38 write_def<3>[ 47.709498] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1803 21:52:47.555059 ault.LCALTA.55
1804 21:52:47.555457 # ok 39 write_valid.LCALTA.55
1805 21:52:47.559764 # ok 40 write_invalid.LCALTA.55
1806 21:52:47.560219 # ok 41 event_missing.LCALTA.55
1807 21:52:47.565372 # ok 42 event_spurious.LCALTA.55
1808 21:52:47.565791 # ok 43 get_value.LCALTA.54
1809 21:52:47.570915 # # LCALTA.54 ACODEC Left DAC Sel
1810 21:52:47.571419 # ok 44 name.LCALTA.54
1811 21:52:47.576431 # ok 45 write_default.LCALTA.54
1812 21:52:47.576867 # ok 46 write_valid.LCALTA.54
1813 21:52:47.581952 # ok 47 write_invalid.LCALTA.54
1814 21:52:47.582375 # ok 48 event_missing.LCALTA.54
1815 21:52:47.587511 # ok 49 event_spurious.LCALTA.54
1816 21:52:47.587934 # ok 50 get_value.LCALTA.53
1817 21:52:47.593120 # # LCALTA.53 ACODEC Right DAC Sel
1818 21:52:47.593539 # ok 51 name.LCALTA.53
1819 21:52:47.598613 # ok 52 write_default.LCALTA.53
1820 21:52:47.599047 # ok 53 write_valid.LCALTA.53
1821 21:52:47.604187 # ok 54 write_invalid.LCALTA.53
1822 21:52:47.604611 # ok 55 event_missing.LCALTA.53
1823 21:52:47.609706 # ok 56 event_spurious.LCALTA.53
1824 21:52:47.610121 # ok 57 get_value.LCALTA.52
1825 21:52:47.615249 # # LCALTA.52 TOACODEC OUT EN Switch
1826 21:52:47.615666 # ok 58 name.LCALTA.52
1827 21:52:47.620790 # ok 59 write_default.LCALTA.52
1828 21:52:47.621211 # ok 60 write_valid.LCALTA.52
1829 21:52:47.626445 # ok 61 write_invalid.LCALTA.52
1830 21:52:47.626936 # ok 62 event_missing.LCALTA.52
1831 21:52:47.631893 # ok 63 event_spurious.LCALTA.52
1832 21:52:47.632412 # ok 64 get_value.LCALTA.51
1833 21:52:47.637504 # # LCALTA.51 TOACODEC SRC
1834 21:52:47.638069 # ok 65 name.LCALTA.51
1835 21:52:47.642992 # ok 66 write_default.LCALTA.51
1836 21:52:47.643496 # ok 67 write_valid.LCALTA.51
1837 21:52:47.648531 # ok 68 write_invalid.LCALTA.51
1838 21:52:47.649043 # ok 69 event_missing.LCALTA.51
1839 21:52:47.654251 # ok 70 event_spurious.LCALTA.51
1840 21:52:47.654854 # ok 71 get_value.LCALTA.50
1841 21:52:47.659706 # # LCALTA.50 TOHDMITX SPDIF SRC
1842 21:52:47.660287 # ok 72 name.LCALTA.50
1843 21:52:47.660759 # ok 73 write_default.LCALTA.50
1844 21:52:47.665222 # ok 74 write_valid.LCALTA.50
1845 21:52:47.665681 # ok 75 write_invalid.LCALTA.50
1846 21:52:47.670748 # ok 76 event_missing.LCALTA.50
1847 21:52:47.676413 # ok 77 event_spurious.LCALTA.50
1848 21:52:47.676866 # ok 78 get_value.LCALTA.49
1849 21:52:47.677264 # # LCALTA.49 TOHDMITX Switch
1850 21:52:47.681835 # ok 79 name.LCALTA.49
1851 21:52:47.682278 # ok 80 write_default.LCALTA.49
1852 21:52:47.687408 # ok 81 write_valid.LCALTA.49
1853 21:52:47.687859 # ok 82 write_invalid.LCALTA.49
1854 21:52:47.692905 # ok 83 event_missing.LCALTA.49
1855 21:52:47.693345 # ok 84 event_spurious.LCALTA.49
1856 21:52:47.698449 # ok 85 get_value.LCALTA.48
1857 21:52:47.698873 # # LCALTA.48 TOHDMITX I2S SRC
1858 21:52:47.704036 # ok 86 name.LCALTA.48
1859 21:52:47.704453 # ok 87 write_default.LCALTA.48
1860 21:52:47.709538 # ok 88 write_valid.LCALTA.48
1861 21:52:47.709954 # ok 89 write_invalid.LCALTA.48
1862 21:52:47.715129 # ok 90 event_missing.LCALTA.48
1863 21:52:47.715544 # ok 91 event_spurious.LCALTA.48
1864 21:52:47.720644 # ok 92 get_value.LCALTA.47
1865 21:52:47.721057 # # LCALTA.47 TODDR_C SRC SEL
1866 21:52:47.726193 # ok 93 name.LCALTA.47
1867 21:52:47.726603 # ok 94 write_default.LCALTA.47
1868 21:52:47.731725 # ok 95 write_valid.LCALTA.47
1869 21:52:47.732173 # ok 96 write_invalid.LCALTA.47
1870 21:52:47.737259 # ok 97 event_missing.LCALTA.47
1871 21:52:47.737689 # ok 98 event_spurious.LCALTA.47
1872 21:52:47.742832 # ok 99 get_value.LCALTA.46
1873 21:52:47.743243 # # LCALTA.46 TODDR_B SRC SEL
1874 21:52:47.743632 # ok 100 name.LCALTA.46
1875 21:52:47.748412 # ok 101 write_default.LCALTA.46
1876 21:52:47.753919 # ok 102 write_valid.LCALTA.46
1877 21:52:47.754333 # ok 103 write_invalid.LCALTA.46
1878 21:52:47.759478 # ok 104 event_missing.LCALTA.46
1879 21:52:47.759894 # ok 105 event_spurious.LCALTA.46
1880 21:52:47.765108 # ok 106 get_value.LCALTA.45
1881 21:52:47.765668 # # LCALTA.45 TODDR_A SRC SEL
1882 21:52:47.766076 # ok 107 name.LCALTA.45
1883 21:52:47.770741 # ok 108 write_default.LCALTA.45
1884 21:52:47.776314 # ok 109 write_valid.LCALTA.45
1885 21:52:47.776834 # ok 110 write_invalid.LCALTA.45
1886 21:52:47.781821 # ok 111 event_missing.LCALTA.45
1887 21:52:47.782320 # ok 112 event_spurious.LCALTA.45
1888 21:52:47.787306 # ok 113 get_value.LCALTA.44
1889 21:52:47.787805 # # LCALTA.44 FRDDR_C SINK 3 SEL
1890 21:52:47.792873 # ok 114 name.LCALTA.44
1891 21:52:47.793374 # ok 115 write_default.LCALTA.44
1892 21:52:47.798545 # ok 116 write_valid.LCALTA.44
1893 21:52:47.799044 # ok 117 write_invalid.LCALTA.44
1894 21:52:47.803932 # ok 118 event_missing.LCALTA.44
1895 21:52:47.804446 # ok 119 event_spurious.LCALTA.44
1896 21:52:47.809516 # ok 120 get_value.LCALTA.43
1897 21:52:47.810010 # # LCALTA.43 FRDDR_C SINK 2 SEL
1898 21:52:47.815046 # ok 121 name.LCALTA.43
1899 21:52:47.815540 # ok 122 write_default.LCALTA.43
1900 21:52:47.820569 # ok 123 write_valid.LCALTA.43
1901 21:52:47.821089 # ok 124 write_invalid.LCALTA.43
1902 21:52:47.826235 # ok 125 event_missing.LCALTA.43
1903 21:52:47.826769 # ok 126 event_spurious.LCALTA.43
1904 21:52:47.831732 # ok 127 get_value.LCALTA.42
1905 21:52:47.832272 # # LCALTA.42 FRDDR_C SINK 1 SEL
1906 21:52:47.837273 # ok 128 name.LCALTA.42
1907 21:52:47.837772 # ok 129 write_default.LCALTA.42
1908 21:52:47.842812 # ok 130 write_valid.LCALTA.42
1909 21:52:47.843311 # ok 131 write_invalid.LCALTA.42
1910 21:52:47.848356 # ok 132 event_missing.LCALTA.42
1911 21:52:47.848859 # ok 133 event_spurious.LCALTA.42
1912 21:52:47.853889 # ok 134 get_value.LCALTA.41
1913 21:52:47.854392 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1914 21:52:47.859564 # ok 135 name.LCALTA.41
1915 21:52:47.860094 # ok 136 write_default.LCALTA.41
1916 21:52:47.865013 # ok 137 write_valid.LCALTA.41
1917 21:52:47.865512 # ok 138 write_invalid.LCALTA.41
1918 21:52:47.870565 # ok 139 event_missing.LCALTA.41
1919 21:52:47.871057 # ok 140 event_spurious.LCALTA.41
1920 21:52:47.876094 # ok 141 get_value.LCALTA.40
1921 21:52:47.876594 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1922 21:52:47.881621 # ok 142 name.LCALTA.40
1923 21:52:47.882111 # ok 143 write_default.LCALTA.40
1924 21:52:47.887198 # ok 144 write_valid.LCALTA.40
1925 21:52:47.887698 # ok 145 write_invalid.LCALTA.40
1926 21:52:47.892714 # ok 146 event_missing.LCALTA.40
1927 21:52:47.893204 # ok 147 event_spurious.LCALTA.40
1928 21:52:47.898300 # ok 148 get_value.LCALTA.39
1929 21:52:47.903827 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1930 21:52:47.904358 # ok 149 name.LCALTA.39
1931 21:52:47.904753 # ok 150 write_default.LCALTA.39
1932 21:52:47.909350 # ok 151 write_valid.LCALTA.39
1933 21:52:47.909839 # ok 152 write_invalid.LCALTA.39
1934 21:52:47.914900 # ok 153 event_missing.LCALTA.39
1935 21:52:47.920554 # ok 154 event_spurious.LCALTA.39
1936 21:52:47.921051 # ok 155 get_value.LCALTA.38
1937 21:52:47.925991 # # LCALTA.38 FRDDR_B SINK 3 SEL
1938 21:52:47.926495 # ok 156 name.LCALTA.38
1939 21:52:47.926889 # ok 157 write_default.LCALTA.38
1940 21:52:47.931553 # ok 158 write_valid.LCALTA.38
1941 21:52:47.932079 # ok 159 write_invalid.LCALTA.38
1942 21:52:47.937062 # ok 160 event_missing.LCALTA.38
1943 21:52:47.942578 # ok 161 event_spurious.LCALTA.38
1944 21:52:47.943075 # ok 162 get_value.LCALTA.37
1945 21:52:47.948230 # # LCALTA.37 FRDDR_B SINK 2 SEL
1946 21:52:47.948737 # ok 163 name.LCALTA.37
1947 21:52:47.949131 # ok 164 write_default.LCALTA.37
1948 21:52:47.953707 # ok 165 write_valid.LCALTA.37
1949 21:52:47.959296 # ok 166 write_invalid.LCALTA.37
1950 21:52:47.959790 # ok 167 event_missing.LCALTA.37
1951 21:52:47.964846 # ok 168 event_spurious.LCALTA.37
1952 21:52:47.965346 # ok 169 get_value.LCALTA.36
1953 21:52:47.970362 # # LCALTA.36 FRDDR_B SINK 1 SEL
1954 21:52:47.970846 # ok 170 name.LCALTA.36
1955 21:52:47.975963 # ok 171 write_default.LCALTA.36
1956 21:52:47.976485 # ok 172 write_valid.LCALTA.36
1957 21:52:47.981581 # ok 173 write_invalid.LCALTA.36
1958 21:52:47.982071 # ok 174 event_missing.LCALTA.36
1959 21:52:47.987021 # ok 175 event_spurious.LCALTA.36
1960 21:52:47.987510 # ok 176 get_value.LCALTA.35
1961 21:52:47.992583 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1962 21:52:47.993071 # ok 177 name.LCALTA.35
1963 21:52:47.998067 # ok 178 write_default.LCALTA.35
1964 21:52:47.998575 # ok 179 write_valid.LCALTA.35
1965 21:52:48.003645 # ok 180 write_invalid.LCALTA.35
1966 21:52:48.004176 # ok 181 event_missing.LCALTA.35
1967 21:52:48.009242 # ok 182 event_spurious.LCALTA.35
1968 21:52:48.009742 # ok 183 get_value.LCALTA.34
1969 21:52:48.014755 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1970 21:52:48.015256 # ok 184 name.LCALTA.34
1971 21:52:48.020327 # ok 185 write_default.LCALTA.34
1972 21:52:48.020825 # ok 186 write_valid.LCALTA.34
1973 21:52:48.025853 # ok 187 write_invalid.LCALTA.34
1974 21:52:48.026354 # ok 188 event_missing.LCALTA.34
1975 21:52:48.031372 # ok 189 event_spurious.LCALTA.34
1976 21:52:48.031869 # ok 190 get_value.LCALTA.33
1977 21:52:48.036929 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1978 21:52:48.037426 # ok 191 name.LCALTA.33
1979 21:52:48.042563 # ok 192 write_default.LCALTA.33
1980 21:52:48.043062 # ok 193 write_valid.LCALTA.33
1981 21:52:48.048014 # ok 194 write_invalid.LCALTA.33
1982 21:52:48.048517 # ok 195 event_missing.LCALTA.33
1983 21:52:48.053559 # ok 196 event_spurious.LCALTA.33
1984 21:52:48.054053 # ok 197 get_value.LCALTA.32
1985 21:52:48.059074 # # LCALTA.32 FRDDR_A SINK 3 SEL
1986 21:52:48.059586 # ok 198 name.LCALTA.32
1987 21:52:48.064701 # ok 199 write_default.LCALTA.32
1988 21:52:48.065213 # ok 200 write_valid.LCALTA.32
1989 21:52:48.070228 # ok 201 write_invalid.LCALTA.32
1990 21:52:48.070735 # ok 202 event_missing.LCALTA.32
1991 21:52:48.075775 # ok 203 event_spurious.LCALTA.32
1992 21:52:48.076307 # ok 204 get_value.LCALTA.31
1993 21:52:48.081335 # # LCALTA.31 FRDDR_A SINK 2 SEL
1994 21:52:48.081822 # ok 205 name.LCALTA.31
1995 21:52:48.086818 # ok 206 write_default.LCALTA.31
1996 21:52:48.087339 # ok 207 write_valid.LCALTA.31
1997 21:52:48.092443 # ok 208 write_invalid.LCALTA.31
1998 21:52:48.092958 # ok 209 event_missing.LCALTA.31
1999 21:52:48.097955 # ok 210 event_spurious.LCALTA.31
2000 21:52:48.098443 # ok 211 get_value.LCALTA.30
2001 21:52:48.103564 # # LCALTA.30 FRDDR_A SINK 1 SEL
2002 21:52:48.104083 # ok 212 name.LCALTA.30
2003 21:52:48.109035 # ok 213 write_default.LCALTA.30
2004 21:52:48.109531 # ok 214 write_valid.LCALTA.30
2005 21:52:48.114602 # ok 215 write_invalid.LCALTA.30
2006 21:52:48.120113 # ok 216 event_missing.LCALTA.30
2007 21:52:48.120609 # ok 217 event_spurious.LCALTA.30
2008 21:52:48.125670 # ok 218 get_value.LCALTA.29
2009 21:52:48.126170 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2010 21:52:48.131191 # ok 219 name.LCALTA.29
2011 21:52:48.131675 # ok 220 write_default.LCALTA.29
2012 21:52:48.136730 # ok 221 write_valid.LCALTA.29
2013 21:52:48.137215 # ok 222 write_invalid.LCALTA.29
2014 21:52:48.142307 # ok 223 event_missing.LCALTA.29
2015 21:52:48.142790 # ok 224 event_spurious.LCALTA.29
2016 21:52:48.147821 # ok 225 get_value.LCALTA.28
2017 21:52:48.148329 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2018 21:52:48.153372 # ok 226 name.LCALTA.28
2019 21:52:48.153858 # ok 227 write_default.LCALTA.28
2020 21:52:48.158966 # ok 228 write_valid.LCALTA.28
2021 21:52:48.159447 # ok 229 write_invalid.LCALTA.28
2022 21:52:48.164603 # ok 230 event_missing.LCALTA.28
2023 21:52:48.165095 # ok 231 event_spurious.LCALTA.28
2024 21:52:48.170060 # ok 232 get_value.LCALTA.27
2025 21:52:48.170547 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2026 21:52:48.175614 # ok 233 name.LCALTA.27
2027 21:52:48.176134 # ok 234 write_default.LCALTA.27
2028 21:52:48.181146 # ok 235 write_valid.LCALTA.27
2029 21:52:48.181633 # ok 236 write_invalid.LCALTA.27
2030 21:52:48.186684 # ok 237 event_missing.LCALTA.27
2031 21:52:48.187172 # ok 238 event_spurious.LCALTA.27
2032 21:52:48.192271 # ok 239 get_value.LCALTA.26
2033 21:52:48.192758 # # LCALTA.26 ELD
2034 21:52:48.197779 # ok 240 name.LCALTA.26
2035 21:52:48.198266 # # ELD is not writeable
2036 21:52:48.203315 # ok 241 # SKIP write_default.LCALTA.26
2037 21:52:48.203800 # # ELD is not writeable
2038 21:52:48.208886 # ok 242 # SKIP write_valid.LCALTA.26
2039 21:52:48.209376 # # ELD is not writeable
2040 21:52:48.214421 # ok 243 # SKIP write_invalid.LCALTA.26
2041 21:52:48.214908 # ok 244 event_missing.LCALTA.26
2042 21:52:48.219944 # ok 245 event_spurious.LCALTA.26
2043 21:52:48.220462 # ok 246 get_value.LCALTA.25
2044 21:52:48.225600 # # LCALTA.25 IEC958 Playback Default
2045 21:52:48.226090 # ok 247 name.LCALTA.25
2046 21:52:48.231016 # ok 248 write_default.LCALTA.25
2047 21:52:48.231500 # ok 249 # SKIP write_valid.LCALTA.25
2048 21:52:48.236561 # ok 250 # SKIP write_invalid.LCALTA.25
2049 21:52:48.242123 # ok 251 event_missing.LCALTA.25
2050 21:52:48.242606 # ok 252 event_spurious.LCALTA.25
2051 21:52:48.247768 # ok 253 get_value.LCALTA.24
2052 21:52:48.248373 # # LCALTA.24 IEC958 Playback Mask
2053 21:52:48.248807 # ok 254 name.LCALTA.24
2054 21:52:48.253239 # # IEC958 Playback Mask is not writeable
2055 21:52:48.258804 # ok 255 # SKIP write_default.LCALTA.24
2056 21:52:48.259303 # # IEC958 Playback Mask is not writeable
2057 21:52:48.264354 # ok 256 # SKIP write_valid.LCALTA.24
2058 21:52:48.269871 # # IEC958 Playback Mask is not writeable
2059 21:52:48.270364 # ok 257 # SKIP write_invalid.LCALTA.24
2060 21:52:48.275406 # ok 258 event_missing.LCALTA.24
2061 21:52:48.275889 # ok 259 event_spurious.LCALTA.24
2062 21:52:48.280970 # ok 260 get_value.LCALTA.23
2063 21:52:48.281452 # # LCALTA.23 Playback Channel Map
2064 21:52:48.286575 # ok 261 name.LCALTA.23
2065 21:52:48.292070 # # Playback Channel Map is not writeable
2066 21:52:48.292554 # ok 262 # SKIP write_default.LCALTA.23
2067 21:52:48.297584 # # Playback Channel Map is not writeable
2068 21:52:48.298071 # ok 263 # SKIP write_valid.LCALTA.23
2069 21:52:48.303131 # # Playback Channel Map is not writeable
2070 21:52:48.308731 # ok 264 # SKIP write_invalid.LCALTA.23
2071 21:52:48.309246 # ok 265 event_missing.LCALTA.23
2072 21:52:48.314244 # ok 266 event_spurious.LCALTA.23
2073 21:52:48.314728 # ok 267 get_value.LCALTA.22
2074 21:52:48.319769 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2075 21:52:48.320290 # ok 268 name.LCALTA.22
2076 21:52:48.325368 # ok 269 write_default.LCALTA.22
2077 21:52:48.325853 # ok 270 write_valid.LCALTA.22
2078 21:52:48.330915 # ok 271 write_invalid.LCALTA.22
2079 21:52:48.331401 # ok 272 event_missing.LCALTA.22
2080 21:52:48.336429 # ok 273 event_spurious.LCALTA.22
2081 21:52:48.341973 # ok 274 get_value.LCALTA.21
2082 21:52:48.342457 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2083 21:52:48.342846 # ok 275 name.LCALTA.21
2084 21:52:48.347593 # ok 276 write_default.LCALTA.21
2085 21:52:48.353062 # ok 277 write_valid.LCALTA.21
2086 21:52:48.353550 # ok 278 write_invalid.LCALTA.21
2087 21:52:48.358633 # ok 279 event_missing.LCALTA.21
2088 21:52:48.359110 # ok 280 event_spurious.LCALTA.21
2089 21:52:48.364224 # ok 281 get_value.LCALTA.20
2090 21:52:48.364717 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2091 21:52:48.369721 # ok 282 name.LCALTA.20
2092 21:52:48.370212 # ok 283 write_default.LCALTA.20
2093 21:52:48.375300 # ok 284 write_valid.LCALTA.20
2094 21:52:48.375797 # ok 285 write_invalid.LCALTA.20
2095 21:52:48.380842 # ok 286 event_missing.LCALTA.20
2096 21:52:48.381324 # ok 287 event_spurious.LCALTA.20
2097 21:52:48.386370 # ok 288 get_value.LCALTA.19
2098 21:52:48.386850 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2099 21:52:48.391917 # ok 289 name.LCALTA.19
2100 21:52:48.392424 # ok 290 write_default.LCALTA.19
2101 21:52:48.397464 # ok 291 write_valid.LCALTA.19
2102 21:52:48.397950 # ok 292 write_invalid.LCALTA.19
2103 21:52:48.403016 # ok 293 event_missing.LCALTA.19
2104 21:52:48.403511 # ok 294 event_spurious.LCALTA.19
2105 21:52:48.408669 # ok 295 get_value.LCALTA.18
2106 21:52:48.409163 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2107 21:52:48.414105 # ok 296 name.LCALTA.18
2108 21:52:48.414598 # ok 297 write_default.LCALTA.18
2109 21:52:48.419703 # ok 298 write_valid.LCALTA.18
2110 21:52:48.420227 # ok 299 write_invalid.LCALTA.18
2111 21:52:48.425188 # ok 300 event_missing.LCALTA.18
2112 21:52:48.425680 # ok 301 event_spurious.LCALTA.18
2113 21:52:48.430733 # ok 302 get_value.LCALTA.17
2114 21:52:48.436302 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2115 21:52:48.436791 # ok 303 name.LCALTA.17
2116 21:52:48.437185 # ok 304 write_default.LCALTA.17
2117 21:52:48.441791 # ok 305 write_valid.LCALTA.17
2118 21:52:48.447337 # ok 306 write_invalid.LCALTA.17
2119 21:52:48.447821 # ok 307 event_missing.LCALTA.17
2120 21:52:48.452909 # ok 308 event_spurious.LCALTA.17
2121 21:52:48.453397 # ok 309 get_value.LCALTA.16
2122 21:52:48.458490 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2123 21:52:48.459013 # ok 310 name.LCALTA.16
2124 21:52:48.464078 # ok 311 write_default.LCALTA.16
2125 21:52:48.464588 # ok 312 write_valid.LCALTA.16
2126 21:52:48.469596 # ok 313 write_invalid.LCALTA.16
2127 21:52:48.470077 # ok 314 event_missing.LCALTA.16
2128 21:52:48.475124 # ok 315 event_spurious.LCALTA.16
2129 21:52:48.475635 # ok 316 get_value.LCALTA.15
2130 21:52:48.480678 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2131 21:52:48.481173 # ok 317 name.LCALTA.15
2132 21:52:48.486177 # ok 318 write_default.LCALTA.15
2133 21:52:48.486661 # ok 319 write_valid.LCALTA.15
2134 21:52:48.491742 # ok 320 write_invalid.LCALTA.15
2135 21:52:48.492259 # ok 321 event_missing.LCALTA.15
2136 21:52:48.497311 # ok 322 event_spurious.LCALTA.15
2137 21:52:48.497800 # ok 323 get_value.LCALTA.14
2138 21:52:48.502852 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2139 21:52:48.503340 # ok 324 name.LCALTA.14
2140 21:52:48.508384 # ok 325 write_default.LCALTA.14
2141 21:52:48.508874 # ok 326 write_valid.LCALTA.14
2142 21:52:48.513921 # ok 327 write_invalid.LCALTA.14
2143 21:52:48.514403 # ok 328 event_missing.LCALTA.14
2144 21:52:48.519537 # ok 329 event_spurious.LCALTA.14
2145 21:52:48.520069 # ok 330 get_value.LCALTA.13
2146 21:52:48.525005 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2147 21:52:48.525494 # ok 331 name.LCALTA.13
2148 21:52:48.530625 # ok 332 write_default.LCALTA.13
2149 21:52:48.531109 # ok 333 write_valid.LCALTA.13
2150 21:52:48.536176 # ok 334 write_invalid.LCALTA.13
2151 21:52:48.536663 # ok 335 event_missing.LCALTA.13
2152 21:52:48.541663 # ok 336 event_spurious.LCALTA.13
2153 21:52:48.542145 # ok 337 get_value.LCALTA.12
2154 21:52:48.547197 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2155 21:52:48.547678 # ok 338 name.LCALTA.12
2156 21:52:48.552778 # ok 339 write_default.LCALTA.12
2157 21:52:48.558281 # ok 340 write_valid.LCALTA.12
2158 21:52:48.558770 # ok 341 write_invalid.LCALTA.12
2159 21:52:48.563891 # ok 342 event_missing.LCALTA.12
2160 21:52:48.564424 # ok 343 event_spurious.LCALTA.12
2161 21:52:48.569400 # ok 344 get_value.LCALTA.11
2162 21:52:48.569900 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2163 21:52:48.574965 # ok 345 name.LCALTA.11
2164 21:52:48.575463 # ok 346 write_default.LCALTA.11
2165 21:52:48.580514 # ok 347 write_valid.LCALTA.11
2166 21:52:48.581014 # ok 348 write_invalid.LCALTA.11
2167 21:52:48.586049 # ok 349 event_missing.LCALTA.11
2168 21:52:48.586547 # ok 350 event_spurious.LCALTA.11
2169 21:52:48.591658 # ok 351 get_value.LCALTA.10
2170 21:52:48.592182 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2171 21:52:48.597151 # ok 352 name.LCALTA.10
2172 21:52:48.597645 # ok 353 write_default.LCALTA.10
2173 21:52:48.602730 # ok 354 write_valid.LCALTA.10
2174 21:52:48.603228 # ok 355 write_invalid.LCALTA.10
2175 21:52:48.608263 # ok 356 event_missing.LCALTA.10
2176 21:52:48.608754 # ok 357 event_spurious.LCALTA.10
2177 21:52:48.613818 # ok 358 get_value.LCALTA.9
2178 21:52:48.614304 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2179 21:52:48.619408 # ok 359 name.LCALTA.9
2180 21:52:48.619907 # ok 360 write_default.LCALTA.9
2181 21:52:48.624875 # ok 361 write_valid.LCALTA.9
2182 21:52:48.625360 # ok 362 write_invalid.LCALTA.9
2183 21:52:48.630449 # ok 363 event_missing.LCALTA.9
2184 21:52:48.630935 # ok 364 event_spurious.LCALTA.9
2185 21:52:48.635969 # ok 365 get_value.LCALTA.8
2186 21:52:48.636493 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2187 21:52:48.641697 # ok 366 name.LCALTA.8
2188 21:52:48.642197 # ok 367 write_default.LCALTA.8
2189 21:52:48.647060 # ok 368 write_valid.LCALTA.8
2190 21:52:48.647570 # ok 369 write_invalid.LCALTA.8
2191 21:52:48.652654 # ok 370 event_missing.LCALTA.8
2192 21:52:48.653156 # ok 371 event_spurious.LCALTA.8
2193 21:52:48.658191 # ok 372 get_value.LCALTA.7
2194 21:52:48.658694 # # LCALTA.7 ACODEC Unmute Ramp Switch
2195 21:52:48.663713 # ok 373 name.LCALTA.7
2196 21:52:48.664269 # ok 374 write_default.LCALTA.7
2197 21:52:48.669269 # ok 375 write_valid.LCALTA.7
2198 21:52:48.669783 # ok 376 write_invalid.LCALTA.7
2199 21:52:48.674803 # ok 377 event_missing.LCALTA.7
2200 21:52:48.675312 # ok 378 event_spurious.LCALTA.7
2201 21:52:48.680468 # ok 379 get_value.LCALTA.6
2202 21:52:48.680979 # # LCALTA.6 ACODEC Mute Ramp Switch
2203 21:52:48.685961 # ok 380 name.LCALTA.6
2204 21:52:48.686463 # ok 381 write_default.LCALTA.6
2205 21:52:48.691503 # ok 382 write_valid.LCALTA.6
2206 21:52:48.692020 # ok 383 write_invalid.LCALTA.6
2207 21:52:48.696968 # ok 384 event_missing.LCALTA.6
2208 21:52:48.697451 # ok 385 event_spurious.LCALTA.6
2209 21:52:48.702715 # ok 386 get_value.LCALTA.5
2210 21:52:48.703204 # # LCALTA.5 ACODEC Volume Ramp Switch
2211 21:52:48.708127 # ok 387 name.LCALTA.5
2212 21:52:48.708629 # ok 388 write_default.LCALTA.5
2213 21:52:48.713681 # ok 389 write_valid.LCALTA.5
2214 21:52:48.714165 # ok 390 write_invalid.LCALTA.5
2215 21:52:48.719179 # ok 391 event_missing.LCALTA.5
2216 21:52:48.719677 # ok 392 event_spurious.LCALTA.5
2217 21:52:48.724729 # ok 393 get_value.LCALTA.4
2218 21:52:48.725235 # # LCALTA.4 ACODEC Ramp Rate
2219 21:52:48.730231 # ok 394 name.LCALTA.4
2220 21:52:48.730739 # ok 395 write_default.LCALTA.4
2221 21:52:48.735825 # ok 396 write_valid.LCALTA.4
2222 21:52:48.736358 # ok 397 write_invalid.LCALTA.4
2223 21:52:48.741432 # ok 398 event_missing.LCALTA.4
2224 21:52:48.741918 # ok 399 event_spurious.LCALTA.4
2225 21:52:48.746894 # ok 400 get_value.LCALTA.3
2226 21:52:48.747367 # # LCALTA.3 ACODEC Playback Volume
2227 21:52:48.752488 # ok 401 name.LCALTA.3
2228 21:52:48.752981 # ok 402 write_default.LCALTA.3
2229 21:52:48.758005 # ok 403 write_valid.LCALTA.3
2230 21:52:48.758498 # ok 404 write_invalid.LCALTA.3
2231 21:52:48.763671 # ok 405 event_missing.LCALTA.3
2232 21:52:48.764184 # ok 406 event_spurious.LCALTA.3
2233 21:52:48.769096 # ok 407 get_value.LCALTA.2
2234 21:52:48.769574 # # LCALTA.2 ACODEC Playback Switch
2235 21:52:48.774685 # ok 408 name.LCALTA.2
2236 21:52:48.775163 # ok 409 write_default.LCALTA.2
2237 21:52:48.780212 # ok 410 write_valid.LCALTA.2
2238 21:52:48.780686 # ok 411 write_invalid.LCALTA.2
2239 21:52:48.785721 # ok 412 event_missing.LCALTA.2
2240 21:52:48.786186 # ok 413 event_spurious.LCALTA.2
2241 21:52:48.791247 # ok 414 get_value.LCALTA.1
2242 21:52:48.791720 # # LCALTA.1 ACODEC Playback Channel Mode
2243 21:52:48.796795 # ok 415 name.LCALTA.1
2244 21:52:48.797275 # ok 416 write_default.LCALTA.1
2245 21:52:48.802394 # ok 417 write_valid.LCALTA.1
2246 21:52:48.802871 # ok 418 write_invalid.LCALTA.1
2247 21:52:48.807871 # ok 419 event_missing.LCALTA.1
2248 21:52:48.808384 # ok 420 event_spurious.LCALTA.1
2249 21:52:48.813500 # ok 421 get_value.LCALTA.0
2250 21:52:48.813996 # # LCALTA.0 TOACODEC Lane Select
2251 21:52:48.819003 # ok 422 name.LCALTA.0
2252 21:52:48.819501 # ok 423 write_default.LCALTA.0
2253 21:52:48.824755 # ok 424 write_valid.LCALTA.0
2254 21:52:48.825279 # ok 425 write_invalid.LCALTA.0
2255 21:52:48.830156 # ok 426 event_missing.LCALTA.0
2256 21:52:48.830679 # ok 427 event_spurious.LCALTA.0
2257 21:52:48.835720 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2258 21:52:48.841227 ok 1 selftests: alsa: mixer-test
2259 21:52:48.841727 # timeout set to 45
2260 21:52:48.842115 # selftests: alsa: pcm-test
2261 21:52:48.846743 # TAP version 13
2262 21:52:48.847232 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2263 21:52:48.852288 # # LCALTA.0 - fe.dai-link-0 (*)
2264 21:52:48.852781 # # LCALTA.0 - fe.dai-link-1 (*)
2265 21:52:48.857815 # # LCALTA.0 - fe.dai-link-2 (*)
2266 21:52:48.858306 # # LCALTA.0 - fe.dai-link-3 (*)
2267 21:52:48.863418 # # LCALTA.0 - fe.dai-link-4 (*)
2268 21:52:48.863902 # # LCALTA.0 - fe.dai-link-5 (*)
2269 21:52:48.868916 # 1..42
2270 21:52:48.874488 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2271 21:52:48.874969 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2272 21:52:48.880022 # # snd_pcm_hw_params: Invalid argument
2273 21:52:48.885719 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2274 21:52:48.891119 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2275 21:52:48.891592 # # snd_pcm_hw_params: Invalid argument
2276 21:52:48.896704 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2277 21:52:48.902207 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2278 21:52:48.907769 # # snd_pcm_hw_params: Invalid argument
2279 21:52:48.913311 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2280 21:52:48.918849 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2281 21:52:48.919345 # # snd_pcm_hw_params: Invalid argument
2282 21:52:48.924432 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2283 21:52:48.929933 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2284 21:52:48.935508 # # snd_pcm_hw_params: Invalid argument
2285 21:52:48.941018 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2286 21:52:48.946732 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2287 21:52:48.947212 # # snd_pcm_hw_params: Invalid argument
2288 21:52:48.952141 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2289 21:52:48.957694 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2290 21:52:48.963184 # # snd_pcm_hw_params: Invalid argument
2291 21:52:48.968751 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2292 21:52:48.969266 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2293 21:52:48.974319 # # snd_pcm_hw_params: Invalid argument
2294 21:52:48.979866 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2295 21:52:48.985507 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2296 21:52:48.986005 # # snd_pcm_hw_params: Invalid argument
2297 21:52:48.996461 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2298 21:52:48.996965 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2299 21:52:49.002075 # # snd_pcm_hw_params: Invalid argument
2300 21:52:49.007718 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2301 21:52:49.013155 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2302 21:52:49.013644 # # snd_pcm_hw_params: Invalid argument
2303 21:52:49.018751 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2304 21:52:49.024258 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2305 21:52:49.029786 # # snd_pcm_hw_params: Invalid argument
2306 21:52:49.035381 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2307 21:52:49.040870 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2308 21:52:49.041384 # # snd_pcm_hw_params: Invalid argument
2309 21:52:49.046480 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2310 21:52:49.051957 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2311 21:52:49.057504 # # snd_pcm_hw_params: Invalid argument
2312 21:52:49.063040 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2313 21:52:49.068711 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2314 21:52:49.069199 # # snd_pcm_hw_params: Invalid argument
2315 21:52:49.074173 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2316 21:52:49.079705 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2317 21:52:49.085234 # # snd_pcm_hw_params: Invalid argument
2318 21:52:49.090823 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2319 21:52:49.091317 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2320 21:52:49.096356 # # snd_pcm_hw_params: Invalid argument
2321 21:52:49.101902 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2322 21:52:49.107488 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2323 21:52:49.112976 # # snd_pcm_hw_params: Invalid argument
2324 21:52:49.118525 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2325 21:52:49.119020 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2326 21:52:49.124084 # # snd_pcm_hw_params: Invalid argument
2327 21:52:49.129769 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2328 21:52:49.135220 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2329 21:52:49.140736 # # snd_pcm_hw_params: Invalid argument
2330 21:52:49.146315 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2331 21:52:49.146832 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2332 21:52:49.151850 # # snd_pcm_hw_params: Invalid argument
2333 21:52:49.157467 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2334 21:52:49.162942 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2335 21:52:49.163457 # # snd_pcm_hw_params: Invalid argument
2336 21:52:49.168539 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2337 21:52:49.174028 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2338 21:52:49.179585 # # snd_pcm_hw_params: Invalid argument
2339 21:52:49.185159 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2340 21:52:49.190741 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2341 21:52:49.191240 # # snd_pcm_hw_params: Invalid argument
2342 21:52:49.196271 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2343 21:52:49.201779 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2344 21:52:49.207300 # # snd_pcm_hw_params: Invalid argument
2345 21:52:49.212833 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2346 21:52:49.218426 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2347 21:52:49.218927 # # snd_pcm_hw_params: Invalid argument
2348 21:52:49.223925 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2349 21:52:49.229534 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2350 21:52:49.235004 # # snd_pcm_hw_params: Invalid argument
2351 21:52:49.240562 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2352 21:52:49.246108 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2353 21:52:49.246607 # # snd_pcm_hw_params: Invalid argument
2354 21:52:49.251811 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2355 21:52:49.257208 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2356 21:52:49.262749 # # snd_pcm_hw_params: Invalid argument
2357 21:52:49.268323 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2358 21:52:49.273894 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2359 21:52:49.274400 # # snd_pcm_hw_params: Invalid argument
2360 21:52:49.279416 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2361 21:52:49.284968 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2362 21:52:49.290517 # # snd_pcm_hw_params: Invalid argument
2363 21:52:49.296101 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2364 21:52:49.301600 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2365 21:52:49.302096 # # snd_pcm_hw_params: Invalid argument
2366 21:52:49.307170 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2367 21:52:49.312779 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2368 21:52:49.318231 # # snd_pcm_hw_params: Invalid argument
2369 21:52:49.323770 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2370 21:52:49.329357 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2371 21:52:49.329853 # # snd_pcm_hw_params: Invalid argument
2372 21:52:49.334871 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2373 21:52:49.340419 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2374 21:52:49.346000 # # snd_pcm_hw_params: Invalid argument
2375 21:52:49.351566 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2376 21:52:49.357070 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2377 21:52:49.357585 # # snd_pcm_hw_params: Invalid argument
2378 21:52:49.362642 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2379 21:52:49.368213 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2380 21:52:49.373771 # # snd_pcm_hw_params: Invalid argument
2381 21:52:49.379334 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2382 21:52:49.384862 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2383 21:52:49.385408 # # snd_pcm_hw_params: Invalid argument
2384 21:52:49.390349 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2385 21:52:49.395907 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2386 21:52:49.401413 # # snd_pcm_hw_params: Invalid argument
2387 21:52:49.406980 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2388 21:52:49.412573 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2389 21:52:49.413090 # # snd_pcm_hw_params: Invalid argument
2390 21:52:49.418071 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2391 21:52:49.423623 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2392 21:52:49.429177 # # snd_pcm_hw_params: Invalid argument
2393 21:52:49.434789 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2394 21:52:49.440315 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2395 21:52:49.440847 # # snd_pcm_hw_params: Invalid argument
2396 21:52:49.445816 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2397 21:52:49.451363 ok 2 selftests: alsa: pcm-test
2398 21:52:49.451876 # timeout set to 45
2399 21:52:49.456908 # selftests: alsa: test-pcmtest-driver
2400 21:52:49.457415 # TAP version 13
2401 21:52:49.457827 # 1..5
2402 21:52:49.462426 # # Starting 5 tests from 1 test cases.
2403 21:52:49.462939 # # RUN pcmtest.playback ...
2404 21:52:49.468087 # # SKIP Can't read patterns. Probably, module isn't loaded
2405 21:52:49.473654 # # OK pcmtest.playback
2406 21:52:49.479137 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2407 21:52:49.484621 # # RUN pcmtest.capture ...
2408 21:52:49.490183 # # SKIP Can't read patterns. Probably, module isn't loaded
2409 21:52:49.495803 # # OK pcmtest.capture
2410 21:52:49.501341 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2411 21:52:49.506894 # # RUN pcmtest.ni_capture ...
2412 21:52:49.512401 # # SKIP Can't read patterns. Probably, module isn't loaded
2413 21:52:49.512926 # # OK pcmtest.ni_capture
2414 21:52:49.523445 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2415 21:52:49.524028 # # RUN pcmtest.ni_playback ...
2416 21:52:49.529051 # # SKIP Can't read patterns. Probably, module isn't loaded
2417 21:52:49.534542 # # OK pcmtest.ni_playback
2418 21:52:49.540142 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2419 21:52:49.545693 # # RUN pcmtest.reset_ioctl ...
2420 21:52:49.551183 # # SKIP Can't read patterns. Probably, module isn't loaded
2421 21:52:49.556796 # # OK pcmtest.reset_ioctl
2422 21:52:49.562263 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2423 21:52:49.567882 # # PASSED: 5 / 5 tests passed.
2424 21:52:49.573770 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2425 21:52:49.574298 ok 3 selftests: alsa: test-pcmtest-driver
2426 21:52:50.169545 alsa_mixer-test_get_value_LCALTA_60 pass
2427 21:52:50.176242 alsa_mixer-test_name_LCALTA_60 pass
2428 21:52:50.177189 alsa_mixer-test_write_default_LCALTA_60 pass
2429 21:52:50.180569 alsa_mixer-test_write_valid_LCALTA_60 pass
2430 21:52:50.186120 alsa_mixer-test_write_invalid_LCALTA_60 pass
2431 21:52:50.194506 alsa_mixer-test_event_missing_LCALTA_60 pass
2432 21:52:50.195005 alsa_mixer-test_event_spurious_LCALTA_60 pass
2433 21:52:50.197137 alsa_mixer-test_get_value_LCALTA_59 pass
2434 21:52:50.202503 alsa_mixer-test_name_LCALTA_59 pass
2435 21:52:50.202835 alsa_mixer-test_write_default_LCALTA_59 pass
2436 21:52:50.208132 alsa_mixer-test_write_valid_LCALTA_59 pass
2437 21:52:50.214010 alsa_mixer-test_write_invalid_LCALTA_59 pass
2438 21:52:50.214456 alsa_mixer-test_event_missing_LCALTA_59 pass
2439 21:52:50.219304 alsa_mixer-test_event_spurious_LCALTA_59 pass
2440 21:52:50.224874 alsa_mixer-test_get_value_LCALTA_58 pass
2441 21:52:50.225372 alsa_mixer-test_name_LCALTA_58 pass
2442 21:52:50.230245 alsa_mixer-test_write_default_LCALTA_58 pass
2443 21:52:50.235812 alsa_mixer-test_write_valid_LCALTA_58 pass
2444 21:52:50.236309 alsa_mixer-test_write_invalid_LCALTA_58 pass
2445 21:52:50.241295 alsa_mixer-test_event_missing_LCALTA_58 pass
2446 21:52:50.246888 alsa_mixer-test_event_spurious_LCALTA_58 pass
2447 21:52:50.252425 alsa_mixer-test_get_value_LCALTA_57 pass
2448 21:52:50.252872 alsa_mixer-test_name_LCALTA_57 pass
2449 21:52:50.258140 alsa_mixer-test_write_default_LCALTA_57 pass
2450 21:52:50.263608 alsa_mixer-test_write_valid_LCALTA_57 pass
2451 21:52:50.264066 alsa_mixer-test_write_invalid_LCALTA_57 pass
2452 21:52:50.269198 alsa_mixer-test_event_missing_LCALTA_57 pass
2453 21:52:50.274730 alsa_mixer-test_event_spurious_LCALTA_57 pass
2454 21:52:50.275170 alsa_mixer-test_get_value_LCALTA_56 pass
2455 21:52:50.280402 alsa_mixer-test_name_LCALTA_56 pass
2456 21:52:50.285920 alsa_mixer-test_write_default_LCALTA_56 pass
2457 21:52:50.286376 alsa_mixer-test_write_valid_LCALTA_56 pass
2458 21:52:50.291380 alsa_mixer-test_write_invalid_LCALTA_56 pass
2459 21:52:50.296977 alsa_mixer-test_event_missing_LCALTA_56 pass
2460 21:52:50.302453 alsa_mixer-test_event_spurious_LCALTA_56 pass
2461 21:52:50.302885 alsa_mixer-test_get_value_LCALTA_55 pass
2462 21:52:50.308039 alsa_mixer-test_name_LCALTA_55 pass
2463 21:52:50.313601 alsa_mixer-test_write_default_LCALTA_55 pass
2464 21:52:50.314047 alsa_mixer-test_write_valid_LCALTA_55 pass
2465 21:52:50.319102 alsa_mixer-test_write_invalid_LCALTA_55 pass
2466 21:52:50.324727 alsa_mixer-test_event_missing_LCALTA_55 pass
2467 21:52:50.325169 alsa_mixer-test_event_spurious_LCALTA_55 pass
2468 21:52:50.330231 alsa_mixer-test_get_value_LCALTA_54 pass
2469 21:52:50.335773 alsa_mixer-test_name_LCALTA_54 pass
2470 21:52:50.336257 alsa_mixer-test_write_default_LCALTA_54 pass
2471 21:52:50.341309 alsa_mixer-test_write_valid_LCALTA_54 pass
2472 21:52:50.346989 alsa_mixer-test_write_invalid_LCALTA_54 pass
2473 21:52:50.347422 alsa_mixer-test_event_missing_LCALTA_54 pass
2474 21:52:50.352392 alsa_mixer-test_event_spurious_LCALTA_54 pass
2475 21:52:50.357952 alsa_mixer-test_get_value_LCALTA_53 pass
2476 21:52:50.358385 alsa_mixer-test_name_LCALTA_53 pass
2477 21:52:50.363476 alsa_mixer-test_write_default_LCALTA_53 pass
2478 21:52:50.369051 alsa_mixer-test_write_valid_LCALTA_53 pass
2479 21:52:50.374599 alsa_mixer-test_write_invalid_LCALTA_53 pass
2480 21:52:50.375022 alsa_mixer-test_event_missing_LCALTA_53 pass
2481 21:52:50.380115 alsa_mixer-test_event_spurious_LCALTA_53 pass
2482 21:52:50.385727 alsa_mixer-test_get_value_LCALTA_52 pass
2483 21:52:50.386273 alsa_mixer-test_name_LCALTA_52 pass
2484 21:52:50.391239 alsa_mixer-test_write_default_LCALTA_52 pass
2485 21:52:50.396795 alsa_mixer-test_write_valid_LCALTA_52 pass
2486 21:52:50.397388 alsa_mixer-test_write_invalid_LCALTA_52 pass
2487 21:52:50.402287 alsa_mixer-test_event_missing_LCALTA_52 pass
2488 21:52:50.407946 alsa_mixer-test_event_spurious_LCALTA_52 pass
2489 21:52:50.408521 alsa_mixer-test_get_value_LCALTA_51 pass
2490 21:52:50.413381 alsa_mixer-test_name_LCALTA_51 pass
2491 21:52:50.418993 alsa_mixer-test_write_default_LCALTA_51 pass
2492 21:52:50.419522 alsa_mixer-test_write_valid_LCALTA_51 pass
2493 21:52:50.424476 alsa_mixer-test_write_invalid_LCALTA_51 pass
2494 21:52:50.429995 alsa_mixer-test_event_missing_LCALTA_51 pass
2495 21:52:50.435613 alsa_mixer-test_event_spurious_LCALTA_51 pass
2496 21:52:50.436183 alsa_mixer-test_get_value_LCALTA_50 pass
2497 21:52:50.441136 alsa_mixer-test_name_LCALTA_50 pass
2498 21:52:50.446713 alsa_mixer-test_write_default_LCALTA_50 pass
2499 21:52:50.447235 alsa_mixer-test_write_valid_LCALTA_50 pass
2500 21:52:50.452269 alsa_mixer-test_write_invalid_LCALTA_50 pass
2501 21:52:50.457782 alsa_mixer-test_event_missing_LCALTA_50 pass
2502 21:52:50.458303 alsa_mixer-test_event_spurious_LCALTA_50 pass
2503 21:52:50.463348 alsa_mixer-test_get_value_LCALTA_49 pass
2504 21:52:50.468981 alsa_mixer-test_name_LCALTA_49 pass
2505 21:52:50.469510 alsa_mixer-test_write_default_LCALTA_49 pass
2506 21:52:50.474391 alsa_mixer-test_write_valid_LCALTA_49 pass
2507 21:52:50.480007 alsa_mixer-test_write_invalid_LCALTA_49 pass
2508 21:52:50.485473 alsa_mixer-test_event_missing_LCALTA_49 pass
2509 21:52:50.486025 alsa_mixer-test_event_spurious_LCALTA_49 pass
2510 21:52:50.491021 alsa_mixer-test_get_value_LCALTA_48 pass
2511 21:52:50.491556 alsa_mixer-test_name_LCALTA_48 pass
2512 21:52:50.496607 alsa_mixer-test_write_default_LCALTA_48 pass
2513 21:52:50.502162 alsa_mixer-test_write_valid_LCALTA_48 pass
2514 21:52:50.507764 alsa_mixer-test_write_invalid_LCALTA_48 pass
2515 21:52:50.508323 alsa_mixer-test_event_missing_LCALTA_48 pass
2516 21:52:50.513282 alsa_mixer-test_event_spurious_LCALTA_48 pass
2517 21:52:50.518804 alsa_mixer-test_get_value_LCALTA_47 pass
2518 21:52:50.519327 alsa_mixer-test_name_LCALTA_47 pass
2519 21:52:50.524320 alsa_mixer-test_write_default_LCALTA_47 pass
2520 21:52:50.529984 alsa_mixer-test_write_valid_LCALTA_47 pass
2521 21:52:50.530520 alsa_mixer-test_write_invalid_LCALTA_47 pass
2522 21:52:50.535439 alsa_mixer-test_event_missing_LCALTA_47 pass
2523 21:52:50.541025 alsa_mixer-test_event_spurious_LCALTA_47 pass
2524 21:52:50.546529 alsa_mixer-test_get_value_LCALTA_46 pass
2525 21:52:50.547039 alsa_mixer-test_name_LCALTA_46 pass
2526 21:52:50.552110 alsa_mixer-test_write_default_LCALTA_46 pass
2527 21:52:50.557587 alsa_mixer-test_write_valid_LCALTA_46 pass
2528 21:52:50.558141 alsa_mixer-test_write_invalid_LCALTA_46 pass
2529 21:52:50.563137 alsa_mixer-test_event_missing_LCALTA_46 pass
2530 21:52:50.568813 alsa_mixer-test_event_spurious_LCALTA_46 pass
2531 21:52:50.569386 alsa_mixer-test_get_value_LCALTA_45 pass
2532 21:52:50.574280 alsa_mixer-test_name_LCALTA_45 pass
2533 21:52:50.579776 alsa_mixer-test_write_default_LCALTA_45 pass
2534 21:52:50.580331 alsa_mixer-test_write_valid_LCALTA_45 pass
2535 21:52:50.585345 alsa_mixer-test_write_invalid_LCALTA_45 pass
2536 21:52:50.590997 alsa_mixer-test_event_missing_LCALTA_45 pass
2537 21:52:50.591525 alsa_mixer-test_event_spurious_LCALTA_45 pass
2538 21:52:50.596466 alsa_mixer-test_get_value_LCALTA_44 pass
2539 21:52:50.601986 alsa_mixer-test_name_LCALTA_44 pass
2540 21:52:50.602541 alsa_mixer-test_write_default_LCALTA_44 pass
2541 21:52:50.607539 alsa_mixer-test_write_valid_LCALTA_44 pass
2542 21:52:50.613126 alsa_mixer-test_write_invalid_LCALTA_44 pass
2543 21:52:50.618688 alsa_mixer-test_event_missing_LCALTA_44 pass
2544 21:52:50.619265 alsa_mixer-test_event_spurious_LCALTA_44 pass
2545 21:52:50.624260 alsa_mixer-test_get_value_LCALTA_43 pass
2546 21:52:50.629765 alsa_mixer-test_name_LCALTA_43 pass
2547 21:52:50.630306 alsa_mixer-test_write_default_LCALTA_43 pass
2548 21:52:50.635301 alsa_mixer-test_write_valid_LCALTA_43 pass
2549 21:52:50.640827 alsa_mixer-test_write_invalid_LCALTA_43 pass
2550 21:52:50.641370 alsa_mixer-test_event_missing_LCALTA_43 pass
2551 21:52:50.646386 alsa_mixer-test_event_spurious_LCALTA_43 pass
2552 21:52:50.652022 alsa_mixer-test_get_value_LCALTA_42 pass
2553 21:52:50.652562 alsa_mixer-test_name_LCALTA_42 pass
2554 21:52:50.657469 alsa_mixer-test_write_default_LCALTA_42 pass
2555 21:52:50.663025 alsa_mixer-test_write_valid_LCALTA_42 pass
2556 21:52:50.663549 alsa_mixer-test_write_invalid_LCALTA_42 pass
2557 21:52:50.668592 alsa_mixer-test_event_missing_LCALTA_42 pass
2558 21:52:50.674142 alsa_mixer-test_event_spurious_LCALTA_42 pass
2559 21:52:50.679728 alsa_mixer-test_get_value_LCALTA_41 pass
2560 21:52:50.680292 alsa_mixer-test_name_LCALTA_41 pass
2561 21:52:50.685230 alsa_mixer-test_write_default_LCALTA_41 pass
2562 21:52:50.690767 alsa_mixer-test_write_valid_LCALTA_41 pass
2563 21:52:50.691300 alsa_mixer-test_write_invalid_LCALTA_41 pass
2564 21:52:50.696300 alsa_mixer-test_event_missing_LCALTA_41 pass
2565 21:52:50.701841 alsa_mixer-test_event_spurious_LCALTA_41 pass
2566 21:52:50.702366 alsa_mixer-test_get_value_LCALTA_40 pass
2567 21:52:50.707425 alsa_mixer-test_name_LCALTA_40 pass
2568 21:52:50.713910 alsa_mixer-test_write_default_LCALTA_40 pass
2569 21:52:50.714516 alsa_mixer-test_write_valid_LCALTA_40 pass
2570 21:52:50.718544 alsa_mixer-test_write_invalid_LCALTA_40 pass
2571 21:52:50.724035 alsa_mixer-test_event_missing_LCALTA_40 pass
2572 21:52:50.729578 alsa_mixer-test_event_spurious_LCALTA_40 pass
2573 21:52:50.730122 alsa_mixer-test_get_value_LCALTA_39 pass
2574 21:52:50.735126 alsa_mixer-test_name_LCALTA_39 pass
2575 21:52:50.740686 alsa_mixer-test_write_default_LCALTA_39 pass
2576 21:52:50.741232 alsa_mixer-test_write_valid_LCALTA_39 pass
2577 21:52:50.746254 alsa_mixer-test_write_invalid_LCALTA_39 pass
2578 21:52:50.751796 alsa_mixer-test_event_missing_LCALTA_39 pass
2579 21:52:50.752366 alsa_mixer-test_event_spurious_LCALTA_39 pass
2580 21:52:50.757318 alsa_mixer-test_get_value_LCALTA_38 pass
2581 21:52:50.762867 alsa_mixer-test_name_LCALTA_38 pass
2582 21:52:50.763408 alsa_mixer-test_write_default_LCALTA_38 pass
2583 21:52:50.768417 alsa_mixer-test_write_valid_LCALTA_38 pass
2584 21:52:50.774025 alsa_mixer-test_write_invalid_LCALTA_38 pass
2585 21:52:50.774547 alsa_mixer-test_event_missing_LCALTA_38 pass
2586 21:52:50.779510 alsa_mixer-test_event_spurious_LCALTA_38 pass
2587 21:52:50.785116 alsa_mixer-test_get_value_LCALTA_37 pass
2588 21:52:50.785656 alsa_mixer-test_name_LCALTA_37 pass
2589 21:52:50.790601 alsa_mixer-test_write_default_LCALTA_37 pass
2590 21:52:50.796231 alsa_mixer-test_write_valid_LCALTA_37 pass
2591 21:52:50.801689 alsa_mixer-test_write_invalid_LCALTA_37 pass
2592 21:52:50.802228 alsa_mixer-test_event_missing_LCALTA_37 pass
2593 21:52:50.807251 alsa_mixer-test_event_spurious_LCALTA_37 pass
2594 21:52:50.812815 alsa_mixer-test_get_value_LCALTA_36 pass
2595 21:52:50.813370 alsa_mixer-test_name_LCALTA_36 pass
2596 21:52:50.818338 alsa_mixer-test_write_default_LCALTA_36 pass
2597 21:52:50.823938 alsa_mixer-test_write_valid_LCALTA_36 pass
2598 21:52:50.824506 alsa_mixer-test_write_invalid_LCALTA_36 pass
2599 21:52:50.829485 alsa_mixer-test_event_missing_LCALTA_36 pass
2600 21:52:50.835077 alsa_mixer-test_event_spurious_LCALTA_36 pass
2601 21:52:50.835607 alsa_mixer-test_get_value_LCALTA_35 pass
2602 21:52:50.840457 alsa_mixer-test_name_LCALTA_35 pass
2603 21:52:50.846025 alsa_mixer-test_write_default_LCALTA_35 pass
2604 21:52:50.846543 alsa_mixer-test_write_valid_LCALTA_35 pass
2605 21:52:50.851552 alsa_mixer-test_write_invalid_LCALTA_35 pass
2606 21:52:50.857098 alsa_mixer-test_event_missing_LCALTA_35 pass
2607 21:52:50.862629 alsa_mixer-test_event_spurious_LCALTA_35 pass
2608 21:52:50.863142 alsa_mixer-test_get_value_LCALTA_34 pass
2609 21:52:50.868240 alsa_mixer-test_name_LCALTA_34 pass
2610 21:52:50.873715 alsa_mixer-test_write_default_LCALTA_34 pass
2611 21:52:50.874207 alsa_mixer-test_write_valid_LCALTA_34 pass
2612 21:52:50.879269 alsa_mixer-test_write_invalid_LCALTA_34 pass
2613 21:52:50.884826 alsa_mixer-test_event_missing_LCALTA_34 pass
2614 21:52:50.885330 alsa_mixer-test_event_spurious_LCALTA_34 pass
2615 21:52:50.890358 alsa_mixer-test_get_value_LCALTA_33 pass
2616 21:52:50.896015 alsa_mixer-test_name_LCALTA_33 pass
2617 21:52:50.896512 alsa_mixer-test_write_default_LCALTA_33 pass
2618 21:52:50.901465 alsa_mixer-test_write_valid_LCALTA_33 pass
2619 21:52:50.907053 alsa_mixer-test_write_invalid_LCALTA_33 pass
2620 21:52:50.912573 alsa_mixer-test_event_missing_LCALTA_33 pass
2621 21:52:50.913074 alsa_mixer-test_event_spurious_LCALTA_33 pass
2622 21:52:50.918107 alsa_mixer-test_get_value_LCALTA_32 pass
2623 21:52:50.918608 alsa_mixer-test_name_LCALTA_32 pass
2624 21:52:50.923646 alsa_mixer-test_write_default_LCALTA_32 pass
2625 21:52:50.929177 alsa_mixer-test_write_valid_LCALTA_32 pass
2626 21:52:50.934782 alsa_mixer-test_write_invalid_LCALTA_32 pass
2627 21:52:50.935300 alsa_mixer-test_event_missing_LCALTA_32 pass
2628 21:52:50.940334 alsa_mixer-test_event_spurious_LCALTA_32 pass
2629 21:52:50.945823 alsa_mixer-test_get_value_LCALTA_31 pass
2630 21:52:50.946323 alsa_mixer-test_name_LCALTA_31 pass
2631 21:52:50.951372 alsa_mixer-test_write_default_LCALTA_31 pass
2632 21:52:50.957018 alsa_mixer-test_write_valid_LCALTA_31 pass
2633 21:52:50.957508 alsa_mixer-test_write_invalid_LCALTA_31 pass
2634 21:52:50.962473 alsa_mixer-test_event_missing_LCALTA_31 pass
2635 21:52:50.968059 alsa_mixer-test_event_spurious_LCALTA_31 pass
2636 21:52:50.973534 alsa_mixer-test_get_value_LCALTA_30 pass
2637 21:52:50.974016 alsa_mixer-test_name_LCALTA_30 pass
2638 21:52:50.979124 alsa_mixer-test_write_default_LCALTA_30 pass
2639 21:52:50.984765 alsa_mixer-test_write_valid_LCALTA_30 pass
2640 21:52:50.985260 alsa_mixer-test_write_invalid_LCALTA_30 pass
2641 21:52:50.990201 alsa_mixer-test_event_missing_LCALTA_30 pass
2642 21:52:50.995755 alsa_mixer-test_event_spurious_LCALTA_30 pass
2643 21:52:50.996280 alsa_mixer-test_get_value_LCALTA_29 pass
2644 21:52:51.001323 alsa_mixer-test_name_LCALTA_29 pass
2645 21:52:51.006885 alsa_mixer-test_write_default_LCALTA_29 pass
2646 21:52:51.007374 alsa_mixer-test_write_valid_LCALTA_29 pass
2647 21:52:51.012366 alsa_mixer-test_write_invalid_LCALTA_29 pass
2648 21:52:51.017999 alsa_mixer-test_event_missing_LCALTA_29 pass
2649 21:52:51.018486 alsa_mixer-test_event_spurious_LCALTA_29 pass
2650 21:52:51.023480 alsa_mixer-test_get_value_LCALTA_28 pass
2651 21:52:51.029039 alsa_mixer-test_name_LCALTA_28 pass
2652 21:52:51.029531 alsa_mixer-test_write_default_LCALTA_28 pass
2653 21:52:51.034566 alsa_mixer-test_write_valid_LCALTA_28 pass
2654 21:52:51.040116 alsa_mixer-test_write_invalid_LCALTA_28 pass
2655 21:52:51.045659 alsa_mixer-test_event_missing_LCALTA_28 pass
2656 21:52:51.046145 alsa_mixer-test_event_spurious_LCALTA_28 pass
2657 21:52:51.051201 alsa_mixer-test_get_value_LCALTA_27 pass
2658 21:52:51.056791 alsa_mixer-test_name_LCALTA_27 pass
2659 21:52:51.057270 alsa_mixer-test_write_default_LCALTA_27 pass
2660 21:52:51.062310 alsa_mixer-test_write_valid_LCALTA_27 pass
2661 21:52:51.067855 alsa_mixer-test_write_invalid_LCALTA_27 pass
2662 21:52:51.068366 alsa_mixer-test_event_missing_LCALTA_27 pass
2663 21:52:51.073391 alsa_mixer-test_event_spurious_LCALTA_27 pass
2664 21:52:51.078998 alsa_mixer-test_get_value_LCALTA_26 pass
2665 21:52:51.079485 alsa_mixer-test_name_LCALTA_26 pass
2666 21:52:51.084474 alsa_mixer-test_write_default_LCALTA_26 skip
2667 21:52:51.090041 alsa_mixer-test_write_valid_LCALTA_26 skip
2668 21:52:51.090551 alsa_mixer-test_write_invalid_LCALTA_26 skip
2669 21:52:51.095554 alsa_mixer-test_event_missing_LCALTA_26 pass
2670 21:52:51.101132 alsa_mixer-test_event_spurious_LCALTA_26 pass
2671 21:52:51.106742 alsa_mixer-test_get_value_LCALTA_25 pass
2672 21:52:51.107228 alsa_mixer-test_name_LCALTA_25 pass
2673 21:52:51.112258 alsa_mixer-test_write_default_LCALTA_25 pass
2674 21:52:51.117791 alsa_mixer-test_write_valid_LCALTA_25 skip
2675 21:52:51.118283 alsa_mixer-test_write_invalid_LCALTA_25 skip
2676 21:52:51.123287 alsa_mixer-test_event_missing_LCALTA_25 pass
2677 21:52:51.128890 alsa_mixer-test_event_spurious_LCALTA_25 pass
2678 21:52:51.129398 alsa_mixer-test_get_value_LCALTA_24 pass
2679 21:52:51.134408 alsa_mixer-test_name_LCALTA_24 pass
2680 21:52:51.140030 alsa_mixer-test_write_default_LCALTA_24 skip
2681 21:52:51.140553 alsa_mixer-test_write_valid_LCALTA_24 skip
2682 21:52:51.145580 alsa_mixer-test_write_invalid_LCALTA_24 skip
2683 21:52:51.151056 alsa_mixer-test_event_missing_LCALTA_24 pass
2684 21:52:51.156638 alsa_mixer-test_event_spurious_LCALTA_24 pass
2685 21:52:51.157157 alsa_mixer-test_get_value_LCALTA_23 pass
2686 21:52:51.162172 alsa_mixer-test_name_LCALTA_23 pass
2687 21:52:51.167784 alsa_mixer-test_write_default_LCALTA_23 skip
2688 21:52:51.168327 alsa_mixer-test_write_valid_LCALTA_23 skip
2689 21:52:51.173241 alsa_mixer-test_write_invalid_LCALTA_23 skip
2690 21:52:51.178820 alsa_mixer-test_event_missing_LCALTA_23 pass
2691 21:52:51.179346 alsa_mixer-test_event_spurious_LCALTA_23 pass
2692 21:52:51.184339 alsa_mixer-test_get_value_LCALTA_22 pass
2693 21:52:51.190057 alsa_mixer-test_name_LCALTA_22 pass
2694 21:52:51.190473 alsa_mixer-test_write_default_LCALTA_22 pass
2695 21:52:51.195451 alsa_mixer-test_write_valid_LCALTA_22 pass
2696 21:52:51.201005 alsa_mixer-test_write_invalid_LCALTA_22 pass
2697 21:52:51.201575 alsa_mixer-test_event_missing_LCALTA_22 pass
2698 21:52:51.206576 alsa_mixer-test_event_spurious_LCALTA_22 pass
2699 21:52:51.212070 alsa_mixer-test_get_value_LCALTA_21 pass
2700 21:52:51.212663 alsa_mixer-test_name_LCALTA_21 pass
2701 21:52:51.217597 alsa_mixer-test_write_default_LCALTA_21 pass
2702 21:52:51.223176 alsa_mixer-test_write_valid_LCALTA_21 pass
2703 21:52:51.228754 alsa_mixer-test_write_invalid_LCALTA_21 pass
2704 21:52:51.229177 alsa_mixer-test_event_missing_LCALTA_21 pass
2705 21:52:51.234245 alsa_mixer-test_event_spurious_LCALTA_21 pass
2706 21:52:51.239805 alsa_mixer-test_get_value_LCALTA_20 pass
2707 21:52:51.240266 alsa_mixer-test_name_LCALTA_20 pass
2708 21:52:51.245353 alsa_mixer-test_write_default_LCALTA_20 pass
2709 21:52:51.251023 alsa_mixer-test_write_valid_LCALTA_20 pass
2710 21:52:51.251433 alsa_mixer-test_write_invalid_LCALTA_20 pass
2711 21:52:51.256454 alsa_mixer-test_event_missing_LCALTA_20 pass
2712 21:52:51.262025 alsa_mixer-test_event_spurious_LCALTA_20 pass
2713 21:52:51.262599 alsa_mixer-test_get_value_LCALTA_19 pass
2714 21:52:51.267488 alsa_mixer-test_name_LCALTA_19 pass
2715 21:52:51.273055 alsa_mixer-test_write_default_LCALTA_19 pass
2716 21:52:51.273630 alsa_mixer-test_write_valid_LCALTA_19 pass
2717 21:52:51.278618 alsa_mixer-test_write_invalid_LCALTA_19 pass
2718 21:52:51.284179 alsa_mixer-test_event_missing_LCALTA_19 pass
2719 21:52:51.289737 alsa_mixer-test_event_spurious_LCALTA_19 pass
2720 21:52:51.290153 alsa_mixer-test_get_value_LCALTA_18 pass
2721 21:52:51.295248 alsa_mixer-test_name_LCALTA_18 pass
2722 21:52:51.300900 alsa_mixer-test_write_default_LCALTA_18 pass
2723 21:52:51.301323 alsa_mixer-test_write_valid_LCALTA_18 pass
2724 21:52:51.306347 alsa_mixer-test_write_invalid_LCALTA_18 pass
2725 21:52:51.312069 alsa_mixer-test_event_missing_LCALTA_18 pass
2726 21:52:51.312497 alsa_mixer-test_event_spurious_LCALTA_18 pass
2727 21:52:51.317367 alsa_mixer-test_get_value_LCALTA_17 pass
2728 21:52:51.322998 alsa_mixer-test_name_LCALTA_17 pass
2729 21:52:51.323382 alsa_mixer-test_write_default_LCALTA_17 pass
2730 21:52:51.328507 alsa_mixer-test_write_valid_LCALTA_17 pass
2731 21:52:51.334128 alsa_mixer-test_write_invalid_LCALTA_17 pass
2732 21:52:51.339688 alsa_mixer-test_event_missing_LCALTA_17 pass
2733 21:52:51.340142 alsa_mixer-test_event_spurious_LCALTA_17 pass
2734 21:52:51.345224 alsa_mixer-test_get_value_LCALTA_16 pass
2735 21:52:51.345642 alsa_mixer-test_name_LCALTA_16 pass
2736 21:52:51.350829 alsa_mixer-test_write_default_LCALTA_16 pass
2737 21:52:51.356348 alsa_mixer-test_write_valid_LCALTA_16 pass
2738 21:52:51.361833 alsa_mixer-test_write_invalid_LCALTA_16 pass
2739 21:52:51.362265 alsa_mixer-test_event_missing_LCALTA_16 pass
2740 21:52:51.367402 alsa_mixer-test_event_spurious_LCALTA_16 pass
2741 21:52:51.373047 alsa_mixer-test_get_value_LCALTA_15 pass
2742 21:52:51.373457 alsa_mixer-test_name_LCALTA_15 pass
2743 21:52:51.378521 alsa_mixer-test_write_default_LCALTA_15 pass
2744 21:52:51.384136 alsa_mixer-test_write_valid_LCALTA_15 pass
2745 21:52:51.384730 alsa_mixer-test_write_invalid_LCALTA_15 pass
2746 21:52:51.389597 alsa_mixer-test_event_missing_LCALTA_15 pass
2747 21:52:51.395127 alsa_mixer-test_event_spurious_LCALTA_15 pass
2748 21:52:51.400730 alsa_mixer-test_get_value_LCALTA_14 pass
2749 21:52:51.401141 alsa_mixer-test_name_LCALTA_14 pass
2750 21:52:51.406234 alsa_mixer-test_write_default_LCALTA_14 pass
2751 21:52:51.411858 alsa_mixer-test_write_valid_LCALTA_14 pass
2752 21:52:51.412314 alsa_mixer-test_write_invalid_LCALTA_14 pass
2753 21:52:51.417315 alsa_mixer-test_event_missing_LCALTA_14 pass
2754 21:52:51.422932 alsa_mixer-test_event_spurious_LCALTA_14 pass
2755 21:52:51.423524 alsa_mixer-test_get_value_LCALTA_13 pass
2756 21:52:51.428417 alsa_mixer-test_name_LCALTA_13 pass
2757 21:52:51.434094 alsa_mixer-test_write_default_LCALTA_13 pass
2758 21:52:51.434675 alsa_mixer-test_write_valid_LCALTA_13 pass
2759 21:52:51.439556 alsa_mixer-test_write_invalid_LCALTA_13 pass
2760 21:52:51.445077 alsa_mixer-test_event_missing_LCALTA_13 pass
2761 21:52:51.445491 alsa_mixer-test_event_spurious_LCALTA_13 pass
2762 21:52:51.450618 alsa_mixer-test_get_value_LCALTA_12 pass
2763 21:52:51.456201 alsa_mixer-test_name_LCALTA_12 pass
2764 21:52:51.456792 alsa_mixer-test_write_default_LCALTA_12 pass
2765 21:52:51.461684 alsa_mixer-test_write_valid_LCALTA_12 pass
2766 21:52:51.467212 alsa_mixer-test_write_invalid_LCALTA_12 pass
2767 21:52:51.472805 alsa_mixer-test_event_missing_LCALTA_12 pass
2768 21:52:51.473236 alsa_mixer-test_event_spurious_LCALTA_12 pass
2769 21:52:51.478328 alsa_mixer-test_get_value_LCALTA_11 pass
2770 21:52:51.483881 alsa_mixer-test_name_LCALTA_11 pass
2771 21:52:51.484338 alsa_mixer-test_write_default_LCALTA_11 pass
2772 21:52:51.489453 alsa_mixer-test_write_valid_LCALTA_11 pass
2773 21:52:51.495112 alsa_mixer-test_write_invalid_LCALTA_11 pass
2774 21:52:51.495542 alsa_mixer-test_event_missing_LCALTA_11 pass
2775 21:52:51.500502 alsa_mixer-test_event_spurious_LCALTA_11 pass
2776 21:52:51.506047 alsa_mixer-test_get_value_LCALTA_10 pass
2777 21:52:51.506607 alsa_mixer-test_name_LCALTA_10 pass
2778 21:52:51.511591 alsa_mixer-test_write_default_LCALTA_10 pass
2779 21:52:51.517086 alsa_mixer-test_write_valid_LCALTA_10 pass
2780 21:52:51.517619 alsa_mixer-test_write_invalid_LCALTA_10 pass
2781 21:52:51.522668 alsa_mixer-test_event_missing_LCALTA_10 pass
2782 21:52:51.528236 alsa_mixer-test_event_spurious_LCALTA_10 pass
2783 21:52:51.533781 alsa_mixer-test_get_value_LCALTA_9 pass
2784 21:52:51.534284 alsa_mixer-test_name_LCALTA_9 pass
2785 21:52:51.539397 alsa_mixer-test_write_default_LCALTA_9 pass
2786 21:52:51.544793 alsa_mixer-test_write_valid_LCALTA_9 pass
2787 21:52:51.545312 alsa_mixer-test_write_invalid_LCALTA_9 pass
2788 21:52:51.550353 alsa_mixer-test_event_missing_LCALTA_9 pass
2789 21:52:51.556011 alsa_mixer-test_event_spurious_LCALTA_9 pass
2790 21:52:51.556528 alsa_mixer-test_get_value_LCALTA_8 pass
2791 21:52:51.561411 alsa_mixer-test_name_LCALTA_8 pass
2792 21:52:51.567018 alsa_mixer-test_write_default_LCALTA_8 pass
2793 21:52:51.567535 alsa_mixer-test_write_valid_LCALTA_8 pass
2794 21:52:51.572538 alsa_mixer-test_write_invalid_LCALTA_8 pass
2795 21:52:51.578267 alsa_mixer-test_event_missing_LCALTA_8 pass
2796 21:52:51.578783 alsa_mixer-test_event_spurious_LCALTA_8 pass
2797 21:52:51.583628 alsa_mixer-test_get_value_LCALTA_7 pass
2798 21:52:51.589141 alsa_mixer-test_name_LCALTA_7 pass
2799 21:52:51.589658 alsa_mixer-test_write_default_LCALTA_7 pass
2800 21:52:51.594722 alsa_mixer-test_write_valid_LCALTA_7 pass
2801 21:52:51.600276 alsa_mixer-test_write_invalid_LCALTA_7 pass
2802 21:52:51.600790 alsa_mixer-test_event_missing_LCALTA_7 pass
2803 21:52:51.605797 alsa_mixer-test_event_spurious_LCALTA_7 pass
2804 21:52:51.611350 alsa_mixer-test_get_value_LCALTA_6 pass
2805 21:52:51.611860 alsa_mixer-test_name_LCALTA_6 pass
2806 21:52:51.617005 alsa_mixer-test_write_default_LCALTA_6 pass
2807 21:52:51.622420 alsa_mixer-test_write_valid_LCALTA_6 pass
2808 21:52:51.622933 alsa_mixer-test_write_invalid_LCALTA_6 pass
2809 21:52:51.628017 alsa_mixer-test_event_missing_LCALTA_6 pass
2810 21:52:51.633525 alsa_mixer-test_event_spurious_LCALTA_6 pass
2811 21:52:51.634038 alsa_mixer-test_get_value_LCALTA_5 pass
2812 21:52:51.639058 alsa_mixer-test_name_LCALTA_5 pass
2813 21:52:51.644724 alsa_mixer-test_write_default_LCALTA_5 pass
2814 21:52:51.645238 alsa_mixer-test_write_valid_LCALTA_5 pass
2815 21:52:51.650171 alsa_mixer-test_write_invalid_LCALTA_5 pass
2816 21:52:51.655758 alsa_mixer-test_event_missing_LCALTA_5 pass
2817 21:52:51.656305 alsa_mixer-test_event_spurious_LCALTA_5 pass
2818 21:52:51.661251 alsa_mixer-test_get_value_LCALTA_4 pass
2819 21:52:51.666869 alsa_mixer-test_name_LCALTA_4 pass
2820 21:52:51.667372 alsa_mixer-test_write_default_LCALTA_4 pass
2821 21:52:51.672365 alsa_mixer-test_write_valid_LCALTA_4 pass
2822 21:52:51.677997 alsa_mixer-test_write_invalid_LCALTA_4 pass
2823 21:52:51.678509 alsa_mixer-test_event_missing_LCALTA_4 pass
2824 21:52:51.683491 alsa_mixer-test_event_spurious_LCALTA_4 pass
2825 21:52:51.688997 alsa_mixer-test_get_value_LCALTA_3 pass
2826 21:52:51.689517 alsa_mixer-test_name_LCALTA_3 pass
2827 21:52:51.694517 alsa_mixer-test_write_default_LCALTA_3 pass
2828 21:52:51.700157 alsa_mixer-test_write_valid_LCALTA_3 pass
2829 21:52:51.700677 alsa_mixer-test_write_invalid_LCALTA_3 pass
2830 21:52:51.705669 alsa_mixer-test_event_missing_LCALTA_3 pass
2831 21:52:51.711229 alsa_mixer-test_event_spurious_LCALTA_3 pass
2832 21:52:51.711732 alsa_mixer-test_get_value_LCALTA_2 pass
2833 21:52:51.716854 alsa_mixer-test_name_LCALTA_2 pass
2834 21:52:51.722283 alsa_mixer-test_write_default_LCALTA_2 pass
2835 21:52:51.722790 alsa_mixer-test_write_valid_LCALTA_2 pass
2836 21:52:51.727885 alsa_mixer-test_write_invalid_LCALTA_2 pass
2837 21:52:51.733397 alsa_mixer-test_event_missing_LCALTA_2 pass
2838 21:52:51.739043 alsa_mixer-test_event_spurious_LCALTA_2 pass
2839 21:52:51.739548 alsa_mixer-test_get_value_LCALTA_1 pass
2840 21:52:51.744484 alsa_mixer-test_name_LCALTA_1 pass
2841 21:52:51.745001 alsa_mixer-test_write_default_LCALTA_1 pass
2842 21:52:51.750020 alsa_mixer-test_write_valid_LCALTA_1 pass
2843 21:52:51.755588 alsa_mixer-test_write_invalid_LCALTA_1 pass
2844 21:52:51.761091 alsa_mixer-test_event_missing_LCALTA_1 pass
2845 21:52:51.761606 alsa_mixer-test_event_spurious_LCALTA_1 pass
2846 21:52:51.766635 alsa_mixer-test_get_value_LCALTA_0 pass
2847 21:52:51.767140 alsa_mixer-test_name_LCALTA_0 pass
2848 21:52:51.772242 alsa_mixer-test_write_default_LCALTA_0 pass
2849 21:52:51.777764 alsa_mixer-test_write_valid_LCALTA_0 pass
2850 21:52:51.783320 alsa_mixer-test_write_invalid_LCALTA_0 pass
2851 21:52:51.783833 alsa_mixer-test_event_missing_LCALTA_0 pass
2852 21:52:51.788827 alsa_mixer-test_event_spurious_LCALTA_0 pass
2853 21:52:51.789338 alsa_mixer-test pass
2854 21:52:51.794393 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2855 21:52:51.800063 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2856 21:52:51.805482 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2857 21:52:51.811012 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2858 21:52:51.811526 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2859 21:52:51.816564 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2860 21:52:51.822101 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2861 21:52:51.827673 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2862 21:52:51.833270 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2863 21:52:51.838776 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2864 21:52:51.839302 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2865 21:52:51.844313 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2866 21:52:51.849883 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2867 21:52:51.855433 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2868 21:52:51.861033 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2869 21:52:51.866479 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2870 21:52:51.866992 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2871 21:52:51.872065 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2872 21:52:51.877612 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2873 21:52:51.883165 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2874 21:52:51.888663 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2875 21:52:51.894344 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2876 21:52:51.894872 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2877 21:52:51.899889 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2878 21:52:51.905406 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2879 21:52:51.910902 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2880 21:52:51.916500 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2881 21:52:51.922094 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2882 21:52:51.922624 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2883 21:52:51.927564 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2884 21:52:51.933166 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2885 21:52:51.938642 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2886 21:52:51.944229 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2887 21:52:51.949718 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2888 21:52:51.955291 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2889 21:52:51.955817 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2890 21:52:51.960817 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2891 21:52:51.966334 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2892 21:52:51.971912 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2893 21:52:51.977365 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2894 21:52:51.982986 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2895 21:52:51.983502 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2896 21:52:51.988458 alsa_pcm-test pass
2897 21:52:51.994044 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2898 21:52:52.005072 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2899 21:52:52.012068 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2900 21:52:52.021725 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2901 21:52:52.027292 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2902 21:52:52.032734 alsa_test-pcmtest-driver pass
2903 21:52:53.039404 + ../../utils/send-to-lava.sh ./output/result.txt
2904 21:52:53.090078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2905 21:52:53.091081 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2907 21:52:53.140892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2908 21:52:53.141670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2910 21:52:53.189529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2911 21:52:53.190569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2913 21:52:53.241827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2914 21:52:53.242751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2916 21:52:53.284449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2917 21:52:53.285233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2919 21:52:53.336209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2920 21:52:53.337090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2922 21:52:53.383706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2923 21:52:53.384668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2925 21:52:53.439719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2926 21:52:53.440631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2928 21:52:53.490138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2929 21:52:53.491042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2931 21:52:53.541091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2932 21:52:53.541983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2934 21:52:53.593226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2935 21:52:53.594133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2937 21:52:53.645472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2938 21:52:53.646356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2940 21:52:53.695011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2941 21:52:53.695959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2943 21:52:53.742037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2944 21:52:53.742988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2946 21:52:53.791505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2947 21:52:53.792402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2949 21:52:53.846373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2950 21:52:53.847253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2952 21:52:53.889659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2953 21:52:53.890473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2955 21:52:53.945165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2956 21:52:53.945933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2958 21:52:53.995511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2959 21:52:53.996307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2961 21:52:54.046626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2962 21:52:54.047408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2964 21:52:54.103755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2965 21:52:54.104597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2967 21:52:54.148026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2968 21:52:54.148808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2970 21:52:54.189856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2971 21:52:54.190629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2973 21:52:54.233097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2974 21:52:54.233877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2976 21:52:54.280433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2977 21:52:54.281212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2979 21:52:54.327829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2980 21:52:54.328684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2982 21:52:54.391722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2983 21:52:54.392536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
2985 21:52:54.442500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
2986 21:52:54.443290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
2988 21:52:54.500493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
2989 21:52:54.501291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
2991 21:52:54.542554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
2992 21:52:54.543335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
2994 21:52:54.599039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
2995 21:52:54.599852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
2997 21:52:54.654317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
2998 21:52:54.655105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3000 21:52:54.703658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3001 21:52:54.704489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3003 21:52:54.755565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3004 21:52:54.756402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3006 21:52:54.815193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3007 21:52:54.816015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3009 21:52:54.868721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3010 21:52:54.869538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3012 21:52:54.927232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3013 21:52:54.928073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3015 21:52:54.976603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3016 21:52:54.977403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3018 21:52:55.030238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3019 21:52:55.031018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3021 21:52:55.091124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3022 21:52:55.091911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3024 21:52:55.135755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3025 21:52:55.136580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3027 21:52:55.179603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3028 21:52:55.180412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3030 21:52:55.233958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3031 21:52:55.234757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3033 21:52:55.288748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3034 21:52:55.289564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3036 21:52:55.331174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3037 21:52:55.331951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3039 21:52:55.381094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3040 21:52:55.381842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3042 21:52:55.433371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3043 21:52:55.434038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3045 21:52:55.486808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3046 21:52:55.487555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3048 21:52:55.545122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3049 21:52:55.545764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3051 21:52:55.599692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3052 21:52:55.600345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3054 21:52:55.647662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3055 21:52:55.648303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3057 21:52:55.694777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3058 21:52:55.695375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3060 21:52:55.747167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3061 21:52:55.747773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3063 21:52:55.802984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3064 21:52:55.803592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3066 21:52:55.854432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3067 21:52:55.855076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3069 21:52:55.911005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3070 21:52:55.911647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3072 21:52:55.969412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3073 21:52:55.970056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3075 21:52:56.016925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3076 21:52:56.017562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3078 21:52:56.066436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3079 21:52:56.067053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3081 21:52:56.131255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3082 21:52:56.131899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3084 21:52:56.174925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3085 21:52:56.175532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3087 21:52:56.222212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3088 21:52:56.222836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3090 21:52:56.277214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3091 21:52:56.277849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3093 21:52:56.333383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3094 21:52:56.334028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3096 21:52:56.384333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3097 21:52:56.384949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3099 21:52:56.441002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3100 21:52:56.441597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3102 21:52:56.493410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3103 21:52:56.494026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3105 21:52:56.545183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3106 21:52:56.545793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3108 21:52:56.598078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3109 21:52:56.598697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3111 21:52:56.643758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3112 21:52:56.644397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3114 21:52:56.693780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3115 21:52:56.694693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3117 21:52:56.753983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3118 21:52:56.754882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3120 21:52:56.805284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3121 21:52:56.806201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3123 21:52:56.858446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3124 21:52:56.859373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3126 21:52:56.910831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3127 21:52:56.911747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3129 21:52:56.955923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3130 21:52:56.956920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3132 21:52:57.013139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3133 21:52:57.014069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3135 21:52:57.066261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3136 21:52:57.067177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3138 21:52:57.124817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3139 21:52:57.125717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3141 21:52:57.174640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3142 21:52:57.175511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3144 21:52:57.228673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3145 21:52:57.229563 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3147 21:52:57.273083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3148 21:52:57.273973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3150 21:52:57.336254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3151 21:52:57.337156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3153 21:52:57.392053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3154 21:52:57.392959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3156 21:52:57.450402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3157 21:52:57.451286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3159 21:52:57.508005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3160 21:52:57.508813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3162 21:52:57.555346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3163 21:52:57.556194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3165 21:52:57.605719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3166 21:52:57.606604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3168 21:52:57.661089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3169 21:52:57.661980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3171 21:52:57.712456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3172 21:52:57.713346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3174 21:52:57.763898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3175 21:52:57.764564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3177 21:52:57.807398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3178 21:52:57.808021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3180 21:52:57.868007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3181 21:52:57.868633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3183 21:52:57.917196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3184 21:52:57.917795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3186 21:52:57.971454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3187 21:52:57.972117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3189 21:52:58.019118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3190 21:52:58.020052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3192 21:52:58.088218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3193 21:52:58.089115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3195 21:52:58.140746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3196 21:52:58.141587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3198 21:52:58.186849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3199 21:52:58.187646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3201 21:52:58.230156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3202 21:52:58.230925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3204 21:52:58.280813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3205 21:52:58.281558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3207 21:52:58.334196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3208 21:52:58.334947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3210 21:52:58.394871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3211 21:52:58.395692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3213 21:52:58.442136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3214 21:52:58.442960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3216 21:52:58.491897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3217 21:52:58.492754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3219 21:52:58.542881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3220 21:52:58.543708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3222 21:52:58.595614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3223 21:52:58.596414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3225 21:52:58.644407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3226 21:52:58.645208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3228 21:52:58.704488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3229 21:52:58.705429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3231 21:52:58.761510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3232 21:52:58.762340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3234 21:52:58.806333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3235 21:52:58.807094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3237 21:52:58.861860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3238 21:52:58.862443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3240 21:52:58.913575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3241 21:52:58.914186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3243 21:52:58.970743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3244 21:52:58.971374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3246 21:52:59.023972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3247 21:52:59.024628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3249 21:52:59.080365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3250 21:52:59.081017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3252 21:52:59.127835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3253 21:52:59.128536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3255 21:52:59.171694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3256 21:52:59.172348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3258 21:52:59.213696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3259 21:52:59.214325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3261 21:52:59.261601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3262 21:52:59.262225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3264 21:52:59.302962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3265 21:52:59.303577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3267 21:52:59.356441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3268 21:52:59.357063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3270 21:52:59.399525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3271 21:52:59.400163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3273 21:52:59.447975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3274 21:52:59.448600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3276 21:52:59.496404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3277 21:52:59.497015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3279 21:52:59.539976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3280 21:52:59.540600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3282 21:52:59.584341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3283 21:52:59.584977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3285 21:52:59.631643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3286 21:52:59.632266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3288 21:52:59.675450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3289 21:52:59.676077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3291 21:52:59.725540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3292 21:52:59.726168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3294 21:52:59.776206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3295 21:52:59.776812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3297 21:52:59.820085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3298 21:52:59.820695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3300 21:52:59.864550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3301 21:52:59.865184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3303 21:52:59.915716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3304 21:52:59.916360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3306 21:52:59.962313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3307 21:52:59.962937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3309 21:53:00.005320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3310 21:53:00.005957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3312 21:53:00.054602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3313 21:53:00.055241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3315 21:53:00.096811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3316 21:53:00.097800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3318 21:53:00.142000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3319 21:53:00.142982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3321 21:53:00.183223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3322 21:53:00.184175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3324 21:53:00.231178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3325 21:53:00.232111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3327 21:53:00.278823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3328 21:53:00.279707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3330 21:53:00.331933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3331 21:53:00.332584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3333 21:53:00.379626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3334 21:53:00.380286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3336 21:53:00.429082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3337 21:53:00.429775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3339 21:53:00.484545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3340 21:53:00.485267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3342 21:53:00.540606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3343 21:53:00.541444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3345 21:53:00.592207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3346 21:53:00.592978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3348 21:53:00.640605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3349 21:53:00.641393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3351 21:53:00.687342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3352 21:53:00.688172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3354 21:53:00.734966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3355 21:53:00.735757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3357 21:53:00.789934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3358 21:53:00.790720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3360 21:53:00.839702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3361 21:53:00.840539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3363 21:53:00.885832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3364 21:53:00.886531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3366 21:53:00.943944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3367 21:53:00.945822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3369 21:53:00.993587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3370 21:53:00.996052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3372 21:53:01.045907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3373 21:53:01.048085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3375 21:53:01.090084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3376 21:53:01.091019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3378 21:53:01.134289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3379 21:53:01.135188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3381 21:53:01.188475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3382 21:53:01.189318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3384 21:53:01.232013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3385 21:53:01.232865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3387 21:53:01.280357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3388 21:53:01.281367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3390 21:53:01.337297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3391 21:53:01.338138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3393 21:53:01.387516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3394 21:53:01.388507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3396 21:53:01.440377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3397 21:53:01.441214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3399 21:53:01.484904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3400 21:53:01.485719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3402 21:53:01.539329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3403 21:53:01.540208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3405 21:53:01.596606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3406 21:53:01.597730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3408 21:53:01.646690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3409 21:53:01.647357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3411 21:53:01.696718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3412 21:53:01.697732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3414 21:53:01.755808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3415 21:53:01.756697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3417 21:53:01.800897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3418 21:53:01.801914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3420 21:53:01.858735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3421 21:53:01.859655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3423 21:53:01.908465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3424 21:53:01.909293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3426 21:53:01.960822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3427 21:53:01.961763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3429 21:53:02.009175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3430 21:53:02.010045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3432 21:53:02.062697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3433 21:53:02.063632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3435 21:53:02.120113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3436 21:53:02.120991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3438 21:53:02.169324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3439 21:53:02.169949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3441 21:53:02.211857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3442 21:53:02.212466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3444 21:53:02.263416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3445 21:53:02.264047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3447 21:53:02.310854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3448 21:53:02.311493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3450 21:53:02.362039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3451 21:53:02.362874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3453 21:53:02.409900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3454 21:53:02.410498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3456 21:53:02.465546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3457 21:53:02.466401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3459 21:53:02.521134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3460 21:53:02.521731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3462 21:53:02.578163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3463 21:53:02.578852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3465 21:53:02.636029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3466 21:53:02.636674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3468 21:53:02.684322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3469 21:53:02.684914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3471 21:53:02.727814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3472 21:53:02.728417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3474 21:53:02.779520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3475 21:53:02.780472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3477 21:53:02.830824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3478 21:53:02.831457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3480 21:53:02.880697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3481 21:53:02.881307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3483 21:53:02.933192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3484 21:53:02.934068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3486 21:53:02.981725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3487 21:53:02.982524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3489 21:53:03.035127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3490 21:53:03.035719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3492 21:53:03.076843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3493 21:53:03.077425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3495 21:53:03.123176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3496 21:53:03.123794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3498 21:53:03.170431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3499 21:53:03.171357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3501 21:53:03.223876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3502 21:53:03.224799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3504 21:53:03.272313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3505 21:53:03.273208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3507 21:53:03.326039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3508 21:53:03.326744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3510 21:53:03.373867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3511 21:53:03.374559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3513 21:53:03.425865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3514 21:53:03.426515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3516 21:53:03.471732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3517 21:53:03.472447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3519 21:53:03.517175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3520 21:53:03.517810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3522 21:53:03.569334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3523 21:53:03.569968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3525 21:53:03.634215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3526 21:53:03.634811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3528 21:53:03.683340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3529 21:53:03.683933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3531 21:53:03.746871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3532 21:53:03.747478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3534 21:53:03.801473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3535 21:53:03.802461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3537 21:53:03.863858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3538 21:53:03.864604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3540 21:53:03.924394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3541 21:53:03.924998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3543 21:53:03.976032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3544 21:53:03.976678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3546 21:53:04.027179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3547 21:53:04.027776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3549 21:53:04.082456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3550 21:53:04.083068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3552 21:53:04.135646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3553 21:53:04.136289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3555 21:53:04.177461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3556 21:53:04.178088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3558 21:53:04.227584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3559 21:53:04.228259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3561 21:53:04.281126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3562 21:53:04.281795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3564 21:53:04.334924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3565 21:53:04.335582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3567 21:53:04.387223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3568 21:53:04.387868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3570 21:53:04.441517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3571 21:53:04.442107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3573 21:53:04.491816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3574 21:53:04.492440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3576 21:53:04.550235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3577 21:53:04.550859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3579 21:53:04.603162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3580 21:53:04.603855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3582 21:53:04.647295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3583 21:53:04.648004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3585 21:53:04.704749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3586 21:53:04.705475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3588 21:53:04.749806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3589 21:53:04.750440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3591 21:53:04.792292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3592 21:53:04.792922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3594 21:53:04.844905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3595 21:53:04.845559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3597 21:53:04.889442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3598 21:53:04.890076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3600 21:53:04.933761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3601 21:53:04.934670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3603 21:53:04.990178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3604 21:53:04.991036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3606 21:53:05.034943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3607 21:53:05.035773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3609 21:53:05.095962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3610 21:53:05.096626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3612 21:53:05.150277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3613 21:53:05.150914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3615 21:53:05.210116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3616 21:53:05.210779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3618 21:53:05.264191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3619 21:53:05.264832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3621 21:53:05.318262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3622 21:53:05.318901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3624 21:53:05.368484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3625 21:53:05.369511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3627 21:53:05.423225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3628 21:53:05.423880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3630 21:53:05.487555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3631 21:53:05.488189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3633 21:53:05.544342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3634 21:53:05.544985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3636 21:53:05.598475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3637 21:53:05.599271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3639 21:53:05.643648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3640 21:53:05.644316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3642 21:53:05.700305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3643 21:53:05.700919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3645 21:53:05.745467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3646 21:53:05.746075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3648 21:53:05.806968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3649 21:53:05.807561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3651 21:53:05.859029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3652 21:53:05.859872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3654 21:53:05.913706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3655 21:53:05.914540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3657 21:53:05.972066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3658 21:53:05.972938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3660 21:53:06.029654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3661 21:53:06.030265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3663 21:53:06.074488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3664 21:53:06.075316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3666 21:53:06.131265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3667 21:53:06.132098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3669 21:53:06.188848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3670 21:53:06.189723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3672 21:53:06.245943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3673 21:53:06.246635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3675 21:53:06.291610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3676 21:53:06.292264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3678 21:53:06.341393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3679 21:53:06.342215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3681 21:53:06.390014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3682 21:53:06.390821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3684 21:53:06.446969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3685 21:53:06.447577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3687 21:53:06.496303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3688 21:53:06.497171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3690 21:53:06.542757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3691 21:53:06.543384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3693 21:53:06.595889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3694 21:53:06.596755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3696 21:53:06.652308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3697 21:53:06.653146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3699 21:53:06.703481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3700 21:53:06.704339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3702 21:53:06.753017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3703 21:53:06.753827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3705 21:53:06.804320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3706 21:53:06.805122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3708 21:53:06.848331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3709 21:53:06.849134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3711 21:53:06.898557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3712 21:53:06.899372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3714 21:53:06.943529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3715 21:53:06.944150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3717 21:53:06.992477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3718 21:53:06.993314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3720 21:53:07.041305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3721 21:53:07.042199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3723 21:53:07.100548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3724 21:53:07.101452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3726 21:53:07.144530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3727 21:53:07.145290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3729 21:53:07.202349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3730 21:53:07.203220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3732 21:53:07.255512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3733 21:53:07.256384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3735 21:53:07.304267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3736 21:53:07.305088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3738 21:53:07.355739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3739 21:53:07.356596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3741 21:53:07.399717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3742 21:53:07.400562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3744 21:53:07.460001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3745 21:53:07.460627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3747 21:53:07.511297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3748 21:53:07.511958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3750 21:53:07.562344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3751 21:53:07.563003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3753 21:53:07.619297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3754 21:53:07.619949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3756 21:53:07.673196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3757 21:53:07.673826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3759 21:53:07.720458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3760 21:53:07.721086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3762 21:53:07.770334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3763 21:53:07.770938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3765 21:53:07.828999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3766 21:53:07.829915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3768 21:53:07.879888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3769 21:53:07.881035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3771 21:53:07.928719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3772 21:53:07.929586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3774 21:53:07.979884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3775 21:53:07.980528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3777 21:53:08.046548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3778 21:53:08.047406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3780 21:53:08.091710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3781 21:53:08.092528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3783 21:53:08.134552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3784 21:53:08.135328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3786 21:53:08.195405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3787 21:53:08.196188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3789 21:53:08.238770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3790 21:53:08.239540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3792 21:53:08.285468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3793 21:53:08.286283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3795 21:53:08.341265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3796 21:53:08.341933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3798 21:53:08.395737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3799 21:53:08.396454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3801 21:53:08.444682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3802 21:53:08.445609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3804 21:53:08.494927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3805 21:53:08.495691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3807 21:53:08.565888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3808 21:53:08.566738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3810 21:53:08.610158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3811 21:53:08.610950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3813 21:53:08.658964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3814 21:53:08.659776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3816 21:53:08.717745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3817 21:53:08.718410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3819 21:53:08.770533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3820 21:53:08.771315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3822 21:53:08.822758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3823 21:53:08.823453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3825 21:53:08.878178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3826 21:53:08.878985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3828 21:53:08.926546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3829 21:53:08.927241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3831 21:53:08.983806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3832 21:53:08.984543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3834 21:53:09.026890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3835 21:53:09.027631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3837 21:53:09.074586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3838 21:53:09.075543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3840 21:53:09.131752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3841 21:53:09.133465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3843 21:53:09.180268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3844 21:53:09.180920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3846 21:53:09.231286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3847 21:53:09.232152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3849 21:53:09.274958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3850 21:53:09.275770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3852 21:53:09.329781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3853 21:53:09.330687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3855 21:53:09.378791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3856 21:53:09.379842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3858 21:53:09.446913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3859 21:53:09.447662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3861 21:53:09.503007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3862 21:53:09.503667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3864 21:53:09.551835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3865 21:53:09.552593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3867 21:53:09.602111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3868 21:53:09.603010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3870 21:53:09.656820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3871 21:53:09.657831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3873 21:53:09.707945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3874 21:53:09.708669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3876 21:53:09.762826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3877 21:53:09.763483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3879 21:53:09.822071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3880 21:53:09.822746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3882 21:53:09.874603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3883 21:53:09.875233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3885 21:53:09.929841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3886 21:53:09.930470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3888 21:53:09.989392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3889 21:53:09.990046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3891 21:53:10.045441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3892 21:53:10.046300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3894 21:53:10.097255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3895 21:53:10.098126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3897 21:53:10.149080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3898 21:53:10.149955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3900 21:53:10.202978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3901 21:53:10.203852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3903 21:53:10.250815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3904 21:53:10.251669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3906 21:53:10.294459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3907 21:53:10.295086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3909 21:53:10.350734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3910 21:53:10.351381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3912 21:53:10.406724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3913 21:53:10.409557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3915 21:53:10.458655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3916 21:53:10.459310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3918 21:53:10.518299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3919 21:53:10.518966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3921 21:53:10.575267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3922 21:53:10.575924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3924 21:53:10.630905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3925 21:53:10.631584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3927 21:53:10.689390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3928 21:53:10.690036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3930 21:53:10.742248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3931 21:53:10.743315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3933 21:53:10.804250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3934 21:53:10.804936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3936 21:53:10.847842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3937 21:53:10.848550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3939 21:53:10.891031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3940 21:53:10.891712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3942 21:53:10.949464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3943 21:53:10.950102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3945 21:53:10.998326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3946 21:53:10.998959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3948 21:53:11.043136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3949 21:53:11.043777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3951 21:53:11.092026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3952 21:53:11.092673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3954 21:53:11.140915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3955 21:53:11.141556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3957 21:53:11.194487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3958 21:53:11.195129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3960 21:53:11.243014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3961 21:53:11.243648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3963 21:53:11.287707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3964 21:53:11.288604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3966 21:53:11.337303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3967 21:53:11.338148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3969 21:53:11.386527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3970 21:53:11.387371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3972 21:53:11.431164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3973 21:53:11.431767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3975 21:53:11.478430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3976 21:53:11.479010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3978 21:53:11.531251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3979 21:53:11.532115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3981 21:53:11.572923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3982 21:53:11.573593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
3984 21:53:11.624396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
3985 21:53:11.625037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
3987 21:53:11.672142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
3988 21:53:11.672775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
3990 21:53:11.724066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
3991 21:53:11.724676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
3993 21:53:11.775457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
3994 21:53:11.776051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
3996 21:53:11.821447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
3997 21:53:11.822304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
3999 21:53:11.879433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4000 21:53:11.880155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4002 21:53:11.929026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4003 21:53:11.929708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4005 21:53:11.980169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4006 21:53:11.980826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4008 21:53:12.035250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4009 21:53:12.035882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4011 21:53:12.090185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4012 21:53:12.090809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4014 21:53:12.141118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4015 21:53:12.141760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4017 21:53:12.191027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4018 21:53:12.191700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4020 21:53:12.241450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4021 21:53:12.242081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4023 21:53:12.293516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4024 21:53:12.294140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4026 21:53:12.338353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4027 21:53:12.338996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4029 21:53:12.396089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4030 21:53:12.396739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4032 21:53:12.444464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4033 21:53:12.445229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4035 21:53:12.493996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4036 21:53:12.494840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4038 21:53:12.552718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4039 21:53:12.553579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4041 21:53:12.599878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4042 21:53:12.600776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4044 21:53:12.648450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4045 21:53:12.649437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4047 21:53:12.702933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4048 21:53:12.703932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4050 21:53:12.754684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4051 21:53:12.755572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4053 21:53:12.818939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4054 21:53:12.819777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4056 21:53:12.871250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4057 21:53:12.872070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4059 21:53:12.921093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4060 21:53:12.921743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4062 21:53:12.966010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4063 21:53:12.966799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4065 21:53:13.012426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4066 21:53:13.013052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4068 21:53:13.061039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4069 21:53:13.061625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4071 21:53:13.110853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4072 21:53:13.111661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4074 21:53:13.156258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4075 21:53:13.157098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4077 21:53:13.201902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4078 21:53:13.202669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4080 21:53:13.249949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4081 21:53:13.250692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4083 21:53:13.302243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4084 21:53:13.303111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4086 21:53:13.347695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4087 21:53:13.348577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4089 21:53:13.393709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4090 21:53:13.394586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4092 21:53:13.440437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4093 21:53:13.441102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4095 21:53:13.492805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4096 21:53:13.493658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4098 21:53:13.546400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4099 21:53:13.547241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4101 21:53:13.588834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4102 21:53:13.589632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4104 21:53:13.638310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4105 21:53:13.639078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4107 21:53:13.697329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4108 21:53:13.697925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4110 21:53:13.743977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4111 21:53:13.744598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4113 21:53:13.804279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4114 21:53:13.805631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4116 21:53:13.851672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4117 21:53:13.852302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4119 21:53:13.907977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4120 21:53:13.908598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4122 21:53:13.962519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4123 21:53:13.963137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4125 21:53:14.014778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4126 21:53:14.015400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4128 21:53:14.067664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4129 21:53:14.068521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4131 21:53:14.122456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4132 21:53:14.123267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4134 21:53:14.167630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4135 21:53:14.168538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4137 21:53:14.218586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4138 21:53:14.219404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4140 21:53:14.276657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4141 21:53:14.277486 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4143 21:53:14.325294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4144 21:53:14.325867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4146 21:53:14.379130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4147 21:53:14.379929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4149 21:53:14.428536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4150 21:53:14.429343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4152 21:53:14.471860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4153 21:53:14.472734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4155 21:53:14.517992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4156 21:53:14.518820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4158 21:53:14.564617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4159 21:53:14.565426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4161 21:53:14.619787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4162 21:53:14.620651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4164 21:53:14.669894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4165 21:53:14.670720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4167 21:53:14.716576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4168 21:53:14.717396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4170 21:53:14.770768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4171 21:53:14.771610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4173 21:53:14.822793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4174 21:53:14.823637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4176 21:53:14.870870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4177 21:53:14.871692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4179 21:53:14.914430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4180 21:53:14.915209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4182 21:53:14.970785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4183 21:53:14.971538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4185 21:53:15.026804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4186 21:53:15.027652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4188 21:53:15.065932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4190 21:53:15.068982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4191 21:53:15.127131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4192 21:53:15.127767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4194 21:53:15.172042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4195 21:53:15.172974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4197 21:53:15.225617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4198 21:53:15.226252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4200 21:53:15.276528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4201 21:53:15.277144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4203 21:53:15.334271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4204 21:53:15.335120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4206 21:53:15.389925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4207 21:53:15.390747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4209 21:53:15.441702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4210 21:53:15.442533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4212 21:53:15.493153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4213 21:53:15.493784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4215 21:53:15.547047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4216 21:53:15.547638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4218 21:53:15.601045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4219 21:53:15.601645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4221 21:53:15.661959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4222 21:53:15.662587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4224 21:53:15.717653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4225 21:53:15.718234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4227 21:53:15.769134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4228 21:53:15.769758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4230 21:53:15.828537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4231 21:53:15.829159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4233 21:53:15.880550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4234 21:53:15.881164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4236 21:53:15.923602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4237 21:53:15.924243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4239 21:53:15.988532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4240 21:53:15.989150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4242 21:53:16.040087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4243 21:53:16.040690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4245 21:53:16.093634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4246 21:53:16.094278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4248 21:53:16.163792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4249 21:53:16.164456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4251 21:53:16.216427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4252 21:53:16.217101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4254 21:53:16.269090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4255 21:53:16.269734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4257 21:53:16.318638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4258 21:53:16.319244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4260 21:53:16.377320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4261 21:53:16.378256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4263 21:53:16.437091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4264 21:53:16.437988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4266 21:53:16.492995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4267 21:53:16.493878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4269 21:53:16.545158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4270 21:53:16.546018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4272 21:53:16.596222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4273 21:53:16.597042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4275 21:53:16.654041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4276 21:53:16.654876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4278 21:53:16.718906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4279 21:53:16.719796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4281 21:53:16.764569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4282 21:53:16.765559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4284 21:53:16.821690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4285 21:53:16.822569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4287 21:53:16.869805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4288 21:53:16.870615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4290 21:53:16.919144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4291 21:53:16.919969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4293 21:53:16.981082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4294 21:53:16.982136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4296 21:53:17.039474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4297 21:53:17.040294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4299 21:53:17.090298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4300 21:53:17.091005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4302 21:53:17.142783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4303 21:53:17.143682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4305 21:53:17.194981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4306 21:53:17.195780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4308 21:53:17.252374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4309 21:53:17.253235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4311 21:53:17.300796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4312 21:53:17.301418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4314 21:53:17.355837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4315 21:53:17.356782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4317 21:53:17.407970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4318 21:53:17.408637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4320 21:53:17.465866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4321 21:53:17.466486 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4323 21:53:17.519815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4324 21:53:17.520483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4326 21:53:17.580157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4327 21:53:17.580775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4329 21:53:17.628731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4330 21:53:17.629339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4332 21:53:17.677475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4333 21:53:17.678124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4335 21:53:17.726083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4336 21:53:17.726477 + set +x
4337 21:53:17.726931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4339 21:53:17.732740 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 680279_1.6.2.4.5>
4340 21:53:17.733052 <LAVA_TEST_RUNNER EXIT>
4341 21:53:17.733489 Received signal: <ENDRUN> 1_kselftest-alsa 680279_1.6.2.4.5
4342 21:53:17.733745 Ending use of test pattern.
4343 21:53:17.733962 Ending test lava.1_kselftest-alsa (680279_1.6.2.4.5), duration 40.93
4345 21:53:17.734766 ok: lava_test_shell seems to have completed
4346 21:53:17.745931 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
shardfile-alsa: pass
4347 21:53:17.746910 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4348 21:53:17.747232 end: 3 lava-test-retry (duration 00:00:42) [common]
4349 21:53:17.747554 start: 4 finalize (timeout 00:06:04) [common]
4350 21:53:17.747864 start: 4.1 power-off (timeout 00:00:30) [common]
4351 21:53:17.748386 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4352 21:53:17.796489 >> OK - accepted request
4353 21:53:17.798541 Returned 0 in 0 seconds
4354 21:53:17.899578 end: 4.1 power-off (duration 00:00:00) [common]
4356 21:53:17.900779 start: 4.2 read-feedback (timeout 00:06:04) [common]
4357 21:53:17.901565 Listened to connection for namespace 'common' for up to 1s
4358 21:53:18.902456 Finalising connection for namespace 'common'
4359 21:53:18.903191 Disconnecting from shell: Finalise
4360 21:53:18.903786 / #
4361 21:53:19.004966 end: 4.2 read-feedback (duration 00:00:01) [common]
4362 21:53:19.005780 end: 4 finalize (duration 00:00:01) [common]
4363 21:53:19.006509 Cleaning after the job
4364 21:53:19.007123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/ramdisk
4365 21:53:19.010516 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/kernel
4366 21:53:19.022499 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/dtb
4367 21:53:19.023942 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/nfsrootfs
4368 21:53:19.080572 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/680279/tftp-deploy-1zi1cn26/modules
4369 21:53:19.086823 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/680279
4370 21:53:22.254951 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/680279
4371 21:53:22.255576 Job finished correctly