Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 05:13:15.092953 lava-dispatcher, installed at version: 2024.01
2 05:13:15.093244 start: 0 validate
3 05:13:15.093389 Start time: 2024-08-31 05:13:15.093383+00:00 (UTC)
4 05:13:15.093550 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 05:13:15.376209 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 05:13:15.518420 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 05:13:15.660235 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 05:13:15.801200 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 05:13:15.947726 validate duration: 0.85
11 05:13:15.948572 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 05:13:15.948834 start: 1.1 download-retry (timeout 00:10:00) [common]
13 05:13:15.949084 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 05:13:15.949609 Not decompressing ramdisk as can be used compressed.
15 05:13:15.949929 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 05:13:15.950120 saving as /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/ramdisk/initrd.cpio.gz
17 05:13:15.950312 total size: 4775763 (4 MB)
18 05:13:16.229697 progress 0 % (0 MB)
19 05:13:16.649448 progress 5 % (0 MB)
20 05:13:16.787788 progress 10 % (0 MB)
21 05:13:16.791447 progress 15 % (0 MB)
22 05:13:16.926533 progress 20 % (0 MB)
23 05:13:16.929895 progress 25 % (1 MB)
24 05:13:16.933044 progress 30 % (1 MB)
25 05:13:16.936939 progress 35 % (1 MB)
26 05:13:17.065302 progress 40 % (1 MB)
27 05:13:17.068696 progress 45 % (2 MB)
28 05:13:17.072161 progress 50 % (2 MB)
29 05:13:17.076086 progress 55 % (2 MB)
30 05:13:17.079529 progress 60 % (2 MB)
31 05:13:17.082913 progress 65 % (2 MB)
32 05:13:17.086699 progress 70 % (3 MB)
33 05:13:17.089801 progress 75 % (3 MB)
34 05:13:17.204374 progress 80 % (3 MB)
35 05:13:17.207905 progress 85 % (3 MB)
36 05:13:17.211773 progress 90 % (4 MB)
37 05:13:17.215184 progress 95 % (4 MB)
38 05:13:17.218356 progress 100 % (4 MB)
39 05:13:17.218886 4 MB downloaded in 1.27 s (3.59 MB/s)
40 05:13:17.219260 end: 1.1.1 http-download (duration 00:00:01) [common]
42 05:13:17.219850 end: 1.1 download-retry (duration 00:00:01) [common]
43 05:13:17.220047 start: 1.2 download-retry (timeout 00:09:59) [common]
44 05:13:17.220238 start: 1.2.1 http-download (timeout 00:09:59) [common]
45 05:13:17.220640 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 05:13:17.220803 saving as /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/kernel/zImage
47 05:13:17.220943 total size: 11354624 (10 MB)
48 05:13:17.221085 No compression specified
49 05:13:17.361546 progress 0 % (0 MB)
50 05:13:17.369612 progress 5 % (0 MB)
51 05:13:17.377655 progress 10 % (1 MB)
52 05:13:17.385690 progress 15 % (1 MB)
53 05:13:17.394123 progress 20 % (2 MB)
54 05:13:17.401666 progress 25 % (2 MB)
55 05:13:17.504657 progress 30 % (3 MB)
56 05:13:17.513155 progress 35 % (3 MB)
57 05:13:17.521070 progress 40 % (4 MB)
58 05:13:17.529003 progress 45 % (4 MB)
59 05:13:17.537367 progress 50 % (5 MB)
60 05:13:17.643500 progress 55 % (5 MB)
61 05:13:17.651491 progress 60 % (6 MB)
62 05:13:17.659622 progress 65 % (7 MB)
63 05:13:17.667733 progress 70 % (7 MB)
64 05:13:17.675697 progress 75 % (8 MB)
65 05:13:17.778346 progress 80 % (8 MB)
66 05:13:17.787310 progress 85 % (9 MB)
67 05:13:17.795246 progress 90 % (9 MB)
68 05:13:17.804596 progress 95 % (10 MB)
69 05:13:17.921982 progress 100 % (10 MB)
70 05:13:17.922547 10 MB downloaded in 0.70 s (15.43 MB/s)
71 05:13:17.922893 end: 1.2.1 http-download (duration 00:00:01) [common]
73 05:13:17.923443 end: 1.2 download-retry (duration 00:00:01) [common]
74 05:13:17.923644 start: 1.3 download-retry (timeout 00:09:58) [common]
75 05:13:17.923831 start: 1.3.1 http-download (timeout 00:09:58) [common]
76 05:13:17.924199 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 05:13:17.924359 saving as /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/dtb/am335x-boneblack.dtb
78 05:13:17.924494 total size: 70308 (0 MB)
79 05:13:17.924632 No compression specified
80 05:13:18.065861 progress 46 % (0 MB)
81 05:13:18.066610 progress 93 % (0 MB)
82 05:13:18.067219 progress 100 % (0 MB)
83 05:13:18.067488 0 MB downloaded in 0.14 s (0.47 MB/s)
84 05:13:18.067805 end: 1.3.1 http-download (duration 00:00:00) [common]
86 05:13:18.068354 end: 1.3 download-retry (duration 00:00:00) [common]
87 05:13:18.068544 start: 1.4 download-retry (timeout 00:09:58) [common]
88 05:13:18.068737 start: 1.4.1 http-download (timeout 00:09:58) [common]
89 05:13:18.069111 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 05:13:18.069275 saving as /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/nfsrootfs/full.rootfs.tar
91 05:13:18.069414 total size: 117747780 (112 MB)
92 05:13:18.069560 Using unxz to decompress xz
93 05:13:18.210704 progress 0 % (0 MB)
94 05:13:18.574910 progress 5 % (5 MB)
95 05:13:18.951110 progress 10 % (11 MB)
96 05:13:19.318419 progress 15 % (16 MB)
97 05:13:19.682767 progress 20 % (22 MB)
98 05:13:20.031731 progress 25 % (28 MB)
99 05:13:20.414422 progress 30 % (33 MB)
100 05:13:20.786182 progress 35 % (39 MB)
101 05:13:21.061992 progress 40 % (44 MB)
102 05:13:21.377459 progress 45 % (50 MB)
103 05:13:21.690955 progress 50 % (56 MB)
104 05:13:22.074282 progress 55 % (61 MB)
105 05:13:22.436668 progress 60 % (67 MB)
106 05:13:22.797861 progress 65 % (73 MB)
107 05:13:23.168382 progress 70 % (78 MB)
108 05:13:23.539948 progress 75 % (84 MB)
109 05:13:23.896784 progress 80 % (89 MB)
110 05:13:24.254569 progress 85 % (95 MB)
111 05:13:24.618327 progress 90 % (101 MB)
112 05:13:24.967163 progress 95 % (106 MB)
113 05:13:25.363264 progress 100 % (112 MB)
114 05:13:25.365923 112 MB downloaded in 7.30 s (15.39 MB/s)
115 05:13:25.366250 end: 1.4.1 http-download (duration 00:00:07) [common]
117 05:13:25.366704 end: 1.4 download-retry (duration 00:00:07) [common]
118 05:13:25.366859 start: 1.5 download-retry (timeout 00:09:51) [common]
119 05:13:25.367009 start: 1.5.1 http-download (timeout 00:09:51) [common]
120 05:13:25.367308 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 05:13:25.367433 saving as /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/modules/modules.tar
122 05:13:25.367540 total size: 6610728 (6 MB)
123 05:13:25.367651 Using unxz to decompress xz
124 05:13:25.509755 progress 0 % (0 MB)
125 05:13:25.527480 progress 5 % (0 MB)
126 05:13:25.548960 progress 10 % (0 MB)
127 05:13:25.570783 progress 15 % (0 MB)
128 05:13:25.592396 progress 20 % (1 MB)
129 05:13:25.613694 progress 25 % (1 MB)
130 05:13:25.635841 progress 30 % (1 MB)
131 05:13:25.657436 progress 35 % (2 MB)
132 05:13:25.678857 progress 40 % (2 MB)
133 05:13:25.700254 progress 45 % (2 MB)
134 05:13:25.721456 progress 50 % (3 MB)
135 05:13:25.742482 progress 55 % (3 MB)
136 05:13:25.766584 progress 60 % (3 MB)
137 05:13:25.787372 progress 65 % (4 MB)
138 05:13:25.808490 progress 70 % (4 MB)
139 05:13:25.831840 progress 75 % (4 MB)
140 05:13:25.854334 progress 80 % (5 MB)
141 05:13:25.876945 progress 85 % (5 MB)
142 05:13:25.896921 progress 90 % (5 MB)
143 05:13:25.918385 progress 95 % (6 MB)
144 05:13:25.939485 progress 100 % (6 MB)
145 05:13:25.946621 6 MB downloaded in 0.58 s (10.89 MB/s)
146 05:13:25.947012 end: 1.5.1 http-download (duration 00:00:01) [common]
148 05:13:25.947464 end: 1.5 download-retry (duration 00:00:01) [common]
149 05:13:25.947617 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
150 05:13:25.947764 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
151 05:13:31.109829 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/681419/extract-nfsrootfs-0qnqcc8h
152 05:13:31.110217 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
153 05:13:31.110316 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
154 05:13:31.110584 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp
155 05:13:31.110730 makedir: /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin
156 05:13:31.110839 makedir: /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/tests
157 05:13:31.110946 makedir: /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/results
158 05:13:31.111054 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-add-keys
159 05:13:31.111227 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-add-sources
160 05:13:31.111374 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-background-process-start
161 05:13:31.111509 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-background-process-stop
162 05:13:31.111647 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-common-functions
163 05:13:31.111781 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-echo-ipv4
164 05:13:31.111919 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-install-packages
165 05:13:31.112050 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-installed-packages
166 05:13:31.112187 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-os-build
167 05:13:31.112329 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-probe-channel
168 05:13:31.112464 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-probe-ip
169 05:13:31.112602 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-target-ip
170 05:13:31.112732 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-target-mac
171 05:13:31.112870 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-target-storage
172 05:13:31.113005 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-test-case
173 05:13:31.113136 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-test-event
174 05:13:31.113266 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-test-feedback
175 05:13:31.113400 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-test-raise
176 05:13:31.113531 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-test-reference
177 05:13:31.113685 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-test-runner
178 05:13:31.113821 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-test-set
179 05:13:31.113958 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-test-shell
180 05:13:31.114102 Updating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-add-keys (debian)
181 05:13:31.114313 Updating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-add-sources (debian)
182 05:13:31.114496 Updating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-install-packages (debian)
183 05:13:31.114659 Updating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-installed-packages (debian)
184 05:13:31.114818 Updating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/bin/lava-os-build (debian)
185 05:13:31.114953 Creating /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/environment
186 05:13:31.115063 LAVA metadata
187 05:13:31.115129 - LAVA_JOB_ID=681419
188 05:13:31.115184 - LAVA_DISPATCHER_IP=192.168.56.193
189 05:13:31.115298 start: 1.6.2.1 ssh-authorize (timeout 00:09:45) [common]
190 05:13:31.115627 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 05:13:31.115718 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:45) [common]
192 05:13:31.115778 skipped lava-vland-overlay
193 05:13:31.115841 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 05:13:31.115908 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:45) [common]
195 05:13:31.115960 skipped lava-multinode-overlay
196 05:13:31.116021 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 05:13:31.116086 start: 1.6.2.4 test-definition (timeout 00:09:45) [common]
198 05:13:31.116152 Loading test definitions
199 05:13:31.116224 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:45) [common]
200 05:13:31.116281 Using /lava-681419 at stage 0
201 05:13:31.116668 uuid=681419_1.6.2.4.1 testdef=None
202 05:13:31.116754 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 05:13:31.116824 start: 1.6.2.4.2 test-overlay (timeout 00:09:45) [common]
204 05:13:31.117288 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 05:13:31.117502 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:45) [common]
207 05:13:31.118453 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 05:13:31.118688 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:45) [common]
210 05:13:31.119273 runner path: /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/0/tests/0_timesync-off test_uuid 681419_1.6.2.4.1
211 05:13:31.119453 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 05:13:31.119664 start: 1.6.2.4.5 git-repo-action (timeout 00:09:45) [common]
214 05:13:31.119725 Using /lava-681419 at stage 0
215 05:13:31.119822 Fetching tests from https://github.com/kernelci/test-definitions.git
216 05:13:31.119906 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/0/tests/1_kselftest-dt'
217 05:13:33.135168 Running '/usr/bin/git checkout kernelci.org
218 05:13:33.234157 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 05:13:33.234962 uuid=681419_1.6.2.4.5 testdef=None
220 05:13:33.235171 end: 1.6.2.4.5 git-repo-action (duration 00:00:02) [common]
222 05:13:33.235490 start: 1.6.2.4.6 test-overlay (timeout 00:09:43) [common]
223 05:13:33.236245 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 05:13:33.236446 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:43) [common]
226 05:13:33.237420 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 05:13:33.237659 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:43) [common]
229 05:13:33.238665 runner path: /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/0/tests/1_kselftest-dt test_uuid 681419_1.6.2.4.5
230 05:13:33.238750 BOARD='beaglebone-black'
231 05:13:33.238802 BRANCH='mainline'
232 05:13:33.238851 SKIPFILE='/dev/null'
233 05:13:33.238899 SKIP_INSTALL='True'
234 05:13:33.238947 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 05:13:33.238996 TST_CASENAME=''
236 05:13:33.239045 TST_CMDFILES='dt'
237 05:13:33.239212 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 05:13:33.239405 Creating lava-test-runner.conf files
240 05:13:33.239461 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681419/lava-overlay-_e014xmp/lava-681419/0 for stage 0
241 05:13:33.239552 - 0_timesync-off
242 05:13:33.239610 - 1_kselftest-dt
243 05:13:33.239698 end: 1.6.2.4 test-definition (duration 00:00:02) [common]
244 05:13:33.239772 start: 1.6.2.5 compress-overlay (timeout 00:09:43) [common]
245 05:13:41.378888 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 05:13:41.379052 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:35) [common]
247 05:13:41.379128 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 05:13:41.379203 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
249 05:13:41.379278 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
250 05:13:41.505975 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 05:13:41.506267 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
252 05:13:41.506417 extracting modules file /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681419/extract-nfsrootfs-0qnqcc8h
253 05:13:41.788400 extracting modules file /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681419/extract-overlay-ramdisk-x12dlpvu/ramdisk
254 05:13:42.090977 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 05:13:42.091158 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
256 05:13:42.091242 [common] Applying overlay to NFS
257 05:13:42.091298 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681419/compress-overlay-zwg33t0p/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681419/extract-nfsrootfs-0qnqcc8h
258 05:13:43.089747 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 05:13:43.089914 start: 1.6.6 prepare-kernel (timeout 00:09:33) [common]
260 05:13:43.089994 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:33) [common]
261 05:13:43.090071 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 05:13:43.090137 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 05:13:43.090206 start: 1.6.7 configure-preseed-file (timeout 00:09:33) [common]
264 05:13:43.090270 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 05:13:43.090337 start: 1.6.8 compress-ramdisk (timeout 00:09:33) [common]
266 05:13:43.090408 Building ramdisk /var/lib/lava/dispatcher/tmp/681419/extract-overlay-ramdisk-x12dlpvu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681419/extract-overlay-ramdisk-x12dlpvu/ramdisk
267 05:13:43.372077 >> 74798 blocks
268 05:13:45.131989 Adding RAMdisk u-boot header.
269 05:13:45.132190 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681419/extract-overlay-ramdisk-x12dlpvu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681419/extract-overlay-ramdisk-x12dlpvu/ramdisk.cpio.gz.uboot
270 05:13:45.221408 output: Image Name:
271 05:13:45.221686 output: Created: Sat Aug 31 05:13:45 2024
272 05:13:45.221816 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 05:13:45.221927 output: Data Size: 14798868 Bytes = 14452.02 KiB = 14.11 MiB
274 05:13:45.222033 output: Load Address: 00000000
275 05:13:45.222137 output: Entry Point: 00000000
276 05:13:45.222242 output:
277 05:13:45.222458 rename /var/lib/lava/dispatcher/tmp/681419/extract-overlay-ramdisk-x12dlpvu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/ramdisk/ramdisk.cpio.gz.uboot
278 05:13:45.222665 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 05:13:45.222824 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
280 05:13:45.222974 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
281 05:13:45.223108 No LXC device requested
282 05:13:45.223245 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 05:13:45.223391 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
284 05:13:45.223528 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 05:13:45.223649 Checking files for TFTP limit of 4294967296 bytes.
286 05:13:45.224510 end: 1 tftp-deploy (duration 00:00:29) [common]
287 05:13:45.224685 start: 2 uboot-action (timeout 00:05:00) [common]
288 05:13:45.224836 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 05:13:45.224977 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 05:13:45.225118 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 05:13:45.225350 substitutions:
292 05:13:45.225465 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 05:13:45.225591 - {DTB_ADDR}: 0x88000000
294 05:13:45.225706 - {DTB}: 681419/tftp-deploy-2pbc44hq/dtb/am335x-boneblack.dtb
295 05:13:45.225812 - {INITRD}: 681419/tftp-deploy-2pbc44hq/ramdisk/ramdisk.cpio.gz.uboot
296 05:13:45.225916 - {KERNEL_ADDR}: 0x82000000
297 05:13:45.226020 - {KERNEL}: 681419/tftp-deploy-2pbc44hq/kernel/zImage
298 05:13:45.226124 - {LAVA_MAC}: None
299 05:13:45.226248 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/681419/extract-nfsrootfs-0qnqcc8h
300 05:13:45.226358 - {NFS_SERVER_IP}: 192.168.56.193
301 05:13:45.226464 - {PRESEED_CONFIG}: None
302 05:13:45.226568 - {PRESEED_LOCAL}: None
303 05:13:45.226671 - {RAMDISK_ADDR}: 0x83000000
304 05:13:45.226775 - {RAMDISK}: 681419/tftp-deploy-2pbc44hq/ramdisk/ramdisk.cpio.gz.uboot
305 05:13:45.226880 - {ROOT_PART}: None
306 05:13:45.226983 - {ROOT}: None
307 05:13:45.227085 - {SERVER_IP}: 192.168.56.193
308 05:13:45.227188 - {TEE_ADDR}: 0x83000000
309 05:13:45.227290 - {TEE}: None
310 05:13:45.227393 Parsed boot commands:
311 05:13:45.227494 - setenv autoload no
312 05:13:45.227599 - setenv initrd_high 0xffffffff
313 05:13:45.227703 - setenv fdt_high 0xffffffff
314 05:13:45.227809 - dhcp
315 05:13:45.227911 - setenv serverip 192.168.56.193
316 05:13:45.228013 - tftp 0x82000000 681419/tftp-deploy-2pbc44hq/kernel/zImage
317 05:13:45.228115 - tftp 0x83000000 681419/tftp-deploy-2pbc44hq/ramdisk/ramdisk.cpio.gz.uboot
318 05:13:45.228218 - setenv initrd_size ${filesize}
319 05:13:45.228322 - tftp 0x88000000 681419/tftp-deploy-2pbc44hq/dtb/am335x-boneblack.dtb
320 05:13:45.228424 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/681419/extract-nfsrootfs-0qnqcc8h,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 05:13:45.228532 - bootz 0x82000000 0x83000000 0x88000000
322 05:13:45.228674 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 05:13:45.229077 start: 2.3 connect-device (timeout 00:05:00) [common]
325 05:13:45.229195 [common] connect-device Connecting to device using 'telnet conserv3 3002'
326 05:13:45.237588 Setting prompt string to ['lava-test: # ']
327 05:13:45.238347 end: 2.3 connect-device (duration 00:00:00) [common]
328 05:13:45.238582 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 05:13:45.238836 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 05:13:45.239021 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 05:13:45.239411 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
332 05:13:45.256878 >> OK - accepted request
333 05:13:45.258476 Returned 0 in 0 seconds
334 05:13:45.358979 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
336 05:13:45.359781 end: 2.4.1 reset-device (duration 00:00:00) [common]
337 05:13:45.360027 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
338 05:13:45.360241 Setting prompt string to ['Hit any key to stop autoboot']
339 05:13:45.360411 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
340 05:13:45.361050 Trying 192.168.56.22...
341 05:13:45.361196 Connected to conserv3.
342 05:13:45.361309 Escape character is '^]'.
343 05:13:45.361428
344 05:13:45.361544 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
345 05:13:45.361679
346 05:13:54.077189
347 05:13:54.084105 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
348 05:13:54.084304 Trying to boot from MMC1
349 05:13:58.136611
350 05:13:58.143308 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
351 05:13:58.143614 Trying to boot from MMC1
352 05:14:00.829417
353 05:14:00.836454 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
354 05:14:00.836711 Trying to boot from MMC1
355 05:14:01.423456
356 05:14:01.423699
357 05:14:01.429123 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
358 05:14:01.429358
359 05:14:01.429501 CPU : AM335X-GP rev 2.0
360 05:14:01.434112 Model: TI AM335x BeagleBone Black
361 05:14:01.434347 DRAM: 512 MiB
362 05:14:01.514367 Core: 160 devices, 18 uclasses, devicetree: separate
363 05:14:01.528211 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
364 05:14:01.929073 NAND: 0 MiB
365 05:14:01.939083 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
366 05:14:02.059750 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
367 05:14:02.081173 <ethaddr> not set. Validating first E-fuse MAC
368 05:14:02.111547 Net: eth2: ethernet@4a100000, eth3: usb_ether
370 05:14:02.170295 Hit any key to stop autoboot: 2
371 05:14:02.170838 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
372 05:14:02.171102 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
373 05:14:02.171291 Setting prompt string to ['=>']
374 05:14:02.171475 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
375 05:14:02.180082 0
376 05:14:02.180687 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
377 05:14:02.180897 Sending with 10 millisecond of delay
379 05:14:03.317121 => setenv autoload no
380 05:14:03.327594 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
381 05:14:03.329627 setenv autoload no
382 05:14:03.330042 Sending with 10 millisecond of delay
384 05:14:05.127779 => setenv initrd_high 0xffffffff
385 05:14:05.138231 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
386 05:14:05.138738 setenv initrd_high 0xffffffff
387 05:14:05.139135 Sending with 10 millisecond of delay
389 05:14:06.755164 => setenv fdt_high 0xffffffff
390 05:14:06.765732 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
391 05:14:06.766377 setenv fdt_high 0xffffffff
392 05:14:06.766829 Sending with 10 millisecond of delay
394 05:14:07.058200 => dhcp
395 05:14:07.068635 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 05:14:07.069056 dhcp
397 05:14:07.071154 link up on port 0, speed 100, full duplex
398 05:14:07.071346 BOOTP broadcast 1
399 05:14:07.323159 BOOTP broadcast 2
400 05:14:07.824023 BOOTP broadcast 3
401 05:14:08.826528 BOOTP broadcast 4
402 05:14:08.847426 *** Unhandled DHCP Option in OFFER/ACK: 42
403 05:14:08.888202 *** Unhandled DHCP Option in OFFER/ACK: 42
404 05:14:08.894621 DHCP client bound to address 192.168.56.5 (1821 ms)
405 05:14:08.895070 Sending with 10 millisecond of delay
407 05:14:10.754063 => setenv serverip 192.168.56.193
408 05:14:10.764510 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
409 05:14:10.765009 setenv serverip 192.168.56.193
410 05:14:10.765407 Sending with 10 millisecond of delay
412 05:14:14.252075 => tftp 0x82000000 681419/tftp-deploy-2pbc44hq/kernel/zImage
413 05:14:14.262394 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
414 05:14:14.262863 tftp 0x82000000 681419/tftp-deploy-2pbc44hq/kernel/zImage
415 05:14:14.263052 link up on port 0, speed 100, full duplex
416 05:14:14.267104 Using ethernet@4a100000 device
417 05:14:14.272765 TFTP from server 192.168.56.193; our IP address is 192.168.56.5
418 05:14:14.280200 Filename '681419/tftp-deploy-2pbc44hq/kernel/zImage'.
419 05:14:14.280335 Load address: 0x82000000
420 05:14:15.958107 Loading: *################################################## 10.8 MiB
421 05:14:15.958409 6.5 MiB/s
422 05:14:15.958568 done
423 05:14:15.962762 Bytes transferred = 11354624 (ad4200 hex)
424 05:14:15.963248 Sending with 10 millisecond of delay
426 05:14:20.421602 => tftp 0x83000000 681419/tftp-deploy-2pbc44hq/ramdisk/ramdisk.cpio.gz.uboot
427 05:14:20.432119 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
428 05:14:20.432688 tftp 0x83000000 681419/tftp-deploy-2pbc44hq/ramdisk/ramdisk.cpio.gz.uboot
429 05:14:20.432935 link up on port 0, speed 100, full duplex
430 05:14:20.436518 Using ethernet@4a100000 device
431 05:14:20.442107 TFTP from server 192.168.56.193; our IP address is 192.168.56.5
432 05:14:20.451001 Filename '681419/tftp-deploy-2pbc44hq/ramdisk/ramdisk.cpio.gz.uboot'.
433 05:14:20.451253 Load address: 0x83000000
434 05:14:22.794807 Loading: *################################################## 14.1 MiB
435 05:14:22.795131 6 MiB/s
436 05:14:22.795289 done
437 05:14:22.797737 Bytes transferred = 14798932 (e1d054 hex)
438 05:14:22.798181 Sending with 10 millisecond of delay
440 05:14:24.660416 => setenv initrd_size ${filesize}
441 05:14:24.671174 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
442 05:14:24.671651 setenv initrd_size ${filesize}
443 05:14:24.672033 Sending with 10 millisecond of delay
445 05:14:28.824812 => tftp 0x88000000 681419/tftp-deploy-2pbc44hq/dtb/am335x-boneblack.dtb
446 05:14:28.835221 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
447 05:14:28.835565 tftp 0x88000000 681419/tftp-deploy-2pbc44hq/dtb/am335x-boneblack.dtb
448 05:14:28.835700 link up on port 0, speed 100, full duplex
449 05:14:28.839969 Using ethernet@4a100000 device
450 05:14:28.845311 TFTP from server 192.168.56.193; our IP address is 192.168.56.5
451 05:14:28.856692 Filename '681419/tftp-deploy-2pbc44hq/dtb/am335x-boneblack.dtb'.
452 05:14:28.856990 Load address: 0x88000000
453 05:14:28.867083 Loading: *################################################## 68.7 KiB
454 05:14:28.867356 5.2 MiB/s
455 05:14:28.867507 done
456 05:14:28.874278 Bytes transferred = 70308 (112a4 hex)
457 05:14:28.874664 Sending with 10 millisecond of delay
459 05:14:42.258359 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/681419/extract-nfsrootfs-0qnqcc8h,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
460 05:14:42.268806 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
461 05:14:42.269273 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/681419/extract-nfsrootfs-0qnqcc8h,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
462 05:14:42.269642 Sending with 10 millisecond of delay
464 05:14:44.611239 => bootz 0x82000000 0x83000000 0x88000000
465 05:14:44.621669 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
466 05:14:44.621949 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
467 05:14:44.622362 bootz 0x82000000 0x83000000 0x88000000
468 05:14:44.622508 Kernel image @ 0x82000000 [ 0x000000 - 0xad4200 ]
469 05:14:44.623745 ## Loading init Ramdisk from Legacy Image at 83000000 ...
470 05:14:44.629229 Image Name:
471 05:14:44.629431 Created: 2024-08-31 5:13:45 UTC
472 05:14:44.634826 Image Type: ARM Linux RAMDisk Image (uncompressed)
473 05:14:44.640299 Data Size: 14798868 Bytes = 14.1 MiB
474 05:14:44.640511 Load Address: 00000000
475 05:14:44.646529 Entry Point: 00000000
476 05:14:44.814903 Verifying Checksum ... OK
477 05:14:44.815170 ## Flattened Device Tree blob at 88000000
478 05:14:44.821376 Booting using the fdt blob at 0x88000000
479 05:14:44.821617 Working FDT set to 88000000
480 05:14:44.826963 Using Device Tree in place at 88000000, end 880142a3
481 05:14:44.831375 Working FDT set to 88000000
482 05:14:44.844772
483 05:14:44.845016 Starting kernel ...
484 05:14:44.845146
485 05:14:44.845564 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
486 05:14:44.845784 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
487 05:14:44.845920 Setting prompt string to ['Linux version [0-9]']
488 05:14:44.846052 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
489 05:14:44.846223 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
490 05:14:45.681696 [ 0.000000] Booting Linux on physical CPU 0x0
491 05:14:45.687790 start: 2.4.4.1 login-action (timeout 00:04:00) [common]
492 05:14:45.688124 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
493 05:14:45.688311 Setting prompt string to []
494 05:14:45.688505 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
495 05:14:45.688671 Using line separator: #'\n'#
496 05:14:45.688816 No login prompt set.
497 05:14:45.688965 Parsing kernel messages
498 05:14:45.689099 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
499 05:14:45.689382 [login-action] Waiting for messages, (timeout 00:04:00)
500 05:14:45.689539 Waiting using forced prompt support (timeout 00:02:00)
501 05:14:45.702454 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j302843-arm-gcc-12-multi-v7-defconfig-hz8dc) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sat Aug 31 04:47:30 UTC 2024
502 05:14:45.713372 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
503 05:14:45.716754 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
504 05:14:45.722704 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
505 05:14:45.728192 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
506 05:14:45.734471 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
507 05:14:45.744447 [ 0.000000] Memory policy: Data cache writeback
508 05:14:45.744815 [ 0.000000] efi: UEFI not found.
509 05:14:45.752725 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
510 05:14:45.758713 [ 0.000000] Zone ranges:
511 05:14:45.764209 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
512 05:14:45.764512 [ 0.000000] Normal empty
513 05:14:45.770233 [ 0.000000] HighMem empty
514 05:14:45.775696 [ 0.000000] Movable zone start for each node
515 05:14:45.775908 [ 0.000000] Early memory node ranges
516 05:14:45.781415 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
517 05:14:45.790481 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
518 05:14:45.815154 [ 0.000000] CPU: All CPU(s) started in SVC mode.
519 05:14:45.820935 [ 0.000000] AM335X ES2.0 (sgx neon)
520 05:14:45.832442 [ 0.000000] percpu: Embedded 17 pages/cpu s40332 r8192 d21108 u69632
521 05:14:45.850484 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/681419/extract-nfsrootfs-0qnqcc8h,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
522 05:14:45.861689 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
523 05:14:45.867492 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
524 05:14:45.873150 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
525 05:14:45.883654 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
526 05:14:45.912470 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
527 05:14:45.918327 <6>[ 0.000000] trace event string verifier disabled
528 05:14:45.918548 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
529 05:14:45.926269 <6>[ 0.000000] rcu: RCU event tracing is enabled.
530 05:14:45.932181 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
531 05:14:45.943636 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
532 05:14:45.948710 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
533 05:14:45.963728 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
534 05:14:45.980892 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
535 05:14:45.987729 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
536 05:14:46.079906 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
537 05:14:46.091319 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
538 05:14:46.097957 <6>[ 0.008333] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
539 05:14:46.110944 <6>[ 0.019142] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
540 05:14:46.118040 <6>[ 0.033887] Console: colour dummy device 80x30
541 05:14:46.124233 Matched prompt #6: WARNING:
542 05:14:46.124545 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
543 05:14:46.129690 <3>[ 0.038785] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
544 05:14:46.132436 <3>[ 0.045857] This ensures that you still see kernel messages. Please
545 05:14:46.138931 <3>[ 0.052579] update your kernel commandline.
546 05:14:46.179395 <6>[ 0.057188] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
547 05:14:46.185262 <6>[ 0.096145] CPU: Testing write buffer coherency: ok
548 05:14:46.191291 <6>[ 0.101513] CPU0: Spectre v2: using BPIALL workaround
549 05:14:46.191600 <6>[ 0.106980] pid_max: default: 32768 minimum: 301
550 05:14:46.202778 <6>[ 0.112166] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
551 05:14:46.209259 <6>[ 0.119986] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
552 05:14:46.216647 <6>[ 0.129275] CPU0: thread -1, cpu 0, socket -1, mpidr 0
553 05:14:46.224633 <6>[ 0.136128] Setting up static identity map for 0x80300000 - 0x803000ac
554 05:14:46.230429 <6>[ 0.145685] rcu: Hierarchical SRCU implementation.
555 05:14:46.238311 <6>[ 0.150965] rcu: Max phase no-delay instances is 1000.
556 05:14:46.246657 <6>[ 0.161967] EFI services will not be available.
557 05:14:46.252596 <6>[ 0.167218] smp: Bringing up secondary CPUs ...
558 05:14:46.257977 <6>[ 0.172257] smp: Brought up 1 node, 1 CPU
559 05:14:46.263912 <6>[ 0.176658] SMP: Total of 1 processors activated (996.14 BogoMIPS).
560 05:14:46.269711 <6>[ 0.183410] CPU: All CPU(s) started in SVC mode.
561 05:14:46.290009 <6>[ 0.188590] Memory: 407004K/522240K available (16384K kernel code, 2540K rwdata, 6736K rodata, 2048K init, 430K bss, 48032K reserved, 65536K cma-reserved, 0K highmem)
562 05:14:46.290319 <6>[ 0.204823] devtmpfs: initialized
563 05:14:46.312219 <6>[ 0.221594] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
564 05:14:46.320453 <6>[ 0.230158] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
565 05:14:46.329393 <6>[ 0.240595] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
566 05:14:46.340314 <6>[ 0.252936] pinctrl core: initialized pinctrl subsystem
567 05:14:46.349281 <6>[ 0.263589] DMI not present or invalid.
568 05:14:46.357865 <6>[ 0.269342] NET: Registered PF_NETLINK/PF_ROUTE protocol family
569 05:14:46.367385 <6>[ 0.278277] DMA: preallocated 256 KiB pool for atomic coherent allocations
570 05:14:46.382070 <6>[ 0.289647] thermal_sys: Registered thermal governor 'step_wise'
571 05:14:46.382397 <6>[ 0.289788] cpuidle: using governor menu
572 05:14:46.409829 <6>[ 0.325247] No ATAGs?
573 05:14:46.415894 <6>[ 0.327892] hw-breakpoint: debug architecture 0x4 unsupported.
574 05:14:46.425974 <6>[ 0.339855] Serial: AMBA PL011 UART driver
575 05:14:46.466863 <6>[ 0.382591] iommu: Default domain type: Translated
576 05:14:46.476145 <6>[ 0.387823] iommu: DMA domain TLB invalidation policy: strict mode
577 05:14:46.486770 <5>[ 0.400754] SCSI subsystem initialized
578 05:14:46.510793 <6>[ 0.420434] usbcore: registered new interface driver usbfs
579 05:14:46.517301 <6>[ 0.426390] usbcore: registered new interface driver hub
580 05:14:46.517662 <6>[ 0.432215] usbcore: registered new device driver usb
581 05:14:46.523282 <6>[ 0.438711] pps_core: LinuxPPS API ver. 1 registered
582 05:14:46.534793 <6>[ 0.444140] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
583 05:14:46.540406 <6>[ 0.453838] PTP clock support registered
584 05:14:46.564570 <6>[ 0.479590] EDAC MC: Ver: 3.0.0
585 05:14:46.583669 <6>[ 0.496764] scmi_core: SCMI protocol bus registered
586 05:14:46.597992 <6>[ 0.514046] vgaarb: loaded
587 05:14:46.611511 <6>[ 0.526988] clocksource: Switched to clocksource dmtimer
588 05:14:46.647542 <6>[ 0.562745] NET: Registered PF_INET protocol family
589 05:14:46.660232 <6>[ 0.568401] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
590 05:14:46.665836 <6>[ 0.577235] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
591 05:14:46.677081 <6>[ 0.586123] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
592 05:14:46.682917 <6>[ 0.594395] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
593 05:14:46.694768 <6>[ 0.602682] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
594 05:14:46.700424 <6>[ 0.610398] TCP: Hash tables configured (established 4096 bind 4096)
595 05:14:46.705943 <6>[ 0.617314] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
596 05:14:46.711891 <6>[ 0.624324] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
597 05:14:46.719526 <6>[ 0.631946] NET: Registered PF_UNIX/PF_LOCAL protocol family
598 05:14:46.756478 <6>[ 0.666389] RPC: Registered named UNIX socket transport module.
599 05:14:46.756785 <6>[ 0.672813] RPC: Registered udp transport module.
600 05:14:46.762055 <6>[ 0.677946] RPC: Registered tcp transport module.
601 05:14:46.770722 <6>[ 0.683052] RPC: Registered tcp-with-tls transport module.
602 05:14:46.776368 <6>[ 0.688981] RPC: Registered tcp NFSv4.1 backchannel transport module.
603 05:14:46.784015 <6>[ 0.695889] PCI: CLS 0 bytes, default 64
604 05:14:46.785871 <5>[ 0.701669] Initialise system trusted keyrings
605 05:14:46.812938 <6>[ 0.725600] Trying to unpack rootfs image as initramfs...
606 05:14:46.838539 <6>[ 0.747655] workingset: timestamp_bits=30 max_order=17 bucket_order=0
607 05:14:46.842767 <6>[ 0.755129] squashfs: version 4.0 (2009/01/31) Phillip Lougher
608 05:14:46.882730 <5>[ 0.797955] NFS: Registering the id_resolver key type
609 05:14:46.888182 <5>[ 0.803557] Key type id_resolver registered
610 05:14:46.893988 <5>[ 0.808254] Key type id_legacy registered
611 05:14:46.900005 <6>[ 0.812693] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
612 05:14:46.909255 <6>[ 0.819903] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
613 05:14:46.955026 <5>[ 0.870700] Key type asymmetric registered
614 05:14:46.960776 <5>[ 0.875223] Asymmetric key parser 'x509' registered
615 05:14:46.972232 <6>[ 0.880719] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
616 05:14:46.972568 <6>[ 0.888657] io scheduler mq-deadline registered
617 05:14:46.978365 <6>[ 0.893588] io scheduler kyber registered
618 05:14:46.983964 <6>[ 0.898058] io scheduler bfq registered
619 05:14:47.399654 <6>[ 1.312381] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
620 05:14:47.435320 <6>[ 1.350948] msm_serial: driver initialized
621 05:14:47.441403 <6>[ 1.355725] SuperH (H)SCI(F) driver initialized
622 05:14:47.447628 <6>[ 1.361056] STMicroelectronics ASC driver initialized
623 05:14:47.452672 <6>[ 1.366664] STM32 USART driver initialized
624 05:14:47.548000 <6>[ 1.462969] brd: module loaded
625 05:14:47.578578 <6>[ 1.493855] loop: module loaded
626 05:14:47.638892 <6>[ 1.553768] CAN device driver interface
627 05:14:47.645331 <6>[ 1.558941] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
628 05:14:47.651318 <6>[ 1.565846] e1000e: Intel(R) PRO/1000 Network Driver
629 05:14:47.658073 <6>[ 1.571310] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
630 05:14:47.663783 <6>[ 1.577753] igb: Intel(R) Gigabit Ethernet Network Driver
631 05:14:47.671173 <6>[ 1.583575] igb: Copyright (c) 2007-2014 Intel Corporation.
632 05:14:47.682764 <6>[ 1.592738] pegasus: Pegasus/Pegasus II USB Ethernet driver
633 05:14:47.688457 <6>[ 1.598885] usbcore: registered new interface driver pegasus
634 05:14:47.691272 <6>[ 1.605010] usbcore: registered new interface driver asix
635 05:14:47.696962 <6>[ 1.610893] usbcore: registered new interface driver ax88179_178a
636 05:14:47.702787 <6>[ 1.617482] usbcore: registered new interface driver cdc_ether
637 05:14:47.708693 <6>[ 1.623779] usbcore: registered new interface driver smsc75xx
638 05:14:47.720134 <6>[ 1.630016] usbcore: registered new interface driver smsc95xx
639 05:14:47.725878 <6>[ 1.636226] usbcore: registered new interface driver net1080
640 05:14:47.731635 <6>[ 1.642368] usbcore: registered new interface driver cdc_subset
641 05:14:47.737378 <6>[ 1.648773] usbcore: registered new interface driver zaurus
642 05:14:47.742611 <6>[ 1.654842] usbcore: registered new interface driver cdc_ncm
643 05:14:47.752180 <6>[ 1.664257] usbcore: registered new interface driver usb-storage
644 05:14:47.875698 <6>[ 1.789310] i2c_dev: i2c /dev entries driver
645 05:14:47.936202 <5>[ 1.843872] cpuidle: enable-method property 'ti,am3352' found operations
646 05:14:47.942131 <6>[ 1.853469] sdhci: Secure Digital Host Controller Interface driver
647 05:14:47.949922 <6>[ 1.860231] sdhci: Copyright(c) Pierre Ossman
648 05:14:47.957147 <6>[ 1.866684] Synopsys Designware Multimedia Card Interface Driver
649 05:14:47.962484 <6>[ 1.874699] sdhci-pltfm: SDHCI platform and OF driver helper
650 05:14:48.025562 <6>[ 1.937557] ledtrig-cpu: registered to indicate activity on CPUs
651 05:14:48.059705 <6>[ 1.968063] usbcore: registered new interface driver usbhid
652 05:14:48.060004 <6>[ 1.974102] usbhid: USB HID core driver
653 05:14:48.100611 <6>[ 2.013498] NET: Registered PF_INET6 protocol family
654 05:14:48.142656 <6>[ 2.058500] Segment Routing with IPv6
655 05:14:48.148773 <6>[ 2.062646] In-situ OAM (IOAM) with IPv6
656 05:14:48.155220 <6>[ 2.067163] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
657 05:14:48.161217 <6>[ 2.074388] NET: Registered PF_PACKET protocol family
658 05:14:48.166896 <6>[ 2.079954] can: controller area network core
659 05:14:48.172497 <6>[ 2.084779] NET: Registered PF_CAN protocol family
660 05:14:48.172767 <6>[ 2.090000] can: raw protocol
661 05:14:48.178300 <6>[ 2.093328] can: broadcast manager protocol
662 05:14:48.184805 <6>[ 2.097922] can: netlink gateway - max_hops=1
663 05:14:48.191177 <5>[ 2.103404] Key type dns_resolver registered
664 05:14:48.197261 <6>[ 2.108464] ThumbEE CPU extension supported.
665 05:14:48.197484 <5>[ 2.113150] Registering SWP/SWPB emulation handler
666 05:14:48.207085 <3>[ 2.118854] omap_voltage_late_init: Voltage driver support not added
667 05:14:48.287334 <5>[ 2.200732] Loading compiled-in X.509 certificates
668 05:14:48.453223 <6>[ 2.355810] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
669 05:14:48.459429 <6>[ 2.372457] pinctrl-single 44e10800.pinmux: 142 pins, size 568
670 05:14:48.485960 <3>[ 2.396046] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
671 05:14:48.586604 <3>[ 2.496011] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
672 05:14:48.673817 <6>[ 2.587925] OMAP GPIO hardware version 0.1
673 05:14:48.694809 <6>[ 2.606497] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
674 05:14:48.767434 <4>[ 2.679038] at24 2-0054: supply vcc not found, using dummy regulator
675 05:14:48.820289 <4>[ 2.731979] at24 2-0055: supply vcc not found, using dummy regulator
676 05:14:48.907394 <4>[ 2.818525] at24 2-0056: supply vcc not found, using dummy regulator
677 05:14:48.957460 <4>[ 2.868716] at24 2-0057: supply vcc not found, using dummy regulator
678 05:14:48.999280 <6>[ 2.911531] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
679 05:14:49.081233 <3>[ 2.989482] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
680 05:14:49.105391 <6>[ 3.010310] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
681 05:14:49.131477 <4>[ 3.041977] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
682 05:14:49.177699 <4>[ 3.087990] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
683 05:14:49.215637 <6>[ 3.127807] omap_rng 48310000.rng: Random Number Generator ver. 20
684 05:14:49.239004 <5>[ 3.153759] random: crng init done
685 05:14:49.336788 <6>[ 3.247199] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
686 05:14:49.874612 <6>[ 3.788468] Freeing initrd memory: 14456K
687 05:14:49.918385 <6>[ 3.827883] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
688 05:14:49.923952 <6>[ 3.838062] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
689 05:14:49.935945 <6>[ 3.845324] cpsw-switch 4a100000.switch: ALE Table size 1024
690 05:14:49.941465 <6>[ 3.851775] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
691 05:14:49.952965 <6>[ 3.859903] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
692 05:14:49.960457 <6>[ 3.871535] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
693 05:14:49.972461 <5>[ 3.880574] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
694 05:14:50.000006 <3>[ 3.910239] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
695 05:14:50.005688 <6>[ 3.918785] edma 49000000.dma: TI EDMA DMA engine driver
696 05:14:50.075467 <3>[ 3.984756] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
697 05:14:50.089820 <6>[ 3.999858] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
698 05:14:50.108026 <3>[ 4.021282] l3-aon-clkctrl:0000:0: failed to disable
699 05:14:50.135042 <6>[ 4.045029] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
700 05:14:50.140659 <6>[ 4.054506] printk: legacy console [ttyS0] enabled
701 05:14:50.146561 <6>[ 4.054506] printk: legacy console [ttyS0] enabled
702 05:14:50.151950 <6>[ 4.064819] printk: legacy bootconsole [omap8250] disabled
703 05:14:50.157944 <6>[ 4.064819] printk: legacy bootconsole [omap8250] disabled
704 05:14:50.218857 <4>[ 4.127764] tps65217-pmic: Failed to locate of_node [id: -1]
705 05:14:50.222555 <4>[ 4.135143] tps65217-bl: Failed to locate of_node [id: -1]
706 05:14:50.238428 <6>[ 4.154367] tps65217 0-0024: TPS65217 ID 0xe version 1.2
707 05:14:50.256707 <6>[ 4.161302] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
708 05:14:50.268334 <6>[ 4.175022] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
709 05:14:50.273972 <6>[ 4.186863] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
710 05:14:50.296415 <6>[ 4.206693] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
711 05:14:50.302425 <6>[ 4.215954] sdhci-omap 48060000.mmc: Got CD GPIO
712 05:14:50.310576 <4>[ 4.221116] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
713 05:14:50.325198 <4>[ 4.234671] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
714 05:14:50.331699 <4>[ 4.243612] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
715 05:14:50.341450 <4>[ 4.252335] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
716 05:14:50.464523 <6>[ 4.375838] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
717 05:14:50.488840 <6>[ 4.400160] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
718 05:14:50.515248 <6>[ 4.424610] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
719 05:14:50.521828 <6>[ 4.433525] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
720 05:14:50.567852 <6>[ 4.473583] mmc1: new high speed MMC card at address 0001
721 05:14:50.568221 <6>[ 4.481432] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
722 05:14:50.578164 <6>[ 4.491227] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
723 05:14:50.585641 <6>[ 4.499145] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
724 05:14:50.591233 <6>[ 4.506462] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
725 05:14:50.620352 <6>[ 4.528169] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
726 05:14:50.709821 <6>[ 4.616643] mmc0: new high speed SDHC card at address aaaa
727 05:14:50.710127 <6>[ 4.623815] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
728 05:14:50.734462 <6>[ 4.648105] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
729 05:14:52.698310 <6>[ 6.607962] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
730 05:14:58.751336 <5>[ 6.667112] Sending DHCP requests ..., OK
731 05:14:58.762397 <6>[ 12.671600] IP-Config: Got DHCP answer from 192.168.56.254, my address is 192.168.56.5
732 05:14:58.762673 <6>[ 12.680021] IP-Config: Complete:
733 05:14:58.774076 <6>[ 12.683559] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.56.5, mask=255.255.255.0, gw=192.168.56.254
734 05:14:58.785549 <6>[ 12.694344] host=192.168.56.5, domain=mayfield.sirena.org.uk, nis-domain=(none)
735 05:14:58.790892 <6>[ 12.702684] bootserver=192.168.56.254, rootserver=192.168.56.193, rootpath=
736 05:14:58.796574 <6>[ 12.702723] nameserver0=192.168.56.254
737 05:14:58.803135 <6>[ 12.715010] ntpserver0=50.205.244.22, ntpserver1=85.199.214.99
738 05:14:58.809323 <6>[ 12.722625] clk: Disabling unused clocks
739 05:14:58.813744 <6>[ 12.727337] PM: genpd: Disabling unused power domains
740 05:14:58.833822 <6>[ 12.746205] Freeing unused kernel image (initmem) memory: 2048K
741 05:14:58.840345 <6>[ 12.755895] Run /init as init process
742 05:14:58.863994 Loading, please wait...
743 05:14:58.939034 Starting systemd-udevd version 252.22-1~deb12u1
744 05:15:02.119659 <4>[ 16.028432] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
745 05:15:02.293251 <4>[ 16.202182] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
746 05:15:02.405207 <6>[ 16.321703] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
747 05:15:02.416200 <6>[ 16.327511] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
748 05:15:02.445527 <6>[ 16.360114] tda998x 0-0070: found TDA19988
749 05:15:02.530509 <6>[ 16.445449] hub 1-0:1.0: USB hub found
750 05:15:02.579460 <6>[ 16.494908] hub 1-0:1.0: 1 port detected
751 05:15:05.631863 Begin: Loading essential drivers ... done.
752 05:15:05.637524 Begin: Running /scripts/init-premount ... done.
753 05:15:05.643065 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
754 05:15:05.650650 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
755 05:15:05.656900 Device /sys/class/net/eth0 found
756 05:15:05.657140 done.
757 05:15:05.730708 Begin: Waiting up to 180 secs for any network device to become available ... done.
758 05:15:05.803852 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
759 05:15:05.882349 IP-Config: eth0 complete (dhcp from 192.168.56.254):
760 05:15:05.893546 address: 192.168.56.5 broadcast: 192.168.56.255 netmask: 255.255.255.0
761 05:15:05.896796 gateway: 192.168.56.254 dns0 : 192.168.56.254 dns1 : 0.0.0.0
762 05:15:05.910537 domain : mayfield.sirena.org.uk
763 05:15:05.910823 rootserver: 192.168.56.254 rootpath:
764 05:15:05.910998 filename :
765 05:15:06.018181 done.
766 05:15:06.027660 Begin: Running /scripts/nfs-bottom ... done.
767 05:15:06.097646 Begin: Running /scripts/init-bottom ... done.
768 05:15:07.465075 <30>[ 21.377160] systemd[1]: System time before build time, advancing clock.
769 05:15:07.688635 <30>[ 21.574650] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
770 05:15:07.697924 <30>[ 21.611867] systemd[1]: Detected architecture arm.
771 05:15:07.710951
772 05:15:07.711201 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
773 05:15:07.711328
774 05:15:07.744839 <30>[ 21.657268] systemd[1]: Hostname set to <debian-bookworm-armhf>.
775 05:15:09.828466 <30>[ 23.739863] systemd[1]: Queued start job for default target graphical.target.
776 05:15:09.845057 <30>[ 23.754612] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
777 05:15:09.852539 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
778 05:15:09.891188 <30>[ 23.799817] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
779 05:15:09.898669 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
780 05:15:09.933814 <30>[ 23.842885] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
781 05:15:09.941163 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
782 05:15:09.978421 <30>[ 23.888821] systemd[1]: Created slice user.slice - User and Session Slice.
783 05:15:09.985306 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
784 05:15:10.021613 <30>[ 23.929246] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
785 05:15:10.034580 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
786 05:15:10.068255 <30>[ 23.978257] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
787 05:15:10.076228 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
788 05:15:10.119064 <30>[ 24.018182] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
789 05:15:10.125443 <30>[ 24.038679] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
790 05:15:10.133107 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
791 05:15:10.166953 <30>[ 24.077417] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
792 05:15:10.175351 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
793 05:15:10.208532 <30>[ 24.118001] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
794 05:15:10.216869 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
795 05:15:10.249395 <30>[ 24.158894] systemd[1]: Reached target paths.target - Path Units.
796 05:15:10.253600 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
797 05:15:10.287143 <30>[ 24.197571] systemd[1]: Reached target remote-fs.target - Remote File Systems.
798 05:15:10.294547 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
799 05:15:10.327168 <30>[ 24.237520] systemd[1]: Reached target slices.target - Slice Units.
800 05:15:10.332693 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
801 05:15:10.367433 <30>[ 24.277688] systemd[1]: Reached target swap.target - Swaps.
802 05:15:10.371554 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
803 05:15:10.408029 <30>[ 24.318406] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
804 05:15:10.420403 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
805 05:15:10.448536 <30>[ 24.358460] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
806 05:15:10.456875 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
807 05:15:10.545054 <30>[ 24.450363] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
808 05:15:10.557827 <30>[ 24.467864] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
809 05:15:10.566237 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
810 05:15:10.599461 <30>[ 24.509449] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
811 05:15:10.606856 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
812 05:15:10.640348 <30>[ 24.550440] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
813 05:15:10.648573 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
814 05:15:10.681949 <30>[ 24.591710] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
815 05:15:10.687778 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
816 05:15:10.729707 <30>[ 24.640512] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
817 05:15:10.742362 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
818 05:15:10.784991 <30>[ 24.688792] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
819 05:15:10.801485 <30>[ 24.705513] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
820 05:15:10.838535 <30>[ 24.749503] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
821 05:15:10.857185 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
822 05:15:10.909371 <30>[ 24.820152] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
823 05:15:10.929966 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
824 05:15:11.012963 <30>[ 24.922764] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
825 05:15:11.045639 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
826 05:15:11.109780 <30>[ 25.020149] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
827 05:15:11.130568 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
828 05:15:11.190275 <30>[ 25.101103] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
829 05:15:11.215783 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
830 05:15:11.279091 <30>[ 25.190998] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
831 05:15:11.290852 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
832 05:15:11.361200 <30>[ 25.271085] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
833 05:15:11.386235 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
834 05:15:11.450488 <30>[ 25.361508] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
835 05:15:11.477267 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
836 05:15:11.530261 <30>[ 25.441462] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
837 05:15:11.557293 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
838 05:15:11.594518 <28>[ 25.499232] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
839 05:15:11.603127 <28>[ 25.513342] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
840 05:15:11.638260 <30>[ 25.550490] systemd[1]: Starting systemd-journald.service - Journal Service...
841 05:15:11.656423 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
842 05:15:11.727388 <30>[ 25.638278] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
843 05:15:11.742181 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
844 05:15:11.777806 <30>[ 25.688725] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
845 05:15:11.840894 Starting [0;1;39msystemd-network-g… units from Kernel command line...
846 05:15:11.908974 <30>[ 25.818380] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
847 05:15:11.958244 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
848 05:15:12.019893 <30>[ 25.930244] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
849 05:15:12.066961 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
850 05:15:12.137848 <30>[ 26.048980] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
851 05:15:12.168517 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
852 05:15:12.207837 <30>[ 26.118768] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
853 05:15:12.246286 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
854 05:15:12.282419 <30>[ 26.192239] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
855 05:15:12.311263 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
856 05:15:12.477805 <30>[ 26.387943] systemd[1]: Started systemd-journald.service - Journal Service.
857 05:15:12.484130 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
858 05:15:12.521370 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
859 05:15:12.562913 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
860 05:15:12.582145 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
861 05:15:12.602828 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
862 05:15:12.642648 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
863 05:15:12.682771 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
864 05:15:12.699956 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
865 05:15:12.730735 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
866 05:15:12.769748 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
867 05:15:12.818007 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
868 05:15:12.886885 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
869 05:15:12.937618 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
870 05:15:13.012581 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
871 05:15:13.100914 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
872 05:15:13.159914 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
873 05:15:13.287647 <46>[ 27.198608] systemd-journald[158]: Received client request to flush runtime journal.
874 05:15:13.308078 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
875 05:15:13.497301 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
876 05:15:14.313672 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
877 05:15:14.676929 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
878 05:15:14.739497 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
879 05:15:15.047473 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
880 05:15:15.279685 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
881 05:15:15.309400 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
882 05:15:15.338138 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
883 05:15:15.397602 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
884 05:15:15.428998 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
885 05:15:16.321282 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
886 05:15:16.409096 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
887 05:15:16.650249 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
888 05:15:16.786199 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
889 05:15:16.863390 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
890 05:15:18.819248 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
891 05:15:19.033651 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
892 05:15:19.541629 <5>[ 33.452850] cfg80211: Loading compiled-in X.509 certificates for regulatory database
893 05:15:19.732867 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
894 05:15:20.581308 <5>[ 34.494785] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
895 05:15:20.662974 <5>[ 34.571311] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
896 05:15:20.668699 <4>[ 34.581840] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
897 05:15:20.676508 <6>[ 34.591021] cfg80211: failed to load regulatory.db
898 05:15:20.891104 <46>[ 34.792549] systemd-journald[158]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
899 05:15:20.951075 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
900 05:15:21.102448 <46>[ 35.006787] systemd-journald[158]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
901 05:15:21.793196 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
902 05:15:30.732405 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
903 05:15:30.767271 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
904 05:15:30.801379 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
905 05:15:30.837828 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
906 05:15:30.933762 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
907 05:15:30.966342 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
908 05:15:31.021033 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
909 05:15:31.080086 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
910 05:15:31.141835 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
911 05:15:31.195675 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
912 05:15:31.242344 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
913 05:15:31.300234 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
914 05:15:31.341103 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
915 05:15:31.396168 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
916 05:15:31.434370 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
917 05:15:31.472121 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
918 05:15:31.523375 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
919 05:15:31.564590 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
920 05:15:31.617528 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
921 05:15:31.645896 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
922 05:15:31.700407 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
923 05:15:31.735845 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
924 05:15:31.775198 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
925 05:15:31.850041 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
926 05:15:31.881440 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
927 05:15:31.981988 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
928 05:15:32.079425 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
929 05:15:32.148746 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
930 05:15:32.226894 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
931 05:15:32.268996 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
932 05:15:32.426840 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
933 05:15:32.506563 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
934 05:15:32.568297 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
935 05:15:32.597611 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
936 05:15:32.628511 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
937 05:15:32.841889 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
938 05:15:32.975467 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
939 05:15:33.378504 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
940 05:15:33.576151 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
941 05:15:33.637301 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
942 05:15:33.653638 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
943 05:15:33.749607 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
944 05:15:33.941008 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
945 05:15:34.124238
946 05:15:34.124491 Debian GNU/Linux worm-armhf login: root (automatic login)
947 05:15:34.126323
948 05:15:34.424737 Linux debian-bookworm-armhf 6.11.0-rc5 #1 SMP Sat Aug 31 04:47:30 UTC 2024 armv7l
949 05:15:34.425026
950 05:15:34.429912 The programs included with the Debian GNU/Linux system are free software;
951 05:15:34.435645 the exact distribution terms for each program are described in the
952 05:15:34.441314 individual files in /usr/share/doc/*/copyright.
953 05:15:34.441483
954 05:15:34.449233 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
955 05:15:34.449421 permitted by applicable law.
956 05:15:39.438302 Unable to match end of the kernel message
958 05:15:39.438639 Setting prompt string to ['/ #']
959 05:15:39.438746 end: 2.4.4.1 login-action (duration 00:00:54) [common]
961 05:15:39.438961 end: 2.4.4 auto-login-action (duration 00:00:55) [common]
962 05:15:39.439054 start: 2.4.5 expect-shell-connection (timeout 00:03:06) [common]
963 05:15:39.439125 Setting prompt string to ['/ #']
964 05:15:39.439189 Forcing a shell prompt, looking for ['/ #']
966 05:15:39.489411 / #
967 05:15:39.489655 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
968 05:15:39.489739 Waiting using forced prompt support (timeout 00:02:30)
969 05:15:39.494464
970 05:15:39.519188 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
971 05:15:39.519464 start: 2.4.6 export-device-env (timeout 00:03:06) [common]
972 05:15:39.519621 Sending with 10 millisecond of delay
974 05:15:44.525246 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/681419/extract-nfsrootfs-0qnqcc8h'
975 05:15:44.536237 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/681419/extract-nfsrootfs-0qnqcc8h'
976 05:15:44.536855 Sending with 10 millisecond of delay
978 05:15:46.828723 / # export NFS_SERVER_IP='192.168.56.193'
979 05:15:46.839552 export NFS_SERVER_IP='192.168.56.193'
980 05:15:46.840897 end: 2.4.6 export-device-env (duration 00:00:07) [common]
981 05:15:46.841177 end: 2.4 uboot-commands (duration 00:02:02) [common]
982 05:15:46.841415 end: 2 uboot-action (duration 00:02:02) [common]
983 05:15:46.841626 start: 3 lava-test-retry (timeout 00:07:29) [common]
984 05:15:46.841837 start: 3.1 lava-test-shell (timeout 00:07:29) [common]
985 05:15:46.842008 Using namespace: common
987 05:15:46.942890 / # #
988 05:15:46.943300 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
989 05:15:46.948461 #
990 05:15:46.954360 Using /lava-681419
992 05:15:47.055643 / # export SHELL=/bin/bash
993 05:15:47.060172 export SHELL=/bin/bash
995 05:15:47.168191 / # . /lava-681419/environment
996 05:15:47.173601 . /lava-681419/environment
998 05:15:47.288174 / # /lava-681419/bin/lava-test-runner /lava-681419/0
999 05:15:47.288680 Test shell timeout: 10s (minimum of the action and connection timeout)
1000 05:15:47.293463 /lava-681419/bin/lava-test-runner /lava-681419/0
1001 05:15:47.757338 + export TESTRUN_ID=0_timesync-off
1002 05:15:47.765019 + TESTRUN_ID=0_timesync-off
1003 05:15:47.765253 + cd /lava-681419/0/tests/0_timesync-off
1004 05:15:47.765460 ++ cat uuid
1005 05:15:47.784701 + UUID=681419_1.6.2.4.1
1006 05:15:47.785008 + set +x
1007 05:15:47.793212 <LAVA_SIGNAL_STARTRUN 0_timesync-off 681419_1.6.2.4.1>
1008 05:15:47.793519 + systemctl stop systemd-timesyncd
1009 05:15:47.793987 Received signal: <STARTRUN> 0_timesync-off 681419_1.6.2.4.1
1010 05:15:47.794175 Starting test lava.0_timesync-off (681419_1.6.2.4.1)
1011 05:15:47.794435 Skipping test definition patterns.
1012 05:15:48.107100 + set +x
1013 05:15:48.120599 <LAVA_SIGNAL_ENDRUN 0_timesync-off 681419_1.6.2.4.1>
1014 05:15:48.121189 Received signal: <ENDRUN> 0_timesync-off 681419_1.6.2.4.1
1015 05:15:48.121427 Ending use of test pattern.
1016 05:15:48.121618 Ending test lava.0_timesync-off (681419_1.6.2.4.1), duration 0.33
1018 05:15:48.313607 + export TESTRUN_ID=1_kselftest-dt
1019 05:15:48.321517 + TESTRUN_ID=1_kselftest-dt
1020 05:15:48.321866 + cd /lava-681419/0/tests/1_kselftest-dt
1021 05:15:48.322077 ++ cat uuid
1022 05:15:48.337632 + UUID=681419_1.6.2.4.5
1023 05:15:48.337967 + set +x
1024 05:15:48.343184 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 681419_1.6.2.4.5>
1025 05:15:48.343492 + cd ./automated/linux/kselftest/
1026 05:15:48.343931 Received signal: <STARTRUN> 1_kselftest-dt 681419_1.6.2.4.5
1027 05:15:48.344114 Starting test lava.1_kselftest-dt (681419_1.6.2.4.5)
1028 05:15:48.344358 Skipping test definition patterns.
1029 05:15:48.371544 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1030 05:15:48.502692 INFO: install_deps skipped
1031 05:15:49.126233 --2024-08-31 05:15:49-- http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1032 05:15:49.163168 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1033 05:15:49.304535 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1034 05:15:49.444989 HTTP request sent, awaiting response... 200 OK
1035 05:15:49.445381 Length: 3607668 (3.4M) [application/octet-stream]
1036 05:15:49.450443 Saving to: 'kselftest_armhf.tar.gz'
1037 05:15:49.450830
1038 05:15:51.647829
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 48.95K 178KB/s
kselftest_armhf.tar 6%[> ] 218.67K 395KB/s
kselftest_armhf.tar 23%[===> ] 836.45K 863KB/s
kselftest_armhf.tar 66%[============> ] 2.28M 1.83MB/s
kselftest_armhf.tar 92%[=================> ] 3.19M 2.18MB/s
kselftest_armhf.tar 99%[==================> ] 3.44M 1.67MB/s
kselftest_armhf.tar 100%[===================>] 3.44M 1.57MB/s in 2.2s
1039 05:15:51.648125
1040 05:15:52.175027 2024-08-31 05:15:51 (1.57 MB/s) - 'kselftest_armhf.tar.gz' saved [3607668/3607668]
1041 05:15:52.175317
1042 05:16:07.663543 skiplist:
1043 05:16:07.663803 ========================================
1044 05:16:07.669425 ========================================
1045 05:16:07.763484 dt:test_unprobed_devices.sh
1046 05:16:07.793878 ============== Tests to run ===============
1047 05:16:07.800397 dt:test_unprobed_devices.sh
1048 05:16:07.804363 ===========End Tests to run ===============
1049 05:16:07.813337 shardfile-dt pass
1050 05:16:08.025423 <12>[ 81.941692] kselftest: Running tests in dt
1051 05:16:08.053082 TAP version 13
1052 05:16:08.074921 1..1
1053 05:16:08.126577 # timeout set to 45
1054 05:16:08.126825 # selftests: dt: test_unprobed_devices.sh
1055 05:16:08.938010 # TAP version 13
1056 05:16:20.805743 # 1..255
1057 05:16:20.975006 # ok 1 / # SKIP
1058 05:16:20.995697 # ok 2 /clk_mcasp0
1059 05:16:21.068837 # ok 3 /clk_mcasp0_fixed # SKIP
1060 05:16:21.136007 # ok 4 /cpus/cpu@0 # SKIP
1061 05:16:21.205537 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1062 05:16:21.229203 # ok 6 /fixedregulator0
1063 05:16:21.244837 # ok 7 /leds
1064 05:16:21.265878 # ok 8 /ocp
1065 05:16:21.289364 # ok 9 /ocp/interconnect@44c00000
1066 05:16:21.316353 # ok 10 /ocp/interconnect@44c00000/segment@0
1067 05:16:21.338928 # ok 11 /ocp/interconnect@44c00000/segment@100000
1068 05:16:21.361543 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1069 05:16:21.433243 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1070 05:16:21.451841 # ok 14 /ocp/interconnect@44c00000/segment@200000
1071 05:16:21.477303 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1072 05:16:21.575013 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1073 05:16:21.643630 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1074 05:16:21.714633 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1075 05:16:21.782775 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1076 05:16:21.856391 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1077 05:16:21.922401 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1078 05:16:21.997787 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1079 05:16:22.064076 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1080 05:16:22.137743 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1081 05:16:22.204062 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1082 05:16:22.266795 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1083 05:16:22.341749 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1084 05:16:22.413830 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1085 05:16:22.480436 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1086 05:16:22.546258 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1087 05:16:22.617097 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1088 05:16:22.699326 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1089 05:16:22.772437 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1090 05:16:22.862117 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1091 05:16:22.931180 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1092 05:16:23.012768 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1093 05:16:23.080174 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1094 05:16:23.160435 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1095 05:16:23.239094 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1096 05:16:23.316491 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1097 05:16:23.396652 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1098 05:16:23.476134 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1099 05:16:23.552361 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1100 05:16:23.637907 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1101 05:16:23.715615 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1102 05:16:23.793901 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1103 05:16:23.866801 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1104 05:16:23.940802 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1105 05:16:24.018809 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1106 05:16:24.099675 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1107 05:16:24.177040 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1108 05:16:24.254013 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1109 05:16:24.327077 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1110 05:16:24.414787 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1111 05:16:24.482823 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1112 05:16:24.569893 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1113 05:16:24.649495 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1114 05:16:24.726245 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1115 05:16:24.808453 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1116 05:16:24.885235 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1117 05:16:24.955933 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1118 05:16:25.045299 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1119 05:16:25.117238 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1120 05:16:25.199036 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1121 05:16:25.276607 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1122 05:16:25.354656 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1123 05:16:25.426515 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1124 05:16:25.508033 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1125 05:16:25.581343 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1126 05:16:25.664244 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1127 05:16:25.745755 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1128 05:16:25.826364 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1129 05:16:25.906525 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1130 05:16:25.985416 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1131 05:16:26.056539 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1132 05:16:26.137204 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1133 05:16:26.211717 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1134 05:16:26.295420 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1135 05:16:26.372981 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1136 05:16:26.449171 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1137 05:16:26.526768 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1138 05:16:26.604458 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1139 05:16:26.683972 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1140 05:16:26.755686 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1141 05:16:26.832908 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1142 05:16:26.914981 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1143 05:16:26.993641 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1144 05:16:27.073317 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1145 05:16:27.148789 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1146 05:16:27.227951 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1147 05:16:27.304610 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1148 05:16:27.386284 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1149 05:16:27.463735 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1150 05:16:27.545434 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1151 05:16:27.567281 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1152 05:16:27.581938 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1153 05:16:27.615368 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1154 05:16:27.630941 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1155 05:16:27.660440 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1156 05:16:27.681861 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1157 05:16:27.712875 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1158 05:16:27.735138 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1159 05:16:27.839987 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1160 05:16:27.866607 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1161 05:16:27.897546 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1162 05:16:27.921692 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1163 05:16:28.035556 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1164 05:16:28.116175 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1165 05:16:28.191478 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1166 05:16:28.269744 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1167 05:16:28.336725 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1168 05:16:28.420480 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1169 05:16:28.488851 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1170 05:16:28.569937 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1171 05:16:28.647725 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1172 05:16:28.719485 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1173 05:16:28.797153 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1174 05:16:28.868816 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1175 05:16:28.947686 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1176 05:16:29.031755 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1177 05:16:29.109435 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1178 05:16:29.185914 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1179 05:16:29.205475 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1180 05:16:29.278003 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1181 05:16:29.355183 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1182 05:16:29.433308 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1183 05:16:29.455262 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1184 05:16:29.522564 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1185 05:16:29.549299 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1186 05:16:29.622906 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1187 05:16:29.641058 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1188 05:16:29.670947 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1189 05:16:29.688149 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1190 05:16:29.717657 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1191 05:16:29.741357 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1192 05:16:29.765697 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1193 05:16:29.792959 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1194 05:16:29.815670 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1195 05:16:29.840108 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1196 05:16:29.917805 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1197 05:16:29.987061 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1198 05:16:30.015292 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1199 05:16:30.088670 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1200 05:16:30.167124 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1201 05:16:30.268713 # not ok 145 /ocp/interconnect@47c00000
1202 05:16:30.351288 # not ok 146 /ocp/interconnect@47c00000/segment@0
1203 05:16:30.381351 # ok 147 /ocp/interconnect@48000000
1204 05:16:30.400624 # ok 148 /ocp/interconnect@48000000/segment@0
1205 05:16:30.426580 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1206 05:16:30.451617 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1207 05:16:30.477624 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1208 05:16:30.503743 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1209 05:16:30.521365 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1210 05:16:30.546074 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1211 05:16:30.567845 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1212 05:16:30.651259 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1213 05:16:30.722560 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1214 05:16:30.750619 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1215 05:16:30.775661 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1216 05:16:30.794109 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1217 05:16:30.824483 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1218 05:16:30.839161 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1219 05:16:30.865134 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1220 05:16:30.894736 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1221 05:16:30.912067 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1222 05:16:30.940084 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1223 05:16:30.965511 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1224 05:16:30.983663 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1225 05:16:31.012925 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1226 05:16:31.031411 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1227 05:16:31.062093 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1228 05:16:31.084846 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1229 05:16:31.107306 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1230 05:16:31.132900 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1231 05:16:31.159889 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1232 05:16:31.183364 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1233 05:16:31.200624 # ok 177 /ocp/interconnect@48000000/segment@100000
1234 05:16:31.231476 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1235 05:16:31.253666 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1236 05:16:31.334467 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1237 05:16:31.401538 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1238 05:16:31.483238 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1239 05:16:31.557370 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1240 05:16:31.579488 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1241 05:16:31.601949 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1242 05:16:31.624031 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1243 05:16:31.649252 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1244 05:16:31.673095 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1245 05:16:31.702056 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1246 05:16:31.719287 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1247 05:16:31.742921 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1248 05:16:31.774303 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1249 05:16:31.790943 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1250 05:16:31.821529 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1251 05:16:31.842511 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1252 05:16:31.869486 # ok 196 /ocp/interconnect@48000000/segment@200000
1253 05:16:31.891537 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1254 05:16:31.974703 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1255 05:16:31.993026 # ok 199 /ocp/interconnect@48000000/segment@300000
1256 05:16:32.018625 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1257 05:16:32.047138 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1258 05:16:32.074519 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1259 05:16:32.090523 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1260 05:16:32.115601 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1261 05:16:32.144840 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1262 05:16:32.219006 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1263 05:16:32.249250 # ok 207 /ocp/interconnect@4a000000
1264 05:16:32.270016 # ok 208 /ocp/interconnect@4a000000/segment@0
1265 05:16:32.293187 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1266 05:16:32.323972 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1267 05:16:32.347798 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1268 05:16:32.371870 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1269 05:16:32.443371 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1270 05:16:32.557961 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1271 05:16:32.636585 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1272 05:16:32.747465 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1273 05:16:32.821445 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1274 05:16:32.896057 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1275 05:16:33.000529 # not ok 219 /ocp/interconnect@4b140000
1276 05:16:33.069777 # not ok 220 /ocp/interconnect@4b140000/segment@0
1277 05:16:33.151039 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1278 05:16:33.169673 # ok 222 /ocp/target-module@40300000
1279 05:16:33.194517 # ok 223 /ocp/target-module@40300000/sram@0
1280 05:16:33.279248 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1281 05:16:33.362999 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1282 05:16:33.380884 # ok 226 /ocp/target-module@47400000
1283 05:16:33.403064 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1284 05:16:33.429639 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1285 05:16:33.450213 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1286 05:16:33.479228 # ok 230 /ocp/target-module@47400000/usb@1400
1287 05:16:33.501373 # ok 231 /ocp/target-module@47400000/usb@1800
1288 05:16:33.519222 # ok 232 /ocp/target-module@47810000
1289 05:16:33.540863 # ok 233 /ocp/target-module@49000000
1290 05:16:33.564023 # ok 234 /ocp/target-module@49000000/dma@0
1291 05:16:33.589256 # ok 235 /ocp/target-module@49800000
1292 05:16:33.614544 # ok 236 /ocp/target-module@49800000/dma@0
1293 05:16:33.633595 # ok 237 /ocp/target-module@49900000
1294 05:16:33.659742 # ok 238 /ocp/target-module@49900000/dma@0
1295 05:16:33.684901 # ok 239 /ocp/target-module@49a00000
1296 05:16:33.708411 # ok 240 /ocp/target-module@49a00000/dma@0
1297 05:16:33.729049 # ok 241 /ocp/target-module@4c000000
1298 05:16:33.805652 # not ok 242 /ocp/target-module@4c000000/emif@0
1299 05:16:33.836476 # ok 243 /ocp/target-module@50000000
1300 05:16:33.859279 # ok 244 /ocp/target-module@53100000
1301 05:16:33.937735 # not ok 245 /ocp/target-module@53100000/sham@0
1302 05:16:33.957760 # ok 246 /ocp/target-module@53500000
1303 05:16:34.037723 # not ok 247 /ocp/target-module@53500000/aes@0
1304 05:16:34.059195 # ok 248 /ocp/target-module@56000000
1305 05:16:34.167421 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1306 05:16:34.251663 # ok 250 /opp-table # SKIP
1307 05:16:34.324602 # ok 251 /soc # SKIP
1308 05:16:34.345009 # ok 252 /sound
1309 05:16:34.365634 # ok 253 /target-module@4b000000
1310 05:16:34.391628 # ok 254 /target-module@4b000000/target-module@140000
1311 05:16:34.413594 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1312 05:16:34.421946 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1313 05:16:34.429977 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1314 05:16:36.638930 dt_test_unprobed_devices_sh_ skip
1315 05:16:36.644108 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1316 05:16:36.649799 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1317 05:16:36.650042 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1318 05:16:36.658352 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1319 05:16:36.658599 dt_test_unprobed_devices_sh_fixedregulator0 pass
1320 05:16:36.664598 dt_test_unprobed_devices_sh_leds pass
1321 05:16:36.670648 dt_test_unprobed_devices_sh_ocp pass
1322 05:16:36.674156 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1323 05:16:36.679211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1324 05:16:36.684868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1325 05:16:36.695803 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1326 05:16:36.701637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1327 05:16:36.707192 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1328 05:16:36.718321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1329 05:16:36.723983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1330 05:16:36.735128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1331 05:16:36.746267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1332 05:16:36.751923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1333 05:16:36.763293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1334 05:16:36.774478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1335 05:16:36.785593 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1336 05:16:36.796571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1337 05:16:36.802327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1338 05:16:36.813903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1339 05:16:36.824751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1340 05:16:36.835974 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1341 05:16:36.847348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1342 05:16:36.853022 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1343 05:16:36.864050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1344 05:16:36.875188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1345 05:16:36.886301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1346 05:16:36.892026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1347 05:16:36.903140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1348 05:16:36.914230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1349 05:16:36.925147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1350 05:16:36.930689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1351 05:16:36.941972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1352 05:16:36.953515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1353 05:16:36.964703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1354 05:16:36.975867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1355 05:16:36.987188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1356 05:16:36.998330 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1357 05:16:37.009445 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1358 05:16:37.020799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1359 05:16:37.031876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1360 05:16:37.043056 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1361 05:16:37.054327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1362 05:16:37.065007 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1363 05:16:37.076305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1364 05:16:37.087350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1365 05:16:37.098524 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1366 05:16:37.110070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1367 05:16:37.121351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1368 05:16:37.132502 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1369 05:16:37.143702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1370 05:16:37.154945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1371 05:16:37.166112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1372 05:16:37.177306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1373 05:16:37.188627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1374 05:16:37.199761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1375 05:16:37.210430 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1376 05:16:37.216179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1377 05:16:37.227621 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1378 05:16:37.238722 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1379 05:16:37.250138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1380 05:16:37.261216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1381 05:16:37.272398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1382 05:16:37.283516 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1383 05:16:37.294817 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1384 05:16:37.305996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1385 05:16:37.316994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1386 05:16:37.328286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1387 05:16:37.339561 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1388 05:16:37.350839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1389 05:16:37.361991 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1390 05:16:37.373015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1391 05:16:37.384057 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1392 05:16:37.395129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1393 05:16:37.406404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1394 05:16:37.412023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1395 05:16:37.423559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1396 05:16:37.434860 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1397 05:16:37.445928 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1398 05:16:37.457195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1399 05:16:37.468008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1400 05:16:37.473905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1401 05:16:37.485262 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1402 05:16:37.496250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1403 05:16:37.507428 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1404 05:16:37.518157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1405 05:16:37.529529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1406 05:16:37.540671 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1407 05:16:37.557791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1408 05:16:37.563371 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1409 05:16:37.574411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1410 05:16:37.585896 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1411 05:16:37.591395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1412 05:16:37.602416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1413 05:16:37.613893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1414 05:16:37.619090 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1415 05:16:37.630508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1416 05:16:37.636134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1417 05:16:37.647254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1418 05:16:37.658039 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1419 05:16:37.669332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1420 05:16:37.674780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1421 05:16:37.686008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1422 05:16:37.703191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1423 05:16:37.714276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1424 05:16:37.725735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1425 05:16:37.736856 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1426 05:16:37.747922 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1427 05:16:37.759234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1428 05:16:37.770407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1429 05:16:37.781720 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1430 05:16:37.797961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1431 05:16:37.809213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1432 05:16:37.820475 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1433 05:16:37.831599 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1434 05:16:37.848925 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1435 05:16:37.859889 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1436 05:16:37.871109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1437 05:16:37.882277 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1438 05:16:37.887927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1439 05:16:37.899086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1440 05:16:37.904610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1441 05:16:37.915864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1442 05:16:37.921383 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1443 05:16:37.932391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1444 05:16:37.937944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1445 05:16:37.949161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1446 05:16:37.954607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1447 05:16:37.965924 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1448 05:16:37.977132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1449 05:16:37.983148 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1450 05:16:37.994214 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1451 05:16:38.005412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1452 05:16:38.010818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1453 05:16:38.022257 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1454 05:16:38.033476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1455 05:16:38.044487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1456 05:16:38.050217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1457 05:16:38.061371 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1458 05:16:38.066620 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1459 05:16:38.072241 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1460 05:16:38.077968 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1461 05:16:38.083467 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1462 05:16:38.089017 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1463 05:16:38.100260 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1464 05:16:38.106039 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1465 05:16:38.117022 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1466 05:16:38.122913 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1467 05:16:38.128514 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1468 05:16:38.139720 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1469 05:16:38.145520 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1470 05:16:38.156388 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1471 05:16:38.162085 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1472 05:16:38.173110 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1473 05:16:38.178940 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1474 05:16:38.190031 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1475 05:16:38.195524 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1476 05:16:38.206547 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1477 05:16:38.212257 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1478 05:16:38.223387 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1479 05:16:38.228771 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1480 05:16:38.239925 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1481 05:16:38.245464 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1482 05:16:38.251283 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1483 05:16:38.262257 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1484 05:16:38.267918 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1485 05:16:38.279103 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1486 05:16:38.284761 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1487 05:16:38.296236 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1488 05:16:38.301622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1489 05:16:38.313109 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1490 05:16:38.318712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1491 05:16:38.324217 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1492 05:16:38.335552 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1493 05:16:38.346357 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1494 05:16:38.357654 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1495 05:16:38.363040 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1496 05:16:38.374217 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1497 05:16:38.385653 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1498 05:16:38.391014 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1499 05:16:38.402267 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1500 05:16:38.407891 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1501 05:16:38.419476 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1502 05:16:38.425088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1503 05:16:38.436267 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1504 05:16:38.441989 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1505 05:16:38.453105 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1506 05:16:38.458358 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1507 05:16:38.469744 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1508 05:16:38.475423 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1509 05:16:38.486533 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1510 05:16:38.491799 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1511 05:16:38.497323 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1512 05:16:38.508526 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1513 05:16:38.514209 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1514 05:16:38.525432 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1515 05:16:38.530974 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1516 05:16:38.542247 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1517 05:16:38.547792 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1518 05:16:38.559332 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1519 05:16:38.564808 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1520 05:16:38.570386 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1521 05:16:38.576358 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1522 05:16:38.587137 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1523 05:16:38.592899 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1524 05:16:38.604312 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1525 05:16:38.609513 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1526 05:16:38.621175 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1527 05:16:38.631998 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1528 05:16:38.643138 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1529 05:16:38.648738 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1530 05:16:38.659969 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1531 05:16:38.671163 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1532 05:16:38.676788 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1533 05:16:38.682373 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1534 05:16:38.688194 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1535 05:16:38.693646 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1536 05:16:38.699231 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1537 05:16:38.704765 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1538 05:16:38.710485 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1539 05:16:38.716158 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1540 05:16:38.727407 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1541 05:16:38.732898 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1542 05:16:38.738646 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1543 05:16:38.744085 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1544 05:16:38.749593 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1545 05:16:38.755236 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1546 05:16:38.760744 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1547 05:16:38.766506 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1548 05:16:38.772008 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1549 05:16:38.777661 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1550 05:16:38.783319 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1551 05:16:38.788825 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1552 05:16:38.794570 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1553 05:16:38.800050 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1554 05:16:38.805648 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1555 05:16:38.811211 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1556 05:16:38.816729 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1557 05:16:38.822540 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1558 05:16:38.827947 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1559 05:16:38.833591 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1560 05:16:38.839218 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1561 05:16:38.844791 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1562 05:16:38.850390 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1563 05:16:38.856068 dt_test_unprobed_devices_sh_opp-table skip
1564 05:16:38.856369 dt_test_unprobed_devices_sh_soc skip
1565 05:16:38.861696 dt_test_unprobed_devices_sh_sound pass
1566 05:16:38.867194 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1567 05:16:38.872800 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1568 05:16:38.878352 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1569 05:16:38.883947 dt_test_unprobed_devices_sh fail
1570 05:16:38.889521 + ../../utils/send-to-lava.sh ./output/result.txt
1571 05:16:38.893695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1572 05:16:38.894169 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1574 05:16:38.938175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1575 05:16:38.938759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1577 05:16:39.036064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1578 05:16:39.036563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1580 05:16:39.125810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1581 05:16:39.126301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1583 05:16:39.217057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1584 05:16:39.217637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1586 05:16:39.305978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1587 05:16:39.306499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1589 05:16:39.393840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1590 05:16:39.394327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1592 05:16:39.486417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1593 05:16:39.486914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1595 05:16:39.571200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1596 05:16:39.571715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1598 05:16:39.659792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1599 05:16:39.660301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1601 05:16:39.748328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1602 05:16:39.748877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1604 05:16:39.832930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1605 05:16:39.833402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1607 05:16:39.914939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1608 05:16:39.915386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1610 05:16:40.005507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1611 05:16:40.005949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1613 05:16:40.090879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1614 05:16:40.091326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1616 05:16:40.180758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1617 05:16:40.181153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1619 05:16:40.265985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1620 05:16:40.266359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1622 05:16:40.353624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1623 05:16:40.354002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1625 05:16:40.436886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1626 05:16:40.437264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1628 05:16:40.524230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1629 05:16:40.524717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1631 05:16:40.613388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1632 05:16:40.613782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1634 05:16:40.701269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1635 05:16:40.701626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1637 05:16:40.787276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1638 05:16:40.787654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1640 05:16:40.877366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1641 05:16:40.877886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1643 05:16:40.964940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1644 05:16:40.965359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1646 05:16:41.052514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1647 05:16:41.052943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1649 05:16:41.138952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1650 05:16:41.139393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1652 05:16:41.227960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1653 05:16:41.228405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1655 05:16:41.318579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1656 05:16:41.319023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1658 05:16:41.403575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1659 05:16:41.404010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1661 05:16:41.490704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1662 05:16:41.491152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1664 05:16:41.579131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1665 05:16:41.579581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1667 05:16:41.665790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1668 05:16:41.666237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1670 05:16:41.746786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1671 05:16:41.747242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1673 05:16:41.827974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1674 05:16:41.828405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1676 05:16:41.917748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1677 05:16:41.918184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1679 05:16:42.014393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1680 05:16:42.014740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1682 05:16:42.107157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1683 05:16:42.107525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1685 05:16:42.191351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1686 05:16:42.191699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1688 05:16:42.277168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1689 05:16:42.277507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1691 05:16:42.366317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1692 05:16:42.366933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1694 05:16:42.451499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1695 05:16:42.451926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1697 05:16:42.540986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1698 05:16:42.541413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1700 05:16:42.628973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1701 05:16:42.629396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1703 05:16:42.716272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1704 05:16:42.716696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1706 05:16:42.804727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1707 05:16:42.805151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1709 05:16:42.888453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1710 05:16:42.888881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1712 05:16:42.974574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1713 05:16:42.975000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1715 05:16:43.055259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1716 05:16:43.055705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1718 05:16:43.144822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1719 05:16:43.145263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1721 05:16:43.229560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1722 05:16:43.229999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1724 05:16:43.318091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1725 05:16:43.318523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1727 05:16:43.400354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1728 05:16:43.400782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1730 05:16:43.485344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1731 05:16:43.485800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1733 05:16:43.572365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1734 05:16:43.572772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1736 05:16:43.656840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1737 05:16:43.657395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1739 05:16:43.749519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1740 05:16:43.750473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1742 05:16:43.834664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1743 05:16:43.835111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1745 05:16:43.957233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1746 05:16:43.957665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1748 05:16:44.050785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1749 05:16:44.051218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1751 05:16:44.136078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1752 05:16:44.136403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1754 05:16:44.223965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1755 05:16:44.224407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1757 05:16:44.308845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1758 05:16:44.309263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1760 05:16:44.397266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1761 05:16:44.397674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1763 05:16:44.484368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1764 05:16:44.484790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1766 05:16:44.571399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1767 05:16:44.571819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1769 05:16:44.657515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1770 05:16:44.657961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1772 05:16:44.738003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1773 05:16:44.738434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1775 05:16:44.817461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1776 05:16:44.817907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1778 05:16:44.903477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1779 05:16:44.903895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1781 05:16:44.984231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1782 05:16:44.984691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1784 05:16:45.072257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1785 05:16:45.072694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1787 05:16:45.157639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1788 05:16:45.158095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1790 05:16:45.238897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1791 05:16:45.239343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1793 05:16:45.325590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1794 05:16:45.325916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1796 05:16:45.406647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1797 05:16:45.407171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1799 05:16:45.488043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1800 05:16:45.488526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1802 05:16:45.574146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1803 05:16:45.574652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1805 05:16:45.663855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1806 05:16:45.664333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1808 05:16:45.752122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1809 05:16:45.752601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1811 05:16:45.839278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1812 05:16:45.839764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1814 05:16:45.928219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1815 05:16:45.928715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1817 05:16:46.017909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1818 05:16:46.018425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1820 05:16:46.103913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1821 05:16:46.104435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1823 05:16:46.191475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1824 05:16:46.191966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1826 05:16:46.277055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1827 05:16:46.277552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1829 05:16:46.364721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1830 05:16:46.365224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1832 05:16:46.452915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1833 05:16:46.453395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1835 05:16:46.541966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1836 05:16:46.542290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1838 05:16:46.628903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1839 05:16:46.629380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1841 05:16:46.717232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1842 05:16:46.717687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1844 05:16:46.804155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1845 05:16:46.804640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1847 05:16:46.891316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1848 05:16:46.891801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1850 05:16:46.981272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1851 05:16:46.981752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1853 05:16:47.068578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1854 05:16:47.069116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1856 05:16:47.153269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1857 05:16:47.153782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1859 05:16:47.238906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1860 05:16:47.239397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1862 05:16:47.326948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1863 05:16:47.327448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1865 05:16:47.414853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1866 05:16:47.415341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1868 05:16:47.495839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1869 05:16:47.496317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1871 05:16:47.582242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1872 05:16:47.582714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1874 05:16:47.671133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1875 05:16:47.671683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1877 05:16:47.758952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1878 05:16:47.759432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1880 05:16:47.846507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1881 05:16:47.847033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1883 05:16:47.932942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1884 05:16:47.933445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1886 05:16:48.015175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1887 05:16:48.015682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1889 05:16:48.104872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1890 05:16:48.105348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1892 05:16:48.189910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1893 05:16:48.190415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1895 05:16:48.278687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1896 05:16:48.279212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1898 05:16:48.359207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1899 05:16:48.359707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1901 05:16:48.446488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1902 05:16:48.447007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1904 05:16:48.538955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1905 05:16:48.539490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1907 05:16:48.627151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1908 05:16:48.627650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1910 05:16:48.708824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1911 05:16:48.709303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1913 05:16:48.795427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1914 05:16:48.795919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1916 05:16:48.878630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1917 05:16:48.879133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1919 05:16:48.966670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1920 05:16:48.967252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1922 05:16:49.055285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1923 05:16:49.055779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1925 05:16:49.141282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1926 05:16:49.141761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1928 05:16:49.231399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1929 05:16:49.231905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1931 05:16:49.317513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1933 05:16:49.320756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1934 05:16:49.404512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1936 05:16:49.407585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1937 05:16:49.490773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1939 05:16:49.494023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1940 05:16:49.576221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1941 05:16:49.576659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1943 05:16:49.662257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1944 05:16:49.662723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1946 05:16:49.742531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1947 05:16:49.742989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1949 05:16:49.822622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1950 05:16:49.823049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1952 05:16:49.908633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1953 05:16:49.909078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1955 05:16:49.993944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1956 05:16:49.994436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1958 05:16:50.079623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1959 05:16:50.080051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1961 05:16:50.165892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1962 05:16:50.166325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1964 05:16:50.253150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1965 05:16:50.253597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1967 05:16:50.339189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1968 05:16:50.339618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1970 05:16:50.423374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1971 05:16:50.423864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1973 05:16:50.509749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1974 05:16:50.510178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1976 05:16:50.597702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1977 05:16:50.598129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1979 05:16:50.680536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1980 05:16:50.680960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1982 05:16:50.769684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1983 05:16:50.770029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1985 05:16:50.855014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1986 05:16:50.855447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1988 05:16:50.942248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
1989 05:16:50.942741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
1991 05:16:51.028327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
1992 05:16:51.028752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
1994 05:16:51.113300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
1995 05:16:51.113736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
1997 05:16:51.191191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
1998 05:16:51.191625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2000 05:16:51.271439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2001 05:16:51.271921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2003 05:16:51.351365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2004 05:16:51.351859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2006 05:16:51.432440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2007 05:16:51.432879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2009 05:16:51.520212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2010 05:16:51.520604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2012 05:16:51.601236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2013 05:16:51.601626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2015 05:16:51.686637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2016 05:16:51.687070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2018 05:16:51.774400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2019 05:16:51.774836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2021 05:16:51.860602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2022 05:16:51.861038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2024 05:16:51.943409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2025 05:16:51.943906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2027 05:16:52.024318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2028 05:16:52.024932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2030 05:16:52.111423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2031 05:16:52.111948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2033 05:16:52.193367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2034 05:16:52.193965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2036 05:16:52.278887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2037 05:16:52.279380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2039 05:16:52.362552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2040 05:16:52.362978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2042 05:16:52.441931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2043 05:16:52.442439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2045 05:16:52.526188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2046 05:16:52.527070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2048 05:16:52.612100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2049 05:16:52.612522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2051 05:16:52.691104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2052 05:16:52.691581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2054 05:16:52.779191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2055 05:16:52.779692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2057 05:16:52.863831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2058 05:16:52.864349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2060 05:16:52.951569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2061 05:16:52.952066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2063 05:16:53.038374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2064 05:16:53.038864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2066 05:16:53.124691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2067 05:16:53.125113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2069 05:16:53.206873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2070 05:16:53.207313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2072 05:16:53.292511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2073 05:16:53.292934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2075 05:16:53.371390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2076 05:16:53.371820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2078 05:16:53.456804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2079 05:16:53.457121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2081 05:16:53.541863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2082 05:16:53.542197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2084 05:16:53.621711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2085 05:16:53.622027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2087 05:16:53.700527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2088 05:16:53.700962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2090 05:16:53.780573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2091 05:16:53.780996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2093 05:16:53.864219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2094 05:16:53.864559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2096 05:16:53.950323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2097 05:16:53.950661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2099 05:16:54.034930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2100 05:16:54.035324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2102 05:16:54.119624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2103 05:16:54.120154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2105 05:16:54.204831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2106 05:16:54.205151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2108 05:16:54.289983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2109 05:16:54.290402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2111 05:16:54.380013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2112 05:16:54.380447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2114 05:16:54.466251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2115 05:16:54.466822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2117 05:16:54.553967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2118 05:16:54.554466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2120 05:16:54.643934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2121 05:16:54.644429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2123 05:16:54.727917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2124 05:16:54.728420 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2126 05:16:54.814909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2127 05:16:54.815344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2129 05:16:54.893902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2130 05:16:54.894332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2132 05:16:54.975018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2133 05:16:54.975548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2135 05:16:55.056060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2136 05:16:55.056496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2138 05:16:55.142748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2139 05:16:55.143165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2141 05:16:55.225350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2142 05:16:55.225868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2144 05:16:55.312349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2145 05:16:55.312859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2147 05:16:55.392068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2148 05:16:55.392402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2150 05:16:55.472052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2151 05:16:55.472553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2153 05:16:55.552657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2154 05:16:55.553155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2156 05:16:55.644605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2157 05:16:55.645040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2159 05:16:55.728748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2160 05:16:55.729207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2162 05:16:55.815687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2163 05:16:55.816126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2165 05:16:55.896088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2166 05:16:55.896513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2168 05:16:55.978906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2169 05:16:55.979422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2171 05:16:56.068061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2172 05:16:56.068503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2174 05:16:56.153464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2175 05:16:56.153947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2177 05:16:56.239355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2178 05:16:56.239792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2180 05:16:56.323894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2181 05:16:56.324329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2183 05:16:56.408369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2184 05:16:56.408799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2186 05:16:56.493744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2187 05:16:56.494175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2189 05:16:56.573370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2190 05:16:56.573838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2192 05:16:56.655420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2193 05:16:56.655848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2195 05:16:56.741921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2196 05:16:56.742440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2198 05:16:56.824553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2199 05:16:56.824977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2201 05:16:56.914278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2202 05:16:56.914768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2204 05:16:57.002311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2205 05:16:57.002805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2207 05:16:57.088537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2208 05:16:57.089032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2210 05:16:57.173948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2211 05:16:57.174441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2213 05:16:57.260460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2214 05:16:57.260893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2216 05:16:57.347411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2217 05:16:57.347844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2219 05:16:57.425401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2220 05:16:57.425877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2222 05:16:57.505655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2223 05:16:57.506155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2225 05:16:57.592267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2226 05:16:57.592691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2228 05:16:57.671122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2229 05:16:57.671554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2231 05:16:57.757109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2232 05:16:57.757603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2234 05:16:57.841143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2235 05:16:57.841582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2237 05:16:57.926163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2238 05:16:57.926597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2240 05:16:58.010719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2241 05:16:58.011154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2243 05:16:58.096381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2244 05:16:58.096710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2246 05:16:58.178844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2248 05:16:58.181933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2249 05:16:58.257874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2250 05:16:58.258315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2252 05:16:58.340304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2253 05:16:58.340737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2255 05:16:58.421916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2256 05:16:58.422351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2258 05:16:58.506773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2259 05:16:58.507203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2261 05:16:58.591265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2262 05:16:58.591695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2264 05:16:58.671467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2265 05:16:58.671888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2267 05:16:58.750953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2268 05:16:58.751462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2270 05:16:58.838109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2271 05:16:58.838631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2273 05:16:58.923825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2274 05:16:58.924327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2276 05:16:59.012025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2277 05:16:59.012464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2279 05:16:59.097194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2280 05:16:59.097630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2282 05:16:59.182599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2283 05:16:59.183100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2285 05:16:59.270233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2286 05:16:59.270568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2288 05:16:59.354874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2289 05:16:59.355377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2291 05:16:59.441980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2292 05:16:59.442335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2294 05:16:59.527158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2295 05:16:59.527713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2297 05:16:59.612118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2298 05:16:59.612448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2300 05:16:59.698273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2301 05:16:59.698778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2303 05:16:59.778292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2304 05:16:59.778728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2306 05:16:59.857387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2307 05:16:59.857845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2309 05:16:59.941626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2310 05:16:59.942058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2312 05:17:00.029328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2313 05:17:00.029911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2315 05:17:00.118167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2316 05:17:00.118621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2318 05:17:00.203017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2319 05:17:00.203559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2321 05:17:00.287966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2322 05:17:00.288458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2324 05:17:00.373922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2325 05:17:00.374441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2327 05:17:00.460776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2328 05:17:00.461257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2330 05:17:00.548525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2331 05:17:00.549033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2333 05:17:00.637517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2334 05:17:00.638052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2336 05:17:00.724382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2337 05:17:00.724820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2339 05:17:00.806408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2340 05:17:00.806643 + set +x
2341 05:17:00.806975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2343 05:17:00.816045 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 681419_1.6.2.4.5>
2344 05:17:00.816164 <LAVA_TEST_RUNNER EXIT>
2345 05:17:00.816395 Received signal: <ENDRUN> 1_kselftest-dt 681419_1.6.2.4.5
2346 05:17:00.816461 Ending use of test pattern.
2347 05:17:00.816514 Ending test lava.1_kselftest-dt (681419_1.6.2.4.5), duration 72.47
2349 05:17:00.816718 ok: lava_test_shell seems to have completed
2350 05:17:00.818832 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2351 05:17:00.819141 end: 3.1 lava-test-shell (duration 00:01:14) [common]
2352 05:17:00.819220 end: 3 lava-test-retry (duration 00:01:14) [common]
2353 05:17:00.819306 start: 4 finalize (timeout 00:06:15) [common]
2354 05:17:00.819385 start: 4.1 power-off (timeout 00:00:30) [common]
2355 05:17:00.819532 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2356 05:17:00.836477 >> OK - accepted request
2357 05:17:00.838381 Returned 0 in 0 seconds
2358 05:17:00.938906 end: 4.1 power-off (duration 00:00:00) [common]
2360 05:17:00.939273 start: 4.2 read-feedback (timeout 00:06:15) [common]
2361 05:17:00.939516 Listened to connection for namespace 'common' for up to 1s
2362 05:17:00.939780 Listened to connection for namespace 'common' for up to 1s
2363 05:17:01.939660 Finalising connection for namespace 'common'
2364 05:17:01.939967 Disconnecting from shell: Finalise
2365 05:17:01.940142 / #
2366 05:17:02.040567 end: 4.2 read-feedback (duration 00:00:01) [common]
2367 05:17:02.040899 end: 4 finalize (duration 00:00:01) [common]
2368 05:17:02.041131 Cleaning after the job
2369 05:17:02.041331 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/ramdisk
2370 05:17:02.048046 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/kernel
2371 05:17:02.053614 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/dtb
2372 05:17:02.054078 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/nfsrootfs
2373 05:17:02.165317 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681419/tftp-deploy-2pbc44hq/modules
2374 05:17:02.171459 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681419
2375 05:17:03.209093 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681419
2376 05:17:03.209320 Job finished correctly