Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 05:34:37.064505 lava-dispatcher, installed at version: 2023.08
2 05:34:37.064829 start: 0 validate
3 05:34:37.065011 Start time: 2024-08-31 05:34:37.064998+00:00 (UTC)
4 05:34:37.065249 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 05:34:37.527483 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 05:34:37.642354 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 05:34:37.757029 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 05:34:37.871135 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 05:34:37.990427 validate duration: 0.93
11 05:34:37.991243 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 05:34:37.991577 start: 1.1 download-retry (timeout 00:10:00) [common]
13 05:34:37.991890 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 05:34:37.992375 Not decompressing ramdisk as can be used compressed.
15 05:34:37.992677 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 05:34:37.992920 saving as /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/ramdisk/initrd.cpio.gz
17 05:34:37.993165 total size: 4775763 (4 MB)
18 05:34:38.221052 progress 0 % (0 MB)
19 05:34:38.558791 progress 5 % (0 MB)
20 05:34:38.785103 progress 10 % (0 MB)
21 05:34:38.806829 progress 15 % (0 MB)
22 05:34:38.900133 progress 20 % (0 MB)
23 05:34:38.922261 progress 25 % (1 MB)
24 05:34:39.027624 progress 30 % (1 MB)
25 05:34:39.134342 progress 35 % (1 MB)
26 05:34:39.233940 progress 40 % (1 MB)
27 05:34:39.258314 progress 45 % (2 MB)
28 05:34:39.362155 progress 50 % (2 MB)
29 05:34:39.465524 progress 55 % (2 MB)
30 05:34:39.490034 progress 60 % (2 MB)
31 05:34:39.593088 progress 65 % (2 MB)
32 05:34:39.696447 progress 70 % (3 MB)
33 05:34:39.717643 progress 75 % (3 MB)
34 05:34:39.818379 progress 80 % (3 MB)
35 05:34:39.913414 progress 85 % (3 MB)
36 05:34:39.941478 progress 90 % (4 MB)
37 05:34:40.043594 progress 95 % (4 MB)
38 05:34:40.134580 progress 100 % (4 MB)
39 05:34:40.135357 4 MB downloaded in 2.14 s (2.13 MB/s)
40 05:34:40.135837 end: 1.1.1 http-download (duration 00:00:02) [common]
42 05:34:40.136711 end: 1.1 download-retry (duration 00:00:02) [common]
43 05:34:40.137006 start: 1.2 download-retry (timeout 00:09:58) [common]
44 05:34:40.137291 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 05:34:40.137697 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 05:34:40.137926 saving as /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/kernel/zImage
47 05:34:40.138144 total size: 11354624 (10 MB)
48 05:34:40.138366 No compression specified
49 05:34:40.258499 progress 0 % (0 MB)
50 05:34:40.498539 progress 5 % (0 MB)
51 05:34:40.720588 progress 10 % (1 MB)
52 05:34:40.948414 progress 15 % (1 MB)
53 05:34:41.177571 progress 20 % (2 MB)
54 05:34:41.399981 progress 25 % (2 MB)
55 05:34:41.620443 progress 30 % (3 MB)
56 05:34:41.844016 progress 35 % (3 MB)
57 05:34:42.063723 progress 40 % (4 MB)
58 05:34:42.282452 progress 45 % (4 MB)
59 05:34:42.504059 progress 50 % (5 MB)
60 05:34:42.638928 progress 55 % (5 MB)
61 05:34:42.856601 progress 60 % (6 MB)
62 05:34:43.077150 progress 65 % (7 MB)
63 05:34:43.293575 progress 70 % (7 MB)
64 05:34:43.507052 progress 75 % (8 MB)
65 05:34:43.842517 progress 80 % (8 MB)
66 05:34:43.966600 progress 85 % (9 MB)
67 05:34:44.207254 progress 90 % (9 MB)
68 05:34:44.519832 progress 95 % (10 MB)
69 05:34:44.752268 progress 100 % (10 MB)
70 05:34:44.752916 10 MB downloaded in 4.61 s (2.35 MB/s)
71 05:34:44.753366 end: 1.2.1 http-download (duration 00:00:05) [common]
73 05:34:44.754177 end: 1.2 download-retry (duration 00:00:05) [common]
74 05:34:44.754476 start: 1.3 download-retry (timeout 00:09:53) [common]
75 05:34:44.754764 start: 1.3.1 http-download (timeout 00:09:53) [common]
76 05:34:44.755159 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 05:34:44.755389 saving as /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/dtb/am335x-boneblack.dtb
78 05:34:44.755609 total size: 70308 (0 MB)
79 05:34:44.755828 No compression specified
80 05:34:44.872247 progress 46 % (0 MB)
81 05:34:44.875059 progress 93 % (0 MB)
82 05:34:44.876043 progress 100 % (0 MB)
83 05:34:44.876454 0 MB downloaded in 0.12 s (0.55 MB/s)
84 05:34:44.876863 end: 1.3.1 http-download (duration 00:00:00) [common]
86 05:34:44.877660 end: 1.3 download-retry (duration 00:00:00) [common]
87 05:34:44.877944 start: 1.4 download-retry (timeout 00:09:53) [common]
88 05:34:44.878230 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 05:34:44.878589 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 05:34:44.878813 saving as /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/nfsrootfs/full.rootfs.tar
91 05:34:44.879027 total size: 117747780 (112 MB)
92 05:34:44.879248 Using unxz to decompress xz
93 05:34:44.996171 progress 0 % (0 MB)
94 05:34:48.381075 progress 5 % (5 MB)
95 05:34:51.509142 progress 10 % (11 MB)
96 05:34:54.219006 progress 15 % (16 MB)
97 05:34:56.221793 progress 20 % (22 MB)
98 05:34:57.656232 progress 25 % (28 MB)
99 05:34:58.710137 progress 30 % (33 MB)
100 05:34:59.592228 progress 35 % (39 MB)
101 05:35:00.313261 progress 40 % (44 MB)
102 05:35:00.961978 progress 45 % (50 MB)
103 05:35:01.524655 progress 50 % (56 MB)
104 05:35:02.033934 progress 55 % (61 MB)
105 05:35:02.603751 progress 60 % (67 MB)
106 05:35:03.212182 progress 65 % (73 MB)
107 05:35:03.783238 progress 70 % (78 MB)
108 05:35:04.493711 progress 75 % (84 MB)
109 05:35:05.220916 progress 80 % (89 MB)
110 05:35:05.931049 progress 85 % (95 MB)
111 05:35:06.614684 progress 90 % (101 MB)
112 05:35:07.281519 progress 95 % (106 MB)
113 05:35:07.939361 progress 100 % (112 MB)
114 05:35:07.943249 112 MB downloaded in 23.06 s (4.87 MB/s)
115 05:35:07.943624 end: 1.4.1 http-download (duration 00:00:23) [common]
117 05:35:07.944291 end: 1.4 download-retry (duration 00:00:23) [common]
118 05:35:07.944508 start: 1.5 download-retry (timeout 00:09:30) [common]
119 05:35:07.944719 start: 1.5.1 http-download (timeout 00:09:30) [common]
120 05:35:07.945028 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 05:35:07.945196 saving as /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/modules/modules.tar
122 05:35:07.945356 total size: 6610728 (6 MB)
123 05:35:07.945519 Using unxz to decompress xz
124 05:35:08.061623 progress 0 % (0 MB)
125 05:35:08.292613 progress 5 % (0 MB)
126 05:35:08.511157 progress 10 % (0 MB)
127 05:35:08.537022 progress 15 % (0 MB)
128 05:35:08.561576 progress 20 % (1 MB)
129 05:35:08.639607 progress 25 % (1 MB)
130 05:35:08.764251 progress 30 % (1 MB)
131 05:35:08.790248 progress 35 % (2 MB)
132 05:35:08.867724 progress 40 % (2 MB)
133 05:35:08.977804 progress 45 % (2 MB)
134 05:35:09.088055 progress 50 % (3 MB)
135 05:35:09.196882 progress 55 % (3 MB)
136 05:35:09.307933 progress 60 % (3 MB)
137 05:35:09.415550 progress 65 % (4 MB)
138 05:35:09.523484 progress 70 % (4 MB)
139 05:35:09.558510 progress 75 % (4 MB)
140 05:35:09.670346 progress 80 % (5 MB)
141 05:35:09.776981 progress 85 % (5 MB)
142 05:35:09.881942 progress 90 % (5 MB)
143 05:35:09.988043 progress 95 % (6 MB)
144 05:35:10.089919 progress 100 % (6 MB)
145 05:35:10.095975 6 MB downloaded in 2.15 s (2.93 MB/s)
146 05:35:10.096412 end: 1.5.1 http-download (duration 00:00:02) [common]
148 05:35:10.097183 end: 1.5 download-retry (duration 00:00:02) [common]
149 05:35:10.097448 start: 1.6 prepare-tftp-overlay (timeout 00:09:28) [common]
150 05:35:10.097720 start: 1.6.1 extract-nfsrootfs (timeout 00:09:28) [common]
151 05:35:15.603565 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1186402/extract-nfsrootfs-zvh23sor
152 05:35:15.603874 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 05:35:15.604025 start: 1.6.2 lava-overlay (timeout 00:09:22) [common]
154 05:35:15.604356 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6
155 05:35:15.604555 makedir: /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin
156 05:35:15.604699 makedir: /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/tests
157 05:35:15.604852 makedir: /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/results
158 05:35:15.605013 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-add-keys
159 05:35:15.605254 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-add-sources
160 05:35:15.605435 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-background-process-start
161 05:35:15.605613 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-background-process-stop
162 05:35:15.605803 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-common-functions
163 05:35:15.605978 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-echo-ipv4
164 05:35:15.606152 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-install-packages
165 05:35:15.606324 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-installed-packages
166 05:35:15.606494 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-os-build
167 05:35:15.606665 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-probe-channel
168 05:35:15.606834 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-probe-ip
169 05:35:15.607007 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-target-ip
170 05:35:15.607177 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-target-mac
171 05:35:15.607347 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-target-storage
172 05:35:15.607520 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-test-case
173 05:35:15.607691 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-test-event
174 05:35:15.607859 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-test-feedback
175 05:35:15.608027 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-test-raise
176 05:35:15.608216 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-test-reference
177 05:35:15.608397 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-test-runner
178 05:35:15.608566 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-test-set
179 05:35:15.608736 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-test-shell
180 05:35:15.608933 Updating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-add-keys (debian)
181 05:35:15.636027 Updating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-add-sources (debian)
182 05:35:15.636497 Updating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-install-packages (debian)
183 05:35:15.636902 Updating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-installed-packages (debian)
184 05:35:15.637299 Updating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/bin/lava-os-build (debian)
185 05:35:15.637649 Creating /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/environment
186 05:35:15.637920 LAVA metadata
187 05:35:15.638130 - LAVA_JOB_ID=1186402
188 05:35:15.638333 - LAVA_DISPATCHER_IP=192.168.11.5
189 05:35:15.638621 start: 1.6.2.1 ssh-authorize (timeout 00:09:22) [common]
190 05:35:15.639270 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 05:35:15.639519 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:22) [common]
192 05:35:15.639703 skipped lava-vland-overlay
193 05:35:15.639935 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 05:35:15.640171 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:22) [common]
195 05:35:15.640407 skipped lava-multinode-overlay
196 05:35:15.640664 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 05:35:15.640924 start: 1.6.2.4 test-definition (timeout 00:09:22) [common]
198 05:35:15.641132 Loading test definitions
199 05:35:15.641401 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:22) [common]
200 05:35:15.641612 Using /lava-1186402 at stage 0
201 05:35:15.642440 uuid=1186402_1.6.2.4.1 testdef=None
202 05:35:15.642708 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 05:35:15.642964 start: 1.6.2.4.2 test-overlay (timeout 00:09:22) [common]
204 05:35:15.644214 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 05:35:15.644914 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:22) [common]
207 05:35:15.671596 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 05:35:15.672453 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:22) [common]
210 05:35:15.707508 runner path: /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/0/tests/0_timesync-off test_uuid 1186402_1.6.2.4.1
211 05:35:15.707981 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 05:35:15.708835 start: 1.6.2.4.5 git-repo-action (timeout 00:09:22) [common]
214 05:35:15.709067 Using /lava-1186402 at stage 0
215 05:35:15.709389 Fetching tests from https://github.com/kernelci/test-definitions.git
216 05:35:15.709630 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/0/tests/1_kselftest-dt'
217 05:35:20.627496 Running '/usr/bin/git checkout kernelci.org
218 05:35:20.847309 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 05:35:20.848134 uuid=1186402_1.6.2.4.5 testdef=None
220 05:35:20.848368 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 05:35:20.848831 start: 1.6.2.4.6 test-overlay (timeout 00:09:17) [common]
223 05:35:20.850372 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 05:35:20.850854 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:17) [common]
226 05:35:20.852980 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 05:35:20.853484 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:17) [common]
229 05:35:20.855537 runner path: /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/0/tests/1_kselftest-dt test_uuid 1186402_1.6.2.4.5
230 05:35:20.855701 BOARD='beaglebone-black'
231 05:35:20.855834 BRANCH='mainline'
232 05:35:20.855962 SKIPFILE='/dev/null'
233 05:35:20.856087 SKIP_INSTALL='True'
234 05:35:20.856229 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 05:35:20.856342 TST_CASENAME=''
236 05:35:20.856430 TST_CMDFILES='dt'
237 05:35:20.856623 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 05:35:20.856938 Creating lava-test-runner.conf files
240 05:35:20.857026 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1186402/lava-overlay-u_mk5pg6/lava-1186402/0 for stage 0
241 05:35:20.857150 - 0_timesync-off
242 05:35:20.857241 - 1_kselftest-dt
243 05:35:20.857372 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 05:35:20.857489 start: 1.6.2.5 compress-overlay (timeout 00:09:17) [common]
245 05:35:29.336794 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 05:35:29.336997 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:09) [common]
247 05:35:29.337143 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 05:35:29.337290 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 05:35:29.337435 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:09) [common]
250 05:35:29.462493 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 05:35:29.462965 start: 1.6.4 extract-modules (timeout 00:09:09) [common]
252 05:35:29.463172 extracting modules file /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1186402/extract-nfsrootfs-zvh23sor
253 05:35:29.764291 extracting modules file /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1186402/extract-overlay-ramdisk-nz4zap28/ramdisk
254 05:35:30.067451 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 05:35:30.067672 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
256 05:35:30.067807 [common] Applying overlay to NFS
257 05:35:30.067915 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1186402/compress-overlay-69mzb_u3/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1186402/extract-nfsrootfs-zvh23sor
258 05:35:31.278491 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 05:35:31.278700 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
260 05:35:31.278827 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
261 05:35:31.278957 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 05:35:31.279077 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 05:35:31.279199 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
264 05:35:31.279315 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 05:35:31.279433 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
266 05:35:31.279534 Building ramdisk /var/lib/lava/dispatcher/tmp/1186402/extract-overlay-ramdisk-nz4zap28/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1186402/extract-overlay-ramdisk-nz4zap28/ramdisk
267 05:35:31.588920 >> 74798 blocks
268 05:35:33.528945 Adding RAMdisk u-boot header.
269 05:35:33.529218 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1186402/extract-overlay-ramdisk-nz4zap28/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1186402/extract-overlay-ramdisk-nz4zap28/ramdisk.cpio.gz.uboot
270 05:35:33.681849 output: Image Name:
271 05:35:33.682169 output: Created: Sat Aug 31 05:35:33 2024
272 05:35:33.682365 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 05:35:33.682551 output: Data Size: 14792785 Bytes = 14446.08 KiB = 14.11 MiB
274 05:35:33.682733 output: Load Address: 00000000
275 05:35:33.682910 output: Entry Point: 00000000
276 05:35:33.683087 output:
277 05:35:33.683373 rename /var/lib/lava/dispatcher/tmp/1186402/extract-overlay-ramdisk-nz4zap28/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/ramdisk/ramdisk.cpio.gz.uboot
278 05:35:33.683675 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 05:35:33.683923 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
280 05:35:33.684167 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:04) [common]
281 05:35:33.684410 No LXC device requested
282 05:35:33.684665 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 05:35:33.684928 start: 1.8 deploy-device-env (timeout 00:09:04) [common]
284 05:35:33.685181 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 05:35:33.685385 Checking files for TFTP limit of 4294967296 bytes.
286 05:35:33.686621 end: 1 tftp-deploy (duration 00:00:56) [common]
287 05:35:33.686896 start: 2 uboot-action (timeout 00:05:00) [common]
288 05:35:33.687163 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 05:35:33.687417 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 05:35:33.687676 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 05:35:33.688057 substitutions:
292 05:35:33.688287 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 05:35:33.688498 - {DTB_ADDR}: 0x88000000
294 05:35:33.688696 - {DTB}: 1186402/tftp-deploy-0oo8el0h/dtb/am335x-boneblack.dtb
295 05:35:33.688895 - {INITRD}: 1186402/tftp-deploy-0oo8el0h/ramdisk/ramdisk.cpio.gz.uboot
296 05:35:33.689091 - {KERNEL_ADDR}: 0x82000000
297 05:35:33.689287 - {KERNEL}: 1186402/tftp-deploy-0oo8el0h/kernel/zImage
298 05:35:33.689481 - {LAVA_MAC}: None
299 05:35:33.689687 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1186402/extract-nfsrootfs-zvh23sor
300 05:35:33.689883 - {NFS_SERVER_IP}: 192.168.11.5
301 05:35:33.690075 - {PRESEED_CONFIG}: None
302 05:35:33.690265 - {PRESEED_LOCAL}: None
303 05:35:33.690455 - {RAMDISK_ADDR}: 0x83000000
304 05:35:33.690645 - {RAMDISK}: 1186402/tftp-deploy-0oo8el0h/ramdisk/ramdisk.cpio.gz.uboot
305 05:35:33.690835 - {ROOT_PART}: None
306 05:35:33.691023 - {ROOT}: None
307 05:35:33.691210 - {SERVER_IP}: 192.168.11.5
308 05:35:33.691397 - {TEE_ADDR}: 0x83000000
309 05:35:33.691584 - {TEE}: None
310 05:35:33.691771 Parsed boot commands:
311 05:35:33.691954 - setenv autoload no
312 05:35:33.692141 - setenv initrd_high 0xffffffff
313 05:35:33.692342 - setenv fdt_high 0xffffffff
314 05:35:33.692528 - dhcp
315 05:35:33.692713 - setenv serverip 192.168.11.5
316 05:35:33.692898 - tftp 0x82000000 1186402/tftp-deploy-0oo8el0h/kernel/zImage
317 05:35:33.693085 - tftp 0x83000000 1186402/tftp-deploy-0oo8el0h/ramdisk/ramdisk.cpio.gz.uboot
318 05:35:33.693275 - setenv initrd_size ${filesize}
319 05:35:33.693462 - tftp 0x88000000 1186402/tftp-deploy-0oo8el0h/dtb/am335x-boneblack.dtb
320 05:35:33.693650 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186402/extract-nfsrootfs-zvh23sor,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 05:35:33.693844 - bootz 0x82000000 0x83000000 0x88000000
322 05:35:33.694087 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 05:35:33.694779 start: 2.3 connect-device (timeout 00:05:00) [common]
325 05:35:33.694979 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 05:35:34.054613 Setting prompt string to ['lava-test: # ']
327 05:35:34.055027 end: 2.3 connect-device (duration 00:00:00) [common]
328 05:35:34.055197 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 05:35:34.055360 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 05:35:34.055532 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 05:35:34.055869 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 05:35:34.420793 Returned 0 in 0 seconds
333 05:35:34.521647 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 05:35:34.522519 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 05:35:34.522830 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 05:35:34.523111 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 05:35:34.523362 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 05:35:34.524095 Trying 127.0.0.1...
340 05:35:34.524363 Connected to 127.0.0.1.
341 05:35:34.524581 Escape character is '^]'.
342 05:35:39.361809
343 05:35:39.365439 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 05:35:39.421953 Trying to boot from MMC2
345 05:35:39.470415 Loading Environment from EXT4... Card did not respond to voltage select!
346 05:35:39.537462
347 05:35:39.537738
348 05:35:39.543068 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 05:35:39.543345
350 05:35:39.547995 CPU : AM335X-GP rev 2.1
351 05:35:39.601875 I2C: ready
352 05:35:39.602141 DRAM: 512 MiB
353 05:35:39.656284 No match for driver 'omap_hsmmc'
354 05:35:39.661801 No match for driver 'omap_hsmmc'
355 05:35:39.662078 Some drivers were not found
356 05:35:39.668176 Reset Source: Power-on reset has occurred.
357 05:35:39.668472 RTC 32KCLK Source: External.
358 05:35:39.675603 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 05:35:39.688977 Loading Environment from EXT4... Card did not respond to voltage select!
360 05:35:39.753438 Board: BeagleBone Black
361 05:35:39.757210 <ethaddr> not set. Validating first E-fuse MAC
362 05:35:39.813971 BeagleBone Black:
363 05:35:39.814246 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 05:35:39.819577 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 05:35:39.825451 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 05:35:39.825725 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 05:35:39.830518 Net: eth0: MII MODE
368 05:35:39.839906 cpsw, usb_ether
369 05:35:39.840179 Press SPACE to abort autoboot in 2 seconds
370 05:35:39.891005 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 05:35:39.891362 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 05:35:39.891631 Setting prompt string to ['=> ']
373 05:35:39.891891 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 05:35:39.895285 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 05:35:39.895592 Sending with 10 millisecond of delay
377 05:35:41.030153 => setenv autoload no
378 05:35:41.040674 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 05:35:41.043013 setenv autoload no
380 05:35:41.043483 Sending with 10 millisecond of delay
382 05:35:42.840384 => setenv initrd_high 0xffffffff
383 05:35:42.850885 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 05:35:42.851364 setenv initrd_high 0xffffffff
385 05:35:42.851814 Sending with 10 millisecond of delay
387 05:35:44.467958 => setenv fdt_high 0xffffffff
388 05:35:44.478506 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 05:35:44.478956 setenv fdt_high 0xffffffff
390 05:35:44.479401 Sending with 10 millisecond of delay
392 05:35:44.770854 => dhcp
393 05:35:44.781327 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 05:35:44.781796 dhcp
395 05:35:44.782028 link up on port 0, speed 100, full duplex
396 05:35:44.782248 BOOTP broadcast 1
397 05:35:44.790197 DHCP client bound to address 192.168.11.7 (4 ms)
398 05:35:44.790679 Sending with 10 millisecond of delay
400 05:35:46.527487 => setenv serverip 192.168.11.5
401 05:35:46.537970 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 05:35:46.538445 setenv serverip 192.168.11.5
403 05:35:46.538895 Sending with 10 millisecond of delay
405 05:35:50.081761 => tftp 0x82000000 1186402/tftp-deploy-0oo8el0h/kernel/zImage
406 05:35:50.092259 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 05:35:50.092795 tftp 0x82000000 1186402/tftp-deploy-0oo8el0h/kernel/zImage
408 05:35:50.093091 link up on port 0, speed 100, full duplex
409 05:35:50.093360 Using cpsw device
410 05:35:50.096599 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
411 05:35:50.102143 Filename '1186402/tftp-deploy-0oo8el0h/kernel/zImage'.
412 05:35:50.200432 Load address: 0x82000000
413 05:35:50.287390 Loading: *#################################################################
414 05:35:50.457195 #################################################################
415 05:35:50.627159 #################################################################
416 05:35:50.818447 #################################################################
417 05:35:50.990297 #################################################################
418 05:35:51.166748 #################################################################
419 05:35:51.325732 #################################################################
420 05:35:51.494944 #################################################################
421 05:35:51.688449 #################################################################
422 05:35:51.861583 #################################################################
423 05:35:52.036441 #################################################################
424 05:35:52.185797 ###########################################################
425 05:35:52.186183 5.2 MiB/s
426 05:35:52.186413 done
427 05:35:52.189260 Bytes transferred = 11354624 (ad4200 hex)
428 05:35:52.189783 Sending with 10 millisecond of delay
430 05:35:56.696524 => tftp 0x83000000 1186402/tftp-deploy-0oo8el0h/ramdisk/ramdisk.cpio.gz.uboot
431 05:35:56.707054 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
432 05:35:56.707567 tftp 0x83000000 1186402/tftp-deploy-0oo8el0h/ramdisk/ramdisk.cpio.gz.uboot
433 05:35:56.707828 link up on port 0, speed 100, full duplex
434 05:35:56.708075 Using cpsw device
435 05:35:56.711287 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
436 05:35:56.774300 Filename '1186402/tftp-deploy-0oo8el0h/ramdisk/ramdisk.cpio.gz.uboot'.
437 05:35:56.774570 Load address: 0x83000000
438 05:35:56.905829 Loading: *#################################################################
439 05:35:57.080826 #################################################################
440 05:35:57.266823 #################################################################
441 05:35:57.439863 #################################################################
442 05:35:57.628387 #################################################################
443 05:35:57.799359 #################################################################
444 05:35:57.967412 #################################################################
445 05:35:58.141842 #################################################################
446 05:35:58.317113 #################################################################
447 05:35:58.492062 #################################################################
448 05:35:58.687123 #################################################################
449 05:35:58.863045 #################################################################
450 05:35:59.038407 #################################################################
451 05:35:59.213685 #################################################################
452 05:35:59.389033 #################################################################
453 05:35:59.474013 #################################
454 05:35:59.474271 5.1 MiB/s
455 05:35:59.474500 done
456 05:35:59.476882 Bytes transferred = 14792849 (e1b891 hex)
457 05:35:59.477376 Sending with 10 millisecond of delay
459 05:36:01.334354 => setenv initrd_size ${filesize}
460 05:36:01.344862 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
461 05:36:01.345330 setenv initrd_size ${filesize}
462 05:36:01.345778 Sending with 10 millisecond of delay
464 05:36:05.551651 => tftp 0x88000000 1186402/tftp-deploy-0oo8el0h/dtb/am335x-boneblack.dtb
465 05:36:05.562118 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
466 05:36:05.562568 tftp 0x88000000 1186402/tftp-deploy-0oo8el0h/dtb/am335x-boneblack.dtb
467 05:36:05.562802 link up on port 0, speed 100, full duplex
468 05:36:05.563016 Using cpsw device
469 05:36:05.566400 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
470 05:36:05.591145 Filename '1186402/tftp-deploy-0oo8el0h/dtb/am335x-boneblack.dtb'.
471 05:36:05.591434 Load address: 0x88000000
472 05:36:05.591695 Loading: *#####
473 05:36:05.591947 4.8 MiB/s
474 05:36:05.597940 done
475 05:36:05.598164 Bytes transferred = 70308 (112a4 hex)
476 05:36:05.598589 Sending with 10 millisecond of delay
478 05:36:18.897460 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186402/extract-nfsrootfs-zvh23sor,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 05:36:18.907954 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
480 05:36:18.908440 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186402/extract-nfsrootfs-zvh23sor,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 05:36:18.908898 Sending with 10 millisecond of delay
483 05:36:21.247609 => bootz 0x82000000 0x83000000 0x88000000
484 05:36:21.258110 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
485 05:36:21.258484 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
486 05:36:21.259138 bootz 0x82000000 0x83000000 0x88000000
487 05:36:21.259454 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 05:36:21.259980 Image Name:
489 05:36:21.260257 Created: 2024-08-31 5:35:33 UTC
490 05:36:21.265324 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 05:36:21.270975 Data Size: 14792785 Bytes = 14.1 MiB
492 05:36:21.271344 Load Address: 00000000
493 05:36:21.278069 Entry Point: 00000000
494 05:36:21.415392 Verifying Checksum ... OK
495 05:36:21.415675 ## Flattened Device Tree blob at 88000000
496 05:36:21.421855 Booting using the fdt blob at 0x88000000
497 05:36:21.426778 Using Device Tree in place at 88000000, end 880142a3
498 05:36:21.434442
499 05:36:21.434728 Starting kernel ...
500 05:36:21.435002
501 05:36:21.435601 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 05:36:21.435949 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
503 05:36:21.436244 Setting prompt string to ['Linux version [0-9]']
504 05:36:21.436538 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
505 05:36:21.436827 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
506 05:36:22.266882 [ 0.000000] Booting Linux on physical CPU 0x0
507 05:36:22.273233 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
508 05:36:22.273620 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 05:36:22.273919 Setting prompt string to []
510 05:36:22.274231 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 05:36:22.274520 Using line separator: #'\n'#
512 05:36:22.274775 No login prompt set.
513 05:36:22.275053 Parsing kernel messages
514 05:36:22.275301 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 05:36:22.275739 [login-action] Waiting for messages, (timeout 00:04:11)
516 05:36:22.289862 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j302843-arm-gcc-12-multi-v7-defconfig-hz8dc) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sat Aug 31 04:47:30 UTC 2024
517 05:36:22.295443 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
518 05:36:22.301210 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
519 05:36:22.312664 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
520 05:36:22.318316 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
521 05:36:22.324062 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
522 05:36:22.324361 [ 0.000000] Memory policy: Data cache writeback
523 05:36:22.330811 [ 0.000000] efi: UEFI not found.
524 05:36:22.336252 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
525 05:36:22.342045 [ 0.000000] Zone ranges:
526 05:36:22.347699 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
527 05:36:22.353455 [ 0.000000] Normal empty
528 05:36:22.353735 [ 0.000000] HighMem empty
529 05:36:22.359095 [ 0.000000] Movable zone start for each node
530 05:36:22.359378 [ 0.000000] Early memory node ranges
531 05:36:22.370694 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
532 05:36:22.375865 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
533 05:36:22.400773 [ 0.000000] CPU: All CPU(s) started in SVC mode.
534 05:36:22.406248 [ 0.000000] AM335X ES2.1 (sgx neon)
535 05:36:22.417940 [ 0.000000] percpu: Embedded 17 pages/cpu s40332 r8192 d21108 u69632
536 05:36:22.438442 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186402/extract-nfsrootfs-zvh23sor,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
537 05:36:22.444333 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
538 05:36:22.455705 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
539 05:36:22.461458 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
540 05:36:22.468885 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
541 05:36:22.497835 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
542 05:36:22.503813 <6>[ 0.000000] trace event string verifier disabled
543 05:36:22.504096 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
544 05:36:22.509562 <6>[ 0.000000] rcu: RCU event tracing is enabled.
545 05:36:22.520951 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
546 05:36:22.526683 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
547 05:36:22.533969 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
548 05:36:22.549086 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
549 05:36:22.566035 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
550 05:36:22.572735 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
551 05:36:22.664817 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
552 05:36:22.676259 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
553 05:36:22.682879 <6>[ 0.008335] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
554 05:36:22.696063 <6>[ 0.019134] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
555 05:36:22.703386 <6>[ 0.033870] Console: colour dummy device 80x30
556 05:36:22.709405 Matched prompt #6: WARNING:
557 05:36:22.709696 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
558 05:36:22.714812 <3>[ 0.038769] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
559 05:36:22.720762 <3>[ 0.045837] This ensures that you still see kernel messages. Please
560 05:36:22.723899 <3>[ 0.052558] update your kernel commandline.
561 05:36:22.764700 <6>[ 0.057168] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
562 05:36:22.770384 <6>[ 0.096137] CPU: Testing write buffer coherency: ok
563 05:36:22.776184 <6>[ 0.101500] CPU0: Spectre v2: using BPIALL workaround
564 05:36:22.776476 <6>[ 0.106963] pid_max: default: 32768 minimum: 301
565 05:36:22.787691 <6>[ 0.112146] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 05:36:22.794584 <6>[ 0.119967] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 05:36:22.801554 <6>[ 0.129252] CPU0: thread -1, cpu 0, socket -1, mpidr 0
568 05:36:22.809945 <6>[ 0.136108] Setting up static identity map for 0x80300000 - 0x803000ac
569 05:36:22.815709 <6>[ 0.145671] rcu: Hierarchical SRCU implementation.
570 05:36:22.823229 <6>[ 0.150950] rcu: Max phase no-delay instances is 1000.
571 05:36:22.831720 <6>[ 0.161939] EFI services will not be available.
572 05:36:22.837506 <6>[ 0.167186] smp: Bringing up secondary CPUs ...
573 05:36:22.843242 <6>[ 0.172222] smp: Brought up 1 node, 1 CPU
574 05:36:22.848991 <6>[ 0.176623] SMP: Total of 1 processors activated (996.14 BogoMIPS).
575 05:36:22.854989 <6>[ 0.183378] CPU: All CPU(s) started in SVC mode.
576 05:36:22.875108 <6>[ 0.188553] Memory: 407012K/522240K available (16384K kernel code, 2540K rwdata, 6736K rodata, 2048K init, 430K bss, 48024K reserved, 65536K cma-reserved, 0K highmem)
577 05:36:22.875389 <6>[ 0.204791] devtmpfs: initialized
578 05:36:22.897055 <6>[ 0.221547] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
579 05:36:22.908700 <6>[ 0.230116] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
580 05:36:22.914482 <6>[ 0.240552] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
581 05:36:22.925265 <6>[ 0.252891] pinctrl core: initialized pinctrl subsystem
582 05:36:22.934486 <6>[ 0.263540] DMI not present or invalid.
583 05:36:22.942888 <6>[ 0.269284] NET: Registered PF_NETLINK/PF_ROUTE protocol family
584 05:36:22.952238 <6>[ 0.278200] DMA: preallocated 256 KiB pool for atomic coherent allocations
585 05:36:22.967105 <6>[ 0.289537] thermal_sys: Registered thermal governor 'step_wise'
586 05:36:22.967339 <6>[ 0.289675] cpuidle: using governor menu
587 05:36:22.994591 <6>[ 0.325126] No ATAGs?
588 05:36:23.000736 <6>[ 0.327767] hw-breakpoint: debug architecture 0x4 unsupported.
589 05:36:23.010888 <6>[ 0.339715] Serial: AMBA PL011 UART driver
590 05:36:23.052341 <6>[ 0.382864] iommu: Default domain type: Translated
591 05:36:23.061379 <6>[ 0.388095] iommu: DMA domain TLB invalidation policy: strict mode
592 05:36:23.071357 <5>[ 0.400574] SCSI subsystem initialized
593 05:36:23.095446 <6>[ 0.420291] usbcore: registered new interface driver usbfs
594 05:36:23.102305 <6>[ 0.426245] usbcore: registered new interface driver hub
595 05:36:23.102556 <6>[ 0.432068] usbcore: registered new device driver usb
596 05:36:23.108050 <6>[ 0.438555] pps_core: LinuxPPS API ver. 1 registered
597 05:36:23.119542 <6>[ 0.443984] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
598 05:36:23.124744 <6>[ 0.453680] PTP clock support registered
599 05:36:23.149761 <6>[ 0.479569] EDAC MC: Ver: 3.0.0
600 05:36:23.168671 <6>[ 0.496595] scmi_core: SCMI protocol bus registered
601 05:36:23.183842 <6>[ 0.513863] vgaarb: loaded
602 05:36:23.196225 <6>[ 0.526802] clocksource: Switched to clocksource dmtimer
603 05:36:23.232338 <6>[ 0.562514] NET: Registered PF_INET protocol family
604 05:36:23.244948 <6>[ 0.568175] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
605 05:36:23.250670 <6>[ 0.577009] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
606 05:36:23.262039 <6>[ 0.585902] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
607 05:36:23.267916 <6>[ 0.594172] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
608 05:36:23.279469 <6>[ 0.602459] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
609 05:36:23.285315 <6>[ 0.610177] TCP: Hash tables configured (established 4096 bind 4096)
610 05:36:23.291043 <6>[ 0.617093] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
611 05:36:23.296936 <6>[ 0.624104] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
612 05:36:23.304469 <6>[ 0.631713] NET: Registered PF_UNIX/PF_LOCAL protocol family
613 05:36:23.341293 <6>[ 0.666141] RPC: Registered named UNIX socket transport module.
614 05:36:23.341584 <6>[ 0.672563] RPC: Registered udp transport module.
615 05:36:23.347043 <6>[ 0.677696] RPC: Registered tcp transport module.
616 05:36:23.352814 <6>[ 0.682799] RPC: Registered tcp-with-tls transport module.
617 05:36:23.365865 <6>[ 0.688729] RPC: Registered tcp NFSv4.1 backchannel transport module.
618 05:36:23.366142 <6>[ 0.695633] PCI: CLS 0 bytes, default 64
619 05:36:23.372971 <5>[ 0.701398] Initialise system trusted keyrings
620 05:36:23.397909 <6>[ 0.725295] Trying to unpack rootfs image as initramfs...
621 05:36:23.422791 <6>[ 0.747176] workingset: timestamp_bits=30 max_order=17 bucket_order=0
622 05:36:23.427681 <6>[ 0.754647] squashfs: version 4.0 (2009/01/31) Phillip Lougher
623 05:36:23.469700 <5>[ 0.800084] NFS: Registering the id_resolver key type
624 05:36:23.475450 <5>[ 0.805671] Key type id_resolver registered
625 05:36:23.481171 <5>[ 0.810333] Key type id_legacy registered
626 05:36:23.486911 <6>[ 0.814768] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
627 05:36:23.496567 <6>[ 0.821987] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
628 05:36:23.539580 <5>[ 0.870114] Key type asymmetric registered
629 05:36:23.545476 <5>[ 0.874637] Asymmetric key parser 'x509' registered
630 05:36:23.556974 <6>[ 0.880124] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
631 05:36:23.557263 <6>[ 0.888061] io scheduler mq-deadline registered
632 05:36:23.562840 <6>[ 0.892992] io scheduler kyber registered
633 05:36:23.568399 <6>[ 0.897463] io scheduler bfq registered
634 05:36:23.929000 <6>[ 1.255611] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
635 05:36:23.961549 <6>[ 1.291885] msm_serial: driver initialized
636 05:36:23.967667 <6>[ 1.296664] SuperH (H)SCI(F) driver initialized
637 05:36:23.973664 <6>[ 1.301954] STMicroelectronics ASC driver initialized
638 05:36:23.976709 <6>[ 1.307616] STM32 USART driver initialized
639 05:36:24.060969 <6>[ 1.390930] brd: module loaded
640 05:36:24.099340 <6>[ 1.429107] loop: module loaded
641 05:36:24.134915 <6>[ 1.464558] CAN device driver interface
642 05:36:24.141403 <6>[ 1.469780] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
643 05:36:24.147281 <6>[ 1.476679] e1000e: Intel(R) PRO/1000 Network Driver
644 05:36:24.153033 <6>[ 1.482137] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
645 05:36:24.158784 <6>[ 1.488576] igb: Intel(R) Gigabit Ethernet Network Driver
646 05:36:24.167074 <6>[ 1.494397] igb: Copyright (c) 2007-2014 Intel Corporation.
647 05:36:24.178773 <6>[ 1.503545] pegasus: Pegasus/Pegasus II USB Ethernet driver
648 05:36:24.184542 <6>[ 1.509693] usbcore: registered new interface driver pegasus
649 05:36:24.190287 <6>[ 1.515819] usbcore: registered new interface driver asix
650 05:36:24.196041 <6>[ 1.521698] usbcore: registered new interface driver ax88179_178a
651 05:36:24.201916 <6>[ 1.528285] usbcore: registered new interface driver cdc_ether
652 05:36:24.207663 <6>[ 1.534581] usbcore: registered new interface driver smsc75xx
653 05:36:24.213413 <6>[ 1.540819] usbcore: registered new interface driver smsc95xx
654 05:36:24.219164 <6>[ 1.547050] usbcore: registered new interface driver net1080
655 05:36:24.224918 <6>[ 1.553166] usbcore: registered new interface driver cdc_subset
656 05:36:24.230787 <6>[ 1.559573] usbcore: registered new interface driver zaurus
657 05:36:24.238341 <6>[ 1.565639] usbcore: registered new interface driver cdc_ncm
658 05:36:24.248088 <6>[ 1.574976] usbcore: registered new interface driver usb-storage
659 05:36:24.389543 <6>[ 1.718176] i2c_dev: i2c /dev entries driver
660 05:36:24.430912 <5>[ 1.753475] cpuidle: enable-method property 'ti,am3352' found operations
661 05:36:24.436786 <6>[ 1.762998] sdhci: Secure Digital Host Controller Interface driver
662 05:36:24.444158 <6>[ 1.769768] sdhci: Copyright(c) Pierre Ossman
663 05:36:24.451294 <6>[ 1.776113] Synopsys Designware Multimedia Card Interface Driver
664 05:36:24.456711 <6>[ 1.783976] sdhci-pltfm: SDHCI platform and OF driver helper
665 05:36:24.523754 <6>[ 1.850550] ledtrig-cpu: registered to indicate activity on CPUs
666 05:36:24.564685 <6>[ 1.887874] usbcore: registered new interface driver usbhid
667 05:36:24.564959 <6>[ 1.893910] usbhid: USB HID core driver
668 05:36:24.595007 <6>[ 1.922898] NET: Registered PF_INET6 protocol family
669 05:36:24.657405 <6>[ 1.988008] Segment Routing with IPv6
670 05:36:24.663277 <6>[ 1.992159] In-situ OAM (IOAM) with IPv6
671 05:36:24.670005 <6>[ 1.996547] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
672 05:36:24.675880 <6>[ 2.003920] NET: Registered PF_PACKET protocol family
673 05:36:24.681629 <6>[ 2.009491] can: controller area network core
674 05:36:24.687348 <6>[ 2.014314] NET: Registered PF_CAN protocol family
675 05:36:24.687576 <6>[ 2.019539] can: raw protocol
676 05:36:24.693116 <6>[ 2.022866] can: broadcast manager protocol
677 05:36:24.699748 <6>[ 2.027462] can: netlink gateway - max_hops=1
678 05:36:24.705863 <5>[ 2.032983] Key type dns_resolver registered
679 05:36:24.712177 <6>[ 2.038040] ThumbEE CPU extension supported.
680 05:36:24.712461 <5>[ 2.042728] Registering SWP/SWPB emulation handler
681 05:36:24.721824 <3>[ 2.048417] omap_voltage_late_init: Voltage driver support not added
682 05:36:24.808995 <5>[ 2.137147] Loading compiled-in X.509 certificates
683 05:36:24.938022 <6>[ 2.255540] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
684 05:36:24.945118 <6>[ 2.272206] pinctrl-single 44e10800.pinmux: 142 pins, size 568
685 05:36:24.971137 <3>[ 2.295671] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
686 05:36:25.065210 <3>[ 2.389688] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
687 05:36:25.158936 <6>[ 2.487856] OMAP GPIO hardware version 0.1
688 05:36:25.179609 <6>[ 2.506342] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
689 05:36:25.252331 <4>[ 2.578867] at24 2-0054: supply vcc not found, using dummy regulator
690 05:36:25.309293 <4>[ 2.635892] at24 2-0055: supply vcc not found, using dummy regulator
691 05:36:25.344233 <4>[ 2.670788] at24 2-0056: supply vcc not found, using dummy regulator
692 05:36:25.394095 <4>[ 2.720640] at24 2-0057: supply vcc not found, using dummy regulator
693 05:36:25.459965 <6>[ 2.787323] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
694 05:36:25.529826 <3>[ 2.853171] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
695 05:36:25.554146 <6>[ 2.873882] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
696 05:36:25.596932 <4>[ 2.922284] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
697 05:36:25.630897 <4>[ 2.956253] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
698 05:36:25.660722 <6>[ 2.987451] omap_rng 48310000.rng: Random Number Generator ver. 20
699 05:36:25.683696 <5>[ 3.013205] random: crng init done
700 05:36:25.785754 <6>[ 3.111005] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
701 05:36:26.452127 <6>[ 3.781032] Freeing initrd memory: 14448K
702 05:36:26.494658 <6>[ 3.819229] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
703 05:36:26.500496 <6>[ 3.829427] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
704 05:36:26.512283 <6>[ 3.836688] cpsw-switch 4a100000.switch: ALE Table size 1024
705 05:36:26.518036 <6>[ 3.843144] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
706 05:36:26.529662 <6>[ 3.851275] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
707 05:36:26.536926 <6>[ 3.862904] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
708 05:36:26.548960 <5>[ 3.871928] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
709 05:36:26.576563 <3>[ 3.901466] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
710 05:36:26.582365 <6>[ 3.910034] edma 49000000.dma: TI EDMA DMA engine driver
711 05:36:26.652627 <3>[ 3.976744] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
712 05:36:26.666251 <6>[ 3.991117] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
713 05:36:26.684961 <3>[ 4.012913] l3-aon-clkctrl:0000:0: failed to disable
714 05:36:26.722328 <6>[ 4.047305] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
715 05:36:26.728071 <6>[ 4.056630] printk: legacy console [ttyS0] enabled
716 05:36:26.733701 <6>[ 4.056630] printk: legacy console [ttyS0] enabled
717 05:36:26.739447 <6>[ 4.067013] printk: legacy bootconsole [omap8250] disabled
718 05:36:26.745325 <6>[ 4.067013] printk: legacy bootconsole [omap8250] disabled
719 05:36:26.793708 <4>[ 4.117511] tps65217-pmic: Failed to locate of_node [id: -1]
720 05:36:26.797270 <4>[ 4.124888] tps65217-bl: Failed to locate of_node [id: -1]
721 05:36:26.813335 <6>[ 4.144239] tps65217 0-0024: TPS65217 ID 0xe version 1.2
722 05:36:26.831817 <6>[ 4.151156] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
723 05:36:26.843444 <6>[ 4.164843] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
724 05:36:26.849119 <6>[ 4.176677] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
725 05:36:26.871568 <6>[ 4.196693] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
726 05:36:26.877573 <6>[ 4.205919] sdhci-omap 48060000.mmc: Got CD GPIO
727 05:36:26.885621 <4>[ 4.211096] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
728 05:36:26.900193 <4>[ 4.224430] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
729 05:36:26.906692 <4>[ 4.233387] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
730 05:36:26.916632 <4>[ 4.242187] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
731 05:36:27.039265 <6>[ 4.365492] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
732 05:36:27.064617 <6>[ 4.389938] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
733 05:36:27.089935 <6>[ 4.414368] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 05:36:27.096616 <6>[ 4.423270] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
735 05:36:27.171628 <6>[ 4.492758] mmc1: new high speed MMC card at address 0001
736 05:36:27.171904 <6>[ 4.500307] mmcblk1: mmc1:0001 M62704 3.56 GiB
737 05:36:27.179547 <6>[ 4.508759] mmcblk1: p1
738 05:36:27.188043 <6>[ 4.513247] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
739 05:36:27.196328 <6>[ 4.521263] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
740 05:36:27.204703 <6>[ 4.529131] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
741 05:36:27.215913 <6>[ 4.538432] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 05:36:30.402729 <6>[ 7.727751] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
743 05:36:30.496069 <5>[ 7.786933] Sending DHCP requests ., OK
744 05:36:30.507422 <6>[ 7.831186] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.7
745 05:36:30.507696 <6>[ 7.839414] IP-Config: Complete:
746 05:36:30.518796 <6>[ 7.842949] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.7, mask=255.255.255.0, gw=192.168.11.1
747 05:36:30.524568 <6>[ 7.853571] host=192.168.11.7, domain=usen.ad.jp, nis-domain=(none)
748 05:36:30.536692 <6>[ 7.860653] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
749 05:36:30.536961 <6>[ 7.860686] nameserver0=192.168.11.1
750 05:36:30.542796 <6>[ 7.872930] clk: Disabling unused clocks
751 05:36:30.549462 <6>[ 7.877669] PM: genpd: Disabling unused power domains
752 05:36:30.568662 <6>[ 7.895996] Freeing unused kernel image (initmem) memory: 2048K
753 05:36:30.576026 <6>[ 7.905601] Run /init as init process
754 05:36:30.600723 Loading, please wait...
755 05:36:30.675022 Starting systemd-udevd version 252.22-1~deb12u1
756 05:36:33.577417 <4>[ 10.901051] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
757 05:36:33.825259 <4>[ 11.148851] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
758 05:36:34.075066 <6>[ 11.406221] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
759 05:36:34.086077 <6>[ 11.412123] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
760 05:36:34.234442 <6>[ 11.564036] hub 1-0:1.0: USB hub found
761 05:36:34.258153 <6>[ 11.587626] hub 1-0:1.0: 1 port detected
762 05:36:34.265468 <6>[ 11.594860] tda998x 0-0070: found TDA19988
763 05:36:37.076298 Begin: Loading essential drivers ... done.
764 05:36:37.081748 Begin: Running /scripts/init-premount ... done.
765 05:36:37.087359 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
766 05:36:37.101286 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
767 05:36:37.101557 Device /sys/class/net/eth0 found
768 05:36:37.101773 done.
769 05:36:37.176763 Begin: Waiting up to 180 secs for any network device to become available ... done.
770 05:36:37.251211 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
771 05:36:37.251481 IP-Config: eth0 guessed broadcast address 192.168.11.255
772 05:36:37.256912 IP-Config: eth0 complete (dhcp from 192.168.11.1):
773 05:36:37.268065 address: 192.168.11.7 broadcast: 192.168.11.255 netmask: 255.255.255.0
774 05:36:37.273555 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
775 05:36:37.279178 domain : usen.ad.jp
776 05:36:37.284262 rootserver: 192.168.11.1 rootpath:
777 05:36:37.284530 filename :
778 05:36:37.356405 done.
779 05:36:37.363706 Begin: Running /scripts/nfs-bottom ... done.
780 05:36:37.436605 Begin: Running /scripts/init-bottom ... done.
781 05:36:38.628723 <30>[ 15.955565] systemd[1]: System time before build time, advancing clock.
782 05:36:38.772893 <30>[ 16.073706] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
783 05:36:38.781949 <30>[ 16.110743] systemd[1]: Detected architecture arm.
784 05:36:38.794238
785 05:36:38.794513 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
786 05:36:38.794738
787 05:36:38.828951 <30>[ 16.156468] systemd[1]: Hostname set to <debian-bookworm-armhf>.
788 05:36:40.995329 <30>[ 18.321846] systemd[1]: Queued start job for default target graphical.target.
789 05:36:41.012133 <30>[ 18.336478] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
790 05:36:41.019647 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
791 05:36:41.055587 <30>[ 18.379181] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
792 05:36:41.063010 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
793 05:36:41.098630 <30>[ 18.422607] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
794 05:36:41.106054 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
795 05:36:41.143377 <30>[ 18.468600] systemd[1]: Created slice user.slice - User and Session Slice.
796 05:36:41.150149 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
797 05:36:41.186760 <30>[ 18.509327] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
798 05:36:41.199863 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
799 05:36:41.233266 <30>[ 18.558020] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
800 05:36:41.244278 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
801 05:36:41.283930 <30>[ 18.597917] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
802 05:36:41.290261 <30>[ 18.618396] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
803 05:36:41.298806 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
804 05:36:41.332032 <30>[ 18.657233] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
805 05:36:41.340407 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
806 05:36:41.372660 <30>[ 18.697631] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
807 05:36:41.381263 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
808 05:36:41.412675 <30>[ 18.737822] systemd[1]: Reached target paths.target - Path Units.
809 05:36:41.417742 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
810 05:36:41.452338 <30>[ 18.777458] systemd[1]: Reached target remote-fs.target - Remote File Systems.
811 05:36:41.459760 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
812 05:36:41.493675 <30>[ 18.818211] systemd[1]: Reached target slices.target - Slice Units.
813 05:36:41.499094 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
814 05:36:41.532332 <30>[ 18.857509] systemd[1]: Reached target swap.target - Swaps.
815 05:36:41.536353 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
816 05:36:41.572684 <30>[ 18.897612] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
817 05:36:41.581593 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
818 05:36:41.613673 <30>[ 18.938444] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
819 05:36:41.621839 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
820 05:36:41.711221 <30>[ 19.031272] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
821 05:36:41.723914 <30>[ 19.048734] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
822 05:36:41.732320 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
823 05:36:41.764561 <30>[ 19.089176] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
824 05:36:41.772001 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
825 05:36:41.805662 <30>[ 19.130314] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
826 05:36:41.813845 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
827 05:36:41.847168 <30>[ 19.171798] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
828 05:36:41.852663 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
829 05:36:41.894714 <30>[ 19.220365] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
830 05:36:41.907334 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
831 05:36:41.949777 <30>[ 19.268547] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
832 05:36:41.966321 <30>[ 19.285260] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
833 05:36:42.003329 <30>[ 19.329167] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
834 05:36:42.022063 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
835 05:36:42.083649 <30>[ 19.409291] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
836 05:36:42.105187 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
837 05:36:42.175625 <30>[ 19.500303] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
838 05:36:42.194176 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
839 05:36:42.265493 <30>[ 19.590783] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
840 05:36:42.291386 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
841 05:36:42.345411 <30>[ 19.671037] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
842 05:36:42.370427 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
843 05:36:42.424666 <30>[ 19.750734] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
844 05:36:42.440573 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
845 05:36:42.493230 <30>[ 19.817963] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
846 05:36:42.513209 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
847 05:36:42.574417 <30>[ 19.900302] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
848 05:36:42.601737 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
849 05:36:42.652103 <30>[ 19.978128] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
850 05:36:42.667107 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
851 05:36:42.709110 <28>[ 20.029070] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
852 05:36:42.717555 <28>[ 20.042735] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
853 05:36:42.753704 <30>[ 20.080152] systemd[1]: Starting systemd-journald.service - Journal Service...
854 05:36:42.782237 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
855 05:36:42.864524 <30>[ 20.190369] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
856 05:36:42.876765 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
857 05:36:42.943998 <30>[ 20.269974] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
858 05:36:42.984306 Starting [0;1;39msystemd-network-g… units from Kernel command line...
859 05:36:43.046281 <30>[ 20.370832] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
860 05:36:43.102243 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
861 05:36:43.182864 <30>[ 20.508199] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
862 05:36:43.231698 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
863 05:36:43.293354 <30>[ 20.619437] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
864 05:36:43.341393 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
865 05:36:43.373108 <30>[ 20.698974] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
866 05:36:43.395510 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
867 05:36:43.437175 <30>[ 20.761993] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
868 05:36:43.463460 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
869 05:36:43.597371 <30>[ 20.924131] systemd[1]: Started systemd-journald.service - Journal Service.
870 05:36:43.631247 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
871 05:36:43.672240 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
872 05:36:43.713531 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
873 05:36:43.755543 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
874 05:36:43.802474 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
875 05:36:43.837710 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
876 05:36:43.883448 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
877 05:36:43.922165 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
878 05:36:43.954449 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
879 05:36:43.992150 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
880 05:36:44.026536 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
881 05:36:44.102833 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
882 05:36:44.144383 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
883 05:36:44.224100 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
884 05:36:44.284526 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
885 05:36:44.375846 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
886 05:36:44.504755 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
887 05:36:44.531686 <46>[ 21.857683] systemd-journald[163]: Received client request to flush runtime journal.
888 05:36:44.652333 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
889 05:36:44.742378 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
890 05:36:45.548773 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
891 05:36:45.623267 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
892 05:36:46.282947 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
893 05:36:46.441928 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
894 05:36:46.473173 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
895 05:36:46.501911 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
896 05:36:46.616701 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
897 05:36:46.675390 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
898 05:36:47.581418 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
899 05:36:47.696117 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
900 05:36:47.915250 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
901 05:36:48.023658 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
902 05:36:48.104612 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
903 05:36:49.135220 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
904 05:36:50.546793 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
905 05:36:51.065776 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
906 05:36:51.170837 <5>[ 28.497329] cfg80211: Loading compiled-in X.509 certificates for regulatory database
907 05:36:52.656730 <5>[ 29.985317] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
908 05:36:52.757797 <5>[ 30.084834] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
909 05:36:52.774634 <4>[ 30.100748] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
910 05:36:52.780311 <6>[ 30.109865] cfg80211: failed to load regulatory.db
911 05:36:52.947055 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
912 05:36:53.298431 <46>[ 30.614832] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
913 05:36:53.415111 <46>[ 30.734631] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
914 05:36:53.445745 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
915 05:37:01.681507 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
916 05:37:01.716097 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
917 05:37:01.753469 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
918 05:37:01.786346 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
919 05:37:01.877927 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
920 05:37:01.933478 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
921 05:37:02.011460 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
922 05:37:02.062637 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
923 05:37:02.111402 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
924 05:37:02.152466 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
925 05:37:02.186782 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
926 05:37:02.260767 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
927 05:37:02.296156 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
928 05:37:02.354415 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
929 05:37:02.414605 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
930 05:37:02.452087 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
931 05:37:02.499373 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
932 05:37:02.540668 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
933 05:37:02.574519 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
934 05:37:02.617058 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
935 05:37:02.660228 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
936 05:37:02.696815 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
937 05:37:02.731614 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
938 05:37:02.817958 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
939 05:37:02.887773 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
940 05:37:03.019929 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
941 05:37:03.111405 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
942 05:37:03.193133 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
943 05:37:03.242147 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
944 05:37:03.257641 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
945 05:37:03.444367 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
946 05:37:03.458122 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
947 05:37:03.562737 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
948 05:37:03.624024 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
949 05:37:03.651855 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
950 05:37:03.827385 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
951 05:37:04.057906 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
952 05:37:04.123128 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
953 05:37:04.169499 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
954 05:37:04.263963 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
955 05:37:04.428993 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
956 05:37:04.578783
957 05:37:04.579079 Debian GNU/Linux 12worm-armhf login: root (automatic login)
958 05:37:04.582194
959 05:37:04.901516 Linux debian-bookworm-armhf 6.11.0-rc5 #1 SMP Sat Aug 31 04:47:30 UTC 2024 armv7l
960 05:37:04.901886
961 05:37:04.907103 The programs included with the Debian GNU/Linux system are free software;
962 05:37:04.912739 the exact distribution terms for each program are described in the
963 05:37:04.918361 individual files in /usr/share/doc/*/copyright.
964 05:37:04.918618
965 05:37:04.926279 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
966 05:37:04.926506 permitted by applicable law.
967 05:37:09.546971 Unable to match end of the kernel message
969 05:37:09.547770 Setting prompt string to ['/ #']
970 05:37:09.548071 end: 2.4.4.1 login-action (duration 00:00:47) [common]
972 05:37:09.548783 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
973 05:37:09.549074 start: 2.4.5 expect-shell-connection (timeout 00:03:24) [common]
974 05:37:09.549312 Setting prompt string to ['/ #']
975 05:37:09.549540 Forcing a shell prompt, looking for ['/ #']
977 05:37:09.600062 / #
978 05:37:09.600456 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
979 05:37:09.600713 Waiting using forced prompt support (timeout 00:02:30)
980 05:37:09.604841
981 05:37:09.611206 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
982 05:37:09.611550 start: 2.4.6 export-device-env (timeout 00:03:24) [common]
983 05:37:09.611808 Sending with 10 millisecond of delay
985 05:37:14.660988 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1186402/extract-nfsrootfs-zvh23sor'
986 05:37:14.671568 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1186402/extract-nfsrootfs-zvh23sor'
987 05:37:14.672652 Sending with 10 millisecond of delay
989 05:37:16.830994 / # export NFS_SERVER_IP='192.168.11.5'
990 05:37:16.841590 export NFS_SERVER_IP='192.168.11.5'
991 05:37:16.842462 end: 2.4.6 export-device-env (duration 00:00:07) [common]
992 05:37:16.842801 end: 2.4 uboot-commands (duration 00:01:43) [common]
993 05:37:16.843118 end: 2 uboot-action (duration 00:01:43) [common]
994 05:37:16.843426 start: 3 lava-test-retry (timeout 00:07:21) [common]
995 05:37:16.843736 start: 3.1 lava-test-shell (timeout 00:07:21) [common]
996 05:37:16.843992 Using namespace: common
998 05:37:16.944755 / # #
999 05:37:16.945270 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1000 05:37:16.949687 #
1001 05:37:16.956118 Using /lava-1186402
1003 05:37:17.056859 / # export SHELL=/bin/bash
1004 05:37:17.061722 export SHELL=/bin/bash
1006 05:37:17.168224 / # . /lava-1186402/environment
1007 05:37:17.172956 . /lava-1186402/environment
1009 05:37:17.285834 / # /lava-1186402/bin/lava-test-runner /lava-1186402/0
1010 05:37:17.286226 Test shell timeout: 10s (minimum of the action and connection timeout)
1011 05:37:17.290597 /lava-1186402/bin/lava-test-runner /lava-1186402/0
1012 05:37:17.706196 + export TESTRUN_ID=0_timesync-off
1013 05:37:17.714199 + TESTRUN_ID=0_timesync-off
1014 05:37:17.714455 + cd /lava-1186402/0/tests/0_timesync-off
1015 05:37:17.714686 ++ cat uuid
1016 05:37:17.729905 + UUID=1186402_1.6.2.4.1
1017 05:37:17.730146 + set +x
1018 05:37:17.735386 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1186402_1.6.2.4.1>
1019 05:37:17.735845 Received signal: <STARTRUN> 0_timesync-off 1186402_1.6.2.4.1
1020 05:37:17.736092 Starting test lava.0_timesync-off (1186402_1.6.2.4.1)
1021 05:37:17.736401 Skipping test definition patterns.
1022 05:37:17.738565 + systemctl stop systemd-timesyncd
1023 05:37:18.054242 + set +x
1024 05:37:18.054827 Received signal: <ENDRUN> 0_timesync-off 1186402_1.6.2.4.1
1025 05:37:18.055107 Ending use of test pattern.
1026 05:37:18.055331 Ending test lava.0_timesync-off (1186402_1.6.2.4.1), duration 0.32
1028 05:37:18.057453 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1186402_1.6.2.4.1>
1029 05:37:18.221160 + export TESTRUN_ID=1_kselftest-dt
1030 05:37:18.229181 + TESTRUN_ID=1_kselftest-dt
1031 05:37:18.229454 + cd /lava-1186402/0/tests/1_kselftest-dt
1032 05:37:18.229695 ++ cat uuid
1033 05:37:18.243383 + UUID=1186402_1.6.2.4.5
1034 05:37:18.243622 + set +x
1035 05:37:18.248997 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1186402_1.6.2.4.5>
1036 05:37:18.249233 + cd ./automated/linux/kselftest/
1037 05:37:18.249661 Received signal: <STARTRUN> 1_kselftest-dt 1186402_1.6.2.4.5
1038 05:37:18.249889 Starting test lava.1_kselftest-dt (1186402_1.6.2.4.5)
1039 05:37:18.250154 Skipping test definition patterns.
1040 05:37:18.277288 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1041 05:37:18.396897 INFO: install_deps skipped
1042 05:37:19.007629 --2024-08-31 05:37:18-- http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1043 05:37:19.025904 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1044 05:37:19.140232 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1045 05:37:19.256399 HTTP request sent, awaiting response... 200 OK
1046 05:37:19.256708 Length: 3607668 (3.4M) [application/octet-stream]
1047 05:37:19.262002 Saving to: 'kselftest_armhf.tar.gz'
1048 05:37:19.262271
1049 05:37:20.902554 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 1%[ ] 44.73K 202KB/s kselftest_armhf.tar 5%[> ] 208.82K 465KB/s kselftest_armhf.tar 19%[==> ] 697.23K 950KB/s kselftest_armhf.tar 37%[======> ] 1.28M 1.23MB/s kselftest_armhf.tar 70%[=============> ] 2.43M 1.87MB/s kselftest_armhf.tar 88%[================> ] 3.04M 2.01MB/s kselftest_armhf.tar 100%[===================>] 3.44M 2.10MB/s in 1.6s
1050 05:37:20.902917
1051 05:37:21.409419 2024-08-31 05:37:20 (2.10 MB/s) - 'kselftest_armhf.tar.gz' saved [3607668/3607668]
1052 05:37:21.409808
1053 05:37:41.069380 skiplist:
1054 05:37:41.069767 ========================================
1055 05:37:41.075060 ========================================
1056 05:37:41.180113 dt:test_unprobed_devices.sh
1057 05:37:41.212256 ============== Tests to run ===============
1058 05:37:41.220166 dt:test_unprobed_devices.sh
1059 05:37:41.224076 ===========End Tests to run ===============
1060 05:37:41.235649 shardfile-dt pass
1061 05:37:41.473603 <12>[ 78.805541] kselftest: Running tests in dt
1062 05:37:41.501498 TAP version 13
1063 05:37:41.525292 1..1
1064 05:37:41.577822 # timeout set to 45
1065 05:37:41.578176 # selftests: dt: test_unprobed_devices.sh
1066 05:37:42.546761 # TAP version 13
1067 05:37:54.507169 # 1..255
1068 05:37:54.690892 # ok 1 / # SKIP
1069 05:37:54.713713 # ok 2 /clk_mcasp0
1070 05:37:54.784845 # ok 3 /clk_mcasp0_fixed # SKIP
1071 05:37:54.854343 # ok 4 /cpus/cpu@0 # SKIP
1072 05:37:54.924627 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1073 05:37:54.948793 # ok 6 /fixedregulator0
1074 05:37:54.968867 # ok 7 /leds
1075 05:37:54.985564 # ok 8 /ocp
1076 05:37:55.008891 # ok 9 /ocp/interconnect@44c00000
1077 05:37:55.031750 # ok 10 /ocp/interconnect@44c00000/segment@0
1078 05:37:55.058790 # ok 11 /ocp/interconnect@44c00000/segment@100000
1079 05:37:55.082935 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1080 05:37:55.153218 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1081 05:37:55.174561 # ok 14 /ocp/interconnect@44c00000/segment@200000
1082 05:37:55.191013 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1083 05:37:55.304627 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1084 05:37:55.378646 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1085 05:37:55.448576 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1086 05:37:55.517806 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1087 05:37:55.583753 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1088 05:37:55.661882 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1089 05:37:55.730144 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1090 05:37:55.799575 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1091 05:37:55.873778 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1092 05:37:55.946675 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1093 05:37:56.013783 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1094 05:37:56.085748 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1095 05:37:56.158262 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1096 05:37:56.221794 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1097 05:37:56.297976 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1098 05:37:56.362593 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1099 05:37:56.438617 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1100 05:37:56.508543 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1101 05:37:56.577114 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1102 05:37:56.643600 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1103 05:37:56.719142 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1104 05:37:56.791875 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1105 05:37:56.857369 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1106 05:37:56.932868 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1107 05:37:57.007527 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1108 05:37:57.071104 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1109 05:37:57.148788 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1110 05:37:57.217507 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1111 05:37:57.288139 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1112 05:37:57.360920 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1113 05:37:57.431117 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1114 05:37:57.499529 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1115 05:37:57.570505 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1116 05:37:57.634999 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1117 05:37:57.711108 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1118 05:37:57.782602 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1119 05:37:57.852882 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1120 05:37:57.921235 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1121 05:37:57.993413 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1122 05:37:58.062672 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1123 05:37:58.133412 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1124 05:37:58.202966 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1125 05:37:58.270050 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1126 05:37:58.339651 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1127 05:37:58.414682 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1128 05:37:58.488171 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1129 05:37:58.551818 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1130 05:37:58.628920 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1131 05:37:58.698416 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1132 05:37:58.763040 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1133 05:37:58.840791 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1134 05:37:58.909830 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1135 05:37:58.986782 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1136 05:37:59.055108 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1137 05:37:59.123597 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1138 05:37:59.198591 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1139 05:37:59.270954 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1140 05:37:59.342399 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1141 05:37:59.412822 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1142 05:37:59.481312 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1143 05:37:59.549414 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1144 05:37:59.627937 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1145 05:37:59.691784 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1146 05:37:59.761617 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1147 05:37:59.839265 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1148 05:37:59.903148 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1149 05:37:59.980514 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1150 05:38:00.049403 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1151 05:38:00.122064 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1152 05:38:00.184980 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1153 05:38:00.259487 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1154 05:38:00.331624 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1155 05:38:00.405775 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1156 05:38:00.469998 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1157 05:38:00.543513 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1158 05:38:00.618164 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1159 05:38:00.684310 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1160 05:38:00.761036 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1161 05:38:00.831159 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1162 05:38:00.853981 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1163 05:38:00.878112 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1164 05:38:00.894368 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1165 05:38:00.918860 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1166 05:38:00.948863 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1167 05:38:00.965481 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1168 05:38:00.994134 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1169 05:38:01.017372 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1170 05:38:01.116613 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1171 05:38:01.146646 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1172 05:38:01.168728 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1173 05:38:01.188605 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1174 05:38:01.296248 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1175 05:38:01.371322 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1176 05:38:01.438944 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1177 05:38:01.511729 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1178 05:38:01.583327 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1179 05:38:01.654120 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1180 05:38:01.721451 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1181 05:38:01.793577 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1182 05:38:01.867846 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1183 05:38:01.950557 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1184 05:38:02.011033 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1185 05:38:02.083988 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1186 05:38:02.152903 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1187 05:38:02.225210 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1188 05:38:02.293177 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1189 05:38:02.370008 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1190 05:38:02.383496 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1191 05:38:02.459910 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1192 05:38:02.520653 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1193 05:38:02.597824 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1194 05:38:02.618783 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1195 05:38:02.688554 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1196 05:38:02.713320 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1197 05:38:02.785526 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1198 05:38:02.805263 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1199 05:38:02.827398 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1200 05:38:02.846429 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1201 05:38:02.876571 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1202 05:38:02.890944 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1203 05:38:02.917326 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1204 05:38:02.945341 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1205 05:38:02.969682 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1206 05:38:02.985342 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1207 05:38:03.059910 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1208 05:38:03.129215 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1209 05:38:03.156514 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1210 05:38:03.226642 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1211 05:38:03.297398 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1212 05:38:03.388568 # not ok 145 /ocp/interconnect@47c00000
1213 05:38:03.460291 # not ok 146 /ocp/interconnect@47c00000/segment@0
1214 05:38:03.481031 # ok 147 /ocp/interconnect@48000000
1215 05:38:03.508525 # ok 148 /ocp/interconnect@48000000/segment@0
1216 05:38:03.533814 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1217 05:38:03.558127 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1218 05:38:03.575957 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1219 05:38:03.604344 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1220 05:38:03.620084 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1221 05:38:03.647872 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1222 05:38:03.671643 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1223 05:38:03.741699 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1224 05:38:03.814487 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1225 05:38:03.836378 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1226 05:38:03.857090 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1227 05:38:03.877465 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1228 05:38:03.907836 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1229 05:38:03.922465 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1230 05:38:03.950837 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1231 05:38:03.974120 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1232 05:38:03.999458 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1233 05:38:04.019575 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1234 05:38:04.040083 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1235 05:38:04.069013 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1236 05:38:04.085399 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1237 05:38:04.113384 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1238 05:38:04.138376 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1239 05:38:04.157257 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1240 05:38:04.176349 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1241 05:38:04.206207 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1242 05:38:04.222104 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1243 05:38:04.247376 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1244 05:38:04.273288 # ok 177 /ocp/interconnect@48000000/segment@100000
1245 05:38:04.290498 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1246 05:38:04.314622 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1247 05:38:04.389117 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1248 05:38:04.460612 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1249 05:38:04.529235 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1250 05:38:04.601359 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1251 05:38:04.621728 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1252 05:38:04.645914 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1253 05:38:04.662173 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1254 05:38:04.687514 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1255 05:38:04.713023 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1256 05:38:04.739708 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1257 05:38:04.757347 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1258 05:38:04.784470 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1259 05:38:04.806902 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1260 05:38:04.826870 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1261 05:38:04.855387 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1262 05:38:04.872008 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1263 05:38:04.897057 # ok 196 /ocp/interconnect@48000000/segment@200000
1264 05:38:04.916019 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1265 05:38:04.993202 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1266 05:38:05.014121 # ok 199 /ocp/interconnect@48000000/segment@300000
1267 05:38:05.030302 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1268 05:38:05.060632 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1269 05:38:05.086491 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1270 05:38:05.109324 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1271 05:38:05.126659 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1272 05:38:05.147994 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1273 05:38:05.224480 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1274 05:38:05.242836 # ok 207 /ocp/interconnect@4a000000
1275 05:38:05.259794 # ok 208 /ocp/interconnect@4a000000/segment@0
1276 05:38:05.289014 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1277 05:38:05.315321 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1278 05:38:05.334395 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1279 05:38:05.361319 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1280 05:38:05.431363 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1281 05:38:05.537127 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1282 05:38:05.609086 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1283 05:38:05.711056 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1284 05:38:05.778175 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1285 05:38:05.849204 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1286 05:38:05.938980 # not ok 219 /ocp/interconnect@4b140000
1287 05:38:06.009391 # not ok 220 /ocp/interconnect@4b140000/segment@0
1288 05:38:06.083756 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1289 05:38:06.103809 # ok 222 /ocp/target-module@40300000
1290 05:38:06.123926 # ok 223 /ocp/target-module@40300000/sram@0
1291 05:38:06.201355 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1292 05:38:06.270610 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1293 05:38:06.291970 # ok 226 /ocp/target-module@47400000
1294 05:38:06.313967 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1295 05:38:06.333967 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1296 05:38:06.357965 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1297 05:38:06.380267 # ok 230 /ocp/target-module@47400000/usb@1400
1298 05:38:06.397714 # ok 231 /ocp/target-module@47400000/usb@1800
1299 05:38:06.422966 # ok 232 /ocp/target-module@47810000
1300 05:38:06.443883 # ok 233 /ocp/target-module@49000000
1301 05:38:06.464835 # ok 234 /ocp/target-module@49000000/dma@0
1302 05:38:06.483871 # ok 235 /ocp/target-module@49800000
1303 05:38:06.507336 # ok 236 /ocp/target-module@49800000/dma@0
1304 05:38:06.528876 # ok 237 /ocp/target-module@49900000
1305 05:38:06.553465 # ok 238 /ocp/target-module@49900000/dma@0
1306 05:38:06.578834 # ok 239 /ocp/target-module@49a00000
1307 05:38:06.600708 # ok 240 /ocp/target-module@49a00000/dma@0
1308 05:38:06.621963 # ok 241 /ocp/target-module@4c000000
1309 05:38:06.691528 # not ok 242 /ocp/target-module@4c000000/emif@0
1310 05:38:06.712378 # ok 243 /ocp/target-module@50000000
1311 05:38:06.732828 # ok 244 /ocp/target-module@53100000
1312 05:38:06.800824 # not ok 245 /ocp/target-module@53100000/sham@0
1313 05:38:06.823199 # ok 246 /ocp/target-module@53500000
1314 05:38:06.893206 # not ok 247 /ocp/target-module@53500000/aes@0
1315 05:38:06.914447 # ok 248 /ocp/target-module@56000000
1316 05:38:07.017227 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1317 05:38:07.089676 # ok 250 /opp-table # SKIP
1318 05:38:07.153539 # ok 251 /soc # SKIP
1319 05:38:07.174260 # ok 252 /sound
1320 05:38:07.197367 # ok 253 /target-module@4b000000
1321 05:38:07.221180 # ok 254 /target-module@4b000000/target-module@140000
1322 05:38:07.242754 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1323 05:38:07.250689 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1324 05:38:07.256345 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1325 05:38:09.282429 dt_test_unprobed_devices_sh_ skip
1326 05:38:09.288015 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1327 05:38:09.293653 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1328 05:38:09.293896 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1329 05:38:09.299261 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1330 05:38:09.304889 dt_test_unprobed_devices_sh_fixedregulator0 pass
1331 05:38:09.310384 dt_test_unprobed_devices_sh_leds pass
1332 05:38:09.310627 dt_test_unprobed_devices_sh_ocp pass
1333 05:38:09.316010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1334 05:38:09.321654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1335 05:38:09.327274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1336 05:38:09.338567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1337 05:38:09.344135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1338 05:38:09.349754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1339 05:38:09.361027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1340 05:38:09.366506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1341 05:38:09.377819 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1342 05:38:09.389093 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1343 05:38:09.400235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1344 05:38:09.405835 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1345 05:38:09.417092 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1346 05:38:09.428347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1347 05:38:09.439456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1348 05:38:09.450706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1349 05:38:09.456220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1350 05:38:09.467456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1351 05:38:09.478709 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1352 05:38:09.489881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1353 05:38:09.501099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1354 05:38:09.506577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1355 05:38:09.517830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1356 05:38:09.529091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1357 05:38:09.540218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1358 05:38:09.545842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1359 05:38:09.557093 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1360 05:38:09.568163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1361 05:38:09.579236 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1362 05:38:09.590514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1363 05:38:09.596162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1364 05:38:09.607284 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1365 05:38:09.618513 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1366 05:38:09.629650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1367 05:38:09.641025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1368 05:38:09.652017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1369 05:38:09.663263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1370 05:38:09.674407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1371 05:38:09.685656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1372 05:38:09.696768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1373 05:38:09.708023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1374 05:38:09.719136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1375 05:38:09.730404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1376 05:38:09.741637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1377 05:38:09.752779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1378 05:38:09.764014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1379 05:38:09.775162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1380 05:38:09.786412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1381 05:38:09.797536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1382 05:38:09.808785 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1383 05:38:09.820032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1384 05:38:09.831159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1385 05:38:09.842282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1386 05:38:09.853533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1387 05:38:09.864656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1388 05:38:09.875907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1389 05:38:09.881533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1390 05:38:09.892657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1391 05:38:09.903905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1392 05:38:09.915027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1393 05:38:09.926281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1394 05:38:09.937405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1395 05:38:09.948655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1396 05:38:09.959903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1397 05:38:09.971028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1398 05:38:09.982278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1399 05:38:09.993403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1400 05:38:10.004655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1401 05:38:10.015773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1402 05:38:10.027030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1403 05:38:10.038155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1404 05:38:10.049404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1405 05:38:10.060524 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1406 05:38:10.071776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1407 05:38:10.077403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1408 05:38:10.088523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1409 05:38:10.099872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1410 05:38:10.111024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1411 05:38:10.122147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1412 05:38:10.127650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1413 05:38:10.144517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1414 05:38:10.155644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1415 05:38:10.161270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1416 05:38:10.178019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1417 05:38:10.189272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1418 05:38:10.200397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1419 05:38:10.206017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1420 05:38:10.217267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1421 05:38:10.228367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1422 05:38:10.234019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1423 05:38:10.245158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1424 05:38:10.256366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1425 05:38:10.262022 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1426 05:38:10.273138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1427 05:38:10.278765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1428 05:38:10.290018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1429 05:38:10.301141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1430 05:38:10.312368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1431 05:38:10.323514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1432 05:38:10.334811 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1433 05:38:10.345983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1434 05:38:10.357189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1435 05:38:10.368226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1436 05:38:10.379494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1437 05:38:10.390581 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1438 05:38:10.401955 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1439 05:38:10.413128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1440 05:38:10.429831 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1441 05:38:10.440966 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1442 05:38:10.452186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1443 05:38:10.463438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1444 05:38:10.474559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1445 05:38:10.491434 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1446 05:38:10.502557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1447 05:38:10.513808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1448 05:38:10.525104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1449 05:38:10.530557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1450 05:38:10.541808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1451 05:38:10.553114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1452 05:38:10.558557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1453 05:38:10.569806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1454 05:38:10.575480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1455 05:38:10.586522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1456 05:38:10.592300 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1457 05:38:10.603322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1458 05:38:10.609000 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1459 05:38:10.620184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1460 05:38:10.625826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1461 05:38:10.636978 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1462 05:38:10.648297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1463 05:38:10.659301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1464 05:38:10.664998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1465 05:38:10.676054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1466 05:38:10.687301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1467 05:38:10.692987 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1468 05:38:10.704053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1469 05:38:10.709678 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1470 05:38:10.715302 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1471 05:38:10.720960 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1472 05:38:10.726431 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1473 05:38:10.737675 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1474 05:38:10.743301 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1475 05:38:10.748955 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1476 05:38:10.760048 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1477 05:38:10.765714 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1478 05:38:10.776953 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1479 05:38:10.782424 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1480 05:38:10.793674 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1481 05:38:10.799175 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1482 05:38:10.804983 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1483 05:38:10.816048 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1484 05:38:10.821550 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1485 05:38:10.832822 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1486 05:38:10.838421 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1487 05:38:10.849547 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1488 05:38:10.855174 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1489 05:38:10.866422 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1490 05:38:10.871923 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1491 05:38:10.883170 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1492 05:38:10.888711 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1493 05:38:10.899921 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1494 05:38:10.905547 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1495 05:38:10.916756 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1496 05:38:10.922299 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1497 05:38:10.927924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1498 05:38:10.939045 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1499 05:38:10.944784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1500 05:38:10.955921 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1501 05:38:10.961548 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1502 05:38:10.972781 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1503 05:38:10.978298 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1504 05:38:10.989422 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1505 05:38:11.000781 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1506 05:38:11.011920 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1507 05:38:11.017421 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1508 05:38:11.028756 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1509 05:38:11.034176 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1510 05:38:11.045416 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1511 05:38:11.051043 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1512 05:38:11.062258 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1513 05:38:11.068018 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1514 05:38:11.079099 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1515 05:38:11.090233 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1516 05:38:11.095846 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1517 05:38:11.107101 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1518 05:38:11.112712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1519 05:38:11.123862 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1520 05:38:11.129351 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1521 05:38:11.134971 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1522 05:38:11.146213 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1523 05:38:11.151720 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1524 05:38:11.157344 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1525 05:38:11.168628 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1526 05:38:11.174091 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1527 05:38:11.185340 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1528 05:38:11.190968 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1529 05:38:11.202089 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1530 05:38:11.207716 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1531 05:38:11.213342 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1532 05:38:11.218967 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1533 05:38:11.230086 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1534 05:38:11.235714 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1535 05:38:11.246963 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1536 05:38:11.252471 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1537 05:38:11.263729 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1538 05:38:11.274964 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1539 05:38:11.286089 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1540 05:38:11.291612 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1541 05:38:11.302857 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1542 05:38:11.314090 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1543 05:38:11.319580 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1544 05:38:11.325184 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1545 05:38:11.330877 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1546 05:38:11.336502 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1547 05:38:11.342108 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1548 05:38:11.347541 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1549 05:38:11.358923 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1550 05:38:11.364468 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1551 05:38:11.370037 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1552 05:38:11.375678 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1553 05:38:11.381173 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1554 05:38:11.386912 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1555 05:38:11.392442 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1556 05:38:11.398078 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1557 05:38:11.403680 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1558 05:38:11.409161 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1559 05:38:11.414911 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1560 05:38:11.420470 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1561 05:38:11.426034 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1562 05:38:11.431691 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1563 05:38:11.437160 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1564 05:38:11.442918 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1565 05:38:11.448450 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1566 05:38:11.454074 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1567 05:38:11.459673 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1568 05:38:11.465209 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1569 05:38:11.470963 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1570 05:38:11.476484 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1571 05:38:11.482083 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1572 05:38:11.487708 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1573 05:38:11.493352 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1574 05:38:11.498921 dt_test_unprobed_devices_sh_opp-table skip
1575 05:38:11.504432 dt_test_unprobed_devices_sh_soc skip
1576 05:38:11.504677 dt_test_unprobed_devices_sh_sound pass
1577 05:38:11.510050 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1578 05:38:11.515695 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1579 05:38:11.526898 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1580 05:38:11.527143 dt_test_unprobed_devices_sh fail
1581 05:38:11.532440 + ../../utils/send-to-lava.sh ./output/result.txt
1582 05:38:11.537754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1583 05:38:11.538277 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1585 05:38:11.553029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1586 05:38:11.553515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1588 05:38:11.646713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1589 05:38:11.647485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1591 05:38:11.741785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1592 05:38:11.742343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1594 05:38:11.837356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1595 05:38:11.837838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1597 05:38:11.934738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1598 05:38:11.935213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1600 05:38:12.027061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1601 05:38:12.027545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1603 05:38:12.118035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1604 05:38:12.118582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1606 05:38:12.211625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1607 05:38:12.212122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1609 05:38:12.305577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1610 05:38:12.306054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1612 05:38:12.401981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1613 05:38:12.402471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1615 05:38:12.496457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1616 05:38:12.496936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1618 05:38:12.591053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1619 05:38:12.591512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1621 05:38:12.686578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1622 05:38:12.687129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1624 05:38:12.781182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1625 05:38:12.781631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1627 05:38:12.877285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1628 05:38:12.877731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1630 05:38:12.973682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1631 05:38:12.974128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1633 05:38:13.068309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1634 05:38:13.068758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1636 05:38:13.165170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1637 05:38:13.165700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1639 05:38:13.258533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1640 05:38:13.258983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1642 05:38:13.354690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1643 05:38:13.355139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1645 05:38:13.447905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1646 05:38:13.448430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1648 05:38:13.543029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1649 05:38:13.543521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1651 05:38:13.633576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1652 05:38:13.634066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1654 05:38:13.729688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1655 05:38:13.730272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1657 05:38:13.817429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1658 05:38:13.817915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1660 05:38:13.908050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1661 05:38:13.908585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1663 05:38:14.000188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1664 05:38:14.000705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1666 05:38:14.091583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1667 05:38:14.092068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1669 05:38:14.187594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1670 05:38:14.188159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1672 05:38:14.278791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1673 05:38:14.279277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1675 05:38:14.369530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1676 05:38:14.370015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1678 05:38:14.458155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1679 05:38:14.458666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1681 05:38:14.547279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1682 05:38:14.547774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1684 05:38:14.643155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1685 05:38:14.643645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1687 05:38:14.740068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1688 05:38:14.740652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1690 05:38:14.833880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1691 05:38:14.834352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1693 05:38:14.927632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1694 05:38:14.928106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1696 05:38:15.019898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1697 05:38:15.020378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1699 05:38:15.114111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1700 05:38:15.114692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1702 05:38:15.208022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1703 05:38:15.208513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1705 05:38:15.307665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1706 05:38:15.308181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1708 05:38:15.403000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1709 05:38:15.403490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1711 05:38:15.497368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1712 05:38:15.497888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1714 05:38:15.590394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1715 05:38:15.590888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1717 05:38:15.682631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1718 05:38:15.683211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1720 05:38:15.778988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1721 05:38:15.779472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1723 05:38:15.868619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1724 05:38:15.869145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1726 05:38:15.962619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1727 05:38:15.963111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1729 05:38:16.055405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1730 05:38:16.055891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1732 05:38:16.150458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1733 05:38:16.151008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1735 05:38:16.239195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1736 05:38:16.239666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1738 05:38:16.331370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1739 05:38:16.331851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1741 05:38:16.426887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1742 05:38:16.427377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1744 05:38:16.521036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1745 05:38:16.521518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1747 05:38:16.614232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1748 05:38:16.614706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1750 05:38:16.707903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1751 05:38:16.708480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1753 05:38:16.804597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1754 05:38:16.805076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1756 05:38:16.896425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1757 05:38:16.896903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1759 05:38:16.991114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1760 05:38:16.991594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1762 05:38:17.085608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1763 05:38:17.086089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1765 05:38:17.180422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1766 05:38:17.180987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1768 05:38:17.274225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1769 05:38:17.274703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1771 05:38:17.368228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1772 05:38:17.368704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1774 05:38:17.464918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1775 05:38:17.465397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1777 05:38:17.557145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1778 05:38:17.557634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1780 05:38:17.650203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1781 05:38:17.650697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1783 05:38:17.743910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1784 05:38:17.744515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1786 05:38:17.834744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1787 05:38:17.835235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1789 05:38:17.924332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1790 05:38:17.924824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1792 05:38:18.015810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1793 05:38:18.016259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1795 05:38:18.105818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1796 05:38:18.106312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1798 05:38:18.197106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1799 05:38:18.197652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1801 05:38:18.286354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1802 05:38:18.286831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1804 05:38:18.378368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1805 05:38:18.378843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1807 05:38:18.470041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1808 05:38:18.470517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1810 05:38:18.563603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1811 05:38:18.564082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1813 05:38:18.656023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1814 05:38:18.656519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1816 05:38:18.749773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1817 05:38:18.750340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1819 05:38:18.842015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1820 05:38:18.842491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1822 05:38:18.939379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1823 05:38:18.939852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1825 05:38:19.034914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1826 05:38:19.035391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1828 05:38:19.128579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1829 05:38:19.129159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1831 05:38:19.224620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1832 05:38:19.225100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1834 05:38:19.319784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1835 05:38:19.320259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1837 05:38:19.414384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1838 05:38:19.414860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1840 05:38:19.508244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1841 05:38:19.508740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1843 05:38:19.603790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1844 05:38:19.604260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1846 05:38:19.697045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1847 05:38:19.697618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1849 05:38:19.796319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1850 05:38:19.796895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1852 05:38:19.891032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1853 05:38:19.891513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1855 05:38:19.985906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1856 05:38:19.986386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1858 05:38:20.081738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1859 05:38:20.082223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1861 05:38:20.177028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1862 05:38:20.177590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1864 05:38:20.270395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1865 05:38:20.270878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1867 05:38:20.363766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1868 05:38:20.364267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1870 05:38:20.457265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1871 05:38:20.457746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1873 05:38:20.550135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1874 05:38:20.550615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1876 05:38:20.647533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1877 05:38:20.648019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1879 05:38:20.738449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1880 05:38:20.738995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1882 05:38:20.833684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1883 05:38:20.834155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1885 05:38:20.927409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1886 05:38:20.927896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1888 05:38:21.021810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1889 05:38:21.022344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1891 05:38:21.116879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1892 05:38:21.117371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1894 05:38:21.208765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1895 05:38:21.209313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1897 05:38:21.296634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1898 05:38:21.297105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1900 05:38:21.384481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1901 05:38:21.384977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1903 05:38:21.472887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1904 05:38:21.473366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1906 05:38:21.565348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1907 05:38:21.565841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1909 05:38:21.657206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1910 05:38:21.657690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1912 05:38:21.756829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1913 05:38:21.757391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1915 05:38:21.860702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1916 05:38:21.861198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1918 05:38:21.953207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1919 05:38:21.953686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1921 05:38:22.049208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1922 05:38:22.049711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1924 05:38:22.147955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1925 05:38:22.148572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1927 05:38:22.241676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1928 05:38:22.242153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1930 05:38:22.332924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1931 05:38:22.333405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1933 05:38:22.427160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1934 05:38:22.427643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1936 05:38:22.519657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1937 05:38:22.520143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1939 05:38:22.606295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1940 05:38:22.606793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1942 05:38:22.697434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1944 05:38:22.700534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1945 05:38:22.794975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1947 05:38:22.798011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1948 05:38:22.888802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1950 05:38:22.891786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1951 05:38:22.986063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1952 05:38:22.986582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1954 05:38:23.078295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1955 05:38:23.078784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1957 05:38:23.168850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1958 05:38:23.169414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1960 05:38:23.264395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1961 05:38:23.264881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1963 05:38:23.356908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1964 05:38:23.357399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1966 05:38:23.453489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1967 05:38:23.453989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1969 05:38:23.546791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1970 05:38:23.547265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1972 05:38:23.643230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1973 05:38:23.643720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1975 05:38:23.735745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1976 05:38:23.736310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1978 05:38:23.828618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1979 05:38:23.829102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1981 05:38:23.919240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1982 05:38:23.919727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1984 05:38:24.018665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1985 05:38:24.019147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1987 05:38:24.110303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1988 05:38:24.110777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1990 05:38:24.205987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1991 05:38:24.206555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1993 05:38:24.303853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1994 05:38:24.304340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1996 05:38:24.397140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1997 05:38:24.397619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1999 05:38:24.492959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2000 05:38:24.493434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2002 05:38:24.586752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2003 05:38:24.587230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2005 05:38:24.683320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2006 05:38:24.683803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2008 05:38:24.774280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2009 05:38:24.774835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2011 05:38:24.868039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2012 05:38:24.868552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2014 05:38:24.962346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2015 05:38:24.962824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2017 05:38:25.052452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2018 05:38:25.052932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2020 05:38:25.150362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2021 05:38:25.150968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2023 05:38:25.242761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2024 05:38:25.243228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2026 05:38:25.340782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2027 05:38:25.341250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2029 05:38:25.436309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2030 05:38:25.436782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2032 05:38:25.527130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2033 05:38:25.527604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2035 05:38:25.618572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2036 05:38:25.619050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2038 05:38:25.709805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2039 05:38:25.710359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2041 05:38:25.805187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2042 05:38:25.805629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2044 05:38:25.898476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2045 05:38:25.898948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2047 05:38:25.990860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2048 05:38:25.991330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2050 05:38:26.084740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2051 05:38:26.085208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2053 05:38:26.183490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2054 05:38:26.184042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2056 05:38:26.274109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2057 05:38:26.274579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2059 05:38:26.369199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2060 05:38:26.369664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2062 05:38:26.463595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2063 05:38:26.464061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2065 05:38:26.559443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2066 05:38:26.559912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2068 05:38:26.651959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2069 05:38:26.652446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2071 05:38:26.746826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2072 05:38:26.747386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2074 05:38:26.842441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2075 05:38:26.842911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2077 05:38:26.937429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2078 05:38:26.937896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2080 05:38:27.032570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2081 05:38:27.033044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2083 05:38:27.125665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2084 05:38:27.126142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2086 05:38:27.215917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2087 05:38:27.216489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2089 05:38:27.304422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2090 05:38:27.304893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2092 05:38:27.391797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2093 05:38:27.392261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2095 05:38:27.482866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2096 05:38:27.483344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2098 05:38:27.575678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2099 05:38:27.576157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2101 05:38:27.662848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2102 05:38:27.663318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2104 05:38:27.754070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2105 05:38:27.754622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2107 05:38:27.876915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2108 05:38:27.877385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2110 05:38:27.976769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2111 05:38:27.977237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2113 05:38:28.067300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2114 05:38:28.067768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2116 05:38:28.163522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2117 05:38:28.164071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2119 05:38:28.253641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2120 05:38:28.254112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2122 05:38:28.348379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2123 05:38:28.348846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2125 05:38:28.437886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2126 05:38:28.438352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2128 05:38:28.525516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2129 05:38:28.525986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2131 05:38:28.615389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2132 05:38:28.615874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2134 05:38:28.706055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2135 05:38:28.706600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2137 05:38:28.798987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2138 05:38:28.799527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2140 05:38:28.895400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2141 05:38:28.895877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2143 05:38:28.986532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2144 05:38:28.987009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2146 05:38:29.083150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2147 05:38:29.083631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2149 05:38:29.177668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2150 05:38:29.178224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2152 05:38:29.273873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2153 05:38:29.274348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2155 05:38:29.367009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2156 05:38:29.367484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2158 05:38:29.462384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2159 05:38:29.462859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2161 05:38:29.557641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2162 05:38:29.558117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2164 05:38:29.654834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2165 05:38:29.655319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2167 05:38:29.749486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2168 05:38:29.750037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2170 05:38:29.841722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2171 05:38:29.842194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2173 05:38:29.937497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2174 05:38:29.937968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2176 05:38:30.033373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2177 05:38:30.033879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2179 05:38:30.124278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2180 05:38:30.124775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2182 05:38:30.217391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2183 05:38:30.217937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2185 05:38:30.312700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2186 05:38:30.313181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2188 05:38:30.407967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2189 05:38:30.408474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2191 05:38:30.504100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2192 05:38:30.504602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2194 05:38:30.595378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2195 05:38:30.595861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2197 05:38:30.691349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2198 05:38:30.691831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2200 05:38:30.785906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2201 05:38:30.786495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2203 05:38:30.879666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2204 05:38:30.880145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2206 05:38:30.973749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2207 05:38:30.974228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2209 05:38:31.067637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2210 05:38:31.068116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2212 05:38:31.164711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2213 05:38:31.165338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2215 05:38:31.255744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2216 05:38:31.256242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2218 05:38:31.347473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2219 05:38:31.347952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2221 05:38:31.442651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2222 05:38:31.443133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2224 05:38:31.536859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2225 05:38:31.537335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2227 05:38:31.629395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2228 05:38:31.629883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2230 05:38:31.723835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2231 05:38:31.724405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2233 05:38:31.817550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2234 05:38:31.818033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2236 05:38:31.913014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2237 05:38:31.913488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2239 05:38:31.999686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2240 05:38:32.000170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2242 05:38:32.093322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2243 05:38:32.093810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2245 05:38:32.184820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2246 05:38:32.185369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2248 05:38:32.277445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2249 05:38:32.277933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2251 05:38:32.371175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2252 05:38:32.371653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2254 05:38:32.465671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2255 05:38:32.466155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2257 05:38:32.554190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2259 05:38:32.557177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2260 05:38:32.649055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2261 05:38:32.649556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2263 05:38:32.745939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2264 05:38:32.746505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2266 05:38:32.840309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2267 05:38:32.840789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2269 05:38:32.933795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2270 05:38:32.934275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2272 05:38:33.029917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2273 05:38:33.030397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2275 05:38:33.123281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2276 05:38:33.123758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2278 05:38:33.218241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2279 05:38:33.218777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2281 05:38:33.312601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2282 05:38:33.313071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2284 05:38:33.409982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2285 05:38:33.410462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2287 05:38:33.503226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2288 05:38:33.503696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2290 05:38:33.599986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2291 05:38:33.600477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2293 05:38:33.694552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2294 05:38:33.695046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2296 05:38:33.790118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2297 05:38:33.790676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2299 05:38:33.881260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2300 05:38:33.881743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2302 05:38:33.976731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2303 05:38:33.977199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2305 05:38:34.069764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2306 05:38:34.070242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2308 05:38:34.165395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2309 05:38:34.165873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2311 05:38:34.258390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2312 05:38:34.258939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2314 05:38:34.356498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2315 05:38:34.356982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2317 05:38:34.450009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2318 05:38:34.450493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2320 05:38:34.543369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2321 05:38:34.543849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2323 05:38:34.640999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2324 05:38:34.641481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2326 05:38:34.734206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2327 05:38:34.734800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2329 05:38:34.829971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2330 05:38:34.830450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2332 05:38:34.922962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2333 05:38:34.923435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2335 05:38:35.016013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2336 05:38:35.016528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2338 05:38:35.109440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2339 05:38:35.109910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2341 05:38:35.199737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2342 05:38:35.200265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2344 05:38:35.290918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2345 05:38:35.291386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2347 05:38:35.381309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2348 05:38:35.381779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2350 05:38:35.468139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2351 05:38:35.468474 + set +x
2352 05:38:35.468975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2354 05:38:35.472467 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1186402_1.6.2.4.5>
2355 05:38:35.472944 Received signal: <ENDRUN> 1_kselftest-dt 1186402_1.6.2.4.5
2356 05:38:35.473200 Ending use of test pattern.
2357 05:38:35.473438 Ending test lava.1_kselftest-dt (1186402_1.6.2.4.5), duration 77.22
2359 05:38:35.479831 <LAVA_TEST_RUNNER EXIT>
2360 05:38:35.480305 ok: lava_test_shell seems to have completed
2361 05:38:35.486110 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2362 05:38:35.487154 end: 3.1 lava-test-shell (duration 00:01:19) [common]
2363 05:38:35.487443 end: 3 lava-test-retry (duration 00:01:19) [common]
2364 05:38:35.487738 start: 4 finalize (timeout 00:06:03) [common]
2365 05:38:35.488032 start: 4.1 power-off (timeout 00:00:30) [common]
2366 05:38:35.488425 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2367 05:38:35.860375 Returned 0 in 0 seconds
2368 05:38:35.961261 end: 4.1 power-off (duration 00:00:00) [common]
2370 05:38:35.962141 start: 4.2 read-feedback (timeout 00:06:02) [common]
2371 05:38:35.962743 Listened to connection for namespace 'common' for up to 1s
2372 05:38:35.963284 Listened to connection for namespace 'common' for up to 1s
2373 05:38:36.963675 Finalising connection for namespace 'common'
2374 05:38:36.964111 Disconnecting from shell: Finalise
2375 05:38:36.964440 / #
2376 05:38:37.065010 end: 4.2 read-feedback (duration 00:00:01) [common]
2377 05:38:37.065376 end: 4 finalize (duration 00:00:02) [common]
2378 05:38:37.065712 Cleaning after the job
2379 05:38:37.066030 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/ramdisk
2380 05:38:37.069732 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/kernel
2381 05:38:37.072633 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/dtb
2382 05:38:37.073089 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/nfsrootfs
2383 05:38:37.124758 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186402/tftp-deploy-0oo8el0h/modules
2384 05:38:37.128227 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1186402
2385 05:38:37.774808 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1186402
2386 05:38:37.775070 Job finished correctly