Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:00:36.186136 lava-dispatcher, installed at version: 2024.01
2 06:00:36.186964 start: 0 validate
3 06:00:36.187425 Start time: 2024-08-31 06:00:36.187396+00:00 (UTC)
4 06:00:36.188027 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:00:36.188563 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 06:00:36.230826 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:00:36.231449 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 06:00:36.259348 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:00:36.260014 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 06:00:37.315235 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:00:37.315778 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
12 06:00:37.356699 validate duration: 1.17
14 06:00:37.357531 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:00:37.357841 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:00:37.358128 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:00:37.358706 Not decompressing ramdisk as can be used compressed.
18 06:00:37.359119 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 06:00:37.359388 saving as /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/ramdisk/rootfs.cpio.gz
20 06:00:37.359682 total size: 8181887 (7 MB)
21 06:00:37.394329 progress 0 % (0 MB)
22 06:00:37.404759 progress 5 % (0 MB)
23 06:00:37.412828 progress 10 % (0 MB)
24 06:00:37.418807 progress 15 % (1 MB)
25 06:00:37.424261 progress 20 % (1 MB)
26 06:00:37.430184 progress 25 % (1 MB)
27 06:00:37.435739 progress 30 % (2 MB)
28 06:00:37.441753 progress 35 % (2 MB)
29 06:00:37.447160 progress 40 % (3 MB)
30 06:00:37.452790 progress 45 % (3 MB)
31 06:00:37.458051 progress 50 % (3 MB)
32 06:00:37.463627 progress 55 % (4 MB)
33 06:00:37.469079 progress 60 % (4 MB)
34 06:00:37.474943 progress 65 % (5 MB)
35 06:00:37.480502 progress 70 % (5 MB)
36 06:00:37.486461 progress 75 % (5 MB)
37 06:00:37.491671 progress 80 % (6 MB)
38 06:00:37.497265 progress 85 % (6 MB)
39 06:00:37.502494 progress 90 % (7 MB)
40 06:00:37.508064 progress 95 % (7 MB)
41 06:00:37.513238 progress 100 % (7 MB)
42 06:00:37.514158 7 MB downloaded in 0.15 s (50.52 MB/s)
43 06:00:37.514831 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:00:37.515792 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:00:37.516148 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:00:37.516459 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:00:37.516969 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
49 06:00:37.517257 saving as /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/kernel/Image
50 06:00:37.517489 total size: 39019008 (37 MB)
51 06:00:37.517750 No compression specified
52 06:00:37.557954 progress 0 % (0 MB)
53 06:00:37.584574 progress 5 % (1 MB)
54 06:00:37.611506 progress 10 % (3 MB)
55 06:00:37.636713 progress 15 % (5 MB)
56 06:00:37.662866 progress 20 % (7 MB)
57 06:00:37.688539 progress 25 % (9 MB)
58 06:00:37.715024 progress 30 % (11 MB)
59 06:00:37.741508 progress 35 % (13 MB)
60 06:00:37.767520 progress 40 % (14 MB)
61 06:00:37.793115 progress 45 % (16 MB)
62 06:00:37.819053 progress 50 % (18 MB)
63 06:00:37.844052 progress 55 % (20 MB)
64 06:00:37.870452 progress 60 % (22 MB)
65 06:00:37.895920 progress 65 % (24 MB)
66 06:00:37.920642 progress 70 % (26 MB)
67 06:00:37.946447 progress 75 % (27 MB)
68 06:00:37.971657 progress 80 % (29 MB)
69 06:00:37.996698 progress 85 % (31 MB)
70 06:00:38.021701 progress 90 % (33 MB)
71 06:00:38.047609 progress 95 % (35 MB)
72 06:00:38.071680 progress 100 % (37 MB)
73 06:00:38.072479 37 MB downloaded in 0.55 s (67.05 MB/s)
74 06:00:38.072986 end: 1.2.1 http-download (duration 00:00:01) [common]
76 06:00:38.073810 end: 1.2 download-retry (duration 00:00:01) [common]
77 06:00:38.074088 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:00:38.074364 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:00:38.074874 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 06:00:38.075164 saving as /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 06:00:38.075375 total size: 53173 (0 MB)
82 06:00:38.075590 No compression specified
83 06:00:38.118142 progress 61 % (0 MB)
84 06:00:38.119033 progress 100 % (0 MB)
85 06:00:38.119578 0 MB downloaded in 0.04 s (1.15 MB/s)
86 06:00:38.120088 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:00:38.120922 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:00:38.121188 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:00:38.121453 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:00:38.121942 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
92 06:00:38.122195 saving as /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/modules/modules.tar
93 06:00:38.122408 total size: 11633732 (11 MB)
94 06:00:38.122624 Using unxz to decompress xz
95 06:00:38.156349 progress 0 % (0 MB)
96 06:00:38.235699 progress 5 % (0 MB)
97 06:00:38.322145 progress 10 % (1 MB)
98 06:00:38.419483 progress 15 % (1 MB)
99 06:00:38.506393 progress 20 % (2 MB)
100 06:00:38.586877 progress 25 % (2 MB)
101 06:00:38.678313 progress 30 % (3 MB)
102 06:00:38.763647 progress 35 % (3 MB)
103 06:00:38.847518 progress 40 % (4 MB)
104 06:00:38.926193 progress 45 % (5 MB)
105 06:00:39.010603 progress 50 % (5 MB)
106 06:00:39.091337 progress 55 % (6 MB)
107 06:00:39.183970 progress 60 % (6 MB)
108 06:00:39.273748 progress 65 % (7 MB)
109 06:00:39.363161 progress 70 % (7 MB)
110 06:00:39.463107 progress 75 % (8 MB)
111 06:00:39.565394 progress 80 % (8 MB)
112 06:00:39.652153 progress 85 % (9 MB)
113 06:00:39.729616 progress 90 % (10 MB)
114 06:00:39.808391 progress 95 % (10 MB)
115 06:00:39.886245 progress 100 % (11 MB)
116 06:00:39.897041 11 MB downloaded in 1.77 s (6.25 MB/s)
117 06:00:39.897985 end: 1.4.1 http-download (duration 00:00:02) [common]
119 06:00:39.899742 end: 1.4 download-retry (duration 00:00:02) [common]
120 06:00:39.900397 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 06:00:39.900980 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 06:00:39.901525 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:00:39.902082 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 06:00:39.903144 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz
125 06:00:39.904089 makedir: /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin
126 06:00:39.904805 makedir: /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/tests
127 06:00:39.905479 makedir: /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/results
128 06:00:39.906144 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-add-keys
129 06:00:39.907166 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-add-sources
130 06:00:39.908217 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-background-process-start
131 06:00:39.909272 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-background-process-stop
132 06:00:39.910320 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-common-functions
133 06:00:39.911389 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-echo-ipv4
134 06:00:39.912439 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-install-packages
135 06:00:39.913427 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-installed-packages
136 06:00:39.914392 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-os-build
137 06:00:39.915362 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-probe-channel
138 06:00:39.916418 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-probe-ip
139 06:00:39.917407 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-target-ip
140 06:00:39.918385 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-target-mac
141 06:00:39.919402 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-target-storage
142 06:00:39.920441 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-test-case
143 06:00:39.921433 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-test-event
144 06:00:39.922398 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-test-feedback
145 06:00:39.923364 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-test-raise
146 06:00:39.924427 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-test-reference
147 06:00:39.925430 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-test-runner
148 06:00:39.926404 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-test-set
149 06:00:39.927363 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-test-shell
150 06:00:39.928379 Updating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-install-packages (oe)
151 06:00:39.929553 Updating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/bin/lava-installed-packages (oe)
152 06:00:39.930482 Creating /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/environment
153 06:00:39.931291 LAVA metadata
154 06:00:39.931858 - LAVA_JOB_ID=681743
155 06:00:39.932382 - LAVA_DISPATCHER_IP=192.168.6.2
156 06:00:39.933124 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 06:00:39.935105 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 06:00:39.935759 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 06:00:39.936249 skipped lava-vland-overlay
160 06:00:39.936793 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 06:00:39.937359 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 06:00:39.937827 skipped lava-multinode-overlay
163 06:00:39.938361 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 06:00:39.938912 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 06:00:39.939432 Loading test definitions
166 06:00:39.940071 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 06:00:39.940535 Using /lava-681743 at stage 0
168 06:00:39.942749 uuid=681743_1.5.2.4.1 testdef=None
169 06:00:39.943330 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 06:00:39.943850 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 06:00:39.947247 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 06:00:39.948470 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 06:00:39.950784 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 06:00:39.951621 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 06:00:39.953841 runner path: /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/0/tests/0_dmesg test_uuid 681743_1.5.2.4.1
178 06:00:39.954434 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 06:00:39.955207 Creating lava-test-runner.conf files
181 06:00:39.955412 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681743/lava-overlay-vgipoyqz/lava-681743/0 for stage 0
182 06:00:39.955781 - 0_dmesg
183 06:00:39.956175 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 06:00:39.956464 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 06:00:39.980535 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 06:00:39.980971 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 06:00:39.981241 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 06:00:39.981511 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 06:00:39.981779 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 06:00:40.904618 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 06:00:40.905091 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 06:00:40.905335 extracting modules file /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681743/extract-overlay-ramdisk-65n8yx_b/ramdisk
193 06:00:42.341985 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 06:00:42.342450 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 06:00:42.342723 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681743/compress-overlay-596g0o3m/overlay-1.5.2.5.tar.gz to ramdisk
196 06:00:42.342937 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681743/compress-overlay-596g0o3m/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681743/extract-overlay-ramdisk-65n8yx_b/ramdisk
197 06:00:42.373233 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 06:00:42.373662 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 06:00:42.373931 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 06:00:42.374159 Converting downloaded kernel to a uImage
201 06:00:42.374466 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/kernel/Image /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/kernel/uImage
202 06:00:42.776526 output: Image Name:
203 06:00:42.776936 output: Created: Sat Aug 31 06:00:42 2024
204 06:00:42.777143 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 06:00:42.777347 output: Data Size: 39019008 Bytes = 38104.50 KiB = 37.21 MiB
206 06:00:42.777551 output: Load Address: 01080000
207 06:00:42.777750 output: Entry Point: 01080000
208 06:00:42.777946 output:
209 06:00:42.778278 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 06:00:42.778541 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 06:00:42.778808 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 06:00:42.779060 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 06:00:42.779314 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 06:00:42.779569 Building ramdisk /var/lib/lava/dispatcher/tmp/681743/extract-overlay-ramdisk-65n8yx_b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681743/extract-overlay-ramdisk-65n8yx_b/ramdisk
215 06:00:45.220509 >> 186561 blocks
216 06:00:54.373748 Adding RAMdisk u-boot header.
217 06:00:54.374486 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681743/extract-overlay-ramdisk-65n8yx_b/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681743/extract-overlay-ramdisk-65n8yx_b/ramdisk.cpio.gz.uboot
218 06:00:54.680784 output: Image Name:
219 06:00:54.681208 output: Created: Sat Aug 31 06:00:54 2024
220 06:00:54.681627 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 06:00:54.682038 output: Data Size: 26560271 Bytes = 25937.76 KiB = 25.33 MiB
222 06:00:54.682444 output: Load Address: 00000000
223 06:00:54.682846 output: Entry Point: 00000000
224 06:00:54.683239 output:
225 06:00:54.684429 rename /var/lib/lava/dispatcher/tmp/681743/extract-overlay-ramdisk-65n8yx_b/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/ramdisk/ramdisk.cpio.gz.uboot
226 06:00:54.685156 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 06:00:54.685708 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 06:00:54.686235 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 06:00:54.686708 No LXC device requested
230 06:00:54.687213 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 06:00:54.687727 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 06:00:54.688263 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 06:00:54.688698 Checking files for TFTP limit of 4294967296 bytes.
234 06:00:54.691351 end: 1 tftp-deploy (duration 00:00:17) [common]
235 06:00:54.691931 start: 2 uboot-action (timeout 00:05:00) [common]
236 06:00:54.692505 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 06:00:54.693019 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 06:00:54.693528 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 06:00:54.694065 Using kernel file from prepare-kernel: 681743/tftp-deploy-ldwytoca/kernel/uImage
240 06:00:54.694675 substitutions:
241 06:00:54.695090 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 06:00:54.695497 - {DTB_ADDR}: 0x01070000
243 06:00:54.695898 - {DTB}: 681743/tftp-deploy-ldwytoca/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 06:00:54.696337 - {INITRD}: 681743/tftp-deploy-ldwytoca/ramdisk/ramdisk.cpio.gz.uboot
245 06:00:54.696745 - {KERNEL_ADDR}: 0x01080000
246 06:00:54.697143 - {KERNEL}: 681743/tftp-deploy-ldwytoca/kernel/uImage
247 06:00:54.697538 - {LAVA_MAC}: None
248 06:00:54.697974 - {PRESEED_CONFIG}: None
249 06:00:54.698378 - {PRESEED_LOCAL}: None
250 06:00:54.698773 - {RAMDISK_ADDR}: 0x08000000
251 06:00:54.699163 - {RAMDISK}: 681743/tftp-deploy-ldwytoca/ramdisk/ramdisk.cpio.gz.uboot
252 06:00:54.699558 - {ROOT_PART}: None
253 06:00:54.699950 - {ROOT}: None
254 06:00:54.700373 - {SERVER_IP}: 192.168.6.2
255 06:00:54.700775 - {TEE_ADDR}: 0x83000000
256 06:00:54.701171 - {TEE}: None
257 06:00:54.701566 Parsed boot commands:
258 06:00:54.701947 - setenv autoload no
259 06:00:54.702337 - setenv initrd_high 0xffffffff
260 06:00:54.702726 - setenv fdt_high 0xffffffff
261 06:00:54.703114 - dhcp
262 06:00:54.703504 - setenv serverip 192.168.6.2
263 06:00:54.703892 - tftpboot 0x01080000 681743/tftp-deploy-ldwytoca/kernel/uImage
264 06:00:54.704311 - tftpboot 0x08000000 681743/tftp-deploy-ldwytoca/ramdisk/ramdisk.cpio.gz.uboot
265 06:00:54.704706 - tftpboot 0x01070000 681743/tftp-deploy-ldwytoca/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 06:00:54.705097 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 06:00:54.705493 - bootm 0x01080000 0x08000000 0x01070000
268 06:00:54.705991 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 06:00:54.707480 start: 2.3 connect-device (timeout 00:05:00) [common]
271 06:00:54.707932 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 06:00:54.722957 Setting prompt string to ['lava-test: # ']
273 06:00:54.724465 end: 2.3 connect-device (duration 00:00:00) [common]
274 06:00:54.725080 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 06:00:54.725687 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 06:00:54.726327 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 06:00:54.727535 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 06:00:54.764467 >> OK - accepted request
279 06:00:54.766629 Returned 0 in 0 seconds
280 06:00:54.867533 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 06:00:54.869253 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 06:00:54.869813 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 06:00:54.870302 Setting prompt string to ['Hit any key to stop autoboot']
285 06:00:54.870752 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 06:00:54.872337 Trying 192.168.56.21...
287 06:00:54.872834 Connected to conserv1.
288 06:00:54.873249 Escape character is '^]'.
289 06:00:54.873671
290 06:00:54.874096 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 06:00:54.874532
292 06:01:01.731187 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 06:01:01.731623 bl2_stage_init 0x01
294 06:01:01.731862 bl2_stage_init 0x81
295 06:01:01.736694 hw id: 0x0000 - pwm id 0x01
296 06:01:01.737017 bl2_stage_init 0xc1
297 06:01:01.742353 bl2_stage_init 0x02
298 06:01:01.742646
299 06:01:01.742863 L0:00000000
300 06:01:01.743071 L1:00000703
301 06:01:01.743271 L2:00008067
302 06:01:01.743470 L3:15000000
303 06:01:01.747919 S1:00000000
304 06:01:01.748205 B2:20282000
305 06:01:01.748412 B1:a0f83180
306 06:01:01.748614
307 06:01:01.748816 TE: 69449
308 06:01:01.749027
309 06:01:01.753456 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 06:01:01.753743
311 06:01:01.759080 Board ID = 1
312 06:01:01.759348 Set cpu clk to 24M
313 06:01:01.759555 Set clk81 to 24M
314 06:01:01.764677 Use GP1_pll as DSU clk.
315 06:01:01.764965 DSU clk: 1200 Mhz
316 06:01:01.765176 CPU clk: 1200 MHz
317 06:01:01.770309 Set clk81 to 166.6M
318 06:01:01.775959 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 06:01:01.776258 board id: 1
320 06:01:01.783153 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 06:01:01.793972 fw parse done
322 06:01:01.800022 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 06:01:01.842996 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 06:01:01.854273 PIEI prepare done
325 06:01:01.854645 fastboot data load
326 06:01:01.854879 fastboot data verify
327 06:01:01.859812 verify result: 266
328 06:01:01.865345 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 06:01:01.865629 LPDDR4 probe
330 06:01:01.865865 ddr clk to 1584MHz
331 06:01:01.873328 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 06:01:01.911116
333 06:01:01.911496 dmc_version 0001
334 06:01:01.918096 Check phy result
335 06:01:01.924171 INFO : End of CA training
336 06:01:01.924458 INFO : End of initialization
337 06:01:01.929684 INFO : Training has run successfully!
338 06:01:01.929941 Check phy result
339 06:01:01.935303 INFO : End of initialization
340 06:01:01.935595 INFO : End of read enable training
341 06:01:01.938578 INFO : End of fine write leveling
342 06:01:01.944172 INFO : End of Write leveling coarse delay
343 06:01:01.949757 INFO : Training has run successfully!
344 06:01:01.950045 Check phy result
345 06:01:01.950254 INFO : End of initialization
346 06:01:01.955352 INFO : End of read dq deskew training
347 06:01:01.960939 INFO : End of MPR read delay center optimization
348 06:01:01.961200 INFO : End of write delay center optimization
349 06:01:01.966542 INFO : End of read delay center optimization
350 06:01:01.972134 INFO : End of max read latency training
351 06:01:01.972389 INFO : Training has run successfully!
352 06:01:01.977765 1D training succeed
353 06:01:01.983649 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 06:01:02.031936 Check phy result
355 06:01:02.032341 INFO : End of initialization
356 06:01:02.057572 INFO : End of 2D read delay Voltage center optimization
357 06:01:02.082731 INFO : End of 2D read delay Voltage center optimization
358 06:01:02.138431 INFO : End of 2D write delay Voltage center optimization
359 06:01:02.193357 INFO : End of 2D write delay Voltage center optimization
360 06:01:02.198979 INFO : Training has run successfully!
361 06:01:02.199306
362 06:01:02.199534 channel==0
363 06:01:02.204569 RxClkDly_Margin_A0==78 ps 8
364 06:01:02.204893 TxDqDly_Margin_A0==98 ps 10
365 06:01:02.210034 RxClkDly_Margin_A1==78 ps 8
366 06:01:02.210356 TxDqDly_Margin_A1==88 ps 9
367 06:01:02.210582 TrainedVREFDQ_A0==76
368 06:01:02.215701 TrainedVREFDQ_A1==75
369 06:01:02.216054 VrefDac_Margin_A0==24
370 06:01:02.216294 DeviceVref_Margin_A0==38
371 06:01:02.221319 VrefDac_Margin_A1==22
372 06:01:02.221649 DeviceVref_Margin_A1==39
373 06:01:02.221881
374 06:01:02.222107
375 06:01:02.222324 channel==1
376 06:01:02.226954 RxClkDly_Margin_A0==78 ps 8
377 06:01:02.227275 TxDqDly_Margin_A0==88 ps 9
378 06:01:02.232561 RxClkDly_Margin_A1==88 ps 9
379 06:01:02.232894 TxDqDly_Margin_A1==98 ps 10
380 06:01:02.238137 TrainedVREFDQ_A0==75
381 06:01:02.238461 TrainedVREFDQ_A1==78
382 06:01:02.238687 VrefDac_Margin_A0==22
383 06:01:02.243771 DeviceVref_Margin_A0==39
384 06:01:02.244125 VrefDac_Margin_A1==22
385 06:01:02.249409 DeviceVref_Margin_A1==36
386 06:01:02.249746
387 06:01:02.249982 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 06:01:02.250200
389 06:01:02.283077 soc_vref_reg_value 0x 00000018 00000017 00000018 00000016 00000018 00000014 00000018 00000015 00000017 00000016 00000016 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000016 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 06:01:02.283508 2D training succeed
391 06:01:02.288552 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 06:01:02.294189 auto size-- 65535DDR cs0 size: 2048MB
393 06:01:02.294524 DDR cs1 size: 2048MB
394 06:01:02.299752 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 06:01:02.300114 cs0 DataBus test pass
396 06:01:02.305374 cs1 DataBus test pass
397 06:01:02.305693 cs0 AddrBus test pass
398 06:01:02.305923 cs1 AddrBus test pass
399 06:01:02.306142
400 06:01:02.310953 100bdlr_step_size ps== 478
401 06:01:02.311270 result report
402 06:01:02.316562 boot times 0Enable ddr reg access
403 06:01:02.320836 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 06:01:02.335608 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 06:01:02.994927 bl2z: ptr: 05129330, size: 00001e40
406 06:01:03.003966 0.0;M3 CHK:0;cm4_sp_mode 0
407 06:01:03.004359 MVN_1=0x00000000
408 06:01:03.004583 MVN_2=0x00000000
409 06:01:03.015471 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 06:01:03.015845 OPS=0x04
411 06:01:03.016116 ring efuse init
412 06:01:03.018462 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 06:01:03.024878 [0.017354 Inits done]
414 06:01:03.025227 secure task start!
415 06:01:03.025468 high task start!
416 06:01:03.025678 low task start!
417 06:01:03.029070 run into bl31
418 06:01:03.037761 NOTICE: BL31: v1.3(release):4fc40b1
419 06:01:03.045531 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 06:01:03.046045 NOTICE: BL31: G12A normal boot!
421 06:01:03.061130 NOTICE: BL31: BL33 decompress pass
422 06:01:03.066794 ERROR: Error initializing runtime service opteed_fast
423 06:01:04.280173 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 06:01:04.280861 bl2_stage_init 0x01
425 06:01:04.281324 bl2_stage_init 0x81
426 06:01:04.285452 hw id: 0x0000 - pwm id 0x01
427 06:01:04.286025 bl2_stage_init 0xc1
428 06:01:04.291083 bl2_stage_init 0x02
429 06:01:04.291655
430 06:01:04.292189 L0:00000000
431 06:01:04.292671 L1:00000703
432 06:01:04.293122 L2:00008067
433 06:01:04.293590 L3:15000000
434 06:01:04.296737 S1:00000000
435 06:01:04.297317 B2:20282000
436 06:01:04.297766 B1:a0f83180
437 06:01:04.298222
438 06:01:04.298667 TE: 68233
439 06:01:04.299103
440 06:01:04.302280 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 06:01:04.302841
442 06:01:04.307849 Board ID = 1
443 06:01:04.308366 Set cpu clk to 24M
444 06:01:04.308811 Set clk81 to 24M
445 06:01:04.313451 Use GP1_pll as DSU clk.
446 06:01:04.314077 DSU clk: 1200 Mhz
447 06:01:04.314541 CPU clk: 1200 MHz
448 06:01:04.319070 Set clk81 to 166.6M
449 06:01:04.324722 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 06:01:04.325130 board id: 1
451 06:01:04.332002 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 06:01:04.342576 fw parse done
453 06:01:04.348508 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 06:01:04.391154 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 06:01:04.402169 PIEI prepare done
456 06:01:04.402586 fastboot data load
457 06:01:04.402860 fastboot data verify
458 06:01:04.407760 verify result: 266
459 06:01:04.413339 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 06:01:04.413720 LPDDR4 probe
461 06:01:04.413989 ddr clk to 1584MHz
462 06:01:04.421495 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 06:01:05.786254 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
464 06:01:05.786862 bl2_stage_init 0x01
465 06:01:05.787300 bl2_stage_init 0x81
466 06:01:05.791954 hw id: 0x0000 - pwm id 0x01
467 06:01:05.792483 bl2_stage_init 0xc1
468 06:01:05.797433 bl2_stage_init 0x02
469 06:01:05.797959
470 06:01:05.798359 L0:00000000
471 06:01:05.798758 L1:00000703
472 06:01:05.799150 L2:00008067
473 06:01:05.799534 L3:15000000
474 06:01:05.803102 S1:00000000
475 06:01:05.803543 B2:20282000
476 06:01:05.803935 B1:a0f83180
477 06:01:05.804360
478 06:01:05.804751 TE: 73565
479 06:01:05.805139
480 06:01:05.808631 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
481 06:01:05.809077
482 06:01:05.814197 Board ID = 1
483 06:01:05.814635 Set cpu clk to 24M
484 06:01:05.815024 Set clk81 to 24M
485 06:01:05.819848 Use GP1_pll as DSU clk.
486 06:01:05.820316 DSU clk: 1200 Mhz
487 06:01:05.820709 CPU clk: 1200 MHz
488 06:01:05.825409 Set clk81 to 166.6M
489 06:01:05.831071 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
490 06:01:05.831505 board id: 1
491 06:01:05.838169 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
492 06:01:05.848849 fw parse done
493 06:01:05.854899 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
494 06:01:05.897468 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
495 06:01:05.908476 PIEI prepare done
496 06:01:05.908979 fastboot data load
497 06:01:05.909377 fastboot data verify
498 06:01:05.914100 verify result: 266
499 06:01:05.919685 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
500 06:01:05.920238 LPDDR4 probe
501 06:01:05.920638 ddr clk to 1584MHz
502 06:01:05.927678 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 06:01:05.964941
504 06:01:05.965443 dmc_version 0001
505 06:01:05.971621 Check phy result
506 06:01:05.977535 INFO : End of CA training
507 06:01:05.978002 INFO : End of initialization
508 06:01:05.983136 INFO : Training has run successfully!
509 06:01:05.983602 Check phy result
510 06:01:05.988815 INFO : End of initialization
511 06:01:05.989359 INFO : End of read enable training
512 06:01:05.994357 INFO : End of fine write leveling
513 06:01:05.999966 INFO : End of Write leveling coarse delay
514 06:01:06.000477 INFO : Training has run successfully!
515 06:01:06.000903 Check phy result
516 06:01:06.005589 INFO : End of initialization
517 06:01:06.006063 INFO : End of read dq deskew training
518 06:01:06.011204 INFO : End of MPR read delay center optimization
519 06:01:06.016832 INFO : End of write delay center optimization
520 06:01:06.022347 INFO : End of read delay center optimization
521 06:01:06.022823 INFO : End of max read latency training
522 06:01:06.027939 INFO : Training has run successfully!
523 06:01:06.028460 1D training succeed
524 06:01:06.037092 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
525 06:01:06.084673 Check phy result
526 06:01:06.085184 INFO : End of initialization
527 06:01:06.107426 INFO : End of 2D read delay Voltage center optimization
528 06:01:06.126106 INFO : End of 2D read delay Voltage center optimization
529 06:01:06.177952 INFO : End of 2D write delay Voltage center optimization
530 06:01:06.227254 INFO : End of 2D write delay Voltage center optimization
531 06:01:06.232770 INFO : Training has run successfully!
532 06:01:06.233135
533 06:01:06.233438 channel==0
534 06:01:06.238433 RxClkDly_Margin_A0==78 ps 8
535 06:01:06.238795 TxDqDly_Margin_A0==98 ps 10
536 06:01:06.244097 RxClkDly_Margin_A1==88 ps 9
537 06:01:06.244606 TxDqDly_Margin_A1==98 ps 10
538 06:01:06.245060 TrainedVREFDQ_A0==75
539 06:01:06.249547 TrainedVREFDQ_A1==74
540 06:01:06.249919 VrefDac_Margin_A0==24
541 06:01:06.250193 DeviceVref_Margin_A0==39
542 06:01:06.255236 VrefDac_Margin_A1==23
543 06:01:06.255599 DeviceVref_Margin_A1==40
544 06:01:06.255895
545 06:01:06.256216
546 06:01:06.260679 channel==1
547 06:01:06.261190 RxClkDly_Margin_A0==78 ps 8
548 06:01:06.261643 TxDqDly_Margin_A0==98 ps 10
549 06:01:06.266374 RxClkDly_Margin_A1==88 ps 9
550 06:01:06.266738 TxDqDly_Margin_A1==88 ps 9
551 06:01:06.271922 TrainedVREFDQ_A0==78
552 06:01:06.272304 TrainedVREFDQ_A1==77
553 06:01:06.272584 VrefDac_Margin_A0==22
554 06:01:06.277494 DeviceVref_Margin_A0==36
555 06:01:06.277846 VrefDac_Margin_A1==22
556 06:01:06.283156 DeviceVref_Margin_A1==37
557 06:01:06.283518
558 06:01:06.283810 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
559 06:01:06.284109
560 06:01:06.316713 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
561 06:01:06.317145 2D training succeed
562 06:01:06.322255 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
563 06:01:06.327930 auto size-- 65535DDR cs0 size: 2048MB
564 06:01:06.328310 DDR cs1 size: 2048MB
565 06:01:06.333524 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
566 06:01:06.334032 cs0 DataBus test pass
567 06:01:06.339173 cs1 DataBus test pass
568 06:01:06.339670 cs0 AddrBus test pass
569 06:01:06.340015 cs1 AddrBus test pass
570 06:01:06.340292
571 06:01:06.344639 100bdlr_step_size ps== 478
572 06:01:06.344991 result report
573 06:01:06.350305 boot times 0Enable ddr reg access
574 06:01:06.355500 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
575 06:01:06.369422 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
576 06:01:07.200229 bl2z: ptr: 05129330, size: 00001e40
577 06:01:07.200659 0.0;M3 CHK:0;cm4_sp_mode 0
578 06:01:07.200934 MVN_1=0x00000000
579 06:01:07.201202 MVN_2=0x00000000
580 06:01:07.201809 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
581 06:01:07.202203 OPS=0x04
582 06:01:07.202433 ring efuse init
583 06:01:07.202681 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
584 06:01:07.202953 [0.017319 Inits done]
585 06:01:07.203200 secure task start!
586 06:01:07.203444 high task start!
587 06:01:07.203682 low task start!
588 06:01:07.203925 run into bl31
589 06:01:07.204233 NOTICE: BL31: v1.3(release):4fc40b1
590 06:01:07.204504 NOTICE: BL31: Built : 15:57:33, May 22 2019
591 06:01:07.204764 NOTICE: BL31: G12A normal boot!
592 06:01:07.205021 NOTICE: BL31: BL33 decompress pass
593 06:01:07.205354 ERROR: Error initializing runtime service opteed_fast
594 06:01:08.335548 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
595 06:01:08.336250 bl2_stage_init 0x01
596 06:01:08.336739 bl2_stage_init 0x81
597 06:01:08.341106 hw id: 0x0000 - pwm id 0x01
598 06:01:08.341622 bl2_stage_init 0xc1
599 06:01:08.346111 bl2_stage_init 0x02
600 06:01:08.346665
601 06:01:08.347136 L0:00000000
602 06:01:08.347592 L1:00000703
603 06:01:08.348083 L2:00008067
604 06:01:08.351661 L3:15000000
605 06:01:08.352191 S1:00000000
606 06:01:08.352648 B2:20282000
607 06:01:08.353098 B1:a0f83180
608 06:01:08.353541
609 06:01:08.353982 TE: 73607
610 06:01:08.354419
611 06:01:08.362830 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
612 06:01:08.363383
613 06:01:08.363821 Board ID = 1
614 06:01:08.364280 Set cpu clk to 24M
615 06:01:08.364700 Set clk81 to 24M
616 06:01:08.368458 Use GP1_pll as DSU clk.
617 06:01:08.368937 DSU clk: 1200 Mhz
618 06:01:08.369362 CPU clk: 1200 MHz
619 06:01:08.374039 Set clk81 to 166.6M
620 06:01:08.379600 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
621 06:01:08.380091 board id: 1
622 06:01:08.387518 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
623 06:01:08.398494 fw parse done
624 06:01:08.404381 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
625 06:01:08.447535 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
626 06:01:08.458673 PIEI prepare done
627 06:01:08.459147 fastboot data load
628 06:01:08.459574 fastboot data verify
629 06:01:08.464208 verify result: 266
630 06:01:08.469732 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
631 06:01:08.470196 LPDDR4 probe
632 06:01:08.470618 ddr clk to 1584MHz
633 06:01:08.477711 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
634 06:01:08.515573
635 06:01:08.516081 dmc_version 0001
636 06:01:08.522523 Check phy result
637 06:01:08.528439 INFO : End of CA training
638 06:01:08.528905 INFO : End of initialization
639 06:01:08.534079 INFO : Training has run successfully!
640 06:01:08.534547 Check phy result
641 06:01:08.539665 INFO : End of initialization
642 06:01:08.540157 INFO : End of read enable training
643 06:01:08.545397 INFO : End of fine write leveling
644 06:01:08.550915 INFO : End of Write leveling coarse delay
645 06:01:08.551391 INFO : Training has run successfully!
646 06:01:08.551808 Check phy result
647 06:01:08.556490 INFO : End of initialization
648 06:01:08.556954 INFO : End of read dq deskew training
649 06:01:08.562038 INFO : End of MPR read delay center optimization
650 06:01:08.567648 INFO : End of write delay center optimization
651 06:01:08.573328 INFO : End of read delay center optimization
652 06:01:08.573827 INFO : End of max read latency training
653 06:01:08.578885 INFO : Training has run successfully!
654 06:01:08.579346 1D training succeed
655 06:01:08.588065 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
656 06:01:08.636346 Check phy result
657 06:01:08.636833 INFO : End of initialization
658 06:01:08.663755 INFO : End of 2D read delay Voltage center optimization
659 06:01:08.687934 INFO : End of 2D read delay Voltage center optimization
660 06:01:08.744691 INFO : End of 2D write delay Voltage center optimization
661 06:01:08.798721 INFO : End of 2D write delay Voltage center optimization
662 06:01:08.804129 INFO : Training has run successfully!
663 06:01:08.804429
664 06:01:08.804663 channel==0
665 06:01:08.809750 RxClkDly_Margin_A0==88 ps 9
666 06:01:08.810221 TxDqDly_Margin_A0==98 ps 10
667 06:01:08.815300 RxClkDly_Margin_A1==88 ps 9
668 06:01:08.815762 TxDqDly_Margin_A1==88 ps 9
669 06:01:08.816234 TrainedVREFDQ_A0==74
670 06:01:08.821022 TrainedVREFDQ_A1==74
671 06:01:08.821384 VrefDac_Margin_A0==24
672 06:01:08.821640 DeviceVref_Margin_A0==40
673 06:01:08.826703 VrefDac_Margin_A1==23
674 06:01:08.827218 DeviceVref_Margin_A1==40
675 06:01:08.827684
676 06:01:08.828149
677 06:01:08.828501 channel==1
678 06:01:08.832164 RxClkDly_Margin_A0==78 ps 8
679 06:01:08.832506 TxDqDly_Margin_A0==98 ps 10
680 06:01:08.837779 RxClkDly_Margin_A1==88 ps 9
681 06:01:08.838261 TxDqDly_Margin_A1==88 ps 9
682 06:01:08.843441 TrainedVREFDQ_A0==78
683 06:01:08.843932 TrainedVREFDQ_A1==77
684 06:01:08.844406 VrefDac_Margin_A0==22
685 06:01:08.849086 DeviceVref_Margin_A0==36
686 06:01:08.849589 VrefDac_Margin_A1==22
687 06:01:08.854724 DeviceVref_Margin_A1==37
688 06:01:08.855197
689 06:01:08.855630 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
690 06:01:08.856088
691 06:01:08.888134 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000016 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
692 06:01:08.888661 2D training succeed
693 06:01:08.893776 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
694 06:01:08.899209 auto size-- 65535DDR cs0 size: 2048MB
695 06:01:08.899683 DDR cs1 size: 2048MB
696 06:01:08.904834 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
697 06:01:08.905302 cs0 DataBus test pass
698 06:01:08.910503 cs1 DataBus test pass
699 06:01:08.911024 cs0 AddrBus test pass
700 06:01:08.911450 cs1 AddrBus test pass
701 06:01:08.911869
702 06:01:08.916032 100bdlr_step_size ps== 464
703 06:01:08.916546 result report
704 06:01:08.921620 boot times 0Enable ddr reg access
705 06:01:08.926788 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
706 06:01:08.940673 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
707 06:01:09.599070 bl2z: ptr: 05129330, size: 00001e40
708 06:01:09.607387 0.0;M3 CHK:0;cm4_sp_mode 0
709 06:01:09.607877 MVN_1=0x00000000
710 06:01:09.608178 MVN_2=0x00000000
711 06:01:09.618885 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
712 06:01:09.619243 OPS=0x04
713 06:01:09.619473 ring efuse init
714 06:01:09.624533 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
715 06:01:09.624875 [0.017354 Inits done]
716 06:01:09.625098 secure task start!
717 06:01:09.632226 high task start!
718 06:01:09.632712 low task start!
719 06:01:09.633067 run into bl31
720 06:01:09.640828 NOTICE: BL31: v1.3(release):4fc40b1
721 06:01:09.648640 NOTICE: BL31: Built : 15:57:33, May 22 2019
722 06:01:09.648981 NOTICE: BL31: G12A normal boot!
723 06:01:09.664227 NOTICE: BL31: BL33 decompress pass
724 06:01:09.669862 ERROR: Error initializing runtime service opteed_fast
725 06:01:10.464053
726 06:01:10.464485
727 06:01:10.469465 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
728 06:01:10.469784
729 06:01:10.472916 Model: Libre Computer AML-S905D3-CC Solitude
730 06:01:10.619863 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
731 06:01:10.635257 DRAM: 2 GiB (effective 3.8 GiB)
732 06:01:10.736174 Core: 406 devices, 33 uclasses, devicetree: separate
733 06:01:10.741985 WDT: Not starting watchdog@f0d0
734 06:01:10.767092 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
735 06:01:10.779768 Loading Environment from FAT... Card did not respond to voltage select! : -110
736 06:01:10.784300 ** Bad device specification mmc 0 **
737 06:01:10.794354 Card did not respond to voltage select! : -110
738 06:01:10.802011 ** Bad device specification mmc 0 **
739 06:01:10.802344 Couldn't find partition mmc 0
740 06:01:10.810311 Card did not respond to voltage select! : -110
741 06:01:10.815906 ** Bad device specification mmc 0 **
742 06:01:10.816254 Couldn't find partition mmc 0
743 06:01:10.820867 Error: could not access storage.
744 06:01:11.117329 Net: eth0: ethernet@ff3f0000
745 06:01:11.117768 starting USB...
746 06:01:11.361977 Bus usb@ff500000: Register 3000140 NbrPorts 3
747 06:01:11.362435 Starting the controller
748 06:01:11.368916 USB XHCI 1.10
749 06:01:12.925707 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
750 06:01:12.933917 scanning usb for storage devices... 0 Storage Device(s) found
752 06:01:12.985404 Hit any key to stop autoboot: 1
753 06:01:12.986197 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
754 06:01:12.986801 start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
755 06:01:12.987287 Setting prompt string to ['=>']
756 06:01:12.987779 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:42)
757 06:01:12.999927 0
758 06:01:13.000824 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
760 06:01:13.102024 => setenv autoload no
761 06:01:13.102655 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
762 06:01:13.107424 setenv autoload no
764 06:01:13.208894 => setenv initrd_high 0xffffffff
765 06:01:13.209527 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
766 06:01:13.213826 setenv initrd_high 0xffffffff
768 06:01:13.315261 => setenv fdt_high 0xffffffff
769 06:01:13.316019 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
770 06:01:13.320267 setenv fdt_high 0xffffffff
772 06:01:13.421669 => dhcp
773 06:01:13.423408 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
774 06:01:13.426170 dhcp
775 06:01:14.532353 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
776 06:01:14.532929 Speed: 1000, full duplex
777 06:01:14.533280 BOOTP broadcast 1
778 06:01:14.781072 BOOTP broadcast 2
779 06:01:15.280902 BOOTP broadcast 3
780 06:01:16.282933 BOOTP broadcast 4
781 06:01:18.283943 BOOTP broadcast 5
782 06:01:18.302369 DHCP client bound to address 192.168.6.12 (3770 ms)
784 06:01:18.403878 => setenv serverip 192.168.6.2
785 06:01:18.404627 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
786 06:01:18.408880 setenv serverip 192.168.6.2
788 06:01:18.510383 => tftpboot 0x01080000 681743/tftp-deploy-ldwytoca/kernel/uImage
789 06:01:18.511220 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
790 06:01:18.517822 tftpboot 0x01080000 681743/tftp-deploy-ldwytoca/kernel/uImage
791 06:01:18.518342 Speed: 1000, full duplex
792 06:01:18.518767 Using ethernet@ff3f0000 device
793 06:01:18.523356 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
794 06:01:18.528781 Filename '681743/tftp-deploy-ldwytoca/kernel/uImage'.
795 06:01:18.532759 Load address: 0x1080000
796 06:01:21.379494 Loading: *################################################## 37.2 MiB
797 06:01:21.379935 13.1 MiB/s
798 06:01:21.380204 done
799 06:01:21.382627 Bytes transferred = 39019072 (2536240 hex)
801 06:01:21.483826 => tftpboot 0x08000000 681743/tftp-deploy-ldwytoca/ramdisk/ramdisk.cpio.gz.uboot
802 06:01:21.484977 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
803 06:01:21.491710 tftpboot 0x08000000 681743/tftp-deploy-ldwytoca/ramdisk/ramdisk.cpio.gz.uboot
804 06:01:21.492611 Speed: 1000, full duplex
805 06:01:21.493130 Using ethernet@ff3f0000 device
806 06:01:21.497199 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
807 06:01:21.507914 Filename '681743/tftp-deploy-ldwytoca/ramdisk/ramdisk.cpio.gz.uboot'.
808 06:01:21.508385 Load address: 0x8000000
809 06:01:23.401764 Loading: *################################################# UDP wrong checksum 00000005 0000b6f4
810 06:01:28.402225 T UDP wrong checksum 00000005 0000b6f4
811 06:01:38.404324 T T UDP wrong checksum 00000005 0000b6f4
812 06:01:45.263288 T UDP wrong checksum 000000ff 000002cf
813 06:01:45.288659 UDP wrong checksum 000000ff 00008bc1
814 06:01:58.408162 T T T UDP wrong checksum 00000005 0000b6f4
815 06:02:18.412023 T T T
816 06:02:18.412442 Retry count exceeded; starting again
818 06:02:18.415368 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
821 06:02:18.416367 end: 2.4 uboot-commands (duration 00:01:24) [common]
823 06:02:18.417089 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
825 06:02:18.417649 end: 2 uboot-action (duration 00:01:24) [common]
827 06:02:18.418462 Cleaning after the job
828 06:02:18.418780 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/ramdisk
829 06:02:18.419587 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/kernel
830 06:02:18.435891 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/dtb
831 06:02:18.436983 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681743/tftp-deploy-ldwytoca/modules
832 06:02:18.442959 start: 4.1 power-off (timeout 00:00:30) [common]
833 06:02:18.443576 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
834 06:02:18.476537 >> OK - accepted request
835 06:02:18.478342 Returned 0 in 0 seconds
836 06:02:18.579104 end: 4.1 power-off (duration 00:00:00) [common]
838 06:02:18.580171 start: 4.2 read-feedback (timeout 00:10:00) [common]
839 06:02:18.580846 Listened to connection for namespace 'common' for up to 1s
840 06:02:19.581859 Finalising connection for namespace 'common'
841 06:02:19.582645 Disconnecting from shell: Finalise
842 06:02:19.583042 =>
843 06:02:19.684050 end: 4.2 read-feedback (duration 00:00:01) [common]
844 06:02:19.684883 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681743
845 06:02:20.037223 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681743
846 06:02:20.037864 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.