Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:01:56.321337 lava-dispatcher, installed at version: 2024.01
2 06:01:56.322120 start: 0 validate
3 06:01:56.322597 Start time: 2024-08-31 06:01:56.322566+00:00 (UTC)
4 06:01:56.323127 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:01:56.323670 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 06:01:56.360344 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:01:56.360947 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fkernel%2FImage exists
8 06:01:56.389140 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:01:56.389790 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:01:56.423529 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:01:56.424084 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:01:56.455179 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 06:01:56.455670 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fmodules.tar.xz exists
14 06:01:56.489391 validate duration: 0.17
16 06:01:56.490262 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:01:56.490602 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:01:56.490928 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:01:56.491527 Not decompressing ramdisk as can be used compressed.
20 06:01:56.492010 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 06:01:56.492313 saving as /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/ramdisk/initrd.cpio.gz
22 06:01:56.492595 total size: 5628182 (5 MB)
23 06:01:56.525838 progress 0 % (0 MB)
24 06:01:56.530075 progress 5 % (0 MB)
25 06:01:56.534257 progress 10 % (0 MB)
26 06:01:56.538011 progress 15 % (0 MB)
27 06:01:56.542046 progress 20 % (1 MB)
28 06:01:56.545715 progress 25 % (1 MB)
29 06:01:56.549844 progress 30 % (1 MB)
30 06:01:56.554010 progress 35 % (1 MB)
31 06:01:56.557688 progress 40 % (2 MB)
32 06:01:56.561751 progress 45 % (2 MB)
33 06:01:56.565351 progress 50 % (2 MB)
34 06:01:56.569292 progress 55 % (2 MB)
35 06:01:56.573315 progress 60 % (3 MB)
36 06:01:56.576834 progress 65 % (3 MB)
37 06:01:56.580717 progress 70 % (3 MB)
38 06:01:56.584239 progress 75 % (4 MB)
39 06:01:56.588191 progress 80 % (4 MB)
40 06:01:56.591654 progress 85 % (4 MB)
41 06:01:56.595564 progress 90 % (4 MB)
42 06:01:56.599221 progress 95 % (5 MB)
43 06:01:56.602453 progress 100 % (5 MB)
44 06:01:56.603108 5 MB downloaded in 0.11 s (48.57 MB/s)
45 06:01:56.603673 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:01:56.604635 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:01:56.604948 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:01:56.605235 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:01:56.605716 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/kernel/Image
51 06:01:56.606000 saving as /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/kernel/Image
52 06:01:56.606222 total size: 39021056 (37 MB)
53 06:01:56.606443 No compression specified
54 06:01:56.639816 progress 0 % (0 MB)
55 06:01:56.664778 progress 5 % (1 MB)
56 06:01:56.690013 progress 10 % (3 MB)
57 06:01:56.714973 progress 15 % (5 MB)
58 06:01:56.739885 progress 20 % (7 MB)
59 06:01:56.765007 progress 25 % (9 MB)
60 06:01:56.790130 progress 30 % (11 MB)
61 06:01:56.814599 progress 35 % (13 MB)
62 06:01:56.839692 progress 40 % (14 MB)
63 06:01:56.864501 progress 45 % (16 MB)
64 06:01:56.889838 progress 50 % (18 MB)
65 06:01:56.914415 progress 55 % (20 MB)
66 06:01:56.939516 progress 60 % (22 MB)
67 06:01:56.964398 progress 65 % (24 MB)
68 06:01:56.989485 progress 70 % (26 MB)
69 06:01:57.014412 progress 75 % (27 MB)
70 06:01:57.038816 progress 80 % (29 MB)
71 06:01:57.063942 progress 85 % (31 MB)
72 06:01:57.089020 progress 90 % (33 MB)
73 06:01:57.113996 progress 95 % (35 MB)
74 06:01:57.138109 progress 100 % (37 MB)
75 06:01:57.138846 37 MB downloaded in 0.53 s (69.87 MB/s)
76 06:01:57.139353 end: 1.2.1 http-download (duration 00:00:01) [common]
78 06:01:57.140257 end: 1.2 download-retry (duration 00:00:01) [common]
79 06:01:57.140570 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:01:57.140864 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:01:57.141358 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 06:01:57.141617 saving as /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/dtb/meson-g12b-a311d-libretech-cc.dtb
83 06:01:57.141835 total size: 54667 (0 MB)
84 06:01:57.142054 No compression specified
85 06:01:57.187572 progress 59 % (0 MB)
86 06:01:57.190006 progress 100 % (0 MB)
87 06:01:57.190899 0 MB downloaded in 0.05 s (1.06 MB/s)
88 06:01:57.191413 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:01:57.192347 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:01:57.192655 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:01:57.192955 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:01:57.193484 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 06:01:57.194335 saving as /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/nfsrootfs/full.rootfs.tar
95 06:01:57.194565 total size: 107552908 (102 MB)
96 06:01:57.194797 Using unxz to decompress xz
97 06:01:57.232480 progress 0 % (0 MB)
98 06:01:57.874378 progress 5 % (5 MB)
99 06:01:58.591798 progress 10 % (10 MB)
100 06:01:59.310375 progress 15 % (15 MB)
101 06:02:00.073720 progress 20 % (20 MB)
102 06:02:00.649093 progress 25 % (25 MB)
103 06:02:01.274287 progress 30 % (30 MB)
104 06:02:02.019223 progress 35 % (35 MB)
105 06:02:02.367218 progress 40 % (41 MB)
106 06:02:02.794520 progress 45 % (46 MB)
107 06:02:03.501083 progress 50 % (51 MB)
108 06:02:04.195769 progress 55 % (56 MB)
109 06:02:04.955705 progress 60 % (61 MB)
110 06:02:05.714111 progress 65 % (66 MB)
111 06:02:06.452782 progress 70 % (71 MB)
112 06:02:07.226529 progress 75 % (76 MB)
113 06:02:07.914408 progress 80 % (82 MB)
114 06:02:08.634461 progress 85 % (87 MB)
115 06:02:09.372522 progress 90 % (92 MB)
116 06:02:10.089757 progress 95 % (97 MB)
117 06:02:10.860063 progress 100 % (102 MB)
118 06:02:10.873483 102 MB downloaded in 13.68 s (7.50 MB/s)
119 06:02:10.874211 end: 1.4.1 http-download (duration 00:00:14) [common]
121 06:02:10.875265 end: 1.4 download-retry (duration 00:00:14) [common]
122 06:02:10.875631 start: 1.5 download-retry (timeout 00:09:46) [common]
123 06:02:10.875968 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 06:02:10.876545 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/modules.tar.xz
125 06:02:10.876843 saving as /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/modules/modules.tar
126 06:02:10.877096 total size: 11634432 (11 MB)
127 06:02:10.877343 Using unxz to decompress xz
128 06:02:10.929378 progress 0 % (0 MB)
129 06:02:11.001876 progress 5 % (0 MB)
130 06:02:11.096812 progress 10 % (1 MB)
131 06:02:11.195194 progress 15 % (1 MB)
132 06:02:11.286706 progress 20 % (2 MB)
133 06:02:11.366685 progress 25 % (2 MB)
134 06:02:11.457418 progress 30 % (3 MB)
135 06:02:11.540382 progress 35 % (3 MB)
136 06:02:11.624139 progress 40 % (4 MB)
137 06:02:11.701442 progress 45 % (5 MB)
138 06:02:11.783533 progress 50 % (5 MB)
139 06:02:11.863213 progress 55 % (6 MB)
140 06:02:11.951328 progress 60 % (6 MB)
141 06:02:12.036984 progress 65 % (7 MB)
142 06:02:12.124887 progress 70 % (7 MB)
143 06:02:12.250220 progress 75 % (8 MB)
144 06:02:12.370784 progress 80 % (8 MB)
145 06:02:12.450651 progress 85 % (9 MB)
146 06:02:12.534127 progress 90 % (10 MB)
147 06:02:12.616483 progress 95 % (10 MB)
148 06:02:12.698018 progress 100 % (11 MB)
149 06:02:12.709004 11 MB downloaded in 1.83 s (6.06 MB/s)
150 06:02:12.709919 end: 1.5.1 http-download (duration 00:00:02) [common]
152 06:02:12.711198 end: 1.5 download-retry (duration 00:00:02) [common]
153 06:02:12.711611 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 06:02:12.712124 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 06:02:22.449669 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/681647/extract-nfsrootfs-7d_kx62n
156 06:02:22.450272 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 06:02:22.450581 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 06:02:22.451217 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj
159 06:02:22.451671 makedir: /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin
160 06:02:22.452048 makedir: /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/tests
161 06:02:22.452403 makedir: /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/results
162 06:02:22.452760 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-add-keys
163 06:02:22.453313 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-add-sources
164 06:02:22.453833 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-background-process-start
165 06:02:22.454341 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-background-process-stop
166 06:02:22.454880 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-common-functions
167 06:02:22.455401 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-echo-ipv4
168 06:02:22.455913 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-install-packages
169 06:02:22.456456 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-installed-packages
170 06:02:22.456965 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-os-build
171 06:02:22.457466 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-probe-channel
172 06:02:22.457967 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-probe-ip
173 06:02:22.458458 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-target-ip
174 06:02:22.458979 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-target-mac
175 06:02:22.459492 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-target-storage
176 06:02:22.460020 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-test-case
177 06:02:22.460535 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-test-event
178 06:02:22.461035 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-test-feedback
179 06:02:22.461530 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-test-raise
180 06:02:22.462023 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-test-reference
181 06:02:22.462520 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-test-runner
182 06:02:22.463019 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-test-set
183 06:02:22.463528 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-test-shell
184 06:02:22.464055 Updating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-install-packages (oe)
185 06:02:22.464612 Updating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/bin/lava-installed-packages (oe)
186 06:02:22.465070 Creating /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/environment
187 06:02:22.465467 LAVA metadata
188 06:02:22.465738 - LAVA_JOB_ID=681647
189 06:02:22.465963 - LAVA_DISPATCHER_IP=192.168.6.2
190 06:02:22.466318 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 06:02:22.467261 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 06:02:22.467573 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 06:02:22.467794 skipped lava-vland-overlay
194 06:02:22.468065 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 06:02:22.468339 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 06:02:22.468565 skipped lava-multinode-overlay
197 06:02:22.468819 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 06:02:22.469081 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 06:02:22.469339 Loading test definitions
200 06:02:22.469627 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 06:02:22.469855 Using /lava-681647 at stage 0
202 06:02:22.471023 uuid=681647_1.6.2.4.1 testdef=None
203 06:02:22.471326 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 06:02:22.471600 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 06:02:22.473532 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 06:02:22.474359 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 06:02:22.476608 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 06:02:22.477445 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 06:02:22.479578 runner path: /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/0/tests/0_dmesg test_uuid 681647_1.6.2.4.1
212 06:02:22.480140 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 06:02:22.480911 Creating lava-test-runner.conf files
215 06:02:22.481121 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681647/lava-overlay-tibfc3bj/lava-681647/0 for stage 0
216 06:02:22.481472 - 0_dmesg
217 06:02:22.481824 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 06:02:22.482109 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 06:02:22.503788 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 06:02:22.504261 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 06:02:22.504550 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 06:02:22.504837 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 06:02:22.505114 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 06:02:23.124850 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 06:02:23.125321 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 06:02:23.125590 extracting modules file /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681647/extract-nfsrootfs-7d_kx62n
227 06:02:24.481684 extracting modules file /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681647/extract-overlay-ramdisk-3xxajepb/ramdisk
228 06:02:25.875175 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 06:02:25.875649 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
230 06:02:25.875942 [common] Applying overlay to NFS
231 06:02:25.876191 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681647/compress-overlay-8iczlpa3/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681647/extract-nfsrootfs-7d_kx62n
232 06:02:25.905075 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 06:02:25.905443 start: 1.6.6 prepare-kernel (timeout 00:09:31) [common]
234 06:02:25.905729 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:31) [common]
235 06:02:25.905964 Converting downloaded kernel to a uImage
236 06:02:25.906271 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/kernel/Image /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/kernel/uImage
237 06:02:26.309384 output: Image Name:
238 06:02:26.309812 output: Created: Sat Aug 31 06:02:25 2024
239 06:02:26.310040 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 06:02:26.310256 output: Data Size: 39021056 Bytes = 38106.50 KiB = 37.21 MiB
241 06:02:26.310466 output: Load Address: 01080000
242 06:02:26.310671 output: Entry Point: 01080000
243 06:02:26.310874 output:
244 06:02:26.311217 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 06:02:26.311491 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 06:02:26.311768 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 06:02:26.312055 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 06:02:26.312332 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 06:02:26.312597 Building ramdisk /var/lib/lava/dispatcher/tmp/681647/extract-overlay-ramdisk-3xxajepb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681647/extract-overlay-ramdisk-3xxajepb/ramdisk
250 06:02:28.496359 >> 171779 blocks
251 06:02:36.113249 Adding RAMdisk u-boot header.
252 06:02:36.113705 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681647/extract-overlay-ramdisk-3xxajepb/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681647/extract-overlay-ramdisk-3xxajepb/ramdisk.cpio.gz.uboot
253 06:02:36.362771 output: Image Name:
254 06:02:36.363168 output: Created: Sat Aug 31 06:02:36 2024
255 06:02:36.363380 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 06:02:36.363586 output: Data Size: 23939105 Bytes = 23378.03 KiB = 22.83 MiB
257 06:02:36.363787 output: Load Address: 00000000
258 06:02:36.364056 output: Entry Point: 00000000
259 06:02:36.364508 output:
260 06:02:36.365672 rename /var/lib/lava/dispatcher/tmp/681647/extract-overlay-ramdisk-3xxajepb/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/ramdisk/ramdisk.cpio.gz.uboot
261 06:02:36.366517 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 06:02:36.367141 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 06:02:36.367727 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 06:02:36.368261 No LXC device requested
265 06:02:36.368809 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 06:02:36.369370 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 06:02:36.369910 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 06:02:36.370358 Checking files for TFTP limit of 4294967296 bytes.
269 06:02:36.373340 end: 1 tftp-deploy (duration 00:00:40) [common]
270 06:02:36.373967 start: 2 uboot-action (timeout 00:05:00) [common]
271 06:02:36.374540 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 06:02:36.375086 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 06:02:36.375633 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 06:02:36.376236 Using kernel file from prepare-kernel: 681647/tftp-deploy-lotfnr53/kernel/uImage
275 06:02:36.376923 substitutions:
276 06:02:36.377370 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 06:02:36.377814 - {DTB_ADDR}: 0x01070000
278 06:02:36.378252 - {DTB}: 681647/tftp-deploy-lotfnr53/dtb/meson-g12b-a311d-libretech-cc.dtb
279 06:02:36.378689 - {INITRD}: 681647/tftp-deploy-lotfnr53/ramdisk/ramdisk.cpio.gz.uboot
280 06:02:36.379122 - {KERNEL_ADDR}: 0x01080000
281 06:02:36.379550 - {KERNEL}: 681647/tftp-deploy-lotfnr53/kernel/uImage
282 06:02:36.380001 - {LAVA_MAC}: None
283 06:02:36.380481 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/681647/extract-nfsrootfs-7d_kx62n
284 06:02:36.380919 - {NFS_SERVER_IP}: 192.168.6.2
285 06:02:36.381347 - {PRESEED_CONFIG}: None
286 06:02:36.381796 - {PRESEED_LOCAL}: None
287 06:02:36.382234 - {RAMDISK_ADDR}: 0x08000000
288 06:02:36.382666 - {RAMDISK}: 681647/tftp-deploy-lotfnr53/ramdisk/ramdisk.cpio.gz.uboot
289 06:02:36.383114 - {ROOT_PART}: None
290 06:02:36.383545 - {ROOT}: None
291 06:02:36.384133 - {SERVER_IP}: 192.168.6.2
292 06:02:36.384586 - {TEE_ADDR}: 0x83000000
293 06:02:36.385022 - {TEE}: None
294 06:02:36.385457 Parsed boot commands:
295 06:02:36.385882 - setenv autoload no
296 06:02:36.386327 - setenv initrd_high 0xffffffff
297 06:02:36.386767 - setenv fdt_high 0xffffffff
298 06:02:36.387190 - dhcp
299 06:02:36.387618 - setenv serverip 192.168.6.2
300 06:02:36.388071 - tftpboot 0x01080000 681647/tftp-deploy-lotfnr53/kernel/uImage
301 06:02:36.388502 - tftpboot 0x08000000 681647/tftp-deploy-lotfnr53/ramdisk/ramdisk.cpio.gz.uboot
302 06:02:36.388931 - tftpboot 0x01070000 681647/tftp-deploy-lotfnr53/dtb/meson-g12b-a311d-libretech-cc.dtb
303 06:02:36.389359 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/681647/extract-nfsrootfs-7d_kx62n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 06:02:36.389800 - bootm 0x01080000 0x08000000 0x01070000
305 06:02:36.390352 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 06:02:36.391977 start: 2.3 connect-device (timeout 00:05:00) [common]
308 06:02:36.392463 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 06:02:36.407346 Setting prompt string to ['lava-test: # ']
310 06:02:36.408978 end: 2.3 connect-device (duration 00:00:00) [common]
311 06:02:36.409630 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 06:02:36.410228 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 06:02:36.410819 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 06:02:36.412327 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 06:02:36.449621 >> OK - accepted request
316 06:02:36.451933 Returned 0 in 0 seconds
317 06:02:36.553228 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 06:02:36.555067 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 06:02:36.555725 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 06:02:36.556351 Setting prompt string to ['Hit any key to stop autoboot']
322 06:02:36.556870 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 06:02:36.558631 Trying 192.168.56.21...
324 06:02:36.559179 Connected to conserv1.
325 06:02:36.559639 Escape character is '^]'.
326 06:02:36.560136
327 06:02:36.560603 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 06:02:36.561071
329 06:02:48.495519 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 06:02:48.496324 bl2_stage_init 0x01
331 06:02:48.496826 bl2_stage_init 0x81
332 06:02:48.500964 hw id: 0x0000 - pwm id 0x01
333 06:02:48.501487 bl2_stage_init 0xc1
334 06:02:48.501928 bl2_stage_init 0x02
335 06:02:48.502360
336 06:02:48.506572 L0:00000000
337 06:02:48.507071 L1:20000703
338 06:02:48.507519 L2:00008067
339 06:02:48.507960 L3:14000000
340 06:02:48.512200 B2:00402000
341 06:02:48.512698 B1:e0f83180
342 06:02:48.513149
343 06:02:48.513585 TE: 58159
344 06:02:48.514040
345 06:02:48.517758 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 06:02:48.518252
347 06:02:48.518698 Board ID = 1
348 06:02:48.523376 Set A53 clk to 24M
349 06:02:48.523861 Set A73 clk to 24M
350 06:02:48.524341 Set clk81 to 24M
351 06:02:48.528908 A53 clk: 1200 MHz
352 06:02:48.529387 A73 clk: 1200 MHz
353 06:02:48.529819 CLK81: 166.6M
354 06:02:48.530243 smccc: 00012ab5
355 06:02:48.534562 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 06:02:48.540217 board id: 1
357 06:02:48.545288 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 06:02:48.556769 fw parse done
359 06:02:48.562060 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 06:02:48.604603 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 06:02:48.616089 PIEI prepare done
362 06:02:48.616575 fastboot data load
363 06:02:48.617017 fastboot data verify
364 06:02:48.621823 verify result: 266
365 06:02:48.627346 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 06:02:48.627829 LPDDR4 probe
367 06:02:48.628308 ddr clk to 1584MHz
368 06:02:48.634477 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 06:02:48.672580
370 06:02:48.673108 dmc_version 0001
371 06:02:48.678720 Check phy result
372 06:02:48.685199 INFO : End of CA training
373 06:02:48.685683 INFO : End of initialization
374 06:02:48.690824 INFO : Training has run successfully!
375 06:02:48.691350 Check phy result
376 06:02:48.696351 INFO : End of initialization
377 06:02:48.696854 INFO : End of read enable training
378 06:02:48.699708 INFO : End of fine write leveling
379 06:02:48.705199 INFO : End of Write leveling coarse delay
380 06:02:48.710828 INFO : Training has run successfully!
381 06:02:48.711326 Check phy result
382 06:02:48.711778 INFO : End of initialization
383 06:02:48.716394 INFO : End of read dq deskew training
384 06:02:48.722018 INFO : End of MPR read delay center optimization
385 06:02:48.722556 INFO : End of write delay center optimization
386 06:02:48.727615 INFO : End of read delay center optimization
387 06:02:48.733208 INFO : End of max read latency training
388 06:02:48.733705 INFO : Training has run successfully!
389 06:02:48.738797 1D training succeed
390 06:02:48.744514 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 06:02:48.791429 Check phy result
392 06:02:48.792021 INFO : End of initialization
393 06:02:48.813293 INFO : End of 2D read delay Voltage center optimization
394 06:02:48.834115 INFO : End of 2D read delay Voltage center optimization
395 06:02:48.885796 INFO : End of 2D write delay Voltage center optimization
396 06:02:48.935681 INFO : End of 2D write delay Voltage center optimization
397 06:02:48.941265 INFO : Training has run successfully!
398 06:02:48.941769
399 06:02:48.942237 channel==0
400 06:02:48.946841 RxClkDly_Margin_A0==88 ps 9
401 06:02:48.947336 TxDqDly_Margin_A0==98 ps 10
402 06:02:48.950223 RxClkDly_Margin_A1==88 ps 9
403 06:02:48.950712 TxDqDly_Margin_A1==98 ps 10
404 06:02:48.955755 TrainedVREFDQ_A0==74
405 06:02:48.956276 TrainedVREFDQ_A1==74
406 06:02:48.956741 VrefDac_Margin_A0==25
407 06:02:48.961356 DeviceVref_Margin_A0==40
408 06:02:48.961852 VrefDac_Margin_A1==25
409 06:02:48.966948 DeviceVref_Margin_A1==40
410 06:02:48.967452
411 06:02:48.967916
412 06:02:48.968421 channel==1
413 06:02:48.968877 RxClkDly_Margin_A0==88 ps 9
414 06:02:48.970459 TxDqDly_Margin_A0==98 ps 10
415 06:02:48.975930 RxClkDly_Margin_A1==88 ps 9
416 06:02:48.976648 TxDqDly_Margin_A1==88 ps 9
417 06:02:48.977323 TrainedVREFDQ_A0==77
418 06:02:48.981595 TrainedVREFDQ_A1==77
419 06:02:48.982135 VrefDac_Margin_A0==22
420 06:02:48.987122 DeviceVref_Margin_A0==37
421 06:02:48.987787 VrefDac_Margin_A1==24
422 06:02:48.988464 DeviceVref_Margin_A1==37
423 06:02:48.989102
424 06:02:48.992732 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 06:02:48.993381
426 06:02:49.026385 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
427 06:02:49.027226 2D training succeed
428 06:02:49.032020 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 06:02:49.037647 auto size-- 65535DDR cs0 size: 2048MB
430 06:02:49.038187 DDR cs1 size: 2048MB
431 06:02:49.043158 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 06:02:49.043727 cs0 DataBus test pass
433 06:02:49.044271 cs1 DataBus test pass
434 06:02:49.048758 cs0 AddrBus test pass
435 06:02:49.049417 cs1 AddrBus test pass
436 06:02:49.050067
437 06:02:49.054361 100bdlr_step_size ps== 420
438 06:02:49.054910 result report
439 06:02:49.055400 boot times 0Enable ddr reg access
440 06:02:49.064172 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 06:02:49.077192 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 06:02:49.651248 0.0;M3 CHK:0;cm4_sp_mode 0
443 06:02:49.651826 MVN_1=0x00000000
444 06:02:49.656720 MVN_2=0x00000000
445 06:02:49.662644 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 06:02:49.663149 OPS=0x10
447 06:02:49.663623 ring efuse init
448 06:02:49.664128 chipver efuse init
449 06:02:49.668207 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 06:02:49.673781 [0.018961 Inits done]
451 06:02:49.674278 secure task start!
452 06:02:49.674737 high task start!
453 06:02:49.677415 low task start!
454 06:02:49.677900 run into bl31
455 06:02:49.684988 NOTICE: BL31: v1.3(release):4fc40b1
456 06:02:49.692716 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 06:02:49.693212 NOTICE: BL31: G12A normal boot!
458 06:02:49.718136 NOTICE: BL31: BL33 decompress pass
459 06:02:49.722934 ERROR: Error initializing runtime service opteed_fast
460 06:02:50.956706
461 06:02:50.957389
462 06:02:50.965060 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 06:02:50.965558
464 06:02:50.966024 Model: Libre Computer AML-A311D-CC Alta
465 06:02:51.173367 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 06:02:51.196855 DRAM: 2 GiB (effective 3.8 GiB)
467 06:02:51.339945 Core: 408 devices, 31 uclasses, devicetree: separate
468 06:02:51.345735 WDT: Not starting watchdog@f0d0
469 06:02:51.378089 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 06:02:51.390509 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 06:02:51.394579 ** Bad device specification mmc 0 **
472 06:02:51.405889 Card did not respond to voltage select! : -110
473 06:02:51.412580 ** Bad device specification mmc 0 **
474 06:02:51.413550 Couldn't find partition mmc 0
475 06:02:51.422019 Card did not respond to voltage select! : -110
476 06:02:51.427377 ** Bad device specification mmc 0 **
477 06:02:51.427897 Couldn't find partition mmc 0
478 06:02:51.431478 Error: could not access storage.
479 06:02:52.696238 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
480 06:02:52.696877 bl2_stage_init 0x81
481 06:02:52.701526 hw id: 0x0000 - pwm id 0x01
482 06:02:52.702093 bl2_stage_init 0xc1
483 06:02:52.702558 bl2_stage_init 0x02
484 06:02:52.703013
485 06:02:52.707192 L0:00000000
486 06:02:52.707748 L1:20000703
487 06:02:52.708255 L2:00008067
488 06:02:52.708713 L3:14000000
489 06:02:52.709159 B2:00402000
490 06:02:52.710034 B1:e0f83180
491 06:02:52.710572
492 06:02:52.711045 TE: 58150
493 06:02:52.711502
494 06:02:52.721018 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 06:02:52.721592
496 06:02:52.722060 Board ID = 1
497 06:02:52.722521 Set A53 clk to 24M
498 06:02:52.722979 Set A73 clk to 24M
499 06:02:52.726638 Set clk81 to 24M
500 06:02:52.727164 A53 clk: 1200 MHz
501 06:02:52.727629 A73 clk: 1200 MHz
502 06:02:52.730216 CLK81: 166.6M
503 06:02:52.730739 smccc: 00012aac
504 06:02:52.735652 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 06:02:52.741152 board id: 1
506 06:02:52.745585 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 06:02:52.757106 fw parse done
508 06:02:52.762270 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 06:02:52.804752 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 06:02:52.816786 PIEI prepare done
511 06:02:52.817332 fastboot data load
512 06:02:52.817811 fastboot data verify
513 06:02:52.822395 verify result: 266
514 06:02:52.827909 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 06:02:52.828488 LPDDR4 probe
516 06:02:52.828950 ddr clk to 1584MHz
517 06:02:52.835017 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 06:02:52.872294
519 06:02:52.872833 dmc_version 0001
520 06:02:52.878850 Check phy result
521 06:02:52.885649 INFO : End of CA training
522 06:02:52.886168 INFO : End of initialization
523 06:02:52.891226 INFO : Training has run successfully!
524 06:02:52.891744 Check phy result
525 06:02:52.896829 INFO : End of initialization
526 06:02:52.897351 INFO : End of read enable training
527 06:02:52.900268 INFO : End of fine write leveling
528 06:02:52.905833 INFO : End of Write leveling coarse delay
529 06:02:52.911326 INFO : Training has run successfully!
530 06:02:52.911838 Check phy result
531 06:02:52.912357 INFO : End of initialization
532 06:02:52.916992 INFO : End of read dq deskew training
533 06:02:52.922546 INFO : End of MPR read delay center optimization
534 06:02:52.923061 INFO : End of write delay center optimization
535 06:02:52.928185 INFO : End of read delay center optimization
536 06:02:52.933857 INFO : End of max read latency training
537 06:02:52.934396 INFO : Training has run successfully!
538 06:02:52.939398 1D training succeed
539 06:02:52.944399 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 06:02:52.991884 Check phy result
541 06:02:52.992474 INFO : End of initialization
542 06:02:53.013563 INFO : End of 2D read delay Voltage center optimization
543 06:02:53.033764 INFO : End of 2D read delay Voltage center optimization
544 06:02:53.085882 INFO : End of 2D write delay Voltage center optimization
545 06:02:53.136110 INFO : End of 2D write delay Voltage center optimization
546 06:02:53.141709 INFO : Training has run successfully!
547 06:02:53.142226
548 06:02:53.142705 channel==0
549 06:02:53.147288 RxClkDly_Margin_A0==88 ps 9
550 06:02:53.147803 TxDqDly_Margin_A0==98 ps 10
551 06:02:53.150554 RxClkDly_Margin_A1==88 ps 9
552 06:02:53.151062 TxDqDly_Margin_A1==98 ps 10
553 06:02:53.156268 TrainedVREFDQ_A0==74
554 06:02:53.156789 TrainedVREFDQ_A1==76
555 06:02:53.161764 VrefDac_Margin_A0==25
556 06:02:53.162291 DeviceVref_Margin_A0==40
557 06:02:53.162748 VrefDac_Margin_A1==25
558 06:02:53.167324 DeviceVref_Margin_A1==38
559 06:02:53.167842
560 06:02:53.168344
561 06:02:53.168795 channel==1
562 06:02:53.169236 RxClkDly_Margin_A0==98 ps 10
563 06:02:53.170654 TxDqDly_Margin_A0==98 ps 10
564 06:02:53.176325 RxClkDly_Margin_A1==98 ps 10
565 06:02:53.176865 TxDqDly_Margin_A1==98 ps 10
566 06:02:53.181806 TrainedVREFDQ_A0==77
567 06:02:53.182421 TrainedVREFDQ_A1==77
568 06:02:53.183030 VrefDac_Margin_A0==22
569 06:02:53.187485 DeviceVref_Margin_A0==37
570 06:02:53.188094 VrefDac_Margin_A1==22
571 06:02:53.188639 DeviceVref_Margin_A1==37
572 06:02:53.189092
573 06:02:53.196344 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 06:02:53.196877
575 06:02:53.227843 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
576 06:02:53.228529 2D training succeed
577 06:02:53.231111 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 06:02:53.236578 auto size-- 65535DDR cs0 size: 2048MB
579 06:02:53.237123 DDR cs1 size: 2048MB
580 06:02:53.242197 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 06:02:53.242736 cs0 DataBus test pass
582 06:02:53.247884 cs1 DataBus test pass
583 06:02:53.248450 cs0 AddrBus test pass
584 06:02:53.248899 cs1 AddrBus test pass
585 06:02:53.249336
586 06:02:53.251397 100bdlr_step_size ps== 420
587 06:02:53.256979 result report
588 06:02:53.257822 boot times 0Enable ddr reg access
589 06:02:53.263882 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 06:02:53.277459 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 06:02:53.852037 0.0;M3 CHK:0;cm4_sp_mode 0
592 06:02:53.852924 MVN_1=0x00000000
593 06:02:53.857493 MVN_2=0x00000000
594 06:02:53.863249 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 06:02:53.863917 OPS=0x10
596 06:02:53.864494 ring efuse init
597 06:02:53.864941 chipver efuse init
598 06:02:53.871479 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 06:02:53.872052 [0.018961 Inits done]
600 06:02:53.879037 secure task start!
601 06:02:53.879569 high task start!
602 06:02:53.880063 low task start!
603 06:02:53.880511 run into bl31
604 06:02:53.885725 NOTICE: BL31: v1.3(release):4fc40b1
605 06:02:53.893562 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 06:02:53.894100 NOTICE: BL31: G12A normal boot!
607 06:02:53.918948 NOTICE: BL31: BL33 decompress pass
608 06:02:53.924672 ERROR: Error initializing runtime service opteed_fast
609 06:02:55.157555
610 06:02:55.158182
611 06:02:55.165641 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 06:02:55.166170
613 06:02:55.166631 Model: Libre Computer AML-A311D-CC Alta
614 06:02:55.374275 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 06:02:55.396968 DRAM: 2 GiB (effective 3.8 GiB)
616 06:02:55.540712 Core: 408 devices, 31 uclasses, devicetree: separate
617 06:02:55.546610 WDT: Not starting watchdog@f0d0
618 06:02:55.578845 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 06:02:55.591264 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 06:02:55.596294 ** Bad device specification mmc 0 **
621 06:02:55.606628 Card did not respond to voltage select! : -110
622 06:02:55.614264 ** Bad device specification mmc 0 **
623 06:02:55.614803 Couldn't find partition mmc 0
624 06:02:55.622652 Card did not respond to voltage select! : -110
625 06:02:55.628181 ** Bad device specification mmc 0 **
626 06:02:55.628706 Couldn't find partition mmc 0
627 06:02:55.633236 Error: could not access storage.
628 06:02:55.975743 Net: eth0: ethernet@ff3f0000
629 06:02:55.976483 starting USB...
630 06:02:56.227400 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 06:02:56.227790 Starting the controller
632 06:02:56.234340 USB XHCI 1.10
633 06:02:57.946150 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 06:02:57.946812 bl2_stage_init 0x01
635 06:02:57.947292 bl2_stage_init 0x81
636 06:02:57.951652 hw id: 0x0000 - pwm id 0x01
637 06:02:57.952223 bl2_stage_init 0xc1
638 06:02:57.953630 bl2_stage_init 0x02
639 06:02:57.954196
640 06:02:57.957201 L0:00000000
641 06:02:57.957720 L1:20000703
642 06:02:57.958169 L2:00008067
643 06:02:57.958636 L3:14000000
644 06:02:57.962839 B2:00402000
645 06:02:57.963357 B1:e0f83180
646 06:02:57.963816
647 06:02:57.964328 TE: 58159
648 06:02:57.964802
649 06:02:57.968359 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 06:02:57.968901
651 06:02:57.969388 Board ID = 1
652 06:02:57.974023 Set A53 clk to 24M
653 06:02:57.974770 Set A73 clk to 24M
654 06:02:57.975348 Set clk81 to 24M
655 06:02:57.979693 A53 clk: 1200 MHz
656 06:02:57.980396 A73 clk: 1200 MHz
657 06:02:57.980920 CLK81: 166.6M
658 06:02:57.981493 smccc: 00012ab5
659 06:02:57.985209 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 06:02:57.990831 board id: 1
661 06:02:57.996734 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 06:02:58.007419 fw parse done
663 06:02:58.013445 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 06:02:58.056054 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 06:02:58.066864 PIEI prepare done
666 06:02:58.067366 fastboot data load
667 06:02:58.067797 fastboot data verify
668 06:02:58.072491 verify result: 266
669 06:02:58.078024 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 06:02:58.078503 LPDDR4 probe
671 06:02:58.078918 ddr clk to 1584MHz
672 06:02:58.086006 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 06:02:58.123321
674 06:02:58.123897 dmc_version 0001
675 06:02:58.129943 Check phy result
676 06:02:58.135858 INFO : End of CA training
677 06:02:58.136365 INFO : End of initialization
678 06:02:58.141380 INFO : Training has run successfully!
679 06:02:58.141850 Check phy result
680 06:02:58.146986 INFO : End of initialization
681 06:02:58.147446 INFO : End of read enable training
682 06:02:58.152628 INFO : End of fine write leveling
683 06:02:58.158157 INFO : End of Write leveling coarse delay
684 06:02:58.158628 INFO : Training has run successfully!
685 06:02:58.159038 Check phy result
686 06:02:58.163926 INFO : End of initialization
687 06:02:58.164510 INFO : End of read dq deskew training
688 06:02:58.169456 INFO : End of MPR read delay center optimization
689 06:02:58.174985 INFO : End of write delay center optimization
690 06:02:58.180585 INFO : End of read delay center optimization
691 06:02:58.181106 INFO : End of max read latency training
692 06:02:58.186180 INFO : Training has run successfully!
693 06:02:58.186693 1D training succeed
694 06:02:58.195333 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 06:02:58.243062 Check phy result
696 06:02:58.243771 INFO : End of initialization
697 06:02:58.264631 INFO : End of 2D read delay Voltage center optimization
698 06:02:58.283972 INFO : End of 2D read delay Voltage center optimization
699 06:02:58.335878 INFO : End of 2D write delay Voltage center optimization
700 06:02:58.384997 INFO : End of 2D write delay Voltage center optimization
701 06:02:58.390597 INFO : Training has run successfully!
702 06:02:58.390974
703 06:02:58.391223 channel==0
704 06:02:58.396777 RxClkDly_Margin_A0==88 ps 9
705 06:02:58.397139 TxDqDly_Margin_A0==98 ps 10
706 06:02:58.401771 RxClkDly_Margin_A1==88 ps 9
707 06:02:58.402151 TxDqDly_Margin_A1==88 ps 9
708 06:02:58.402523 TrainedVREFDQ_A0==74
709 06:02:58.407334 TrainedVREFDQ_A1==74
710 06:02:58.407724 VrefDac_Margin_A0==25
711 06:02:58.407936 DeviceVref_Margin_A0==40
712 06:02:58.412841 VrefDac_Margin_A1==25
713 06:02:58.413140 DeviceVref_Margin_A1==40
714 06:02:58.413369
715 06:02:58.413622
716 06:02:58.413844 channel==1
717 06:02:58.418529 RxClkDly_Margin_A0==88 ps 9
718 06:02:58.418869 TxDqDly_Margin_A0==98 ps 10
719 06:02:58.424047 RxClkDly_Margin_A1==88 ps 9
720 06:02:58.424329 TxDqDly_Margin_A1==88 ps 9
721 06:02:58.429667 TrainedVREFDQ_A0==77
722 06:02:58.430016 TrainedVREFDQ_A1==77
723 06:02:58.430235 VrefDac_Margin_A0==23
724 06:02:58.435301 DeviceVref_Margin_A0==37
725 06:02:58.435958 VrefDac_Margin_A1==24
726 06:02:58.440907 DeviceVref_Margin_A1==37
727 06:02:58.441533
728 06:02:58.442097 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 06:02:58.442648
730 06:02:58.474641 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000019 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
731 06:02:58.475284 2D training succeed
732 06:02:58.480195 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 06:02:58.485770 auto size-- 65535DDR cs0 size: 2048MB
734 06:02:58.486430 DDR cs1 size: 2048MB
735 06:02:58.491373 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 06:02:58.492056 cs0 DataBus test pass
737 06:02:58.497005 cs1 DataBus test pass
738 06:02:58.497626 cs0 AddrBus test pass
739 06:02:58.498181 cs1 AddrBus test pass
740 06:02:58.498677
741 06:02:58.502627 100bdlr_step_size ps== 420
742 06:02:58.503286 result report
743 06:02:58.508287 boot times 0Enable ddr reg access
744 06:02:58.513369 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 06:02:58.528403 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 06:02:59.098930 0.0;M3 CHK:0;cm4_sp_mode 0
747 06:02:59.099345 MVN_1=0x00000000
748 06:02:59.104710 MVN_2=0x00000000
749 06:02:59.110148 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 06:02:59.110624 OPS=0x10
751 06:02:59.111025 ring efuse init
752 06:02:59.111418 chipver efuse init
753 06:02:59.115709 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 06:02:59.121376 [0.018960 Inits done]
755 06:02:59.121881 secure task start!
756 06:02:59.122281 high task start!
757 06:02:59.126057 low task start!
758 06:02:59.126623 run into bl31
759 06:02:59.132648 NOTICE: BL31: v1.3(release):4fc40b1
760 06:02:59.140451 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 06:02:59.141003 NOTICE: BL31: G12A normal boot!
762 06:02:59.165807 NOTICE: BL31: BL33 decompress pass
763 06:02:59.171649 ERROR: Error initializing runtime service opteed_fast
764 06:03:00.404367
765 06:03:00.405033
766 06:03:00.412687 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 06:03:00.413211
768 06:03:00.413660 Model: Libre Computer AML-A311D-CC Alta
769 06:03:00.620257 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 06:03:00.643763 DRAM: 2 GiB (effective 3.8 GiB)
771 06:03:00.787369 Core: 408 devices, 31 uclasses, devicetree: separate
772 06:03:00.793451 WDT: Not starting watchdog@f0d0
773 06:03:00.825515 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 06:03:00.837970 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 06:03:00.842277 ** Bad device specification mmc 0 **
776 06:03:00.853309 Card did not respond to voltage select! : -110
777 06:03:00.861123 ** Bad device specification mmc 0 **
778 06:03:00.861630 Couldn't find partition mmc 0
779 06:03:00.869272 Card did not respond to voltage select! : -110
780 06:03:00.874800 ** Bad device specification mmc 0 **
781 06:03:00.875295 Couldn't find partition mmc 0
782 06:03:00.879826 Error: could not access storage.
783 06:03:01.223558 Net: eth0: ethernet@ff3f0000
784 06:03:01.224261 starting USB...
785 06:03:01.475203 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 06:03:01.475841 Starting the controller
787 06:03:01.482228 USB XHCI 1.10
788 06:03:03.647600 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 06:03:03.648041 bl2_stage_init 0x01
790 06:03:03.648274 bl2_stage_init 0x81
791 06:03:03.653071 hw id: 0x0000 - pwm id 0x01
792 06:03:03.653472 bl2_stage_init 0xc1
793 06:03:03.653797 bl2_stage_init 0x02
794 06:03:03.654112
795 06:03:03.658620 L0:00000000
796 06:03:03.659003 L1:20000703
797 06:03:03.659246 L2:00008067
798 06:03:03.659459 L3:14000000
799 06:03:03.664176 B2:00402000
800 06:03:03.664553 B1:e0f83180
801 06:03:03.664882
802 06:03:03.665207 TE: 58124
803 06:03:03.665529
804 06:03:03.669780 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 06:03:03.670061
806 06:03:03.670275 Board ID = 1
807 06:03:03.675502 Set A53 clk to 24M
808 06:03:03.675877 Set A73 clk to 24M
809 06:03:03.676239 Set clk81 to 24M
810 06:03:03.680975 A53 clk: 1200 MHz
811 06:03:03.681339 A73 clk: 1200 MHz
812 06:03:03.681658 CLK81: 166.6M
813 06:03:03.681887 smccc: 00012a92
814 06:03:03.686569 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 06:03:03.692173 board id: 1
816 06:03:03.697174 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 06:03:03.708754 fw parse done
818 06:03:03.714679 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 06:03:03.757354 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 06:03:03.768229 PIEI prepare done
821 06:03:03.768533 fastboot data load
822 06:03:03.768754 fastboot data verify
823 06:03:03.773930 verify result: 266
824 06:03:03.779630 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 06:03:03.779906 LPDDR4 probe
826 06:03:03.780163 ddr clk to 1584MHz
827 06:03:03.786456 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 06:03:03.823926
829 06:03:03.824308 dmc_version 0001
830 06:03:03.830719 Check phy result
831 06:03:03.837265 INFO : End of CA training
832 06:03:03.837546 INFO : End of initialization
833 06:03:03.842882 INFO : Training has run successfully!
834 06:03:03.843150 Check phy result
835 06:03:03.848720 INFO : End of initialization
836 06:03:03.848992 INFO : End of read enable training
837 06:03:03.851790 INFO : End of fine write leveling
838 06:03:03.857393 INFO : End of Write leveling coarse delay
839 06:03:03.862979 INFO : Training has run successfully!
840 06:03:03.863260 Check phy result
841 06:03:03.863488 INFO : End of initialization
842 06:03:03.868617 INFO : End of read dq deskew training
843 06:03:03.874241 INFO : End of MPR read delay center optimization
844 06:03:03.874652 INFO : End of write delay center optimization
845 06:03:03.879797 INFO : End of read delay center optimization
846 06:03:03.885375 INFO : End of max read latency training
847 06:03:03.885663 INFO : Training has run successfully!
848 06:03:03.890968 1D training succeed
849 06:03:03.896838 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 06:03:03.944702 Check phy result
851 06:03:03.945094 INFO : End of initialization
852 06:03:03.967042 INFO : End of 2D read delay Voltage center optimization
853 06:03:03.986485 INFO : End of 2D read delay Voltage center optimization
854 06:03:04.037633 INFO : End of 2D write delay Voltage center optimization
855 06:03:04.087881 INFO : End of 2D write delay Voltage center optimization
856 06:03:04.093418 INFO : Training has run successfully!
857 06:03:04.093708
858 06:03:04.093926 channel==0
859 06:03:04.098932 RxClkDly_Margin_A0==88 ps 9
860 06:03:04.099342 TxDqDly_Margin_A0==98 ps 10
861 06:03:04.104631 RxClkDly_Margin_A1==88 ps 9
862 06:03:04.104921 TxDqDly_Margin_A1==98 ps 10
863 06:03:04.105139 TrainedVREFDQ_A0==74
864 06:03:04.110896 TrainedVREFDQ_A1==74
865 06:03:04.111168 VrefDac_Margin_A0==24
866 06:03:04.111379 DeviceVref_Margin_A0==40
867 06:03:04.115776 VrefDac_Margin_A1==24
868 06:03:04.116057 DeviceVref_Margin_A1==40
869 06:03:04.116269
870 06:03:04.116474
871 06:03:04.121399 channel==1
872 06:03:04.121666 RxClkDly_Margin_A0==88 ps 9
873 06:03:04.121875 TxDqDly_Margin_A0==98 ps 10
874 06:03:04.127092 RxClkDly_Margin_A1==88 ps 9
875 06:03:04.127413 TxDqDly_Margin_A1==88 ps 9
876 06:03:04.132651 TrainedVREFDQ_A0==77
877 06:03:04.132927 TrainedVREFDQ_A1==77
878 06:03:04.133139 VrefDac_Margin_A0==23
879 06:03:04.138227 DeviceVref_Margin_A0==37
880 06:03:04.138499 VrefDac_Margin_A1==24
881 06:03:04.143740 DeviceVref_Margin_A1==37
882 06:03:04.144043
883 06:03:04.144261 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 06:03:04.144469
885 06:03:04.177359 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
886 06:03:04.177696 2D training succeed
887 06:03:04.182941 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 06:03:04.188643 auto size-- 65535DDR cs0 size: 2048MB
889 06:03:04.188912 DDR cs1 size: 2048MB
890 06:03:04.194138 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 06:03:04.194406 cs0 DataBus test pass
892 06:03:04.199746 cs1 DataBus test pass
893 06:03:04.200040 cs0 AddrBus test pass
894 06:03:04.200258 cs1 AddrBus test pass
895 06:03:04.200463
896 06:03:04.205375 100bdlr_step_size ps== 420
897 06:03:04.205649 result report
898 06:03:04.210957 boot times 0Enable ddr reg access
899 06:03:04.215363 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 06:03:04.229747 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 06:03:04.803457 0.0;M3 CHK:0;cm4_sp_mode 0
902 06:03:04.803899 MVN_1=0x00000000
903 06:03:04.808849 MVN_2=0x00000000
904 06:03:04.814696 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 06:03:04.814985 OPS=0x10
906 06:03:04.815206 ring efuse init
907 06:03:04.815429 chipver efuse init
908 06:03:04.822834 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 06:03:04.823266 [0.018961 Inits done]
910 06:03:04.830463 secure task start!
911 06:03:04.830865 high task start!
912 06:03:04.831106 low task start!
913 06:03:04.831316 run into bl31
914 06:03:04.837074 NOTICE: BL31: v1.3(release):4fc40b1
915 06:03:04.844880 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 06:03:04.845305 NOTICE: BL31: G12A normal boot!
917 06:03:04.870254 NOTICE: BL31: BL33 decompress pass
918 06:03:04.876185 ERROR: Error initializing runtime service opteed_fast
919 06:03:06.108870
920 06:03:06.109273
921 06:03:06.117231 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 06:03:06.117640
923 06:03:06.117955 Model: Libre Computer AML-A311D-CC Alta
924 06:03:06.327082 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 06:03:06.349002 DRAM: 2 GiB (effective 3.8 GiB)
926 06:03:06.492002 Core: 408 devices, 31 uclasses, devicetree: separate
927 06:03:06.497920 WDT: Not starting watchdog@f0d0
928 06:03:06.530113 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 06:03:06.542586 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 06:03:06.547441 ** Bad device specification mmc 0 **
931 06:03:06.557899 Card did not respond to voltage select! : -110
932 06:03:06.565590 ** Bad device specification mmc 0 **
933 06:03:06.565904 Couldn't find partition mmc 0
934 06:03:06.573917 Card did not respond to voltage select! : -110
935 06:03:06.579431 ** Bad device specification mmc 0 **
936 06:03:06.579836 Couldn't find partition mmc 0
937 06:03:06.584485 Error: could not access storage.
938 06:03:06.928249 Net: eth0: ethernet@ff3f0000
939 06:03:06.928676 starting USB...
940 06:03:07.179561 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 06:03:07.180113 Starting the controller
942 06:03:07.185040 USB XHCI 1.10
943 06:03:08.742691 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
944 06:03:08.750996 scanning usb for storage devices... 0 Storage Device(s) found
946 06:03:08.802148 Hit any key to stop autoboot: 1
947 06:03:08.802902 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
948 06:03:08.803262 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
949 06:03:08.803526 Setting prompt string to ['=>']
950 06:03:08.803784 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
951 06:03:08.808454 0
952 06:03:08.809050 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
953 06:03:08.809389 Sending with 10 millisecond of delay
955 06:03:09.945277 => setenv autoload no
956 06:03:09.956070 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
957 06:03:09.960981 setenv autoload no
958 06:03:09.961698 Sending with 10 millisecond of delay
960 06:03:11.760081 => setenv initrd_high 0xffffffff
961 06:03:11.770823 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
962 06:03:11.771638 setenv initrd_high 0xffffffff
963 06:03:11.772395 Sending with 10 millisecond of delay
965 06:03:13.388970 => setenv fdt_high 0xffffffff
966 06:03:13.399733 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
967 06:03:13.400597 setenv fdt_high 0xffffffff
968 06:03:13.401308 Sending with 10 millisecond of delay
970 06:03:13.693159 => dhcp
971 06:03:13.703896 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
972 06:03:13.704754 dhcp
973 06:03:13.705199 Speed: 1000, full duplex
974 06:03:13.705620 BOOTP broadcast 1
975 06:03:13.951292 BOOTP broadcast 2
976 06:03:13.973635 DHCP client bound to address 192.168.6.33 (271 ms)
977 06:03:13.974397 Sending with 10 millisecond of delay
979 06:03:15.651791 => setenv serverip 192.168.6.2
980 06:03:15.662633 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 06:03:15.663538 setenv serverip 192.168.6.2
982 06:03:15.664224 Sending with 10 millisecond of delay
984 06:03:19.390534 => tftpboot 0x01080000 681647/tftp-deploy-lotfnr53/kernel/uImage
985 06:03:19.401955 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
986 06:03:19.403529 tftpboot 0x01080000 681647/tftp-deploy-lotfnr53/kernel/uImage
987 06:03:19.404493 Speed: 1000, full duplex
988 06:03:19.405373 Using ethernet@ff3f0000 device
989 06:03:19.406273 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
990 06:03:19.410408 Filename '681647/tftp-deploy-lotfnr53/kernel/uImage'.
991 06:03:19.414303 Load address: 0x1080000
992 06:03:22.391298 Loading: *################################################## 37.2 MiB
993 06:03:22.391954 12.5 MiB/s
994 06:03:22.392450 done
995 06:03:22.395537 Bytes transferred = 39021120 (2536a40 hex)
996 06:03:22.396385 Sending with 10 millisecond of delay
998 06:03:27.084200 => tftpboot 0x08000000 681647/tftp-deploy-lotfnr53/ramdisk/ramdisk.cpio.gz.uboot
999 06:03:27.095040 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
1000 06:03:27.095956 tftpboot 0x08000000 681647/tftp-deploy-lotfnr53/ramdisk/ramdisk.cpio.gz.uboot
1001 06:03:27.096500 Speed: 1000, full duplex
1002 06:03:27.096969 Using ethernet@ff3f0000 device
1003 06:03:27.097948 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1004 06:03:27.109614 Filename '681647/tftp-deploy-lotfnr53/ramdisk/ramdisk.cpio.gz.uboot'.
1005 06:03:27.110181 Load address: 0x8000000
1006 06:03:34.258471 Loading: *##############T ################################### UDP wrong checksum 00000005 0000f7fc
1007 06:03:39.259866 T UDP wrong checksum 00000005 0000f7fc
1008 06:03:49.261870 T T UDP wrong checksum 00000005 0000f7fc
1009 06:03:55.678616 T UDP wrong checksum 000000ff 0000e31e
1010 06:03:55.703691 UDP wrong checksum 000000ff 00006811
1011 06:04:09.265863 T T T UDP wrong checksum 00000005 0000f7fc
1012 06:04:24.270063 T T
1013 06:04:24.270735 Retry count exceeded; starting again
1015 06:04:24.274314 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1018 06:04:24.278684 end: 2.4 uboot-commands (duration 00:01:48) [common]
1020 06:04:24.281550 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1022 06:04:24.283546 end: 2 uboot-action (duration 00:01:48) [common]
1024 06:04:24.286947 Cleaning after the job
1025 06:04:24.288165 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/ramdisk
1026 06:04:24.290744 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/kernel
1027 06:04:24.333079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/dtb
1028 06:04:24.333942 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/nfsrootfs
1029 06:04:24.512193 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681647/tftp-deploy-lotfnr53/modules
1030 06:04:24.535974 start: 4.1 power-off (timeout 00:00:30) [common]
1031 06:04:24.536673 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1032 06:04:24.570732 >> OK - accepted request
1033 06:04:24.572736 Returned 0 in 0 seconds
1034 06:04:24.674537 end: 4.1 power-off (duration 00:00:00) [common]
1036 06:04:24.675881 start: 4.2 read-feedback (timeout 00:10:00) [common]
1037 06:04:24.676856 Listened to connection for namespace 'common' for up to 1s
1038 06:04:25.677808 Finalising connection for namespace 'common'
1039 06:04:25.678457 Disconnecting from shell: Finalise
1040 06:04:25.678853 =>
1041 06:04:25.780111 end: 4.2 read-feedback (duration 00:00:01) [common]
1042 06:04:25.781214 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681647
1043 06:04:27.834128 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681647
1044 06:04:27.834749 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.