Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:52:33.714421 lava-dispatcher, installed at version: 2024.01
2 04:52:33.715778 start: 0 validate
3 04:52:33.716367 Start time: 2024-08-31 04:52:33.716335+00:00 (UTC)
4 04:52:33.716959 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:52:33.717578 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 04:52:33.758958 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:52:33.759507 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 04:52:33.793896 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:52:33.794529 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:52:33.830497 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:52:33.831009 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:52:33.863793 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:52:33.864325 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
14 04:52:33.910421 validate duration: 0.19
16 04:52:33.911932 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:52:33.912583 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:52:33.913192 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:52:33.914199 Not decompressing ramdisk as can be used compressed.
20 04:52:33.914954 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 04:52:33.915472 saving as /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/ramdisk/initrd.cpio.gz
22 04:52:33.916009 total size: 5628182 (5 MB)
23 04:52:33.955012 progress 0 % (0 MB)
24 04:52:33.962675 progress 5 % (0 MB)
25 04:52:33.970587 progress 10 % (0 MB)
26 04:52:33.977620 progress 15 % (0 MB)
27 04:52:33.985438 progress 20 % (1 MB)
28 04:52:33.990369 progress 25 % (1 MB)
29 04:52:33.994368 progress 30 % (1 MB)
30 04:52:33.998347 progress 35 % (1 MB)
31 04:52:34.001959 progress 40 % (2 MB)
32 04:52:34.005946 progress 45 % (2 MB)
33 04:52:34.009548 progress 50 % (2 MB)
34 04:52:34.013522 progress 55 % (2 MB)
35 04:52:34.017505 progress 60 % (3 MB)
36 04:52:34.021126 progress 65 % (3 MB)
37 04:52:34.025059 progress 70 % (3 MB)
38 04:52:34.028656 progress 75 % (4 MB)
39 04:52:34.032700 progress 80 % (4 MB)
40 04:52:34.036250 progress 85 % (4 MB)
41 04:52:34.040286 progress 90 % (4 MB)
42 04:52:34.044079 progress 95 % (5 MB)
43 04:52:34.047321 progress 100 % (5 MB)
44 04:52:34.048000 5 MB downloaded in 0.13 s (40.66 MB/s)
45 04:52:34.048574 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:52:34.049516 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:52:34.049831 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:52:34.050118 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:52:34.050601 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+debug/gcc-12/kernel/Image
51 04:52:34.050856 saving as /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/kernel/Image
52 04:52:34.051073 total size: 167969280 (160 MB)
53 04:52:34.051291 No compression specified
54 04:52:34.085931 progress 0 % (0 MB)
55 04:52:34.188181 progress 5 % (8 MB)
56 04:52:34.292238 progress 10 % (16 MB)
57 04:52:34.393588 progress 15 % (24 MB)
58 04:52:34.495037 progress 20 % (32 MB)
59 04:52:34.596200 progress 25 % (40 MB)
60 04:52:34.697465 progress 30 % (48 MB)
61 04:52:34.799580 progress 35 % (56 MB)
62 04:52:34.901198 progress 40 % (64 MB)
63 04:52:35.002485 progress 45 % (72 MB)
64 04:52:35.104227 progress 50 % (80 MB)
65 04:52:35.205659 progress 55 % (88 MB)
66 04:52:35.307066 progress 60 % (96 MB)
67 04:52:35.408506 progress 65 % (104 MB)
68 04:52:35.511306 progress 70 % (112 MB)
69 04:52:35.612359 progress 75 % (120 MB)
70 04:52:35.713398 progress 80 % (128 MB)
71 04:52:35.815037 progress 85 % (136 MB)
72 04:52:35.916266 progress 90 % (144 MB)
73 04:52:36.017037 progress 95 % (152 MB)
74 04:52:36.117844 progress 100 % (160 MB)
75 04:52:36.118398 160 MB downloaded in 2.07 s (77.49 MB/s)
76 04:52:36.118868 end: 1.2.1 http-download (duration 00:00:02) [common]
78 04:52:36.119687 end: 1.2 download-retry (duration 00:00:02) [common]
79 04:52:36.119961 start: 1.3 download-retry (timeout 00:09:58) [common]
80 04:52:36.120267 start: 1.3.1 http-download (timeout 00:09:58) [common]
81 04:52:36.120747 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 04:52:36.121013 saving as /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/dtb/meson-g12b-a311d-libretech-cc.dtb
83 04:52:36.121220 total size: 54667 (0 MB)
84 04:52:36.121430 No compression specified
85 04:52:36.160336 progress 59 % (0 MB)
86 04:52:36.161197 progress 100 % (0 MB)
87 04:52:36.161748 0 MB downloaded in 0.04 s (1.29 MB/s)
88 04:52:36.162206 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:52:36.163020 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:52:36.163277 start: 1.4 download-retry (timeout 00:09:58) [common]
92 04:52:36.163538 start: 1.4.1 http-download (timeout 00:09:58) [common]
93 04:52:36.164025 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 04:52:36.164275 saving as /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/nfsrootfs/full.rootfs.tar
95 04:52:36.164478 total size: 107552908 (102 MB)
96 04:52:36.164686 Using unxz to decompress xz
97 04:52:36.200135 progress 0 % (0 MB)
98 04:52:36.861083 progress 5 % (5 MB)
99 04:52:37.573240 progress 10 % (10 MB)
100 04:52:38.344903 progress 15 % (15 MB)
101 04:52:39.097671 progress 20 % (20 MB)
102 04:52:39.682718 progress 25 % (25 MB)
103 04:52:40.310739 progress 30 % (30 MB)
104 04:52:41.049070 progress 35 % (35 MB)
105 04:52:41.404058 progress 40 % (41 MB)
106 04:52:41.842753 progress 45 % (46 MB)
107 04:52:42.533845 progress 50 % (51 MB)
108 04:52:43.217875 progress 55 % (56 MB)
109 04:52:43.977531 progress 60 % (61 MB)
110 04:52:44.730245 progress 65 % (66 MB)
111 04:52:45.456628 progress 70 % (71 MB)
112 04:52:46.221274 progress 75 % (76 MB)
113 04:52:46.893077 progress 80 % (82 MB)
114 04:52:47.594765 progress 85 % (87 MB)
115 04:52:48.338097 progress 90 % (92 MB)
116 04:52:49.088440 progress 95 % (97 MB)
117 04:52:49.866495 progress 100 % (102 MB)
118 04:52:49.878698 102 MB downloaded in 13.71 s (7.48 MB/s)
119 04:52:49.879396 end: 1.4.1 http-download (duration 00:00:14) [common]
121 04:52:49.880379 end: 1.4 download-retry (duration 00:00:14) [common]
122 04:52:49.880694 start: 1.5 download-retry (timeout 00:09:44) [common]
123 04:52:49.880995 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 04:52:49.881643 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+debug/gcc-12/modules.tar.xz
125 04:52:49.881957 saving as /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/modules/modules.tar
126 04:52:49.882170 total size: 27403736 (26 MB)
127 04:52:49.882419 Using unxz to decompress xz
128 04:52:49.930249 progress 0 % (0 MB)
129 04:52:50.113545 progress 5 % (1 MB)
130 04:52:50.327255 progress 10 % (2 MB)
131 04:52:50.523463 progress 15 % (3 MB)
132 04:52:50.734129 progress 20 % (5 MB)
133 04:52:50.933762 progress 25 % (6 MB)
134 04:52:51.128943 progress 30 % (7 MB)
135 04:52:51.333148 progress 35 % (9 MB)
136 04:52:51.533490 progress 40 % (10 MB)
137 04:52:51.731477 progress 45 % (11 MB)
138 04:52:51.929837 progress 50 % (13 MB)
139 04:52:52.112239 progress 55 % (14 MB)
140 04:52:52.319775 progress 60 % (15 MB)
141 04:52:52.551946 progress 65 % (17 MB)
142 04:52:52.770623 progress 70 % (18 MB)
143 04:52:53.001802 progress 75 % (19 MB)
144 04:52:53.218619 progress 80 % (20 MB)
145 04:52:53.409023 progress 85 % (22 MB)
146 04:52:53.621423 progress 90 % (23 MB)
147 04:52:53.814719 progress 95 % (24 MB)
148 04:52:54.019888 progress 100 % (26 MB)
149 04:52:54.030765 26 MB downloaded in 4.15 s (6.30 MB/s)
150 04:52:54.032110 end: 1.5.1 http-download (duration 00:00:04) [common]
152 04:52:54.034822 end: 1.5 download-retry (duration 00:00:04) [common]
153 04:52:54.035670 start: 1.6 prepare-tftp-overlay (timeout 00:09:40) [common]
154 04:52:54.036507 start: 1.6.1 extract-nfsrootfs (timeout 00:09:40) [common]
155 04:53:03.798753 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/681347/extract-nfsrootfs-wzybmmop
156 04:53:03.799358 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 04:53:03.799647 start: 1.6.2 lava-overlay (timeout 00:09:30) [common]
158 04:53:03.800293 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y
159 04:53:03.800731 makedir: /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin
160 04:53:03.801064 makedir: /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/tests
161 04:53:03.801383 makedir: /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/results
162 04:53:03.801723 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-add-keys
163 04:53:03.802272 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-add-sources
164 04:53:03.802772 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-background-process-start
165 04:53:03.803306 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-background-process-stop
166 04:53:03.803854 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-common-functions
167 04:53:03.804373 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-echo-ipv4
168 04:53:03.804854 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-install-packages
169 04:53:03.805346 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-installed-packages
170 04:53:03.805828 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-os-build
171 04:53:03.806297 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-probe-channel
172 04:53:03.806767 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-probe-ip
173 04:53:03.807255 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-target-ip
174 04:53:03.807753 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-target-mac
175 04:53:03.808272 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-target-storage
176 04:53:03.808764 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-test-case
177 04:53:03.809266 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-test-event
178 04:53:03.809744 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-test-feedback
179 04:53:03.810210 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-test-raise
180 04:53:03.810675 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-test-reference
181 04:53:03.811163 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-test-runner
182 04:53:03.811660 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-test-set
183 04:53:03.812165 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-test-shell
184 04:53:03.812649 Updating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-install-packages (oe)
185 04:53:03.813172 Updating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/bin/lava-installed-packages (oe)
186 04:53:03.813610 Creating /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/environment
187 04:53:03.813972 LAVA metadata
188 04:53:03.814234 - LAVA_JOB_ID=681347
189 04:53:03.814453 - LAVA_DISPATCHER_IP=192.168.6.2
190 04:53:03.814806 start: 1.6.2.1 ssh-authorize (timeout 00:09:30) [common]
191 04:53:03.815806 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 04:53:03.816147 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:30) [common]
193 04:53:03.816362 skipped lava-vland-overlay
194 04:53:03.816604 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 04:53:03.816861 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:30) [common]
196 04:53:03.817083 skipped lava-multinode-overlay
197 04:53:03.817327 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 04:53:03.817581 start: 1.6.2.4 test-definition (timeout 00:09:30) [common]
199 04:53:03.817833 Loading test definitions
200 04:53:03.818112 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:30) [common]
201 04:53:03.818333 Using /lava-681347 at stage 0
202 04:53:03.819500 uuid=681347_1.6.2.4.1 testdef=None
203 04:53:03.819811 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 04:53:03.820100 start: 1.6.2.4.2 test-overlay (timeout 00:09:30) [common]
205 04:53:03.821878 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 04:53:03.822668 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:30) [common]
208 04:53:03.824911 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 04:53:03.825746 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:30) [common]
211 04:53:03.827888 runner path: /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/0/tests/0_dmesg test_uuid 681347_1.6.2.4.1
212 04:53:03.828487 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 04:53:03.829250 Creating lava-test-runner.conf files
215 04:53:03.829452 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681347/lava-overlay-qryvri0y/lava-681347/0 for stage 0
216 04:53:03.829778 - 0_dmesg
217 04:53:03.830121 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 04:53:03.830399 start: 1.6.2.5 compress-overlay (timeout 00:09:30) [common]
219 04:53:03.851574 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 04:53:03.851933 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:30) [common]
221 04:53:03.852223 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 04:53:03.852492 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 04:53:03.852759 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:30) [common]
224 04:53:04.461199 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 04:53:04.461677 start: 1.6.4 extract-modules (timeout 00:09:29) [common]
226 04:53:04.461953 extracting modules file /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681347/extract-nfsrootfs-wzybmmop
227 04:53:06.108608 extracting modules file /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681347/extract-overlay-ramdisk-o2vd0zl3/ramdisk
228 04:53:07.791334 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 04:53:07.791793 start: 1.6.5 apply-overlay-tftp (timeout 00:09:26) [common]
230 04:53:07.792105 [common] Applying overlay to NFS
231 04:53:07.792323 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681347/compress-overlay-kk2xg_8x/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681347/extract-nfsrootfs-wzybmmop
232 04:53:07.821261 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 04:53:07.821648 start: 1.6.6 prepare-kernel (timeout 00:09:26) [common]
234 04:53:07.821972 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:26) [common]
235 04:53:07.822212 Converting downloaded kernel to a uImage
236 04:53:07.822521 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/kernel/Image /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/kernel/uImage
237 04:53:09.496957 output: Image Name:
238 04:53:09.497398 output: Created: Sat Aug 31 04:53:07 2024
239 04:53:09.497621 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 04:53:09.497833 output: Data Size: 167969280 Bytes = 164032.50 KiB = 160.19 MiB
241 04:53:09.498040 output: Load Address: 01080000
242 04:53:09.498244 output: Entry Point: 01080000
243 04:53:09.498445 output:
244 04:53:09.498783 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
245 04:53:09.499056 end: 1.6.6 prepare-kernel (duration 00:00:02) [common]
246 04:53:09.499326 start: 1.6.7 configure-preseed-file (timeout 00:09:24) [common]
247 04:53:09.499588 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 04:53:09.499857 start: 1.6.8 compress-ramdisk (timeout 00:09:24) [common]
249 04:53:09.500196 Building ramdisk /var/lib/lava/dispatcher/tmp/681347/extract-overlay-ramdisk-o2vd0zl3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681347/extract-overlay-ramdisk-o2vd0zl3/ramdisk
250 04:53:14.733257 >> 421456 blocks
251 04:53:32.116266 Adding RAMdisk u-boot header.
252 04:53:32.116950 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681347/extract-overlay-ramdisk-o2vd0zl3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681347/extract-overlay-ramdisk-o2vd0zl3/ramdisk.cpio.gz.uboot
253 04:53:32.628843 output: Image Name:
254 04:53:32.629278 output: Created: Sat Aug 31 04:53:32 2024
255 04:53:32.629533 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 04:53:32.629780 output: Data Size: 50545161 Bytes = 49360.51 KiB = 48.20 MiB
257 04:53:32.630025 output: Load Address: 00000000
258 04:53:32.630262 output: Entry Point: 00000000
259 04:53:32.630491 output:
260 04:53:32.631324 rename /var/lib/lava/dispatcher/tmp/681347/extract-overlay-ramdisk-o2vd0zl3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/ramdisk/ramdisk.cpio.gz.uboot
261 04:53:32.631789 end: 1.6.8 compress-ramdisk (duration 00:00:23) [common]
262 04:53:32.632235 end: 1.6 prepare-tftp-overlay (duration 00:00:39) [common]
263 04:53:32.632850 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:01) [common]
264 04:53:32.633386 No LXC device requested
265 04:53:32.633958 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 04:53:32.634527 start: 1.8 deploy-device-env (timeout 00:09:01) [common]
267 04:53:32.635076 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 04:53:32.635530 Checking files for TFTP limit of 4294967296 bytes.
269 04:53:32.638478 end: 1 tftp-deploy (duration 00:00:59) [common]
270 04:53:32.639105 start: 2 uboot-action (timeout 00:05:00) [common]
271 04:53:32.639675 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 04:53:32.640247 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 04:53:32.640803 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 04:53:32.641374 Using kernel file from prepare-kernel: 681347/tftp-deploy-1r6yf6lf/kernel/uImage
275 04:53:32.642054 substitutions:
276 04:53:32.642498 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 04:53:32.642944 - {DTB_ADDR}: 0x01070000
278 04:53:32.643382 - {DTB}: 681347/tftp-deploy-1r6yf6lf/dtb/meson-g12b-a311d-libretech-cc.dtb
279 04:53:32.643825 - {INITRD}: 681347/tftp-deploy-1r6yf6lf/ramdisk/ramdisk.cpio.gz.uboot
280 04:53:32.644300 - {KERNEL_ADDR}: 0x01080000
281 04:53:32.644738 - {KERNEL}: 681347/tftp-deploy-1r6yf6lf/kernel/uImage
282 04:53:32.645172 - {LAVA_MAC}: None
283 04:53:32.645644 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/681347/extract-nfsrootfs-wzybmmop
284 04:53:32.646085 - {NFS_SERVER_IP}: 192.168.6.2
285 04:53:32.646515 - {PRESEED_CONFIG}: None
286 04:53:32.646943 - {PRESEED_LOCAL}: None
287 04:53:32.647371 - {RAMDISK_ADDR}: 0x08000000
288 04:53:32.647797 - {RAMDISK}: 681347/tftp-deploy-1r6yf6lf/ramdisk/ramdisk.cpio.gz.uboot
289 04:53:32.648253 - {ROOT_PART}: None
290 04:53:32.648679 - {ROOT}: None
291 04:53:32.649105 - {SERVER_IP}: 192.168.6.2
292 04:53:32.649531 - {TEE_ADDR}: 0x83000000
293 04:53:32.649958 - {TEE}: None
294 04:53:32.650385 Parsed boot commands:
295 04:53:32.650799 - setenv autoload no
296 04:53:32.651225 - setenv initrd_high 0xffffffff
297 04:53:32.651648 - setenv fdt_high 0xffffffff
298 04:53:32.652100 - dhcp
299 04:53:32.652530 - setenv serverip 192.168.6.2
300 04:53:32.652954 - tftpboot 0x01080000 681347/tftp-deploy-1r6yf6lf/kernel/uImage
301 04:53:32.653378 - tftpboot 0x08000000 681347/tftp-deploy-1r6yf6lf/ramdisk/ramdisk.cpio.gz.uboot
302 04:53:32.653802 - tftpboot 0x01070000 681347/tftp-deploy-1r6yf6lf/dtb/meson-g12b-a311d-libretech-cc.dtb
303 04:53:32.654227 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/681347/extract-nfsrootfs-wzybmmop,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 04:53:32.654662 - bootm 0x01080000 0x08000000 0x01070000
305 04:53:32.655203 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 04:53:32.656862 start: 2.3 connect-device (timeout 00:05:00) [common]
308 04:53:32.657317 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 04:53:32.672278 Setting prompt string to ['lava-test: # ']
310 04:53:32.673899 end: 2.3 connect-device (duration 00:00:00) [common]
311 04:53:32.674554 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 04:53:32.675234 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 04:53:32.675845 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 04:53:32.676517 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 04:53:32.709188 >> OK - accepted request
316 04:53:32.711258 Returned 0 in 0 seconds
317 04:53:32.812371 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 04:53:32.814073 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 04:53:32.814704 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 04:53:32.815266 Setting prompt string to ['Hit any key to stop autoboot']
322 04:53:32.815775 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 04:53:32.817508 Trying 192.168.56.21...
324 04:53:32.818025 Connected to conserv1.
325 04:53:32.818496 Escape character is '^]'.
326 04:53:32.818956
327 04:53:32.819419 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 04:53:32.819884
329 04:53:44.100441 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 04:53:44.101101 bl2_stage_init 0x81
331 04:53:44.106226 hw id: 0x0000 - pwm id 0x01
332 04:53:44.106708 bl2_stage_init 0xc1
333 04:53:44.107162 bl2_stage_init 0x02
334 04:53:44.107599
335 04:53:44.111572 L0:00000000
336 04:53:44.112074 L1:20000703
337 04:53:44.112525 L2:00008067
338 04:53:44.112955 L3:14000000
339 04:53:44.113383 B2:00402000
340 04:53:44.117176 B1:e0f83180
341 04:53:44.117659
342 04:53:44.118095 TE: 58150
343 04:53:44.118526
344 04:53:44.122927 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 04:53:44.123395
346 04:53:44.123830 Board ID = 1
347 04:53:44.128496 Set A53 clk to 24M
348 04:53:44.128964 Set A73 clk to 24M
349 04:53:44.129395 Set clk81 to 24M
350 04:53:44.134287 A53 clk: 1200 MHz
351 04:53:44.134743 A73 clk: 1200 MHz
352 04:53:44.135174 CLK81: 166.6M
353 04:53:44.135599 smccc: 00012aab
354 04:53:44.139489 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 04:53:44.145131 board id: 1
356 04:53:44.149936 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 04:53:44.161586 fw parse done
358 04:53:44.167612 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 04:53:44.210209 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 04:53:44.221056 PIEI prepare done
361 04:53:44.221527 fastboot data load
362 04:53:44.221963 fastboot data verify
363 04:53:44.226739 verify result: 266
364 04:53:44.232327 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 04:53:44.232788 LPDDR4 probe
366 04:53:44.233212 ddr clk to 1584MHz
367 04:53:44.240387 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 04:53:44.276772
369 04:53:44.277249 dmc_version 0001
370 04:53:44.284250 Check phy result
371 04:53:44.290128 INFO : End of CA training
372 04:53:44.290585 INFO : End of initialization
373 04:53:44.295728 INFO : Training has run successfully!
374 04:53:44.296230 Check phy result
375 04:53:44.301341 INFO : End of initialization
376 04:53:44.301798 INFO : End of read enable training
377 04:53:44.304624 INFO : End of fine write leveling
378 04:53:44.310179 INFO : End of Write leveling coarse delay
379 04:53:44.315721 INFO : Training has run successfully!
380 04:53:44.316266 Check phy result
381 04:53:44.316731 INFO : End of initialization
382 04:53:44.321283 INFO : End of read dq deskew training
383 04:53:44.326899 INFO : End of MPR read delay center optimization
384 04:53:44.327380 INFO : End of write delay center optimization
385 04:53:44.332539 INFO : End of read delay center optimization
386 04:53:44.338077 INFO : End of max read latency training
387 04:53:44.338575 INFO : Training has run successfully!
388 04:53:44.343670 1D training succeed
389 04:53:44.349691 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 04:53:44.396970 Check phy result
391 04:53:44.397485 INFO : End of initialization
392 04:53:44.418854 INFO : End of 2D read delay Voltage center optimization
393 04:53:44.439172 INFO : End of 2D read delay Voltage center optimization
394 04:53:44.491208 INFO : End of 2D write delay Voltage center optimization
395 04:53:44.542206 INFO : End of 2D write delay Voltage center optimization
396 04:53:44.547089 INFO : Training has run successfully!
397 04:53:44.547577
398 04:53:44.548066 channel==0
399 04:53:44.552646 RxClkDly_Margin_A0==88 ps 9
400 04:53:44.553125 TxDqDly_Margin_A0==98 ps 10
401 04:53:44.558306 RxClkDly_Margin_A1==78 ps 8
402 04:53:44.558784 TxDqDly_Margin_A1==88 ps 9
403 04:53:44.559240 TrainedVREFDQ_A0==74
404 04:53:44.563875 TrainedVREFDQ_A1==74
405 04:53:44.564379 VrefDac_Margin_A0==25
406 04:53:44.564833 DeviceVref_Margin_A0==40
407 04:53:44.569594 VrefDac_Margin_A1==26
408 04:53:44.570079 DeviceVref_Margin_A1==40
409 04:53:44.570527
410 04:53:44.570970
411 04:53:44.571414 channel==1
412 04:53:44.575025 RxClkDly_Margin_A0==98 ps 10
413 04:53:44.575495 TxDqDly_Margin_A0==88 ps 9
414 04:53:44.580664 RxClkDly_Margin_A1==98 ps 10
415 04:53:44.581166 TxDqDly_Margin_A1==88 ps 9
416 04:53:44.586331 TrainedVREFDQ_A0==77
417 04:53:44.586803 TrainedVREFDQ_A1==77
418 04:53:44.587255 VrefDac_Margin_A0==23
419 04:53:44.591882 DeviceVref_Margin_A0==37
420 04:53:44.592395 VrefDac_Margin_A1==22
421 04:53:44.597710 DeviceVref_Margin_A1==37
422 04:53:44.598195
423 04:53:44.598643 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 04:53:44.599083
425 04:53:44.631168 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
426 04:53:44.631854 2D training succeed
427 04:53:44.636720 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 04:53:44.642401 auto size-- 65535DDR cs0 size: 2048MB
429 04:53:44.642882 DDR cs1 size: 2048MB
430 04:53:44.647934 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 04:53:44.648446 cs0 DataBus test pass
432 04:53:44.653639 cs1 DataBus test pass
433 04:53:44.654110 cs0 AddrBus test pass
434 04:53:44.654557 cs1 AddrBus test pass
435 04:53:44.654993
436 04:53:44.659111 100bdlr_step_size ps== 420
437 04:53:44.659602 result report
438 04:53:44.664711 boot times 0Enable ddr reg access
439 04:53:44.669974 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 04:53:44.683496 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 04:53:45.257026 0.0;M3 CHK:0;cm4_sp_mode 0
442 04:53:45.257391 MVN_1=0x00000000
443 04:53:45.262715 MVN_2=0x00000000
444 04:53:45.268343 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 04:53:45.268817 OPS=0x10
446 04:53:45.269269 ring efuse init
447 04:53:45.269712 chipver efuse init
448 04:53:45.273963 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 04:53:45.279567 [0.018961 Inits done]
450 04:53:45.280085 secure task start!
451 04:53:45.280542 high task start!
452 04:53:45.284164 low task start!
453 04:53:45.284630 run into bl31
454 04:53:45.290791 NOTICE: BL31: v1.3(release):4fc40b1
455 04:53:45.297671 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 04:53:45.298147 NOTICE: BL31: G12A normal boot!
457 04:53:45.324004 NOTICE: BL31: BL33 decompress pass
458 04:53:45.329786 ERROR: Error initializing runtime service opteed_fast
459 04:53:46.562548
460 04:53:46.563169
461 04:53:46.570935 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 04:53:46.571431
463 04:53:46.571887 Model: Libre Computer AML-A311D-CC Alta
464 04:53:46.779299 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 04:53:46.802766 DRAM: 2 GiB (effective 3.8 GiB)
466 04:53:46.945717 Core: 408 devices, 31 uclasses, devicetree: separate
467 04:53:46.951584 WDT: Not starting watchdog@f0d0
468 04:53:46.983956 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
469 04:53:46.996193 Loading Environment from FAT... Card did not respond to voltage select! : -110
470 04:53:47.001131 ** Bad device specification mmc 0 **
471 04:53:47.011465 Card did not respond to voltage select! : -110
472 04:53:47.019140 ** Bad device specification mmc 0 **
473 04:53:47.019614 Couldn't find partition mmc 0
474 04:53:47.027450 Card did not respond to voltage select! : -110
475 04:53:47.032985 ** Bad device specification mmc 0 **
476 04:53:47.033461 Couldn't find partition mmc 0
477 04:53:47.038035 Error: could not access storage.
478 04:53:48.301120 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
479 04:53:48.301766 bl2_stage_init 0x01
480 04:53:48.302236 bl2_stage_init 0x81
481 04:53:48.306665 hw id: 0x0000 - pwm id 0x01
482 04:53:48.307143 bl2_stage_init 0xc1
483 04:53:48.307597 bl2_stage_init 0x02
484 04:53:48.308082
485 04:53:48.312255 L0:00000000
486 04:53:48.312741 L1:20000703
487 04:53:48.313195 L2:00008067
488 04:53:48.313646 L3:14000000
489 04:53:48.317879 B2:00402000
490 04:53:48.318367 B1:e0f83180
491 04:53:48.318813
492 04:53:48.319257 TE: 58124
493 04:53:48.319700
494 04:53:48.323459 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 04:53:48.323934
496 04:53:48.324420 Board ID = 1
497 04:53:48.329071 Set A53 clk to 24M
498 04:53:48.329539 Set A73 clk to 24M
499 04:53:48.329986 Set clk81 to 24M
500 04:53:48.334649 A53 clk: 1200 MHz
501 04:53:48.335117 A73 clk: 1200 MHz
502 04:53:48.335560 CLK81: 166.6M
503 04:53:48.336027 smccc: 00012a92
504 04:53:48.340239 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 04:53:48.345882 board id: 1
506 04:53:48.351736 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 04:53:48.362302 fw parse done
508 04:53:48.368243 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 04:53:48.410890 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 04:53:48.421891 PIEI prepare done
511 04:53:48.422373 fastboot data load
512 04:53:48.422829 fastboot data verify
513 04:53:48.427535 verify result: 266
514 04:53:48.433164 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 04:53:48.433636 LPDDR4 probe
516 04:53:48.434083 ddr clk to 1584MHz
517 04:53:48.441247 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 04:53:48.478254
519 04:53:48.478728 dmc_version 0001
520 04:53:48.484928 Check phy result
521 04:53:48.490787 INFO : End of CA training
522 04:53:48.491252 INFO : End of initialization
523 04:53:48.496402 INFO : Training has run successfully!
524 04:53:48.496869 Check phy result
525 04:53:48.502077 INFO : End of initialization
526 04:53:48.502606 INFO : End of read enable training
527 04:53:48.507596 INFO : End of fine write leveling
528 04:53:48.513207 INFO : End of Write leveling coarse delay
529 04:53:48.513681 INFO : Training has run successfully!
530 04:53:48.514128 Check phy result
531 04:53:48.518799 INFO : End of initialization
532 04:53:48.519281 INFO : End of read dq deskew training
533 04:53:48.524409 INFO : End of MPR read delay center optimization
534 04:53:48.530038 INFO : End of write delay center optimization
535 04:53:48.535590 INFO : End of read delay center optimization
536 04:53:48.536095 INFO : End of max read latency training
537 04:53:48.541207 INFO : Training has run successfully!
538 04:53:48.541679 1D training succeed
539 04:53:48.550382 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 04:53:48.598059 Check phy result
541 04:53:48.598529 INFO : End of initialization
542 04:53:48.619693 INFO : End of 2D read delay Voltage center optimization
543 04:53:48.639831 INFO : End of 2D read delay Voltage center optimization
544 04:53:48.691574 INFO : End of 2D write delay Voltage center optimization
545 04:53:48.740829 INFO : End of 2D write delay Voltage center optimization
546 04:53:48.746405 INFO : Training has run successfully!
547 04:53:48.746878
548 04:53:48.747328 channel==0
549 04:53:48.752077 RxClkDly_Margin_A0==88 ps 9
550 04:53:48.752561 TxDqDly_Margin_A0==98 ps 10
551 04:53:48.757595 RxClkDly_Margin_A1==88 ps 9
552 04:53:48.758067 TxDqDly_Margin_A1==98 ps 10
553 04:53:48.758518 TrainedVREFDQ_A0==74
554 04:53:48.763200 TrainedVREFDQ_A1==74
555 04:53:48.763677 VrefDac_Margin_A0==25
556 04:53:48.764161 DeviceVref_Margin_A0==40
557 04:53:48.768832 VrefDac_Margin_A1==25
558 04:53:48.769297 DeviceVref_Margin_A1==40
559 04:53:48.769741
560 04:53:48.770183
561 04:53:48.774410 channel==1
562 04:53:48.774874 RxClkDly_Margin_A0==98 ps 10
563 04:53:48.775317 TxDqDly_Margin_A0==98 ps 10
564 04:53:48.780099 RxClkDly_Margin_A1==98 ps 10
565 04:53:48.780570 TxDqDly_Margin_A1==88 ps 9
566 04:53:48.785598 TrainedVREFDQ_A0==77
567 04:53:48.786065 TrainedVREFDQ_A1==77
568 04:53:48.786513 VrefDac_Margin_A0==22
569 04:53:48.791201 DeviceVref_Margin_A0==37
570 04:53:48.791662 VrefDac_Margin_A1==23
571 04:53:48.796830 DeviceVref_Margin_A1==37
572 04:53:48.797297
573 04:53:48.797749 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 04:53:48.802405
575 04:53:48.830410 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
576 04:53:48.830931 2D training succeed
577 04:53:48.836089 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 04:53:48.841603 auto size-- 65535DDR cs0 size: 2048MB
579 04:53:48.842081 DDR cs1 size: 2048MB
580 04:53:48.847202 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 04:53:48.847674 cs0 DataBus test pass
582 04:53:48.852836 cs1 DataBus test pass
583 04:53:48.853306 cs0 AddrBus test pass
584 04:53:48.853746 cs1 AddrBus test pass
585 04:53:48.854181
586 04:53:48.858396 100bdlr_step_size ps== 420
587 04:53:48.858878 result report
588 04:53:48.864100 boot times 0Enable ddr reg access
589 04:53:48.869427 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 04:53:48.882914 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 04:53:49.455064 0.0;M3 CHK:0;cm4_sp_mode 0
592 04:53:49.455619 MVN_1=0x00000000
593 04:53:49.460756 MVN_2=0x00000000
594 04:53:49.466420 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 04:53:49.466926 OPS=0x10
596 04:53:49.467417 ring efuse init
597 04:53:49.467889 chipver efuse init
598 04:53:49.472088 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 04:53:49.477544 [0.018961 Inits done]
600 04:53:49.478015 secure task start!
601 04:53:49.478445 high task start!
602 04:53:49.482321 low task start!
603 04:53:49.482780 run into bl31
604 04:53:49.488767 NOTICE: BL31: v1.3(release):4fc40b1
605 04:53:49.496756 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 04:53:49.497222 NOTICE: BL31: G12A normal boot!
607 04:53:49.521908 NOTICE: BL31: BL33 decompress pass
608 04:53:49.527759 ERROR: Error initializing runtime service opteed_fast
609 04:53:50.760641
610 04:53:50.761229
611 04:53:50.768958 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 04:53:50.769447
613 04:53:50.769903 Model: Libre Computer AML-A311D-CC Alta
614 04:53:50.977383 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 04:53:51.000873 DRAM: 2 GiB (effective 3.8 GiB)
616 04:53:51.143756 Core: 408 devices, 31 uclasses, devicetree: separate
617 04:53:51.149699 WDT: Not starting watchdog@f0d0
618 04:53:51.181881 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 04:53:51.194420 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 04:53:51.199369 ** Bad device specification mmc 0 **
621 04:53:51.209576 Card did not respond to voltage select! : -110
622 04:53:51.217322 ** Bad device specification mmc 0 **
623 04:53:51.217795 Couldn't find partition mmc 0
624 04:53:51.225574 Card did not respond to voltage select! : -110
625 04:53:51.231163 ** Bad device specification mmc 0 **
626 04:53:51.231633 Couldn't find partition mmc 0
627 04:53:51.236173 Error: could not access storage.
628 04:53:51.578823 Net: eth0: ethernet@ff3f0000
629 04:53:51.579434 starting USB...
630 04:53:51.830550 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 04:53:51.831128 Starting the controller
632 04:53:51.837719 USB XHCI 1.10
633 04:53:53.549685 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 04:53:53.550354 bl2_stage_init 0x01
635 04:53:53.550835 bl2_stage_init 0x81
636 04:53:53.555312 hw id: 0x0000 - pwm id 0x01
637 04:53:53.555848 bl2_stage_init 0xc1
638 04:53:53.556370 bl2_stage_init 0x02
639 04:53:53.556831
640 04:53:53.560898 L0:00000000
641 04:53:53.561429 L1:20000703
642 04:53:53.561888 L2:00008067
643 04:53:53.562339 L3:14000000
644 04:53:53.566528 B2:00402000
645 04:53:53.567055 B1:e0f83180
646 04:53:53.567518
647 04:53:53.567969 TE: 58159
648 04:53:53.568457
649 04:53:53.572058 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 04:53:53.572591
651 04:53:53.573056 Board ID = 1
652 04:53:53.577605 Set A53 clk to 24M
653 04:53:53.578125 Set A73 clk to 24M
654 04:53:53.578581 Set clk81 to 24M
655 04:53:53.583383 A53 clk: 1200 MHz
656 04:53:53.583908 A73 clk: 1200 MHz
657 04:53:53.584408 CLK81: 166.6M
658 04:53:53.584856 smccc: 00012ab5
659 04:53:53.588826 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 04:53:53.594427 board id: 1
661 04:53:53.600459 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 04:53:53.611021 fw parse done
663 04:53:53.617151 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 04:53:53.659432 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 04:53:53.670366 PIEI prepare done
666 04:53:53.670888 fastboot data load
667 04:53:53.671353 fastboot data verify
668 04:53:53.676065 verify result: 266
669 04:53:53.681728 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 04:53:53.682255 LPDDR4 probe
671 04:53:53.682708 ddr clk to 1584MHz
672 04:53:53.689574 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 04:53:53.726853
674 04:53:53.727377 dmc_version 0001
675 04:53:53.733580 Check phy result
676 04:53:53.739441 INFO : End of CA training
677 04:53:53.739958 INFO : End of initialization
678 04:53:53.745016 INFO : Training has run successfully!
679 04:53:53.745550 Check phy result
680 04:53:53.750636 INFO : End of initialization
681 04:53:53.751156 INFO : End of read enable training
682 04:53:53.754018 INFO : End of fine write leveling
683 04:53:53.759537 INFO : End of Write leveling coarse delay
684 04:53:53.765129 INFO : Training has run successfully!
685 04:53:53.765649 Check phy result
686 04:53:53.766107 INFO : End of initialization
687 04:53:53.770775 INFO : End of read dq deskew training
688 04:53:53.776355 INFO : End of MPR read delay center optimization
689 04:53:53.776885 INFO : End of write delay center optimization
690 04:53:53.781977 INFO : End of read delay center optimization
691 04:53:53.787568 INFO : End of max read latency training
692 04:53:53.788132 INFO : Training has run successfully!
693 04:53:53.793159 1D training succeed
694 04:53:53.799089 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 04:53:53.846607 Check phy result
696 04:53:53.847132 INFO : End of initialization
697 04:53:53.869161 INFO : End of 2D read delay Voltage center optimization
698 04:53:53.889416 INFO : End of 2D read delay Voltage center optimization
699 04:53:53.941414 INFO : End of 2D write delay Voltage center optimization
700 04:53:53.990759 INFO : End of 2D write delay Voltage center optimization
701 04:53:53.996391 INFO : Training has run successfully!
702 04:53:53.996908
703 04:53:53.997368 channel==0
704 04:53:54.002040 RxClkDly_Margin_A0==78 ps 8
705 04:53:54.002573 TxDqDly_Margin_A0==98 ps 10
706 04:53:54.007592 RxClkDly_Margin_A1==88 ps 9
707 04:53:54.008152 TxDqDly_Margin_A1==88 ps 9
708 04:53:54.008621 TrainedVREFDQ_A0==74
709 04:53:54.013184 TrainedVREFDQ_A1==74
710 04:53:54.013714 VrefDac_Margin_A0==25
711 04:53:54.014168 DeviceVref_Margin_A0==40
712 04:53:54.018768 VrefDac_Margin_A1==24
713 04:53:54.019283 DeviceVref_Margin_A1==40
714 04:53:54.019741
715 04:53:54.020228
716 04:53:54.020679 channel==1
717 04:53:54.024385 RxClkDly_Margin_A0==98 ps 10
718 04:53:54.024900 TxDqDly_Margin_A0==88 ps 9
719 04:53:54.030044 RxClkDly_Margin_A1==98 ps 10
720 04:53:54.030563 TxDqDly_Margin_A1==88 ps 9
721 04:53:54.035577 TrainedVREFDQ_A0==76
722 04:53:54.036125 TrainedVREFDQ_A1==77
723 04:53:54.036587 VrefDac_Margin_A0==22
724 04:53:54.041186 DeviceVref_Margin_A0==38
725 04:53:54.041705 VrefDac_Margin_A1==24
726 04:53:54.046779 DeviceVref_Margin_A1==37
727 04:53:54.047296
728 04:53:54.047753 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 04:53:54.048240
730 04:53:54.080319 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
731 04:53:54.080871 2D training succeed
732 04:53:54.086046 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 04:53:54.091597 auto size-- 65535DDR cs0 size: 2048MB
734 04:53:54.092138 DDR cs1 size: 2048MB
735 04:53:54.097235 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 04:53:54.097724 cs0 DataBus test pass
737 04:53:54.102815 cs1 DataBus test pass
738 04:53:54.103345 cs0 AddrBus test pass
739 04:53:54.103823 cs1 AddrBus test pass
740 04:53:54.104301
741 04:53:54.108341 100bdlr_step_size ps== 420
742 04:53:54.108872 result report
743 04:53:54.114048 boot times 0Enable ddr reg access
744 04:53:54.119230 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 04:53:54.132712 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 04:53:54.706303 0.0;M3 CHK:0;cm4_sp_mode 0
747 04:53:54.706841 MVN_1=0x00000000
748 04:53:54.711858 MVN_2=0x00000000
749 04:53:54.717621 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 04:53:54.718175 OPS=0x10
751 04:53:54.718619 ring efuse init
752 04:53:54.719046 chipver efuse init
753 04:53:54.723206 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 04:53:54.728774 [0.018961 Inits done]
755 04:53:54.729286 secure task start!
756 04:53:54.729723 high task start!
757 04:53:54.733383 low task start!
758 04:53:54.733886 run into bl31
759 04:53:54.740045 NOTICE: BL31: v1.3(release):4fc40b1
760 04:53:54.747851 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 04:53:54.748394 NOTICE: BL31: G12A normal boot!
762 04:53:54.773249 NOTICE: BL31: BL33 decompress pass
763 04:53:54.778972 ERROR: Error initializing runtime service opteed_fast
764 04:53:56.011691
765 04:53:56.012052
766 04:53:56.020182 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 04:53:56.021409
768 04:53:56.021934 Model: Libre Computer AML-A311D-CC Alta
769 04:53:56.228486 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 04:53:56.251951 DRAM: 2 GiB (effective 3.8 GiB)
771 04:53:56.395026 Core: 408 devices, 31 uclasses, devicetree: separate
772 04:53:56.400951 WDT: Not starting watchdog@f0d0
773 04:53:56.433274 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 04:53:56.445603 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 04:53:56.450624 ** Bad device specification mmc 0 **
776 04:53:56.461021 Card did not respond to voltage select! : -110
777 04:53:56.468617 ** Bad device specification mmc 0 **
778 04:53:56.469143 Couldn't find partition mmc 0
779 04:53:56.477032 Card did not respond to voltage select! : -110
780 04:53:56.482476 ** Bad device specification mmc 0 **
781 04:53:56.482994 Couldn't find partition mmc 0
782 04:53:56.487556 Error: could not access storage.
783 04:53:56.829948 Net: eth0: ethernet@ff3f0000
784 04:53:56.830505 starting USB...
785 04:53:57.081629 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 04:53:57.081928 Starting the controller
787 04:53:57.088646 USB XHCI 1.10
788 04:53:59.249851 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 04:53:59.250450 bl2_stage_init 0x01
790 04:53:59.250927 bl2_stage_init 0x81
791 04:53:59.255378 hw id: 0x0000 - pwm id 0x01
792 04:53:59.255906 bl2_stage_init 0xc1
793 04:53:59.256420 bl2_stage_init 0x02
794 04:53:59.256875
795 04:53:59.260972 L0:00000000
796 04:53:59.261499 L1:20000703
797 04:53:59.261961 L2:00008067
798 04:53:59.262412 L3:14000000
799 04:53:59.263860 B2:00402000
800 04:53:59.264408 B1:e0f83180
801 04:53:59.264866
802 04:53:59.265318 TE: 58159
803 04:53:59.265770
804 04:53:59.275022 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 04:53:59.275553
806 04:53:59.276046 Board ID = 1
807 04:53:59.276502 Set A53 clk to 24M
808 04:53:59.276945 Set A73 clk to 24M
809 04:53:59.280725 Set clk81 to 24M
810 04:53:59.281247 A53 clk: 1200 MHz
811 04:53:59.281707 A73 clk: 1200 MHz
812 04:53:59.286154 CLK81: 166.6M
813 04:53:59.286668 smccc: 00012ab5
814 04:53:59.291815 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 04:53:59.292365 board id: 1
816 04:53:59.300587 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 04:53:59.310989 fw parse done
818 04:53:59.316960 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 04:53:59.359579 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 04:53:59.370534 PIEI prepare done
821 04:53:59.371052 fastboot data load
822 04:53:59.371513 fastboot data verify
823 04:53:59.376227 verify result: 266
824 04:53:59.381843 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 04:53:59.382367 LPDDR4 probe
826 04:53:59.382830 ddr clk to 1584MHz
827 04:53:59.389902 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 04:53:59.427026
829 04:53:59.427552 dmc_version 0001
830 04:53:59.433725 Check phy result
831 04:53:59.439591 INFO : End of CA training
832 04:53:59.440136 INFO : End of initialization
833 04:53:59.445197 INFO : Training has run successfully!
834 04:53:59.445720 Check phy result
835 04:53:59.450847 INFO : End of initialization
836 04:53:59.451364 INFO : End of read enable training
837 04:53:59.454087 INFO : End of fine write leveling
838 04:53:59.459591 INFO : End of Write leveling coarse delay
839 04:53:59.465242 INFO : Training has run successfully!
840 04:53:59.465767 Check phy result
841 04:53:59.466223 INFO : End of initialization
842 04:53:59.470843 INFO : End of read dq deskew training
843 04:53:59.476381 INFO : End of MPR read delay center optimization
844 04:53:59.476898 INFO : End of write delay center optimization
845 04:53:59.482055 INFO : End of read delay center optimization
846 04:53:59.487601 INFO : End of max read latency training
847 04:53:59.488147 INFO : Training has run successfully!
848 04:53:59.493235 1D training succeed
849 04:53:59.499242 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 04:53:59.546746 Check phy result
851 04:53:59.547266 INFO : End of initialization
852 04:53:59.569229 INFO : End of 2D read delay Voltage center optimization
853 04:53:59.589327 INFO : End of 2D read delay Voltage center optimization
854 04:53:59.641251 INFO : End of 2D write delay Voltage center optimization
855 04:53:59.690540 INFO : End of 2D write delay Voltage center optimization
856 04:53:59.696141 INFO : Training has run successfully!
857 04:53:59.696661
858 04:53:59.697113 channel==0
859 04:53:59.701651 RxClkDly_Margin_A0==88 ps 9
860 04:53:59.702171 TxDqDly_Margin_A0==98 ps 10
861 04:53:59.707277 RxClkDly_Margin_A1==88 ps 9
862 04:53:59.707812 TxDqDly_Margin_A1==98 ps 10
863 04:53:59.708347 TrainedVREFDQ_A0==74
864 04:53:59.712899 TrainedVREFDQ_A1==74
865 04:53:59.713445 VrefDac_Margin_A0==25
866 04:53:59.713903 DeviceVref_Margin_A0==40
867 04:53:59.718447 VrefDac_Margin_A1==25
868 04:53:59.718977 DeviceVref_Margin_A1==40
869 04:53:59.719408
870 04:53:59.719834
871 04:53:59.724121 channel==1
872 04:53:59.724630 RxClkDly_Margin_A0==98 ps 10
873 04:53:59.725060 TxDqDly_Margin_A0==98 ps 10
874 04:53:59.729644 RxClkDly_Margin_A1==98 ps 10
875 04:53:59.730151 TxDqDly_Margin_A1==88 ps 9
876 04:53:59.735306 TrainedVREFDQ_A0==77
877 04:53:59.735818 TrainedVREFDQ_A1==77
878 04:53:59.736285 VrefDac_Margin_A0==23
879 04:53:59.740887 DeviceVref_Margin_A0==37
880 04:53:59.741393 VrefDac_Margin_A1==22
881 04:53:59.746430 DeviceVref_Margin_A1==37
882 04:53:59.746934
883 04:53:59.747367 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 04:53:59.752038
885 04:53:59.779955 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
886 04:53:59.780535 2D training succeed
887 04:53:59.785632 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 04:53:59.791192 auto size-- 65535DDR cs0 size: 2048MB
889 04:53:59.791709 DDR cs1 size: 2048MB
890 04:53:59.796871 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 04:53:59.797381 cs0 DataBus test pass
892 04:53:59.802453 cs1 DataBus test pass
893 04:53:59.802957 cs0 AddrBus test pass
894 04:53:59.803390 cs1 AddrBus test pass
895 04:53:59.803813
896 04:53:59.808055 100bdlr_step_size ps== 420
897 04:53:59.808575 result report
898 04:53:59.813643 boot times 0Enable ddr reg access
899 04:53:59.819098 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 04:53:59.832485 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 04:54:00.404508 0.0;M3 CHK:0;cm4_sp_mode 0
902 04:54:00.404816 MVN_1=0x00000000
903 04:54:00.410035 MVN_2=0x00000000
904 04:54:00.415974 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 04:54:00.416538 OPS=0x10
906 04:54:00.416998 ring efuse init
907 04:54:00.417447 chipver efuse init
908 04:54:00.421419 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 04:54:00.426908 [0.018961 Inits done]
910 04:54:00.427420 secure task start!
911 04:54:00.427872 high task start!
912 04:54:00.431622 low task start!
913 04:54:00.432172 run into bl31
914 04:54:00.438252 NOTICE: BL31: v1.3(release):4fc40b1
915 04:54:00.446020 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 04:54:00.446546 NOTICE: BL31: G12A normal boot!
917 04:54:00.471269 NOTICE: BL31: BL33 decompress pass
918 04:54:00.477023 ERROR: Error initializing runtime service opteed_fast
919 04:54:01.709823
920 04:54:01.710142
921 04:54:01.718337 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 04:54:01.719477
923 04:54:01.720432 Model: Libre Computer AML-A311D-CC Alta
924 04:54:01.926774 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 04:54:01.950322 DRAM: 2 GiB (effective 3.8 GiB)
926 04:54:02.093091 Core: 408 devices, 31 uclasses, devicetree: separate
927 04:54:02.099079 WDT: Not starting watchdog@f0d0
928 04:54:02.131098 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 04:54:02.143588 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 04:54:02.148685 ** Bad device specification mmc 0 **
931 04:54:02.159157 Card did not respond to voltage select! : -110
932 04:54:02.166801 ** Bad device specification mmc 0 **
933 04:54:02.167335 Couldn't find partition mmc 0
934 04:54:02.175076 Card did not respond to voltage select! : -110
935 04:54:02.180576 ** Bad device specification mmc 0 **
936 04:54:02.181100 Couldn't find partition mmc 0
937 04:54:02.185638 Error: could not access storage.
938 04:54:02.528207 Net: eth0: ethernet@ff3f0000
939 04:54:02.528752 starting USB...
940 04:54:02.779869 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 04:54:02.780433 Starting the controller
942 04:54:02.786903 USB XHCI 1.10
943 04:54:04.649737 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
944 04:54:04.650315 bl2_stage_init 0x01
945 04:54:04.650785 bl2_stage_init 0x81
946 04:54:04.655325 hw id: 0x0000 - pwm id 0x01
947 04:54:04.655854 bl2_stage_init 0xc1
948 04:54:04.656369 bl2_stage_init 0x02
949 04:54:04.656825
950 04:54:04.660872 L0:00000000
951 04:54:04.661396 L1:20000703
952 04:54:04.661854 L2:00008067
953 04:54:04.662301 L3:14000000
954 04:54:04.666543 B2:00402000
955 04:54:04.667064 B1:e0f83180
956 04:54:04.667522
957 04:54:04.667974 TE: 58159
958 04:54:04.668461
959 04:54:04.672140 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 04:54:04.672681
961 04:54:04.673139 Board ID = 1
962 04:54:04.677701 Set A53 clk to 24M
963 04:54:04.678227 Set A73 clk to 24M
964 04:54:04.678685 Set clk81 to 24M
965 04:54:04.683328 A53 clk: 1200 MHz
966 04:54:04.683845 A73 clk: 1200 MHz
967 04:54:04.684342 CLK81: 166.6M
968 04:54:04.684789 smccc: 00012ab5
969 04:54:04.688888 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 04:54:04.694495 board id: 1
971 04:54:04.700345 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 04:54:04.710957 fw parse done
973 04:54:04.716989 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 04:54:04.759549 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 04:54:04.770451 PIEI prepare done
976 04:54:04.770960 fastboot data load
977 04:54:04.771394 fastboot data verify
978 04:54:04.776215 verify result: 266
979 04:54:04.781767 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 04:54:04.782281 LPDDR4 probe
981 04:54:04.782710 ddr clk to 1584MHz
982 04:54:04.789709 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 04:54:04.826103
984 04:54:04.826614 dmc_version 0001
985 04:54:04.833663 Check phy result
986 04:54:04.839542 INFO : End of CA training
987 04:54:04.840074 INFO : End of initialization
988 04:54:04.845189 INFO : Training has run successfully!
989 04:54:04.845693 Check phy result
990 04:54:04.850773 INFO : End of initialization
991 04:54:04.851275 INFO : End of read enable training
992 04:54:04.856386 INFO : End of fine write leveling
993 04:54:04.862008 INFO : End of Write leveling coarse delay
994 04:54:04.862528 INFO : Training has run successfully!
995 04:54:04.862982 Check phy result
996 04:54:04.867592 INFO : End of initialization
997 04:54:04.868147 INFO : End of read dq deskew training
998 04:54:04.873185 INFO : End of MPR read delay center optimization
999 04:54:04.878815 INFO : End of write delay center optimization
1000 04:54:04.884386 INFO : End of read delay center optimization
1001 04:54:04.884918 INFO : End of max read latency training
1002 04:54:04.890016 INFO : Training has run successfully!
1003 04:54:04.890540 1D training succeed
1004 04:54:04.899176 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 04:54:04.946719 Check phy result
1006 04:54:04.947239 INFO : End of initialization
1007 04:54:04.968476 INFO : End of 2D read delay Voltage center optimization
1008 04:54:04.988780 INFO : End of 2D read delay Voltage center optimization
1009 04:54:05.040794 INFO : End of 2D write delay Voltage center optimization
1010 04:54:05.090196 INFO : End of 2D write delay Voltage center optimization
1011 04:54:05.095760 INFO : Training has run successfully!
1012 04:54:05.096338
1013 04:54:05.096814 channel==0
1014 04:54:05.101367 RxClkDly_Margin_A0==88 ps 9
1015 04:54:05.101905 TxDqDly_Margin_A0==98 ps 10
1016 04:54:05.104796 RxClkDly_Margin_A1==88 ps 9
1017 04:54:05.105318 TxDqDly_Margin_A1==98 ps 10
1018 04:54:05.110085 TrainedVREFDQ_A0==74
1019 04:54:05.110616 TrainedVREFDQ_A1==74
1020 04:54:05.115660 VrefDac_Margin_A0==25
1021 04:54:05.116220 DeviceVref_Margin_A0==40
1022 04:54:05.116687 VrefDac_Margin_A1==25
1023 04:54:05.121348 DeviceVref_Margin_A1==40
1024 04:54:05.121869
1025 04:54:05.122330
1026 04:54:05.122775 channel==1
1027 04:54:05.123219 RxClkDly_Margin_A0==98 ps 10
1028 04:54:05.126866 TxDqDly_Margin_A0==88 ps 9
1029 04:54:05.127392 RxClkDly_Margin_A1==98 ps 10
1030 04:54:05.132603 TxDqDly_Margin_A1==88 ps 9
1031 04:54:05.133129 TrainedVREFDQ_A0==76
1032 04:54:05.133591 TrainedVREFDQ_A1==77
1033 04:54:05.138133 VrefDac_Margin_A0==22
1034 04:54:05.138653 DeviceVref_Margin_A0==38
1035 04:54:05.143687 VrefDac_Margin_A1==22
1036 04:54:05.144235 DeviceVref_Margin_A1==37
1037 04:54:05.144692
1038 04:54:05.149160 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 04:54:05.149683
1040 04:54:05.177200 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1041 04:54:05.182774 2D training succeed
1042 04:54:05.188388 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 04:54:05.188922 auto size-- 65535DDR cs0 size: 2048MB
1044 04:54:05.193986 DDR cs1 size: 2048MB
1045 04:54:05.194520 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 04:54:05.199579 cs0 DataBus test pass
1047 04:54:05.200141 cs1 DataBus test pass
1048 04:54:05.200610 cs0 AddrBus test pass
1049 04:54:05.205208 cs1 AddrBus test pass
1050 04:54:05.205728
1051 04:54:05.206189 100bdlr_step_size ps== 420
1052 04:54:05.206653 result report
1053 04:54:05.210789 boot times 0Enable ddr reg access
1054 04:54:05.218658 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 04:54:05.232039 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 04:54:05.805749 0.0;M3 CHK:0;cm4_sp_mode 0
1057 04:54:05.806376 MVN_1=0x00000000
1058 04:54:05.811287 MVN_2=0x00000000
1059 04:54:05.817027 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 04:54:05.817554 OPS=0x10
1061 04:54:05.818019 ring efuse init
1062 04:54:05.818465 chipver efuse init
1063 04:54:05.822656 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 04:54:05.828234 [0.018961 Inits done]
1065 04:54:05.828758 secure task start!
1066 04:54:05.829212 high task start!
1067 04:54:05.832791 low task start!
1068 04:54:05.833307 run into bl31
1069 04:54:05.839456 NOTICE: BL31: v1.3(release):4fc40b1
1070 04:54:05.847281 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 04:54:05.847806 NOTICE: BL31: G12A normal boot!
1072 04:54:05.872653 NOTICE: BL31: BL33 decompress pass
1073 04:54:05.877293 ERROR: Error initializing runtime service opteed_fast
1074 04:54:07.111031
1075 04:54:07.111617
1076 04:54:07.118592 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 04:54:07.119126
1078 04:54:07.119596 Model: Libre Computer AML-A311D-CC Alta
1079 04:54:07.327896 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 04:54:07.351304 DRAM: 2 GiB (effective 3.8 GiB)
1081 04:54:07.494320 Core: 408 devices, 31 uclasses, devicetree: separate
1082 04:54:07.499241 WDT: Not starting watchdog@f0d0
1083 04:54:07.532409 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 04:54:07.544841 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 04:54:07.548939 ** Bad device specification mmc 0 **
1086 04:54:07.560194 Card did not respond to voltage select! : -110
1087 04:54:07.567876 ** Bad device specification mmc 0 **
1088 04:54:07.568426 Couldn't find partition mmc 0
1089 04:54:07.576197 Card did not respond to voltage select! : -110
1090 04:54:07.581793 ** Bad device specification mmc 0 **
1091 04:54:07.582317 Couldn't find partition mmc 0
1092 04:54:07.586924 Error: could not access storage.
1093 04:54:07.930292 Net: eth0: ethernet@ff3f0000
1094 04:54:07.930845 starting USB...
1095 04:54:08.182049 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 04:54:08.182602 Starting the controller
1097 04:54:08.189056 USB XHCI 1.10
1098 04:54:09.742962 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 04:54:09.751308 scanning usb for storage devices... 0 Storage Device(s) found
1101 04:54:09.803085 Hit any key to stop autoboot: 1
1102 04:54:09.804111 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1103 04:54:09.804819 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1104 04:54:09.805333 Setting prompt string to ['=>']
1105 04:54:09.805850 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1106 04:54:09.818745 0
1107 04:54:09.819694 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 04:54:09.820264 Sending with 10 millisecond of delay
1110 04:54:10.955006 => setenv autoload no
1111 04:54:10.965800 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1112 04:54:10.971151 setenv autoload no
1113 04:54:10.971952 Sending with 10 millisecond of delay
1115 04:54:12.769284 => setenv initrd_high 0xffffffff
1116 04:54:12.779794 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1117 04:54:12.780335 setenv initrd_high 0xffffffff
1118 04:54:12.780850 Sending with 10 millisecond of delay
1120 04:54:14.396810 => setenv fdt_high 0xffffffff
1121 04:54:14.407663 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 04:54:14.408613 setenv fdt_high 0xffffffff
1123 04:54:14.409387 Sending with 10 millisecond of delay
1125 04:54:14.701279 => dhcp
1126 04:54:14.712061 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1127 04:54:14.712959 dhcp
1128 04:54:14.713443 Speed: 1000, full duplex
1129 04:54:14.713899 BOOTP broadcast 1
1130 04:54:14.888713 DHCP client bound to address 192.168.6.33 (176 ms)
1131 04:54:14.889553 Sending with 10 millisecond of delay
1133 04:54:16.567776 => setenv serverip 192.168.6.2
1134 04:54:16.579248 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1135 04:54:16.580809 setenv serverip 192.168.6.2
1136 04:54:16.581973 Sending with 10 millisecond of delay
1138 04:54:20.308277 => tftpboot 0x01080000 681347/tftp-deploy-1r6yf6lf/kernel/uImage
1139 04:54:20.321391 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1140 04:54:20.321984 tftpboot 0x01080000 681347/tftp-deploy-1r6yf6lf/kernel/uImage
1141 04:54:20.322240 Speed: 1000, full duplex
1142 04:54:20.322463 Using ethernet@ff3f0000 device
1143 04:54:20.322676 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1144 04:54:20.327104 Filename '681347/tftp-deploy-1r6yf6lf/kernel/uImage'.
1145 04:54:20.331090 Load address: 0x1080000
1146 04:54:24.532642 Loading: *###################
1147 04:54:24.533312 TFTP error: trying to overwrite reserved memory...
1149 04:54:24.534806 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1152 04:54:24.536895 end: 2.4 uboot-commands (duration 00:00:52) [common]
1154 04:54:24.538416 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1156 04:54:24.539547 end: 2 uboot-action (duration 00:00:52) [common]
1158 04:54:24.541262 Cleaning after the job
1159 04:54:24.541886 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/ramdisk
1160 04:54:24.572130 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/kernel
1161 04:54:24.629988 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/dtb
1162 04:54:24.630908 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/nfsrootfs
1163 04:54:24.783172 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681347/tftp-deploy-1r6yf6lf/modules
1164 04:54:24.836417 start: 4.1 power-off (timeout 00:00:30) [common]
1165 04:54:24.837098 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1166 04:54:24.870003 >> OK - accepted request
1167 04:54:24.871808 Returned 0 in 0 seconds
1168 04:54:24.972626 end: 4.1 power-off (duration 00:00:00) [common]
1170 04:54:24.973615 start: 4.2 read-feedback (timeout 00:10:00) [common]
1171 04:54:24.974254 Listened to connection for namespace 'common' for up to 1s
1172 04:54:25.975188 Finalising connection for namespace 'common'
1173 04:54:25.975692 Disconnecting from shell: Finalise
1174 04:54:25.976007 =>
1175 04:54:26.076689 end: 4.2 read-feedback (duration 00:00:01) [common]
1176 04:54:26.077139 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681347
1177 04:54:27.907657 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681347
1178 04:54:27.908310 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.