Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:19:55.049700 lava-dispatcher, installed at version: 2024.01
2 05:19:55.050534 start: 0 validate
3 05:19:55.051028 Start time: 2024-08-31 05:19:55.050997+00:00 (UTC)
4 05:19:55.051595 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:19:55.052426 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:19:55.092963 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:19:55.093535 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fkernel%2FImage exists
8 05:19:55.126075 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:19:55.126750 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:19:57.179045 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:19:57.179604 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fmodules.tar.xz exists
12 05:19:57.214366 validate duration: 2.16
14 05:19:57.215235 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:19:57.215584 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:19:57.215890 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:19:57.216508 Not decompressing ramdisk as can be used compressed.
18 05:19:57.216956 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:19:57.217204 saving as /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/ramdisk/rootfs.cpio.gz
20 05:19:57.217474 total size: 8181887 (7 MB)
21 05:19:57.253175 progress 0 % (0 MB)
22 05:19:57.260223 progress 5 % (0 MB)
23 05:19:57.266148 progress 10 % (0 MB)
24 05:19:57.272185 progress 15 % (1 MB)
25 05:19:57.277925 progress 20 % (1 MB)
26 05:19:57.283841 progress 25 % (1 MB)
27 05:19:57.289612 progress 30 % (2 MB)
28 05:19:57.295674 progress 35 % (2 MB)
29 05:19:57.301137 progress 40 % (3 MB)
30 05:19:57.307229 progress 45 % (3 MB)
31 05:19:57.312852 progress 50 % (3 MB)
32 05:19:57.318939 progress 55 % (4 MB)
33 05:19:57.324443 progress 60 % (4 MB)
34 05:19:57.330477 progress 65 % (5 MB)
35 05:19:57.336054 progress 70 % (5 MB)
36 05:19:57.342405 progress 75 % (5 MB)
37 05:19:57.347830 progress 80 % (6 MB)
38 05:19:57.353672 progress 85 % (6 MB)
39 05:19:57.358754 progress 90 % (7 MB)
40 05:19:57.363934 progress 95 % (7 MB)
41 05:19:57.369148 progress 100 % (7 MB)
42 05:19:57.369892 7 MB downloaded in 0.15 s (51.20 MB/s)
43 05:19:57.370451 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:19:57.371354 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:19:57.371645 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:19:57.371914 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:19:57.372427 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/kernel/Image
49 05:19:57.372708 saving as /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/kernel/Image
50 05:19:57.372922 total size: 39021056 (37 MB)
51 05:19:57.373146 No compression specified
52 05:19:57.413284 progress 0 % (0 MB)
53 05:19:57.439516 progress 5 % (1 MB)
54 05:19:57.466584 progress 10 % (3 MB)
55 05:19:57.492023 progress 15 % (5 MB)
56 05:19:57.517970 progress 20 % (7 MB)
57 05:19:57.543554 progress 25 % (9 MB)
58 05:19:57.568596 progress 30 % (11 MB)
59 05:19:57.592991 progress 35 % (13 MB)
60 05:19:57.617523 progress 40 % (14 MB)
61 05:19:57.642004 progress 45 % (16 MB)
62 05:19:57.666988 progress 50 % (18 MB)
63 05:19:57.691205 progress 55 % (20 MB)
64 05:19:57.716007 progress 60 % (22 MB)
65 05:19:57.741033 progress 65 % (24 MB)
66 05:19:57.765291 progress 70 % (26 MB)
67 05:19:57.790057 progress 75 % (27 MB)
68 05:19:57.814530 progress 80 % (29 MB)
69 05:19:57.839433 progress 85 % (31 MB)
70 05:19:57.863762 progress 90 % (33 MB)
71 05:19:57.888506 progress 95 % (35 MB)
72 05:19:57.911569 progress 100 % (37 MB)
73 05:19:57.912350 37 MB downloaded in 0.54 s (68.99 MB/s)
74 05:19:57.912847 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:19:57.913670 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:19:57.913943 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:19:57.914206 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:19:57.914663 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 05:19:57.914965 saving as /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/dtb/meson-g12b-a311d-libretech-cc.dtb
81 05:19:57.915179 total size: 54667 (0 MB)
82 05:19:57.915391 No compression specified
83 05:19:57.948651 progress 59 % (0 MB)
84 05:19:57.949501 progress 100 % (0 MB)
85 05:19:57.950042 0 MB downloaded in 0.03 s (1.50 MB/s)
86 05:19:57.950503 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:19:57.951324 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:19:57.951584 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:19:57.951848 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:19:57.952333 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/modules.tar.xz
92 05:19:57.952585 saving as /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/modules/modules.tar
93 05:19:57.952792 total size: 11634432 (11 MB)
94 05:19:57.953005 Using unxz to decompress xz
95 05:19:57.988757 progress 0 % (0 MB)
96 05:19:58.058122 progress 5 % (0 MB)
97 05:19:58.137866 progress 10 % (1 MB)
98 05:19:58.228098 progress 15 % (1 MB)
99 05:19:58.310665 progress 20 % (2 MB)
100 05:19:58.388258 progress 25 % (2 MB)
101 05:19:58.473795 progress 30 % (3 MB)
102 05:19:58.555686 progress 35 % (3 MB)
103 05:19:58.636376 progress 40 % (4 MB)
104 05:19:58.711047 progress 45 % (5 MB)
105 05:19:58.791306 progress 50 % (5 MB)
106 05:19:58.869492 progress 55 % (6 MB)
107 05:19:58.955829 progress 60 % (6 MB)
108 05:19:59.039088 progress 65 % (7 MB)
109 05:19:59.123080 progress 70 % (7 MB)
110 05:19:59.217747 progress 75 % (8 MB)
111 05:19:59.314194 progress 80 % (8 MB)
112 05:19:59.392236 progress 85 % (9 MB)
113 05:19:59.472154 progress 90 % (10 MB)
114 05:19:59.551073 progress 95 % (10 MB)
115 05:19:59.628927 progress 100 % (11 MB)
116 05:19:59.638789 11 MB downloaded in 1.69 s (6.58 MB/s)
117 05:19:59.639382 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:19:59.640513 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:19:59.641094 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 05:19:59.641665 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 05:19:59.642207 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:19:59.642758 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 05:19:59.643816 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm
125 05:19:59.644790 makedir: /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin
126 05:19:59.645505 makedir: /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/tests
127 05:19:59.646225 makedir: /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/results
128 05:19:59.646896 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-add-keys
129 05:19:59.647961 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-add-sources
130 05:19:59.649037 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-background-process-start
131 05:19:59.650117 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-background-process-stop
132 05:19:59.651206 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-common-functions
133 05:19:59.652272 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-echo-ipv4
134 05:19:59.653305 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-install-packages
135 05:19:59.654292 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-installed-packages
136 05:19:59.655284 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-os-build
137 05:19:59.656314 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-probe-channel
138 05:19:59.657327 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-probe-ip
139 05:19:59.658356 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-target-ip
140 05:19:59.659379 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-target-mac
141 05:19:59.660399 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-target-storage
142 05:19:59.661422 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-test-case
143 05:19:59.662440 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-test-event
144 05:19:59.663561 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-test-feedback
145 05:19:59.664600 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-test-raise
146 05:19:59.665580 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-test-reference
147 05:19:59.666568 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-test-runner
148 05:19:59.667580 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-test-set
149 05:19:59.668610 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-test-shell
150 05:19:59.669602 Updating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-install-packages (oe)
151 05:19:59.670717 Updating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/bin/lava-installed-packages (oe)
152 05:19:59.671661 Creating /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/environment
153 05:19:59.672520 LAVA metadata
154 05:19:59.673059 - LAVA_JOB_ID=681648
155 05:19:59.673528 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:19:59.674270 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 05:19:59.676259 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:19:59.676857 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 05:19:59.677271 skipped lava-vland-overlay
160 05:19:59.677757 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:19:59.678265 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 05:19:59.678696 skipped lava-multinode-overlay
163 05:19:59.679179 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:19:59.679706 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 05:19:59.680308 Loading test definitions
166 05:19:59.680947 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 05:19:59.681394 Using /lava-681648 at stage 0
168 05:19:59.683651 uuid=681648_1.5.2.4.1 testdef=None
169 05:19:59.684189 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:19:59.684471 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 05:19:59.686357 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:19:59.687180 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 05:19:59.689566 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:19:59.690456 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 05:19:59.692781 runner path: /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/0/tests/0_dmesg test_uuid 681648_1.5.2.4.1
178 05:19:59.693443 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:19:59.694235 Creating lava-test-runner.conf files
181 05:19:59.694442 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681648/lava-overlay-4mdfyxcm/lava-681648/0 for stage 0
182 05:19:59.694797 - 0_dmesg
183 05:19:59.695159 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:19:59.695441 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 05:19:59.719757 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:19:59.720227 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:19:59.720494 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:19:59.720764 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:19:59.721029 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:20:00.661755 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:20:00.662214 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 05:20:00.662498 extracting modules file /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681648/extract-overlay-ramdisk-l3um3q1v/ramdisk
193 05:20:01.992225 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 05:20:01.992730 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 05:20:01.993016 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681648/compress-overlay-k3qqimbx/overlay-1.5.2.5.tar.gz to ramdisk
196 05:20:01.993232 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681648/compress-overlay-k3qqimbx/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681648/extract-overlay-ramdisk-l3um3q1v/ramdisk
197 05:20:02.023881 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:20:02.024354 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 05:20:02.024631 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 05:20:02.024862 Converting downloaded kernel to a uImage
201 05:20:02.025176 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/kernel/Image /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/kernel/uImage
202 05:20:02.447487 output: Image Name:
203 05:20:02.447912 output: Created: Sat Aug 31 05:20:02 2024
204 05:20:02.448159 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:20:02.448367 output: Data Size: 39021056 Bytes = 38106.50 KiB = 37.21 MiB
206 05:20:02.448570 output: Load Address: 01080000
207 05:20:02.448769 output: Entry Point: 01080000
208 05:20:02.448966 output:
209 05:20:02.449295 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 05:20:02.449559 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 05:20:02.449831 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 05:20:02.450083 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:20:02.450338 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 05:20:02.450591 Building ramdisk /var/lib/lava/dispatcher/tmp/681648/extract-overlay-ramdisk-l3um3q1v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681648/extract-overlay-ramdisk-l3um3q1v/ramdisk
215 05:20:05.031218 >> 186562 blocks
216 05:20:13.302551 Adding RAMdisk u-boot header.
217 05:20:13.302984 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681648/extract-overlay-ramdisk-l3um3q1v/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681648/extract-overlay-ramdisk-l3um3q1v/ramdisk.cpio.gz.uboot
218 05:20:13.604291 output: Image Name:
219 05:20:13.604694 output: Created: Sat Aug 31 05:20:13 2024
220 05:20:13.604904 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:20:13.605106 output: Data Size: 26553761 Bytes = 25931.41 KiB = 25.32 MiB
222 05:20:13.605303 output: Load Address: 00000000
223 05:20:13.605499 output: Entry Point: 00000000
224 05:20:13.605694 output:
225 05:20:13.606271 rename /var/lib/lava/dispatcher/tmp/681648/extract-overlay-ramdisk-l3um3q1v/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/ramdisk/ramdisk.cpio.gz.uboot
226 05:20:13.606676 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 05:20:13.606951 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 05:20:13.607217 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 05:20:13.607450 No LXC device requested
230 05:20:13.607697 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:20:13.607949 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 05:20:13.608544 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:20:13.609002 Checking files for TFTP limit of 4294967296 bytes.
234 05:20:13.611930 end: 1 tftp-deploy (duration 00:00:16) [common]
235 05:20:13.612587 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:20:13.613162 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:20:13.613707 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:20:13.614252 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:20:13.614831 Using kernel file from prepare-kernel: 681648/tftp-deploy-y2bz_llu/kernel/uImage
240 05:20:13.615515 substitutions:
241 05:20:13.615968 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:20:13.616450 - {DTB_ADDR}: 0x01070000
243 05:20:13.616889 - {DTB}: 681648/tftp-deploy-y2bz_llu/dtb/meson-g12b-a311d-libretech-cc.dtb
244 05:20:13.617329 - {INITRD}: 681648/tftp-deploy-y2bz_llu/ramdisk/ramdisk.cpio.gz.uboot
245 05:20:13.617767 - {KERNEL_ADDR}: 0x01080000
246 05:20:13.618198 - {KERNEL}: 681648/tftp-deploy-y2bz_llu/kernel/uImage
247 05:20:13.618634 - {LAVA_MAC}: None
248 05:20:13.619112 - {PRESEED_CONFIG}: None
249 05:20:13.619547 - {PRESEED_LOCAL}: None
250 05:20:13.619998 - {RAMDISK_ADDR}: 0x08000000
251 05:20:13.620434 - {RAMDISK}: 681648/tftp-deploy-y2bz_llu/ramdisk/ramdisk.cpio.gz.uboot
252 05:20:13.620869 - {ROOT_PART}: None
253 05:20:13.621298 - {ROOT}: None
254 05:20:13.621726 - {SERVER_IP}: 192.168.6.2
255 05:20:13.622158 - {TEE_ADDR}: 0x83000000
256 05:20:13.622588 - {TEE}: None
257 05:20:13.623016 Parsed boot commands:
258 05:20:13.623433 - setenv autoload no
259 05:20:13.623861 - setenv initrd_high 0xffffffff
260 05:20:13.624317 - setenv fdt_high 0xffffffff
261 05:20:13.624746 - dhcp
262 05:20:13.625174 - setenv serverip 192.168.6.2
263 05:20:13.625600 - tftpboot 0x01080000 681648/tftp-deploy-y2bz_llu/kernel/uImage
264 05:20:13.626029 - tftpboot 0x08000000 681648/tftp-deploy-y2bz_llu/ramdisk/ramdisk.cpio.gz.uboot
265 05:20:13.626459 - tftpboot 0x01070000 681648/tftp-deploy-y2bz_llu/dtb/meson-g12b-a311d-libretech-cc.dtb
266 05:20:13.626889 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:20:13.627325 - bootm 0x01080000 0x08000000 0x01070000
268 05:20:13.627863 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:20:13.629519 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:20:13.630003 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 05:20:13.645208 Setting prompt string to ['lava-test: # ']
273 05:20:13.646779 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:20:13.647425 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:20:13.648054 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:20:13.648625 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:20:13.649860 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 05:20:13.685764 >> OK - accepted request
279 05:20:13.687856 Returned 0 in 0 seconds
280 05:20:13.789052 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:20:13.790738 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:20:13.791341 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:20:13.791884 Setting prompt string to ['Hit any key to stop autoboot']
285 05:20:13.792466 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:20:13.794189 Trying 192.168.56.21...
287 05:20:13.794703 Connected to conserv1.
288 05:20:13.795157 Escape character is '^]'.
289 05:20:13.795623
290 05:20:13.796128 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 05:20:13.796603
292 05:20:25.114501 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 05:20:25.114950 bl2_stage_init 0x81
294 05:20:25.122345 hw id: 0x0000 - pwm id 0x01
295 05:20:25.122795 bl2_stage_init 0xc1
296 05:20:25.123029 bl2_stage_init 0x02
297 05:20:25.123245
298 05:20:25.123517 L0:00000000
299 05:20:25.123746 L1:20000703
300 05:20:25.123958 L2:00008067
301 05:20:25.124216 L3:14000000
302 05:20:25.124417 B2:00402000
303 05:20:25.132447 B1:e0f83180
304 05:20:25.133183
305 05:20:25.133630 TE: 58150
306 05:20:25.134033
307 05:20:25.134532 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 05:20:25.134913
309 05:20:25.135295 Board ID = 1
310 05:20:25.146832 Set A53 clk to 24M
311 05:20:25.147273 Set A73 clk to 24M
312 05:20:25.147526 Set clk81 to 24M
313 05:20:25.147762 A53 clk: 1200 MHz
314 05:20:25.148042 A73 clk: 1200 MHz
315 05:20:25.148293 CLK81: 166.6M
316 05:20:25.148540 smccc: 00012aac
317 05:20:25.150791 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 05:20:25.157599 board id: 1
319 05:20:25.167301 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 05:20:25.178365 fw parse done
321 05:20:25.183593 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 05:20:25.221214 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 05:20:25.232206 PIEI prepare done
324 05:20:25.232776 fastboot data load
325 05:20:25.233183 fastboot data verify
326 05:20:25.237850 verify result: 266
327 05:20:25.243445 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 05:20:25.244044 LPDDR4 probe
329 05:20:25.244466 ddr clk to 1584MHz
330 05:20:25.251436 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 05:20:25.288719
332 05:20:25.289332 dmc_version 0001
333 05:20:25.295426 Check phy result
334 05:20:25.301227 INFO : End of CA training
335 05:20:25.301801 INFO : End of initialization
336 05:20:25.306823 INFO : Training has run successfully!
337 05:20:25.307381 Check phy result
338 05:20:25.312415 INFO : End of initialization
339 05:20:25.312977 INFO : End of read enable training
340 05:20:25.318112 INFO : End of fine write leveling
341 05:20:25.323656 INFO : End of Write leveling coarse delay
342 05:20:25.324290 INFO : Training has run successfully!
343 05:20:25.324761 Check phy result
344 05:20:25.329277 INFO : End of initialization
345 05:20:25.329797 INFO : End of read dq deskew training
346 05:20:25.334801 INFO : End of MPR read delay center optimization
347 05:20:25.340459 INFO : End of write delay center optimization
348 05:20:25.346013 INFO : End of read delay center optimization
349 05:20:25.346510 INFO : End of max read latency training
350 05:20:25.351603 INFO : Training has run successfully!
351 05:20:25.352125 1D training succeed
352 05:20:25.360728 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 05:20:25.421002 Check phy result
354 05:20:25.421651 INFO : End of initialization
355 05:20:25.431325 INFO : End of 2D read delay Voltage center optimization
356 05:20:25.453499 INFO : End of 2D read delay Voltage center optimization
357 05:20:25.503479 INFO : End of 2D write delay Voltage center optimization
358 05:20:25.552642 INFO : End of 2D write delay Voltage center optimization
359 05:20:25.558138 INFO : Training has run successfully!
360 05:20:25.558521
361 05:20:25.558769 channel==0
362 05:20:25.563718 RxClkDly_Margin_A0==88 ps 9
363 05:20:25.564167 TxDqDly_Margin_A0==98 ps 10
364 05:20:25.569630 RxClkDly_Margin_A1==88 ps 9
365 05:20:25.570008 TxDqDly_Margin_A1==88 ps 9
366 05:20:25.570245 TrainedVREFDQ_A0==74
367 05:20:25.575154 TrainedVREFDQ_A1==74
368 05:20:25.575534 VrefDac_Margin_A0==25
369 05:20:25.575766 DeviceVref_Margin_A0==40
370 05:20:25.580687 VrefDac_Margin_A1==25
371 05:20:25.581040 DeviceVref_Margin_A1==40
372 05:20:25.581266
373 05:20:25.581488
374 05:20:25.581714 channel==1
375 05:20:25.586246 RxClkDly_Margin_A0==98 ps 10
376 05:20:25.586628 TxDqDly_Margin_A0==98 ps 10
377 05:20:25.591872 RxClkDly_Margin_A1==98 ps 10
378 05:20:25.592262 TxDqDly_Margin_A1==88 ps 9
379 05:20:25.597397 TrainedVREFDQ_A0==77
380 05:20:25.597731 TrainedVREFDQ_A1==77
381 05:20:25.597954 VrefDac_Margin_A0==22
382 05:20:25.603048 DeviceVref_Margin_A0==37
383 05:20:25.603342 VrefDac_Margin_A1==24
384 05:20:25.608697 DeviceVref_Margin_A1==37
385 05:20:25.609123
386 05:20:25.609359 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 05:20:25.609581
388 05:20:25.642191 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
389 05:20:25.642641 2D training succeed
390 05:20:25.647762 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 05:20:25.653374 auto size-- 65535DDR cs0 size: 2048MB
392 05:20:25.653757 DDR cs1 size: 2048MB
393 05:20:25.659008 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 05:20:25.659319 cs0 DataBus test pass
395 05:20:25.664477 cs1 DataBus test pass
396 05:20:25.664778 cs0 AddrBus test pass
397 05:20:25.664995 cs1 AddrBus test pass
398 05:20:25.665203
399 05:20:25.670099 100bdlr_step_size ps== 420
400 05:20:25.670419 result report
401 05:20:25.675678 boot times 0Enable ddr reg access
402 05:20:25.681050 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 05:20:25.694513 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 05:20:26.267623 0.0;M3 CHK:0;cm4_sp_mode 0
405 05:20:26.268080 MVN_1=0x00000000
406 05:20:26.272999 MVN_2=0x00000000
407 05:20:26.278768 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 05:20:26.279231 OPS=0x10
409 05:20:26.279464 ring efuse init
410 05:20:26.279681 chipver efuse init
411 05:20:26.284364 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 05:20:26.289955 [0.018961 Inits done]
413 05:20:26.290223 secure task start!
414 05:20:26.290441 high task start!
415 05:20:26.294574 low task start!
416 05:20:26.294854 run into bl31
417 05:20:26.301325 NOTICE: BL31: v1.3(release):4fc40b1
418 05:20:26.309034 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 05:20:26.309317 NOTICE: BL31: G12A normal boot!
420 05:20:26.334473 NOTICE: BL31: BL33 decompress pass
421 05:20:26.340099 ERROR: Error initializing runtime service opteed_fast
422 05:20:27.573063
423 05:20:27.573479
424 05:20:27.581373 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 05:20:27.581675
426 05:20:27.581900 Model: Libre Computer AML-A311D-CC Alta
427 05:20:27.789897 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 05:20:27.813265 DRAM: 2 GiB (effective 3.8 GiB)
429 05:20:27.956291 Core: 408 devices, 31 uclasses, devicetree: separate
430 05:20:27.962038 WDT: Not starting watchdog@f0d0
431 05:20:27.994358 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 05:20:28.006781 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 05:20:28.011741 ** Bad device specification mmc 0 **
434 05:20:28.022085 Card did not respond to voltage select! : -110
435 05:20:28.029724 ** Bad device specification mmc 0 **
436 05:20:28.030034 Couldn't find partition mmc 0
437 05:20:28.038065 Card did not respond to voltage select! : -110
438 05:20:28.043577 ** Bad device specification mmc 0 **
439 05:20:28.043870 Couldn't find partition mmc 0
440 05:20:28.048634 Error: could not access storage.
441 05:20:29.311791 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
442 05:20:29.312485 bl2_stage_init 0x01
443 05:20:29.312900 bl2_stage_init 0x81
444 05:20:29.317296 hw id: 0x0000 - pwm id 0x01
445 05:20:29.317753 bl2_stage_init 0xc1
446 05:20:29.318152 bl2_stage_init 0x02
447 05:20:29.318545
448 05:20:29.322892 L0:00000000
449 05:20:29.323333 L1:20000703
450 05:20:29.323730 L2:00008067
451 05:20:29.324155 L3:14000000
452 05:20:29.328496 B2:00402000
453 05:20:29.328921 B1:e0f83180
454 05:20:29.329310
455 05:20:29.329700 TE: 58159
456 05:20:29.330091
457 05:20:29.334097 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 05:20:29.334541
459 05:20:29.334949 Board ID = 1
460 05:20:29.339714 Set A53 clk to 24M
461 05:20:29.340170 Set A73 clk to 24M
462 05:20:29.340566 Set clk81 to 24M
463 05:20:29.345292 A53 clk: 1200 MHz
464 05:20:29.345714 A73 clk: 1200 MHz
465 05:20:29.346103 CLK81: 166.6M
466 05:20:29.346491 smccc: 00012ab5
467 05:20:29.350887 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 05:20:29.356501 board id: 1
469 05:20:29.362471 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 05:20:29.374225 fw parse done
471 05:20:29.379157 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 05:20:29.421626 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 05:20:29.432513 PIEI prepare done
474 05:20:29.432844 fastboot data load
475 05:20:29.433059 fastboot data verify
476 05:20:29.438171 verify result: 266
477 05:20:29.443851 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 05:20:29.444437 LPDDR4 probe
479 05:20:29.444842 ddr clk to 1584MHz
480 05:20:29.451770 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 05:20:29.489092
482 05:20:29.489700 dmc_version 0001
483 05:20:29.495704 Check phy result
484 05:20:29.501587 INFO : End of CA training
485 05:20:29.502082 INFO : End of initialization
486 05:20:29.507194 INFO : Training has run successfully!
487 05:20:29.507714 Check phy result
488 05:20:29.512772 INFO : End of initialization
489 05:20:29.513287 INFO : End of read enable training
490 05:20:29.518369 INFO : End of fine write leveling
491 05:20:29.523964 INFO : End of Write leveling coarse delay
492 05:20:29.524490 INFO : Training has run successfully!
493 05:20:29.524918 Check phy result
494 05:20:29.529607 INFO : End of initialization
495 05:20:29.530108 INFO : End of read dq deskew training
496 05:20:29.535169 INFO : End of MPR read delay center optimization
497 05:20:29.540763 INFO : End of write delay center optimization
498 05:20:29.546365 INFO : End of read delay center optimization
499 05:20:29.546880 INFO : End of max read latency training
500 05:20:29.551938 INFO : Training has run successfully!
501 05:20:29.552454 1D training succeed
502 05:20:29.561162 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 05:20:29.608850 Check phy result
504 05:20:29.609266 INFO : End of initialization
505 05:20:29.630597 INFO : End of 2D read delay Voltage center optimization
506 05:20:29.650852 INFO : End of 2D read delay Voltage center optimization
507 05:20:29.702960 INFO : End of 2D write delay Voltage center optimization
508 05:20:29.752283 INFO : End of 2D write delay Voltage center optimization
509 05:20:29.757802 INFO : Training has run successfully!
510 05:20:29.758109
511 05:20:29.758331 channel==0
512 05:20:29.763383 RxClkDly_Margin_A0==88 ps 9
513 05:20:29.763682 TxDqDly_Margin_A0==98 ps 10
514 05:20:29.768975 RxClkDly_Margin_A1==88 ps 9
515 05:20:29.769265 TxDqDly_Margin_A1==98 ps 10
516 05:20:29.769481 TrainedVREFDQ_A0==74
517 05:20:29.774626 TrainedVREFDQ_A1==75
518 05:20:29.774954 VrefDac_Margin_A0==25
519 05:20:29.775170 DeviceVref_Margin_A0==40
520 05:20:29.780204 VrefDac_Margin_A1==25
521 05:20:29.780498 DeviceVref_Margin_A1==39
522 05:20:29.780711
523 05:20:29.780918
524 05:20:29.785792 channel==1
525 05:20:29.786077 RxClkDly_Margin_A0==88 ps 9
526 05:20:29.786281 TxDqDly_Margin_A0==98 ps 10
527 05:20:29.791405 RxClkDly_Margin_A1==98 ps 10
528 05:20:29.791698 TxDqDly_Margin_A1==108 ps 11
529 05:20:29.796983 TrainedVREFDQ_A0==76
530 05:20:29.797279 TrainedVREFDQ_A1==78
531 05:20:29.797489 VrefDac_Margin_A0==22
532 05:20:29.802589 DeviceVref_Margin_A0==38
533 05:20:29.802890 VrefDac_Margin_A1==22
534 05:20:29.808187 DeviceVref_Margin_A1==36
535 05:20:29.808487
536 05:20:29.808696 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 05:20:29.813798
538 05:20:29.841798 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
539 05:20:29.842185 2D training succeed
540 05:20:29.847379 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 05:20:29.852972 auto size-- 65535DDR cs0 size: 2048MB
542 05:20:29.853276 DDR cs1 size: 2048MB
543 05:20:29.858594 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 05:20:29.858890 cs0 DataBus test pass
545 05:20:29.864191 cs1 DataBus test pass
546 05:20:29.864485 cs0 AddrBus test pass
547 05:20:29.864694 cs1 AddrBus test pass
548 05:20:29.864896
549 05:20:29.869778 100bdlr_step_size ps== 420
550 05:20:29.870081 result report
551 05:20:29.875420 boot times 0Enable ddr reg access
552 05:20:29.880919 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 05:20:29.894387 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 05:20:30.468187 0.0;M3 CHK:0;cm4_sp_mode 0
555 05:20:30.468619 MVN_1=0x00000000
556 05:20:30.473655 MVN_2=0x00000000
557 05:20:30.479431 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 05:20:30.479743 OPS=0x10
559 05:20:30.479949 ring efuse init
560 05:20:30.480186 chipver efuse init
561 05:20:30.485002 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 05:20:30.490511 [0.018961 Inits done]
563 05:20:30.490808 secure task start!
564 05:20:30.491014 high task start!
565 05:20:30.495220 low task start!
566 05:20:30.495511 run into bl31
567 05:20:30.501938 NOTICE: BL31: v1.3(release):4fc40b1
568 05:20:30.509647 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 05:20:30.509960 NOTICE: BL31: G12A normal boot!
570 05:20:30.535050 NOTICE: BL31: BL33 decompress pass
571 05:20:30.540804 ERROR: Error initializing runtime service opteed_fast
572 05:20:31.773571
573 05:20:31.773982
574 05:20:31.782084 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 05:20:31.782389
576 05:20:31.782605 Model: Libre Computer AML-A311D-CC Alta
577 05:20:31.990423 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 05:20:32.013852 DRAM: 2 GiB (effective 3.8 GiB)
579 05:20:32.156727 Core: 408 devices, 31 uclasses, devicetree: separate
580 05:20:32.162680 WDT: Not starting watchdog@f0d0
581 05:20:32.194910 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 05:20:32.207462 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 05:20:32.212419 ** Bad device specification mmc 0 **
584 05:20:32.222711 Card did not respond to voltage select! : -110
585 05:20:32.230507 ** Bad device specification mmc 0 **
586 05:20:32.231051 Couldn't find partition mmc 0
587 05:20:32.238799 Card did not respond to voltage select! : -110
588 05:20:32.244260 ** Bad device specification mmc 0 **
589 05:20:32.244837 Couldn't find partition mmc 0
590 05:20:32.249360 Error: could not access storage.
591 05:20:32.591889 Net: eth0: ethernet@ff3f0000
592 05:20:32.592553 starting USB...
593 05:20:32.843645 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 05:20:32.844272 Starting the controller
595 05:20:32.850641 USB XHCI 1.10
596 05:20:34.560756 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 05:20:34.561387 bl2_stage_init 0x01
598 05:20:34.561816 bl2_stage_init 0x81
599 05:20:34.566195 hw id: 0x0000 - pwm id 0x01
600 05:20:34.566708 bl2_stage_init 0xc1
601 05:20:34.567129 bl2_stage_init 0x02
602 05:20:34.567531
603 05:20:34.571847 L0:00000000
604 05:20:34.572370 L1:20000703
605 05:20:34.572783 L2:00008067
606 05:20:34.573185 L3:14000000
607 05:20:34.574747 B2:00402000
608 05:20:34.575222 B1:e0f83180
609 05:20:34.575644
610 05:20:34.576099 TE: 58167
611 05:20:34.576509
612 05:20:34.585815 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 05:20:34.586319
614 05:20:34.586737 Board ID = 1
615 05:20:34.587139 Set A53 clk to 24M
616 05:20:34.587542 Set A73 clk to 24M
617 05:20:34.591470 Set clk81 to 24M
618 05:20:34.591940 A53 clk: 1200 MHz
619 05:20:34.592390 A73 clk: 1200 MHz
620 05:20:34.596998 CLK81: 166.6M
621 05:20:34.597461 smccc: 00012abe
622 05:20:34.602685 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 05:20:34.603156 board id: 1
624 05:20:34.611288 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 05:20:34.621957 fw parse done
626 05:20:34.627888 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 05:20:34.670414 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 05:20:34.681488 PIEI prepare done
629 05:20:34.681961 fastboot data load
630 05:20:34.682374 fastboot data verify
631 05:20:34.687018 verify result: 266
632 05:20:34.692589 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 05:20:34.693061 LPDDR4 probe
634 05:20:34.693468 ddr clk to 1584MHz
635 05:20:34.700527 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 05:20:34.737811
637 05:20:34.738322 dmc_version 0001
638 05:20:34.744525 Check phy result
639 05:20:34.750475 INFO : End of CA training
640 05:20:34.750936 INFO : End of initialization
641 05:20:34.756029 INFO : Training has run successfully!
642 05:20:34.756492 Check phy result
643 05:20:34.761528 INFO : End of initialization
644 05:20:34.761987 INFO : End of read enable training
645 05:20:34.767168 INFO : End of fine write leveling
646 05:20:34.772789 INFO : End of Write leveling coarse delay
647 05:20:34.773247 INFO : Training has run successfully!
648 05:20:34.773655 Check phy result
649 05:20:34.778487 INFO : End of initialization
650 05:20:34.778943 INFO : End of read dq deskew training
651 05:20:34.783894 INFO : End of MPR read delay center optimization
652 05:20:34.789490 INFO : End of write delay center optimization
653 05:20:34.795099 INFO : End of read delay center optimization
654 05:20:34.795555 INFO : End of max read latency training
655 05:20:34.800704 INFO : Training has run successfully!
656 05:20:34.801162 1D training succeed
657 05:20:34.809828 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 05:20:34.857481 Check phy result
659 05:20:34.857966 INFO : End of initialization
660 05:20:34.879233 INFO : End of 2D read delay Voltage center optimization
661 05:20:34.899433 INFO : End of 2D read delay Voltage center optimization
662 05:20:34.951481 INFO : End of 2D write delay Voltage center optimization
663 05:20:35.000892 INFO : End of 2D write delay Voltage center optimization
664 05:20:35.006459 INFO : Training has run successfully!
665 05:20:35.006928
666 05:20:35.007343 channel==0
667 05:20:35.012070 RxClkDly_Margin_A0==88 ps 9
668 05:20:35.012540 TxDqDly_Margin_A0==98 ps 10
669 05:20:35.017686 RxClkDly_Margin_A1==88 ps 9
670 05:20:35.018168 TxDqDly_Margin_A1==98 ps 10
671 05:20:35.018587 TrainedVREFDQ_A0==74
672 05:20:35.023271 TrainedVREFDQ_A1==74
673 05:20:35.023739 VrefDac_Margin_A0==24
674 05:20:35.024184 DeviceVref_Margin_A0==40
675 05:20:35.028865 VrefDac_Margin_A1==25
676 05:20:35.029326 DeviceVref_Margin_A1==40
677 05:20:35.029733
678 05:20:35.030137
679 05:20:35.034449 channel==1
680 05:20:35.034904 RxClkDly_Margin_A0==98 ps 10
681 05:20:35.035312 TxDqDly_Margin_A0==98 ps 10
682 05:20:35.039883 RxClkDly_Margin_A1==88 ps 9
683 05:20:35.040169 TxDqDly_Margin_A1==88 ps 9
684 05:20:35.045653 TrainedVREFDQ_A0==77
685 05:20:35.046134 TrainedVREFDQ_A1==77
686 05:20:35.046567 VrefDac_Margin_A0==22
687 05:20:35.051267 DeviceVref_Margin_A0==37
688 05:20:35.051724 VrefDac_Margin_A1==24
689 05:20:35.056842 DeviceVref_Margin_A1==37
690 05:20:35.057302
691 05:20:35.057709 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 05:20:35.058105
693 05:20:35.090486 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
694 05:20:35.091004 2D training succeed
695 05:20:35.096060 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 05:20:35.101645 auto size-- 65535DDR cs0 size: 2048MB
697 05:20:35.102107 DDR cs1 size: 2048MB
698 05:20:35.107257 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 05:20:35.107736 cs0 DataBus test pass
700 05:20:35.112857 cs1 DataBus test pass
701 05:20:35.113317 cs0 AddrBus test pass
702 05:20:35.113724 cs1 AddrBus test pass
703 05:20:35.114126
704 05:20:35.118446 100bdlr_step_size ps== 420
705 05:20:35.118913 result report
706 05:20:35.124062 boot times 0Enable ddr reg access
707 05:20:35.129467 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 05:20:35.142843 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 05:20:35.716521 0.0;M3 CHK:0;cm4_sp_mode 0
710 05:20:35.716931 MVN_1=0x00000000
711 05:20:35.721986 MVN_2=0x00000000
712 05:20:35.727935 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 05:20:35.728801 OPS=0x10
714 05:20:35.729013 ring efuse init
715 05:20:35.729214 chipver efuse init
716 05:20:35.733321 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 05:20:35.738845 [0.018961 Inits done]
718 05:20:35.739240 secure task start!
719 05:20:35.739585 high task start!
720 05:20:35.743502 low task start!
721 05:20:35.744078 run into bl31
722 05:20:35.750174 NOTICE: BL31: v1.3(release):4fc40b1
723 05:20:35.757908 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 05:20:35.758218 NOTICE: BL31: G12A normal boot!
725 05:20:35.783327 NOTICE: BL31: BL33 decompress pass
726 05:20:35.788990 ERROR: Error initializing runtime service opteed_fast
727 05:20:37.021943
728 05:20:37.022342
729 05:20:37.030332 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 05:20:37.030696
731 05:20:37.030964 Model: Libre Computer AML-A311D-CC Alta
732 05:20:37.238722 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 05:20:37.262097 DRAM: 2 GiB (effective 3.8 GiB)
734 05:20:37.405087 Core: 408 devices, 31 uclasses, devicetree: separate
735 05:20:37.410963 WDT: Not starting watchdog@f0d0
736 05:20:37.443195 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 05:20:37.455680 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 05:20:37.460680 ** Bad device specification mmc 0 **
739 05:20:37.471022 Card did not respond to voltage select! : -110
740 05:20:37.478664 ** Bad device specification mmc 0 **
741 05:20:37.479016 Couldn't find partition mmc 0
742 05:20:37.486997 Card did not respond to voltage select! : -110
743 05:20:37.492520 ** Bad device specification mmc 0 **
744 05:20:37.493000 Couldn't find partition mmc 0
745 05:20:37.497628 Error: could not access storage.
746 05:20:37.840086 Net: eth0: ethernet@ff3f0000
747 05:20:37.840487 starting USB...
748 05:20:38.091799 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 05:20:38.092387 Starting the controller
750 05:20:38.098816 USB XHCI 1.10
751 05:20:40.261696 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 05:20:40.262345 bl2_stage_init 0x01
753 05:20:40.262806 bl2_stage_init 0x81
754 05:20:40.267300 hw id: 0x0000 - pwm id 0x01
755 05:20:40.267863 bl2_stage_init 0xc1
756 05:20:40.268358 bl2_stage_init 0x02
757 05:20:40.268787
758 05:20:40.272953 L0:00000000
759 05:20:40.273506 L1:20000703
760 05:20:40.273951 L2:00008067
761 05:20:40.274372 L3:14000000
762 05:20:40.278540 B2:00402000
763 05:20:40.279078 B1:e0f83180
764 05:20:40.279506
765 05:20:40.279925 TE: 58124
766 05:20:40.280385
767 05:20:40.284220 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 05:20:40.284767
769 05:20:40.285256 Board ID = 1
770 05:20:40.289812 Set A53 clk to 24M
771 05:20:40.290366 Set A73 clk to 24M
772 05:20:40.290795 Set clk81 to 24M
773 05:20:40.295489 A53 clk: 1200 MHz
774 05:20:40.296056 A73 clk: 1200 MHz
775 05:20:40.296501 CLK81: 166.6M
776 05:20:40.296960 smccc: 00012a92
777 05:20:40.300946 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 05:20:40.306593 board id: 1
779 05:20:40.312128 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 05:20:40.323046 fw parse done
781 05:20:40.328251 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 05:20:40.371004 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 05:20:40.382419 PIEI prepare done
784 05:20:40.382994 fastboot data load
785 05:20:40.383448 fastboot data verify
786 05:20:40.388094 verify result: 266
787 05:20:40.393654 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 05:20:40.394205 LPDDR4 probe
789 05:20:40.394634 ddr clk to 1584MHz
790 05:20:40.400778 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 05:20:40.438583
792 05:20:40.439155 dmc_version 0001
793 05:20:40.445618 Check phy result
794 05:20:40.451474 INFO : End of CA training
795 05:20:40.452050 INFO : End of initialization
796 05:20:40.457087 INFO : Training has run successfully!
797 05:20:40.457612 Check phy result
798 05:20:40.462686 INFO : End of initialization
799 05:20:40.463208 INFO : End of read enable training
800 05:20:40.468276 INFO : End of fine write leveling
801 05:20:40.473829 INFO : End of Write leveling coarse delay
802 05:20:40.474329 INFO : Training has run successfully!
803 05:20:40.474748 Check phy result
804 05:20:40.479461 INFO : End of initialization
805 05:20:40.479970 INFO : End of read dq deskew training
806 05:20:40.485059 INFO : End of MPR read delay center optimization
807 05:20:40.490633 INFO : End of write delay center optimization
808 05:20:40.496235 INFO : End of read delay center optimization
809 05:20:40.496742 INFO : End of max read latency training
810 05:20:40.501843 INFO : Training has run successfully!
811 05:20:40.502346 1D training succeed
812 05:20:40.510154 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 05:20:40.558272 Check phy result
814 05:20:40.558810 INFO : End of initialization
815 05:20:40.579640 INFO : End of 2D read delay Voltage center optimization
816 05:20:40.599686 INFO : End of 2D read delay Voltage center optimization
817 05:20:40.652387 INFO : End of 2D write delay Voltage center optimization
818 05:20:40.701522 INFO : End of 2D write delay Voltage center optimization
819 05:20:40.707085 INFO : Training has run successfully!
820 05:20:40.707606
821 05:20:40.708083 channel==0
822 05:20:40.712684 RxClkDly_Margin_A0==88 ps 9
823 05:20:40.713221 TxDqDly_Margin_A0==98 ps 10
824 05:20:40.718251 RxClkDly_Margin_A1==88 ps 9
825 05:20:40.718756 TxDqDly_Margin_A1==98 ps 10
826 05:20:40.719193 TrainedVREFDQ_A0==74
827 05:20:40.724133 TrainedVREFDQ_A1==76
828 05:20:40.724656 VrefDac_Margin_A0==25
829 05:20:40.725054 DeviceVref_Margin_A0==40
830 05:20:40.730384 VrefDac_Margin_A1==25
831 05:20:40.730922 DeviceVref_Margin_A1==38
832 05:20:40.731496
833 05:20:40.731954
834 05:20:40.735036 channel==1
835 05:20:40.735517 RxClkDly_Margin_A0==98 ps 10
836 05:20:40.735914 TxDqDly_Margin_A0==98 ps 10
837 05:20:40.740618 RxClkDly_Margin_A1==98 ps 10
838 05:20:40.741097 TxDqDly_Margin_A1==88 ps 9
839 05:20:40.746200 TrainedVREFDQ_A0==77
840 05:20:40.746684 TrainedVREFDQ_A1==77
841 05:20:40.747082 VrefDac_Margin_A0==22
842 05:20:40.751816 DeviceVref_Margin_A0==37
843 05:20:40.752337 VrefDac_Margin_A1==22
844 05:20:40.757423 DeviceVref_Margin_A1==37
845 05:20:40.757895
846 05:20:40.758287 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 05:20:40.763034
848 05:20:40.791000 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
849 05:20:40.791580 2D training succeed
850 05:20:40.796654 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 05:20:40.802236 auto size-- 65535DDR cs0 size: 2048MB
852 05:20:40.802723 DDR cs1 size: 2048MB
853 05:20:40.807851 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 05:20:40.808386 cs0 DataBus test pass
855 05:20:40.813438 cs1 DataBus test pass
856 05:20:40.813923 cs0 AddrBus test pass
857 05:20:40.814321 cs1 AddrBus test pass
858 05:20:40.814707
859 05:20:40.819054 100bdlr_step_size ps== 420
860 05:20:40.819548 result report
861 05:20:40.824637 boot times 0Enable ddr reg access
862 05:20:40.829514 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 05:20:40.843246 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 05:20:41.415644 0.0;M3 CHK:0;cm4_sp_mode 0
865 05:20:41.416124 MVN_1=0x00000000
866 05:20:41.421137 MVN_2=0x00000000
867 05:20:41.426902 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 05:20:41.427692 OPS=0x10
869 05:20:41.427912 ring efuse init
870 05:20:41.428216 chipver efuse init
871 05:20:41.432497 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 05:20:41.437953 [0.018961 Inits done]
873 05:20:41.438273 secure task start!
874 05:20:41.438483 high task start!
875 05:20:41.441891 low task start!
876 05:20:41.442338 run into bl31
877 05:20:41.449132 NOTICE: BL31: v1.3(release):4fc40b1
878 05:20:41.457141 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 05:20:41.457809 NOTICE: BL31: G12A normal boot!
880 05:20:41.482383 NOTICE: BL31: BL33 decompress pass
881 05:20:41.487359 ERROR: Error initializing runtime service opteed_fast
882 05:20:42.720982
883 05:20:42.721599
884 05:20:42.728749 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 05:20:42.729237
886 05:20:42.729667 Model: Libre Computer AML-A311D-CC Alta
887 05:20:42.937850 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 05:20:42.961286 DRAM: 2 GiB (effective 3.8 GiB)
889 05:20:43.104265 Core: 408 devices, 31 uclasses, devicetree: separate
890 05:20:43.110118 WDT: Not starting watchdog@f0d0
891 05:20:43.142366 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 05:20:43.154733 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 05:20:43.159769 ** Bad device specification mmc 0 **
894 05:20:43.170103 Card did not respond to voltage select! : -110
895 05:20:43.177766 ** Bad device specification mmc 0 **
896 05:20:43.178262 Couldn't find partition mmc 0
897 05:20:43.186103 Card did not respond to voltage select! : -110
898 05:20:43.191632 ** Bad device specification mmc 0 **
899 05:20:43.192162 Couldn't find partition mmc 0
900 05:20:43.196675 Error: could not access storage.
901 05:20:43.538998 Net: eth0: ethernet@ff3f0000
902 05:20:43.539404 starting USB...
903 05:20:43.790847 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 05:20:43.791408 Starting the controller
905 05:20:43.797678 USB XHCI 1.10
906 05:20:45.352029 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 05:20:45.360411 scanning usb for storage devices... 0 Storage Device(s) found
909 05:20:45.411788 Hit any key to stop autoboot: 1
910 05:20:45.412800 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 05:20:45.413177 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 05:20:45.413466 Setting prompt string to ['=>']
913 05:20:45.413751 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 05:20:45.427768 0
915 05:20:45.428525 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 05:20:45.428856 Sending with 10 millisecond of delay
918 05:20:46.563867 => setenv autoload no
919 05:20:46.574742 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 05:20:46.580040 setenv autoload no
921 05:20:46.580825 Sending with 10 millisecond of delay
923 05:20:48.377922 => setenv initrd_high 0xffffffff
924 05:20:48.388749 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 05:20:48.389677 setenv initrd_high 0xffffffff
926 05:20:48.390670 Sending with 10 millisecond of delay
928 05:20:50.007753 => setenv fdt_high 0xffffffff
929 05:20:50.018598 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
930 05:20:50.019485 setenv fdt_high 0xffffffff
931 05:20:50.020277 Sending with 10 millisecond of delay
933 05:20:50.312323 => dhcp
934 05:20:50.323123 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 05:20:50.324040 dhcp
936 05:20:50.324541 Speed: 1000, full duplex
937 05:20:50.324998 BOOTP broadcast 1
938 05:20:50.571670 BOOTP broadcast 2
939 05:20:50.664054 DHCP client bound to address 192.168.6.33 (339 ms)
940 05:20:50.664574 Sending with 10 millisecond of delay
942 05:20:52.340761 => setenv serverip 192.168.6.2
943 05:20:52.351624 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 05:20:52.352612 setenv serverip 192.168.6.2
945 05:20:52.353349 Sending with 10 millisecond of delay
947 05:20:56.082154 => tftpboot 0x01080000 681648/tftp-deploy-y2bz_llu/kernel/uImage
948 05:20:56.092698 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 05:20:56.093243 tftpboot 0x01080000 681648/tftp-deploy-y2bz_llu/kernel/uImage
950 05:20:56.093468 Speed: 1000, full duplex
951 05:20:56.093669 Using ethernet@ff3f0000 device
952 05:20:56.095543 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
953 05:20:56.100982 Filename '681648/tftp-deploy-y2bz_llu/kernel/uImage'.
954 05:20:56.104835 Load address: 0x1080000
955 05:20:58.580783 Loading: *################################################## 37.2 MiB
956 05:20:58.581306 15 MiB/s
957 05:20:58.581635 done
958 05:20:58.584608 Bytes transferred = 39021120 (2536a40 hex)
959 05:20:58.585250 Sending with 10 millisecond of delay
961 05:21:03.272480 => tftpboot 0x08000000 681648/tftp-deploy-y2bz_llu/ramdisk/ramdisk.cpio.gz.uboot
962 05:21:03.283211 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
963 05:21:03.284045 tftpboot 0x08000000 681648/tftp-deploy-y2bz_llu/ramdisk/ramdisk.cpio.gz.uboot
964 05:21:03.284517 Speed: 1000, full duplex
965 05:21:03.285006 Using ethernet@ff3f0000 device
966 05:21:03.290117 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
967 05:21:03.297763 Filename '681648/tftp-deploy-y2bz_llu/ramdisk/ramdisk.cpio.gz.uboot'.
968 05:21:03.298214 Load address: 0x8000000
969 05:21:07.602778 Loading: *########################## UDP wrong checksum 00000007 000036b1
970 05:21:10.280074 T ####################### UDP wrong checksum 00000005 0000f520
971 05:21:15.282056 T UDP wrong checksum 00000005 0000f520
972 05:21:25.284173 T T UDP wrong checksum 00000005 0000f520
973 05:21:45.287912 T T T T UDP wrong checksum 00000005 0000f520
974 05:21:46.738418 UDP wrong checksum 000000ff 0000a156
975 05:21:46.765114 UDP wrong checksum 000000ff 00003149
976 05:22:00.291284 T T
977 05:22:00.292128 Retry count exceeded; starting again
979 05:22:00.294142 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
982 05:22:00.296608 end: 2.4 uboot-commands (duration 00:01:47) [common]
984 05:22:00.298292 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
986 05:22:00.299518 end: 2 uboot-action (duration 00:01:47) [common]
988 05:22:00.301609 Cleaning after the job
989 05:22:00.302322 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/ramdisk
990 05:22:00.303711 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/kernel
991 05:22:00.348885 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/dtb
992 05:22:00.349847 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681648/tftp-deploy-y2bz_llu/modules
993 05:22:00.373008 start: 4.1 power-off (timeout 00:00:30) [common]
994 05:22:00.373785 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
995 05:22:00.407967 >> OK - accepted request
996 05:22:00.409903 Returned 0 in 0 seconds
997 05:22:00.511414 end: 4.1 power-off (duration 00:00:00) [common]
999 05:22:00.512735 start: 4.2 read-feedback (timeout 00:10:00) [common]
1000 05:22:00.513751 Listened to connection for namespace 'common' for up to 1s
1001 05:22:01.514701 Finalising connection for namespace 'common'
1002 05:22:01.515626 Disconnecting from shell: Finalise
1003 05:22:01.516435 =>
1004 05:22:01.617731 end: 4.2 read-feedback (duration 00:00:01) [common]
1005 05:22:01.618665 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681648
1006 05:22:01.937187 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681648
1007 05:22:01.937825 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.