Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:50:14.020430 lava-dispatcher, installed at version: 2024.01
2 04:50:14.021287 start: 0 validate
3 04:50:14.021799 Start time: 2024-08-31 04:50:14.021765+00:00 (UTC)
4 04:50:14.022382 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:50:14.022955 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 04:50:14.060128 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:50:14.060720 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 04:50:14.093343 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:50:14.093977 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:50:34.226629 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:50:34.227147 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 04:50:38.306557 validate duration: 24.28
14 04:50:38.307398 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:50:38.307735 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:50:38.308046 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:50:38.308638 Not decompressing ramdisk as can be used compressed.
18 04:50:38.309081 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 04:50:38.309315 saving as /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/ramdisk/rootfs.cpio.gz
20 04:50:38.309565 total size: 8181887 (7 MB)
21 04:50:38.342686 progress 0 % (0 MB)
22 04:50:38.353391 progress 5 % (0 MB)
23 04:50:38.363767 progress 10 % (0 MB)
24 04:50:38.371598 progress 15 % (1 MB)
25 04:50:38.377032 progress 20 % (1 MB)
26 04:50:38.382817 progress 25 % (1 MB)
27 04:50:38.388160 progress 30 % (2 MB)
28 04:50:38.393957 progress 35 % (2 MB)
29 04:50:38.399219 progress 40 % (3 MB)
30 04:50:38.404900 progress 45 % (3 MB)
31 04:50:38.410136 progress 50 % (3 MB)
32 04:50:38.415805 progress 55 % (4 MB)
33 04:50:38.421254 progress 60 % (4 MB)
34 04:50:38.426883 progress 65 % (5 MB)
35 04:50:38.432125 progress 70 % (5 MB)
36 04:50:38.437785 progress 75 % (5 MB)
37 04:50:38.443027 progress 80 % (6 MB)
38 04:50:38.448617 progress 85 % (6 MB)
39 04:50:38.453871 progress 90 % (7 MB)
40 04:50:38.459416 progress 95 % (7 MB)
41 04:50:38.464312 progress 100 % (7 MB)
42 04:50:38.464988 7 MB downloaded in 0.16 s (50.21 MB/s)
43 04:50:38.465540 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:50:38.466437 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:50:38.466725 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:50:38.466993 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:50:38.467467 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+debug/gcc-12/kernel/Image
49 04:50:38.467709 saving as /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/kernel/Image
50 04:50:38.467917 total size: 167969280 (160 MB)
51 04:50:38.468152 No compression specified
52 04:50:38.506329 progress 0 % (0 MB)
53 04:50:38.608487 progress 5 % (8 MB)
54 04:50:38.714473 progress 10 % (16 MB)
55 04:50:38.824041 progress 15 % (24 MB)
56 04:50:38.932609 progress 20 % (32 MB)
57 04:50:39.045489 progress 25 % (40 MB)
58 04:50:39.149565 progress 30 % (48 MB)
59 04:50:39.251820 progress 35 % (56 MB)
60 04:50:39.353878 progress 40 % (64 MB)
61 04:50:39.455882 progress 45 % (72 MB)
62 04:50:39.558271 progress 50 % (80 MB)
63 04:50:39.660368 progress 55 % (88 MB)
64 04:50:39.764626 progress 60 % (96 MB)
65 04:50:39.872282 progress 65 % (104 MB)
66 04:50:39.980765 progress 70 % (112 MB)
67 04:50:40.088120 progress 75 % (120 MB)
68 04:50:40.195848 progress 80 % (128 MB)
69 04:50:40.303379 progress 85 % (136 MB)
70 04:50:40.409940 progress 90 % (144 MB)
71 04:50:40.520224 progress 95 % (152 MB)
72 04:50:40.626981 progress 100 % (160 MB)
73 04:50:40.627559 160 MB downloaded in 2.16 s (74.17 MB/s)
74 04:50:40.628192 end: 1.2.1 http-download (duration 00:00:02) [common]
76 04:50:40.629129 end: 1.2 download-retry (duration 00:00:02) [common]
77 04:50:40.629440 start: 1.3 download-retry (timeout 00:09:58) [common]
78 04:50:40.629741 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 04:50:40.630251 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 04:50:40.630545 saving as /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/dtb/meson-g12b-a311d-libretech-cc.dtb
81 04:50:40.630765 total size: 54667 (0 MB)
82 04:50:40.630990 No compression specified
83 04:50:40.671863 progress 59 % (0 MB)
84 04:50:40.672759 progress 100 % (0 MB)
85 04:50:40.673363 0 MB downloaded in 0.04 s (1.22 MB/s)
86 04:50:40.673911 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:50:40.674781 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:50:40.675079 start: 1.4 download-retry (timeout 00:09:58) [common]
90 04:50:40.675370 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 04:50:40.675868 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 04:50:40.676175 saving as /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/modules/modules.tar
93 04:50:40.676396 total size: 27403736 (26 MB)
94 04:50:40.676614 Using unxz to decompress xz
95 04:50:40.727974 progress 0 % (0 MB)
96 04:50:40.985780 progress 5 % (1 MB)
97 04:50:41.228732 progress 10 % (2 MB)
98 04:50:41.441357 progress 15 % (3 MB)
99 04:50:41.664371 progress 20 % (5 MB)
100 04:50:41.877163 progress 25 % (6 MB)
101 04:50:42.094065 progress 30 % (7 MB)
102 04:50:42.304248 progress 35 % (9 MB)
103 04:50:42.509433 progress 40 % (10 MB)
104 04:50:42.720241 progress 45 % (11 MB)
105 04:50:42.931567 progress 50 % (13 MB)
106 04:50:43.124547 progress 55 % (14 MB)
107 04:50:43.337488 progress 60 % (15 MB)
108 04:50:43.559828 progress 65 % (17 MB)
109 04:50:43.770155 progress 70 % (18 MB)
110 04:50:44.010764 progress 75 % (19 MB)
111 04:50:44.244665 progress 80 % (20 MB)
112 04:50:44.443956 progress 85 % (22 MB)
113 04:50:44.664111 progress 90 % (23 MB)
114 04:50:44.866649 progress 95 % (24 MB)
115 04:50:45.090408 progress 100 % (26 MB)
116 04:50:45.100696 26 MB downloaded in 4.42 s (5.91 MB/s)
117 04:50:45.101414 end: 1.4.1 http-download (duration 00:00:04) [common]
119 04:50:45.102308 end: 1.4 download-retry (duration 00:00:04) [common]
120 04:50:45.102600 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 04:50:45.102882 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 04:50:45.103148 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:50:45.103417 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 04:50:45.104100 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5
125 04:50:45.104646 makedir: /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin
126 04:50:45.105104 makedir: /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/tests
127 04:50:45.105475 makedir: /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/results
128 04:50:45.105865 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-add-keys
129 04:50:45.106510 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-add-sources
130 04:50:45.107176 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-background-process-start
131 04:50:45.107835 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-background-process-stop
132 04:50:45.108588 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-common-functions
133 04:50:45.109246 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-echo-ipv4
134 04:50:45.109852 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-install-packages
135 04:50:45.110446 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-installed-packages
136 04:50:45.111022 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-os-build
137 04:50:45.111608 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-probe-channel
138 04:50:45.112234 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-probe-ip
139 04:50:45.112871 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-target-ip
140 04:50:45.113449 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-target-mac
141 04:50:45.114002 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-target-storage
142 04:50:45.114600 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-test-case
143 04:50:45.115151 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-test-event
144 04:50:45.115784 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-test-feedback
145 04:50:45.116378 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-test-raise
146 04:50:45.116918 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-test-reference
147 04:50:45.117523 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-test-runner
148 04:50:45.118155 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-test-set
149 04:50:45.118738 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-test-shell
150 04:50:45.119397 Updating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-install-packages (oe)
151 04:50:45.120104 Updating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/bin/lava-installed-packages (oe)
152 04:50:45.120647 Creating /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/environment
153 04:50:45.121176 LAVA metadata
154 04:50:45.121476 - LAVA_JOB_ID=681354
155 04:50:45.121708 - LAVA_DISPATCHER_IP=192.168.6.2
156 04:50:45.122114 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 04:50:45.123386 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 04:50:45.123805 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 04:50:45.124063 skipped lava-vland-overlay
160 04:50:45.124341 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 04:50:45.124617 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 04:50:45.124863 skipped lava-multinode-overlay
163 04:50:45.125130 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 04:50:45.125410 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 04:50:45.125691 Loading test definitions
166 04:50:45.126041 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 04:50:45.126339 Using /lava-681354 at stage 0
168 04:50:45.127658 uuid=681354_1.5.2.4.1 testdef=None
169 04:50:45.128035 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 04:50:45.128338 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 04:50:45.130372 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 04:50:45.131316 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 04:50:45.134047 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 04:50:45.135007 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 04:50:45.137669 runner path: /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/0/tests/0_dmesg test_uuid 681354_1.5.2.4.1
178 04:50:45.138410 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 04:50:45.139250 Creating lava-test-runner.conf files
181 04:50:45.139468 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681354/lava-overlay-wl15fip5/lava-681354/0 for stage 0
182 04:50:45.139854 - 0_dmesg
183 04:50:45.140306 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 04:50:45.140615 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 04:50:45.167370 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 04:50:45.167850 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 04:50:45.168163 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 04:50:45.168451 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 04:50:45.168740 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 04:50:46.164910 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 04:50:46.165384 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 04:50:46.165632 extracting modules file /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681354/extract-overlay-ramdisk-z4eaxmtp/ramdisk
193 04:50:47.893695 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 04:50:47.894185 start: 1.5.5 apply-overlay-tftp (timeout 00:09:50) [common]
195 04:50:47.894466 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681354/compress-overlay-uaqanwgv/overlay-1.5.2.5.tar.gz to ramdisk
196 04:50:47.894681 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681354/compress-overlay-uaqanwgv/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681354/extract-overlay-ramdisk-z4eaxmtp/ramdisk
197 04:50:47.928162 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 04:50:47.928707 start: 1.5.6 prepare-kernel (timeout 00:09:50) [common]
199 04:50:47.929076 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:50) [common]
200 04:50:47.929373 Converting downloaded kernel to a uImage
201 04:50:47.929745 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/kernel/Image /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/kernel/uImage
202 04:50:49.594969 output: Image Name:
203 04:50:49.595400 output: Created: Sat Aug 31 04:50:47 2024
204 04:50:49.595612 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 04:50:49.595818 output: Data Size: 167969280 Bytes = 164032.50 KiB = 160.19 MiB
206 04:50:49.596064 output: Load Address: 01080000
207 04:50:49.596273 output: Entry Point: 01080000
208 04:50:49.596469 output:
209 04:50:49.596807 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 04:50:49.597084 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 04:50:49.597358 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 04:50:49.597615 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 04:50:49.597878 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 04:50:49.598134 Building ramdisk /var/lib/lava/dispatcher/tmp/681354/extract-overlay-ramdisk-z4eaxmtp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681354/extract-overlay-ramdisk-z4eaxmtp/ramdisk
215 04:50:56.494050 >> 436239 blocks
216 04:51:14.996885 Adding RAMdisk u-boot header.
217 04:51:14.997332 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681354/extract-overlay-ramdisk-z4eaxmtp/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681354/extract-overlay-ramdisk-z4eaxmtp/ramdisk.cpio.gz.uboot
218 04:51:15.544973 output: Image Name:
219 04:51:15.545398 output: Created: Sat Aug 31 04:51:15 2024
220 04:51:15.545608 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 04:51:15.545814 output: Data Size: 53174704 Bytes = 51928.42 KiB = 50.71 MiB
222 04:51:15.546015 output: Load Address: 00000000
223 04:51:15.546214 output: Entry Point: 00000000
224 04:51:15.546409 output:
225 04:51:15.546991 rename /var/lib/lava/dispatcher/tmp/681354/extract-overlay-ramdisk-z4eaxmtp/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/ramdisk/ramdisk.cpio.gz.uboot
226 04:51:15.547412 end: 1.5.8 compress-ramdisk (duration 00:00:26) [common]
227 04:51:15.547697 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
228 04:51:15.547973 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:23) [common]
229 04:51:15.548470 No LXC device requested
230 04:51:15.548973 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 04:51:15.549479 start: 1.7 deploy-device-env (timeout 00:09:23) [common]
232 04:51:15.549970 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 04:51:15.550377 Checking files for TFTP limit of 4294967296 bytes.
234 04:51:15.553069 end: 1 tftp-deploy (duration 00:00:37) [common]
235 04:51:15.553672 start: 2 uboot-action (timeout 00:05:00) [common]
236 04:51:15.554200 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 04:51:15.554695 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 04:51:15.555191 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 04:51:15.555721 Using kernel file from prepare-kernel: 681354/tftp-deploy-gs3435u8/kernel/uImage
240 04:51:15.556379 substitutions:
241 04:51:15.556793 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 04:51:15.557196 - {DTB_ADDR}: 0x01070000
243 04:51:15.557593 - {DTB}: 681354/tftp-deploy-gs3435u8/dtb/meson-g12b-a311d-libretech-cc.dtb
244 04:51:15.557993 - {INITRD}: 681354/tftp-deploy-gs3435u8/ramdisk/ramdisk.cpio.gz.uboot
245 04:51:15.558387 - {KERNEL_ADDR}: 0x01080000
246 04:51:15.558778 - {KERNEL}: 681354/tftp-deploy-gs3435u8/kernel/uImage
247 04:51:15.559173 - {LAVA_MAC}: None
248 04:51:15.559601 - {PRESEED_CONFIG}: None
249 04:51:15.560023 - {PRESEED_LOCAL}: None
250 04:51:15.560422 - {RAMDISK_ADDR}: 0x08000000
251 04:51:15.560811 - {RAMDISK}: 681354/tftp-deploy-gs3435u8/ramdisk/ramdisk.cpio.gz.uboot
252 04:51:15.561206 - {ROOT_PART}: None
253 04:51:15.561598 - {ROOT}: None
254 04:51:15.561988 - {SERVER_IP}: 192.168.6.2
255 04:51:15.562382 - {TEE_ADDR}: 0x83000000
256 04:51:15.562770 - {TEE}: None
257 04:51:15.563158 Parsed boot commands:
258 04:51:15.563537 - setenv autoload no
259 04:51:15.563927 - setenv initrd_high 0xffffffff
260 04:51:15.564347 - setenv fdt_high 0xffffffff
261 04:51:15.564734 - dhcp
262 04:51:15.565121 - setenv serverip 192.168.6.2
263 04:51:15.565507 - tftpboot 0x01080000 681354/tftp-deploy-gs3435u8/kernel/uImage
264 04:51:15.565894 - tftpboot 0x08000000 681354/tftp-deploy-gs3435u8/ramdisk/ramdisk.cpio.gz.uboot
265 04:51:15.566281 - tftpboot 0x01070000 681354/tftp-deploy-gs3435u8/dtb/meson-g12b-a311d-libretech-cc.dtb
266 04:51:15.566718 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 04:51:15.567148 - bootm 0x01080000 0x08000000 0x01070000
268 04:51:15.567680 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 04:51:15.569305 start: 2.3 connect-device (timeout 00:05:00) [common]
271 04:51:15.569794 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 04:51:15.587370 Setting prompt string to ['lava-test: # ']
273 04:51:15.588952 end: 2.3 connect-device (duration 00:00:00) [common]
274 04:51:15.589571 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 04:51:15.590121 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 04:51:15.590678 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 04:51:15.591634 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 04:51:15.626414 >> OK - accepted request
279 04:51:15.628643 Returned 0 in 0 seconds
280 04:51:15.729606 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 04:51:15.731353 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 04:51:15.731917 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 04:51:15.732475 Setting prompt string to ['Hit any key to stop autoboot']
285 04:51:15.732927 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 04:51:15.734510 Trying 192.168.56.21...
287 04:51:15.734982 Connected to conserv1.
288 04:51:15.735398 Escape character is '^]'.
289 04:51:15.735820
290 04:51:15.736300 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 04:51:15.736736
292 04:51:27.428030 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 04:51:27.428646 bl2_stage_init 0x01
294 04:51:27.429068 bl2_stage_init 0x81
295 04:51:27.433667 hw id: 0x0000 - pwm id 0x01
296 04:51:27.434130 bl2_stage_init 0xc1
297 04:51:27.434531 bl2_stage_init 0x02
298 04:51:27.434918
299 04:51:27.439106 L0:00000000
300 04:51:27.439536 L1:20000703
301 04:51:27.439923 L2:00008067
302 04:51:27.440351 L3:14000000
303 04:51:27.444709 B2:00402000
304 04:51:27.445123 B1:e0f83180
305 04:51:27.445510
306 04:51:27.445894 TE: 58167
307 04:51:27.446280
308 04:51:27.450320 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 04:51:27.450736
310 04:51:27.451123 Board ID = 1
311 04:51:27.455859 Set A53 clk to 24M
312 04:51:27.456297 Set A73 clk to 24M
313 04:51:27.456682 Set clk81 to 24M
314 04:51:27.461481 A53 clk: 1200 MHz
315 04:51:27.461890 A73 clk: 1200 MHz
316 04:51:27.462275 CLK81: 166.6M
317 04:51:27.462658 smccc: 00012abe
318 04:51:27.467068 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 04:51:27.472686 board id: 1
320 04:51:27.478557 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 04:51:27.489200 fw parse done
322 04:51:27.495155 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 04:51:27.537792 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 04:51:27.548757 PIEI prepare done
325 04:51:27.549164 fastboot data load
326 04:51:27.549552 fastboot data verify
327 04:51:27.554343 verify result: 266
328 04:51:27.559880 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 04:51:27.560326 LPDDR4 probe
330 04:51:27.560709 ddr clk to 1584MHz
331 04:51:27.567894 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 04:51:27.605168
333 04:51:27.605629 dmc_version 0001
334 04:51:27.611880 Check phy result
335 04:51:27.617678 INFO : End of CA training
336 04:51:27.618103 INFO : End of initialization
337 04:51:27.623346 INFO : Training has run successfully!
338 04:51:27.623760 Check phy result
339 04:51:27.628876 INFO : End of initialization
340 04:51:27.629287 INFO : End of read enable training
341 04:51:27.634468 INFO : End of fine write leveling
342 04:51:27.640113 INFO : End of Write leveling coarse delay
343 04:51:27.640527 INFO : Training has run successfully!
344 04:51:27.640916 Check phy result
345 04:51:27.645743 INFO : End of initialization
346 04:51:27.646157 INFO : End of read dq deskew training
347 04:51:27.651363 INFO : End of MPR read delay center optimization
348 04:51:27.656930 INFO : End of write delay center optimization
349 04:51:27.662504 INFO : End of read delay center optimization
350 04:51:27.662915 INFO : End of max read latency training
351 04:51:27.668085 INFO : Training has run successfully!
352 04:51:27.668508 1D training succeed
353 04:51:27.677294 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 04:51:27.724887 Check phy result
355 04:51:27.725302 INFO : End of initialization
356 04:51:27.747412 INFO : End of 2D read delay Voltage center optimization
357 04:51:27.767628 INFO : End of 2D read delay Voltage center optimization
358 04:51:27.819383 INFO : End of 2D write delay Voltage center optimization
359 04:51:27.868639 INFO : End of 2D write delay Voltage center optimization
360 04:51:27.874170 INFO : Training has run successfully!
361 04:51:27.874584
362 04:51:27.874977 channel==0
363 04:51:27.879750 RxClkDly_Margin_A0==88 ps 9
364 04:51:27.880200 TxDqDly_Margin_A0==98 ps 10
365 04:51:27.885352 RxClkDly_Margin_A1==88 ps 9
366 04:51:27.885760 TxDqDly_Margin_A1==98 ps 10
367 04:51:27.886154 TrainedVREFDQ_A0==74
368 04:51:27.890922 TrainedVREFDQ_A1==74
369 04:51:27.891331 VrefDac_Margin_A0==24
370 04:51:27.891716 DeviceVref_Margin_A0==40
371 04:51:27.896531 VrefDac_Margin_A1==25
372 04:51:27.896938 DeviceVref_Margin_A1==40
373 04:51:27.897330
374 04:51:27.897714
375 04:51:27.902125 channel==1
376 04:51:27.902530 RxClkDly_Margin_A0==98 ps 10
377 04:51:27.902918 TxDqDly_Margin_A0==88 ps 9
378 04:51:27.907735 RxClkDly_Margin_A1==88 ps 9
379 04:51:27.908165 TxDqDly_Margin_A1==88 ps 9
380 04:51:27.913349 TrainedVREFDQ_A0==76
381 04:51:27.913757 TrainedVREFDQ_A1==77
382 04:51:27.914145 VrefDac_Margin_A0==23
383 04:51:27.918927 DeviceVref_Margin_A0==38
384 04:51:27.919327 VrefDac_Margin_A1==24
385 04:51:27.924548 DeviceVref_Margin_A1==37
386 04:51:27.924954
387 04:51:27.925344 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 04:51:27.925731
389 04:51:27.958148 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 04:51:27.958635 2D training succeed
391 04:51:27.963732 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 04:51:27.969357 auto size-- 65535DDR cs0 size: 2048MB
393 04:51:27.969765 DDR cs1 size: 2048MB
394 04:51:27.974937 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 04:51:27.975345 cs0 DataBus test pass
396 04:51:27.980666 cs1 DataBus test pass
397 04:51:27.981087 cs0 AddrBus test pass
398 04:51:27.981476 cs1 AddrBus test pass
399 04:51:27.981858
400 04:51:27.986225 100bdlr_step_size ps== 420
401 04:51:27.986660 result report
402 04:51:27.991845 boot times 0Enable ddr reg access
403 04:51:27.997110 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 04:51:28.010650 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 04:51:28.582649 0.0;M3 CHK:0;cm4_sp_mode 0
406 04:51:28.583232 MVN_1=0x00000000
407 04:51:28.588171 MVN_2=0x00000000
408 04:51:28.593846 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 04:51:28.594284 OPS=0x10
410 04:51:28.594692 ring efuse init
411 04:51:28.595092 chipver efuse init
412 04:51:28.602062 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 04:51:28.602502 [0.018960 Inits done]
414 04:51:28.608756 secure task start!
415 04:51:28.609189 high task start!
416 04:51:28.609589 low task start!
417 04:51:28.609982 run into bl31
418 04:51:28.616284 NOTICE: BL31: v1.3(release):4fc40b1
419 04:51:28.624094 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 04:51:28.624524 NOTICE: BL31: G12A normal boot!
421 04:51:28.649487 NOTICE: BL31: BL33 decompress pass
422 04:51:28.654182 ERROR: Error initializing runtime service opteed_fast
423 04:51:29.888144
424 04:51:29.888789
425 04:51:29.896574 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 04:51:29.897103
427 04:51:29.897567 Model: Libre Computer AML-A311D-CC Alta
428 04:51:30.105208 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 04:51:30.128528 DRAM: 2 GiB (effective 3.8 GiB)
430 04:51:30.271353 Core: 408 devices, 31 uclasses, devicetree: separate
431 04:51:30.277334 WDT: Not starting watchdog@f0d0
432 04:51:30.309419 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 04:51:30.321993 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 04:51:30.326981 ** Bad device specification mmc 0 **
435 04:51:30.337159 Card did not respond to voltage select! : -110
436 04:51:30.344804 ** Bad device specification mmc 0 **
437 04:51:30.345246 Couldn't find partition mmc 0
438 04:51:30.353168 Card did not respond to voltage select! : -110
439 04:51:30.358647 ** Bad device specification mmc 0 **
440 04:51:30.359079 Couldn't find partition mmc 0
441 04:51:30.363752 Error: could not access storage.
442 04:51:31.628439 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 04:51:31.629014 bl2_stage_init 0x01
444 04:51:31.629452 bl2_stage_init 0x81
445 04:51:31.634004 hw id: 0x0000 - pwm id 0x01
446 04:51:31.634467 bl2_stage_init 0xc1
447 04:51:31.634882 bl2_stage_init 0x02
448 04:51:31.635288
449 04:51:31.639593 L0:00000000
450 04:51:31.640078 L1:20000703
451 04:51:31.640496 L2:00008067
452 04:51:31.640894 L3:14000000
453 04:51:31.645161 B2:00402000
454 04:51:31.645620 B1:e0f83180
455 04:51:31.646033
456 04:51:31.646441 TE: 58167
457 04:51:31.646846
458 04:51:31.650741 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 04:51:31.651207
460 04:51:31.651620 Board ID = 1
461 04:51:31.656372 Set A53 clk to 24M
462 04:51:31.656827 Set A73 clk to 24M
463 04:51:31.657240 Set clk81 to 24M
464 04:51:31.662005 A53 clk: 1200 MHz
465 04:51:31.662454 A73 clk: 1200 MHz
466 04:51:31.662865 CLK81: 166.6M
467 04:51:31.663264 smccc: 00012abe
468 04:51:31.667564 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 04:51:31.673161 board id: 1
470 04:51:31.679062 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 04:51:31.689699 fw parse done
472 04:51:31.695639 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 04:51:31.738305 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 04:51:31.749145 PIEI prepare done
475 04:51:31.749587 fastboot data load
476 04:51:31.750002 fastboot data verify
477 04:51:31.754723 verify result: 266
478 04:51:31.760328 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 04:51:31.760774 LPDDR4 probe
480 04:51:31.761183 ddr clk to 1584MHz
481 04:51:31.768304 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 04:51:31.805598
483 04:51:31.806045 dmc_version 0001
484 04:51:31.812221 Check phy result
485 04:51:31.818099 INFO : End of CA training
486 04:51:31.818539 INFO : End of initialization
487 04:51:31.823716 INFO : Training has run successfully!
488 04:51:31.824200 Check phy result
489 04:51:31.829289 INFO : End of initialization
490 04:51:31.829728 INFO : End of read enable training
491 04:51:31.834933 INFO : End of fine write leveling
492 04:51:31.840489 INFO : End of Write leveling coarse delay
493 04:51:31.840928 INFO : Training has run successfully!
494 04:51:31.841337 Check phy result
495 04:51:31.846152 INFO : End of initialization
496 04:51:31.846592 INFO : End of read dq deskew training
497 04:51:31.851708 INFO : End of MPR read delay center optimization
498 04:51:31.857303 INFO : End of write delay center optimization
499 04:51:31.862939 INFO : End of read delay center optimization
500 04:51:31.863384 INFO : End of max read latency training
501 04:51:31.868501 INFO : Training has run successfully!
502 04:51:31.868944 1D training succeed
503 04:51:31.877701 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 04:51:31.925351 Check phy result
505 04:51:31.925871 INFO : End of initialization
506 04:51:31.946959 INFO : End of 2D read delay Voltage center optimization
507 04:51:31.967095 INFO : End of 2D read delay Voltage center optimization
508 04:51:32.018909 INFO : End of 2D write delay Voltage center optimization
509 04:51:32.068234 INFO : End of 2D write delay Voltage center optimization
510 04:51:32.073738 INFO : Training has run successfully!
511 04:51:32.074195
512 04:51:32.074612 channel==0
513 04:51:32.079324 RxClkDly_Margin_A0==88 ps 9
514 04:51:32.079774 TxDqDly_Margin_A0==98 ps 10
515 04:51:32.084975 RxClkDly_Margin_A1==88 ps 9
516 04:51:32.085423 TxDqDly_Margin_A1==98 ps 10
517 04:51:32.085836 TrainedVREFDQ_A0==74
518 04:51:32.090510 TrainedVREFDQ_A1==74
519 04:51:32.090970 VrefDac_Margin_A0==25
520 04:51:32.091382 DeviceVref_Margin_A0==40
521 04:51:32.096148 VrefDac_Margin_A1==25
522 04:51:32.096595 DeviceVref_Margin_A1==40
523 04:51:32.097005
524 04:51:32.097405
525 04:51:32.101714 channel==1
526 04:51:32.102162 RxClkDly_Margin_A0==98 ps 10
527 04:51:32.102577 TxDqDly_Margin_A0==88 ps 9
528 04:51:32.107313 RxClkDly_Margin_A1==98 ps 10
529 04:51:32.107757 TxDqDly_Margin_A1==88 ps 9
530 04:51:32.112952 TrainedVREFDQ_A0==76
531 04:51:32.113397 TrainedVREFDQ_A1==77
532 04:51:32.113807 VrefDac_Margin_A0==22
533 04:51:32.118522 DeviceVref_Margin_A0==38
534 04:51:32.118968 VrefDac_Margin_A1==22
535 04:51:32.124147 DeviceVref_Margin_A1==37
536 04:51:32.124589
537 04:51:32.124992 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 04:51:32.125392
539 04:51:32.157747 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 04:51:32.158259 2D training succeed
541 04:51:32.163295 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 04:51:32.168983 auto size-- 65535DDR cs0 size: 2048MB
543 04:51:32.169440 DDR cs1 size: 2048MB
544 04:51:32.174531 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 04:51:32.174984 cs0 DataBus test pass
546 04:51:32.180124 cs1 DataBus test pass
547 04:51:32.180571 cs0 AddrBus test pass
548 04:51:32.180975 cs1 AddrBus test pass
549 04:51:32.181375
550 04:51:32.185717 100bdlr_step_size ps== 420
551 04:51:32.186169 result report
552 04:51:32.191293 boot times 0Enable ddr reg access
553 04:51:32.196694 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 04:51:32.210175 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 04:51:32.782319 0.0;M3 CHK:0;cm4_sp_mode 0
556 04:51:32.782891 MVN_1=0x00000000
557 04:51:32.787804 MVN_2=0x00000000
558 04:51:32.793559 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 04:51:32.794096 OPS=0x10
560 04:51:32.794557 ring efuse init
561 04:51:32.794946 chipver efuse init
562 04:51:32.801765 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 04:51:32.802272 [0.018961 Inits done]
564 04:51:32.802665 secure task start!
565 04:51:32.809279 high task start!
566 04:51:32.809715 low task start!
567 04:51:32.810101 run into bl31
568 04:51:32.815834 NOTICE: BL31: v1.3(release):4fc40b1
569 04:51:32.823656 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 04:51:32.824118 NOTICE: BL31: G12A normal boot!
571 04:51:32.849140 NOTICE: BL31: BL33 decompress pass
572 04:51:32.854161 ERROR: Error initializing runtime service opteed_fast
573 04:51:34.087647
574 04:51:34.088243
575 04:51:34.095221 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 04:51:34.095700
577 04:51:34.096145 Model: Libre Computer AML-A311D-CC Alta
578 04:51:34.303541 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 04:51:34.326809 DRAM: 2 GiB (effective 3.8 GiB)
580 04:51:34.470865 Core: 408 devices, 31 uclasses, devicetree: separate
581 04:51:34.475743 WDT: Not starting watchdog@f0d0
582 04:51:34.508979 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 04:51:34.521387 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 04:51:34.525725 ** Bad device specification mmc 0 **
585 04:51:34.536681 Card did not respond to voltage select! : -110
586 04:51:34.543504 ** Bad device specification mmc 0 **
587 04:51:34.543975 Couldn't find partition mmc 0
588 04:51:34.552654 Card did not respond to voltage select! : -110
589 04:51:34.558153 ** Bad device specification mmc 0 **
590 04:51:34.558492 Couldn't find partition mmc 0
591 04:51:34.562271 Error: could not access storage.
592 04:51:34.905750 Net: eth0: ethernet@ff3f0000
593 04:51:34.906176 starting USB...
594 04:51:35.157653 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 04:51:35.158322 Starting the controller
596 04:51:35.164240 USB XHCI 1.10
597 04:51:36.878612 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 04:51:36.879052 bl2_stage_init 0x01
599 04:51:36.879330 bl2_stage_init 0x81
600 04:51:36.884103 hw id: 0x0000 - pwm id 0x01
601 04:51:36.884505 bl2_stage_init 0xc1
602 04:51:36.884804 bl2_stage_init 0x02
603 04:51:36.885073
604 04:51:36.889694 L0:00000000
605 04:51:36.890015 L1:20000703
606 04:51:36.890285 L2:00008067
607 04:51:36.890554 L3:14000000
608 04:51:36.895316 B2:00402000
609 04:51:36.895630 B1:e0f83180
610 04:51:36.895898
611 04:51:36.896189 TE: 58124
612 04:51:36.896460
613 04:51:36.900820 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 04:51:36.901154
615 04:51:36.901430 Board ID = 1
616 04:51:36.906479 Set A53 clk to 24M
617 04:51:36.906799 Set A73 clk to 24M
618 04:51:36.907067 Set clk81 to 24M
619 04:51:36.912098 A53 clk: 1200 MHz
620 04:51:36.912419 A73 clk: 1200 MHz
621 04:51:36.912688 CLK81: 166.6M
622 04:51:36.912936 smccc: 00012a92
623 04:51:36.917733 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 04:51:36.923250 board id: 1
625 04:51:36.929217 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 04:51:36.939805 fw parse done
627 04:51:36.945101 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 04:51:36.988632 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 04:51:36.999317 PIEI prepare done
630 04:51:36.999887 fastboot data load
631 04:51:37.000381 fastboot data verify
632 04:51:37.004930 verify result: 266
633 04:51:37.010495 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 04:51:37.010811 LPDDR4 probe
635 04:51:37.011212 ddr clk to 1584MHz
636 04:51:37.018068 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 04:51:37.055790
638 04:51:37.056167 dmc_version 0001
639 04:51:37.062019 Check phy result
640 04:51:37.068317 INFO : End of CA training
641 04:51:37.068645 INFO : End of initialization
642 04:51:37.073949 INFO : Training has run successfully!
643 04:51:37.074425 Check phy result
644 04:51:37.079523 INFO : End of initialization
645 04:51:37.080016 INFO : End of read enable training
646 04:51:37.082894 INFO : End of fine write leveling
647 04:51:37.088458 INFO : End of Write leveling coarse delay
648 04:51:37.094017 INFO : Training has run successfully!
649 04:51:37.094327 Check phy result
650 04:51:37.094743 INFO : End of initialization
651 04:51:37.099613 INFO : End of read dq deskew training
652 04:51:37.103151 INFO : End of MPR read delay center optimization
653 04:51:37.108585 INFO : End of write delay center optimization
654 04:51:37.114196 INFO : End of read delay center optimization
655 04:51:37.114649 INFO : End of max read latency training
656 04:51:37.119706 INFO : Training has run successfully!
657 04:51:37.120054 1D training succeed
658 04:51:37.127651 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 04:51:37.174740 Check phy result
660 04:51:37.175270 INFO : End of initialization
661 04:51:37.197423 INFO : End of 2D read delay Voltage center optimization
662 04:51:37.216634 INFO : End of 2D read delay Voltage center optimization
663 04:51:37.269612 INFO : End of 2D write delay Voltage center optimization
664 04:51:37.319106 INFO : End of 2D write delay Voltage center optimization
665 04:51:37.324634 INFO : Training has run successfully!
666 04:51:37.325202
667 04:51:37.325705 channel==0
668 04:51:37.330265 RxClkDly_Margin_A0==88 ps 9
669 04:51:37.330825 TxDqDly_Margin_A0==98 ps 10
670 04:51:37.333635 RxClkDly_Margin_A1==88 ps 9
671 04:51:37.334182 TxDqDly_Margin_A1==98 ps 10
672 04:51:37.339176 TrainedVREFDQ_A0==74
673 04:51:37.339726 TrainedVREFDQ_A1==74
674 04:51:37.340256 VrefDac_Margin_A0==25
675 04:51:37.344908 DeviceVref_Margin_A0==40
676 04:51:37.345227 VrefDac_Margin_A1==25
677 04:51:37.350384 DeviceVref_Margin_A1==40
678 04:51:37.350827
679 04:51:37.351451
680 04:51:37.352167 channel==1
681 04:51:37.352520 RxClkDly_Margin_A0==98 ps 10
682 04:51:37.355973 TxDqDly_Margin_A0==98 ps 10
683 04:51:37.356320 RxClkDly_Margin_A1==98 ps 10
684 04:51:37.361480 TxDqDly_Margin_A1==88 ps 9
685 04:51:37.361812 TrainedVREFDQ_A0==77
686 04:51:37.362083 TrainedVREFDQ_A1==77
687 04:51:37.367183 VrefDac_Margin_A0==23
688 04:51:37.367638 DeviceVref_Margin_A0==37
689 04:51:37.372668 VrefDac_Margin_A1==22
690 04:51:37.373099 DeviceVref_Margin_A1==37
691 04:51:37.373505
692 04:51:37.378322 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 04:51:37.378771
694 04:51:37.406104 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
695 04:51:37.411713 2D training succeed
696 04:51:37.417324 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 04:51:37.417662 auto size-- 65535DDR cs0 size: 2048MB
698 04:51:37.422986 DDR cs1 size: 2048MB
699 04:51:37.423471 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 04:51:37.428487 cs0 DataBus test pass
701 04:51:37.428816 cs1 DataBus test pass
702 04:51:37.429087 cs0 AddrBus test pass
703 04:51:37.434165 cs1 AddrBus test pass
704 04:51:37.434625
705 04:51:37.435011 100bdlr_step_size ps== 420
706 04:51:37.435421 result report
707 04:51:37.439754 boot times 0Enable ddr reg access
708 04:51:37.446892 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 04:51:37.460097 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 04:51:38.034499 0.0;M3 CHK:0;cm4_sp_mode 0
711 04:51:38.034929 MVN_1=0x00000000
712 04:51:38.040082 MVN_2=0x00000000
713 04:51:38.045860 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 04:51:38.046381 OPS=0x10
715 04:51:38.046788 ring efuse init
716 04:51:38.047181 chipver efuse init
717 04:51:38.051380 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 04:51:38.056924 [0.018961 Inits done]
719 04:51:38.057354 secure task start!
720 04:51:38.057745 high task start!
721 04:51:38.060571 low task start!
722 04:51:38.060998 run into bl31
723 04:51:38.068193 NOTICE: BL31: v1.3(release):4fc40b1
724 04:51:38.075256 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 04:51:38.075688 NOTICE: BL31: G12A normal boot!
726 04:51:38.101538 NOTICE: BL31: BL33 decompress pass
727 04:51:38.106289 ERROR: Error initializing runtime service opteed_fast
728 04:51:39.339863
729 04:51:39.340298
730 04:51:39.347413 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 04:51:39.347668
732 04:51:39.347878 Model: Libre Computer AML-A311D-CC Alta
733 04:51:39.555697 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 04:51:39.579214 DRAM: 2 GiB (effective 3.8 GiB)
735 04:51:39.723160 Core: 408 devices, 31 uclasses, devicetree: separate
736 04:51:39.728089 WDT: Not starting watchdog@f0d0
737 04:51:39.761260 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 04:51:39.773697 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 04:51:39.777701 ** Bad device specification mmc 0 **
740 04:51:39.789095 Card did not respond to voltage select! : -110
741 04:51:39.796560 ** Bad device specification mmc 0 **
742 04:51:39.796830 Couldn't find partition mmc 0
743 04:51:39.805089 Card did not respond to voltage select! : -110
744 04:51:39.810499 ** Bad device specification mmc 0 **
745 04:51:39.810763 Couldn't find partition mmc 0
746 04:51:39.814685 Error: could not access storage.
747 04:51:40.157131 Net: eth0: ethernet@ff3f0000
748 04:51:40.157475 starting USB...
749 04:51:40.409875 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 04:51:40.410221 Starting the controller
751 04:51:40.416780 USB XHCI 1.10
752 04:51:42.580200 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 04:51:42.580793 bl2_stage_init 0x01
754 04:51:42.581218 bl2_stage_init 0x81
755 04:51:42.585693 hw id: 0x0000 - pwm id 0x01
756 04:51:42.586159 bl2_stage_init 0xc1
757 04:51:42.586573 bl2_stage_init 0x02
758 04:51:42.586974
759 04:51:42.591272 L0:00000000
760 04:51:42.591756 L1:20000703
761 04:51:42.592214 L2:00008067
762 04:51:42.592636 L3:14000000
763 04:51:42.594255 B2:00402000
764 04:51:42.594684 B1:e0f83180
765 04:51:42.595087
766 04:51:42.595485 TE: 58167
767 04:51:42.595883
768 04:51:42.605311 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 04:51:42.605805
770 04:51:42.606220 Board ID = 1
771 04:51:42.606620 Set A53 clk to 24M
772 04:51:42.607013 Set A73 clk to 24M
773 04:51:42.611087 Set clk81 to 24M
774 04:51:42.611525 A53 clk: 1200 MHz
775 04:51:42.611926 A73 clk: 1200 MHz
776 04:51:42.616634 CLK81: 166.6M
777 04:51:42.617074 smccc: 00012abe
778 04:51:42.622269 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 04:51:42.622709 board id: 1
780 04:51:42.630514 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 04:51:42.641379 fw parse done
782 04:51:42.647253 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 04:51:42.689876 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 04:51:42.700790 PIEI prepare done
785 04:51:42.701084 fastboot data load
786 04:51:42.701345 fastboot data verify
787 04:51:42.706429 verify result: 266
788 04:51:42.712021 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 04:51:42.712319 LPDDR4 probe
790 04:51:42.712558 ddr clk to 1584MHz
791 04:51:42.719896 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 04:51:42.756363
793 04:51:42.756735 dmc_version 0001
794 04:51:42.763641 Check phy result
795 04:51:42.769874 INFO : End of CA training
796 04:51:42.770210 INFO : End of initialization
797 04:51:42.775505 INFO : Training has run successfully!
798 04:51:42.775942 Check phy result
799 04:51:42.780999 INFO : End of initialization
800 04:51:42.781316 INFO : End of read enable training
801 04:51:42.786951 INFO : End of fine write leveling
802 04:51:42.792269 INFO : End of Write leveling coarse delay
803 04:51:42.792699 INFO : Training has run successfully!
804 04:51:42.793071 Check phy result
805 04:51:42.797808 INFO : End of initialization
806 04:51:42.798124 INFO : End of read dq deskew training
807 04:51:42.803487 INFO : End of MPR read delay center optimization
808 04:51:42.809129 INFO : End of write delay center optimization
809 04:51:42.814662 INFO : End of read delay center optimization
810 04:51:42.815113 INFO : End of max read latency training
811 04:51:42.820199 INFO : Training has run successfully!
812 04:51:42.820523 1D training succeed
813 04:51:42.829409 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 04:51:42.876328 Check phy result
815 04:51:42.876822 INFO : End of initialization
816 04:51:42.898642 INFO : End of 2D read delay Voltage center optimization
817 04:51:42.918108 INFO : End of 2D read delay Voltage center optimization
818 04:51:42.970824 INFO : End of 2D write delay Voltage center optimization
819 04:51:43.020527 INFO : End of 2D write delay Voltage center optimization
820 04:51:43.026049 INFO : Training has run successfully!
821 04:51:43.026505
822 04:51:43.026873 channel==0
823 04:51:43.031667 RxClkDly_Margin_A0==88 ps 9
824 04:51:43.032136 TxDqDly_Margin_A0==98 ps 10
825 04:51:43.037251 RxClkDly_Margin_A1==88 ps 9
826 04:51:43.037593 TxDqDly_Margin_A1==98 ps 10
827 04:51:43.037848 TrainedVREFDQ_A0==74
828 04:51:43.042943 TrainedVREFDQ_A1==74
829 04:51:43.043263 VrefDac_Margin_A0==25
830 04:51:43.043505 DeviceVref_Margin_A0==40
831 04:51:43.048496 VrefDac_Margin_A1==25
832 04:51:43.048830 DeviceVref_Margin_A1==40
833 04:51:43.049079
834 04:51:43.049312
835 04:51:43.054014 channel==1
836 04:51:43.054320 RxClkDly_Margin_A0==98 ps 10
837 04:51:43.054560 TxDqDly_Margin_A0==98 ps 10
838 04:51:43.059649 RxClkDly_Margin_A1==98 ps 10
839 04:51:43.059948 TxDqDly_Margin_A1==88 ps 9
840 04:51:43.065234 TrainedVREFDQ_A0==77
841 04:51:43.065697 TrainedVREFDQ_A1==77
842 04:51:43.066048 VrefDac_Margin_A0==22
843 04:51:43.070823 DeviceVref_Margin_A0==37
844 04:51:43.071234 VrefDac_Margin_A1==24
845 04:51:43.076415 DeviceVref_Margin_A1==37
846 04:51:43.076825
847 04:51:43.077184 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 04:51:43.082050
849 04:51:43.110049 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 04:51:43.110550 2D training succeed
851 04:51:43.115683 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 04:51:43.121216 auto size-- 65535DDR cs0 size: 2048MB
853 04:51:43.121634 DDR cs1 size: 2048MB
854 04:51:43.126838 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 04:51:43.127292 cs0 DataBus test pass
856 04:51:43.132418 cs1 DataBus test pass
857 04:51:43.132847 cs0 AddrBus test pass
858 04:51:43.133206 cs1 AddrBus test pass
859 04:51:43.133535
860 04:51:43.138020 100bdlr_step_size ps== 420
861 04:51:43.138439 result report
862 04:51:43.143654 boot times 0Enable ddr reg access
863 04:51:43.148087 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 04:51:43.161730 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 04:51:43.736240 0.0;M3 CHK:0;cm4_sp_mode 0
866 04:51:43.736797 MVN_1=0x00000000
867 04:51:43.741724 MVN_2=0x00000000
868 04:51:43.747408 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 04:51:43.747864 OPS=0x10
870 04:51:43.748287 ring efuse init
871 04:51:43.748653 chipver efuse init
872 04:51:43.752978 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 04:51:43.758702 [0.018961 Inits done]
874 04:51:43.759119 secure task start!
875 04:51:43.759481 high task start!
876 04:51:43.762404 low task start!
877 04:51:43.762814 run into bl31
878 04:51:43.769810 NOTICE: BL31: v1.3(release):4fc40b1
879 04:51:43.777334 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 04:51:43.777781 NOTICE: BL31: G12A normal boot!
881 04:51:43.802927 NOTICE: BL31: BL33 decompress pass
882 04:51:43.808021 ERROR: Error initializing runtime service opteed_fast
883 04:51:45.041567
884 04:51:45.042261
885 04:51:45.050030 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 04:51:45.051012
887 04:51:45.051539 Model: Libre Computer AML-A311D-CC Alta
888 04:51:45.258320 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 04:51:45.282041 DRAM: 2 GiB (effective 3.8 GiB)
890 04:51:45.424969 Core: 408 devices, 31 uclasses, devicetree: separate
891 04:51:45.429663 WDT: Not starting watchdog@f0d0
892 04:51:45.463099 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 04:51:45.475334 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 04:51:45.479740 ** Bad device specification mmc 0 **
895 04:51:45.490638 Card did not respond to voltage select! : -110
896 04:51:45.498028 ** Bad device specification mmc 0 **
897 04:51:45.498711 Couldn't find partition mmc 0
898 04:51:45.506623 Card did not respond to voltage select! : -110
899 04:51:45.512120 ** Bad device specification mmc 0 **
900 04:51:45.512818 Couldn't find partition mmc 0
901 04:51:45.516208 Error: could not access storage.
902 04:51:45.859521 Net: eth0: ethernet@ff3f0000
903 04:51:45.859951 starting USB...
904 04:51:46.111490 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 04:51:46.112305 Starting the controller
906 04:51:46.118170 USB XHCI 1.10
907 04:51:47.980124 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 04:51:47.980642 bl2_stage_init 0x01
909 04:51:47.980972 bl2_stage_init 0x81
910 04:51:47.985549 hw id: 0x0000 - pwm id 0x01
911 04:51:47.985923 bl2_stage_init 0xc1
912 04:51:47.986217 bl2_stage_init 0x02
913 04:51:47.986536
914 04:51:47.991340 L0:00000000
915 04:51:47.991705 L1:20000703
916 04:51:47.992022 L2:00008067
917 04:51:47.992317 L3:14000000
918 04:51:47.996781 B2:00402000
919 04:51:47.997155 B1:e0f83180
920 04:51:47.997453
921 04:51:47.997744 TE: 58167
922 04:51:47.997981
923 04:51:48.002325 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 04:51:48.002718
925 04:51:48.003016 Board ID = 1
926 04:51:48.008006 Set A53 clk to 24M
927 04:51:48.008386 Set A73 clk to 24M
928 04:51:48.008682 Set clk81 to 24M
929 04:51:48.013577 A53 clk: 1200 MHz
930 04:51:48.013958 A73 clk: 1200 MHz
931 04:51:48.014253 CLK81: 166.6M
932 04:51:48.014574 smccc: 00012abd
933 04:51:48.019238 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 04:51:48.024770 board id: 1
935 04:51:48.030493 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 04:51:48.041451 fw parse done
937 04:51:48.046476 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 04:51:48.089052 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 04:51:48.100718 PIEI prepare done
940 04:51:48.101117 fastboot data load
941 04:51:48.101406 fastboot data verify
942 04:51:48.106392 verify result: 266
943 04:51:48.112010 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 04:51:48.112376 LPDDR4 probe
945 04:51:48.112646 ddr clk to 1584MHz
946 04:51:48.119789 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 04:51:48.157287
948 04:51:48.157770 dmc_version 0001
949 04:51:48.163328 Check phy result
950 04:51:48.169766 INFO : End of CA training
951 04:51:48.170128 INFO : End of initialization
952 04:51:48.175354 INFO : Training has run successfully!
953 04:51:48.175764 Check phy result
954 04:51:48.180938 INFO : End of initialization
955 04:51:48.181334 INFO : End of read enable training
956 04:51:48.186726 INFO : End of fine write leveling
957 04:51:48.192318 INFO : End of Write leveling coarse delay
958 04:51:48.192691 INFO : Training has run successfully!
959 04:51:48.192993 Check phy result
960 04:51:48.197771 INFO : End of initialization
961 04:51:48.198168 INFO : End of read dq deskew training
962 04:51:48.203340 INFO : End of MPR read delay center optimization
963 04:51:48.208985 INFO : End of write delay center optimization
964 04:51:48.214590 INFO : End of read delay center optimization
965 04:51:48.214944 INFO : End of max read latency training
966 04:51:48.220207 INFO : Training has run successfully!
967 04:51:48.220600 1D training succeed
968 04:51:48.228898 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 04:51:48.276109 Check phy result
970 04:51:48.276581 INFO : End of initialization
971 04:51:48.299120 INFO : End of 2D read delay Voltage center optimization
972 04:51:48.319791 INFO : End of 2D read delay Voltage center optimization
973 04:51:48.371346 INFO : End of 2D write delay Voltage center optimization
974 04:51:48.421289 INFO : End of 2D write delay Voltage center optimization
975 04:51:48.426845 INFO : Training has run successfully!
976 04:51:48.427292
977 04:51:48.427648 channel==0
978 04:51:48.432421 RxClkDly_Margin_A0==88 ps 9
979 04:51:48.432829 TxDqDly_Margin_A0==98 ps 10
980 04:51:48.438045 RxClkDly_Margin_A1==88 ps 9
981 04:51:48.438472 TxDqDly_Margin_A1==98 ps 10
982 04:51:48.438820 TrainedVREFDQ_A0==74
983 04:51:48.443620 TrainedVREFDQ_A1==74
984 04:51:48.444078 VrefDac_Margin_A0==25
985 04:51:48.444452 DeviceVref_Margin_A0==40
986 04:51:48.449144 VrefDac_Margin_A1==25
987 04:51:48.449561 DeviceVref_Margin_A1==40
988 04:51:48.449905
989 04:51:48.450204
990 04:51:48.454837 channel==1
991 04:51:48.455309 RxClkDly_Margin_A0==98 ps 10
992 04:51:48.455674 TxDqDly_Margin_A0==98 ps 10
993 04:51:48.460536 RxClkDly_Margin_A1==98 ps 10
994 04:51:48.460973 TxDqDly_Margin_A1==98 ps 10
995 04:51:48.465975 TrainedVREFDQ_A0==77
996 04:51:48.466383 TrainedVREFDQ_A1==78
997 04:51:48.466736 VrefDac_Margin_A0==22
998 04:51:48.471510 DeviceVref_Margin_A0==37
999 04:51:48.471909 VrefDac_Margin_A1==23
1000 04:51:48.477147 DeviceVref_Margin_A1==36
1001 04:51:48.477566
1002 04:51:48.477888 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 04:51:48.482739
1004 04:51:48.510847 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1005 04:51:48.511340 2D training succeed
1006 04:51:48.516454 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 04:51:48.521935 auto size-- 65535DDR cs0 size: 2048MB
1008 04:51:48.522323 DDR cs1 size: 2048MB
1009 04:51:48.527518 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 04:51:48.527900 cs0 DataBus test pass
1011 04:51:48.533146 cs1 DataBus test pass
1012 04:51:48.533537 cs0 AddrBus test pass
1013 04:51:48.533855 cs1 AddrBus test pass
1014 04:51:48.534159
1015 04:51:48.538817 100bdlr_step_size ps== 420
1016 04:51:48.539253 result report
1017 04:51:48.544383 boot times 0Enable ddr reg access
1018 04:51:48.548917 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 04:51:48.563356 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 04:51:49.136363 0.0;M3 CHK:0;cm4_sp_mode 0
1021 04:51:49.136971 MVN_1=0x00000000
1022 04:51:49.141865 MVN_2=0x00000000
1023 04:51:49.147660 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 04:51:49.148165 OPS=0x10
1025 04:51:49.148581 ring efuse init
1026 04:51:49.148957 chipver efuse init
1027 04:51:49.153196 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 04:51:49.158793 [0.018961 Inits done]
1029 04:51:49.159146 secure task start!
1030 04:51:49.159411 high task start!
1031 04:51:49.162579 low task start!
1032 04:51:49.163046 run into bl31
1033 04:51:49.170055 NOTICE: BL31: v1.3(release):4fc40b1
1034 04:51:49.177686 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 04:51:49.178041 NOTICE: BL31: G12A normal boot!
1036 04:51:49.203157 NOTICE: BL31: BL33 decompress pass
1037 04:51:49.207875 ERROR: Error initializing runtime service opteed_fast
1038 04:51:50.441758
1039 04:51:50.442147
1040 04:51:50.449793 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 04:51:50.450360
1042 04:51:50.450831 Model: Libre Computer AML-A311D-CC Alta
1043 04:51:50.658344 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 04:51:50.682164 DRAM: 2 GiB (effective 3.8 GiB)
1045 04:51:50.825036 Core: 408 devices, 31 uclasses, devicetree: separate
1046 04:51:50.829976 WDT: Not starting watchdog@f0d0
1047 04:51:50.863155 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 04:51:50.875616 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 04:51:50.880003 ** Bad device specification mmc 0 **
1050 04:51:50.890944 Card did not respond to voltage select! : -110
1051 04:51:50.897655 ** Bad device specification mmc 0 **
1052 04:51:50.898187 Couldn't find partition mmc 0
1053 04:51:50.906936 Card did not respond to voltage select! : -110
1054 04:51:50.912448 ** Bad device specification mmc 0 **
1055 04:51:50.912983 Couldn't find partition mmc 0
1056 04:51:50.916659 Error: could not access storage.
1057 04:51:51.259373 Net: eth0: ethernet@ff3f0000
1058 04:51:51.260054 starting USB...
1059 04:51:51.511755 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 04:51:51.512201 Starting the controller
1061 04:51:51.518648 USB XHCI 1.10
1062 04:51:53.072597 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 04:51:53.080267 scanning usb for storage devices... 0 Storage Device(s) found
1065 04:51:53.131703 Hit any key to stop autoboot: 1
1066 04:51:53.132540 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 04:51:53.133035 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1068 04:51:53.133331 Setting prompt string to ['=>']
1069 04:51:53.133611 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1070 04:51:53.138623 0
1071 04:51:53.139611 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 04:51:53.140284 Sending with 10 millisecond of delay
1074 04:51:54.275595 => setenv autoload no
1075 04:51:54.286519 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 04:51:54.291946 setenv autoload no
1077 04:51:54.292821 Sending with 10 millisecond of delay
1079 04:51:56.091112 => setenv initrd_high 0xffffffff
1080 04:51:56.101974 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1081 04:51:56.102944 setenv initrd_high 0xffffffff
1082 04:51:56.103754 Sending with 10 millisecond of delay
1084 04:51:57.721107 => setenv fdt_high 0xffffffff
1085 04:51:57.731922 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 04:51:57.732857 setenv fdt_high 0xffffffff
1087 04:51:57.733607 Sending with 10 millisecond of delay
1089 04:51:58.025543 => dhcp
1090 04:51:58.036312 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 04:51:58.037160 dhcp
1092 04:51:58.037626 Speed: 1000, full duplex
1093 04:51:58.038067 BOOTP broadcast 1
1094 04:51:58.254542 DHCP client bound to address 192.168.6.33 (218 ms)
1095 04:51:58.255460 Sending with 10 millisecond of delay
1097 04:51:59.932249 => setenv serverip 192.168.6.2
1098 04:51:59.943078 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 04:51:59.944069 setenv serverip 192.168.6.2
1100 04:51:59.944872 Sending with 10 millisecond of delay
1102 04:52:03.669444 => tftpboot 0x01080000 681354/tftp-deploy-gs3435u8/kernel/uImage
1103 04:52:03.680274 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 04:52:03.681201 tftpboot 0x01080000 681354/tftp-deploy-gs3435u8/kernel/uImage
1105 04:52:03.681855 Speed: 1000, full duplex
1106 04:52:03.682344 Using ethernet@ff3f0000 device
1107 04:52:03.683220 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1108 04:52:03.688476 Filename '681354/tftp-deploy-gs3435u8/kernel/uImage'.
1109 04:52:03.692724 Load address: 0x1080000
1110 04:52:08.046498 Loading: *###################
1111 04:52:08.047004 TFTP error: trying to overwrite reserved memory...
1113 04:52:08.048110 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1116 04:52:08.049372 end: 2.4 uboot-commands (duration 00:00:52) [common]
1118 04:52:08.050302 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1120 04:52:08.051068 end: 2 uboot-action (duration 00:00:52) [common]
1122 04:52:08.052159 Cleaning after the job
1123 04:52:08.052585 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/ramdisk
1124 04:52:08.068204 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/kernel
1125 04:52:08.121930 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/dtb
1126 04:52:08.123018 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681354/tftp-deploy-gs3435u8/modules
1127 04:52:08.185859 start: 4.1 power-off (timeout 00:00:30) [common]
1128 04:52:08.186686 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1129 04:52:08.219529 >> OK - accepted request
1130 04:52:08.222253 Returned 0 in 0 seconds
1131 04:52:08.323145 end: 4.1 power-off (duration 00:00:00) [common]
1133 04:52:08.324358 start: 4.2 read-feedback (timeout 00:10:00) [common]
1134 04:52:08.325154 Listened to connection for namespace 'common' for up to 1s
1135 04:52:09.326128 Finalising connection for namespace 'common'
1136 04:52:09.326868 Disconnecting from shell: Finalise
1137 04:52:09.327343 =>
1138 04:52:09.428322 end: 4.2 read-feedback (duration 00:00:01) [common]
1139 04:52:09.428799 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681354
1140 04:52:09.765573 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681354
1141 04:52:09.766336 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.