Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:50:14.408815 lava-dispatcher, installed at version: 2024.01
2 04:50:14.409646 start: 0 validate
3 04:50:14.410122 Start time: 2024-08-31 04:50:14.410091+00:00 (UTC)
4 04:50:14.410688 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:50:14.411239 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 04:50:14.452807 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:50:14.453392 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 04:50:14.486858 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:50:14.487492 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 04:50:35.618666 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:50:35.619160 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 04:50:38.670613 validate duration: 24.26
14 04:50:38.671875 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:50:38.672334 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:50:38.672714 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:50:38.673399 Not decompressing ramdisk as can be used compressed.
18 04:50:38.673910 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 04:50:38.674354 saving as /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/ramdisk/rootfs.cpio.gz
20 04:50:38.674663 total size: 8181887 (7 MB)
21 04:50:38.726039 progress 0 % (0 MB)
22 04:50:38.732205 progress 5 % (0 MB)
23 04:50:38.738286 progress 10 % (0 MB)
24 04:50:38.744319 progress 15 % (1 MB)
25 04:50:38.749894 progress 20 % (1 MB)
26 04:50:38.755886 progress 25 % (1 MB)
27 04:50:38.761620 progress 30 % (2 MB)
28 04:50:38.767578 progress 35 % (2 MB)
29 04:50:38.773098 progress 40 % (3 MB)
30 04:50:38.778974 progress 45 % (3 MB)
31 04:50:38.784624 progress 50 % (3 MB)
32 04:50:38.790666 progress 55 % (4 MB)
33 04:50:38.796198 progress 60 % (4 MB)
34 04:50:38.802025 progress 65 % (5 MB)
35 04:50:38.807507 progress 70 % (5 MB)
36 04:50:38.813403 progress 75 % (5 MB)
37 04:50:38.819051 progress 80 % (6 MB)
38 04:50:38.824990 progress 85 % (6 MB)
39 04:50:38.830387 progress 90 % (7 MB)
40 04:50:38.836083 progress 95 % (7 MB)
41 04:50:38.841072 progress 100 % (7 MB)
42 04:50:38.841786 7 MB downloaded in 0.17 s (46.70 MB/s)
43 04:50:38.842391 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:50:38.843395 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:50:38.843733 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:50:38.844087 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:50:38.844627 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+debug/gcc-12/kernel/Image
49 04:50:38.844906 saving as /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/kernel/Image
50 04:50:38.845142 total size: 167969280 (160 MB)
51 04:50:38.845378 No compression specified
52 04:50:38.894051 progress 0 % (0 MB)
53 04:50:39.010182 progress 5 % (8 MB)
54 04:50:39.120162 progress 10 % (16 MB)
55 04:50:39.229834 progress 15 % (24 MB)
56 04:50:39.339834 progress 20 % (32 MB)
57 04:50:39.449297 progress 25 % (40 MB)
58 04:50:39.558654 progress 30 % (48 MB)
59 04:50:39.668348 progress 35 % (56 MB)
60 04:50:39.777732 progress 40 % (64 MB)
61 04:50:39.886774 progress 45 % (72 MB)
62 04:50:39.996554 progress 50 % (80 MB)
63 04:50:40.106112 progress 55 % (88 MB)
64 04:50:40.215491 progress 60 % (96 MB)
65 04:50:40.324139 progress 65 % (104 MB)
66 04:50:40.436980 progress 70 % (112 MB)
67 04:50:40.551857 progress 75 % (120 MB)
68 04:50:40.660528 progress 80 % (128 MB)
69 04:50:40.771891 progress 85 % (136 MB)
70 04:50:40.881293 progress 90 % (144 MB)
71 04:50:40.991323 progress 95 % (152 MB)
72 04:50:41.101296 progress 100 % (160 MB)
73 04:50:41.101854 160 MB downloaded in 2.26 s (70.98 MB/s)
74 04:50:41.102364 end: 1.2.1 http-download (duration 00:00:02) [common]
76 04:50:41.103262 end: 1.2 download-retry (duration 00:00:02) [common]
77 04:50:41.103570 start: 1.3 download-retry (timeout 00:09:58) [common]
78 04:50:41.103864 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 04:50:41.104415 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 04:50:41.104725 saving as /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 04:50:41.104953 total size: 53173 (0 MB)
82 04:50:41.105176 No compression specified
83 04:50:41.142545 progress 61 % (0 MB)
84 04:50:41.143420 progress 100 % (0 MB)
85 04:50:41.144017 0 MB downloaded in 0.04 s (1.30 MB/s)
86 04:50:41.144534 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:50:41.145416 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:50:41.145714 start: 1.4 download-retry (timeout 00:09:58) [common]
90 04:50:41.145995 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 04:50:41.146506 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 04:50:41.146799 saving as /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/modules/modules.tar
93 04:50:41.147024 total size: 27403736 (26 MB)
94 04:50:41.147253 Using unxz to decompress xz
95 04:50:41.203737 progress 0 % (0 MB)
96 04:50:41.413387 progress 5 % (1 MB)
97 04:50:41.660511 progress 10 % (2 MB)
98 04:50:41.868325 progress 15 % (3 MB)
99 04:50:42.099146 progress 20 % (5 MB)
100 04:50:42.313263 progress 25 % (6 MB)
101 04:50:42.523651 progress 30 % (7 MB)
102 04:50:42.741098 progress 35 % (9 MB)
103 04:50:42.945172 progress 40 % (10 MB)
104 04:50:43.157333 progress 45 % (11 MB)
105 04:50:43.369478 progress 50 % (13 MB)
106 04:50:43.566058 progress 55 % (14 MB)
107 04:50:43.794129 progress 60 % (15 MB)
108 04:50:44.046559 progress 65 % (17 MB)
109 04:50:44.273070 progress 70 % (18 MB)
110 04:50:44.520302 progress 75 % (19 MB)
111 04:50:44.752328 progress 80 % (20 MB)
112 04:50:44.950386 progress 85 % (22 MB)
113 04:50:45.172755 progress 90 % (23 MB)
114 04:50:45.398890 progress 95 % (24 MB)
115 04:50:45.617146 progress 100 % (26 MB)
116 04:50:45.628245 26 MB downloaded in 4.48 s (5.83 MB/s)
117 04:50:45.628980 end: 1.4.1 http-download (duration 00:00:04) [common]
119 04:50:45.629906 end: 1.4 download-retry (duration 00:00:04) [common]
120 04:50:45.630212 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 04:50:45.630519 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 04:50:45.630800 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:50:45.631086 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 04:50:45.631773 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l
125 04:50:45.633071 makedir: /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin
126 04:50:45.633629 makedir: /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/tests
127 04:50:45.634044 makedir: /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/results
128 04:50:45.635000 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-add-keys
129 04:50:45.635870 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-add-sources
130 04:50:45.636602 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-background-process-start
131 04:50:45.637416 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-background-process-stop
132 04:50:45.638220 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-common-functions
133 04:50:45.638913 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-echo-ipv4
134 04:50:45.640373 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-install-packages
135 04:50:45.641058 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-installed-packages
136 04:50:45.641766 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-os-build
137 04:50:45.642443 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-probe-channel
138 04:50:45.643197 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-probe-ip
139 04:50:45.644452 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-target-ip
140 04:50:45.645315 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-target-mac
141 04:50:45.646052 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-target-storage
142 04:50:45.646837 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-test-case
143 04:50:45.647479 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-test-event
144 04:50:45.648237 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-test-feedback
145 04:50:45.649496 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-test-raise
146 04:50:45.650332 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-test-reference
147 04:50:45.651029 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-test-runner
148 04:50:45.651694 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-test-set
149 04:50:45.652412 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-test-shell
150 04:50:45.653280 Updating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-install-packages (oe)
151 04:50:45.654610 Updating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/bin/lava-installed-packages (oe)
152 04:50:45.655261 Creating /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/environment
153 04:50:45.655853 LAVA metadata
154 04:50:45.656224 - LAVA_JOB_ID=681356
155 04:50:45.656481 - LAVA_DISPATCHER_IP=192.168.6.2
156 04:50:45.656922 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 04:50:45.658299 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 04:50:45.658733 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 04:50:45.658971 skipped lava-vland-overlay
160 04:50:45.659247 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 04:50:45.659566 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 04:50:45.659820 skipped lava-multinode-overlay
163 04:50:45.660871 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 04:50:45.661300 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 04:50:45.661640 Loading test definitions
166 04:50:45.662001 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 04:50:45.662837 Using /lava-681356 at stage 0
168 04:50:45.664426 uuid=681356_1.5.2.4.1 testdef=None
169 04:50:45.664906 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 04:50:45.665237 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 04:50:45.668179 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 04:50:45.669281 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 04:50:45.673615 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 04:50:45.678097 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 04:50:45.688875 runner path: /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/0/tests/0_dmesg test_uuid 681356_1.5.2.4.1
178 04:50:45.691458 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 04:50:45.695341 Creating lava-test-runner.conf files
181 04:50:45.696381 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681356/lava-overlay-2gyp560l/lava-681356/0 for stage 0
182 04:50:45.697842 - 0_dmesg
183 04:50:45.699518 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 04:50:45.700885 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 04:50:45.785344 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 04:50:45.786995 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 04:50:45.788217 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 04:50:45.789492 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 04:50:45.790749 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 04:50:46.810250 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 04:50:46.810746 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 04:50:46.811075 extracting modules file /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681356/extract-overlay-ramdisk-35osn53c/ramdisk
193 04:50:48.546509 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 04:50:48.547022 start: 1.5.5 apply-overlay-tftp (timeout 00:09:50) [common]
195 04:50:48.547314 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681356/compress-overlay-e46b4qpi/overlay-1.5.2.5.tar.gz to ramdisk
196 04:50:48.547530 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681356/compress-overlay-e46b4qpi/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681356/extract-overlay-ramdisk-35osn53c/ramdisk
197 04:50:48.579125 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 04:50:48.579591 start: 1.5.6 prepare-kernel (timeout 00:09:50) [common]
199 04:50:48.579862 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:50) [common]
200 04:50:48.580125 Converting downloaded kernel to a uImage
201 04:50:48.580441 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/kernel/Image /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/kernel/uImage
202 04:50:50.226158 output: Image Name:
203 04:50:50.226597 output: Created: Sat Aug 31 04:50:48 2024
204 04:50:50.226825 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 04:50:50.227046 output: Data Size: 167969280 Bytes = 164032.50 KiB = 160.19 MiB
206 04:50:50.227257 output: Load Address: 01080000
207 04:50:50.227464 output: Entry Point: 01080000
208 04:50:50.227673 output:
209 04:50:50.228062 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 04:50:50.228373 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 04:50:50.228663 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 04:50:50.228941 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 04:50:50.229225 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 04:50:50.229525 Building ramdisk /var/lib/lava/dispatcher/tmp/681356/extract-overlay-ramdisk-35osn53c/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681356/extract-overlay-ramdisk-35osn53c/ramdisk
215 04:50:57.219863 >> 436239 blocks
216 04:51:15.549942 Adding RAMdisk u-boot header.
217 04:51:15.551016 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681356/extract-overlay-ramdisk-35osn53c/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681356/extract-overlay-ramdisk-35osn53c/ramdisk.cpio.gz.uboot
218 04:51:16.095455 output: Image Name:
219 04:51:16.096193 output: Created: Sat Aug 31 04:51:15 2024
220 04:51:16.096700 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 04:51:16.097173 output: Data Size: 53173232 Bytes = 51926.98 KiB = 50.71 MiB
222 04:51:16.097628 output: Load Address: 00000000
223 04:51:16.098077 output: Entry Point: 00000000
224 04:51:16.098522 output:
225 04:51:16.099205 rename /var/lib/lava/dispatcher/tmp/681356/extract-overlay-ramdisk-35osn53c/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/ramdisk/ramdisk.cpio.gz.uboot
226 04:51:16.099683 end: 1.5.8 compress-ramdisk (duration 00:00:26) [common]
227 04:51:16.100341 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
228 04:51:16.100973 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:23) [common]
229 04:51:16.101492 No LXC device requested
230 04:51:16.102068 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 04:51:16.102651 start: 1.7 deploy-device-env (timeout 00:09:23) [common]
232 04:51:16.103212 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 04:51:16.103683 Checking files for TFTP limit of 4294967296 bytes.
234 04:51:16.106697 end: 1 tftp-deploy (duration 00:00:37) [common]
235 04:51:16.107396 start: 2 uboot-action (timeout 00:05:00) [common]
236 04:51:16.108050 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 04:51:16.108646 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 04:51:16.109229 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 04:51:16.109841 Using kernel file from prepare-kernel: 681356/tftp-deploy-1jo0nvkd/kernel/uImage
240 04:51:16.110560 substitutions:
241 04:51:16.111045 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 04:51:16.111509 - {DTB_ADDR}: 0x01070000
243 04:51:16.111964 - {DTB}: 681356/tftp-deploy-1jo0nvkd/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 04:51:16.112453 - {INITRD}: 681356/tftp-deploy-1jo0nvkd/ramdisk/ramdisk.cpio.gz.uboot
245 04:51:16.112910 - {KERNEL_ADDR}: 0x01080000
246 04:51:16.113353 - {KERNEL}: 681356/tftp-deploy-1jo0nvkd/kernel/uImage
247 04:51:16.113800 - {LAVA_MAC}: None
248 04:51:16.114288 - {PRESEED_CONFIG}: None
249 04:51:16.114740 - {PRESEED_LOCAL}: None
250 04:51:16.115186 - {RAMDISK_ADDR}: 0x08000000
251 04:51:16.115627 - {RAMDISK}: 681356/tftp-deploy-1jo0nvkd/ramdisk/ramdisk.cpio.gz.uboot
252 04:51:16.116104 - {ROOT_PART}: None
253 04:51:16.116552 - {ROOT}: None
254 04:51:16.116993 - {SERVER_IP}: 192.168.6.2
255 04:51:16.117439 - {TEE_ADDR}: 0x83000000
256 04:51:16.117881 - {TEE}: None
257 04:51:16.118319 Parsed boot commands:
258 04:51:16.118749 - setenv autoload no
259 04:51:16.119187 - setenv initrd_high 0xffffffff
260 04:51:16.119624 - setenv fdt_high 0xffffffff
261 04:51:16.120086 - dhcp
262 04:51:16.120536 - setenv serverip 192.168.6.2
263 04:51:16.120975 - tftpboot 0x01080000 681356/tftp-deploy-1jo0nvkd/kernel/uImage
264 04:51:16.121416 - tftpboot 0x08000000 681356/tftp-deploy-1jo0nvkd/ramdisk/ramdisk.cpio.gz.uboot
265 04:51:16.121855 - tftpboot 0x01070000 681356/tftp-deploy-1jo0nvkd/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 04:51:16.122295 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 04:51:16.122737 - bootm 0x01080000 0x08000000 0x01070000
268 04:51:16.123321 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 04:51:16.125040 start: 2.3 connect-device (timeout 00:05:00) [common]
271 04:51:16.125549 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 04:51:16.140918 Setting prompt string to ['lava-test: # ']
273 04:51:16.142150 end: 2.3 connect-device (duration 00:00:00) [common]
274 04:51:16.142627 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 04:51:16.142991 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 04:51:16.143326 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 04:51:16.144229 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 04:51:16.179092 >> OK - accepted request
279 04:51:16.181382 Returned 0 in 0 seconds
280 04:51:16.282768 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 04:51:16.284766 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 04:51:16.285199 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 04:51:16.285521 Setting prompt string to ['Hit any key to stop autoboot']
285 04:51:16.285857 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 04:51:16.287377 Trying 192.168.56.21...
287 04:51:16.287706 Connected to conserv1.
288 04:51:16.288163 Escape character is '^]'.
289 04:51:16.288679
290 04:51:16.289192 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 04:51:16.289702
292 04:51:24.414861 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 04:51:24.415525 bl2_stage_init 0x01
294 04:51:24.416064 bl2_stage_init 0x81
295 04:51:24.420347 hw id: 0x0000 - pwm id 0x01
296 04:51:24.420866 bl2_stage_init 0xc1
297 04:51:24.425335 bl2_stage_init 0x02
298 04:51:24.425904
299 04:51:24.426391 L0:00000000
300 04:51:24.426866 L1:00000703
301 04:51:24.427318 L2:00008067
302 04:51:24.430781 L3:15000000
303 04:51:24.431263 S1:00000000
304 04:51:24.431736 B2:20282000
305 04:51:24.432242 B1:a0f83180
306 04:51:24.432695
307 04:51:24.433142 TE: 69554
308 04:51:24.433588
309 04:51:24.442007 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 04:51:24.442495
311 04:51:24.442945 Board ID = 1
312 04:51:24.443395 Set cpu clk to 24M
313 04:51:24.443836 Set clk81 to 24M
314 04:51:24.447631 Use GP1_pll as DSU clk.
315 04:51:24.448138 DSU clk: 1200 Mhz
316 04:51:24.448591 CPU clk: 1200 MHz
317 04:51:24.453277 Set clk81 to 166.6M
318 04:51:24.458855 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 04:51:24.459336 board id: 1
320 04:51:24.466627 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 04:51:24.477582 fw parse done
322 04:51:24.483512 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 04:51:24.526655 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 04:51:24.537784 PIEI prepare done
325 04:51:24.538266 fastboot data load
326 04:51:24.538724 fastboot data verify
327 04:51:24.543390 verify result: 266
328 04:51:24.548961 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 04:51:24.549455 LPDDR4 probe
330 04:51:24.549917 ddr clk to 1584MHz
331 04:51:24.556932 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 04:51:24.594798
333 04:51:24.595319 dmc_version 0001
334 04:51:24.601726 Check phy result
335 04:51:24.607750 INFO : End of CA training
336 04:51:24.608282 INFO : End of initialization
337 04:51:24.613364 INFO : Training has run successfully!
338 04:51:24.613840 Check phy result
339 04:51:24.618928 INFO : End of initialization
340 04:51:24.619407 INFO : End of read enable training
341 04:51:24.622297 INFO : End of fine write leveling
342 04:51:24.627861 INFO : End of Write leveling coarse delay
343 04:51:24.633462 INFO : Training has run successfully!
344 04:51:24.633939 Check phy result
345 04:51:24.634392 INFO : End of initialization
346 04:51:24.639007 INFO : End of read dq deskew training
347 04:51:24.644667 INFO : End of MPR read delay center optimization
348 04:51:24.645148 INFO : End of write delay center optimization
349 04:51:24.650283 INFO : End of read delay center optimization
350 04:51:24.655880 INFO : End of max read latency training
351 04:51:24.656385 INFO : Training has run successfully!
352 04:51:24.661501 1D training succeed
353 04:51:24.667356 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 04:51:24.715609 Check phy result
355 04:51:24.716159 INFO : End of initialization
356 04:51:24.742985 INFO : End of 2D read delay Voltage center optimization
357 04:51:24.767203 INFO : End of 2D read delay Voltage center optimization
358 04:51:24.823965 INFO : End of 2D write delay Voltage center optimization
359 04:51:24.877910 INFO : End of 2D write delay Voltage center optimization
360 04:51:24.883537 INFO : Training has run successfully!
361 04:51:24.884062
362 04:51:24.884663 channel==0
363 04:51:24.889131 RxClkDly_Margin_A0==69 ps 7
364 04:51:24.889610 TxDqDly_Margin_A0==98 ps 10
365 04:51:24.892408 RxClkDly_Margin_A1==88 ps 9
366 04:51:24.892881 TxDqDly_Margin_A1==88 ps 9
367 04:51:24.897947 TrainedVREFDQ_A0==74
368 04:51:24.898421 TrainedVREFDQ_A1==74
369 04:51:24.898869 VrefDac_Margin_A0==25
370 04:51:24.903570 DeviceVref_Margin_A0==40
371 04:51:24.904061 VrefDac_Margin_A1==23
372 04:51:24.909908 DeviceVref_Margin_A1==40
373 04:51:24.910394
374 04:51:24.910844
375 04:51:24.911286 channel==1
376 04:51:24.911728 RxClkDly_Margin_A0==88 ps 9
377 04:51:24.914786 TxDqDly_Margin_A0==98 ps 10
378 04:51:24.915260 RxClkDly_Margin_A1==78 ps 8
379 04:51:24.920278 TxDqDly_Margin_A1==88 ps 9
380 04:51:24.920752 TrainedVREFDQ_A0==75
381 04:51:24.921201 TrainedVREFDQ_A1==75
382 04:51:24.925914 VrefDac_Margin_A0==22
383 04:51:24.926394 DeviceVref_Margin_A0==39
384 04:51:24.931490 VrefDac_Margin_A1==20
385 04:51:24.931958 DeviceVref_Margin_A1==39
386 04:51:24.932449
387 04:51:24.937077 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 04:51:24.937547
389 04:51:24.965073 soc_vref_reg_value 0x 00000019 00000018 00000019 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000019 00000018 00000019 00000015 00000018 00000015 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 04:51:24.970652 2D training succeed
391 04:51:24.976299 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 04:51:24.976775 auto size-- 65535DDR cs0 size: 2048MB
393 04:51:24.981860 DDR cs1 size: 2048MB
394 04:51:24.982325 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 04:51:24.987511 cs0 DataBus test pass
396 04:51:24.988031 cs1 DataBus test pass
397 04:51:24.988486 cs0 AddrBus test pass
398 04:51:24.993091 cs1 AddrBus test pass
399 04:51:24.993567
400 04:51:24.994018 100bdlr_step_size ps== 471
401 04:51:24.994473 result report
402 04:51:24.998670 boot times 0Enable ddr reg access
403 04:51:25.006264 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 04:51:25.020102 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 04:51:25.680306 bl2z: ptr: 05129330, size: 00001e40
406 04:51:25.689774 0.0;M3 CHK:0;cm4_sp_mode 0
407 04:51:25.690280 MVN_1=0x00000000
408 04:51:25.690731 MVN_2=0x00000000
409 04:51:25.701287 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 04:51:25.701782 OPS=0x04
411 04:51:25.702227 ring efuse init
412 04:51:25.704301 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 04:51:25.710426 [0.017354 Inits done]
414 04:51:25.710895 secure task start!
415 04:51:25.711339 high task start!
416 04:51:25.711772 low task start!
417 04:51:25.714619 run into bl31
418 04:51:25.723303 NOTICE: BL31: v1.3(release):4fc40b1
419 04:51:25.731133 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 04:51:25.731619 NOTICE: BL31: G12A normal boot!
421 04:51:25.746588 NOTICE: BL31: BL33 decompress pass
422 04:51:25.754929 ERROR: Error initializing runtime service opteed_fast
423 04:51:26.962942 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 04:51:26.963346 bl2_stage_init 0x01
425 04:51:26.963560 bl2_stage_init 0x81
426 04:51:26.968582 hw id: 0x0000 - pwm id 0x01
427 04:51:26.969157 bl2_stage_init 0xc1
428 04:51:26.974198 bl2_stage_init 0x02
429 04:51:26.974740
430 04:51:26.975232 L0:00000000
431 04:51:26.975670 L1:00000703
432 04:51:26.976136 L2:00008067
433 04:51:26.976569 L3:15000000
434 04:51:26.980301 S1:00000000
435 04:51:26.980811 B2:20282000
436 04:51:26.981254 B1:a0f83180
437 04:51:26.981688
438 04:51:26.982121 TE: 67592
439 04:51:26.982556
440 04:51:26.985878 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 04:51:26.986385
442 04:51:26.991474 Board ID = 1
443 04:51:26.991971 Set cpu clk to 24M
444 04:51:26.992450 Set clk81 to 24M
445 04:51:26.997079 Use GP1_pll as DSU clk.
446 04:51:26.997572 DSU clk: 1200 Mhz
447 04:51:26.998005 CPU clk: 1200 MHz
448 04:51:26.998431 Set clk81 to 166.6M
449 04:51:27.008223 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 04:51:27.008729 board id: 1
451 04:51:27.015036 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 04:51:27.025699 fw parse done
453 04:51:27.031750 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 04:51:27.074278 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 04:51:27.085212 PIEI prepare done
456 04:51:27.085739 fastboot data load
457 04:51:27.086184 fastboot data verify
458 04:51:27.090814 verify result: 266
459 04:51:27.096473 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 04:51:27.096994 LPDDR4 probe
461 04:51:27.097433 ddr clk to 1584MHz
462 04:51:27.106931 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 04:51:28.465554 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
464 04:51:28.465979 bl2_stage_init 0x01
465 04:51:28.466211 bl2_stage_init 0x81
466 04:51:28.471182 hw id: 0x0000 - pwm id 0x01
467 04:51:28.471657 bl2_stage_init 0xc1
468 04:51:28.476753 bl2_stage_init 0x02
469 04:51:28.477204
470 04:51:28.477556 L0:00000000
471 04:51:28.477809 L1:00000703
472 04:51:28.478019 L2:00008067
473 04:51:28.478218 L3:15000000
474 04:51:28.482341 S1:00000000
475 04:51:28.482783 B2:20282000
476 04:51:28.483131 B1:a0f83180
477 04:51:28.483456
478 04:51:28.483798 TE: 70599
479 04:51:28.484181
480 04:51:28.487936 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
481 04:51:28.488398
482 04:51:28.493539 Board ID = 1
483 04:51:28.493862 Set cpu clk to 24M
484 04:51:28.494078 Set clk81 to 24M
485 04:51:28.499130 Use GP1_pll as DSU clk.
486 04:51:28.499581 DSU clk: 1200 Mhz
487 04:51:28.499951 CPU clk: 1200 MHz
488 04:51:28.504749 Set clk81 to 166.6M
489 04:51:28.510320 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
490 04:51:28.510654 board id: 1
491 04:51:28.517509 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
492 04:51:28.528457 fw parse done
493 04:51:28.534404 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
494 04:51:28.576588 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
495 04:51:28.588732 PIEI prepare done
496 04:51:28.589075 fastboot data load
497 04:51:28.589298 fastboot data verify
498 04:51:28.594304 verify result: 266
499 04:51:28.599901 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
500 04:51:28.600381 LPDDR4 probe
501 04:51:28.600738 ddr clk to 1584MHz
502 04:51:28.607570 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 04:51:28.644724
504 04:51:28.645074 dmc_version 0001
505 04:51:28.651680 Check phy result
506 04:51:28.658601 INFO : End of CA training
507 04:51:28.658928 INFO : End of initialization
508 04:51:28.664218 INFO : Training has run successfully!
509 04:51:28.664674 Check phy result
510 04:51:28.669828 INFO : End of initialization
511 04:51:28.670292 INFO : End of read enable training
512 04:51:28.675409 INFO : End of fine write leveling
513 04:51:28.681004 INFO : End of Write leveling coarse delay
514 04:51:28.681334 INFO : Training has run successfully!
515 04:51:28.681559 Check phy result
516 04:51:28.686610 INFO : End of initialization
517 04:51:28.686937 INFO : End of read dq deskew training
518 04:51:28.692203 INFO : End of MPR read delay center optimization
519 04:51:28.697793 INFO : End of write delay center optimization
520 04:51:28.703394 INFO : End of read delay center optimization
521 04:51:28.703717 INFO : End of max read latency training
522 04:51:28.708995 INFO : Training has run successfully!
523 04:51:28.709440 1D training succeed
524 04:51:28.718157 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
525 04:51:28.766479 Check phy result
526 04:51:28.766833 INFO : End of initialization
527 04:51:28.793918 INFO : End of 2D read delay Voltage center optimization
528 04:51:28.818069 INFO : End of 2D read delay Voltage center optimization
529 04:51:28.874764 INFO : End of 2D write delay Voltage center optimization
530 04:51:28.928903 INFO : End of 2D write delay Voltage center optimization
531 04:51:28.934340 INFO : Training has run successfully!
532 04:51:28.934669
533 04:51:28.934888 channel==0
534 04:51:28.939943 RxClkDly_Margin_A0==78 ps 8
535 04:51:28.940427 TxDqDly_Margin_A0==98 ps 10
536 04:51:28.945612 RxClkDly_Margin_A1==88 ps 9
537 04:51:28.946079 TxDqDly_Margin_A1==98 ps 10
538 04:51:28.946446 TrainedVREFDQ_A0==74
539 04:51:28.951121 TrainedVREFDQ_A1==74
540 04:51:28.951452 VrefDac_Margin_A0==24
541 04:51:28.951681 DeviceVref_Margin_A0==40
542 04:51:28.956827 VrefDac_Margin_A1==23
543 04:51:28.957279 DeviceVref_Margin_A1==40
544 04:51:28.957630
545 04:51:28.957975
546 04:51:28.962369 channel==1
547 04:51:28.962829 RxClkDly_Margin_A0==88 ps 9
548 04:51:28.963090 TxDqDly_Margin_A0==88 ps 9
549 04:51:28.968011 RxClkDly_Margin_A1==88 ps 9
550 04:51:28.968458 TxDqDly_Margin_A1==88 ps 9
551 04:51:28.973659 TrainedVREFDQ_A0==75
552 04:51:28.973987 TrainedVREFDQ_A1==77
553 04:51:28.974204 VrefDac_Margin_A0==23
554 04:51:28.979183 DeviceVref_Margin_A0==39
555 04:51:28.979642 VrefDac_Margin_A1==22
556 04:51:28.984891 DeviceVref_Margin_A1==37
557 04:51:28.985351
558 04:51:28.985701 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
559 04:51:28.985949
560 04:51:29.018306 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000019 00000018 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
561 04:51:29.018667 2D training succeed
562 04:51:29.023920 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
563 04:51:29.029594 auto size-- 65535DDR cs0 size: 2048MB
564 04:51:29.030054 DDR cs1 size: 2048MB
565 04:51:29.035155 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
566 04:51:29.035489 cs0 DataBus test pass
567 04:51:29.040836 cs1 DataBus test pass
568 04:51:29.041285 cs0 AddrBus test pass
569 04:51:29.041658 cs1 AddrBus test pass
570 04:51:29.042001
571 04:51:29.046320 100bdlr_step_size ps== 471
572 04:51:29.046644 result report
573 04:51:29.051928 boot times 0Enable ddr reg access
574 04:51:29.057104 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
575 04:51:29.070958 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
576 04:51:29.730332 bl2z: ptr: 05129330, size: 00001e40
577 04:51:29.737425 0.0;M3 CHK:0;cm4_sp_mode 0
578 04:51:29.737770 MVN_1=0x00000000
579 04:51:29.737986 MVN_2=0x00000000
580 04:51:29.748866 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
581 04:51:29.749331 OPS=0x04
582 04:51:29.749690 ring efuse init
583 04:51:29.754533 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
584 04:51:29.755004 [0.017354 Inits done]
585 04:51:29.755269 secure task start!
586 04:51:29.762524 high task start!
587 04:51:29.762846 low task start!
588 04:51:29.763072 run into bl31
589 04:51:29.771139 NOTICE: BL31: v1.3(release):4fc40b1
590 04:51:29.778957 NOTICE: BL31: Built : 15:57:33, May 22 2019
591 04:51:29.779412 NOTICE: BL31: G12A normal boot!
592 04:51:29.794505 NOTICE: BL31: BL33 decompress pass
593 04:51:29.800181 ERROR: Error initializing runtime service opteed_fast
594 04:51:31.017044 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
595 04:51:31.017442 bl2_stage_init 0x01
596 04:51:31.017666 bl2_stage_init 0x81
597 04:51:31.022531 hw id: 0x0000 - pwm id 0x01
598 04:51:31.022983 bl2_stage_init 0xc1
599 04:51:31.026863 bl2_stage_init 0x02
600 04:51:31.027312
601 04:51:31.027663 L0:00000000
602 04:51:31.027910 L1:00000703
603 04:51:31.028166 L2:00008067
604 04:51:31.032374 L3:15000000
605 04:51:31.032826 S1:00000000
606 04:51:31.033188 B2:20282000
607 04:51:31.033534 B1:a0f83180
608 04:51:31.033858
609 04:51:31.034179 TE: 71535
610 04:51:31.037962
611 04:51:31.043483 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
612 04:51:31.043804
613 04:51:31.044044 Board ID = 1
614 04:51:31.044259 Set cpu clk to 24M
615 04:51:31.044482 Set clk81 to 24M
616 04:51:31.049133 Use GP1_pll as DSU clk.
617 04:51:31.049582 DSU clk: 1200 Mhz
618 04:51:31.049913 CPU clk: 1200 MHz
619 04:51:31.054754 Set clk81 to 166.6M
620 04:51:31.060387 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
621 04:51:31.060708 board id: 1
622 04:51:31.068952 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
623 04:51:31.079741 fw parse done
624 04:51:31.085769 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
625 04:51:31.128830 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
626 04:51:31.140011 PIEI prepare done
627 04:51:31.140472 fastboot data load
628 04:51:31.140736 fastboot data verify
629 04:51:31.145555 verify result: 266
630 04:51:31.151172 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
631 04:51:31.151492 LPDDR4 probe
632 04:51:31.151701 ddr clk to 1584MHz
633 04:51:31.158271 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
634 04:51:31.196901
635 04:51:31.197380 dmc_version 0001
636 04:51:31.203928 Check phy result
637 04:51:31.209980 INFO : End of CA training
638 04:51:31.210299 INFO : End of initialization
639 04:51:31.215492 INFO : Training has run successfully!
640 04:51:31.215938 Check phy result
641 04:51:31.221208 INFO : End of initialization
642 04:51:31.221537 INFO : End of read enable training
643 04:51:31.226724 INFO : End of fine write leveling
644 04:51:31.232358 INFO : End of Write leveling coarse delay
645 04:51:31.232812 INFO : Training has run successfully!
646 04:51:31.233068 Check phy result
647 04:51:31.237939 INFO : End of initialization
648 04:51:31.238254 INFO : End of read dq deskew training
649 04:51:31.243514 INFO : End of MPR read delay center optimization
650 04:51:31.249211 INFO : End of write delay center optimization
651 04:51:31.254707 INFO : End of read delay center optimization
652 04:51:31.255027 INFO : End of max read latency training
653 04:51:31.260320 INFO : Training has run successfully!
654 04:51:31.260796 1D training succeed
655 04:51:31.269518 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
656 04:51:31.317849 Check phy result
657 04:51:31.318195 INFO : End of initialization
658 04:51:31.345363 INFO : End of 2D read delay Voltage center optimization
659 04:51:31.369454 INFO : End of 2D read delay Voltage center optimization
660 04:51:31.426149 INFO : End of 2D write delay Voltage center optimization
661 04:51:31.480147 INFO : End of 2D write delay Voltage center optimization
662 04:51:31.485706 INFO : Training has run successfully!
663 04:51:31.486024
664 04:51:31.486266 channel==0
665 04:51:31.491286 RxClkDly_Margin_A0==78 ps 8
666 04:51:31.491604 TxDqDly_Margin_A0==98 ps 10
667 04:51:31.496887 RxClkDly_Margin_A1==88 ps 9
668 04:51:31.497339 TxDqDly_Margin_A1==88 ps 9
669 04:51:31.497686 TrainedVREFDQ_A0==74
670 04:51:31.502501 TrainedVREFDQ_A1==74
671 04:51:31.502834 VrefDac_Margin_A0==24
672 04:51:31.503059 DeviceVref_Margin_A0==40
673 04:51:31.508047 VrefDac_Margin_A1==23
674 04:51:31.508495 DeviceVref_Margin_A1==40
675 04:51:31.508849
676 04:51:31.509183
677 04:51:31.509514 channel==1
678 04:51:31.513716 RxClkDly_Margin_A0==88 ps 9
679 04:51:31.514035 TxDqDly_Margin_A0==98 ps 10
680 04:51:31.519279 RxClkDly_Margin_A1==78 ps 8
681 04:51:31.519730 TxDqDly_Margin_A1==78 ps 8
682 04:51:31.524929 TrainedVREFDQ_A0==78
683 04:51:31.525457 TrainedVREFDQ_A1==75
684 04:51:31.525895 VrefDac_Margin_A0==22
685 04:51:31.530472 DeviceVref_Margin_A0==36
686 04:51:31.530942 VrefDac_Margin_A1==22
687 04:51:31.536045 DeviceVref_Margin_A1==39
688 04:51:31.536515
689 04:51:31.536943 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
690 04:51:31.537360
691 04:51:31.569642 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000016 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
692 04:51:31.570177 2D training succeed
693 04:51:31.575247 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
694 04:51:31.580783 auto size-- 65535DDR cs0 size: 2048MB
695 04:51:31.581254 DDR cs1 size: 2048MB
696 04:51:31.586329 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
697 04:51:31.586834 cs0 DataBus test pass
698 04:51:31.592021 cs1 DataBus test pass
699 04:51:31.592486 cs0 AddrBus test pass
700 04:51:31.592913 cs1 AddrBus test pass
701 04:51:31.593331
702 04:51:31.597527 100bdlr_step_size ps== 485
703 04:51:31.597995 result report
704 04:51:31.603125 boot times 0Enable ddr reg access
705 04:51:31.608283 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
706 04:51:31.622216 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
707 04:51:32.281723 bl2z: ptr: 05129330, size: 00001e40
708 04:51:32.290738 0.0;M3 CHK:0;cm4_sp_mode 0
709 04:51:32.291299 MVN_1=0x00000000
710 04:51:32.291717 MVN_2=0x00000000
711 04:51:32.302301 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
712 04:51:32.302844 OPS=0x04
713 04:51:32.303244 ring efuse init
714 04:51:32.307791 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
715 04:51:32.308278 [0.017354 Inits done]
716 04:51:32.308673 secure task start!
717 04:51:32.315826 high task start!
718 04:51:32.316299 low task start!
719 04:51:32.316693 run into bl31
720 04:51:32.324429 NOTICE: BL31: v1.3(release):4fc40b1
721 04:51:32.332344 NOTICE: BL31: Built : 15:57:33, May 22 2019
722 04:51:32.332785 NOTICE: BL31: G12A normal boot!
723 04:51:32.347787 NOTICE: BL31: BL33 decompress pass
724 04:51:32.353525 ERROR: Error initializing runtime service opteed_fast
725 04:51:33.148804
726 04:51:33.149399
727 04:51:33.154176 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
728 04:51:33.154655
729 04:51:33.157239 Model: Libre Computer AML-S905D3-CC Solitude
730 04:51:33.303750 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
731 04:51:33.319721 DRAM: 2 GiB (effective 3.8 GiB)
732 04:51:33.421055 Core: 406 devices, 33 uclasses, devicetree: separate
733 04:51:33.426943 WDT: Not starting watchdog@f0d0
734 04:51:33.452006 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
735 04:51:33.464395 Loading Environment from FAT... Card did not respond to voltage select! : -110
736 04:51:33.469290 ** Bad device specification mmc 0 **
737 04:51:33.479363 Card did not respond to voltage select! : -110
738 04:51:33.486001 ** Bad device specification mmc 0 **
739 04:51:33.486460 Couldn't find partition mmc 0
740 04:51:33.495396 Card did not respond to voltage select! : -110
741 04:51:33.500754 ** Bad device specification mmc 0 **
742 04:51:33.501246 Couldn't find partition mmc 0
743 04:51:33.504874 Error: could not access storage.
744 04:51:33.803369 Net: eth0: ethernet@ff3f0000
745 04:51:33.803927 starting USB...
746 04:51:34.047968 Bus usb@ff500000: Register 3000140 NbrPorts 3
747 04:51:34.048523 Starting the controller
748 04:51:34.054996 USB XHCI 1.10
749 04:51:35.608946 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
750 04:51:35.616342 scanning usb for storage devices... 0 Storage Device(s) found
752 04:51:35.667815 Hit any key to stop autoboot: 1
753 04:51:35.669776 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
754 04:51:35.672131 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
755 04:51:35.672618 Setting prompt string to ['=>']
756 04:51:35.672880 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
757 04:51:35.673871 0
758 04:51:35.674824 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
760 04:51:35.777114 => setenv autoload no
761 04:51:35.777595 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
762 04:51:35.783378 setenv autoload no
764 04:51:35.884530 => setenv initrd_high 0xffffffff
765 04:51:35.885198 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
766 04:51:35.889141 setenv initrd_high 0xffffffff
768 04:51:35.990334 => setenv fdt_high 0xffffffff
769 04:51:35.991004 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
770 04:51:35.994290 setenv fdt_high 0xffffffff
772 04:51:36.095490 => dhcp
773 04:51:36.096217 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
774 04:51:36.099863 dhcp
775 04:51:37.105229 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
776 04:51:37.105623 Speed: 1000, full duplex
777 04:51:37.105854 BOOTP broadcast 1
778 04:51:37.353781 BOOTP broadcast 2
779 04:51:37.855109 BOOTP broadcast 3
780 04:51:38.855562 BOOTP broadcast 4
781 04:51:40.856751 BOOTP broadcast 5
782 04:51:40.875243 DHCP client bound to address 192.168.6.12 (3768 ms)
784 04:51:40.976243 => setenv serverip 192.168.6.2
785 04:51:40.977161 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
786 04:51:40.980980 setenv serverip 192.168.6.2
788 04:51:41.082520 => tftpboot 0x01080000 681356/tftp-deploy-1jo0nvkd/kernel/uImage
789 04:51:41.083260 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
790 04:51:41.089700 tftpboot 0x01080000 681356/tftp-deploy-1jo0nvkd/kernel/uImage
791 04:51:41.090244 Speed: 1000, full duplex
792 04:51:41.090707 Using ethernet@ff3f0000 device
793 04:51:41.095275 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
794 04:51:41.100730 Filename '681356/tftp-deploy-1jo0nvkd/kernel/uImage'.
795 04:51:41.104358 Load address: 0x1080000
796 04:51:45.428648 Loading: *###################
797 04:51:45.429068 TFTP error: trying to overwrite reserved memory...
799 04:51:45.432897 end: 2.4.3 bootloader-commands (duration 00:00:10) [common]
802 04:51:45.435272 end: 2.4 uboot-commands (duration 00:00:29) [common]
804 04:51:45.436591 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
806 04:51:45.437846 end: 2 uboot-action (duration 00:00:29) [common]
808 04:51:45.439756 Cleaning after the job
809 04:51:45.440588 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/ramdisk
810 04:51:45.464611 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/kernel
811 04:51:45.519645 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/dtb
812 04:51:45.526273 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681356/tftp-deploy-1jo0nvkd/modules
813 04:51:45.582831 start: 4.1 power-off (timeout 00:00:30) [common]
814 04:51:45.583532 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
815 04:51:45.615403 >> OK - accepted request
816 04:51:45.617551 Returned 0 in 0 seconds
817 04:51:45.718433 end: 4.1 power-off (duration 00:00:00) [common]
819 04:51:45.719542 start: 4.2 read-feedback (timeout 00:10:00) [common]
820 04:51:45.720349 Listened to connection for namespace 'common' for up to 1s
821 04:51:46.721178 Finalising connection for namespace 'common'
822 04:51:46.721695 Disconnecting from shell: Finalise
823 04:51:46.721989 =>
824 04:51:46.822676 end: 4.2 read-feedback (duration 00:00:01) [common]
825 04:51:46.823144 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681356
826 04:51:47.173737 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681356
827 04:51:47.174340 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.