Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:17:14.783092 lava-dispatcher, installed at version: 2024.01
2 05:17:14.783909 start: 0 validate
3 05:17:14.784411 Start time: 2024-08-31 05:17:14.784379+00:00 (UTC)
4 05:17:14.784946 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:17:14.785493 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:17:14.822257 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:17:14.822819 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 05:17:14.850900 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:17:14.851541 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:17:16.904750 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:17:16.905262 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 05:17:16.945222 validate duration: 2.16
14 05:17:16.946071 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:17:16.946420 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:17:16.946731 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:17:16.947324 Not decompressing ramdisk as can be used compressed.
18 05:17:16.947795 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:17:16.948070 saving as /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/ramdisk/rootfs.cpio.gz
20 05:17:16.948339 total size: 8181887 (7 MB)
21 05:17:16.989365 progress 0 % (0 MB)
22 05:17:16.996866 progress 5 % (0 MB)
23 05:17:17.002745 progress 10 % (0 MB)
24 05:17:17.008873 progress 15 % (1 MB)
25 05:17:17.014309 progress 20 % (1 MB)
26 05:17:17.020218 progress 25 % (1 MB)
27 05:17:17.025786 progress 30 % (2 MB)
28 05:17:17.031516 progress 35 % (2 MB)
29 05:17:17.036846 progress 40 % (3 MB)
30 05:17:17.042527 progress 45 % (3 MB)
31 05:17:17.048105 progress 50 % (3 MB)
32 05:17:17.054368 progress 55 % (4 MB)
33 05:17:17.060167 progress 60 % (4 MB)
34 05:17:17.066465 progress 65 % (5 MB)
35 05:17:17.072288 progress 70 % (5 MB)
36 05:17:17.077946 progress 75 % (5 MB)
37 05:17:17.083896 progress 80 % (6 MB)
38 05:17:17.089950 progress 85 % (6 MB)
39 05:17:17.095473 progress 90 % (7 MB)
40 05:17:17.101372 progress 95 % (7 MB)
41 05:17:17.106259 progress 100 % (7 MB)
42 05:17:17.106969 7 MB downloaded in 0.16 s (49.20 MB/s)
43 05:17:17.107728 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:17:17.108725 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:17:17.109045 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:17:17.109350 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:17:17.109866 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 05:17:17.110146 saving as /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/kernel/Image
50 05:17:17.110378 total size: 66032128 (62 MB)
51 05:17:17.110611 No compression specified
52 05:17:17.150349 progress 0 % (0 MB)
53 05:17:17.191594 progress 5 % (3 MB)
54 05:17:17.233328 progress 10 % (6 MB)
55 05:17:17.275306 progress 15 % (9 MB)
56 05:17:17.316754 progress 20 % (12 MB)
57 05:17:17.358150 progress 25 % (15 MB)
58 05:17:17.399686 progress 30 % (18 MB)
59 05:17:17.441254 progress 35 % (22 MB)
60 05:17:17.482866 progress 40 % (25 MB)
61 05:17:17.524160 progress 45 % (28 MB)
62 05:17:17.565916 progress 50 % (31 MB)
63 05:17:17.607958 progress 55 % (34 MB)
64 05:17:17.650010 progress 60 % (37 MB)
65 05:17:17.691319 progress 65 % (40 MB)
66 05:17:17.733365 progress 70 % (44 MB)
67 05:17:17.775195 progress 75 % (47 MB)
68 05:17:17.816914 progress 80 % (50 MB)
69 05:17:17.858569 progress 85 % (53 MB)
70 05:17:17.900385 progress 90 % (56 MB)
71 05:17:17.942163 progress 95 % (59 MB)
72 05:17:17.983206 progress 100 % (62 MB)
73 05:17:17.983767 62 MB downloaded in 0.87 s (72.10 MB/s)
74 05:17:17.984298 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:17:17.985155 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:17:17.985454 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:17:17.985736 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:17:17.986291 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 05:17:17.986581 saving as /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/dtb/meson-g12b-a311d-libretech-cc.dtb
81 05:17:17.986804 total size: 54667 (0 MB)
82 05:17:17.987025 No compression specified
83 05:17:18.028642 progress 59 % (0 MB)
84 05:17:18.029554 progress 100 % (0 MB)
85 05:17:18.030188 0 MB downloaded in 0.04 s (1.20 MB/s)
86 05:17:18.030710 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:17:18.031703 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:17:18.032009 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:17:18.032299 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:17:18.032793 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 05:17:18.033055 saving as /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/modules/modules.tar
93 05:17:18.033273 total size: 16068796 (15 MB)
94 05:17:18.033493 Using unxz to decompress xz
95 05:17:18.072186 progress 0 % (0 MB)
96 05:17:18.173050 progress 5 % (0 MB)
97 05:17:18.290015 progress 10 % (1 MB)
98 05:17:18.398957 progress 15 % (2 MB)
99 05:17:18.515863 progress 20 % (3 MB)
100 05:17:18.625368 progress 25 % (3 MB)
101 05:17:18.739322 progress 30 % (4 MB)
102 05:17:18.847446 progress 35 % (5 MB)
103 05:17:18.958256 progress 40 % (6 MB)
104 05:17:19.068024 progress 45 % (6 MB)
105 05:17:19.178277 progress 50 % (7 MB)
106 05:17:19.286819 progress 55 % (8 MB)
107 05:17:19.405484 progress 60 % (9 MB)
108 05:17:19.515962 progress 65 % (9 MB)
109 05:17:19.634695 progress 70 % (10 MB)
110 05:17:19.764141 progress 75 % (11 MB)
111 05:17:19.899133 progress 80 % (12 MB)
112 05:17:20.021818 progress 85 % (13 MB)
113 05:17:20.139029 progress 90 % (13 MB)
114 05:17:20.247760 progress 95 % (14 MB)
115 05:17:20.361786 progress 100 % (15 MB)
116 05:17:20.373080 15 MB downloaded in 2.34 s (6.55 MB/s)
117 05:17:20.373709 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:17:20.374646 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:17:20.374976 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 05:17:20.375304 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 05:17:20.375605 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:17:20.375912 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 05:17:20.376938 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm
125 05:17:20.377876 makedir: /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin
126 05:17:20.378596 makedir: /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/tests
127 05:17:20.379258 makedir: /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/results
128 05:17:20.379902 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-add-keys
129 05:17:20.380961 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-add-sources
130 05:17:20.381925 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-background-process-start
131 05:17:20.382909 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-background-process-stop
132 05:17:20.384004 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-common-functions
133 05:17:20.385018 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-echo-ipv4
134 05:17:20.385971 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-install-packages
135 05:17:20.386906 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-installed-packages
136 05:17:20.387835 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-os-build
137 05:17:20.388856 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-probe-channel
138 05:17:20.389806 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-probe-ip
139 05:17:20.390788 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-target-ip
140 05:17:20.391736 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-target-mac
141 05:17:20.392499 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-target-storage
142 05:17:20.393090 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-test-case
143 05:17:20.393664 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-test-event
144 05:17:20.394224 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-test-feedback
145 05:17:20.394781 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-test-raise
146 05:17:20.395379 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-test-reference
147 05:17:20.396005 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-test-runner
148 05:17:20.396594 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-test-set
149 05:17:20.397159 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-test-shell
150 05:17:20.397734 Updating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-install-packages (oe)
151 05:17:20.398329 Updating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/bin/lava-installed-packages (oe)
152 05:17:20.398838 Creating /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/environment
153 05:17:20.399292 LAVA metadata
154 05:17:20.399584 - LAVA_JOB_ID=681597
155 05:17:20.399814 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:17:20.400239 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 05:17:20.401353 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:17:20.401711 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 05:17:20.401941 skipped lava-vland-overlay
160 05:17:20.402204 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:17:20.402482 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 05:17:20.402718 skipped lava-multinode-overlay
163 05:17:20.402977 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:17:20.403251 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 05:17:20.403519 Loading test definitions
166 05:17:20.403822 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 05:17:20.404100 Using /lava-681597 at stage 0
168 05:17:20.405353 uuid=681597_1.5.2.4.1 testdef=None
169 05:17:20.405687 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:17:20.405974 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 05:17:20.407947 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:17:20.408855 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 05:17:20.411335 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:17:20.412271 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 05:17:20.414607 runner path: /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/0/tests/0_dmesg test_uuid 681597_1.5.2.4.1
178 05:17:20.415226 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:17:20.416076 Creating lava-test-runner.conf files
181 05:17:20.416301 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681597/lava-overlay-kdg7vfsm/lava-681597/0 for stage 0
182 05:17:20.416678 - 0_dmesg
183 05:17:20.417067 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:17:20.417377 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 05:17:20.442488 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:17:20.442920 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:17:20.443192 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:17:20.443468 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:17:20.443738 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:17:21.375846 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:17:21.376343 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 05:17:21.376601 extracting modules file /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681597/extract-overlay-ramdisk-1l8694kf/ramdisk
193 05:17:23.217867 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 05:17:23.218497 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 05:17:23.218907 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681597/compress-overlay-clda6r0h/overlay-1.5.2.5.tar.gz to ramdisk
196 05:17:23.219176 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681597/compress-overlay-clda6r0h/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681597/extract-overlay-ramdisk-1l8694kf/ramdisk
197 05:17:23.259349 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:17:23.259974 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 05:17:23.260427 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 05:17:23.260761 Converting downloaded kernel to a uImage
201 05:17:23.261176 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/kernel/Image /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/kernel/uImage
202 05:17:23.919657 output: Image Name:
203 05:17:23.920088 output: Created: Sat Aug 31 05:17:23 2024
204 05:17:23.920304 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:17:23.920509 output: Data Size: 66032128 Bytes = 64484.50 KiB = 62.97 MiB
206 05:17:23.920711 output: Load Address: 01080000
207 05:17:23.920910 output: Entry Point: 01080000
208 05:17:23.921106 output:
209 05:17:23.921440 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 05:17:23.921732 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 05:17:23.922005 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 05:17:23.922258 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:17:23.922514 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 05:17:23.922769 Building ramdisk /var/lib/lava/dispatcher/tmp/681597/extract-overlay-ramdisk-1l8694kf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681597/extract-overlay-ramdisk-1l8694kf/ramdisk
215 05:17:27.234616 >> 255155 blocks
216 05:17:38.154361 Adding RAMdisk u-boot header.
217 05:17:38.155051 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681597/extract-overlay-ramdisk-1l8694kf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681597/extract-overlay-ramdisk-1l8694kf/ramdisk.cpio.gz.uboot
218 05:17:38.516167 output: Image Name:
219 05:17:38.516570 output: Created: Sat Aug 31 05:17:38 2024
220 05:17:38.516774 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:17:38.516976 output: Data Size: 33528769 Bytes = 32742.94 KiB = 31.98 MiB
222 05:17:38.517174 output: Load Address: 00000000
223 05:17:38.517370 output: Entry Point: 00000000
224 05:17:38.517567 output:
225 05:17:38.518236 rename /var/lib/lava/dispatcher/tmp/681597/extract-overlay-ramdisk-1l8694kf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/ramdisk/ramdisk.cpio.gz.uboot
226 05:17:38.518652 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 05:17:38.518933 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
228 05:17:38.519206 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 05:17:38.519459 No LXC device requested
230 05:17:38.519710 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:17:38.519967 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 05:17:38.520530 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:17:38.520983 Checking files for TFTP limit of 4294967296 bytes.
234 05:17:38.523906 end: 1 tftp-deploy (duration 00:00:22) [common]
235 05:17:38.524626 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:17:38.525206 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:17:38.525752 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:17:38.526298 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:17:38.526875 Using kernel file from prepare-kernel: 681597/tftp-deploy-cm5c6kqm/kernel/uImage
240 05:17:38.527551 substitutions:
241 05:17:38.528028 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:17:38.528480 - {DTB_ADDR}: 0x01070000
243 05:17:38.528922 - {DTB}: 681597/tftp-deploy-cm5c6kqm/dtb/meson-g12b-a311d-libretech-cc.dtb
244 05:17:38.529362 - {INITRD}: 681597/tftp-deploy-cm5c6kqm/ramdisk/ramdisk.cpio.gz.uboot
245 05:17:38.529799 - {KERNEL_ADDR}: 0x01080000
246 05:17:38.530232 - {KERNEL}: 681597/tftp-deploy-cm5c6kqm/kernel/uImage
247 05:17:38.530665 - {LAVA_MAC}: None
248 05:17:38.531136 - {PRESEED_CONFIG}: None
249 05:17:38.531569 - {PRESEED_LOCAL}: None
250 05:17:38.532017 - {RAMDISK_ADDR}: 0x08000000
251 05:17:38.532452 - {RAMDISK}: 681597/tftp-deploy-cm5c6kqm/ramdisk/ramdisk.cpio.gz.uboot
252 05:17:38.532888 - {ROOT_PART}: None
253 05:17:38.533318 - {ROOT}: None
254 05:17:38.533747 - {SERVER_IP}: 192.168.6.2
255 05:17:38.534179 - {TEE_ADDR}: 0x83000000
256 05:17:38.534607 - {TEE}: None
257 05:17:38.535037 Parsed boot commands:
258 05:17:38.535451 - setenv autoload no
259 05:17:38.535878 - setenv initrd_high 0xffffffff
260 05:17:38.536333 - setenv fdt_high 0xffffffff
261 05:17:38.536765 - dhcp
262 05:17:38.537191 - setenv serverip 192.168.6.2
263 05:17:38.537615 - tftpboot 0x01080000 681597/tftp-deploy-cm5c6kqm/kernel/uImage
264 05:17:38.538045 - tftpboot 0x08000000 681597/tftp-deploy-cm5c6kqm/ramdisk/ramdisk.cpio.gz.uboot
265 05:17:38.538470 - tftpboot 0x01070000 681597/tftp-deploy-cm5c6kqm/dtb/meson-g12b-a311d-libretech-cc.dtb
266 05:17:38.538897 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:17:38.539327 - bootm 0x01080000 0x08000000 0x01070000
268 05:17:38.539858 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:17:38.541502 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:17:38.541979 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 05:17:38.557489 Setting prompt string to ['lava-test: # ']
273 05:17:38.559091 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:17:38.559757 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:17:38.560396 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:17:38.560955 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:17:38.562191 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 05:17:38.599227 >> OK - accepted request
279 05:17:38.601353 Returned 0 in 0 seconds
280 05:17:38.702565 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:17:38.704444 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:17:38.705075 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:17:38.705634 Setting prompt string to ['Hit any key to stop autoboot']
285 05:17:38.706130 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:17:38.707849 Trying 192.168.56.21...
287 05:17:38.708420 Connected to conserv1.
288 05:17:38.708883 Escape character is '^]'.
289 05:17:38.709349
290 05:17:38.709818 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 05:17:38.710301
292 05:17:49.998779 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 05:17:49.999453 bl2_stage_init 0x01
294 05:17:49.999915 bl2_stage_init 0x81
295 05:17:50.004348 hw id: 0x0000 - pwm id 0x01
296 05:17:50.004878 bl2_stage_init 0xc1
297 05:17:50.005335 bl2_stage_init 0x02
298 05:17:50.005786
299 05:17:50.009922 L0:00000000
300 05:17:50.010408 L1:20000703
301 05:17:50.010843 L2:00008067
302 05:17:50.011271 L3:14000000
303 05:17:50.015581 B2:00402000
304 05:17:50.016085 B1:e0f83180
305 05:17:50.016522
306 05:17:50.016955 TE: 58167
307 05:17:50.017389
308 05:17:50.021208 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 05:17:50.021682
310 05:17:50.022115 Board ID = 1
311 05:17:50.027038 Set A53 clk to 24M
312 05:17:50.027509 Set A73 clk to 24M
313 05:17:50.027939 Set clk81 to 24M
314 05:17:50.032329 A53 clk: 1200 MHz
315 05:17:50.032794 A73 clk: 1200 MHz
316 05:17:50.033228 CLK81: 166.6M
317 05:17:50.033657 smccc: 00012abd
318 05:17:50.037906 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 05:17:50.043548 board id: 1
320 05:17:50.049452 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:17:50.059964 fw parse done
322 05:17:50.065851 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:17:50.108464 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:17:50.119370 PIEI prepare done
325 05:17:50.119842 fastboot data load
326 05:17:50.120326 fastboot data verify
327 05:17:50.125161 verify result: 266
328 05:17:50.130755 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 05:17:50.131271 LPDDR4 probe
330 05:17:50.131711 ddr clk to 1584MHz
331 05:17:50.138660 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:17:50.175976
333 05:17:50.176529 dmc_version 0001
334 05:17:50.182641 Check phy result
335 05:17:50.188503 INFO : End of CA training
336 05:17:50.189011 INFO : End of initialization
337 05:17:50.194152 INFO : Training has run successfully!
338 05:17:50.194648 Check phy result
339 05:17:50.199768 INFO : End of initialization
340 05:17:50.200289 INFO : End of read enable training
341 05:17:50.205275 INFO : End of fine write leveling
342 05:17:50.210912 INFO : End of Write leveling coarse delay
343 05:17:50.211411 INFO : Training has run successfully!
344 05:17:50.211850 Check phy result
345 05:17:50.216531 INFO : End of initialization
346 05:17:50.217027 INFO : End of read dq deskew training
347 05:17:50.222126 INFO : End of MPR read delay center optimization
348 05:17:50.227651 INFO : End of write delay center optimization
349 05:17:50.233317 INFO : End of read delay center optimization
350 05:17:50.233821 INFO : End of max read latency training
351 05:17:50.238938 INFO : Training has run successfully!
352 05:17:50.239445 1D training succeed
353 05:17:50.248185 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:17:50.296157 Check phy result
355 05:17:50.296733 INFO : End of initialization
356 05:17:50.317228 INFO : End of 2D read delay Voltage center optimization
357 05:17:50.337377 INFO : End of 2D read delay Voltage center optimization
358 05:17:50.389274 INFO : End of 2D write delay Voltage center optimization
359 05:17:50.438520 INFO : End of 2D write delay Voltage center optimization
360 05:17:50.444175 INFO : Training has run successfully!
361 05:17:50.444594
362 05:17:50.444934 channel==0
363 05:17:50.449652 RxClkDly_Margin_A0==88 ps 9
364 05:17:50.450082 TxDqDly_Margin_A0==98 ps 10
365 05:17:50.455207 RxClkDly_Margin_A1==88 ps 9
366 05:17:50.455581 TxDqDly_Margin_A1==98 ps 10
367 05:17:50.455817 TrainedVREFDQ_A0==74
368 05:17:50.460797 TrainedVREFDQ_A1==76
369 05:17:50.461180 VrefDac_Margin_A0==25
370 05:17:50.461492 DeviceVref_Margin_A0==40
371 05:17:50.466450 VrefDac_Margin_A1==25
372 05:17:50.466799 DeviceVref_Margin_A1==38
373 05:17:50.467008
374 05:17:50.467211
375 05:17:50.472118 channel==1
376 05:17:50.472560 RxClkDly_Margin_A0==98 ps 10
377 05:17:50.472960 TxDqDly_Margin_A0==98 ps 10
378 05:17:50.477578 RxClkDly_Margin_A1==88 ps 9
379 05:17:50.478005 TxDqDly_Margin_A1==88 ps 9
380 05:17:50.483171 TrainedVREFDQ_A0==77
381 05:17:50.483619 TrainedVREFDQ_A1==77
382 05:17:50.484099 VrefDac_Margin_A0==22
383 05:17:50.488758 DeviceVref_Margin_A0==37
384 05:17:50.489188 VrefDac_Margin_A1==24
385 05:17:50.494391 DeviceVref_Margin_A1==37
386 05:17:50.494825
387 05:17:50.495227 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:17:50.495620
389 05:17:50.528105 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 05:17:50.528657 2D training succeed
391 05:17:50.533596 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:17:50.539254 auto size-- 65535DDR cs0 size: 2048MB
393 05:17:50.539686 DDR cs1 size: 2048MB
394 05:17:50.544794 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:17:50.545220 cs0 DataBus test pass
396 05:17:50.550421 cs1 DataBus test pass
397 05:17:50.550844 cs0 AddrBus test pass
398 05:17:50.551236 cs1 AddrBus test pass
399 05:17:50.551624
400 05:17:50.556098 100bdlr_step_size ps== 432
401 05:17:50.556538 result report
402 05:17:50.561606 boot times 0Enable ddr reg access
403 05:17:50.566940 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:17:50.579487 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 05:17:51.152385 0.0;M3 CHK:0;cm4_sp_mode 0
406 05:17:51.152976 MVN_1=0x00000000
407 05:17:51.157900 MVN_2=0x00000000
408 05:17:51.163646 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 05:17:51.164120 OPS=0x10
410 05:17:51.164526 ring efuse init
411 05:17:51.164945 chipver efuse init
412 05:17:51.169348 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 05:17:51.174921 [0.018961 Inits done]
414 05:17:51.175358 secure task start!
415 05:17:51.175758 high task start!
416 05:17:51.179495 low task start!
417 05:17:51.179924 run into bl31
418 05:17:51.186118 NOTICE: BL31: v1.3(release):4fc40b1
419 05:17:51.192955 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 05:17:51.193403 NOTICE: BL31: G12A normal boot!
421 05:17:51.219756 NOTICE: BL31: BL33 decompress pass
422 05:17:51.225459 ERROR: Error initializing runtime service opteed_fast
423 05:17:52.458521
424 05:17:52.459183
425 05:17:52.466783 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 05:17:52.467317
427 05:17:52.467745 Model: Libre Computer AML-A311D-CC Alta
428 05:17:52.674268 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 05:17:52.698554 DRAM: 2 GiB (effective 3.8 GiB)
430 05:17:52.841613 Core: 408 devices, 31 uclasses, devicetree: separate
431 05:17:52.847475 WDT: Not starting watchdog@f0d0
432 05:17:52.879713 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 05:17:52.892258 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 05:17:52.897168 ** Bad device specification mmc 0 **
435 05:17:52.907651 Card did not respond to voltage select! : -110
436 05:17:52.915148 ** Bad device specification mmc 0 **
437 05:17:52.915660 Couldn't find partition mmc 0
438 05:17:52.923467 Card did not respond to voltage select! : -110
439 05:17:52.928945 ** Bad device specification mmc 0 **
440 05:17:52.929424 Couldn't find partition mmc 0
441 05:17:52.934032 Error: could not access storage.
442 05:17:54.199103 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 05:17:54.199743 bl2_stage_init 0x01
444 05:17:54.200277 bl2_stage_init 0x81
445 05:17:54.204583 hw id: 0x0000 - pwm id 0x01
446 05:17:54.205093 bl2_stage_init 0xc1
447 05:17:54.205554 bl2_stage_init 0x02
448 05:17:54.206008
449 05:17:54.210215 L0:00000000
450 05:17:54.210709 L1:20000703
451 05:17:54.211161 L2:00008067
452 05:17:54.211609 L3:14000000
453 05:17:54.215798 B2:00402000
454 05:17:54.216318 B1:e0f83180
455 05:17:54.216774
456 05:17:54.217224 TE: 58167
457 05:17:54.217676
458 05:17:54.221320 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 05:17:54.221840
460 05:17:54.222302 Board ID = 1
461 05:17:54.227009 Set A53 clk to 24M
462 05:17:54.227505 Set A73 clk to 24M
463 05:17:54.227957 Set clk81 to 24M
464 05:17:54.232684 A53 clk: 1200 MHz
465 05:17:54.233179 A73 clk: 1200 MHz
466 05:17:54.233636 CLK81: 166.6M
467 05:17:54.234083 smccc: 00012abe
468 05:17:54.238262 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 05:17:54.243751 board id: 1
470 05:17:54.248761 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 05:17:54.260410 fw parse done
472 05:17:54.265486 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 05:17:54.308038 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 05:17:54.319910 PIEI prepare done
475 05:17:54.320432 fastboot data load
476 05:17:54.320893 fastboot data verify
477 05:17:54.325441 verify result: 266
478 05:17:54.331110 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 05:17:54.331603 LPDDR4 probe
480 05:17:54.332090 ddr clk to 1584MHz
481 05:17:54.338075 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 05:17:54.375664
483 05:17:54.376188 dmc_version 0001
484 05:17:54.382110 Check phy result
485 05:17:54.389004 INFO : End of CA training
486 05:17:54.389334 INFO : End of initialization
487 05:17:54.394530 INFO : Training has run successfully!
488 05:17:54.395033 Check phy result
489 05:17:54.400253 INFO : End of initialization
490 05:17:54.400739 INFO : End of read enable training
491 05:17:54.405839 INFO : End of fine write leveling
492 05:17:54.411420 INFO : End of Write leveling coarse delay
493 05:17:54.411909 INFO : Training has run successfully!
494 05:17:54.412411 Check phy result
495 05:17:54.416929 INFO : End of initialization
496 05:17:54.417416 INFO : End of read dq deskew training
497 05:17:54.422530 INFO : End of MPR read delay center optimization
498 05:17:54.428111 INFO : End of write delay center optimization
499 05:17:54.433615 INFO : End of read delay center optimization
500 05:17:54.434107 INFO : End of max read latency training
501 05:17:54.439237 INFO : Training has run successfully!
502 05:17:54.439714 1D training succeed
503 05:17:54.448444 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 05:17:54.496113 Check phy result
505 05:17:54.496415 INFO : End of initialization
506 05:17:54.517847 INFO : End of 2D read delay Voltage center optimization
507 05:17:54.537976 INFO : End of 2D read delay Voltage center optimization
508 05:17:54.589709 INFO : End of 2D write delay Voltage center optimization
509 05:17:54.639813 INFO : End of 2D write delay Voltage center optimization
510 05:17:54.645550 INFO : Training has run successfully!
511 05:17:54.645838
512 05:17:54.646050 channel==0
513 05:17:54.650619 RxClkDly_Margin_A0==88 ps 9
514 05:17:54.651289 TxDqDly_Margin_A0==98 ps 10
515 05:17:54.656289 RxClkDly_Margin_A1==88 ps 9
516 05:17:54.656904 TxDqDly_Margin_A1==98 ps 10
517 05:17:54.657399 TrainedVREFDQ_A0==74
518 05:17:54.661827 TrainedVREFDQ_A1==74
519 05:17:54.662376 VrefDac_Margin_A0==25
520 05:17:54.662848 DeviceVref_Margin_A0==40
521 05:17:54.667434 VrefDac_Margin_A1==25
522 05:17:54.667937 DeviceVref_Margin_A1==40
523 05:17:54.668445
524 05:17:54.668906
525 05:17:54.672976 channel==1
526 05:17:54.673476 RxClkDly_Margin_A0==98 ps 10
527 05:17:54.673939 TxDqDly_Margin_A0==98 ps 10
528 05:17:54.678705 RxClkDly_Margin_A1==98 ps 10
529 05:17:54.679210 TxDqDly_Margin_A1==88 ps 9
530 05:17:54.684250 TrainedVREFDQ_A0==77
531 05:17:54.684802 TrainedVREFDQ_A1==77
532 05:17:54.685273 VrefDac_Margin_A0==22
533 05:17:54.689815 DeviceVref_Margin_A0==37
534 05:17:54.690328 VrefDac_Margin_A1==22
535 05:17:54.695430 DeviceVref_Margin_A1==37
536 05:17:54.695948
537 05:17:54.696455 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 05:17:54.701079
539 05:17:54.729126 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 05:17:54.729772 2D training succeed
541 05:17:54.734850 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 05:17:54.740264 auto size-- 65535DDR cs0 size: 2048MB
543 05:17:54.740900 DDR cs1 size: 2048MB
544 05:17:54.745854 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 05:17:54.746474 cs0 DataBus test pass
546 05:17:54.751413 cs1 DataBus test pass
547 05:17:54.751960 cs0 AddrBus test pass
548 05:17:54.752484 cs1 AddrBus test pass
549 05:17:54.752944
550 05:17:54.756993 100bdlr_step_size ps== 420
551 05:17:54.757512 result report
552 05:17:54.762638 boot times 0Enable ddr reg access
553 05:17:54.767363 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 05:17:54.781511 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 05:17:55.355088 0.0;M3 CHK:0;cm4_sp_mode 0
556 05:17:55.355730 MVN_1=0x00000000
557 05:17:55.360766 MVN_2=0x00000000
558 05:17:55.366411 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 05:17:55.366965 OPS=0x10
560 05:17:55.367437 ring efuse init
561 05:17:55.367911 chipver efuse init
562 05:17:55.374719 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 05:17:55.375295 [0.018961 Inits done]
564 05:17:55.382114 secure task start!
565 05:17:55.382587 high task start!
566 05:17:55.383019 low task start!
567 05:17:55.383447 run into bl31
568 05:17:55.388834 NOTICE: BL31: v1.3(release):4fc40b1
569 05:17:55.396661 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 05:17:55.397154 NOTICE: BL31: G12A normal boot!
571 05:17:55.422023 NOTICE: BL31: BL33 decompress pass
572 05:17:55.427679 ERROR: Error initializing runtime service opteed_fast
573 05:17:56.660604
574 05:17:56.661268
575 05:17:56.668987 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 05:17:56.669504
577 05:17:56.669968 Model: Libre Computer AML-A311D-CC Alta
578 05:17:56.876617 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 05:17:56.900940 DRAM: 2 GiB (effective 3.8 GiB)
580 05:17:57.043951 Core: 408 devices, 31 uclasses, devicetree: separate
581 05:17:57.048779 WDT: Not starting watchdog@f0d0
582 05:17:57.082569 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 05:17:57.094462 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 05:17:57.099409 ** Bad device specification mmc 0 **
585 05:17:57.109709 Card did not respond to voltage select! : -110
586 05:17:57.116982 ** Bad device specification mmc 0 **
587 05:17:57.117514 Couldn't find partition mmc 0
588 05:17:57.125672 Card did not respond to voltage select! : -110
589 05:17:57.131157 ** Bad device specification mmc 0 **
590 05:17:57.131675 Couldn't find partition mmc 0
591 05:17:57.136255 Error: could not access storage.
592 05:17:57.477775 Net: eth0: ethernet@ff3f0000
593 05:17:57.478394 starting USB...
594 05:17:57.730466 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 05:17:57.731097 Starting the controller
596 05:17:57.737390 USB XHCI 1.10
597 05:17:59.582517 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 05:17:59.583161 bl2_stage_init 0x01
599 05:17:59.583625 bl2_stage_init 0x81
600 05:17:59.584170 hw id: 0x0000 - pwm id 0x01
601 05:17:59.584639 bl2_stage_init 0xc1
602 05:17:59.585086 bl2_stage_init 0x02
603 05:17:59.585531
604 05:17:59.585983 L0:00000000
605 05:17:59.586427 L1:20000703
606 05:17:59.586865 L2:00008067
607 05:17:59.587305 L3:14000000
608 05:17:59.587737 B2:00402000
609 05:17:59.588199 B1:e0f83180
610 05:17:59.588639
611 05:17:59.589081 TE: 58124
612 05:17:59.589523
613 05:17:59.589963 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 05:17:59.590406
615 05:17:59.590843 Board ID = 1
616 05:17:59.591276 Set A53 clk to 24M
617 05:17:59.591709 Set A73 clk to 24M
618 05:17:59.592169 Set clk81 to 24M
619 05:17:59.592610 A53 clk: 1200 MHz
620 05:17:59.593047 A73 clk: 1200 MHz
621 05:17:59.593483 CLK81: 166.6M
622 05:17:59.593919 smccc: 00012a92
623 05:17:59.594349 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 05:17:59.594786 board id: 1
625 05:17:59.595221 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 05:17:59.595655 fw parse done
627 05:17:59.596121 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 05:17:59.596569 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 05:17:59.597008 PIEI prepare done
630 05:17:59.597442 fastboot data load
631 05:17:59.597878 fastboot data verify
632 05:17:59.598310 verify result: 266
633 05:17:59.598739 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 05:17:59.599177 LPDDR4 probe
635 05:17:59.599602 ddr clk to 1584MHz
636 05:17:59.600450 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 05:17:59.626474
638 05:17:59.626981 dmc_version 0001
639 05:17:59.633167 Check phy result
640 05:17:59.639138 INFO : End of CA training
641 05:17:59.639619 INFO : End of initialization
642 05:17:59.644612 INFO : Training has run successfully!
643 05:17:59.645099 Check phy result
644 05:17:59.650223 INFO : End of initialization
645 05:17:59.650700 INFO : End of read enable training
646 05:17:59.653566 INFO : End of fine write leveling
647 05:17:59.659144 INFO : End of Write leveling coarse delay
648 05:17:59.664719 INFO : Training has run successfully!
649 05:17:59.665194 Check phy result
650 05:17:59.665643 INFO : End of initialization
651 05:17:59.670371 INFO : End of read dq deskew training
652 05:17:59.675965 INFO : End of MPR read delay center optimization
653 05:17:59.676475 INFO : End of write delay center optimization
654 05:17:59.681520 INFO : End of read delay center optimization
655 05:17:59.687113 INFO : End of max read latency training
656 05:17:59.687586 INFO : Training has run successfully!
657 05:17:59.692751 1D training succeed
658 05:17:59.698587 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 05:17:59.746497 Check phy result
660 05:17:59.747103 INFO : End of initialization
661 05:17:59.767916 INFO : End of 2D read delay Voltage center optimization
662 05:17:59.788245 INFO : End of 2D read delay Voltage center optimization
663 05:17:59.840238 INFO : End of 2D write delay Voltage center optimization
664 05:17:59.889586 INFO : End of 2D write delay Voltage center optimization
665 05:17:59.895124 INFO : Training has run successfully!
666 05:17:59.895612
667 05:17:59.896148 channel==0
668 05:17:59.900726 RxClkDly_Margin_A0==88 ps 9
669 05:17:59.901211 TxDqDly_Margin_A0==98 ps 10
670 05:17:59.906344 RxClkDly_Margin_A1==88 ps 9
671 05:17:59.906820 TxDqDly_Margin_A1==98 ps 10
672 05:17:59.907275 TrainedVREFDQ_A0==74
673 05:17:59.911919 TrainedVREFDQ_A1==74
674 05:17:59.912435 VrefDac_Margin_A0==25
675 05:17:59.912881 DeviceVref_Margin_A0==40
676 05:17:59.917542 VrefDac_Margin_A1==25
677 05:17:59.918018 DeviceVref_Margin_A1==40
678 05:17:59.918459
679 05:17:59.918901
680 05:17:59.923135 channel==1
681 05:17:59.923615 RxClkDly_Margin_A0==98 ps 10
682 05:17:59.924088 TxDqDly_Margin_A0==88 ps 9
683 05:17:59.928740 RxClkDly_Margin_A1==98 ps 10
684 05:17:59.929216 TxDqDly_Margin_A1==88 ps 9
685 05:17:59.934333 TrainedVREFDQ_A0==76
686 05:17:59.934810 TrainedVREFDQ_A1==77
687 05:17:59.935259 VrefDac_Margin_A0==22
688 05:17:59.940001 DeviceVref_Margin_A0==38
689 05:17:59.940475 VrefDac_Margin_A1==22
690 05:17:59.945525 DeviceVref_Margin_A1==37
691 05:17:59.946016
692 05:17:59.946469 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 05:17:59.946929
694 05:17:59.979164 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
695 05:17:59.979743 2D training succeed
696 05:17:59.984706 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 05:17:59.990316 auto size-- 65535DDR cs0 size: 2048MB
698 05:17:59.990796 DDR cs1 size: 2048MB
699 05:17:59.995908 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 05:17:59.996428 cs0 DataBus test pass
701 05:18:00.001528 cs1 DataBus test pass
702 05:18:00.002008 cs0 AddrBus test pass
703 05:18:00.002453 cs1 AddrBus test pass
704 05:18:00.002909
705 05:18:00.007138 100bdlr_step_size ps== 420
706 05:18:00.007628 result report
707 05:18:00.012761 boot times 0Enable ddr reg access
708 05:18:00.017210 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 05:18:00.031641 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 05:18:00.605647 0.0;M3 CHK:0;cm4_sp_mode 0
711 05:18:00.606468 MVN_1=0x00000000
712 05:18:00.610936 MVN_2=0x00000000
713 05:18:00.616846 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 05:18:00.617599 OPS=0x10
715 05:18:00.618229 ring efuse init
716 05:18:00.618831 chipver efuse init
717 05:18:00.625136 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 05:18:00.625812 [0.018961 Inits done]
719 05:18:00.626406 secure task start!
720 05:18:00.632434 high task start!
721 05:18:00.633143 low task start!
722 05:18:00.633754 run into bl31
723 05:18:00.639133 NOTICE: BL31: v1.3(release):4fc40b1
724 05:18:00.646908 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 05:18:00.647623 NOTICE: BL31: G12A normal boot!
726 05:18:00.672197 NOTICE: BL31: BL33 decompress pass
727 05:18:00.677905 ERROR: Error initializing runtime service opteed_fast
728 05:18:01.911015
729 05:18:01.911887
730 05:18:01.920854 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 05:18:01.921471
732 05:18:01.921921 Model: Libre Computer AML-A311D-CC Alta
733 05:18:02.127767 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 05:18:02.151001 DRAM: 2 GiB (effective 3.8 GiB)
735 05:18:02.293983 Core: 408 devices, 31 uclasses, devicetree: separate
736 05:18:02.299778 WDT: Not starting watchdog@f0d0
737 05:18:02.332074 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 05:18:02.344531 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 05:18:02.349576 ** Bad device specification mmc 0 **
740 05:18:02.360630 Card did not respond to voltage select! : -110
741 05:18:02.367603 ** Bad device specification mmc 0 **
742 05:18:02.367910 Couldn't find partition mmc 0
743 05:18:02.376005 Card did not respond to voltage select! : -110
744 05:18:02.381430 ** Bad device specification mmc 0 **
745 05:18:02.381728 Couldn't find partition mmc 0
746 05:18:02.386466 Error: could not access storage.
747 05:18:02.728944 Net: eth0: ethernet@ff3f0000
748 05:18:02.729368 starting USB...
749 05:18:02.980742 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 05:18:02.981158 Starting the controller
751 05:18:02.987735 USB XHCI 1.10
752 05:18:05.150933 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 05:18:05.151370 bl2_stage_init 0x01
754 05:18:05.151609 bl2_stage_init 0x81
755 05:18:05.156390 hw id: 0x0000 - pwm id 0x01
756 05:18:05.156704 bl2_stage_init 0xc1
757 05:18:05.156932 bl2_stage_init 0x02
758 05:18:05.157143
759 05:18:05.161986 L0:00000000
760 05:18:05.162283 L1:20000703
761 05:18:05.162503 L2:00008067
762 05:18:05.162725 L3:14000000
763 05:18:05.164979 B2:00402000
764 05:18:05.165269 B1:e0f83180
765 05:18:05.165488
766 05:18:05.165712 TE: 58159
767 05:18:05.165940
768 05:18:05.176189 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 05:18:05.176514
770 05:18:05.176735 Board ID = 1
771 05:18:05.176954 Set A53 clk to 24M
772 05:18:05.177166 Set A73 clk to 24M
773 05:18:05.181883 Set clk81 to 24M
774 05:18:05.182182 A53 clk: 1200 MHz
775 05:18:05.182409 A73 clk: 1200 MHz
776 05:18:05.185224 CLK81: 166.6M
777 05:18:05.185510 smccc: 00012ab5
778 05:18:05.190747 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 05:18:05.196362 board id: 1
780 05:18:05.201540 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 05:18:05.212155 fw parse done
782 05:18:05.218126 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 05:18:05.260585 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 05:18:05.271615 PIEI prepare done
785 05:18:05.272076 fastboot data load
786 05:18:05.272348 fastboot data verify
787 05:18:05.277178 verify result: 266
788 05:18:05.282818 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 05:18:05.283431 LPDDR4 probe
790 05:18:05.283864 ddr clk to 1584MHz
791 05:18:05.290904 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 05:18:05.328208
793 05:18:05.328845 dmc_version 0001
794 05:18:05.334812 Check phy result
795 05:18:05.340692 INFO : End of CA training
796 05:18:05.341252 INFO : End of initialization
797 05:18:05.346307 INFO : Training has run successfully!
798 05:18:05.346862 Check phy result
799 05:18:05.351887 INFO : End of initialization
800 05:18:05.352463 INFO : End of read enable training
801 05:18:05.357502 INFO : End of fine write leveling
802 05:18:05.363084 INFO : End of Write leveling coarse delay
803 05:18:05.363646 INFO : Training has run successfully!
804 05:18:05.364117 Check phy result
805 05:18:05.368734 INFO : End of initialization
806 05:18:05.369315 INFO : End of read dq deskew training
807 05:18:05.374265 INFO : End of MPR read delay center optimization
808 05:18:05.379867 INFO : End of write delay center optimization
809 05:18:05.385426 INFO : End of read delay center optimization
810 05:18:05.385957 INFO : End of max read latency training
811 05:18:05.391031 INFO : Training has run successfully!
812 05:18:05.391531 1D training succeed
813 05:18:05.400146 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 05:18:05.447826 Check phy result
815 05:18:05.448385 INFO : End of initialization
816 05:18:05.470394 INFO : End of 2D read delay Voltage center optimization
817 05:18:05.490640 INFO : End of 2D read delay Voltage center optimization
818 05:18:05.542709 INFO : End of 2D write delay Voltage center optimization
819 05:18:05.592116 INFO : End of 2D write delay Voltage center optimization
820 05:18:05.597640 INFO : Training has run successfully!
821 05:18:05.598124
822 05:18:05.598549 channel==0
823 05:18:05.603238 RxClkDly_Margin_A0==88 ps 9
824 05:18:05.603718 TxDqDly_Margin_A0==98 ps 10
825 05:18:05.608860 RxClkDly_Margin_A1==88 ps 9
826 05:18:05.609340 TxDqDly_Margin_A1==98 ps 10
827 05:18:05.609770 TrainedVREFDQ_A0==74
828 05:18:05.614507 TrainedVREFDQ_A1==74
829 05:18:05.615014 VrefDac_Margin_A0==25
830 05:18:05.615434 DeviceVref_Margin_A0==40
831 05:18:05.620052 VrefDac_Margin_A1==25
832 05:18:05.620560 DeviceVref_Margin_A1==40
833 05:18:05.620957
834 05:18:05.621359
835 05:18:05.625632 channel==1
836 05:18:05.626105 RxClkDly_Margin_A0==98 ps 10
837 05:18:05.626499 TxDqDly_Margin_A0==98 ps 10
838 05:18:05.631242 RxClkDly_Margin_A1==88 ps 9
839 05:18:05.631714 TxDqDly_Margin_A1==108 ps 11
840 05:18:05.636863 TrainedVREFDQ_A0==77
841 05:18:05.637334 TrainedVREFDQ_A1==78
842 05:18:05.637727 VrefDac_Margin_A0==22
843 05:18:05.642431 DeviceVref_Margin_A0==37
844 05:18:05.642891 VrefDac_Margin_A1==24
845 05:18:05.648059 DeviceVref_Margin_A1==36
846 05:18:05.648517
847 05:18:05.648910 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 05:18:05.653601
849 05:18:05.681591 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
850 05:18:05.682129 2D training succeed
851 05:18:05.687213 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 05:18:05.692874 auto size-- 65535DDR cs0 size: 2048MB
853 05:18:05.693341 DDR cs1 size: 2048MB
854 05:18:05.698418 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 05:18:05.698886 cs0 DataBus test pass
856 05:18:05.704089 cs1 DataBus test pass
857 05:18:05.704558 cs0 AddrBus test pass
858 05:18:05.704955 cs1 AddrBus test pass
859 05:18:05.705343
860 05:18:05.709598 100bdlr_step_size ps== 420
861 05:18:05.710069 result report
862 05:18:05.715189 boot times 0Enable ddr reg access
863 05:18:05.720746 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 05:18:05.734189 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 05:18:06.307819 0.0;M3 CHK:0;cm4_sp_mode 0
866 05:18:06.308485 MVN_1=0x00000000
867 05:18:06.313354 MVN_2=0x00000000
868 05:18:06.319075 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 05:18:06.319562 OPS=0x10
870 05:18:06.320008 ring efuse init
871 05:18:06.320424 chipver efuse init
872 05:18:06.324693 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 05:18:06.330269 [0.018961 Inits done]
874 05:18:06.330742 secure task start!
875 05:18:06.331155 high task start!
876 05:18:06.334944 low task start!
877 05:18:06.335415 run into bl31
878 05:18:06.341559 NOTICE: BL31: v1.3(release):4fc40b1
879 05:18:06.349362 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 05:18:06.349850 NOTICE: BL31: G12A normal boot!
881 05:18:06.374752 NOTICE: BL31: BL33 decompress pass
882 05:18:06.380429 ERROR: Error initializing runtime service opteed_fast
883 05:18:07.613260
884 05:18:07.613920
885 05:18:07.621695 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 05:18:07.622216
887 05:18:07.622686 Model: Libre Computer AML-A311D-CC Alta
888 05:18:07.830124 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 05:18:07.853504 DRAM: 2 GiB (effective 3.8 GiB)
890 05:18:07.996530 Core: 408 devices, 31 uclasses, devicetree: separate
891 05:18:08.002415 WDT: Not starting watchdog@f0d0
892 05:18:08.034657 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 05:18:08.047049 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 05:18:08.052088 ** Bad device specification mmc 0 **
895 05:18:08.062410 Card did not respond to voltage select! : -110
896 05:18:08.070071 ** Bad device specification mmc 0 **
897 05:18:08.070558 Couldn't find partition mmc 0
898 05:18:08.078426 Card did not respond to voltage select! : -110
899 05:18:08.083917 ** Bad device specification mmc 0 **
900 05:18:08.084469 Couldn't find partition mmc 0
901 05:18:08.088958 Error: could not access storage.
902 05:18:08.432531 Net: eth0: ethernet@ff3f0000
903 05:18:08.433162 starting USB...
904 05:18:08.684454 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 05:18:08.685032 Starting the controller
906 05:18:08.691283 USB XHCI 1.10
907 05:18:10.245276 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 05:18:10.253714 scanning usb for storage devices... 0 Storage Device(s) found
910 05:18:10.305219 Hit any key to stop autoboot: 1
911 05:18:10.306043 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 05:18:10.306688 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 05:18:10.307180 Setting prompt string to ['=>']
914 05:18:10.307670 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 05:18:10.321368 0
916 05:18:10.322297 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 05:18:10.322804 Sending with 10 millisecond of delay
919 05:18:11.457469 => setenv autoload no
920 05:18:11.468252 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 05:18:11.473216 setenv autoload no
922 05:18:11.473937 Sending with 10 millisecond of delay
924 05:18:13.271687 => setenv initrd_high 0xffffffff
925 05:18:13.282582 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 05:18:13.283468 setenv initrd_high 0xffffffff
927 05:18:13.284252 Sending with 10 millisecond of delay
929 05:18:14.903650 => setenv fdt_high 0xffffffff
930 05:18:14.914332 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
931 05:18:14.914886 setenv fdt_high 0xffffffff
932 05:18:14.915374 Sending with 10 millisecond of delay
934 05:18:15.206799 => dhcp
935 05:18:15.217367 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 05:18:15.217949 dhcp
937 05:18:15.218207 Speed: 1000, full duplex
938 05:18:15.218436 BOOTP broadcast 1
939 05:18:15.465733 BOOTP broadcast 2
940 05:18:15.966866 BOOTP broadcast 3
941 05:18:15.980399 DHCP client bound to address 192.168.6.33 (763 ms)
942 05:18:15.981234 Sending with 10 millisecond of delay
944 05:18:17.658402 => setenv serverip 192.168.6.2
945 05:18:17.669096 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
946 05:18:17.669822 setenv serverip 192.168.6.2
947 05:18:17.670377 Sending with 10 millisecond of delay
949 05:18:21.397338 => tftpboot 0x01080000 681597/tftp-deploy-cm5c6kqm/kernel/uImage
950 05:18:21.408102 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
951 05:18:21.408942 tftpboot 0x01080000 681597/tftp-deploy-cm5c6kqm/kernel/uImage
952 05:18:21.409375 Speed: 1000, full duplex
953 05:18:21.409784 Using ethernet@ff3f0000 device
954 05:18:21.410715 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
955 05:18:21.416337 Filename '681597/tftp-deploy-cm5c6kqm/kernel/uImage'.
956 05:18:21.420207 Load address: 0x1080000
957 05:18:25.617303 Loading: *################################################## 63 MiB
958 05:18:25.617934 15 MiB/s
959 05:18:25.618372 done
960 05:18:25.621508 Bytes transferred = 66032192 (3ef9240 hex)
961 05:18:25.622326 Sending with 10 millisecond of delay
963 05:18:30.309915 => tftpboot 0x08000000 681597/tftp-deploy-cm5c6kqm/ramdisk/ramdisk.cpio.gz.uboot
964 05:18:30.320696 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:08)
965 05:18:30.321516 tftpboot 0x08000000 681597/tftp-deploy-cm5c6kqm/ramdisk/ramdisk.cpio.gz.uboot
966 05:18:30.321965 Speed: 1000, full duplex
967 05:18:30.322378 Using ethernet@ff3f0000 device
968 05:18:30.323557 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
969 05:18:30.335366 Filename '681597/tftp-deploy-cm5c6kqm/ramdisk/ramdisk.cpio.gz.uboot'.
970 05:18:30.335869 Load address: 0x8000000
971 05:18:32.494760 Loading: *################################################# UDP wrong checksum 00000007 000036b1
972 05:18:37.495150 T UDP wrong checksum 00000007 000036b1
973 05:18:47.497179 T T UDP wrong checksum 00000007 000036b1
974 05:19:07.501079 T T T T UDP wrong checksum 00000007 000036b1
975 05:19:21.799059 T T UDP wrong checksum 000000ff 00003cb9
976 05:19:21.816751 UDP wrong checksum 000000ff 0000cfab
977 05:19:27.505349 T
978 05:19:27.505730 Retry count exceeded; starting again
980 05:19:27.506552 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
983 05:19:27.507712 end: 2.4 uboot-commands (duration 00:01:49) [common]
985 05:19:27.509083 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
987 05:19:27.510081 end: 2 uboot-action (duration 00:01:49) [common]
989 05:19:27.511553 Cleaning after the job
990 05:19:27.512088 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/ramdisk
991 05:19:27.513187 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/kernel
992 05:19:27.569207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/dtb
993 05:19:27.569983 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681597/tftp-deploy-cm5c6kqm/modules
994 05:19:27.599414 start: 4.1 power-off (timeout 00:00:30) [common]
995 05:19:27.600090 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
996 05:19:27.630334 >> OK - accepted request
997 05:19:27.632110 Returned 0 in 0 seconds
998 05:19:27.733232 end: 4.1 power-off (duration 00:00:00) [common]
1000 05:19:27.734147 start: 4.2 read-feedback (timeout 00:10:00) [common]
1001 05:19:27.735013 Listened to connection for namespace 'common' for up to 1s
1002 05:19:28.735049 Finalising connection for namespace 'common'
1003 05:19:28.735651 Disconnecting from shell: Finalise
1004 05:19:28.736065 =>
1005 05:19:28.836910 end: 4.2 read-feedback (duration 00:00:01) [common]
1006 05:19:28.837711 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681597
1007 05:19:29.139312 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681597
1008 05:19:29.140025 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.