Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:14:34.448799 lava-dispatcher, installed at version: 2024.01
2 05:14:34.449646 start: 0 validate
3 05:14:34.450183 Start time: 2024-08-31 05:14:34.450151+00:00 (UTC)
4 05:14:34.450774 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:14:34.451351 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:14:34.498497 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:14:34.499083 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:14:34.534377 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:14:34.535052 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:14:34.572929 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:14:34.573508 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 05:14:34.619754 validate duration: 0.17
14 05:14:34.620724 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:14:34.621081 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:14:34.621402 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:14:34.622033 Not decompressing ramdisk as can be used compressed.
18 05:14:34.622513 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:14:34.622766 saving as /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/ramdisk/rootfs.cpio.gz
20 05:14:34.623033 total size: 8181887 (7 MB)
21 05:14:34.663670 progress 0 % (0 MB)
22 05:14:34.669828 progress 5 % (0 MB)
23 05:14:34.675419 progress 10 % (0 MB)
24 05:14:34.681279 progress 15 % (1 MB)
25 05:14:34.686887 progress 20 % (1 MB)
26 05:14:34.692847 progress 25 % (1 MB)
27 05:14:34.698226 progress 30 % (2 MB)
28 05:14:34.704183 progress 35 % (2 MB)
29 05:14:34.709482 progress 40 % (3 MB)
30 05:14:34.715209 progress 45 % (3 MB)
31 05:14:34.720816 progress 50 % (3 MB)
32 05:14:34.726559 progress 55 % (4 MB)
33 05:14:34.731949 progress 60 % (4 MB)
34 05:14:34.737681 progress 65 % (5 MB)
35 05:14:34.742976 progress 70 % (5 MB)
36 05:14:34.748740 progress 75 % (5 MB)
37 05:14:34.754088 progress 80 % (6 MB)
38 05:14:34.759787 progress 85 % (6 MB)
39 05:14:34.765129 progress 90 % (7 MB)
40 05:14:34.770695 progress 95 % (7 MB)
41 05:14:34.775904 progress 100 % (7 MB)
42 05:14:34.776681 7 MB downloaded in 0.15 s (50.79 MB/s)
43 05:14:34.777245 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:14:34.778149 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:14:34.778445 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:14:34.778717 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:14:34.779260 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/kernel/Image
49 05:14:34.779528 saving as /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/kernel/Image
50 05:14:34.779738 total size: 45308416 (43 MB)
51 05:14:34.779952 No compression specified
52 05:14:34.821575 progress 0 % (0 MB)
53 05:14:34.850376 progress 5 % (2 MB)
54 05:14:34.878802 progress 10 % (4 MB)
55 05:14:34.907089 progress 15 % (6 MB)
56 05:14:34.935405 progress 20 % (8 MB)
57 05:14:34.963292 progress 25 % (10 MB)
58 05:14:34.991182 progress 30 % (12 MB)
59 05:14:35.019090 progress 35 % (15 MB)
60 05:14:35.047704 progress 40 % (17 MB)
61 05:14:35.075663 progress 45 % (19 MB)
62 05:14:35.103491 progress 50 % (21 MB)
63 05:14:35.131950 progress 55 % (23 MB)
64 05:14:35.160906 progress 60 % (25 MB)
65 05:14:35.188804 progress 65 % (28 MB)
66 05:14:35.216788 progress 70 % (30 MB)
67 05:14:35.245344 progress 75 % (32 MB)
68 05:14:35.273025 progress 80 % (34 MB)
69 05:14:35.300224 progress 85 % (36 MB)
70 05:14:35.327435 progress 90 % (38 MB)
71 05:14:35.355374 progress 95 % (41 MB)
72 05:14:35.382774 progress 100 % (43 MB)
73 05:14:35.383476 43 MB downloaded in 0.60 s (71.57 MB/s)
74 05:14:35.383957 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:14:35.384798 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:14:35.385069 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:14:35.385332 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:14:35.385815 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 05:14:35.386087 saving as /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/dtb/meson-g12b-a311d-libretech-cc.dtb
81 05:14:35.386296 total size: 54667 (0 MB)
82 05:14:35.386505 No compression specified
83 05:14:35.426495 progress 59 % (0 MB)
84 05:14:35.427331 progress 100 % (0 MB)
85 05:14:35.427866 0 MB downloaded in 0.04 s (1.25 MB/s)
86 05:14:35.428398 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:14:35.429222 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:14:35.429482 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:14:35.429742 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:14:35.430201 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/modules.tar.xz
92 05:14:35.430434 saving as /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/modules/modules.tar
93 05:14:35.430638 total size: 11496964 (10 MB)
94 05:14:35.430847 Using unxz to decompress xz
95 05:14:35.473355 progress 0 % (0 MB)
96 05:14:35.538867 progress 5 % (0 MB)
97 05:14:35.621355 progress 10 % (1 MB)
98 05:14:35.699523 progress 15 % (1 MB)
99 05:14:35.784680 progress 20 % (2 MB)
100 05:14:35.860845 progress 25 % (2 MB)
101 05:14:35.940841 progress 30 % (3 MB)
102 05:14:36.015779 progress 35 % (3 MB)
103 05:14:36.098566 progress 40 % (4 MB)
104 05:14:36.178130 progress 45 % (4 MB)
105 05:14:36.259530 progress 50 % (5 MB)
106 05:14:36.340146 progress 55 % (6 MB)
107 05:14:36.419730 progress 60 % (6 MB)
108 05:14:36.505982 progress 65 % (7 MB)
109 05:14:36.581881 progress 70 % (7 MB)
110 05:14:36.664488 progress 75 % (8 MB)
111 05:14:36.753792 progress 80 % (8 MB)
112 05:14:36.850136 progress 85 % (9 MB)
113 05:14:36.919441 progress 90 % (9 MB)
114 05:14:36.995846 progress 95 % (10 MB)
115 05:14:37.066184 progress 100 % (10 MB)
116 05:14:37.079796 10 MB downloaded in 1.65 s (6.65 MB/s)
117 05:14:37.080642 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:14:37.082395 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:14:37.082976 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 05:14:37.083545 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 05:14:37.084115 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:14:37.084679 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 05:14:37.085719 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e
125 05:14:37.086578 makedir: /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin
126 05:14:37.087252 makedir: /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/tests
127 05:14:37.087913 makedir: /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/results
128 05:14:37.088612 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-add-keys
129 05:14:37.089620 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-add-sources
130 05:14:37.090608 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-background-process-start
131 05:14:37.091614 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-background-process-stop
132 05:14:37.092711 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-common-functions
133 05:14:37.093693 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-echo-ipv4
134 05:14:37.094657 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-install-packages
135 05:14:37.095605 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-installed-packages
136 05:14:37.096596 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-os-build
137 05:14:37.097550 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-probe-channel
138 05:14:37.098500 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-probe-ip
139 05:14:37.099458 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-target-ip
140 05:14:37.100440 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-target-mac
141 05:14:37.101403 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-target-storage
142 05:14:37.102372 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-test-case
143 05:14:37.103328 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-test-event
144 05:14:37.104299 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-test-feedback
145 05:14:37.105369 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-test-raise
146 05:14:37.106332 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-test-reference
147 05:14:37.107280 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-test-runner
148 05:14:37.108293 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-test-set
149 05:14:37.109274 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-test-shell
150 05:14:37.110238 Updating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-install-packages (oe)
151 05:14:37.111277 Updating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/bin/lava-installed-packages (oe)
152 05:14:37.112189 Creating /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/environment
153 05:14:37.112942 LAVA metadata
154 05:14:37.113466 - LAVA_JOB_ID=681528
155 05:14:37.113937 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:14:37.114636 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 05:14:37.116548 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:14:37.117186 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 05:14:37.117636 skipped lava-vland-overlay
160 05:14:37.118170 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:14:37.118728 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 05:14:37.119196 skipped lava-multinode-overlay
163 05:14:37.119726 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:14:37.120329 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 05:14:37.120804 Loading test definitions
166 05:14:37.121343 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 05:14:37.121778 Using /lava-681528 at stage 0
168 05:14:37.123916 uuid=681528_1.5.2.4.1 testdef=None
169 05:14:37.124297 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:14:37.124566 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 05:14:37.126335 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:14:37.127128 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 05:14:37.129343 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:14:37.130169 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 05:14:37.132322 runner path: /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/0/tests/0_dmesg test_uuid 681528_1.5.2.4.1
178 05:14:37.132865 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:14:37.133627 Creating lava-test-runner.conf files
181 05:14:37.133827 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681528/lava-overlay-fs2rw21e/lava-681528/0 for stage 0
182 05:14:37.134149 - 0_dmesg
183 05:14:37.134488 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:14:37.134764 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 05:14:37.158864 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:14:37.159340 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:14:37.159609 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:14:37.159884 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:14:37.160187 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:14:38.069508 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:14:38.069981 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 05:14:38.070230 extracting modules file /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681528/extract-overlay-ramdisk-hpb2poic/ramdisk
193 05:14:39.392580 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 05:14:39.393030 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 05:14:39.393312 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681528/compress-overlay-mo1x3ba0/overlay-1.5.2.5.tar.gz to ramdisk
196 05:14:39.393526 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681528/compress-overlay-mo1x3ba0/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681528/extract-overlay-ramdisk-hpb2poic/ramdisk
197 05:14:39.423498 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:14:39.423898 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 05:14:39.424208 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 05:14:39.424437 Converting downloaded kernel to a uImage
201 05:14:39.424739 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/kernel/Image /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/kernel/uImage
202 05:14:39.945703 output: Image Name:
203 05:14:39.946104 output: Created: Sat Aug 31 05:14:39 2024
204 05:14:39.946314 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:14:39.946516 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
206 05:14:39.946717 output: Load Address: 01080000
207 05:14:39.946915 output: Entry Point: 01080000
208 05:14:39.947112 output:
209 05:14:39.947442 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 05:14:39.947710 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 05:14:39.948009 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 05:14:39.948281 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:14:39.948544 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 05:14:39.948797 Building ramdisk /var/lib/lava/dispatcher/tmp/681528/extract-overlay-ramdisk-hpb2poic/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681528/extract-overlay-ramdisk-hpb2poic/ramdisk
215 05:14:42.290792 >> 179908 blocks
216 05:14:50.770587 Adding RAMdisk u-boot header.
217 05:14:50.771403 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681528/extract-overlay-ramdisk-hpb2poic/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681528/extract-overlay-ramdisk-hpb2poic/ramdisk.cpio.gz.uboot
218 05:14:51.044434 output: Image Name:
219 05:14:51.044852 output: Created: Sat Aug 31 05:14:50 2024
220 05:14:51.045277 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:14:51.045700 output: Data Size: 25882129 Bytes = 25275.52 KiB = 24.68 MiB
222 05:14:51.046110 output: Load Address: 00000000
223 05:14:51.046513 output: Entry Point: 00000000
224 05:14:51.046906 output:
225 05:14:51.047889 rename /var/lib/lava/dispatcher/tmp/681528/extract-overlay-ramdisk-hpb2poic/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/ramdisk/ramdisk.cpio.gz.uboot
226 05:14:51.048655 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 05:14:51.049220 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 05:14:51.049768 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 05:14:51.050231 No LXC device requested
230 05:14:51.050744 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:14:51.051265 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 05:14:51.051770 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:14:51.052223 Checking files for TFTP limit of 4294967296 bytes.
234 05:14:51.054882 end: 1 tftp-deploy (duration 00:00:16) [common]
235 05:14:51.055459 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:14:51.056018 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:14:51.056539 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:14:51.057076 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:14:51.057611 Using kernel file from prepare-kernel: 681528/tftp-deploy-3wjk8udh/kernel/uImage
240 05:14:51.058227 substitutions:
241 05:14:51.058643 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:14:51.059056 - {DTB_ADDR}: 0x01070000
243 05:14:51.059460 - {DTB}: 681528/tftp-deploy-3wjk8udh/dtb/meson-g12b-a311d-libretech-cc.dtb
244 05:14:51.059867 - {INITRD}: 681528/tftp-deploy-3wjk8udh/ramdisk/ramdisk.cpio.gz.uboot
245 05:14:51.060298 - {KERNEL_ADDR}: 0x01080000
246 05:14:51.060701 - {KERNEL}: 681528/tftp-deploy-3wjk8udh/kernel/uImage
247 05:14:51.061102 - {LAVA_MAC}: None
248 05:14:51.061545 - {PRESEED_CONFIG}: None
249 05:14:51.061950 - {PRESEED_LOCAL}: None
250 05:14:51.062348 - {RAMDISK_ADDR}: 0x08000000
251 05:14:51.062743 - {RAMDISK}: 681528/tftp-deploy-3wjk8udh/ramdisk/ramdisk.cpio.gz.uboot
252 05:14:51.063146 - {ROOT_PART}: None
253 05:14:51.063543 - {ROOT}: None
254 05:14:51.063939 - {SERVER_IP}: 192.168.6.2
255 05:14:51.064370 - {TEE_ADDR}: 0x83000000
256 05:14:51.064771 - {TEE}: None
257 05:14:51.065169 Parsed boot commands:
258 05:14:51.065554 - setenv autoload no
259 05:14:51.065947 - setenv initrd_high 0xffffffff
260 05:14:51.066342 - setenv fdt_high 0xffffffff
261 05:14:51.066732 - dhcp
262 05:14:51.067121 - setenv serverip 192.168.6.2
263 05:14:51.067511 - tftpboot 0x01080000 681528/tftp-deploy-3wjk8udh/kernel/uImage
264 05:14:51.067900 - tftpboot 0x08000000 681528/tftp-deploy-3wjk8udh/ramdisk/ramdisk.cpio.gz.uboot
265 05:14:51.068325 - tftpboot 0x01070000 681528/tftp-deploy-3wjk8udh/dtb/meson-g12b-a311d-libretech-cc.dtb
266 05:14:51.068721 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:14:51.069120 - bootm 0x01080000 0x08000000 0x01070000
268 05:14:51.069619 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:14:51.071115 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:14:51.071571 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 05:14:51.087537 Setting prompt string to ['lava-test: # ']
273 05:14:51.089087 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:14:51.089717 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:14:51.090275 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:14:51.090804 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:14:51.092219 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 05:14:51.128266 >> OK - accepted request
279 05:14:51.130470 Returned 0 in 0 seconds
280 05:14:51.231633 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:14:51.233280 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:14:51.233875 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:14:51.234391 Setting prompt string to ['Hit any key to stop autoboot']
285 05:14:51.234854 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:14:51.236452 Trying 192.168.56.21...
287 05:14:51.236931 Connected to conserv1.
288 05:14:51.237365 Escape character is '^]'.
289 05:14:51.237783
290 05:14:51.238204 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 05:14:51.238633
292 05:15:02.988851 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 05:15:02.989305 bl2_stage_init 0x01
294 05:15:02.989544 bl2_stage_init 0x81
295 05:15:02.994422 hw id: 0x0000 - pwm id 0x01
296 05:15:02.994755 bl2_stage_init 0xc1
297 05:15:02.994990 bl2_stage_init 0x02
298 05:15:02.995210
299 05:15:02.999876 L0:00000000
300 05:15:03.000198 L1:20000703
301 05:15:03.000411 L2:00008067
302 05:15:03.000615 L3:14000000
303 05:15:03.005463 B2:00402000
304 05:15:03.005746 B1:e0f83180
305 05:15:03.005969
306 05:15:03.006179 TE: 58159
307 05:15:03.006385
308 05:15:03.011174 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 05:15:03.011461
310 05:15:03.011673 Board ID = 1
311 05:15:03.016794 Set A53 clk to 24M
312 05:15:03.017102 Set A73 clk to 24M
313 05:15:03.017315 Set clk81 to 24M
314 05:15:03.022219 A53 clk: 1200 MHz
315 05:15:03.022515 A73 clk: 1200 MHz
316 05:15:03.022722 CLK81: 166.6M
317 05:15:03.022928 smccc: 00012ab5
318 05:15:03.027850 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 05:15:03.033494 board id: 1
320 05:15:03.039484 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:15:03.049959 fw parse done
322 05:15:03.055958 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:15:03.098526 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:15:03.109446 PIEI prepare done
325 05:15:03.109762 fastboot data load
326 05:15:03.109973 fastboot data verify
327 05:15:03.115189 verify result: 266
328 05:15:03.120636 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 05:15:03.120954 LPDDR4 probe
330 05:15:03.121167 ddr clk to 1584MHz
331 05:15:03.128609 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:15:03.165989
333 05:15:03.166408 dmc_version 0001
334 05:15:03.172622 Check phy result
335 05:15:03.178483 INFO : End of CA training
336 05:15:03.178973 INFO : End of initialization
337 05:15:03.184212 INFO : Training has run successfully!
338 05:15:03.184562 Check phy result
339 05:15:03.189681 INFO : End of initialization
340 05:15:03.190168 INFO : End of read enable training
341 05:15:03.193005 INFO : End of fine write leveling
342 05:15:03.198519 INFO : End of Write leveling coarse delay
343 05:15:03.204207 INFO : Training has run successfully!
344 05:15:03.204558 Check phy result
345 05:15:03.204787 INFO : End of initialization
346 05:15:03.209753 INFO : End of read dq deskew training
347 05:15:03.215374 INFO : End of MPR read delay center optimization
348 05:15:03.215725 INFO : End of write delay center optimization
349 05:15:03.220991 INFO : End of read delay center optimization
350 05:15:03.226535 INFO : End of max read latency training
351 05:15:03.227031 INFO : Training has run successfully!
352 05:15:03.232223 1D training succeed
353 05:15:03.238135 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:15:03.285703 Check phy result
355 05:15:03.286118 INFO : End of initialization
356 05:15:03.307495 INFO : End of 2D read delay Voltage center optimization
357 05:15:03.327739 INFO : End of 2D read delay Voltage center optimization
358 05:15:03.379830 INFO : End of 2D write delay Voltage center optimization
359 05:15:03.429112 INFO : End of 2D write delay Voltage center optimization
360 05:15:03.434685 INFO : Training has run successfully!
361 05:15:03.435030
362 05:15:03.435250 channel==0
363 05:15:03.440313 RxClkDly_Margin_A0==88 ps 9
364 05:15:03.440648 TxDqDly_Margin_A0==98 ps 10
365 05:15:03.445942 RxClkDly_Margin_A1==88 ps 9
366 05:15:03.446407 TxDqDly_Margin_A1==98 ps 10
367 05:15:03.446767 TrainedVREFDQ_A0==74
368 05:15:03.451538 TrainedVREFDQ_A1==74
369 05:15:03.451870 VrefDac_Margin_A0==25
370 05:15:03.452137 DeviceVref_Margin_A0==40
371 05:15:03.457109 VrefDac_Margin_A1==25
372 05:15:03.457459 DeviceVref_Margin_A1==40
373 05:15:03.457681
374 05:15:03.457901
375 05:15:03.462749 channel==1
376 05:15:03.463089 RxClkDly_Margin_A0==98 ps 10
377 05:15:03.463318 TxDqDly_Margin_A0==98 ps 10
378 05:15:03.468351 RxClkDly_Margin_A1==98 ps 10
379 05:15:03.468708 TxDqDly_Margin_A1==108 ps 11
380 05:15:03.473920 TrainedVREFDQ_A0==77
381 05:15:03.474394 TrainedVREFDQ_A1==78
382 05:15:03.474747 VrefDac_Margin_A0==22
383 05:15:03.479435 DeviceVref_Margin_A0==37
384 05:15:03.479775 VrefDac_Margin_A1==22
385 05:15:03.485093 DeviceVref_Margin_A1==36
386 05:15:03.485428
387 05:15:03.490714 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:15:03.491193
389 05:15:03.518634 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 05:15:03.519221 2D training succeed
391 05:15:03.524211 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:15:03.529825 auto size-- 65535DDR cs0 size: 2048MB
393 05:15:03.530166 DDR cs1 size: 2048MB
394 05:15:03.535364 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:15:03.535830 cs0 DataBus test pass
396 05:15:03.540998 cs1 DataBus test pass
397 05:15:03.541474 cs0 AddrBus test pass
398 05:15:03.541741 cs1 AddrBus test pass
399 05:15:03.541957
400 05:15:03.546596 100bdlr_step_size ps== 420
401 05:15:03.547087 result report
402 05:15:03.552202 boot times 0Enable ddr reg access
403 05:15:03.557819 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:15:03.571276 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 05:15:04.144923 0.0;M3 CHK:0;cm4_sp_mode 0
406 05:15:04.145357 MVN_1=0x00000000
407 05:15:04.150494 MVN_2=0x00000000
408 05:15:04.156251 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 05:15:04.156598 OPS=0x10
410 05:15:04.156822 ring efuse init
411 05:15:04.157026 chipver efuse init
412 05:15:04.161813 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 05:15:04.167391 [0.018961 Inits done]
414 05:15:04.167855 secure task start!
415 05:15:04.168256 high task start!
416 05:15:04.171949 low task start!
417 05:15:04.172424 run into bl31
418 05:15:04.178625 NOTICE: BL31: v1.3(release):4fc40b1
419 05:15:04.186463 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 05:15:04.186799 NOTICE: BL31: G12A normal boot!
421 05:15:04.211799 NOTICE: BL31: BL33 decompress pass
422 05:15:04.217458 ERROR: Error initializing runtime service opteed_fast
423 05:15:05.450338
424 05:15:05.451001
425 05:15:05.458741 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 05:15:05.459308
427 05:15:05.459784 Model: Libre Computer AML-A311D-CC Alta
428 05:15:05.667249 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 05:15:05.690566 DRAM: 2 GiB (effective 3.8 GiB)
430 05:15:05.833574 Core: 408 devices, 31 uclasses, devicetree: separate
431 05:15:05.839381 WDT: Not starting watchdog@f0d0
432 05:15:05.871685 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 05:15:05.884131 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 05:15:05.889162 ** Bad device specification mmc 0 **
435 05:15:05.899486 Card did not respond to voltage select! : -110
436 05:15:05.907026 ** Bad device specification mmc 0 **
437 05:15:05.907575 Couldn't find partition mmc 0
438 05:15:05.915502 Card did not respond to voltage select! : -110
439 05:15:05.920878 ** Bad device specification mmc 0 **
440 05:15:05.921415 Couldn't find partition mmc 0
441 05:15:05.925949 Error: could not access storage.
442 05:15:07.189246 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 05:15:07.189851 bl2_stage_init 0x01
444 05:15:07.190105 bl2_stage_init 0x81
445 05:15:07.194681 hw id: 0x0000 - pwm id 0x01
446 05:15:07.195098 bl2_stage_init 0xc1
447 05:15:07.195601 bl2_stage_init 0x02
448 05:15:07.195928
449 05:15:07.200331 L0:00000000
450 05:15:07.200883 L1:20000703
451 05:15:07.201354 L2:00008067
452 05:15:07.201813 L3:14000000
453 05:15:07.203164 B2:00402000
454 05:15:07.203737 B1:e0f83180
455 05:15:07.204261
456 05:15:07.204725 TE: 58159
457 05:15:07.205184
458 05:15:07.214371 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 05:15:07.214986
460 05:15:07.215479 Board ID = 1
461 05:15:07.215932 Set A53 clk to 24M
462 05:15:07.216426 Set A73 clk to 24M
463 05:15:07.219929 Set clk81 to 24M
464 05:15:07.220563 A53 clk: 1200 MHz
465 05:15:07.221036 A73 clk: 1200 MHz
466 05:15:07.225644 CLK81: 166.6M
467 05:15:07.226219 smccc: 00012ab5
468 05:15:07.231150 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 05:15:07.231725 board id: 1
470 05:15:07.239791 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 05:15:07.250426 fw parse done
472 05:15:07.256381 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 05:15:07.299005 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 05:15:07.309943 PIEI prepare done
475 05:15:07.310540 fastboot data load
476 05:15:07.311132 fastboot data verify
477 05:15:07.315720 verify result: 266
478 05:15:07.321152 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 05:15:07.321733 LPDDR4 probe
480 05:15:07.322481 ddr clk to 1584MHz
481 05:15:07.329141 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 05:15:07.366583
483 05:15:07.367269 dmc_version 0001
484 05:15:07.373076 Check phy result
485 05:15:07.378949 INFO : End of CA training
486 05:15:07.379568 INFO : End of initialization
487 05:15:07.384627 INFO : Training has run successfully!
488 05:15:07.385226 Check phy result
489 05:15:07.390182 INFO : End of initialization
490 05:15:07.390764 INFO : End of read enable training
491 05:15:07.395782 INFO : End of fine write leveling
492 05:15:07.401360 INFO : End of Write leveling coarse delay
493 05:15:07.401881 INFO : Training has run successfully!
494 05:15:07.402341 Check phy result
495 05:15:07.406967 INFO : End of initialization
496 05:15:07.407560 INFO : End of read dq deskew training
497 05:15:07.412531 INFO : End of MPR read delay center optimization
498 05:15:07.418106 INFO : End of write delay center optimization
499 05:15:07.423729 INFO : End of read delay center optimization
500 05:15:07.424339 INFO : End of max read latency training
501 05:15:07.429328 INFO : Training has run successfully!
502 05:15:07.429916 1D training succeed
503 05:15:07.438504 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 05:15:07.486145 Check phy result
505 05:15:07.486722 INFO : End of initialization
506 05:15:07.507810 INFO : End of 2D read delay Voltage center optimization
507 05:15:07.527907 INFO : End of 2D read delay Voltage center optimization
508 05:15:07.579897 INFO : End of 2D write delay Voltage center optimization
509 05:15:07.629060 INFO : End of 2D write delay Voltage center optimization
510 05:15:07.634530 INFO : Training has run successfully!
511 05:15:07.635046
512 05:15:07.635509 channel==0
513 05:15:07.640133 RxClkDly_Margin_A0==88 ps 9
514 05:15:07.640801 TxDqDly_Margin_A0==98 ps 10
515 05:15:07.645793 RxClkDly_Margin_A1==88 ps 9
516 05:15:07.646332 TxDqDly_Margin_A1==98 ps 10
517 05:15:07.646794 TrainedVREFDQ_A0==74
518 05:15:07.651310 TrainedVREFDQ_A1==74
519 05:15:07.651830 VrefDac_Margin_A0==25
520 05:15:07.652336 DeviceVref_Margin_A0==40
521 05:15:07.656972 VrefDac_Margin_A1==25
522 05:15:07.657491 DeviceVref_Margin_A1==40
523 05:15:07.657940
524 05:15:07.658499
525 05:15:07.662574 channel==1
526 05:15:07.663090 RxClkDly_Margin_A0==98 ps 10
527 05:15:07.663643 TxDqDly_Margin_A0==88 ps 9
528 05:15:07.668183 RxClkDly_Margin_A1==98 ps 10
529 05:15:07.668773 TxDqDly_Margin_A1==88 ps 9
530 05:15:07.673777 TrainedVREFDQ_A0==77
531 05:15:07.674298 TrainedVREFDQ_A1==77
532 05:15:07.674757 VrefDac_Margin_A0==22
533 05:15:07.679336 DeviceVref_Margin_A0==37
534 05:15:07.679853 VrefDac_Margin_A1==23
535 05:15:07.684906 DeviceVref_Margin_A1==37
536 05:15:07.685401
537 05:15:07.685852 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 05:15:07.686301
539 05:15:07.718539 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 05:15:07.719142 2D training succeed
541 05:15:07.724146 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 05:15:07.729774 auto size-- 65535DDR cs0 size: 2048MB
543 05:15:07.730303 DDR cs1 size: 2048MB
544 05:15:07.735344 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 05:15:07.735933 cs0 DataBus test pass
546 05:15:07.740996 cs1 DataBus test pass
547 05:15:07.741531 cs0 AddrBus test pass
548 05:15:07.741990 cs1 AddrBus test pass
549 05:15:07.742448
550 05:15:07.746612 100bdlr_step_size ps== 420
551 05:15:07.747176 result report
552 05:15:07.752187 boot times 0Enable ddr reg access
553 05:15:07.757462 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 05:15:07.770967 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 05:15:08.343042 0.0;M3 CHK:0;cm4_sp_mode 0
556 05:15:08.343692 MVN_1=0x00000000
557 05:15:08.348484 MVN_2=0x00000000
558 05:15:08.354244 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 05:15:08.354794 OPS=0x10
560 05:15:08.355275 ring efuse init
561 05:15:08.355757 chipver efuse init
562 05:15:08.359853 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 05:15:08.365410 [0.018961 Inits done]
564 05:15:08.365898 secure task start!
565 05:15:08.366330 high task start!
566 05:15:08.369973 low task start!
567 05:15:08.370445 run into bl31
568 05:15:08.376613 NOTICE: BL31: v1.3(release):4fc40b1
569 05:15:08.384469 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 05:15:08.384952 NOTICE: BL31: G12A normal boot!
571 05:15:08.409874 NOTICE: BL31: BL33 decompress pass
572 05:15:08.415554 ERROR: Error initializing runtime service opteed_fast
573 05:15:09.648575
574 05:15:09.648966
575 05:15:09.656967 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 05:15:09.657420
577 05:15:09.657766 Model: Libre Computer AML-A311D-CC Alta
578 05:15:09.865483 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 05:15:09.888967 DRAM: 2 GiB (effective 3.8 GiB)
580 05:15:10.031886 Core: 408 devices, 31 uclasses, devicetree: separate
581 05:15:10.037773 WDT: Not starting watchdog@f0d0
582 05:15:10.069921 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 05:15:10.082332 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 05:15:10.087380 ** Bad device specification mmc 0 **
585 05:15:10.097725 Card did not respond to voltage select! : -110
586 05:15:10.105325 ** Bad device specification mmc 0 **
587 05:15:10.105634 Couldn't find partition mmc 0
588 05:15:10.113731 Card did not respond to voltage select! : -110
589 05:15:10.119105 ** Bad device specification mmc 0 **
590 05:15:10.119408 Couldn't find partition mmc 0
591 05:15:10.124337 Error: could not access storage.
592 05:15:10.466770 Net: eth0: ethernet@ff3f0000
593 05:15:10.467383 starting USB...
594 05:15:10.718616 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 05:15:10.719031 Starting the controller
596 05:15:10.725457 USB XHCI 1.10
597 05:15:12.438140 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 05:15:12.438813 bl2_stage_init 0x01
599 05:15:12.439345 bl2_stage_init 0x81
600 05:15:12.443532 hw id: 0x0000 - pwm id 0x01
601 05:15:12.444133 bl2_stage_init 0xc1
602 05:15:12.444614 bl2_stage_init 0x02
603 05:15:12.445065
604 05:15:12.449172 L0:00000000
605 05:15:12.449779 L1:20000703
606 05:15:12.450349 L2:00008067
607 05:15:12.450973 L3:14000000
608 05:15:12.454777 B2:00402000
609 05:15:12.455378 B1:e0f83180
610 05:15:12.455957
611 05:15:12.456549 TE: 58124
612 05:15:12.457069
613 05:15:12.460551 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 05:15:12.461143
615 05:15:12.461624 Board ID = 1
616 05:15:12.465952 Set A53 clk to 24M
617 05:15:12.466462 Set A73 clk to 24M
618 05:15:12.466910 Set clk81 to 24M
619 05:15:12.471480 A53 clk: 1200 MHz
620 05:15:12.472006 A73 clk: 1200 MHz
621 05:15:12.472463 CLK81: 166.6M
622 05:15:12.472904 smccc: 00012a92
623 05:15:12.477089 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 05:15:12.482783 board id: 1
625 05:15:12.488657 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 05:15:12.499307 fw parse done
627 05:15:12.505230 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 05:15:12.548030 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 05:15:12.558729 PIEI prepare done
630 05:15:12.559333 fastboot data load
631 05:15:12.559805 fastboot data verify
632 05:15:12.564538 verify result: 266
633 05:15:12.570022 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 05:15:12.570532 LPDDR4 probe
635 05:15:12.570980 ddr clk to 1584MHz
636 05:15:12.578013 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 05:15:12.615336
638 05:15:12.615869 dmc_version 0001
639 05:15:12.621942 Check phy result
640 05:15:12.627713 INFO : End of CA training
641 05:15:12.628281 INFO : End of initialization
642 05:15:12.633407 INFO : Training has run successfully!
643 05:15:12.633907 Check phy result
644 05:15:12.639028 INFO : End of initialization
645 05:15:12.639499 INFO : End of read enable training
646 05:15:12.644520 INFO : End of fine write leveling
647 05:15:12.650151 INFO : End of Write leveling coarse delay
648 05:15:12.650624 INFO : Training has run successfully!
649 05:15:12.651069 Check phy result
650 05:15:12.655817 INFO : End of initialization
651 05:15:12.656317 INFO : End of read dq deskew training
652 05:15:12.661380 INFO : End of MPR read delay center optimization
653 05:15:12.666953 INFO : End of write delay center optimization
654 05:15:12.672527 INFO : End of read delay center optimization
655 05:15:12.673102 INFO : End of max read latency training
656 05:15:12.678163 INFO : Training has run successfully!
657 05:15:12.678646 1D training succeed
658 05:15:12.687353 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 05:15:12.734887 Check phy result
660 05:15:12.735411 INFO : End of initialization
661 05:15:12.756540 INFO : End of 2D read delay Voltage center optimization
662 05:15:12.776848 INFO : End of 2D read delay Voltage center optimization
663 05:15:12.828956 INFO : End of 2D write delay Voltage center optimization
664 05:15:12.878439 INFO : End of 2D write delay Voltage center optimization
665 05:15:12.884018 INFO : Training has run successfully!
666 05:15:12.884510
667 05:15:12.884985 channel==0
668 05:15:12.889614 RxClkDly_Margin_A0==88 ps 9
669 05:15:12.890096 TxDqDly_Margin_A0==98 ps 10
670 05:15:12.895147 RxClkDly_Margin_A1==88 ps 9
671 05:15:12.895620 TxDqDly_Margin_A1==98 ps 10
672 05:15:12.896113 TrainedVREFDQ_A0==74
673 05:15:12.900798 TrainedVREFDQ_A1==74
674 05:15:12.901301 VrefDac_Margin_A0==25
675 05:15:12.901756 DeviceVref_Margin_A0==40
676 05:15:12.906478 VrefDac_Margin_A1==25
677 05:15:12.906977 DeviceVref_Margin_A1==40
678 05:15:12.907426
679 05:15:12.907878
680 05:15:12.911929 channel==1
681 05:15:12.912456 RxClkDly_Margin_A0==98 ps 10
682 05:15:12.912913 TxDqDly_Margin_A0==98 ps 10
683 05:15:12.917611 RxClkDly_Margin_A1==98 ps 10
684 05:15:12.918106 TxDqDly_Margin_A1==98 ps 10
685 05:15:12.923071 TrainedVREFDQ_A0==77
686 05:15:12.923559 TrainedVREFDQ_A1==78
687 05:15:12.924040 VrefDac_Margin_A0==22
688 05:15:12.928692 DeviceVref_Margin_A0==37
689 05:15:12.929179 VrefDac_Margin_A1==22
690 05:15:12.934332 DeviceVref_Margin_A1==36
691 05:15:12.934819
692 05:15:12.935275 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 05:15:12.939891
694 05:15:12.967774 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
695 05:15:12.968355 2D training succeed
696 05:15:12.973470 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 05:15:12.978998 auto size-- 65535DDR cs0 size: 2048MB
698 05:15:12.979491 DDR cs1 size: 2048MB
699 05:15:12.984651 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 05:15:12.985145 cs0 DataBus test pass
701 05:15:12.990232 cs1 DataBus test pass
702 05:15:12.990708 cs0 AddrBus test pass
703 05:15:12.991158 cs1 AddrBus test pass
704 05:15:12.991597
705 05:15:12.995798 100bdlr_step_size ps== 420
706 05:15:12.996314 result report
707 05:15:13.001477 boot times 0Enable ddr reg access
708 05:15:13.006927 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 05:15:13.020537 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 05:15:13.594138 0.0;M3 CHK:0;cm4_sp_mode 0
711 05:15:13.594534 MVN_1=0x00000000
712 05:15:13.599616 MVN_2=0x00000000
713 05:15:13.605289 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 05:15:13.605578 OPS=0x10
715 05:15:13.605786 ring efuse init
716 05:15:13.605982 chipver efuse init
717 05:15:13.610879 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 05:15:13.616506 [0.018961 Inits done]
719 05:15:13.616975 secure task start!
720 05:15:13.617416 high task start!
721 05:15:13.621089 low task start!
722 05:15:13.621553 run into bl31
723 05:15:13.627805 NOTICE: BL31: v1.3(release):4fc40b1
724 05:15:13.635598 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 05:15:13.636111 NOTICE: BL31: G12A normal boot!
726 05:15:13.660881 NOTICE: BL31: BL33 decompress pass
727 05:15:13.666566 ERROR: Error initializing runtime service opteed_fast
728 05:15:14.899520
729 05:15:14.900212
730 05:15:14.906992 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 05:15:14.907516
732 05:15:14.908014 Model: Libre Computer AML-A311D-CC Alta
733 05:15:15.115370 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 05:15:15.138923 DRAM: 2 GiB (effective 3.8 GiB)
735 05:15:15.282824 Core: 408 devices, 31 uclasses, devicetree: separate
736 05:15:15.288717 WDT: Not starting watchdog@f0d0
737 05:15:15.320939 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 05:15:15.333352 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 05:15:15.338362 ** Bad device specification mmc 0 **
740 05:15:15.348669 Card did not respond to voltage select! : -110
741 05:15:15.356361 ** Bad device specification mmc 0 **
742 05:15:15.356854 Couldn't find partition mmc 0
743 05:15:15.364760 Card did not respond to voltage select! : -110
744 05:15:15.370216 ** Bad device specification mmc 0 **
745 05:15:15.370721 Couldn't find partition mmc 0
746 05:15:15.374297 Error: could not access storage.
747 05:15:15.718715 Net: eth0: ethernet@ff3f0000
748 05:15:15.719093 starting USB...
749 05:15:15.970565 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 05:15:15.971157 Starting the controller
751 05:15:15.976640 USB XHCI 1.10
752 05:15:18.138133 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 05:15:18.138734 bl2_stage_init 0x01
754 05:15:18.139161 bl2_stage_init 0x81
755 05:15:18.143775 hw id: 0x0000 - pwm id 0x01
756 05:15:18.144292 bl2_stage_init 0xc1
757 05:15:18.144716 bl2_stage_init 0x02
758 05:15:18.145128
759 05:15:18.149389 L0:00000000
760 05:15:18.149867 L1:20000703
761 05:15:18.150280 L2:00008067
762 05:15:18.150682 L3:14000000
763 05:15:18.152265 B2:00402000
764 05:15:18.152722 B1:e0f83180
765 05:15:18.153140
766 05:15:18.153550 TE: 58159
767 05:15:18.153955
768 05:15:18.163376 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 05:15:18.163858
770 05:15:18.164306 Board ID = 1
771 05:15:18.164711 Set A53 clk to 24M
772 05:15:18.165112 Set A73 clk to 24M
773 05:15:18.169095 Set clk81 to 24M
774 05:15:18.169556 A53 clk: 1200 MHz
775 05:15:18.169967 A73 clk: 1200 MHz
776 05:15:18.172471 CLK81: 166.6M
777 05:15:18.172934 smccc: 00012ab5
778 05:15:18.178090 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 05:15:18.183640 board id: 1
780 05:15:18.188784 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 05:15:18.199497 fw parse done
782 05:15:18.205421 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 05:15:18.248096 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 05:15:18.258938 PIEI prepare done
785 05:15:18.259411 fastboot data load
786 05:15:18.259831 fastboot data verify
787 05:15:18.264511 verify result: 266
788 05:15:18.270109 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 05:15:18.270571 LPDDR4 probe
790 05:15:18.270979 ddr clk to 1584MHz
791 05:15:18.278132 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 05:15:18.315345
793 05:15:18.315833 dmc_version 0001
794 05:15:18.322014 Check phy result
795 05:15:18.327943 INFO : End of CA training
796 05:15:18.328438 INFO : End of initialization
797 05:15:18.333506 INFO : Training has run successfully!
798 05:15:18.333973 Check phy result
799 05:15:18.339107 INFO : End of initialization
800 05:15:18.339570 INFO : End of read enable training
801 05:15:18.344693 INFO : End of fine write leveling
802 05:15:18.350297 INFO : End of Write leveling coarse delay
803 05:15:18.350764 INFO : Training has run successfully!
804 05:15:18.351180 Check phy result
805 05:15:18.355945 INFO : End of initialization
806 05:15:18.356440 INFO : End of read dq deskew training
807 05:15:18.361488 INFO : End of MPR read delay center optimization
808 05:15:18.367111 INFO : End of write delay center optimization
809 05:15:18.372681 INFO : End of read delay center optimization
810 05:15:18.373147 INFO : End of max read latency training
811 05:15:18.378299 INFO : Training has run successfully!
812 05:15:18.378759 1D training succeed
813 05:15:18.387408 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 05:15:18.435057 Check phy result
815 05:15:18.435545 INFO : End of initialization
816 05:15:18.456829 INFO : End of 2D read delay Voltage center optimization
817 05:15:18.477044 INFO : End of 2D read delay Voltage center optimization
818 05:15:18.529073 INFO : End of 2D write delay Voltage center optimization
819 05:15:18.578456 INFO : End of 2D write delay Voltage center optimization
820 05:15:18.584125 INFO : Training has run successfully!
821 05:15:18.584627
822 05:15:18.585058 channel==0
823 05:15:18.589613 RxClkDly_Margin_A0==88 ps 9
824 05:15:18.590082 TxDqDly_Margin_A0==98 ps 10
825 05:15:18.595195 RxClkDly_Margin_A1==88 ps 9
826 05:15:18.595659 TxDqDly_Margin_A1==98 ps 10
827 05:15:18.596120 TrainedVREFDQ_A0==74
828 05:15:18.600825 TrainedVREFDQ_A1==74
829 05:15:18.601333 VrefDac_Margin_A0==25
830 05:15:18.601747 DeviceVref_Margin_A0==40
831 05:15:18.606385 VrefDac_Margin_A1==25
832 05:15:18.606861 DeviceVref_Margin_A1==40
833 05:15:18.607249
834 05:15:18.607640
835 05:15:18.612106 channel==1
836 05:15:18.612561 RxClkDly_Margin_A0==98 ps 10
837 05:15:18.612950 TxDqDly_Margin_A0==88 ps 9
838 05:15:18.617575 RxClkDly_Margin_A1==88 ps 9
839 05:15:18.618025 TxDqDly_Margin_A1==88 ps 9
840 05:15:18.623148 TrainedVREFDQ_A0==77
841 05:15:18.623605 TrainedVREFDQ_A1==77
842 05:15:18.624024 VrefDac_Margin_A0==22
843 05:15:18.628751 DeviceVref_Margin_A0==37
844 05:15:18.629202 VrefDac_Margin_A1==24
845 05:15:18.634376 DeviceVref_Margin_A1==37
846 05:15:18.634835
847 05:15:18.635229 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 05:15:18.635617
849 05:15:18.667893 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 05:15:18.668441 2D training succeed
851 05:15:18.673561 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 05:15:18.679167 auto size-- 65535DDR cs0 size: 2048MB
853 05:15:18.679627 DDR cs1 size: 2048MB
854 05:15:18.684791 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 05:15:18.685247 cs0 DataBus test pass
856 05:15:18.690376 cs1 DataBus test pass
857 05:15:18.690833 cs0 AddrBus test pass
858 05:15:18.691225 cs1 AddrBus test pass
859 05:15:18.691611
860 05:15:18.695960 100bdlr_step_size ps== 420
861 05:15:18.696466 result report
862 05:15:18.701564 boot times 0Enable ddr reg access
863 05:15:18.706808 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 05:15:18.720368 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 05:15:19.296185 0.0;M3 CHK:0;cm4_sp_mode 0
866 05:15:19.296972 MVN_1=0x00000000
867 05:15:19.299507 MVN_2=0x00000000
868 05:15:19.305157 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 05:15:19.305683 OPS=0x10
870 05:15:19.306303 ring efuse init
871 05:15:19.306769 chipver efuse init
872 05:15:19.310786 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 05:15:19.316444 [0.018961 Inits done]
874 05:15:19.317300 secure task start!
875 05:15:19.318218 high task start!
876 05:15:19.321088 low task start!
877 05:15:19.321993 run into bl31
878 05:15:19.327650 NOTICE: BL31: v1.3(release):4fc40b1
879 05:15:19.335413 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 05:15:19.336211 NOTICE: BL31: G12A normal boot!
881 05:15:19.360815 NOTICE: BL31: BL33 decompress pass
882 05:15:19.366417 ERROR: Error initializing runtime service opteed_fast
883 05:15:20.599576
884 05:15:20.600446
885 05:15:20.607863 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 05:15:20.608484
887 05:15:20.608951 Model: Libre Computer AML-A311D-CC Alta
888 05:15:20.816363 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 05:15:20.839645 DRAM: 2 GiB (effective 3.8 GiB)
890 05:15:20.982651 Core: 408 devices, 31 uclasses, devicetree: separate
891 05:15:20.988500 WDT: Not starting watchdog@f0d0
892 05:15:21.020818 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 05:15:21.033281 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 05:15:21.038268 ** Bad device specification mmc 0 **
895 05:15:21.048610 Card did not respond to voltage select! : -110
896 05:15:21.056253 ** Bad device specification mmc 0 **
897 05:15:21.056791 Couldn't find partition mmc 0
898 05:15:21.064612 Card did not respond to voltage select! : -110
899 05:15:21.070104 ** Bad device specification mmc 0 **
900 05:15:21.070648 Couldn't find partition mmc 0
901 05:15:21.075178 Error: could not access storage.
902 05:15:21.418597 Net: eth0: ethernet@ff3f0000
903 05:15:21.419176 starting USB...
904 05:15:21.670482 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 05:15:21.671057 Starting the controller
906 05:15:21.677457 USB XHCI 1.10
907 05:15:23.538178 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 05:15:23.538598 bl2_stage_init 0x01
909 05:15:23.538814 bl2_stage_init 0x81
910 05:15:23.543814 hw id: 0x0000 - pwm id 0x01
911 05:15:23.545363 bl2_stage_init 0xc1
912 05:15:23.547563 bl2_stage_init 0x02
913 05:15:23.548557
914 05:15:23.549952 L0:00000000
915 05:15:23.550469 L1:20000703
916 05:15:23.550896 L2:00008067
917 05:15:23.551312 L3:14000000
918 05:15:23.554775 B2:00402000
919 05:15:23.555249 B1:e0f83180
920 05:15:23.555724
921 05:15:23.556221 TE: 58159
922 05:15:23.556680
923 05:15:23.560446 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 05:15:23.560982
925 05:15:23.561414 Board ID = 1
926 05:15:23.566020 Set A53 clk to 24M
927 05:15:23.566504 Set A73 clk to 24M
928 05:15:23.566920 Set clk81 to 24M
929 05:15:23.571612 A53 clk: 1200 MHz
930 05:15:23.572157 A73 clk: 1200 MHz
931 05:15:23.572585 CLK81: 166.6M
932 05:15:23.572992 smccc: 00012ab5
933 05:15:23.577250 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 05:15:23.582812 board id: 1
935 05:15:23.588741 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 05:15:23.599196 fw parse done
937 05:15:23.605265 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 05:15:23.647782 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 05:15:23.658687 PIEI prepare done
940 05:15:23.659169 fastboot data load
941 05:15:23.659573 fastboot data verify
942 05:15:23.664265 verify result: 266
943 05:15:23.669860 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 05:15:23.670296 LPDDR4 probe
945 05:15:23.670692 ddr clk to 1584MHz
946 05:15:23.679119 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 05:15:23.715131
948 05:15:23.715652 dmc_version 0001
949 05:15:23.721803 Check phy result
950 05:15:23.727628 INFO : End of CA training
951 05:15:23.727921 INFO : End of initialization
952 05:15:23.733286 INFO : Training has run successfully!
953 05:15:23.733904 Check phy result
954 05:15:23.738987 INFO : End of initialization
955 05:15:23.739569 INFO : End of read enable training
956 05:15:23.742199 INFO : End of fine write leveling
957 05:15:23.747790 INFO : End of Write leveling coarse delay
958 05:15:23.753358 INFO : Training has run successfully!
959 05:15:23.753888 Check phy result
960 05:15:23.754491 INFO : End of initialization
961 05:15:23.758943 INFO : End of read dq deskew training
962 05:15:23.764526 INFO : End of MPR read delay center optimization
963 05:15:23.765034 INFO : End of write delay center optimization
964 05:15:23.770165 INFO : End of read delay center optimization
965 05:15:23.775806 INFO : End of max read latency training
966 05:15:23.776435 INFO : Training has run successfully!
967 05:15:23.781368 1D training succeed
968 05:15:23.787332 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 05:15:23.834905 Check phy result
970 05:15:23.835550 INFO : End of initialization
971 05:15:23.856500 INFO : End of 2D read delay Voltage center optimization
972 05:15:23.876629 INFO : End of 2D read delay Voltage center optimization
973 05:15:23.928493 INFO : End of 2D write delay Voltage center optimization
974 05:15:23.977803 INFO : End of 2D write delay Voltage center optimization
975 05:15:23.983336 INFO : Training has run successfully!
976 05:15:23.983917
977 05:15:23.984388 channel==0
978 05:15:23.989012 RxClkDly_Margin_A0==88 ps 9
979 05:15:23.989542 TxDqDly_Margin_A0==98 ps 10
980 05:15:23.994577 RxClkDly_Margin_A1==88 ps 9
981 05:15:23.995103 TxDqDly_Margin_A1==98 ps 10
982 05:15:23.995514 TrainedVREFDQ_A0==74
983 05:15:24.000189 TrainedVREFDQ_A1==74
984 05:15:24.000727 VrefDac_Margin_A0==25
985 05:15:24.001132 DeviceVref_Margin_A0==40
986 05:15:24.005859 VrefDac_Margin_A1==25
987 05:15:24.006372 DeviceVref_Margin_A1==40
988 05:15:24.006774
989 05:15:24.007171
990 05:15:24.011372 channel==1
991 05:15:24.011888 RxClkDly_Margin_A0==98 ps 10
992 05:15:24.012325 TxDqDly_Margin_A0==98 ps 10
993 05:15:24.016979 RxClkDly_Margin_A1==98 ps 10
994 05:15:24.017495 TxDqDly_Margin_A1==88 ps 9
995 05:15:24.022572 TrainedVREFDQ_A0==77
996 05:15:24.023088 TrainedVREFDQ_A1==77
997 05:15:24.023491 VrefDac_Margin_A0==22
998 05:15:24.028195 DeviceVref_Margin_A0==37
999 05:15:24.028739 VrefDac_Margin_A1==22
1000 05:15:24.033868 DeviceVref_Margin_A1==37
1001 05:15:24.034392
1002 05:15:24.034793 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 05:15:24.039358
1004 05:15:24.067314 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1005 05:15:24.067914 2D training succeed
1006 05:15:24.073012 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 05:15:24.078554 auto size-- 65535DDR cs0 size: 2048MB
1008 05:15:24.079089 DDR cs1 size: 2048MB
1009 05:15:24.084158 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 05:15:24.084673 cs0 DataBus test pass
1011 05:15:24.089859 cs1 DataBus test pass
1012 05:15:24.090381 cs0 AddrBus test pass
1013 05:15:24.090788 cs1 AddrBus test pass
1014 05:15:24.091186
1015 05:15:24.095353 100bdlr_step_size ps== 420
1016 05:15:24.095877 result report
1017 05:15:24.100962 boot times 0Enable ddr reg access
1018 05:15:24.106384 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 05:15:24.119880 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 05:15:24.691953 0.0;M3 CHK:0;cm4_sp_mode 0
1021 05:15:24.692708 MVN_1=0x00000000
1022 05:15:24.697419 MVN_2=0x00000000
1023 05:15:24.703166 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 05:15:24.703695 OPS=0x10
1025 05:15:24.704149 ring efuse init
1026 05:15:24.704555 chipver efuse init
1027 05:15:24.708721 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 05:15:24.714321 [0.018960 Inits done]
1029 05:15:24.714812 secure task start!
1030 05:15:24.715211 high task start!
1031 05:15:24.718995 low task start!
1032 05:15:24.719489 run into bl31
1033 05:15:24.725558 NOTICE: BL31: v1.3(release):4fc40b1
1034 05:15:24.733353 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 05:15:24.733853 NOTICE: BL31: G12A normal boot!
1036 05:15:24.758800 NOTICE: BL31: BL33 decompress pass
1037 05:15:24.764455 ERROR: Error initializing runtime service opteed_fast
1038 05:15:25.997270
1039 05:15:25.997895
1040 05:15:26.005731 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 05:15:26.006043
1042 05:15:26.006265 Model: Libre Computer AML-A311D-CC Alta
1043 05:15:26.214194 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 05:15:26.237589 DRAM: 2 GiB (effective 3.8 GiB)
1045 05:15:26.380466 Core: 408 devices, 31 uclasses, devicetree: separate
1046 05:15:26.386950 WDT: Not starting watchdog@f0d0
1047 05:15:26.418606 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 05:15:26.432194 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 05:15:26.436067 ** Bad device specification mmc 0 **
1050 05:15:26.446349 Card did not respond to voltage select! : -110
1051 05:15:26.453997 ** Bad device specification mmc 0 **
1052 05:15:26.454379 Couldn't find partition mmc 0
1053 05:15:26.462407 Card did not respond to voltage select! : -110
1054 05:15:26.467810 ** Bad device specification mmc 0 **
1055 05:15:26.468345 Couldn't find partition mmc 0
1056 05:15:26.472880 Error: could not access storage.
1057 05:15:26.815433 Net: eth0: ethernet@ff3f0000
1058 05:15:26.815906 starting USB...
1059 05:15:27.067305 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 05:15:27.068045 Starting the controller
1061 05:15:27.074117 USB XHCI 1.10
1062 05:15:28.630240 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 05:15:28.638607 scanning usb for storage devices... 0 Storage Device(s) found
1065 05:15:28.690985 Hit any key to stop autoboot: 1
1066 05:15:28.691929 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 05:15:28.692372 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1068 05:15:28.692710 Setting prompt string to ['=>']
1069 05:15:28.693031 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1070 05:15:28.706931 0
1071 05:15:28.708903 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 05:15:28.709600 Sending with 10 millisecond of delay
1074 05:15:29.861634 => setenv autoload no
1075 05:15:29.872209 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 05:15:29.875209 setenv autoload no
1077 05:15:29.875833 Sending with 10 millisecond of delay
1079 05:15:31.672724 => setenv initrd_high 0xffffffff
1080 05:15:31.683530 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1081 05:15:31.684708 setenv initrd_high 0xffffffff
1082 05:15:31.685310 Sending with 10 millisecond of delay
1084 05:15:33.301431 => setenv fdt_high 0xffffffff
1085 05:15:33.312027 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 05:15:33.313958 setenv fdt_high 0xffffffff
1087 05:15:33.315212 Sending with 10 millisecond of delay
1089 05:15:33.607067 => dhcp
1090 05:15:33.617846 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1091 05:15:33.618660 dhcp
1092 05:15:33.619101 Speed: 1000, full duplex
1093 05:15:33.619511 BOOTP broadcast 1
1094 05:15:33.865945 BOOTP broadcast 2
1095 05:15:33.901264 DHCP client bound to address 192.168.6.33 (283 ms)
1096 05:15:33.902097 Sending with 10 millisecond of delay
1098 05:15:35.578547 => setenv serverip 192.168.6.2
1099 05:15:35.589316 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1100 05:15:35.590178 setenv serverip 192.168.6.2
1101 05:15:35.590902 Sending with 10 millisecond of delay
1103 05:15:39.316904 => tftpboot 0x01080000 681528/tftp-deploy-3wjk8udh/kernel/uImage
1104 05:15:39.327757 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1105 05:15:39.328740 tftpboot 0x01080000 681528/tftp-deploy-3wjk8udh/kernel/uImage
1106 05:15:39.329217 Speed: 1000, full duplex
1107 05:15:39.329661 Using ethernet@ff3f0000 device
1108 05:15:39.330432 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1109 05:15:39.336064 Filename '681528/tftp-deploy-3wjk8udh/kernel/uImage'.
1110 05:15:39.339741 Load address: 0x1080000
1111 05:15:42.101372 Loading: *############################################# UDP wrong checksum 000000ff 0000b43a
1112 05:15:42.122092 # UDP wrong checksum 000000ff 00004e2d
1113 05:15:42.356131 #### 43.2 MiB
1114 05:15:42.356752 14.3 MiB/s
1115 05:15:42.357203 done
1116 05:15:42.360643 Bytes transferred = 45308480 (2b35a40 hex)
1117 05:15:42.361426 Sending with 10 millisecond of delay
1119 05:15:47.052070 => tftpboot 0x08000000 681528/tftp-deploy-3wjk8udh/ramdisk/ramdisk.cpio.gz.uboot
1120 05:15:47.062859 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1121 05:15:47.063725 tftpboot 0x08000000 681528/tftp-deploy-3wjk8udh/ramdisk/ramdisk.cpio.gz.uboot
1122 05:15:47.064194 Speed: 1000, full duplex
1123 05:15:47.064599 Using ethernet@ff3f0000 device
1124 05:15:47.065477 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1125 05:15:47.074094 Filename '681528/tftp-deploy-3wjk8udh/ramdisk/ramdisk.cpio.gz.uboot'.
1126 05:15:47.074582 Load address: 0x8000000
1127 05:15:53.802646 Loading: *#############T #################################### UDP wrong checksum 00000005 0000fe29
1128 05:15:58.802335 T UDP wrong checksum 00000005 0000fe29
1129 05:16:08.804390 T T UDP wrong checksum 00000005 0000fe29
1130 05:16:28.808182 T T T T UDP wrong checksum 00000005 0000fe29
1131 05:16:43.812356 T T
1132 05:16:43.812791 Retry count exceeded; starting again
1134 05:16:43.815779 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1137 05:16:43.816836 end: 2.4 uboot-commands (duration 00:01:53) [common]
1139 05:16:43.817586 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1141 05:16:43.818126 end: 2 uboot-action (duration 00:01:53) [common]
1143 05:16:43.818957 Cleaning after the job
1144 05:16:43.819271 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/ramdisk
1145 05:16:43.820137 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/kernel
1146 05:16:43.846371 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/dtb
1147 05:16:43.847250 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681528/tftp-deploy-3wjk8udh/modules
1148 05:16:43.869819 start: 4.1 power-off (timeout 00:00:30) [common]
1149 05:16:43.870468 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1150 05:16:43.903116 >> OK - accepted request
1151 05:16:43.905302 Returned 0 in 0 seconds
1152 05:16:44.006299 end: 4.1 power-off (duration 00:00:00) [common]
1154 05:16:44.007236 start: 4.2 read-feedback (timeout 00:10:00) [common]
1155 05:16:44.007912 Listened to connection for namespace 'common' for up to 1s
1156 05:16:45.008565 Finalising connection for namespace 'common'
1157 05:16:45.009353 Disconnecting from shell: Finalise
1158 05:16:45.009937 =>
1159 05:16:45.110918 end: 4.2 read-feedback (duration 00:00:01) [common]
1160 05:16:45.111409 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681528
1161 05:16:45.372375 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681528
1162 05:16:45.372978 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.