Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:14:14.377435 lava-dispatcher, installed at version: 2024.01
2 05:14:14.378204 start: 0 validate
3 05:14:14.378671 Start time: 2024-08-31 05:14:14.378639+00:00 (UTC)
4 05:14:14.379219 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:14:14.379754 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:14:14.423569 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:14:14.424679 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:14:14.457148 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:14:14.457824 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 05:14:14.489984 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:14:14.490513 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 05:14:14.530612 validate duration: 0.15
14 05:14:14.531499 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:14:14.531838 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:14:14.532173 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:14:14.532777 Not decompressing ramdisk as can be used compressed.
18 05:14:14.533224 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:14:14.533504 saving as /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/ramdisk/rootfs.cpio.gz
20 05:14:14.533786 total size: 8181887 (7 MB)
21 05:14:14.576979 progress 0 % (0 MB)
22 05:14:14.582590 progress 5 % (0 MB)
23 05:14:14.587957 progress 10 % (0 MB)
24 05:14:14.593620 progress 15 % (1 MB)
25 05:14:14.598797 progress 20 % (1 MB)
26 05:14:14.604348 progress 25 % (1 MB)
27 05:14:14.609514 progress 30 % (2 MB)
28 05:14:14.615110 progress 35 % (2 MB)
29 05:14:14.620302 progress 40 % (3 MB)
30 05:14:14.625875 progress 45 % (3 MB)
31 05:14:14.630981 progress 50 % (3 MB)
32 05:14:14.636605 progress 55 % (4 MB)
33 05:14:14.641722 progress 60 % (4 MB)
34 05:14:14.647205 progress 65 % (5 MB)
35 05:14:14.652299 progress 70 % (5 MB)
36 05:14:14.657794 progress 75 % (5 MB)
37 05:14:14.662987 progress 80 % (6 MB)
38 05:14:14.668537 progress 85 % (6 MB)
39 05:14:14.673618 progress 90 % (7 MB)
40 05:14:14.679074 progress 95 % (7 MB)
41 05:14:14.683826 progress 100 % (7 MB)
42 05:14:14.684507 7 MB downloaded in 0.15 s (51.78 MB/s)
43 05:14:14.685086 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:14:14.686033 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:14:14.686353 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:14:14.686643 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:14:14.687150 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/kernel/Image
49 05:14:14.687414 saving as /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/kernel/Image
50 05:14:14.687635 total size: 45308416 (43 MB)
51 05:14:14.687854 No compression specified
52 05:14:14.728521 progress 0 % (0 MB)
53 05:14:14.758390 progress 5 % (2 MB)
54 05:14:14.788569 progress 10 % (4 MB)
55 05:14:14.817563 progress 15 % (6 MB)
56 05:14:14.846082 progress 20 % (8 MB)
57 05:14:14.874884 progress 25 % (10 MB)
58 05:14:14.902548 progress 30 % (12 MB)
59 05:14:14.930641 progress 35 % (15 MB)
60 05:14:14.959202 progress 40 % (17 MB)
61 05:14:14.986932 progress 45 % (19 MB)
62 05:14:15.014926 progress 50 % (21 MB)
63 05:14:15.042974 progress 55 % (23 MB)
64 05:14:15.071143 progress 60 % (25 MB)
65 05:14:15.098721 progress 65 % (28 MB)
66 05:14:15.126675 progress 70 % (30 MB)
67 05:14:15.155230 progress 75 % (32 MB)
68 05:14:15.183122 progress 80 % (34 MB)
69 05:14:15.211315 progress 85 % (36 MB)
70 05:14:15.239381 progress 90 % (38 MB)
71 05:14:15.267199 progress 95 % (41 MB)
72 05:14:15.294715 progress 100 % (43 MB)
73 05:14:15.295403 43 MB downloaded in 0.61 s (71.10 MB/s)
74 05:14:15.295882 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:14:15.296729 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:14:15.297006 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:14:15.297270 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:14:15.297722 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 05:14:15.297993 saving as /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 05:14:15.298200 total size: 53173 (0 MB)
82 05:14:15.298407 No compression specified
83 05:14:15.342239 progress 61 % (0 MB)
84 05:14:15.343089 progress 100 % (0 MB)
85 05:14:15.343616 0 MB downloaded in 0.05 s (1.12 MB/s)
86 05:14:15.344133 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:14:15.344953 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:14:15.345213 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:14:15.345471 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:14:15.345928 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/modules.tar.xz
92 05:14:15.346175 saving as /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/modules/modules.tar
93 05:14:15.346380 total size: 11496964 (10 MB)
94 05:14:15.346587 Using unxz to decompress xz
95 05:14:15.389507 progress 0 % (0 MB)
96 05:14:15.455657 progress 5 % (0 MB)
97 05:14:15.540097 progress 10 % (1 MB)
98 05:14:15.619686 progress 15 % (1 MB)
99 05:14:15.706021 progress 20 % (2 MB)
100 05:14:15.779628 progress 25 % (2 MB)
101 05:14:15.857623 progress 30 % (3 MB)
102 05:14:15.930713 progress 35 % (3 MB)
103 05:14:16.009601 progress 40 % (4 MB)
104 05:14:16.086223 progress 45 % (4 MB)
105 05:14:16.165520 progress 50 % (5 MB)
106 05:14:16.244210 progress 55 % (6 MB)
107 05:14:16.321731 progress 60 % (6 MB)
108 05:14:16.405813 progress 65 % (7 MB)
109 05:14:16.480389 progress 70 % (7 MB)
110 05:14:16.562970 progress 75 % (8 MB)
111 05:14:16.652742 progress 80 % (8 MB)
112 05:14:16.749209 progress 85 % (9 MB)
113 05:14:16.818868 progress 90 % (9 MB)
114 05:14:16.895850 progress 95 % (10 MB)
115 05:14:16.966409 progress 100 % (10 MB)
116 05:14:16.980113 10 MB downloaded in 1.63 s (6.71 MB/s)
117 05:14:16.981028 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:14:16.982640 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:14:16.983162 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 05:14:16.983677 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 05:14:16.984203 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:14:16.984708 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 05:14:16.985654 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh
125 05:14:16.986475 makedir: /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin
126 05:14:16.987100 makedir: /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/tests
127 05:14:16.987703 makedir: /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/results
128 05:14:16.988339 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-add-keys
129 05:14:16.989278 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-add-sources
130 05:14:16.990213 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-background-process-start
131 05:14:16.991178 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-background-process-stop
132 05:14:16.992163 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-common-functions
133 05:14:16.993066 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-echo-ipv4
134 05:14:16.993942 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-install-packages
135 05:14:16.994805 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-installed-packages
136 05:14:16.995661 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-os-build
137 05:14:16.996565 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-probe-channel
138 05:14:16.997428 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-probe-ip
139 05:14:16.998310 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-target-ip
140 05:14:16.999314 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-target-mac
141 05:14:17.000225 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-target-storage
142 05:14:17.001116 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-test-case
143 05:14:17.001986 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-test-event
144 05:14:17.002844 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-test-feedback
145 05:14:17.003697 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-test-raise
146 05:14:17.004590 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-test-reference
147 05:14:17.005452 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-test-runner
148 05:14:17.006331 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-test-set
149 05:14:17.007224 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-test-shell
150 05:14:17.008168 Updating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-install-packages (oe)
151 05:14:17.009114 Updating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/bin/lava-installed-packages (oe)
152 05:14:17.009913 Creating /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/environment
153 05:14:17.010601 LAVA metadata
154 05:14:17.011074 - LAVA_JOB_ID=681573
155 05:14:17.011495 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:14:17.012159 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 05:14:17.013907 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:14:17.014519 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 05:14:17.014947 skipped lava-vland-overlay
160 05:14:17.015464 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:14:17.016053 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 05:14:17.016541 skipped lava-multinode-overlay
163 05:14:17.017088 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:14:17.017645 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 05:14:17.018153 Loading test definitions
166 05:14:17.018742 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 05:14:17.019217 Using /lava-681573 at stage 0
168 05:14:17.020819 uuid=681573_1.5.2.4.1 testdef=None
169 05:14:17.021156 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:14:17.021448 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 05:14:17.023237 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:14:17.024054 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 05:14:17.026293 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:14:17.027132 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 05:14:17.030359 runner path: /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/0/tests/0_dmesg test_uuid 681573_1.5.2.4.1
178 05:14:17.031334 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:14:17.032447 Creating lava-test-runner.conf files
181 05:14:17.032652 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681573/lava-overlay-4y2swtsh/lava-681573/0 for stage 0
182 05:14:17.033021 - 0_dmesg
183 05:14:17.033376 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:14:17.033653 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 05:14:17.057167 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:14:17.057567 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:14:17.057827 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:14:17.058090 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:14:17.058352 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:14:18.031421 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:14:18.031862 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 05:14:18.032303 extracting modules file /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681573/extract-overlay-ramdisk-tuo3ntxc/ramdisk
193 05:14:19.399342 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 05:14:19.399818 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 05:14:19.400112 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681573/compress-overlay-yzcqk30i/overlay-1.5.2.5.tar.gz to ramdisk
196 05:14:19.400328 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681573/compress-overlay-yzcqk30i/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681573/extract-overlay-ramdisk-tuo3ntxc/ramdisk
197 05:14:19.433372 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:14:19.433834 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 05:14:19.434108 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 05:14:19.434336 Converting downloaded kernel to a uImage
201 05:14:19.434644 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/kernel/Image /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/kernel/uImage
202 05:14:19.895201 output: Image Name:
203 05:14:19.895609 output: Created: Sat Aug 31 05:14:19 2024
204 05:14:19.895836 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:14:19.896120 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
206 05:14:19.896345 output: Load Address: 01080000
207 05:14:19.896581 output: Entry Point: 01080000
208 05:14:19.896817 output:
209 05:14:19.897252 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 05:14:19.897545 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 05:14:19.897818 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 05:14:19.898120 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:14:19.898392 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 05:14:19.898662 Building ramdisk /var/lib/lava/dispatcher/tmp/681573/extract-overlay-ramdisk-tuo3ntxc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681573/extract-overlay-ramdisk-tuo3ntxc/ramdisk
215 05:14:22.329903 >> 179908 blocks
216 05:14:30.782442 Adding RAMdisk u-boot header.
217 05:14:30.783155 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681573/extract-overlay-ramdisk-tuo3ntxc/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681573/extract-overlay-ramdisk-tuo3ntxc/ramdisk.cpio.gz.uboot
218 05:14:31.113066 output: Image Name:
219 05:14:31.113461 output: Created: Sat Aug 31 05:14:30 2024
220 05:14:31.113669 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:14:31.113870 output: Data Size: 25882697 Bytes = 25276.07 KiB = 24.68 MiB
222 05:14:31.114069 output: Load Address: 00000000
223 05:14:31.114265 output: Entry Point: 00000000
224 05:14:31.114460 output:
225 05:14:31.115170 rename /var/lib/lava/dispatcher/tmp/681573/extract-overlay-ramdisk-tuo3ntxc/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/ramdisk/ramdisk.cpio.gz.uboot
226 05:14:31.115586 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 05:14:31.115866 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 05:14:31.116282 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 05:14:31.116752 No LXC device requested
230 05:14:31.117244 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:14:31.117741 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 05:14:31.118224 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:14:31.118629 Checking files for TFTP limit of 4294967296 bytes.
234 05:14:31.121272 end: 1 tftp-deploy (duration 00:00:17) [common]
235 05:14:31.121837 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:14:31.122348 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:14:31.122834 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:14:31.123325 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:14:31.123839 Using kernel file from prepare-kernel: 681573/tftp-deploy-4toignji/kernel/uImage
240 05:14:31.124496 substitutions:
241 05:14:31.124908 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:14:31.125305 - {DTB_ADDR}: 0x01070000
243 05:14:31.125699 - {DTB}: 681573/tftp-deploy-4toignji/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 05:14:31.126093 - {INITRD}: 681573/tftp-deploy-4toignji/ramdisk/ramdisk.cpio.gz.uboot
245 05:14:31.126485 - {KERNEL_ADDR}: 0x01080000
246 05:14:31.126872 - {KERNEL}: 681573/tftp-deploy-4toignji/kernel/uImage
247 05:14:31.127260 - {LAVA_MAC}: None
248 05:14:31.127683 - {PRESEED_CONFIG}: None
249 05:14:31.128100 - {PRESEED_LOCAL}: None
250 05:14:31.128489 - {RAMDISK_ADDR}: 0x08000000
251 05:14:31.128872 - {RAMDISK}: 681573/tftp-deploy-4toignji/ramdisk/ramdisk.cpio.gz.uboot
252 05:14:31.129260 - {ROOT_PART}: None
253 05:14:31.129644 - {ROOT}: None
254 05:14:31.130026 - {SERVER_IP}: 192.168.6.2
255 05:14:31.130414 - {TEE_ADDR}: 0x83000000
256 05:14:31.130800 - {TEE}: None
257 05:14:31.131183 Parsed boot commands:
258 05:14:31.131554 - setenv autoload no
259 05:14:31.131938 - setenv initrd_high 0xffffffff
260 05:14:31.132349 - setenv fdt_high 0xffffffff
261 05:14:31.132733 - dhcp
262 05:14:31.133114 - setenv serverip 192.168.6.2
263 05:14:31.133496 - tftpboot 0x01080000 681573/tftp-deploy-4toignji/kernel/uImage
264 05:14:31.133878 - tftpboot 0x08000000 681573/tftp-deploy-4toignji/ramdisk/ramdisk.cpio.gz.uboot
265 05:14:31.134260 - tftpboot 0x01070000 681573/tftp-deploy-4toignji/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 05:14:31.134641 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:14:31.135030 - bootm 0x01080000 0x08000000 0x01070000
268 05:14:31.135519 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:14:31.136999 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:14:31.137437 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 05:14:31.152204 Setting prompt string to ['lava-test: # ']
273 05:14:31.153671 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:14:31.154261 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:14:31.154791 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:14:31.155294 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:14:31.156470 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 05:14:31.192792 >> OK - accepted request
279 05:14:31.194928 Returned 0 in 0 seconds
280 05:14:31.296062 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:14:31.297685 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:14:31.298237 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:14:31.298734 Setting prompt string to ['Hit any key to stop autoboot']
285 05:14:31.299174 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:14:31.300765 Trying 192.168.56.21...
287 05:14:31.301240 Connected to conserv1.
288 05:14:31.301657 Escape character is '^]'.
289 05:14:31.302073
290 05:14:31.302494 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 05:14:31.302907
292 05:14:38.823148 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 05:14:38.823808 bl2_stage_init 0x01
294 05:14:38.824332 bl2_stage_init 0x81
295 05:14:38.828756 hw id: 0x0000 - pwm id 0x01
296 05:14:38.829271 bl2_stage_init 0xc1
297 05:14:38.834469 bl2_stage_init 0x02
298 05:14:38.834969
299 05:14:38.835413 L0:00000000
300 05:14:38.835844 L1:00000703
301 05:14:38.836314 L2:00008067
302 05:14:38.836728 L3:15000000
303 05:14:38.839895 S1:00000000
304 05:14:38.840380 B2:20282000
305 05:14:38.840804 B1:a0f83180
306 05:14:38.841217
307 05:14:38.841626 TE: 68877
308 05:14:38.842037
309 05:14:38.845426 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 05:14:38.845904
311 05:14:38.850978 Board ID = 1
312 05:14:38.851455 Set cpu clk to 24M
313 05:14:38.851874 Set clk81 to 24M
314 05:14:38.854646 Use GP1_pll as DSU clk.
315 05:14:38.855107 DSU clk: 1200 Mhz
316 05:14:38.860307 CPU clk: 1200 MHz
317 05:14:38.860788 Set clk81 to 166.6M
318 05:14:38.865988 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 05:14:38.866463 board id: 1
320 05:14:38.874400 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:14:38.885849 fw parse done
322 05:14:38.891955 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:14:38.934820 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:14:38.945929 PIEI prepare done
325 05:14:38.946443 fastboot data load
326 05:14:38.946872 fastboot data verify
327 05:14:38.951490 verify result: 266
328 05:14:38.957103 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 05:14:38.957599 LPDDR4 probe
330 05:14:38.958022 ddr clk to 1584MHz
331 05:14:38.964900 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:14:39.001999
333 05:14:39.002549 dmc_version 0001
334 05:14:39.009106 Check phy result
335 05:14:39.015837 INFO : End of CA training
336 05:14:39.016380 INFO : End of initialization
337 05:14:39.021575 INFO : Training has run successfully!
338 05:14:39.022066 Check phy result
339 05:14:39.027075 INFO : End of initialization
340 05:14:39.027547 INFO : End of read enable training
341 05:14:39.032778 INFO : End of fine write leveling
342 05:14:39.038231 INFO : End of Write leveling coarse delay
343 05:14:39.038704 INFO : Training has run successfully!
344 05:14:39.039125 Check phy result
345 05:14:39.043801 INFO : End of initialization
346 05:14:39.044312 INFO : End of read dq deskew training
347 05:14:39.049492 INFO : End of MPR read delay center optimization
348 05:14:39.055002 INFO : End of write delay center optimization
349 05:14:39.060834 INFO : End of read delay center optimization
350 05:14:39.061719 INFO : End of max read latency training
351 05:14:39.066284 INFO : Training has run successfully!
352 05:14:39.067100 1D training succeed
353 05:14:39.074550 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:14:39.123699 Check phy result
355 05:14:39.124783 INFO : End of initialization
356 05:14:39.150228 INFO : End of 2D read delay Voltage center optimization
357 05:14:39.175281 INFO : End of 2D read delay Voltage center optimization
358 05:14:39.231433 INFO : End of 2D write delay Voltage center optimization
359 05:14:39.286096 INFO : End of 2D write delay Voltage center optimization
360 05:14:39.291644 INFO : Training has run successfully!
361 05:14:39.292503
362 05:14:39.293215 channel==0
363 05:14:39.297207 RxClkDly_Margin_A0==78 ps 8
364 05:14:39.298003 TxDqDly_Margin_A0==98 ps 10
365 05:14:39.302860 RxClkDly_Margin_A1==88 ps 9
366 05:14:39.303670 TxDqDly_Margin_A1==98 ps 10
367 05:14:39.304510 TrainedVREFDQ_A0==74
368 05:14:39.308370 TrainedVREFDQ_A1==75
369 05:14:39.309212 VrefDac_Margin_A0==24
370 05:14:39.309968 DeviceVref_Margin_A0==40
371 05:14:39.313937 VrefDac_Margin_A1==23
372 05:14:39.314747 DeviceVref_Margin_A1==39
373 05:14:39.315503
374 05:14:39.316393
375 05:14:39.319631 channel==1
376 05:14:39.320475 RxClkDly_Margin_A0==88 ps 9
377 05:14:39.321176 TxDqDly_Margin_A0==88 ps 9
378 05:14:39.325181 RxClkDly_Margin_A1==78 ps 8
379 05:14:39.325996 TxDqDly_Margin_A1==88 ps 9
380 05:14:39.330858 TrainedVREFDQ_A0==75
381 05:14:39.331665 TrainedVREFDQ_A1==75
382 05:14:39.332416 VrefDac_Margin_A0==22
383 05:14:39.336366 DeviceVref_Margin_A0==39
384 05:14:39.337103 VrefDac_Margin_A1==22
385 05:14:39.341961 DeviceVref_Margin_A1==39
386 05:14:39.342790
387 05:14:39.343580 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:14:39.344393
389 05:14:39.375653 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 05:14:39.376535 2D training succeed
391 05:14:39.381111 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:14:39.386777 auto size-- 65535DDR cs0 size: 2048MB
393 05:14:39.387291 DDR cs1 size: 2048MB
394 05:14:39.392296 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:14:39.392823 cs0 DataBus test pass
396 05:14:39.397981 cs1 DataBus test pass
397 05:14:39.398548 cs0 AddrBus test pass
398 05:14:39.399014 cs1 AddrBus test pass
399 05:14:39.399492
400 05:14:39.403567 100bdlr_step_size ps== 471
401 05:14:39.404146 result report
402 05:14:39.409131 boot times 0Enable ddr reg access
403 05:14:39.413477 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:14:39.427923 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 05:14:40.087113 bl2z: ptr: 05129330, size: 00001e40
406 05:14:40.096436 0.0;M3 CHK:0;cm4_sp_mode 0
407 05:14:40.096914 MVN_1=0x00000000
408 05:14:40.097317 MVN_2=0x00000000
409 05:14:40.107925 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 05:14:40.108409 OPS=0x04
411 05:14:40.108809 ring efuse init
412 05:14:40.113596 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 05:14:40.114032 [0.017354 Inits done]
414 05:14:40.114422 secure task start!
415 05:14:40.120557 high task start!
416 05:14:40.120975 low task start!
417 05:14:40.121361 run into bl31
418 05:14:40.129361 NOTICE: BL31: v1.3(release):4fc40b1
419 05:14:40.136431 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 05:14:40.136904 NOTICE: BL31: G12A normal boot!
421 05:14:40.152842 NOTICE: BL31: BL33 decompress pass
422 05:14:40.157987 ERROR: Error initializing runtime service opteed_fast
423 05:14:41.373405 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 05:14:41.373991 bl2_stage_init 0x01
425 05:14:41.374392 bl2_stage_init 0x81
426 05:14:41.378983 hw id: 0x0000 - pwm id 0x01
427 05:14:41.379429 bl2_stage_init 0xc1
428 05:14:41.384514 bl2_stage_init 0x02
429 05:14:41.384946
430 05:14:41.385342 L0:00000000
431 05:14:41.385723 L1:00000703
432 05:14:41.386105 L2:00008067
433 05:14:41.386484 L3:15000000
434 05:14:41.390132 S1:00000000
435 05:14:41.390560 B2:20282000
436 05:14:41.390946 B1:a0f83180
437 05:14:41.391323
438 05:14:41.391706 TE: 69346
439 05:14:41.392149
440 05:14:41.395738 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 05:14:41.396200
442 05:14:41.401359 Board ID = 1
443 05:14:41.401786 Set cpu clk to 24M
444 05:14:41.402169 Set clk81 to 24M
445 05:14:41.406990 Use GP1_pll as DSU clk.
446 05:14:41.407410 DSU clk: 1200 Mhz
447 05:14:41.407791 CPU clk: 1200 MHz
448 05:14:41.412511 Set clk81 to 166.6M
449 05:14:41.418104 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 05:14:41.418534 board id: 1
451 05:14:41.424577 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 05:14:41.436224 fw parse done
453 05:14:41.441408 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 05:14:41.484893 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 05:14:41.496431 PIEI prepare done
456 05:14:41.496856 fastboot data load
457 05:14:41.497245 fastboot data verify
458 05:14:41.502046 verify result: 266
459 05:14:41.507671 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 05:14:41.508159 LPDDR4 probe
461 05:14:41.508553 ddr clk to 1584MHz
462 05:14:42.875543 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 05:14:42.876204 bl2_stage_init 0x01
464 05:14:42.876639 bl2_stage_init 0x81
465 05:14:42.881154 hw id: 0x0000 - pwm id 0x01
466 05:14:42.881659 bl2_stage_init 0xc1
467 05:14:42.886756 bl2_stage_init 0x02
468 05:14:42.887237
469 05:14:42.887657 L0:00000000
470 05:14:42.888099 L1:00000703
471 05:14:42.888510 L2:00008067
472 05:14:42.888909 L3:15000000
473 05:14:42.892345 S1:00000000
474 05:14:42.892825 B2:20282000
475 05:14:42.893236 B1:a0f83180
476 05:14:42.893633
477 05:14:42.894027 TE: 71578
478 05:14:42.894422
479 05:14:42.897924 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 05:14:42.898404
481 05:14:42.903544 Board ID = 1
482 05:14:42.904038 Set cpu clk to 24M
483 05:14:42.904455 Set clk81 to 24M
484 05:14:42.909112 Use GP1_pll as DSU clk.
485 05:14:42.909583 DSU clk: 1200 Mhz
486 05:14:42.909988 CPU clk: 1200 MHz
487 05:14:42.914708 Set clk81 to 166.6M
488 05:14:42.920308 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 05:14:42.920780 board id: 1
490 05:14:42.926850 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 05:14:42.938453 fw parse done
492 05:14:42.943440 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 05:14:42.987393 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 05:14:42.998659 PIEI prepare done
495 05:14:42.999135 fastboot data load
496 05:14:42.999547 fastboot data verify
497 05:14:43.004275 verify result: 266
498 05:14:43.009847 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 05:14:43.010320 LPDDR4 probe
500 05:14:43.010736 ddr clk to 1584MHz
501 05:14:43.017817 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 05:14:43.055522
503 05:14:43.056036 dmc_version 0001
504 05:14:43.062588 Check phy result
505 05:14:43.068571 INFO : End of CA training
506 05:14:43.069055 INFO : End of initialization
507 05:14:43.074139 INFO : Training has run successfully!
508 05:14:43.074613 Check phy result
509 05:14:43.079767 INFO : End of initialization
510 05:14:43.080281 INFO : End of read enable training
511 05:14:43.083142 INFO : End of fine write leveling
512 05:14:43.088695 INFO : End of Write leveling coarse delay
513 05:14:43.094585 INFO : Training has run successfully!
514 05:14:43.095056 Check phy result
515 05:14:43.095460 INFO : End of initialization
516 05:14:43.099878 INFO : End of read dq deskew training
517 05:14:43.114130 INFO : End of MPR read delay center optimization
518 05:14:43.114611 INFO : End of write delay center optimization
519 05:14:43.115030 INFO : End of read delay center optimization
520 05:14:43.115954 INFO : End of max read latency training
521 05:14:43.121437 INFO : Training has run successfully!
522 05:14:43.121916 1D training succeed
523 05:14:43.128241 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 05:14:43.176468 Check phy result
525 05:14:43.176937 INFO : End of initialization
526 05:14:43.203783 INFO : End of 2D read delay Voltage center optimization
527 05:14:43.227967 INFO : End of 2D read delay Voltage center optimization
528 05:14:43.284627 INFO : End of 2D write delay Voltage center optimization
529 05:14:43.338572 INFO : End of 2D write delay Voltage center optimization
530 05:14:43.344177 INFO : Training has run successfully!
531 05:14:43.344648
532 05:14:43.345062 channel==0
533 05:14:43.349751 RxClkDly_Margin_A0==78 ps 8
534 05:14:43.350238 TxDqDly_Margin_A0==98 ps 10
535 05:14:43.355425 RxClkDly_Margin_A1==88 ps 9
536 05:14:43.355894 TxDqDly_Margin_A1==98 ps 10
537 05:14:43.356346 TrainedVREFDQ_A0==74
538 05:14:43.360939 TrainedVREFDQ_A1==74
539 05:14:43.361411 VrefDac_Margin_A0==25
540 05:14:43.361819 DeviceVref_Margin_A0==40
541 05:14:43.366536 VrefDac_Margin_A1==23
542 05:14:43.367006 DeviceVref_Margin_A1==40
543 05:14:43.367416
544 05:14:43.367820
545 05:14:43.372185 channel==1
546 05:14:43.372655 RxClkDly_Margin_A0==88 ps 9
547 05:14:43.373065 TxDqDly_Margin_A0==98 ps 10
548 05:14:43.377753 RxClkDly_Margin_A1==88 ps 9
549 05:14:43.378226 TxDqDly_Margin_A1==98 ps 10
550 05:14:43.383423 TrainedVREFDQ_A0==78
551 05:14:43.383891 TrainedVREFDQ_A1==78
552 05:14:43.384339 VrefDac_Margin_A0==22
553 05:14:43.388933 DeviceVref_Margin_A0==36
554 05:14:43.389404 VrefDac_Margin_A1==22
555 05:14:43.394546 DeviceVref_Margin_A1==36
556 05:14:43.395022
557 05:14:43.395434 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 05:14:43.395836
559 05:14:43.428104 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
560 05:14:43.428616 2D training succeed
561 05:14:43.433741 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 05:14:43.439418 auto size-- 65535DDR cs0 size: 2048MB
563 05:14:43.439893 DDR cs1 size: 2048MB
564 05:14:43.444960 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 05:14:43.445432 cs0 DataBus test pass
566 05:14:43.450560 cs1 DataBus test pass
567 05:14:43.451037 cs0 AddrBus test pass
568 05:14:43.451444 cs1 AddrBus test pass
569 05:14:43.451841
570 05:14:43.456219 100bdlr_step_size ps== 478
571 05:14:43.456729 result report
572 05:14:43.461758 boot times 0Enable ddr reg access
573 05:14:43.467083 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 05:14:43.480904 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 05:14:44.139548 bl2z: ptr: 05129330, size: 00001e40
576 05:14:44.148006 0.0;M3 CHK:0;cm4_sp_mode 0
577 05:14:44.148507 MVN_1=0x00000000
578 05:14:44.148915 MVN_2=0x00000000
579 05:14:44.159325 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 05:14:44.159803 OPS=0x04
581 05:14:44.160249 ring efuse init
582 05:14:44.162363 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 05:14:44.168439 [0.017354 Inits done]
584 05:14:44.168906 secure task start!
585 05:14:44.169310 high task start!
586 05:14:44.169706 low task start!
587 05:14:44.172191 run into bl31
588 05:14:44.187485 NOTICE: BL31: v1.3(release):4fc40b1
589 05:14:44.190575 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 05:14:44.191062 NOTICE: BL31: G12A normal boot!
591 05:14:44.204716 NOTICE: BL31: BL33 decompress pass
592 05:14:44.210513 ERROR: Error initializing runtime service opteed_fast
593 05:14:45.423783 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 05:14:45.424391 bl2_stage_init 0x01
595 05:14:45.424816 bl2_stage_init 0x81
596 05:14:45.429494 hw id: 0x0000 - pwm id 0x01
597 05:14:45.429979 bl2_stage_init 0xc1
598 05:14:45.434910 bl2_stage_init 0x02
599 05:14:45.435381
600 05:14:45.435797 L0:00000000
601 05:14:45.436231 L1:00000703
602 05:14:45.436634 L2:00008067
603 05:14:45.437029 L3:15000000
604 05:14:45.440536 S1:00000000
605 05:14:45.441009 B2:20282000
606 05:14:45.441419 B1:a0f83180
607 05:14:45.441817
608 05:14:45.442217 TE: 69601
609 05:14:45.442612
610 05:14:45.446248 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 05:14:45.446724
612 05:14:45.451853 Board ID = 1
613 05:14:45.452363 Set cpu clk to 24M
614 05:14:45.452777 Set clk81 to 24M
615 05:14:45.457345 Use GP1_pll as DSU clk.
616 05:14:45.457818 DSU clk: 1200 Mhz
617 05:14:45.458228 CPU clk: 1200 MHz
618 05:14:45.462909 Set clk81 to 166.6M
619 05:14:45.468565 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 05:14:45.469040 board id: 1
621 05:14:45.475939 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 05:14:45.486431 fw parse done
623 05:14:45.492470 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 05:14:45.534909 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 05:14:45.545845 PIEI prepare done
626 05:14:45.546313 fastboot data load
627 05:14:45.546729 fastboot data verify
628 05:14:45.551473 verify result: 266
629 05:14:45.557044 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 05:14:45.557520 LPDDR4 probe
631 05:14:45.557927 ddr clk to 1584MHz
632 05:14:45.565019 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 05:14:45.602238
634 05:14:45.602718 dmc_version 0001
635 05:14:45.608926 Check phy result
636 05:14:45.614855 INFO : End of CA training
637 05:14:45.615323 INFO : End of initialization
638 05:14:45.620446 INFO : Training has run successfully!
639 05:14:45.620991 Check phy result
640 05:14:45.626094 INFO : End of initialization
641 05:14:45.626574 INFO : End of read enable training
642 05:14:45.631736 INFO : End of fine write leveling
643 05:14:45.637264 INFO : End of Write leveling coarse delay
644 05:14:45.637738 INFO : Training has run successfully!
645 05:14:45.638147 Check phy result
646 05:14:45.642860 INFO : End of initialization
647 05:14:45.643333 INFO : End of read dq deskew training
648 05:14:45.648459 INFO : End of MPR read delay center optimization
649 05:14:45.654034 INFO : End of write delay center optimization
650 05:14:45.659710 INFO : End of read delay center optimization
651 05:14:45.660207 INFO : End of max read latency training
652 05:14:45.665227 INFO : Training has run successfully!
653 05:14:45.665696 1D training succeed
654 05:14:45.674423 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 05:14:45.722006 Check phy result
656 05:14:45.722482 INFO : End of initialization
657 05:14:45.744398 INFO : End of 2D read delay Voltage center optimization
658 05:14:45.763558 INFO : End of 2D read delay Voltage center optimization
659 05:14:45.815399 INFO : End of 2D write delay Voltage center optimization
660 05:14:45.864612 INFO : End of 2D write delay Voltage center optimization
661 05:14:45.870187 INFO : Training has run successfully!
662 05:14:45.870664
663 05:14:45.871070 channel==0
664 05:14:45.875796 RxClkDly_Margin_A0==78 ps 8
665 05:14:45.876310 TxDqDly_Margin_A0==98 ps 10
666 05:14:45.881375 RxClkDly_Margin_A1==88 ps 9
667 05:14:45.881847 TxDqDly_Margin_A1==88 ps 9
668 05:14:45.882262 TrainedVREFDQ_A0==74
669 05:14:45.886998 TrainedVREFDQ_A1==75
670 05:14:45.887469 VrefDac_Margin_A0==25
671 05:14:45.887877 DeviceVref_Margin_A0==40
672 05:14:45.892572 VrefDac_Margin_A1==23
673 05:14:45.893038 DeviceVref_Margin_A1==39
674 05:14:45.893443
675 05:14:45.893847
676 05:14:45.894250 channel==1
677 05:14:45.898225 RxClkDly_Margin_A0==88 ps 9
678 05:14:45.898797 TxDqDly_Margin_A0==98 ps 10
679 05:14:45.903715 RxClkDly_Margin_A1==88 ps 9
680 05:14:45.904243 TxDqDly_Margin_A1==88 ps 9
681 05:14:45.909295 TrainedVREFDQ_A0==78
682 05:14:45.909803 TrainedVREFDQ_A1==75
683 05:14:45.910264 VrefDac_Margin_A0==22
684 05:14:45.914880 DeviceVref_Margin_A0==36
685 05:14:45.915361 VrefDac_Margin_A1==22
686 05:14:45.920472 DeviceVref_Margin_A1==39
687 05:14:45.920952
688 05:14:45.921410 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 05:14:45.921860
690 05:14:45.954097 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
691 05:14:45.954631 2D training succeed
692 05:14:45.959710 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 05:14:45.965290 auto size-- 65535DDR cs0 size: 2048MB
694 05:14:45.965798 DDR cs1 size: 2048MB
695 05:14:45.970876 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 05:14:45.971360 cs0 DataBus test pass
697 05:14:45.976482 cs1 DataBus test pass
698 05:14:45.976972 cs0 AddrBus test pass
699 05:14:45.977425 cs1 AddrBus test pass
700 05:14:45.977870
701 05:14:45.982062 100bdlr_step_size ps== 478
702 05:14:45.982560 result report
703 05:14:45.987709 boot times 0Enable ddr reg access
704 05:14:45.992868 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 05:14:46.006737 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 05:14:46.661596 bl2z: ptr: 05129330, size: 00001e40
707 05:14:46.668185 0.0;M3 CHK:0;cm4_sp_mode 0
708 05:14:46.668767 MVN_1=0x00000000
709 05:14:46.669208 MVN_2=0x00000000
710 05:14:46.679747 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 05:14:46.680377 OPS=0x04
712 05:14:46.680817 ring efuse init
713 05:14:46.685266 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 05:14:46.685768 [0.017319 Inits done]
715 05:14:46.686202 secure task start!
716 05:14:46.692750 high task start!
717 05:14:46.693224 low task start!
718 05:14:46.693649 run into bl31
719 05:14:46.701379 NOTICE: BL31: v1.3(release):4fc40b1
720 05:14:46.709167 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 05:14:46.709644 NOTICE: BL31: G12A normal boot!
722 05:14:46.724716 NOTICE: BL31: BL33 decompress pass
723 05:14:46.730506 ERROR: Error initializing runtime service opteed_fast
724 05:14:47.526008
725 05:14:47.526667
726 05:14:47.531362 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 05:14:47.531872
728 05:14:47.534898 Model: Libre Computer AML-S905D3-CC Solitude
729 05:14:47.681950 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 05:14:47.697250 DRAM: 2 GiB (effective 3.8 GiB)
731 05:14:47.798122 Core: 406 devices, 33 uclasses, devicetree: separate
732 05:14:47.804043 WDT: Not starting watchdog@f0d0
733 05:14:47.829065 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 05:14:47.841330 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 05:14:47.846313 ** Bad device specification mmc 0 **
736 05:14:47.856344 Card did not respond to voltage select! : -110
737 05:14:47.864020 ** Bad device specification mmc 0 **
738 05:14:47.864522 Couldn't find partition mmc 0
739 05:14:47.872347 Card did not respond to voltage select! : -110
740 05:14:47.877869 ** Bad device specification mmc 0 **
741 05:14:47.878365 Couldn't find partition mmc 0
742 05:14:47.882938 Error: could not access storage.
743 05:14:48.179200 Net: eth0: ethernet@ff3f0000
744 05:14:48.179936 starting USB...
745 05:14:48.424110 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 05:14:48.424721 Starting the controller
747 05:14:48.430610 USB XHCI 1.10
748 05:14:49.985395 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 05:14:49.993041 scanning usb for storage devices... 0 Storage Device(s) found
751 05:14:50.044740 Hit any key to stop autoboot: 1
752 05:14:50.045667 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 05:14:50.046391 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 05:14:50.046970 Setting prompt string to ['=>']
755 05:14:50.047518 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 05:14:50.059257 0
757 05:14:50.060276 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 05:14:50.161598 => setenv autoload no
760 05:14:50.162373 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 05:14:50.167885 setenv autoload no
763 05:14:50.269541 => setenv initrd_high 0xffffffff
764 05:14:50.270267 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 05:14:50.273607 setenv initrd_high 0xffffffff
767 05:14:50.375236 => setenv fdt_high 0xffffffff
768 05:14:50.376014 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 05:14:50.379420 setenv fdt_high 0xffffffff
771 05:14:50.481023 => dhcp
772 05:14:50.481769 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 05:14:50.485262 dhcp
774 05:14:50.991098 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 05:14:50.991719 Speed: 1000, full duplex
776 05:14:50.992195 BOOTP broadcast 1
777 05:14:51.239659 BOOTP broadcast 2
778 05:14:51.740386 BOOTP broadcast 3
779 05:14:52.741386 BOOTP broadcast 4
780 05:14:54.743052 BOOTP broadcast 5
781 05:14:54.757336 DHCP client bound to address 192.168.6.12 (3766 ms)
783 05:14:54.859132 => setenv serverip 192.168.6.2
784 05:14:54.860162 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
785 05:14:54.863545 setenv serverip 192.168.6.2
787 05:14:54.965280 => tftpboot 0x01080000 681573/tftp-deploy-4toignji/kernel/uImage
788 05:14:54.966027 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
789 05:14:54.972575 tftpboot 0x01080000 681573/tftp-deploy-4toignji/kernel/uImage
790 05:14:54.972985 Speed: 1000, full duplex
791 05:14:54.973231 Using ethernet@ff3f0000 device
792 05:14:54.978202 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 05:14:54.983685 Filename '681573/tftp-deploy-4toignji/kernel/uImage'.
794 05:14:54.987655 Load address: 0x1080000
795 05:14:58.082392 Loading: *################################################## 43.2 MiB
796 05:14:58.082990 13.9 MiB/s
797 05:14:58.083422 done
798 05:14:58.085957 Bytes transferred = 45308480 (2b35a40 hex)
800 05:14:58.187574 => tftpboot 0x08000000 681573/tftp-deploy-4toignji/ramdisk/ramdisk.cpio.gz.uboot
801 05:14:58.188385 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
802 05:14:58.195061 tftpboot 0x08000000 681573/tftp-deploy-4toignji/ramdisk/ramdisk.cpio.gz.uboot
803 05:14:58.195554 Speed: 1000, full duplex
804 05:14:58.195950 Using ethernet@ff3f0000 device
805 05:14:58.200581 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
806 05:14:58.210305 Filename '681573/tftp-deploy-4toignji/ramdisk/ramdisk.cpio.gz.uboot'.
807 05:14:58.210809 Load address: 0x8000000
808 05:14:59.908876 Loading: *################################################# UDP wrong checksum 00000005 00007d36
809 05:15:04.908887 T UDP wrong checksum 00000005 00007d36
810 05:15:14.909271 T UDP wrong checksum 00000005 00007d36
811 05:15:27.557274 T T T UDP wrong checksum 000000ff 00005f50
812 05:15:27.584734 UDP wrong checksum 000000ff 0000ee42
813 05:15:34.912360 T UDP wrong checksum 00000005 00007d36
814 05:15:37.499316 T UDP wrong checksum 000000ff 0000b8a3
815 05:15:37.553392 UDP wrong checksum 000000ff 00005096
816 05:15:42.106999 T UDP wrong checksum 000000ff 0000b43a
817 05:15:42.128050 UDP wrong checksum 000000ff 00004e2d
818 05:15:54.919824 T T
819 05:15:54.920485 Retry count exceeded; starting again
821 05:15:54.921945 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
824 05:15:54.923818 end: 2.4 uboot-commands (duration 00:01:24) [common]
826 05:15:54.925416 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
828 05:15:54.926437 end: 2 uboot-action (duration 00:01:24) [common]
830 05:15:54.927925 Cleaning after the job
831 05:15:54.928501 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/ramdisk
832 05:15:54.929688 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/kernel
833 05:15:54.975952 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/dtb
834 05:15:54.976844 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681573/tftp-deploy-4toignji/modules
835 05:15:54.998421 start: 4.1 power-off (timeout 00:00:30) [common]
836 05:15:54.999085 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
837 05:15:55.032669 >> OK - accepted request
838 05:15:55.034724 Returned 0 in 0 seconds
839 05:15:55.135454 end: 4.1 power-off (duration 00:00:00) [common]
841 05:15:55.136447 start: 4.2 read-feedback (timeout 00:10:00) [common]
842 05:15:55.137106 Listened to connection for namespace 'common' for up to 1s
843 05:15:56.138317 Finalising connection for namespace 'common'
844 05:15:56.138852 Disconnecting from shell: Finalise
845 05:15:56.139174 =>
846 05:15:56.239876 end: 4.2 read-feedback (duration 00:00:01) [common]
847 05:15:56.240405 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681573
848 05:15:56.518798 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681573
849 05:15:56.519441 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.